1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cadence CDNSP DRD Driver. 4 * 5 * Copyright (C) 2020 Cadence. 6 * 7 * Author: Pawel Laszczak <pawell@cadence.com> 8 * 9 * Code based on Linux XHCI driver. 10 * Origin: Copyright (C) 2008 Intel Corp. 11 */ 12 13 #include <linux/dma-mapping.h> 14 #include <linux/dmapool.h> 15 #include <linux/slab.h> 16 #include <linux/usb.h> 17 18 #include "cdnsp-gadget.h" 19 #include "cdnsp-trace.h" 20 21 static void cdnsp_free_stream_info(struct cdnsp_device *pdev, 22 struct cdnsp_ep *pep); 23 /* 24 * Allocates a generic ring segment from the ring pool, sets the dma address, 25 * initializes the segment to zero, and sets the private next pointer to NULL. 26 * 27 * "All components of all Command and Transfer TRBs shall be initialized to '0'" 28 */ 29 static struct cdnsp_segment *cdnsp_segment_alloc(struct cdnsp_device *pdev, 30 unsigned int cycle_state, 31 unsigned int max_packet, 32 gfp_t flags) 33 { 34 struct cdnsp_segment *seg; 35 dma_addr_t dma; 36 int i; 37 38 seg = kzalloc_obj(*seg, flags); 39 if (!seg) 40 return NULL; 41 42 seg->trbs = dma_pool_zalloc(pdev->segment_pool, flags, &dma); 43 if (!seg->trbs) { 44 kfree(seg); 45 return NULL; 46 } 47 48 if (max_packet) { 49 seg->bounce_buf = kzalloc(max_packet, flags | GFP_DMA); 50 if (!seg->bounce_buf) 51 goto free_dma; 52 } 53 54 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs. */ 55 if (cycle_state == 0) { 56 for (i = 0; i < TRBS_PER_SEGMENT; i++) 57 seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE); 58 } 59 seg->dma = dma; 60 seg->next = NULL; 61 62 return seg; 63 64 free_dma: 65 dma_pool_free(pdev->segment_pool, seg->trbs, dma); 66 kfree(seg); 67 68 return NULL; 69 } 70 71 static void cdnsp_segment_free(struct cdnsp_device *pdev, 72 struct cdnsp_segment *seg) 73 { 74 if (seg->trbs) 75 dma_pool_free(pdev->segment_pool, seg->trbs, seg->dma); 76 77 kfree(seg->bounce_buf); 78 kfree(seg); 79 } 80 81 static void cdnsp_free_segments_for_ring(struct cdnsp_device *pdev, 82 struct cdnsp_segment *first) 83 { 84 struct cdnsp_segment *seg; 85 86 seg = first->next; 87 88 while (seg != first) { 89 struct cdnsp_segment *next = seg->next; 90 91 cdnsp_segment_free(pdev, seg); 92 seg = next; 93 } 94 95 cdnsp_segment_free(pdev, first); 96 } 97 98 /* 99 * Make the prev segment point to the next segment. 100 * 101 * Change the last TRB in the prev segment to be a Link TRB which points to the 102 * DMA address of the next segment. The caller needs to set any Link TRB 103 * related flags, such as End TRB, Toggle Cycle, and no snoop. 104 */ 105 static void cdnsp_link_segments(struct cdnsp_device *pdev, 106 struct cdnsp_segment *prev, 107 struct cdnsp_segment *next, 108 enum cdnsp_ring_type type) 109 { 110 struct cdnsp_link_trb *link; 111 u32 val; 112 113 if (!prev || !next) 114 return; 115 116 prev->next = next; 117 if (type != TYPE_EVENT) { 118 link = &prev->trbs[TRBS_PER_SEGMENT - 1].link; 119 link->segment_ptr = cpu_to_le64(next->dma); 120 121 /* 122 * Set the last TRB in the segment to have a TRB type ID 123 * of Link TRB 124 */ 125 val = le32_to_cpu(link->control); 126 val &= ~TRB_TYPE_BITMASK; 127 val |= TRB_TYPE(TRB_LINK); 128 link->control = cpu_to_le32(val); 129 } 130 } 131 132 /* 133 * Link the ring to the new segments. 134 * Set Toggle Cycle for the new ring if needed. 135 */ 136 static void cdnsp_link_rings(struct cdnsp_device *pdev, 137 struct cdnsp_ring *ring, 138 struct cdnsp_segment *first, 139 struct cdnsp_segment *last, 140 unsigned int num_segs) 141 { 142 struct cdnsp_segment *next; 143 144 if (!ring || !first || !last) 145 return; 146 147 next = ring->enq_seg->next; 148 cdnsp_link_segments(pdev, ring->enq_seg, first, ring->type); 149 cdnsp_link_segments(pdev, last, next, ring->type); 150 ring->num_segs += num_segs; 151 ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs; 152 153 if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) { 154 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= 155 ~cpu_to_le32(LINK_TOGGLE); 156 last->trbs[TRBS_PER_SEGMENT - 1].link.control |= 157 cpu_to_le32(LINK_TOGGLE); 158 ring->last_seg = last; 159 } 160 } 161 162 /* 163 * We need a radix tree for mapping physical addresses of TRBs to which stream 164 * ID they belong to. We need to do this because the device controller won't 165 * tell us which stream ring the TRB came from. We could store the stream ID 166 * in an event data TRB, but that doesn't help us for the cancellation case, 167 * since the endpoint may stop before it reaches that event data TRB. 168 * 169 * The radix tree maps the upper portion of the TRB DMA address to a ring 170 * segment that has the same upper portion of DMA addresses. For example, 171 * say I have segments of size 1KB, that are always 1KB aligned. A segment may 172 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the 173 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to 174 * pass the radix tree a key to get the right stream ID: 175 * 176 * 0x10c90fff >> 10 = 0x43243 177 * 0x10c912c0 >> 10 = 0x43244 178 * 0x10c91400 >> 10 = 0x43245 179 * 180 * Obviously, only those TRBs with DMA addresses that are within the segment 181 * will make the radix tree return the stream ID for that ring. 182 * 183 * Caveats for the radix tree: 184 * 185 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an 186 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be 187 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the 188 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit 189 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit 190 * extended systems (where the DMA address can be bigger than 32-bits), 191 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that. 192 */ 193 static int cdnsp_insert_segment_mapping(struct radix_tree_root *trb_address_map, 194 struct cdnsp_ring *ring, 195 struct cdnsp_segment *seg, 196 gfp_t mem_flags) 197 { 198 unsigned long key; 199 int ret; 200 201 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); 202 203 /* Skip any segments that were already added. */ 204 if (radix_tree_lookup(trb_address_map, key)) 205 return 0; 206 207 ret = radix_tree_maybe_preload(mem_flags); 208 if (ret) 209 return ret; 210 211 ret = radix_tree_insert(trb_address_map, key, ring); 212 radix_tree_preload_end(); 213 214 return ret; 215 } 216 217 static void cdnsp_remove_segment_mapping(struct radix_tree_root *trb_address_map, 218 struct cdnsp_segment *seg) 219 { 220 unsigned long key; 221 222 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); 223 if (radix_tree_lookup(trb_address_map, key)) 224 radix_tree_delete(trb_address_map, key); 225 } 226 227 static int cdnsp_update_stream_segment_mapping(struct radix_tree_root *trb_address_map, 228 struct cdnsp_ring *ring, 229 struct cdnsp_segment *first_seg, 230 struct cdnsp_segment *last_seg, 231 gfp_t mem_flags) 232 { 233 struct cdnsp_segment *failed_seg; 234 struct cdnsp_segment *seg; 235 int ret; 236 237 seg = first_seg; 238 do { 239 ret = cdnsp_insert_segment_mapping(trb_address_map, ring, seg, 240 mem_flags); 241 if (ret) 242 goto remove_streams; 243 if (seg == last_seg) 244 return 0; 245 seg = seg->next; 246 } while (seg != first_seg); 247 248 return 0; 249 250 remove_streams: 251 failed_seg = seg; 252 seg = first_seg; 253 do { 254 cdnsp_remove_segment_mapping(trb_address_map, seg); 255 if (seg == failed_seg) 256 return ret; 257 seg = seg->next; 258 } while (seg != first_seg); 259 260 return ret; 261 } 262 263 static void cdnsp_remove_stream_mapping(struct cdnsp_ring *ring) 264 { 265 struct cdnsp_segment *seg; 266 267 seg = ring->first_seg; 268 do { 269 cdnsp_remove_segment_mapping(ring->trb_address_map, seg); 270 seg = seg->next; 271 } while (seg != ring->first_seg); 272 } 273 274 static int cdnsp_update_stream_mapping(struct cdnsp_ring *ring) 275 { 276 return cdnsp_update_stream_segment_mapping(ring->trb_address_map, ring, 277 ring->first_seg, ring->last_seg, GFP_ATOMIC); 278 } 279 280 static void cdnsp_ring_free(struct cdnsp_device *pdev, struct cdnsp_ring *ring) 281 { 282 if (!ring) 283 return; 284 285 trace_cdnsp_ring_free(ring); 286 287 if (ring->first_seg) { 288 if (ring->type == TYPE_STREAM) 289 cdnsp_remove_stream_mapping(ring); 290 291 cdnsp_free_segments_for_ring(pdev, ring->first_seg); 292 } 293 294 kfree(ring); 295 } 296 297 void cdnsp_initialize_ring_info(struct cdnsp_ring *ring) 298 { 299 ring->enqueue = ring->first_seg->trbs; 300 ring->enq_seg = ring->first_seg; 301 ring->dequeue = ring->enqueue; 302 ring->deq_seg = ring->first_seg; 303 304 /* 305 * The ring is initialized to 0. The producer must write 1 to the cycle 306 * bit to handover ownership of the TRB, so PCS = 1. The consumer must 307 * compare CCS to the cycle bit to check ownership, so CCS = 1. 308 * 309 * New rings are initialized with cycle state equal to 1; if we are 310 * handling ring expansion, set the cycle state equal to the old ring. 311 */ 312 ring->cycle_state = 1; 313 314 /* 315 * Each segment has a link TRB, and leave an extra TRB for SW 316 * accounting purpose 317 */ 318 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; 319 } 320 321 /* Allocate segments and link them for a ring. */ 322 static int cdnsp_alloc_segments_for_ring(struct cdnsp_device *pdev, 323 struct cdnsp_segment **first, 324 struct cdnsp_segment **last, 325 unsigned int num_segs, 326 unsigned int cycle_state, 327 enum cdnsp_ring_type type, 328 unsigned int max_packet, 329 gfp_t flags) 330 { 331 struct cdnsp_segment *prev; 332 333 /* Allocate first segment. */ 334 prev = cdnsp_segment_alloc(pdev, cycle_state, max_packet, flags); 335 if (!prev) 336 return -ENOMEM; 337 338 num_segs--; 339 *first = prev; 340 341 /* Allocate all other segments. */ 342 while (num_segs > 0) { 343 struct cdnsp_segment *next; 344 345 next = cdnsp_segment_alloc(pdev, cycle_state, 346 max_packet, flags); 347 if (!next) { 348 cdnsp_free_segments_for_ring(pdev, *first); 349 return -ENOMEM; 350 } 351 352 cdnsp_link_segments(pdev, prev, next, type); 353 354 prev = next; 355 num_segs--; 356 } 357 358 cdnsp_link_segments(pdev, prev, *first, type); 359 *last = prev; 360 361 return 0; 362 } 363 364 /* 365 * Create a new ring with zero or more segments. 366 * 367 * Link each segment together into a ring. 368 * Set the end flag and the cycle toggle bit on the last segment. 369 */ 370 static struct cdnsp_ring *cdnsp_ring_alloc(struct cdnsp_device *pdev, 371 unsigned int num_segs, 372 enum cdnsp_ring_type type, 373 unsigned int max_packet, 374 gfp_t flags) 375 { 376 struct cdnsp_ring *ring; 377 int ret; 378 379 ring = kzalloc_obj(*(ring), flags); 380 if (!ring) 381 return NULL; 382 383 ring->num_segs = num_segs; 384 ring->bounce_buf_len = max_packet; 385 INIT_LIST_HEAD(&ring->td_list); 386 ring->type = type; 387 388 if (num_segs == 0) 389 return ring; 390 391 ret = cdnsp_alloc_segments_for_ring(pdev, &ring->first_seg, 392 &ring->last_seg, num_segs, 393 1, type, max_packet, flags); 394 if (ret) 395 goto fail; 396 397 return ring; 398 fail: 399 kfree(ring); 400 return NULL; 401 } 402 403 void cdnsp_free_endpoint_rings(struct cdnsp_device *pdev, struct cdnsp_ep *pep) 404 { 405 cdnsp_ring_free(pdev, pep->ring); 406 pep->ring = NULL; 407 cdnsp_free_stream_info(pdev, pep); 408 } 409 410 /* 411 * Expand an existing ring. 412 * Allocate a new ring which has same segment numbers and link the two rings. 413 */ 414 int cdnsp_ring_expansion(struct cdnsp_device *pdev, 415 struct cdnsp_ring *ring, 416 unsigned int num_trbs, 417 gfp_t flags) 418 { 419 unsigned int num_segs_needed; 420 struct cdnsp_segment *first; 421 struct cdnsp_segment *last; 422 unsigned int num_segs; 423 int ret; 424 425 num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) / 426 (TRBS_PER_SEGMENT - 1); 427 428 /* Allocate number of segments we needed, or double the ring size. */ 429 num_segs = max(ring->num_segs, num_segs_needed); 430 431 ret = cdnsp_alloc_segments_for_ring(pdev, &first, &last, num_segs, 432 ring->cycle_state, ring->type, 433 ring->bounce_buf_len, flags); 434 if (ret) 435 return -ENOMEM; 436 437 if (ring->type == TYPE_STREAM) 438 ret = cdnsp_update_stream_segment_mapping(ring->trb_address_map, 439 ring, first, 440 last, flags); 441 442 if (ret) { 443 cdnsp_free_segments_for_ring(pdev, first); 444 445 return ret; 446 } 447 448 cdnsp_link_rings(pdev, ring, first, last, num_segs); 449 trace_cdnsp_ring_expansion(ring); 450 451 return 0; 452 } 453 454 static int cdnsp_init_device_ctx(struct cdnsp_device *pdev) 455 { 456 int size = HCC_64BYTE_CONTEXT(pdev->hcc_params) ? 2048 : 1024; 457 458 pdev->out_ctx.type = CDNSP_CTX_TYPE_DEVICE; 459 pdev->out_ctx.size = size; 460 pdev->out_ctx.ctx_size = CTX_SIZE(pdev->hcc_params); 461 pdev->out_ctx.bytes = dma_pool_zalloc(pdev->device_pool, GFP_ATOMIC, 462 &pdev->out_ctx.dma); 463 464 if (!pdev->out_ctx.bytes) 465 return -ENOMEM; 466 467 pdev->in_ctx.type = CDNSP_CTX_TYPE_INPUT; 468 pdev->in_ctx.ctx_size = pdev->out_ctx.ctx_size; 469 pdev->in_ctx.size = size + pdev->out_ctx.ctx_size; 470 pdev->in_ctx.bytes = dma_pool_zalloc(pdev->device_pool, GFP_ATOMIC, 471 &pdev->in_ctx.dma); 472 473 if (!pdev->in_ctx.bytes) { 474 dma_pool_free(pdev->device_pool, pdev->out_ctx.bytes, 475 pdev->out_ctx.dma); 476 return -ENOMEM; 477 } 478 479 return 0; 480 } 481 482 struct cdnsp_input_control_ctx 483 *cdnsp_get_input_control_ctx(struct cdnsp_container_ctx *ctx) 484 { 485 if (ctx->type != CDNSP_CTX_TYPE_INPUT) 486 return NULL; 487 488 return (struct cdnsp_input_control_ctx *)ctx->bytes; 489 } 490 491 struct cdnsp_slot_ctx *cdnsp_get_slot_ctx(struct cdnsp_container_ctx *ctx) 492 { 493 if (ctx->type == CDNSP_CTX_TYPE_DEVICE) 494 return (struct cdnsp_slot_ctx *)ctx->bytes; 495 496 return (struct cdnsp_slot_ctx *)(ctx->bytes + ctx->ctx_size); 497 } 498 499 struct cdnsp_ep_ctx *cdnsp_get_ep_ctx(struct cdnsp_container_ctx *ctx, 500 unsigned int ep_index) 501 { 502 /* Increment ep index by offset of start of ep ctx array. */ 503 ep_index++; 504 if (ctx->type == CDNSP_CTX_TYPE_INPUT) 505 ep_index++; 506 507 return (struct cdnsp_ep_ctx *)(ctx->bytes + (ep_index * ctx->ctx_size)); 508 } 509 510 static void cdnsp_free_stream_ctx(struct cdnsp_device *pdev, 511 struct cdnsp_ep *pep) 512 { 513 dma_pool_free(pdev->device_pool, pep->stream_info.stream_ctx_array, 514 pep->stream_info.ctx_array_dma); 515 } 516 517 /* The stream context array must be a power of 2. */ 518 static struct cdnsp_stream_ctx 519 *cdnsp_alloc_stream_ctx(struct cdnsp_device *pdev, struct cdnsp_ep *pep) 520 { 521 size_t size = sizeof(struct cdnsp_stream_ctx) * 522 pep->stream_info.num_stream_ctxs; 523 524 if (size > CDNSP_CTX_SIZE) 525 return NULL; 526 527 /** 528 * Driver uses intentionally the device_pool to allocated stream 529 * context array. Device Pool has 2048 bytes of size what gives us 530 * 128 entries. 531 */ 532 return dma_pool_zalloc(pdev->device_pool, GFP_DMA32 | GFP_ATOMIC, 533 &pep->stream_info.ctx_array_dma); 534 } 535 536 struct cdnsp_ring *cdnsp_dma_to_transfer_ring(struct cdnsp_ep *pep, u64 address) 537 { 538 if (pep->ep_state & EP_HAS_STREAMS) 539 return radix_tree_lookup(&pep->stream_info.trb_address_map, 540 address >> TRB_SEGMENT_SHIFT); 541 542 return pep->ring; 543 } 544 545 /* 546 * Change an endpoint's internal structure so it supports stream IDs. 547 * The number of requested streams includes stream 0, which cannot be used by 548 * driver. 549 * 550 * The number of stream contexts in the stream context array may be bigger than 551 * the number of streams the driver wants to use. This is because the number of 552 * stream context array entries must be a power of two. 553 */ 554 int cdnsp_alloc_stream_info(struct cdnsp_device *pdev, 555 struct cdnsp_ep *pep, 556 unsigned int num_stream_ctxs, 557 unsigned int num_streams) 558 { 559 struct cdnsp_stream_info *stream_info; 560 struct cdnsp_ring *cur_ring; 561 u32 cur_stream; 562 u64 addr; 563 int ret; 564 int mps; 565 566 stream_info = &pep->stream_info; 567 stream_info->num_streams = num_streams; 568 stream_info->num_stream_ctxs = num_stream_ctxs; 569 570 /* Initialize the array of virtual pointers to stream rings. */ 571 stream_info->stream_rings = kzalloc_objs(struct cdnsp_ring *, 572 num_streams, GFP_ATOMIC); 573 if (!stream_info->stream_rings) 574 return -ENOMEM; 575 576 /* Initialize the array of DMA addresses for stream rings for the HW. */ 577 stream_info->stream_ctx_array = cdnsp_alloc_stream_ctx(pdev, pep); 578 if (!stream_info->stream_ctx_array) 579 goto cleanup_stream_rings; 580 581 memset(stream_info->stream_ctx_array, 0, 582 sizeof(struct cdnsp_stream_ctx) * num_stream_ctxs); 583 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC); 584 mps = usb_endpoint_maxp(pep->endpoint.desc); 585 586 /* 587 * Allocate rings for all the streams that the driver will use, 588 * and add their segment DMA addresses to the radix tree. 589 * Stream 0 is reserved. 590 */ 591 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { 592 cur_ring = cdnsp_ring_alloc(pdev, 2, TYPE_STREAM, mps, 593 GFP_ATOMIC); 594 stream_info->stream_rings[cur_stream] = cur_ring; 595 596 if (!cur_ring) 597 goto cleanup_rings; 598 599 cdnsp_ring_init(pdev, cur_ring); 600 cur_ring->stream_id = cur_stream; 601 cur_ring->trb_address_map = &stream_info->trb_address_map; 602 603 /* Set deq ptr, cycle bit, and stream context type. */ 604 addr = cur_ring->first_seg->dma | SCT_FOR_CTX(SCT_PRI_TR) | 605 cur_ring->cycle_state; 606 607 stream_info->stream_ctx_array[cur_stream].stream_ring = 608 cpu_to_le64(addr); 609 610 trace_cdnsp_set_stream_ring(cur_ring); 611 612 ret = cdnsp_update_stream_mapping(cur_ring); 613 if (ret) 614 goto cleanup_rings; 615 } 616 617 return 0; 618 619 cleanup_rings: 620 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { 621 cur_ring = stream_info->stream_rings[cur_stream]; 622 if (cur_ring) { 623 cdnsp_ring_free(pdev, cur_ring); 624 stream_info->stream_rings[cur_stream] = NULL; 625 } 626 } 627 628 cdnsp_free_stream_ctx(pdev, pep); 629 630 cleanup_stream_rings: 631 kfree(pep->stream_info.stream_rings); 632 633 return -ENOMEM; 634 } 635 636 /* Frees all stream contexts associated with the endpoint. */ 637 static void cdnsp_free_stream_info(struct cdnsp_device *pdev, 638 struct cdnsp_ep *pep) 639 { 640 struct cdnsp_stream_info *stream_info = &pep->stream_info; 641 struct cdnsp_ring *cur_ring; 642 int cur_stream; 643 644 if (!(pep->ep_state & EP_HAS_STREAMS)) 645 return; 646 647 for (cur_stream = 1; cur_stream < stream_info->num_streams; 648 cur_stream++) { 649 cur_ring = stream_info->stream_rings[cur_stream]; 650 if (cur_ring) { 651 cdnsp_ring_free(pdev, cur_ring); 652 stream_info->stream_rings[cur_stream] = NULL; 653 } 654 } 655 656 if (stream_info->stream_ctx_array) 657 cdnsp_free_stream_ctx(pdev, pep); 658 659 kfree(stream_info->stream_rings); 660 pep->ep_state &= ~EP_HAS_STREAMS; 661 } 662 663 /* All the cdnsp_tds in the ring's TD list should be freed at this point.*/ 664 static void cdnsp_free_priv_device(struct cdnsp_device *pdev) 665 { 666 pdev->dcbaa->dev_context_ptrs[1] = 0; 667 668 cdnsp_free_endpoint_rings(pdev, &pdev->eps[0]); 669 670 if (pdev->in_ctx.bytes) 671 dma_pool_free(pdev->device_pool, pdev->in_ctx.bytes, 672 pdev->in_ctx.dma); 673 674 if (pdev->out_ctx.bytes) 675 dma_pool_free(pdev->device_pool, pdev->out_ctx.bytes, 676 pdev->out_ctx.dma); 677 678 pdev->in_ctx.bytes = NULL; 679 pdev->out_ctx.bytes = NULL; 680 } 681 682 static int cdnsp_alloc_priv_device(struct cdnsp_device *pdev) 683 { 684 int ret; 685 686 ret = cdnsp_init_device_ctx(pdev); 687 if (ret) 688 return ret; 689 690 /* Allocate endpoint 0 ring. */ 691 pdev->eps[0].ring = cdnsp_ring_alloc(pdev, 2, TYPE_CTRL, 0, GFP_ATOMIC); 692 if (!pdev->eps[0].ring) 693 goto fail; 694 695 cdnsp_ring_init(pdev, pdev->eps[0].ring); 696 697 /* Point to output device context in dcbaa. */ 698 pdev->dcbaa->dev_context_ptrs[1] = cpu_to_le64(pdev->out_ctx.dma); 699 pdev->cmd.in_ctx = &pdev->in_ctx; 700 701 trace_cdnsp_alloc_priv_device(pdev); 702 return 0; 703 fail: 704 dma_pool_free(pdev->device_pool, pdev->out_ctx.bytes, 705 pdev->out_ctx.dma); 706 dma_pool_free(pdev->device_pool, pdev->in_ctx.bytes, 707 pdev->in_ctx.dma); 708 709 return ret; 710 } 711 712 void cdnsp_copy_ep0_dequeue_into_input_ctx(struct cdnsp_device *pdev) 713 { 714 struct cdnsp_ep_ctx *ep0_ctx = pdev->eps[0].in_ctx; 715 struct cdnsp_ring *ep_ring = pdev->eps[0].ring; 716 dma_addr_t dma; 717 718 dma = cdnsp_trb_virt_to_dma(ep_ring->enq_seg, ep_ring->enqueue); 719 ep0_ctx->deq = cpu_to_le64(dma | ep_ring->cycle_state); 720 } 721 722 /* Setup an controller private device for a Set Address command. */ 723 int cdnsp_setup_addressable_priv_dev(struct cdnsp_device *pdev) 724 { 725 struct cdnsp_slot_ctx *slot_ctx; 726 struct cdnsp_ep_ctx *ep0_ctx; 727 u32 max_packets, port; 728 729 ep0_ctx = cdnsp_get_ep_ctx(&pdev->in_ctx, 0); 730 slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx); 731 732 /* Only the control endpoint is valid - one endpoint context. */ 733 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); 734 735 switch (pdev->gadget.speed) { 736 case USB_SPEED_SUPER_PLUS: 737 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP); 738 max_packets = MAX_PACKET(512); 739 break; 740 case USB_SPEED_SUPER: 741 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS); 742 max_packets = MAX_PACKET(512); 743 break; 744 case USB_SPEED_HIGH: 745 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS); 746 max_packets = MAX_PACKET(64); 747 break; 748 case USB_SPEED_FULL: 749 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS); 750 max_packets = MAX_PACKET(64); 751 break; 752 default: 753 /* Speed was not set , this shouldn't happen. */ 754 return -EINVAL; 755 } 756 757 port = DEV_PORT(pdev->active_port->port_num); 758 slot_ctx->dev_port |= cpu_to_le32(port); 759 slot_ctx->dev_state = cpu_to_le32((pdev->device_address & 760 DEV_ADDR_MASK)); 761 ep0_ctx->tx_info = cpu_to_le32(EP_AVG_TRB_LENGTH(0x8)); 762 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP)); 763 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) | 764 max_packets); 765 766 ep0_ctx->deq = cpu_to_le64(pdev->eps[0].ring->first_seg->dma | 767 pdev->eps[0].ring->cycle_state); 768 769 trace_cdnsp_setup_addressable_priv_device(pdev); 770 771 return 0; 772 } 773 774 /* 775 * Convert interval expressed as 2^(bInterval - 1) == interval into 776 * straight exponent value 2^n == interval. 777 */ 778 static unsigned int cdnsp_parse_exponent_interval(struct usb_gadget *g, 779 struct cdnsp_ep *pep) 780 { 781 unsigned int interval; 782 783 interval = clamp_val(pep->endpoint.desc->bInterval, 1, 16) - 1; 784 if (interval != pep->endpoint.desc->bInterval - 1) 785 dev_warn(&g->dev, "ep %s - rounding interval to %d %sframes\n", 786 pep->name, 1 << interval, 787 g->speed == USB_SPEED_FULL ? "" : "micro"); 788 789 /* 790 * Full speed isoc endpoints specify interval in frames, 791 * not microframes. We are using microframes everywhere, 792 * so adjust accordingly. 793 */ 794 if (g->speed == USB_SPEED_FULL) 795 interval += 3; /* 1 frame = 2^3 uframes */ 796 797 /* Controller handles only up to 512ms (2^12). */ 798 if (interval > 12) 799 interval = 12; 800 801 return interval; 802 } 803 804 /* 805 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of 806 * microframes, rounded down to nearest power of 2. 807 */ 808 static unsigned int cdnsp_microframes_to_exponent(struct usb_gadget *g, 809 struct cdnsp_ep *pep, 810 unsigned int desc_interval, 811 unsigned int min_exponent, 812 unsigned int max_exponent) 813 { 814 unsigned int interval; 815 816 interval = fls(desc_interval) - 1; 817 return clamp_val(interval, min_exponent, max_exponent); 818 } 819 820 /* 821 * Return the polling interval. 822 * 823 * The polling interval is expressed in "microframes". If controllers's Interval 824 * field is set to N, it will service the endpoint every 2^(Interval)*125us. 825 */ 826 static unsigned int cdnsp_get_endpoint_interval(struct usb_gadget *g, 827 struct cdnsp_ep *pep) 828 { 829 unsigned int interval = 0; 830 831 switch (g->speed) { 832 case USB_SPEED_HIGH: 833 case USB_SPEED_SUPER_PLUS: 834 case USB_SPEED_SUPER: 835 if (usb_endpoint_xfer_int(pep->endpoint.desc) || 836 usb_endpoint_xfer_isoc(pep->endpoint.desc)) 837 interval = cdnsp_parse_exponent_interval(g, pep); 838 break; 839 case USB_SPEED_FULL: 840 if (usb_endpoint_xfer_isoc(pep->endpoint.desc)) { 841 interval = cdnsp_parse_exponent_interval(g, pep); 842 } else if (usb_endpoint_xfer_int(pep->endpoint.desc)) { 843 interval = pep->endpoint.desc->bInterval << 3; 844 interval = cdnsp_microframes_to_exponent(g, pep, 845 interval, 846 3, 10); 847 } 848 849 break; 850 default: 851 WARN_ON(1); 852 } 853 854 return interval; 855 } 856 857 /* 858 * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps. 859 * High speed endpoint descriptors can define "the number of additional 860 * transaction opportunities per microframe", but that goes in the Max Burst 861 * endpoint context field. 862 */ 863 static u32 cdnsp_get_endpoint_mult(struct usb_gadget *g, struct cdnsp_ep *pep) 864 { 865 if (g->speed < USB_SPEED_SUPER || 866 !usb_endpoint_xfer_isoc(pep->endpoint.desc)) 867 return 0; 868 869 return pep->endpoint.comp_desc->bmAttributes; 870 } 871 872 static u32 cdnsp_get_endpoint_max_burst(struct usb_gadget *g, 873 struct cdnsp_ep *pep) 874 { 875 /* Super speed and Plus have max burst in ep companion desc */ 876 if (g->speed >= USB_SPEED_SUPER) 877 return pep->endpoint.comp_desc->bMaxBurst; 878 879 if (g->speed == USB_SPEED_HIGH && 880 (usb_endpoint_xfer_isoc(pep->endpoint.desc) || 881 usb_endpoint_xfer_int(pep->endpoint.desc))) 882 return usb_endpoint_maxp_mult(pep->endpoint.desc) - 1; 883 884 return 0; 885 } 886 887 static u32 cdnsp_get_endpoint_type(const struct usb_endpoint_descriptor *desc) 888 { 889 int in; 890 891 in = usb_endpoint_dir_in(desc); 892 893 switch (usb_endpoint_type(desc)) { 894 case USB_ENDPOINT_XFER_CONTROL: 895 return CTRL_EP; 896 case USB_ENDPOINT_XFER_BULK: 897 return in ? BULK_IN_EP : BULK_OUT_EP; 898 case USB_ENDPOINT_XFER_ISOC: 899 return in ? ISOC_IN_EP : ISOC_OUT_EP; 900 case USB_ENDPOINT_XFER_INT: 901 return in ? INT_IN_EP : INT_OUT_EP; 902 } 903 904 return 0; 905 } 906 907 /* 908 * Return the maximum endpoint service interval time (ESIT) payload. 909 * Basically, this is the maxpacket size, multiplied by the burst size 910 * and mult size. 911 */ 912 static u32 cdnsp_get_max_esit_payload(struct usb_gadget *g, 913 struct cdnsp_ep *pep) 914 { 915 int max_packet; 916 int max_burst; 917 918 /* Only applies for interrupt or isochronous endpoints*/ 919 if (usb_endpoint_xfer_control(pep->endpoint.desc) || 920 usb_endpoint_xfer_bulk(pep->endpoint.desc)) 921 return 0; 922 923 /* SuperSpeedPlus Isoc ep sending over 48k per EIST. */ 924 if (g->speed >= USB_SPEED_SUPER_PLUS && 925 USB_SS_SSP_ISOC_COMP(pep->endpoint.desc->bmAttributes)) 926 return le16_to_cpu(pep->endpoint.comp_desc->wBytesPerInterval); 927 /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */ 928 else if (g->speed >= USB_SPEED_SUPER) 929 return le16_to_cpu(pep->endpoint.comp_desc->wBytesPerInterval); 930 931 max_packet = usb_endpoint_maxp(pep->endpoint.desc); 932 max_burst = usb_endpoint_maxp_mult(pep->endpoint.desc); 933 934 /* A 0 in max burst means 1 transfer per ESIT */ 935 return max_packet * max_burst; 936 } 937 938 int cdnsp_endpoint_init(struct cdnsp_device *pdev, 939 struct cdnsp_ep *pep, 940 gfp_t mem_flags) 941 { 942 enum cdnsp_ring_type ring_type; 943 struct cdnsp_ep_ctx *ep_ctx; 944 unsigned int err_count = 0; 945 unsigned int avg_trb_len; 946 unsigned int max_packet; 947 unsigned int max_burst; 948 unsigned int interval; 949 u32 max_esit_payload; 950 unsigned int mult; 951 u32 endpoint_type; 952 int ret; 953 954 ep_ctx = pep->in_ctx; 955 956 endpoint_type = cdnsp_get_endpoint_type(pep->endpoint.desc); 957 if (!endpoint_type) 958 return -EINVAL; 959 960 ring_type = usb_endpoint_type(pep->endpoint.desc); 961 962 /* 963 * Get values to fill the endpoint context, mostly from ep descriptor. 964 * The average TRB buffer length for bulk endpoints is unclear as we 965 * have no clue on scatter gather list entry size. For Isoc and Int, 966 * set it to max available. 967 */ 968 max_esit_payload = cdnsp_get_max_esit_payload(&pdev->gadget, pep); 969 interval = cdnsp_get_endpoint_interval(&pdev->gadget, pep); 970 mult = cdnsp_get_endpoint_mult(&pdev->gadget, pep); 971 max_packet = usb_endpoint_maxp(pep->endpoint.desc); 972 max_burst = cdnsp_get_endpoint_max_burst(&pdev->gadget, pep); 973 avg_trb_len = max_esit_payload; 974 975 /* Allow 3 retries for everything but isoc, set CErr = 3. */ 976 if (!usb_endpoint_xfer_isoc(pep->endpoint.desc)) 977 err_count = 3; 978 if (usb_endpoint_xfer_bulk(pep->endpoint.desc) && 979 pdev->gadget.speed == USB_SPEED_HIGH) 980 max_packet = 512; 981 /* Controller spec indicates that ctrl ep avg TRB Length should be 8. */ 982 if (usb_endpoint_xfer_control(pep->endpoint.desc)) 983 avg_trb_len = 8; 984 985 /* Set up the endpoint ring. */ 986 pep->ring = cdnsp_ring_alloc(pdev, 2, ring_type, max_packet, mem_flags); 987 if (!pep->ring) 988 return -ENOMEM; 989 990 cdnsp_ring_init(pdev, pep->ring); 991 992 pep->skip = false; 993 994 /* Fill the endpoint context */ 995 ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) | 996 EP_INTERVAL(interval) | EP_MULT(mult)); 997 ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) | 998 MAX_PACKET(max_packet) | MAX_BURST(max_burst) | 999 ERROR_COUNT(err_count)); 1000 ep_ctx->deq = cpu_to_le64(pep->ring->first_seg->dma | 1001 pep->ring->cycle_state); 1002 1003 ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) | 1004 EP_AVG_TRB_LENGTH(avg_trb_len)); 1005 1006 if (usb_endpoint_xfer_bulk(pep->endpoint.desc) && 1007 pdev->gadget.speed > USB_SPEED_HIGH) { 1008 ret = cdnsp_alloc_streams(pdev, pep); 1009 if (ret < 0) 1010 return ret; 1011 } 1012 1013 return 0; 1014 } 1015 1016 void cdnsp_endpoint_zero(struct cdnsp_device *pdev, struct cdnsp_ep *pep) 1017 { 1018 pep->in_ctx->ep_info = 0; 1019 pep->in_ctx->ep_info2 = 0; 1020 pep->in_ctx->deq = 0; 1021 pep->in_ctx->tx_info = 0; 1022 } 1023 1024 static int cdnsp_alloc_erst(struct cdnsp_device *pdev, 1025 struct cdnsp_ring *evt_ring, 1026 struct cdnsp_erst *erst) 1027 { 1028 struct cdnsp_erst_entry *entry; 1029 struct cdnsp_segment *seg; 1030 unsigned int val; 1031 size_t size; 1032 1033 size = sizeof(struct cdnsp_erst_entry) * evt_ring->num_segs; 1034 erst->entries = dma_alloc_coherent(pdev->dev, size, 1035 &erst->erst_dma_addr, GFP_KERNEL); 1036 if (!erst->entries) 1037 return -ENOMEM; 1038 1039 erst->num_entries = evt_ring->num_segs; 1040 1041 seg = evt_ring->first_seg; 1042 for (val = 0; val < evt_ring->num_segs; val++) { 1043 entry = &erst->entries[val]; 1044 entry->seg_addr = cpu_to_le64(seg->dma); 1045 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); 1046 entry->rsvd = 0; 1047 seg = seg->next; 1048 } 1049 1050 return 0; 1051 } 1052 1053 static void cdnsp_free_erst(struct cdnsp_device *pdev, struct cdnsp_erst *erst) 1054 { 1055 size_t size = sizeof(struct cdnsp_erst_entry) * (erst->num_entries); 1056 struct device *dev = pdev->dev; 1057 1058 if (erst->entries) 1059 dma_free_coherent(dev, size, erst->entries, 1060 erst->erst_dma_addr); 1061 1062 erst->entries = NULL; 1063 } 1064 1065 void cdnsp_mem_cleanup(struct cdnsp_device *pdev) 1066 { 1067 struct device *dev = pdev->dev; 1068 1069 cdnsp_free_priv_device(pdev); 1070 cdnsp_free_erst(pdev, &pdev->erst); 1071 1072 if (pdev->event_ring) 1073 cdnsp_ring_free(pdev, pdev->event_ring); 1074 1075 pdev->event_ring = NULL; 1076 1077 if (pdev->cmd_ring) 1078 cdnsp_ring_free(pdev, pdev->cmd_ring); 1079 1080 pdev->cmd_ring = NULL; 1081 1082 dma_pool_destroy(pdev->segment_pool); 1083 pdev->segment_pool = NULL; 1084 dma_pool_destroy(pdev->device_pool); 1085 pdev->device_pool = NULL; 1086 1087 dma_free_coherent(dev, sizeof(*pdev->dcbaa), 1088 pdev->dcbaa, pdev->dcbaa->dma); 1089 1090 pdev->dcbaa = NULL; 1091 memset(&pdev->usb2_port, 0, sizeof(struct cdnsp_port)); 1092 memset(&pdev->eusb_port, 0, sizeof(struct cdnsp_port)); 1093 memset(&pdev->usb3_port, 0, sizeof(struct cdnsp_port)); 1094 pdev->active_port = NULL; 1095 } 1096 1097 static void cdnsp_add_in_port(struct cdnsp_device *pdev, 1098 struct cdnsp_port *port, 1099 __le32 __iomem *addr) 1100 { 1101 u32 temp, port_offset, port_count; 1102 1103 temp = readl(addr); 1104 port->maj_rev = CDNSP_EXT_PORT_MAJOR(temp); 1105 port->min_rev = CDNSP_EXT_PORT_MINOR(temp); 1106 1107 /* Port offset and count in the third dword.*/ 1108 temp = readl(addr + 2); 1109 port_offset = CDNSP_EXT_PORT_OFF(temp); 1110 port_count = CDNSP_EXT_PORT_COUNT(temp); 1111 1112 if (port == &pdev->eusb_port) { 1113 /* 1114 * If controller has usb2 + eusb port then eusb is as 1115 * second port 1116 */ 1117 if (port_count == 2) 1118 port_offset++; 1119 1120 if (port_count == 1 && pdev->usb2_port.exist) 1121 return; 1122 } 1123 1124 trace_cdnsp_port_info(addr, port_offset, port_count, port->maj_rev); 1125 1126 port->port_num = port_offset; 1127 port->exist = 1; 1128 } 1129 1130 /* 1131 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that 1132 * specify what speeds each port is supposed to be. 1133 */ 1134 static int cdnsp_setup_port_arrays(struct cdnsp_device *pdev) 1135 { 1136 void __iomem *base; 1137 u32 offset; 1138 int i; 1139 1140 base = &pdev->cap_regs->hc_capbase; 1141 offset = cdnsp_find_next_ext_cap(base, 0, 1142 EXT_CAP_CFG_DEV_20PORT_CAP_ID); 1143 if (offset) 1144 pdev->port20_regs = base + offset; 1145 1146 offset = 0; 1147 1148 /* Driver expects max 2 extended protocol capability. */ 1149 for (i = 0; i < 2; i++) { 1150 u32 temp; 1151 1152 offset = cdnsp_find_next_ext_cap(base, offset, 1153 EXT_CAPS_PROTOCOL); 1154 temp = readl(base + offset); 1155 1156 if (CDNSP_EXT_PORT_MAJOR(temp) == 0x03 && 1157 !pdev->usb3_port.port_num) 1158 cdnsp_add_in_port(pdev, &pdev->usb3_port, 1159 base + offset); 1160 1161 if (CDNSP_EXT_PORT_MAJOR(temp) == 0x02) { 1162 if (!pdev->usb2_port.port_num && pdev->port20_regs) 1163 cdnsp_add_in_port(pdev, &pdev->usb2_port, 1164 base + offset); 1165 1166 if (!pdev->eusb_port.port_num) 1167 cdnsp_add_in_port(pdev, &pdev->eusb_port, 1168 base + offset); 1169 } 1170 } 1171 1172 if (!pdev->usb2_port.exist && !pdev->eusb_port.exist && 1173 !pdev->usb3_port.exist) { 1174 dev_err(pdev->dev, "Error: No port detected\n"); 1175 return -ENODEV; 1176 } 1177 1178 if (pdev->usb2_port.exist) { 1179 pdev->usb2_port.regs = (struct cdnsp_port_regs __iomem *) 1180 (&pdev->op_regs->port_reg_base + NUM_PORT_REGS * 1181 (pdev->usb2_port.port_num - 1)); 1182 trace_cdnsp_init("Found USB 2.0 port."); 1183 } 1184 1185 if (pdev->eusb_port.exist) { 1186 pdev->eusb_port.regs = (struct cdnsp_port_regs __iomem *) 1187 (&pdev->op_regs->port_reg_base + NUM_PORT_REGS * 1188 (pdev->eusb_port.port_num - 1)); 1189 trace_cdnsp_init("Found eUSB 2.0 port."); 1190 } 1191 1192 if (pdev->usb3_port.exist) { 1193 offset = cdnsp_find_next_ext_cap(base, 0, D_XEC_CFG_3XPORT_CAP); 1194 pdev->port3x_regs = base + offset; 1195 1196 pdev->usb3_port.regs = (struct cdnsp_port_regs __iomem *) 1197 (&pdev->op_regs->port_reg_base + NUM_PORT_REGS * 1198 (pdev->usb3_port.port_num - 1)); 1199 trace_cdnsp_init("Found USB 3.x port."); 1200 } 1201 1202 return 0; 1203 } 1204 1205 static void cdnsp_initialize_ring_segments(struct cdnsp_device *pdev, struct cdnsp_ring *ring) 1206 { 1207 struct cdnsp_segment *seg; 1208 1209 /* Only event ring does not use link TRB. */ 1210 if (ring->type == TYPE_EVENT) 1211 return; 1212 1213 seg = ring->first_seg; 1214 1215 while (seg) { 1216 struct cdnsp_segment *next = seg->next; 1217 1218 cdnsp_link_segments(pdev, seg, next, ring->type); 1219 if (next == ring->first_seg) 1220 break; 1221 1222 seg = next; 1223 } 1224 1225 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |= cpu_to_le32(LINK_TOGGLE); 1226 } 1227 1228 void cdnsp_ring_init(struct cdnsp_device *pdev, struct cdnsp_ring *ring) 1229 { 1230 cdnsp_initialize_ring_segments(pdev, ring); 1231 cdnsp_initialize_ring_info(ring); 1232 trace_cdnsp_ring_alloc(ring); 1233 } 1234 1235 /* 1236 * Initialize memory for CDNSP (one-time init). 1237 * 1238 * Program the PAGESIZE register, initialize the device context array, create 1239 * device contexts, set up a command ring segment, create event 1240 * ring (one for now). 1241 */ 1242 int cdnsp_mem_init(struct cdnsp_device *pdev) 1243 { 1244 struct device *dev = pdev->dev; 1245 int ret = -ENOMEM; 1246 dma_addr_t dma; 1247 u32 page_size; 1248 1249 /* 1250 * Use 4K pages, since that's common and the minimum the 1251 * controller supports 1252 */ 1253 page_size = 1 << 12; 1254 1255 /* 1256 * Doorbell array must be physically contiguous 1257 * and 64-byte (cache line) aligned. 1258 */ 1259 pdev->dcbaa = dma_alloc_coherent(dev, sizeof(*pdev->dcbaa), 1260 &dma, GFP_KERNEL); 1261 if (!pdev->dcbaa) 1262 return -ENOMEM; 1263 1264 pdev->dcbaa->dma = dma; 1265 1266 /* 1267 * Initialize the ring segment pool. The ring must be a contiguous 1268 * structure comprised of TRBs. The TRBs must be 16 byte aligned, 1269 * however, the command ring segment needs 64-byte aligned segments 1270 * and our use of dma addresses in the trb_address_map radix tree needs 1271 * TRB_SEGMENT_SIZE alignment, so driver pick the greater alignment 1272 * need. 1273 */ 1274 pdev->segment_pool = dma_pool_create("CDNSP ring segments", dev, 1275 TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, 1276 page_size); 1277 if (!pdev->segment_pool) 1278 goto release_dcbaa; 1279 1280 pdev->device_pool = dma_pool_create("CDNSP input/output contexts", dev, 1281 CDNSP_CTX_SIZE, 64, page_size); 1282 if (!pdev->device_pool) 1283 goto destroy_segment_pool; 1284 1285 1286 /* Set up the command ring to have one segments for now. */ 1287 pdev->cmd_ring = cdnsp_ring_alloc(pdev, 1, TYPE_COMMAND, 0, GFP_KERNEL); 1288 if (!pdev->cmd_ring) 1289 goto destroy_device_pool; 1290 1291 /* Set ir_set to interrupt register set 0 */ 1292 pdev->ir_set = &pdev->run_regs->ir_set[0]; 1293 1294 /* 1295 * Event ring setup: Allocate a normal ring, but also setup 1296 * the event ring segment table (ERST). 1297 */ 1298 pdev->event_ring = cdnsp_ring_alloc(pdev, ERST_NUM_SEGS, TYPE_EVENT, 1299 0, GFP_KERNEL); 1300 if (!pdev->event_ring) 1301 goto free_cmd_ring; 1302 1303 ret = cdnsp_alloc_erst(pdev, pdev->event_ring, &pdev->erst); 1304 if (ret) 1305 goto free_event_ring; 1306 1307 ret = cdnsp_setup_port_arrays(pdev); 1308 if (ret) 1309 goto free_erst; 1310 1311 ret = cdnsp_alloc_priv_device(pdev); 1312 if (ret) { 1313 dev_err(pdev->dev, 1314 "Could not allocate cdnsp_device data structures\n"); 1315 goto free_erst; 1316 } 1317 1318 return 0; 1319 1320 free_erst: 1321 cdnsp_free_erst(pdev, &pdev->erst); 1322 free_event_ring: 1323 cdnsp_ring_free(pdev, pdev->event_ring); 1324 free_cmd_ring: 1325 cdnsp_ring_free(pdev, pdev->cmd_ring); 1326 destroy_device_pool: 1327 dma_pool_destroy(pdev->device_pool); 1328 destroy_segment_pool: 1329 dma_pool_destroy(pdev->segment_pool); 1330 release_dcbaa: 1331 dma_free_coherent(dev, sizeof(*pdev->dcbaa), pdev->dcbaa, 1332 pdev->dcbaa->dma); 1333 1334 cdnsp_reset(pdev); 1335 1336 return ret; 1337 } 1338