1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller PCI glue driver 4 * 5 * Copyright (C) 2011-2013 Samsung India Software Operations 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <ufs/ufshcd.h> 13 #include <linux/delay.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/pm_qos.h> 18 #include <linux/debugfs.h> 19 #include <linux/uuid.h> 20 #include <linux/acpi.h> 21 #include <linux/gpio/consumer.h> 22 23 #define MAX_SUPP_MAC 64 24 25 enum intel_ufs_dsm_func_id { 26 INTEL_DSM_FNS = 0, 27 INTEL_DSM_RESET = 1, 28 }; 29 30 struct intel_host { 31 u32 dsm_fns; 32 u32 active_ltr; 33 u32 idle_ltr; 34 struct dentry *debugfs_root; 35 struct gpio_desc *reset_gpio; 36 }; 37 38 static const guid_t intel_dsm_guid = 39 GUID_INIT(0x1A4832A0, 0x7D03, 0x43CA, 40 0xB0, 0x20, 0xF6, 0xDC, 0xD1, 0x2A, 0x19, 0x50); 41 42 static bool __intel_dsm_supported(struct intel_host *host, 43 enum intel_ufs_dsm_func_id fn) 44 { 45 return fn < 32 && fn >= 0 && (host->dsm_fns & (1u << fn)); 46 } 47 48 #define INTEL_DSM_SUPPORTED(host, name) \ 49 __intel_dsm_supported(host, INTEL_DSM_##name) 50 51 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 52 unsigned int fn, u32 *result) 53 { 54 union acpi_object *obj; 55 int err = 0; 56 size_t len; 57 58 obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL, 59 ACPI_TYPE_BUFFER); 60 if (!obj) 61 return -EOPNOTSUPP; 62 63 if (obj->buffer.length < 1) { 64 err = -EINVAL; 65 goto out; 66 } 67 68 len = min_t(size_t, obj->buffer.length, 4); 69 70 *result = 0; 71 memcpy(result, obj->buffer.pointer, len); 72 out: 73 ACPI_FREE(obj); 74 75 return err; 76 } 77 78 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 79 unsigned int fn, u32 *result) 80 { 81 if (!__intel_dsm_supported(intel_host, fn)) 82 return -EOPNOTSUPP; 83 84 return __intel_dsm(intel_host, dev, fn, result); 85 } 86 87 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev) 88 { 89 int err; 90 91 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 92 dev_dbg(dev, "DSM fns %#x, error %d\n", intel_host->dsm_fns, err); 93 } 94 95 static int ufs_intel_hce_enable_notify(struct ufs_hba *hba, 96 enum ufs_notify_change_status status) 97 { 98 /* Cannot enable ICE until after HC enable */ 99 if (status == POST_CHANGE && hba->caps & UFSHCD_CAP_CRYPTO) { 100 u32 hce = ufshcd_readl(hba, REG_CONTROLLER_ENABLE); 101 102 hce |= CRYPTO_GENERAL_ENABLE; 103 ufshcd_writel(hba, hce, REG_CONTROLLER_ENABLE); 104 } 105 106 return 0; 107 } 108 109 static int ufs_intel_disable_lcc(struct ufs_hba *hba) 110 { 111 u32 attr = UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE); 112 u32 lcc_enable = 0; 113 114 ufshcd_dme_get(hba, attr, &lcc_enable); 115 if (lcc_enable) 116 ufshcd_disable_host_tx_lcc(hba); 117 118 return 0; 119 } 120 121 static int ufs_intel_link_startup_notify(struct ufs_hba *hba, 122 enum ufs_notify_change_status status) 123 { 124 int err = 0; 125 126 switch (status) { 127 case PRE_CHANGE: 128 err = ufs_intel_disable_lcc(hba); 129 break; 130 case POST_CHANGE: 131 break; 132 default: 133 break; 134 } 135 136 return err; 137 } 138 139 static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes) 140 { 141 struct ufs_pa_layer_attr pwr_info = hba->pwr_info; 142 int ret; 143 144 pwr_info.lane_rx = lanes; 145 pwr_info.lane_tx = lanes; 146 ret = ufshcd_config_pwr_mode(hba, &pwr_info); 147 if (ret) 148 dev_err(hba->dev, "%s: Setting %u lanes, err = %d\n", 149 __func__, lanes, ret); 150 return ret; 151 } 152 153 static int ufs_intel_lkf_pwr_change_notify(struct ufs_hba *hba, 154 enum ufs_notify_change_status status, 155 const struct ufs_pa_layer_attr *dev_max_params, 156 struct ufs_pa_layer_attr *dev_req_params) 157 { 158 int err = 0; 159 160 switch (status) { 161 case PRE_CHANGE: 162 if (ufshcd_is_hs_mode(dev_max_params) && 163 (hba->pwr_info.lane_rx != 2 || hba->pwr_info.lane_tx != 2)) 164 ufs_intel_set_lanes(hba, 2); 165 memcpy(dev_req_params, dev_max_params, sizeof(*dev_req_params)); 166 break; 167 case POST_CHANGE: 168 if (ufshcd_is_hs_mode(dev_req_params)) { 169 u32 peer_granularity; 170 171 usleep_range(1000, 1250); 172 err = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 173 &peer_granularity); 174 } 175 break; 176 default: 177 break; 178 } 179 180 return err; 181 } 182 183 static int ufs_intel_lkf_apply_dev_quirks(struct ufs_hba *hba) 184 { 185 u32 granularity, peer_granularity; 186 u32 pa_tactivate, peer_pa_tactivate; 187 int ret; 188 189 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &granularity); 190 if (ret) 191 goto out; 192 193 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &peer_granularity); 194 if (ret) 195 goto out; 196 197 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 198 if (ret) 199 goto out; 200 201 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &peer_pa_tactivate); 202 if (ret) 203 goto out; 204 205 if (granularity == peer_granularity) { 206 u32 new_peer_pa_tactivate = pa_tactivate + 2; 207 208 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), new_peer_pa_tactivate); 209 } 210 out: 211 return ret; 212 } 213 214 #define INTEL_ACTIVELTR 0x804 215 #define INTEL_IDLELTR 0x808 216 217 #define INTEL_LTR_REQ BIT(15) 218 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 219 #define INTEL_LTR_SCALE_1US (2 << 10) 220 #define INTEL_LTR_SCALE_32US (3 << 10) 221 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 222 223 static void intel_cache_ltr(struct ufs_hba *hba) 224 { 225 struct intel_host *host = ufshcd_get_variant(hba); 226 227 host->active_ltr = readl(hba->mmio_base + INTEL_ACTIVELTR); 228 host->idle_ltr = readl(hba->mmio_base + INTEL_IDLELTR); 229 } 230 231 static void intel_ltr_set(struct device *dev, s32 val) 232 { 233 struct ufs_hba *hba = dev_get_drvdata(dev); 234 struct intel_host *host = ufshcd_get_variant(hba); 235 u32 ltr; 236 237 pm_runtime_get_sync(dev); 238 239 /* 240 * Program latency tolerance (LTR) accordingly what has been asked 241 * by the PM QoS layer or disable it in case we were passed 242 * negative value or PM_QOS_LATENCY_ANY. 243 */ 244 ltr = readl(hba->mmio_base + INTEL_ACTIVELTR); 245 246 if (val == PM_QOS_LATENCY_ANY || val < 0) { 247 ltr &= ~INTEL_LTR_REQ; 248 } else { 249 ltr |= INTEL_LTR_REQ; 250 ltr &= ~INTEL_LTR_SCALE_MASK; 251 ltr &= ~INTEL_LTR_VALUE_MASK; 252 253 if (val > INTEL_LTR_VALUE_MASK) { 254 val >>= 5; 255 if (val > INTEL_LTR_VALUE_MASK) 256 val = INTEL_LTR_VALUE_MASK; 257 ltr |= INTEL_LTR_SCALE_32US | val; 258 } else { 259 ltr |= INTEL_LTR_SCALE_1US | val; 260 } 261 } 262 263 if (ltr == host->active_ltr) 264 goto out; 265 266 writel(ltr, hba->mmio_base + INTEL_ACTIVELTR); 267 writel(ltr, hba->mmio_base + INTEL_IDLELTR); 268 269 /* Cache the values into intel_host structure */ 270 intel_cache_ltr(hba); 271 out: 272 pm_runtime_put(dev); 273 } 274 275 static void intel_ltr_expose(struct device *dev) 276 { 277 dev->power.set_latency_tolerance = intel_ltr_set; 278 dev_pm_qos_expose_latency_tolerance(dev); 279 } 280 281 static void intel_ltr_hide(struct device *dev) 282 { 283 dev_pm_qos_hide_latency_tolerance(dev); 284 dev->power.set_latency_tolerance = NULL; 285 } 286 287 static void intel_add_debugfs(struct ufs_hba *hba) 288 { 289 struct dentry *dir = debugfs_create_dir(dev_name(hba->dev), NULL); 290 struct intel_host *host = ufshcd_get_variant(hba); 291 292 intel_cache_ltr(hba); 293 294 host->debugfs_root = dir; 295 debugfs_create_x32("active_ltr", 0444, dir, &host->active_ltr); 296 debugfs_create_x32("idle_ltr", 0444, dir, &host->idle_ltr); 297 } 298 299 static void intel_remove_debugfs(struct ufs_hba *hba) 300 { 301 struct intel_host *host = ufshcd_get_variant(hba); 302 303 debugfs_remove_recursive(host->debugfs_root); 304 } 305 306 static int ufs_intel_device_reset(struct ufs_hba *hba) 307 { 308 struct intel_host *host = ufshcd_get_variant(hba); 309 310 if (INTEL_DSM_SUPPORTED(host, RESET)) { 311 u32 result = 0; 312 int err; 313 314 err = intel_dsm(host, hba->dev, INTEL_DSM_RESET, &result); 315 if (!err && !result) 316 err = -EIO; 317 if (err) 318 dev_err(hba->dev, "%s: DSM error %d result %u\n", 319 __func__, err, result); 320 return err; 321 } 322 323 if (!host->reset_gpio) 324 return -EOPNOTSUPP; 325 326 gpiod_set_value_cansleep(host->reset_gpio, 1); 327 usleep_range(10, 15); 328 329 gpiod_set_value_cansleep(host->reset_gpio, 0); 330 usleep_range(10, 15); 331 332 return 0; 333 } 334 335 static struct gpio_desc *ufs_intel_get_reset_gpio(struct device *dev) 336 { 337 /* GPIO in _DSD has active low setting */ 338 return devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 339 } 340 341 static int ufs_intel_common_init(struct ufs_hba *hba) 342 { 343 struct intel_host *host; 344 345 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 346 347 host = devm_kzalloc(hba->dev, sizeof(*host), GFP_KERNEL); 348 if (!host) 349 return -ENOMEM; 350 ufshcd_set_variant(hba, host); 351 intel_dsm_init(host, hba->dev); 352 if (INTEL_DSM_SUPPORTED(host, RESET)) { 353 if (hba->vops->device_reset) 354 hba->caps |= UFSHCD_CAP_DEEPSLEEP; 355 } else { 356 if (hba->vops->device_reset) 357 host->reset_gpio = ufs_intel_get_reset_gpio(hba->dev); 358 if (IS_ERR(host->reset_gpio)) { 359 dev_err(hba->dev, "%s: failed to get reset GPIO, error %ld\n", 360 __func__, PTR_ERR(host->reset_gpio)); 361 host->reset_gpio = NULL; 362 } 363 if (host->reset_gpio) { 364 gpiod_set_value_cansleep(host->reset_gpio, 0); 365 hba->caps |= UFSHCD_CAP_DEEPSLEEP; 366 } 367 } 368 intel_ltr_expose(hba->dev); 369 intel_add_debugfs(hba); 370 return 0; 371 } 372 373 static void ufs_intel_common_exit(struct ufs_hba *hba) 374 { 375 intel_remove_debugfs(hba); 376 intel_ltr_hide(hba->dev); 377 } 378 379 static int ufs_intel_resume(struct ufs_hba *hba, enum ufs_pm_op op) 380 { 381 if (ufshcd_is_link_hibern8(hba)) { 382 int ret = ufshcd_uic_hibern8_exit(hba); 383 384 if (!ret) { 385 ufshcd_set_link_active(hba); 386 } else { 387 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 388 __func__, ret); 389 /* 390 * Force reset and restore. Any other actions can lead 391 * to an unrecoverable state. 392 */ 393 ufshcd_set_link_off(hba); 394 } 395 } 396 397 return 0; 398 } 399 400 static int ufs_intel_ehl_init(struct ufs_hba *hba) 401 { 402 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8; 403 return ufs_intel_common_init(hba); 404 } 405 406 static int ufs_intel_lkf_init(struct ufs_hba *hba) 407 { 408 int err; 409 410 hba->nop_out_timeout = 200; 411 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8; 412 hba->caps |= UFSHCD_CAP_CRYPTO; 413 err = ufs_intel_common_init(hba); 414 /* LKF always needs a full reset, so set PM accordingly */ 415 if (hba->caps & UFSHCD_CAP_DEEPSLEEP) { 416 hba->spm_lvl = UFS_PM_LVL_6; 417 hba->rpm_lvl = UFS_PM_LVL_6; 418 } else { 419 hba->spm_lvl = UFS_PM_LVL_5; 420 hba->rpm_lvl = UFS_PM_LVL_5; 421 } 422 return err; 423 } 424 425 static int ufs_intel_adl_init(struct ufs_hba *hba) 426 { 427 hba->nop_out_timeout = 200; 428 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8; 429 hba->caps |= UFSHCD_CAP_WB_EN; 430 return ufs_intel_common_init(hba); 431 } 432 433 static int ufs_intel_mtl_init(struct ufs_hba *hba) 434 { 435 hba->rpm_lvl = UFS_PM_LVL_2; 436 hba->spm_lvl = UFS_PM_LVL_2; 437 hba->caps |= UFSHCD_CAP_CRYPTO | UFSHCD_CAP_WB_EN; 438 return ufs_intel_common_init(hba); 439 } 440 441 static int ufs_qemu_get_hba_mac(struct ufs_hba *hba) 442 { 443 return MAX_SUPP_MAC; 444 } 445 446 static int ufs_qemu_mcq_config_resource(struct ufs_hba *hba) 447 { 448 hba->mcq_base = hba->mmio_base + ufshcd_mcq_queue_cfg_addr(hba); 449 450 return 0; 451 } 452 453 static int ufs_qemu_op_runtime_config(struct ufs_hba *hba) 454 { 455 struct ufshcd_mcq_opr_info_t *opr; 456 int i; 457 458 u32 sqdao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_SQDAO, 0)); 459 u32 sqisao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_SQISAO, 0)); 460 u32 cqdao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_CQDAO, 0)); 461 u32 cqisao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_CQISAO, 0)); 462 463 hba->mcq_opr[OPR_SQD].offset = sqdao; 464 hba->mcq_opr[OPR_SQIS].offset = sqisao; 465 hba->mcq_opr[OPR_CQD].offset = cqdao; 466 hba->mcq_opr[OPR_CQIS].offset = cqisao; 467 468 for (i = 0; i < OPR_MAX; i++) { 469 opr = &hba->mcq_opr[i]; 470 opr->stride = 48; 471 opr->base = hba->mmio_base + opr->offset; 472 } 473 474 return 0; 475 } 476 477 static struct ufs_hba_variant_ops ufs_qemu_hba_vops = { 478 .name = "qemu-pci", 479 .get_hba_mac = ufs_qemu_get_hba_mac, 480 .mcq_config_resource = ufs_qemu_mcq_config_resource, 481 .op_runtime_config = ufs_qemu_op_runtime_config, 482 }; 483 484 static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = { 485 .name = "intel-pci", 486 .init = ufs_intel_common_init, 487 .exit = ufs_intel_common_exit, 488 .link_startup_notify = ufs_intel_link_startup_notify, 489 .resume = ufs_intel_resume, 490 }; 491 492 static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = { 493 .name = "intel-pci", 494 .init = ufs_intel_ehl_init, 495 .exit = ufs_intel_common_exit, 496 .link_startup_notify = ufs_intel_link_startup_notify, 497 .resume = ufs_intel_resume, 498 }; 499 500 static struct ufs_hba_variant_ops ufs_intel_lkf_hba_vops = { 501 .name = "intel-pci", 502 .init = ufs_intel_lkf_init, 503 .exit = ufs_intel_common_exit, 504 .hce_enable_notify = ufs_intel_hce_enable_notify, 505 .link_startup_notify = ufs_intel_link_startup_notify, 506 .pwr_change_notify = ufs_intel_lkf_pwr_change_notify, 507 .apply_dev_quirks = ufs_intel_lkf_apply_dev_quirks, 508 .resume = ufs_intel_resume, 509 .device_reset = ufs_intel_device_reset, 510 }; 511 512 static struct ufs_hba_variant_ops ufs_intel_adl_hba_vops = { 513 .name = "intel-pci", 514 .init = ufs_intel_adl_init, 515 .exit = ufs_intel_common_exit, 516 .link_startup_notify = ufs_intel_link_startup_notify, 517 .resume = ufs_intel_resume, 518 .device_reset = ufs_intel_device_reset, 519 }; 520 521 static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = { 522 .name = "intel-pci", 523 .init = ufs_intel_mtl_init, 524 .exit = ufs_intel_common_exit, 525 .hce_enable_notify = ufs_intel_hce_enable_notify, 526 .link_startup_notify = ufs_intel_link_startup_notify, 527 .resume = ufs_intel_resume, 528 .device_reset = ufs_intel_device_reset, 529 }; 530 531 #ifdef CONFIG_PM_SLEEP 532 static int ufshcd_pci_restore(struct device *dev) 533 { 534 struct ufs_hba *hba = dev_get_drvdata(dev); 535 536 /* Force a full reset and restore */ 537 ufshcd_set_link_off(hba); 538 539 return ufshcd_system_resume(dev); 540 } 541 #endif 542 543 /** 544 * ufshcd_pci_remove - de-allocate PCI/SCSI host and host memory space 545 * data structure memory 546 * @pdev: pointer to PCI handle 547 */ 548 static void ufshcd_pci_remove(struct pci_dev *pdev) 549 { 550 struct ufs_hba *hba = pci_get_drvdata(pdev); 551 552 pm_runtime_forbid(&pdev->dev); 553 pm_runtime_get_noresume(&pdev->dev); 554 ufshcd_remove(hba); 555 } 556 557 /** 558 * ufshcd_pci_probe - probe routine of the driver 559 * @pdev: pointer to PCI device handle 560 * @id: PCI device id 561 * 562 * Return: 0 on success, non-zero value on failure. 563 */ 564 static int 565 ufshcd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 566 { 567 struct ufs_hba *hba; 568 void __iomem *mmio_base; 569 int err; 570 571 err = pcim_enable_device(pdev); 572 if (err) { 573 dev_err(&pdev->dev, "pcim_enable_device failed\n"); 574 return err; 575 } 576 577 pci_set_master(pdev); 578 579 mmio_base = pcim_iomap_region(pdev, 0, UFSHCD); 580 if (IS_ERR(mmio_base)) { 581 dev_err(&pdev->dev, "request and iomap failed\n"); 582 return PTR_ERR(mmio_base); 583 } 584 585 err = ufshcd_alloc_host(&pdev->dev, &hba); 586 if (err) { 587 dev_err(&pdev->dev, "Allocation failed\n"); 588 return err; 589 } 590 591 hba->vops = (struct ufs_hba_variant_ops *)id->driver_data; 592 593 err = ufshcd_init(hba, mmio_base, pdev->irq); 594 if (err) { 595 dev_err(&pdev->dev, "Initialization failed\n"); 596 return err; 597 } 598 599 pm_runtime_put_noidle(&pdev->dev); 600 pm_runtime_allow(&pdev->dev); 601 602 return 0; 603 } 604 605 static const struct dev_pm_ops ufshcd_pci_pm_ops = { 606 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 607 #ifdef CONFIG_PM_SLEEP 608 .suspend = ufshcd_system_suspend, 609 .resume = ufshcd_system_resume, 610 .freeze = ufshcd_system_suspend, 611 .thaw = ufshcd_system_resume, 612 .poweroff = ufshcd_system_suspend, 613 .restore = ufshcd_pci_restore, 614 .prepare = ufshcd_suspend_prepare, 615 .complete = ufshcd_resume_complete, 616 #endif 617 }; 618 619 static const struct pci_device_id ufshcd_pci_tbl[] = { 620 { PCI_VENDOR_ID_REDHAT, 0x0013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 621 (kernel_ulong_t)&ufs_qemu_hba_vops }, 622 { PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 623 { PCI_VDEVICE(INTEL, 0x9DFA), (kernel_ulong_t)&ufs_intel_cnl_hba_vops }, 624 { PCI_VDEVICE(INTEL, 0x4B41), (kernel_ulong_t)&ufs_intel_ehl_hba_vops }, 625 { PCI_VDEVICE(INTEL, 0x4B43), (kernel_ulong_t)&ufs_intel_ehl_hba_vops }, 626 { PCI_VDEVICE(INTEL, 0x98FA), (kernel_ulong_t)&ufs_intel_lkf_hba_vops }, 627 { PCI_VDEVICE(INTEL, 0x51FF), (kernel_ulong_t)&ufs_intel_adl_hba_vops }, 628 { PCI_VDEVICE(INTEL, 0x54FF), (kernel_ulong_t)&ufs_intel_adl_hba_vops }, 629 { PCI_VDEVICE(INTEL, 0x7E47), (kernel_ulong_t)&ufs_intel_mtl_hba_vops }, 630 { PCI_VDEVICE(INTEL, 0xA847), (kernel_ulong_t)&ufs_intel_mtl_hba_vops }, 631 { PCI_VDEVICE(INTEL, 0x7747), (kernel_ulong_t)&ufs_intel_mtl_hba_vops }, 632 { PCI_VDEVICE(INTEL, 0xE447), (kernel_ulong_t)&ufs_intel_mtl_hba_vops }, 633 { PCI_VDEVICE(INTEL, 0x4D47), (kernel_ulong_t)&ufs_intel_mtl_hba_vops }, 634 { } /* terminate list */ 635 }; 636 637 MODULE_DEVICE_TABLE(pci, ufshcd_pci_tbl); 638 639 static struct pci_driver ufshcd_pci_driver = { 640 .name = UFSHCD, 641 .id_table = ufshcd_pci_tbl, 642 .probe = ufshcd_pci_probe, 643 .remove = ufshcd_pci_remove, 644 .driver = { 645 .pm = &ufshcd_pci_pm_ops 646 }, 647 }; 648 649 module_pci_driver(ufshcd_pci_driver); 650 651 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 652 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 653 MODULE_DESCRIPTION("UFS host controller PCI glue driver"); 654 MODULE_LICENSE("GPL"); 655