1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef UFS_QCOM_H_ 6 #define UFS_QCOM_H_ 7 8 #include <linux/reset-controller.h> 9 #include <linux/reset.h> 10 #include <soc/qcom/ice.h> 11 #include <ufs/ufshcd.h> 12 13 #define MPHY_TX_FSM_STATE 0x41 14 #define TX_FSM_HIBERN8 0x1 15 #define HBRN8_POLL_TOUT_MS 100 16 #define DEFAULT_CLK_RATE_HZ 1000000 17 #define MAX_SUPP_MAC 64 18 #define MAX_ESI_VEC 32 19 20 #define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) 21 #define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) 22 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0) 23 #define UFS_DEV_VER_MAJOR_MASK GENMASK(7, 4) 24 25 #define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B 26 27 /* bit and mask definitions for PA_VS_CLK_CFG_REG attribute */ 28 #define PA_VS_CLK_CFG_REG 0x9004 29 #define PA_VS_CLK_CFG_REG_MASK GENMASK(8, 0) 30 31 /* bit and mask definitions for DL_VS_CLK_CFG attribute */ 32 #define DL_VS_CLK_CFG 0xA00B 33 #define DL_VS_CLK_CFG_MASK GENMASK(9, 0) 34 #define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9) 35 36 #define UFS_QCOM_EOM_VOLTAGE_STEPS_MAX 127 37 #define UFS_QCOM_EOM_TIMING_STEPS_MAX 63 38 #define UFS_QCOM_EOM_TARGET_TEST_COUNT_MIN 8 39 #define UFS_QCOM_EOM_TARGET_TEST_COUNT_G6 0x3F 40 41 #define SW_RX_FOM_EOM_COORDS 23 42 #define SW_RX_FOM_EOM_COORDS_WEIGHT (127 / SW_RX_FOM_EOM_COORDS) 43 44 struct ufs_eom_coord { 45 int t_step; 46 int v_step; 47 u8 eye_mask; 48 }; 49 50 static const struct ufs_eom_coord sw_rx_fom_eom_coords_g6[SW_RX_FOM_EOM_COORDS] = { 51 [0] = { -2, -15, UFS_EOM_EYE_MASK_M }, 52 [1] = { 0, -15, UFS_EOM_EYE_MASK_M }, 53 [2] = { 2, -15, UFS_EOM_EYE_MASK_M }, 54 [3] = { -4, -10, UFS_EOM_EYE_MASK_M }, 55 [4] = { -2, -10, UFS_EOM_EYE_MASK_M }, 56 [5] = { 0, -10, UFS_EOM_EYE_MASK_M }, 57 [6] = { 2, -10, UFS_EOM_EYE_MASK_M }, 58 [7] = { 4, -10, UFS_EOM_EYE_MASK_M }, 59 [8] = { -6, 0, UFS_EOM_EYE_MASK_M }, 60 [9] = { -4, 0, UFS_EOM_EYE_MASK_M }, 61 [10] = { -2, 0, UFS_EOM_EYE_MASK_M }, 62 [11] = { 0, 0, UFS_EOM_EYE_MASK_M }, 63 [12] = { 2, 0, UFS_EOM_EYE_MASK_M }, 64 [13] = { 4, 0, UFS_EOM_EYE_MASK_M }, 65 [14] = { 6, 0, UFS_EOM_EYE_MASK_M }, 66 [15] = { -4, 10, UFS_EOM_EYE_MASK_M }, 67 [16] = { -2, 10, UFS_EOM_EYE_MASK_M }, 68 [17] = { 0, 10, UFS_EOM_EYE_MASK_M }, 69 [18] = { 2, 10, UFS_EOM_EYE_MASK_M }, 70 [19] = { 4, 10, UFS_EOM_EYE_MASK_M }, 71 [20] = { -2, 15, UFS_EOM_EYE_MASK_M }, 72 [21] = { 0, 15, UFS_EOM_EYE_MASK_M }, 73 [22] = { 2, 15, UFS_EOM_EYE_MASK_M }, 74 }; 75 76 /* Qualcomm MCQ Configuration */ 77 #define UFS_QCOM_MCQCAP_QCFGPTR 224 /* 0xE0 in hex */ 78 #define UFS_QCOM_MCQ_CONFIG_OFFSET (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) /* 0x1C000 */ 79 80 /* Doorbell offsets within MCQ region (relative to MCQ_CONFIG_BASE) */ 81 #define UFS_QCOM_MCQ_SQD_OFFSET 0x5000 82 #define UFS_QCOM_MCQ_CQD_OFFSET 0x5080 83 #define UFS_QCOM_MCQ_SQIS_OFFSET 0x5040 84 #define UFS_QCOM_MCQ_CQIS_OFFSET 0x50C0 85 #define UFS_QCOM_MCQ_STRIDE 0x100 86 87 /* Calculated doorbell address offsets (relative to mmio_base) */ 88 #define UFS_QCOM_SQD_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_SQD_OFFSET) 89 #define UFS_QCOM_CQD_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_CQD_OFFSET) 90 #define UFS_QCOM_SQIS_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_SQIS_OFFSET) 91 #define UFS_QCOM_CQIS_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_CQIS_OFFSET) 92 #define REG_UFS_MCQ_STRIDE UFS_QCOM_MCQ_STRIDE 93 94 /* MCQ Vendor specific address offsets (relative to MCQ_CONFIG_BASE) */ 95 #define UFS_MEM_VS_BASE 0x4000 96 #define UFS_MEM_CQIS_VS 0x4008 97 98 /* QCOM UFS host controller vendor specific registers */ 99 enum { 100 REG_UFS_SYS1CLK_1US = 0xC0, 101 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4, 102 REG_UFS_LOCAL_PORT_ID_REG = 0xC8, 103 REG_UFS_PA_ERR_CODE = 0xCC, 104 /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ 105 REG_UFS_PARAM0 = 0xD0, 106 /* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */ 107 REG_UFS_CFG0 = 0xD8, 108 REG_UFS_CFG1 = 0xDC, 109 REG_UFS_CFG2 = 0xE0, 110 REG_UFS_HW_VERSION = 0xE4, 111 112 UFS_TEST_BUS = 0xE8, 113 UFS_TEST_BUS_CTRL_0 = 0xEC, 114 UFS_TEST_BUS_CTRL_1 = 0xF0, 115 UFS_TEST_BUS_CTRL_2 = 0xF4, 116 UFS_UNIPRO_CFG = 0xF8, 117 118 /* 119 * QCOM UFS host controller vendor specific registers 120 * added in HW Version 3.0.0 121 */ 122 UFS_AH8_CFG = 0xFC, 123 124 UFS_RD_REG_MCQ = 0xD00, 125 UFS_MEM_ICE_CFG = 0x2600, 126 REG_UFS_MEM_ICE_CONFIG = 0x260C, 127 REG_UFS_MEM_ICE_NUM_CORE = 0x2664, 128 129 REG_UFS_CFG3 = 0x271C, 130 131 REG_UFS_DEBUG_SPARE_CFG = 0x284C, 132 }; 133 134 /* QCOM UFS host controller vendor specific debug registers */ 135 enum { 136 UFS_DBG_RD_REG_UAWM = 0x100, 137 UFS_DBG_RD_REG_UARM = 0x200, 138 UFS_DBG_RD_REG_TXUC = 0x300, 139 UFS_DBG_RD_REG_RXUC = 0x400, 140 UFS_DBG_RD_REG_DFC = 0x500, 141 UFS_DBG_RD_REG_TRLUT = 0x600, 142 UFS_DBG_RD_REG_TMRLUT = 0x700, 143 UFS_UFS_DBG_RD_REG_OCSC = 0x800, 144 145 UFS_UFS_DBG_RD_DESC_RAM = 0x1500, 146 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700, 147 UFS_UFS_DBG_RD_RESP_RAM = 0x1800, 148 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900, 149 }; 150 151 /* QCOM UFS HC vendor specific Hibern8 count registers */ 152 enum { 153 REG_UFS_HW_H8_ENTER_CNT = 0x2700, 154 REG_UFS_SW_H8_ENTER_CNT = 0x2704, 155 REG_UFS_SW_AFTER_HW_H8_ENTER_CNT = 0x2708, 156 REG_UFS_HW_H8_EXIT_CNT = 0x270C, 157 REG_UFS_SW_H8_EXIT_CNT = 0x2710, 158 }; 159 160 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x) 161 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) 162 163 /* bit definitions for REG_UFS_CFG0 register */ 164 #define QUNIPRO_G4_SEL BIT(5) 165 166 /* bit definitions for REG_UFS_CFG1 register */ 167 #define QUNIPRO_SEL BIT(0) 168 #define UFS_PHY_SOFT_RESET BIT(1) 169 #define UTP_DBG_RAMS_EN BIT(17) 170 #define TEST_BUS_EN BIT(18) 171 #define TEST_BUS_SEL GENMASK(22, 19) 172 #define UFS_REG_TEST_BUS_EN BIT(30) 173 174 /* bit definitions for REG_UFS_CFG2 register */ 175 #define UAWM_HW_CGC_EN BIT(0) 176 #define UARM_HW_CGC_EN BIT(1) 177 #define TXUC_HW_CGC_EN BIT(2) 178 #define RXUC_HW_CGC_EN BIT(3) 179 #define DFC_HW_CGC_EN BIT(4) 180 #define TRLUT_HW_CGC_EN BIT(5) 181 #define TMRLUT_HW_CGC_EN BIT(6) 182 #define OCSC_HW_CGC_EN BIT(7) 183 184 /* bit definitions for REG_UFS_CFG3 register */ 185 #define ESI_VEC_MASK GENMASK(22, 12) 186 187 /* bit definitions for REG_UFS_PARAM0 */ 188 #define MAX_HS_GEAR_MASK GENMASK(6, 4) 189 #define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) 190 191 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ 192 #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */ 193 194 /* bit definition for UFS Shared ICE config */ 195 #define UFS_QCOM_CAP_ICE_CONFIG BIT(0) 196 197 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ 198 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ 199 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\ 200 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) 201 202 /* QUniPro Vendor specific attributes */ 203 #define PA_TX_HSG1_SYNC_LENGTH 0x1552 204 #define PA_VS_CONFIG_REG1 0x9000 205 #define DME_VS_CORE_CLK_CTRL 0xD002 206 #define TX_HS_EQUALIZER 0x0037 207 208 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ 209 #define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16) 210 #define CLK_1US_CYCLES_MASK GENMASK(7, 0) 211 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) 212 #define PA_VS_CORE_CLK_40NS_CYCLES 0x9007 213 #define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0) 214 215 216 /* QCOM UFS host controller core clk frequencies */ 217 #define UNIPRO_CORE_CLK_FREQ_37_5_MHZ 38 218 #define UNIPRO_CORE_CLK_FREQ_75_MHZ 75 219 #define UNIPRO_CORE_CLK_FREQ_100_MHZ 100 220 #define UNIPRO_CORE_CLK_FREQ_150_MHZ 150 221 #define UNIPRO_CORE_CLK_FREQ_300_MHZ 300 222 #define UNIPRO_CORE_CLK_FREQ_201_5_MHZ 202 223 #define UNIPRO_CORE_CLK_FREQ_403_MHZ 403 224 225 /* TX_HSG1_SYNC_LENGTH attr value */ 226 #define PA_TX_HSG1_SYNC_LENGTH_VAL 0x4A 227 228 /* 229 * Some ufs device vendors need a different TSync length. 230 * Enable this quirk to give an additional TX_HS_SYNC_LENGTH. 231 */ 232 #define UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH BIT(16) 233 234 /* 235 * Some ufs device vendors need a different Deemphasis setting. 236 * Enable this quirk to tune TX Deemphasis parameters. 237 */ 238 #define UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING BIT(17) 239 240 /* ICE allocator type to share AES engines among TX stream and RX stream */ 241 #define ICE_ALLOCATOR_TYPE 2 242 243 /* 244 * Number of cores allocated for RX stream when Read data block received and 245 * Write data block is not in progress 246 */ 247 #define NUM_RX_R1W0 28 248 249 /* 250 * Number of cores allocated for TX stream when Device asked to send write 251 * data block and Read data block is not in progress 252 */ 253 #define NUM_TX_R0W1 28 254 255 /* 256 * Number of cores allocated for RX stream when Read data block received and 257 * Write data block is in progress 258 * OR 259 * Device asked to send write data block and Read data block is in progress 260 */ 261 #define NUM_RX_R1W1 15 262 263 /* 264 * Number of cores allocated for TX stream (UFS write) when Read data block 265 * received and Write data block is in progress 266 * OR 267 * Device asked to send write data block and Read data block is in progress 268 */ 269 #define NUM_TX_R1W1 13 270 271 static inline void 272 ufs_qcom_get_controller_revision(struct ufs_hba *hba, 273 u8 *major, u16 *minor, u16 *step) 274 { 275 u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION); 276 277 *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); 278 *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); 279 *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver); 280 }; 281 282 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) 283 { 284 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1); 285 286 /* 287 * Dummy read to ensure the write takes effect before doing any sort 288 * of delay 289 */ 290 ufshcd_readl(hba, REG_UFS_CFG1); 291 } 292 293 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) 294 { 295 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1); 296 297 /* 298 * Dummy read to ensure the write takes effect before doing any sort 299 * of delay 300 */ 301 ufshcd_readl(hba, REG_UFS_CFG1); 302 } 303 304 /* Host controller hardware version: major.minor.step */ 305 struct ufs_hw_version { 306 u16 step; 307 u16 minor; 308 u8 major; 309 }; 310 311 struct ufs_qcom_testbus { 312 u8 select_major; 313 u8 select_minor; 314 }; 315 316 struct gpio_desc; 317 318 struct ufs_qcom_host { 319 struct phy *generic_phy; 320 struct ufs_hba *hba; 321 struct ufs_pa_layer_attr dev_req_params; 322 struct clk_bulk_data *clks; 323 u32 num_clks; 324 bool is_lane_clks_enabled; 325 326 struct icc_path *icc_ddr; 327 struct icc_path *icc_cpu; 328 329 #ifdef CONFIG_SCSI_UFS_CRYPTO 330 struct qcom_ice *ice; 331 #endif 332 u32 caps; 333 void __iomem *dev_ref_clk_ctrl_mmio; 334 bool is_dev_ref_clk_enabled; 335 struct ufs_hw_version hw_ver; 336 337 u32 dev_ref_clk_en_mask; 338 339 struct ufs_qcom_testbus testbus; 340 341 /* Reset control of HCI */ 342 struct reset_control *core_reset; 343 struct reset_controller_dev rcdev; 344 345 struct gpio_desc *device_reset; 346 347 struct ufs_host_params host_params; 348 u32 phy_gear; 349 350 bool esi_enabled; 351 352 u32 saved_tx_eq_g1_setting; 353 }; 354 355 struct ufs_qcom_drvdata { 356 enum ufshcd_quirks quirks; 357 bool no_phy_retention; 358 const struct ufs_hba_variant_ops *vops; 359 }; 360 361 static inline u32 362 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg) 363 { 364 if (host->hw_ver.major <= 0x02) 365 return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg); 366 367 return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg); 368 }; 369 370 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba) 371 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba) 372 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba) 373 #define ceil(freq, div) ((freq) % (div) == 0 ? ((freq)/(div)) : ((freq)/(div) + 1)) 374 375 int ufs_qcom_testbus_config(struct ufs_qcom_host *host); 376 377 #endif /* UFS_QCOM_H_ */ 378