xref: /linux/drivers/ufs/host/ufs-qcom.h (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3  */
4 
5 #ifndef UFS_QCOM_H_
6 #define UFS_QCOM_H_
7 
8 #include <linux/reset-controller.h>
9 #include <linux/reset.h>
10 #include <soc/qcom/ice.h>
11 #include <ufs/ufshcd.h>
12 
13 #define MPHY_TX_FSM_STATE       0x41
14 #define TX_FSM_HIBERN8          0x1
15 #define HBRN8_POLL_TOUT_MS      100
16 #define DEFAULT_CLK_RATE_HZ     1000000
17 #define MAX_SUPP_MAC		64
18 #define MAX_ESI_VEC		32
19 
20 #define UFS_HW_VER_MAJOR_MASK	GENMASK(31, 28)
21 #define UFS_HW_VER_MINOR_MASK	GENMASK(27, 16)
22 #define UFS_HW_VER_STEP_MASK	GENMASK(15, 0)
23 #define UFS_DEV_VER_MAJOR_MASK	GENMASK(7, 4)
24 
25 #define UFS_QCOM_LIMIT_HS_RATE		PA_HS_MODE_B
26 
27 /* QCOM UFS host controller vendor specific registers */
28 enum {
29 	REG_UFS_SYS1CLK_1US                 = 0xC0,
30 	REG_UFS_TX_SYMBOL_CLK_NS_US         = 0xC4,
31 	REG_UFS_LOCAL_PORT_ID_REG           = 0xC8,
32 	REG_UFS_PA_ERR_CODE                 = 0xCC,
33 	/* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
34 	REG_UFS_PARAM0                      = 0xD0,
35 	/* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */
36 	REG_UFS_CFG0                        = 0xD8,
37 	REG_UFS_CFG1                        = 0xDC,
38 	REG_UFS_CFG2                        = 0xE0,
39 	REG_UFS_HW_VERSION                  = 0xE4,
40 
41 	UFS_TEST_BUS				= 0xE8,
42 	UFS_TEST_BUS_CTRL_0			= 0xEC,
43 	UFS_TEST_BUS_CTRL_1			= 0xF0,
44 	UFS_TEST_BUS_CTRL_2			= 0xF4,
45 	UFS_UNIPRO_CFG				= 0xF8,
46 
47 	/*
48 	 * QCOM UFS host controller vendor specific registers
49 	 * added in HW Version 3.0.0
50 	 */
51 	UFS_AH8_CFG				= 0xFC,
52 
53 	REG_UFS_CFG3				= 0x271C,
54 
55 	REG_UFS_DEBUG_SPARE_CFG			= 0x284C,
56 };
57 
58 /* QCOM UFS host controller vendor specific debug registers */
59 enum {
60 	UFS_DBG_RD_REG_UAWM			= 0x100,
61 	UFS_DBG_RD_REG_UARM			= 0x200,
62 	UFS_DBG_RD_REG_TXUC			= 0x300,
63 	UFS_DBG_RD_REG_RXUC			= 0x400,
64 	UFS_DBG_RD_REG_DFC			= 0x500,
65 	UFS_DBG_RD_REG_TRLUT			= 0x600,
66 	UFS_DBG_RD_REG_TMRLUT			= 0x700,
67 	UFS_UFS_DBG_RD_REG_OCSC			= 0x800,
68 
69 	UFS_UFS_DBG_RD_DESC_RAM			= 0x1500,
70 	UFS_UFS_DBG_RD_PRDT_RAM			= 0x1700,
71 	UFS_UFS_DBG_RD_RESP_RAM			= 0x1800,
72 	UFS_UFS_DBG_RD_EDTL_RAM			= 0x1900,
73 };
74 
75 enum {
76 	UFS_MEM_CQIS_VS		= 0x8,
77 };
78 
79 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x)	(0x000 + x)
80 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x)	(0x400 + x)
81 
82 /* bit definitions for REG_UFS_CFG0 register */
83 #define QUNIPRO_G4_SEL		BIT(5)
84 
85 /* bit definitions for REG_UFS_CFG1 register */
86 #define QUNIPRO_SEL		BIT(0)
87 #define UFS_PHY_SOFT_RESET	BIT(1)
88 #define UTP_DBG_RAMS_EN		BIT(17)
89 #define TEST_BUS_EN		BIT(18)
90 #define TEST_BUS_SEL		GENMASK(22, 19)
91 #define UFS_REG_TEST_BUS_EN	BIT(30)
92 
93 /* bit definitions for REG_UFS_CFG2 register */
94 #define UAWM_HW_CGC_EN		BIT(0)
95 #define UARM_HW_CGC_EN		BIT(1)
96 #define TXUC_HW_CGC_EN		BIT(2)
97 #define RXUC_HW_CGC_EN		BIT(3)
98 #define DFC_HW_CGC_EN		BIT(4)
99 #define TRLUT_HW_CGC_EN		BIT(5)
100 #define TMRLUT_HW_CGC_EN	BIT(6)
101 #define OCSC_HW_CGC_EN		BIT(7)
102 
103 /* bit definitions for REG_UFS_CFG3 register */
104 #define ESI_VEC_MASK		GENMASK(22, 12)
105 
106 /* bit definitions for REG_UFS_PARAM0 */
107 #define MAX_HS_GEAR_MASK	GENMASK(6, 4)
108 #define UFS_QCOM_MAX_GEAR(x)	FIELD_GET(MAX_HS_GEAR_MASK, (x))
109 
110 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
111 #define TEST_BUS_SUB_SEL_MASK	GENMASK(4, 0)  /* All XXX_SEL fields are 5 bits wide */
112 
113 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
114 				 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
115 				 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
116 				 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
117 
118 /* QUniPro Vendor specific attributes */
119 #define PA_VS_CONFIG_REG1	0x9000
120 #define DME_VS_CORE_CLK_CTRL	0xD002
121 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
122 #define CLK_1US_CYCLES_MASK_V4				GENMASK(27, 16)
123 #define CLK_1US_CYCLES_MASK				GENMASK(7, 0)
124 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT	BIT(8)
125 #define PA_VS_CORE_CLK_40NS_CYCLES			0x9007
126 #define PA_VS_CORE_CLK_40NS_CYCLES_MASK			GENMASK(6, 0)
127 
128 
129 /* QCOM UFS host controller core clk frequencies */
130 #define UNIPRO_CORE_CLK_FREQ_37_5_MHZ          38
131 #define UNIPRO_CORE_CLK_FREQ_75_MHZ            75
132 #define UNIPRO_CORE_CLK_FREQ_100_MHZ           100
133 #define UNIPRO_CORE_CLK_FREQ_150_MHZ           150
134 #define UNIPRO_CORE_CLK_FREQ_300_MHZ           300
135 #define UNIPRO_CORE_CLK_FREQ_201_5_MHZ         202
136 #define UNIPRO_CORE_CLK_FREQ_403_MHZ           403
137 
138 static inline void
139 ufs_qcom_get_controller_revision(struct ufs_hba *hba,
140 				 u8 *major, u16 *minor, u16 *step)
141 {
142 	u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
143 
144 	*major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver);
145 	*minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver);
146 	*step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver);
147 };
148 
149 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
150 {
151 	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
152 
153 	/*
154 	 * Dummy read to ensure the write takes effect before doing any sort
155 	 * of delay
156 	 */
157 	ufshcd_readl(hba, REG_UFS_CFG1);
158 }
159 
160 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
161 {
162 	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1);
163 
164 	/*
165 	 * Dummy read to ensure the write takes effect before doing any sort
166 	 * of delay
167 	 */
168 	ufshcd_readl(hba, REG_UFS_CFG1);
169 }
170 
171 /* Host controller hardware version: major.minor.step */
172 struct ufs_hw_version {
173 	u16 step;
174 	u16 minor;
175 	u8 major;
176 };
177 
178 struct ufs_qcom_testbus {
179 	u8 select_major;
180 	u8 select_minor;
181 };
182 
183 struct gpio_desc;
184 
185 struct ufs_qcom_host {
186 	struct phy *generic_phy;
187 	struct ufs_hba *hba;
188 	struct ufs_pa_layer_attr dev_req_params;
189 	struct clk_bulk_data *clks;
190 	u32 num_clks;
191 	bool is_lane_clks_enabled;
192 
193 	struct icc_path *icc_ddr;
194 	struct icc_path *icc_cpu;
195 
196 #ifdef CONFIG_SCSI_UFS_CRYPTO
197 	struct qcom_ice *ice;
198 #endif
199 
200 	void __iomem *dev_ref_clk_ctrl_mmio;
201 	bool is_dev_ref_clk_enabled;
202 	struct ufs_hw_version hw_ver;
203 
204 	u32 dev_ref_clk_en_mask;
205 
206 	struct ufs_qcom_testbus testbus;
207 
208 	/* Reset control of HCI */
209 	struct reset_control *core_reset;
210 	struct reset_controller_dev rcdev;
211 
212 	struct gpio_desc *device_reset;
213 
214 	struct ufs_host_params host_params;
215 	u32 phy_gear;
216 
217 	bool esi_enabled;
218 };
219 
220 static inline u32
221 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg)
222 {
223 	if (host->hw_ver.major <= 0x02)
224 		return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg);
225 
226 	return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg);
227 };
228 
229 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
230 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
231 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
232 #define ceil(freq, div) ((freq) % (div) == 0 ? ((freq)/(div)) : ((freq)/(div) + 1))
233 
234 int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
235 
236 #endif /* UFS_QCOM_H_ */
237