1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef UFS_QCOM_H_ 6 #define UFS_QCOM_H_ 7 8 #include <linux/reset-controller.h> 9 #include <linux/reset.h> 10 #include <soc/qcom/ice.h> 11 #include <ufs/ufshcd.h> 12 13 #define MPHY_TX_FSM_STATE 0x41 14 #define TX_FSM_HIBERN8 0x1 15 #define HBRN8_POLL_TOUT_MS 100 16 #define DEFAULT_CLK_RATE_HZ 1000000 17 #define MAX_SUPP_MAC 64 18 #define MAX_ESI_VEC 32 19 20 #define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) 21 #define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) 22 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0) 23 #define UFS_DEV_VER_MAJOR_MASK GENMASK(7, 4) 24 25 #define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B 26 27 /* bit and mask definitions for PA_VS_CLK_CFG_REG attribute */ 28 #define PA_VS_CLK_CFG_REG 0x9004 29 #define PA_VS_CLK_CFG_REG_MASK GENMASK(8, 0) 30 31 /* bit and mask definitions for DL_VS_CLK_CFG attribute */ 32 #define DL_VS_CLK_CFG 0xA00B 33 #define DL_VS_CLK_CFG_MASK GENMASK(9, 0) 34 #define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9) 35 36 /* Qualcomm MCQ Configuration */ 37 #define UFS_QCOM_MCQCAP_QCFGPTR 224 /* 0xE0 in hex */ 38 #define UFS_QCOM_MCQ_CONFIG_OFFSET (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) /* 0x1C000 */ 39 40 /* Doorbell offsets within MCQ region (relative to MCQ_CONFIG_BASE) */ 41 #define UFS_QCOM_MCQ_SQD_OFFSET 0x5000 42 #define UFS_QCOM_MCQ_CQD_OFFSET 0x5080 43 #define UFS_QCOM_MCQ_SQIS_OFFSET 0x5040 44 #define UFS_QCOM_MCQ_CQIS_OFFSET 0x50C0 45 #define UFS_QCOM_MCQ_STRIDE 0x100 46 47 /* Calculated doorbell address offsets (relative to mmio_base) */ 48 #define UFS_QCOM_SQD_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_SQD_OFFSET) 49 #define UFS_QCOM_CQD_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_CQD_OFFSET) 50 #define UFS_QCOM_SQIS_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_SQIS_OFFSET) 51 #define UFS_QCOM_CQIS_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_CQIS_OFFSET) 52 #define REG_UFS_MCQ_STRIDE UFS_QCOM_MCQ_STRIDE 53 54 /* MCQ Vendor specific address offsets (relative to MCQ_CONFIG_BASE) */ 55 #define UFS_MEM_VS_BASE 0x4000 56 #define UFS_MEM_CQIS_VS 0x4008 57 58 /* QCOM UFS host controller vendor specific registers */ 59 enum { 60 REG_UFS_SYS1CLK_1US = 0xC0, 61 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4, 62 REG_UFS_LOCAL_PORT_ID_REG = 0xC8, 63 REG_UFS_PA_ERR_CODE = 0xCC, 64 /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ 65 REG_UFS_PARAM0 = 0xD0, 66 /* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */ 67 REG_UFS_CFG0 = 0xD8, 68 REG_UFS_CFG1 = 0xDC, 69 REG_UFS_CFG2 = 0xE0, 70 REG_UFS_HW_VERSION = 0xE4, 71 72 UFS_TEST_BUS = 0xE8, 73 UFS_TEST_BUS_CTRL_0 = 0xEC, 74 UFS_TEST_BUS_CTRL_1 = 0xF0, 75 UFS_TEST_BUS_CTRL_2 = 0xF4, 76 UFS_UNIPRO_CFG = 0xF8, 77 78 /* 79 * QCOM UFS host controller vendor specific registers 80 * added in HW Version 3.0.0 81 */ 82 UFS_AH8_CFG = 0xFC, 83 84 UFS_RD_REG_MCQ = 0xD00, 85 UFS_MEM_ICE_CFG = 0x2600, 86 REG_UFS_MEM_ICE_CONFIG = 0x260C, 87 REG_UFS_MEM_ICE_NUM_CORE = 0x2664, 88 89 REG_UFS_CFG3 = 0x271C, 90 91 REG_UFS_DEBUG_SPARE_CFG = 0x284C, 92 }; 93 94 /* QCOM UFS host controller vendor specific debug registers */ 95 enum { 96 UFS_DBG_RD_REG_UAWM = 0x100, 97 UFS_DBG_RD_REG_UARM = 0x200, 98 UFS_DBG_RD_REG_TXUC = 0x300, 99 UFS_DBG_RD_REG_RXUC = 0x400, 100 UFS_DBG_RD_REG_DFC = 0x500, 101 UFS_DBG_RD_REG_TRLUT = 0x600, 102 UFS_DBG_RD_REG_TMRLUT = 0x700, 103 UFS_UFS_DBG_RD_REG_OCSC = 0x800, 104 105 UFS_UFS_DBG_RD_DESC_RAM = 0x1500, 106 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700, 107 UFS_UFS_DBG_RD_RESP_RAM = 0x1800, 108 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900, 109 }; 110 111 /* QCOM UFS HC vendor specific Hibern8 count registers */ 112 enum { 113 REG_UFS_HW_H8_ENTER_CNT = 0x2700, 114 REG_UFS_SW_H8_ENTER_CNT = 0x2704, 115 REG_UFS_SW_AFTER_HW_H8_ENTER_CNT = 0x2708, 116 REG_UFS_HW_H8_EXIT_CNT = 0x270C, 117 REG_UFS_SW_H8_EXIT_CNT = 0x2710, 118 }; 119 120 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x) 121 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) 122 123 /* bit definitions for REG_UFS_CFG0 register */ 124 #define QUNIPRO_G4_SEL BIT(5) 125 126 /* bit definitions for REG_UFS_CFG1 register */ 127 #define QUNIPRO_SEL BIT(0) 128 #define UFS_PHY_SOFT_RESET BIT(1) 129 #define UTP_DBG_RAMS_EN BIT(17) 130 #define TEST_BUS_EN BIT(18) 131 #define TEST_BUS_SEL GENMASK(22, 19) 132 #define UFS_REG_TEST_BUS_EN BIT(30) 133 134 /* bit definitions for REG_UFS_CFG2 register */ 135 #define UAWM_HW_CGC_EN BIT(0) 136 #define UARM_HW_CGC_EN BIT(1) 137 #define TXUC_HW_CGC_EN BIT(2) 138 #define RXUC_HW_CGC_EN BIT(3) 139 #define DFC_HW_CGC_EN BIT(4) 140 #define TRLUT_HW_CGC_EN BIT(5) 141 #define TMRLUT_HW_CGC_EN BIT(6) 142 #define OCSC_HW_CGC_EN BIT(7) 143 144 /* bit definitions for REG_UFS_CFG3 register */ 145 #define ESI_VEC_MASK GENMASK(22, 12) 146 147 /* bit definitions for REG_UFS_PARAM0 */ 148 #define MAX_HS_GEAR_MASK GENMASK(6, 4) 149 #define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) 150 151 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ 152 #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */ 153 154 /* bit definition for UFS Shared ICE config */ 155 #define UFS_QCOM_CAP_ICE_CONFIG BIT(0) 156 157 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ 158 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ 159 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\ 160 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) 161 162 /* QUniPro Vendor specific attributes */ 163 #define PA_TX_HSG1_SYNC_LENGTH 0x1552 164 #define PA_VS_CONFIG_REG1 0x9000 165 #define DME_VS_CORE_CLK_CTRL 0xD002 166 #define TX_HS_EQUALIZER 0x0037 167 168 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ 169 #define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16) 170 #define CLK_1US_CYCLES_MASK GENMASK(7, 0) 171 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) 172 #define PA_VS_CORE_CLK_40NS_CYCLES 0x9007 173 #define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0) 174 175 176 /* QCOM UFS host controller core clk frequencies */ 177 #define UNIPRO_CORE_CLK_FREQ_37_5_MHZ 38 178 #define UNIPRO_CORE_CLK_FREQ_75_MHZ 75 179 #define UNIPRO_CORE_CLK_FREQ_100_MHZ 100 180 #define UNIPRO_CORE_CLK_FREQ_150_MHZ 150 181 #define UNIPRO_CORE_CLK_FREQ_300_MHZ 300 182 #define UNIPRO_CORE_CLK_FREQ_201_5_MHZ 202 183 #define UNIPRO_CORE_CLK_FREQ_403_MHZ 403 184 185 /* TX_HSG1_SYNC_LENGTH attr value */ 186 #define PA_TX_HSG1_SYNC_LENGTH_VAL 0x4A 187 188 /* 189 * Some ufs device vendors need a different TSync length. 190 * Enable this quirk to give an additional TX_HS_SYNC_LENGTH. 191 */ 192 #define UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH BIT(16) 193 194 /* 195 * Some ufs device vendors need a different Deemphasis setting. 196 * Enable this quirk to tune TX Deemphasis parameters. 197 */ 198 #define UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING BIT(17) 199 200 /* ICE allocator type to share AES engines among TX stream and RX stream */ 201 #define ICE_ALLOCATOR_TYPE 2 202 203 /* 204 * Number of cores allocated for RX stream when Read data block received and 205 * Write data block is not in progress 206 */ 207 #define NUM_RX_R1W0 28 208 209 /* 210 * Number of cores allocated for TX stream when Device asked to send write 211 * data block and Read data block is not in progress 212 */ 213 #define NUM_TX_R0W1 28 214 215 /* 216 * Number of cores allocated for RX stream when Read data block received and 217 * Write data block is in progress 218 * OR 219 * Device asked to send write data block and Read data block is in progress 220 */ 221 #define NUM_RX_R1W1 15 222 223 /* 224 * Number of cores allocated for TX stream (UFS write) when Read data block 225 * received and Write data block is in progress 226 * OR 227 * Device asked to send write data block and Read data block is in progress 228 */ 229 #define NUM_TX_R1W1 13 230 231 static inline void 232 ufs_qcom_get_controller_revision(struct ufs_hba *hba, 233 u8 *major, u16 *minor, u16 *step) 234 { 235 u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION); 236 237 *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); 238 *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); 239 *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver); 240 }; 241 242 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) 243 { 244 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1); 245 246 /* 247 * Dummy read to ensure the write takes effect before doing any sort 248 * of delay 249 */ 250 ufshcd_readl(hba, REG_UFS_CFG1); 251 } 252 253 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) 254 { 255 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1); 256 257 /* 258 * Dummy read to ensure the write takes effect before doing any sort 259 * of delay 260 */ 261 ufshcd_readl(hba, REG_UFS_CFG1); 262 } 263 264 /* Host controller hardware version: major.minor.step */ 265 struct ufs_hw_version { 266 u16 step; 267 u16 minor; 268 u8 major; 269 }; 270 271 struct ufs_qcom_testbus { 272 u8 select_major; 273 u8 select_minor; 274 }; 275 276 struct gpio_desc; 277 278 struct ufs_qcom_host { 279 struct phy *generic_phy; 280 struct ufs_hba *hba; 281 struct ufs_pa_layer_attr dev_req_params; 282 struct clk_bulk_data *clks; 283 u32 num_clks; 284 bool is_lane_clks_enabled; 285 286 struct icc_path *icc_ddr; 287 struct icc_path *icc_cpu; 288 289 #ifdef CONFIG_SCSI_UFS_CRYPTO 290 struct qcom_ice *ice; 291 #endif 292 u32 caps; 293 void __iomem *dev_ref_clk_ctrl_mmio; 294 bool is_dev_ref_clk_enabled; 295 struct ufs_hw_version hw_ver; 296 297 u32 dev_ref_clk_en_mask; 298 299 struct ufs_qcom_testbus testbus; 300 301 /* Reset control of HCI */ 302 struct reset_control *core_reset; 303 struct reset_controller_dev rcdev; 304 305 struct gpio_desc *device_reset; 306 307 struct ufs_host_params host_params; 308 u32 phy_gear; 309 310 bool esi_enabled; 311 }; 312 313 struct ufs_qcom_drvdata { 314 enum ufshcd_quirks quirks; 315 bool no_phy_retention; 316 }; 317 318 static inline u32 319 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg) 320 { 321 if (host->hw_ver.major <= 0x02) 322 return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg); 323 324 return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg); 325 }; 326 327 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba) 328 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba) 329 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba) 330 #define ceil(freq, div) ((freq) % (div) == 0 ? ((freq)/(div)) : ((freq)/(div) + 1)) 331 332 int ufs_qcom_testbus_config(struct ufs_qcom_host *host); 333 334 #endif /* UFS_QCOM_H_ */ 335