1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef UFS_QCOM_H_ 6 #define UFS_QCOM_H_ 7 8 #include <linux/reset-controller.h> 9 #include <linux/reset.h> 10 #include <soc/qcom/ice.h> 11 #include <ufs/ufshcd.h> 12 13 #define MPHY_TX_FSM_STATE 0x41 14 #define TX_FSM_HIBERN8 0x1 15 #define HBRN8_POLL_TOUT_MS 100 16 #define DEFAULT_CLK_RATE_HZ 1000000 17 #define MAX_SUPP_MAC 64 18 #define MAX_ESI_VEC 32 19 20 #define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) 21 #define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) 22 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0) 23 #define UFS_DEV_VER_MAJOR_MASK GENMASK(7, 4) 24 25 #define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B 26 27 /* bit and mask definitions for PA_VS_CLK_CFG_REG attribute */ 28 #define PA_VS_CLK_CFG_REG 0x9004 29 #define PA_VS_CLK_CFG_REG_MASK GENMASK(8, 0) 30 31 /* bit and mask definitions for DL_VS_CLK_CFG attribute */ 32 #define DL_VS_CLK_CFG 0xA00B 33 #define DL_VS_CLK_CFG_MASK GENMASK(9, 0) 34 #define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9) 35 36 /* QCOM UFS host controller vendor specific registers */ 37 enum { 38 REG_UFS_SYS1CLK_1US = 0xC0, 39 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4, 40 REG_UFS_LOCAL_PORT_ID_REG = 0xC8, 41 REG_UFS_PA_ERR_CODE = 0xCC, 42 /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ 43 REG_UFS_PARAM0 = 0xD0, 44 /* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */ 45 REG_UFS_CFG0 = 0xD8, 46 REG_UFS_CFG1 = 0xDC, 47 REG_UFS_CFG2 = 0xE0, 48 REG_UFS_HW_VERSION = 0xE4, 49 50 UFS_TEST_BUS = 0xE8, 51 UFS_TEST_BUS_CTRL_0 = 0xEC, 52 UFS_TEST_BUS_CTRL_1 = 0xF0, 53 UFS_TEST_BUS_CTRL_2 = 0xF4, 54 UFS_UNIPRO_CFG = 0xF8, 55 56 /* 57 * QCOM UFS host controller vendor specific registers 58 * added in HW Version 3.0.0 59 */ 60 UFS_AH8_CFG = 0xFC, 61 62 UFS_RD_REG_MCQ = 0xD00, 63 64 REG_UFS_MEM_ICE_CONFIG = 0x260C, 65 REG_UFS_MEM_ICE_NUM_CORE = 0x2664, 66 67 REG_UFS_CFG3 = 0x271C, 68 69 REG_UFS_DEBUG_SPARE_CFG = 0x284C, 70 }; 71 72 /* QCOM UFS host controller vendor specific debug registers */ 73 enum { 74 UFS_DBG_RD_REG_UAWM = 0x100, 75 UFS_DBG_RD_REG_UARM = 0x200, 76 UFS_DBG_RD_REG_TXUC = 0x300, 77 UFS_DBG_RD_REG_RXUC = 0x400, 78 UFS_DBG_RD_REG_DFC = 0x500, 79 UFS_DBG_RD_REG_TRLUT = 0x600, 80 UFS_DBG_RD_REG_TMRLUT = 0x700, 81 UFS_UFS_DBG_RD_REG_OCSC = 0x800, 82 83 UFS_UFS_DBG_RD_DESC_RAM = 0x1500, 84 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700, 85 UFS_UFS_DBG_RD_RESP_RAM = 0x1800, 86 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900, 87 }; 88 89 /* QCOM UFS HC vendor specific Hibern8 count registers */ 90 enum { 91 REG_UFS_HW_H8_ENTER_CNT = 0x2700, 92 REG_UFS_SW_H8_ENTER_CNT = 0x2704, 93 REG_UFS_SW_AFTER_HW_H8_ENTER_CNT = 0x2708, 94 REG_UFS_HW_H8_EXIT_CNT = 0x270C, 95 REG_UFS_SW_H8_EXIT_CNT = 0x2710, 96 }; 97 98 enum { 99 UFS_MEM_CQIS_VS = 0x8, 100 }; 101 102 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x) 103 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) 104 105 /* bit definitions for REG_UFS_CFG0 register */ 106 #define QUNIPRO_G4_SEL BIT(5) 107 108 /* bit definitions for REG_UFS_CFG1 register */ 109 #define QUNIPRO_SEL BIT(0) 110 #define UFS_PHY_SOFT_RESET BIT(1) 111 #define UTP_DBG_RAMS_EN BIT(17) 112 #define TEST_BUS_EN BIT(18) 113 #define TEST_BUS_SEL GENMASK(22, 19) 114 #define UFS_REG_TEST_BUS_EN BIT(30) 115 116 /* bit definitions for REG_UFS_CFG2 register */ 117 #define UAWM_HW_CGC_EN BIT(0) 118 #define UARM_HW_CGC_EN BIT(1) 119 #define TXUC_HW_CGC_EN BIT(2) 120 #define RXUC_HW_CGC_EN BIT(3) 121 #define DFC_HW_CGC_EN BIT(4) 122 #define TRLUT_HW_CGC_EN BIT(5) 123 #define TMRLUT_HW_CGC_EN BIT(6) 124 #define OCSC_HW_CGC_EN BIT(7) 125 126 /* bit definitions for REG_UFS_CFG3 register */ 127 #define ESI_VEC_MASK GENMASK(22, 12) 128 129 /* bit definitions for REG_UFS_PARAM0 */ 130 #define MAX_HS_GEAR_MASK GENMASK(6, 4) 131 #define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) 132 133 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ 134 #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */ 135 136 /* bit definition for UFS Shared ICE config */ 137 #define UFS_QCOM_CAP_ICE_CONFIG BIT(0) 138 139 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ 140 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ 141 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\ 142 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) 143 144 /* QUniPro Vendor specific attributes */ 145 #define PA_TX_HSG1_SYNC_LENGTH 0x1552 146 #define PA_VS_CONFIG_REG1 0x9000 147 #define DME_VS_CORE_CLK_CTRL 0xD002 148 #define TX_HS_EQUALIZER 0x0037 149 150 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ 151 #define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16) 152 #define CLK_1US_CYCLES_MASK GENMASK(7, 0) 153 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) 154 #define PA_VS_CORE_CLK_40NS_CYCLES 0x9007 155 #define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0) 156 157 158 /* QCOM UFS host controller core clk frequencies */ 159 #define UNIPRO_CORE_CLK_FREQ_37_5_MHZ 38 160 #define UNIPRO_CORE_CLK_FREQ_75_MHZ 75 161 #define UNIPRO_CORE_CLK_FREQ_100_MHZ 100 162 #define UNIPRO_CORE_CLK_FREQ_150_MHZ 150 163 #define UNIPRO_CORE_CLK_FREQ_300_MHZ 300 164 #define UNIPRO_CORE_CLK_FREQ_201_5_MHZ 202 165 #define UNIPRO_CORE_CLK_FREQ_403_MHZ 403 166 167 /* TX_HSG1_SYNC_LENGTH attr value */ 168 #define PA_TX_HSG1_SYNC_LENGTH_VAL 0x4A 169 170 /* 171 * Some ufs device vendors need a different TSync length. 172 * Enable this quirk to give an additional TX_HS_SYNC_LENGTH. 173 */ 174 #define UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH BIT(16) 175 176 /* 177 * Some ufs device vendors need a different Deemphasis setting. 178 * Enable this quirk to tune TX Deemphasis parameters. 179 */ 180 #define UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING BIT(17) 181 182 /* ICE allocator type to share AES engines among TX stream and RX stream */ 183 #define ICE_ALLOCATOR_TYPE 2 184 185 /* 186 * Number of cores allocated for RX stream when Read data block received and 187 * Write data block is not in progress 188 */ 189 #define NUM_RX_R1W0 28 190 191 /* 192 * Number of cores allocated for TX stream when Device asked to send write 193 * data block and Read data block is not in progress 194 */ 195 #define NUM_TX_R0W1 28 196 197 /* 198 * Number of cores allocated for RX stream when Read data block received and 199 * Write data block is in progress 200 * OR 201 * Device asked to send write data block and Read data block is in progress 202 */ 203 #define NUM_RX_R1W1 15 204 205 /* 206 * Number of cores allocated for TX stream (UFS write) when Read data block 207 * received and Write data block is in progress 208 * OR 209 * Device asked to send write data block and Read data block is in progress 210 */ 211 #define NUM_TX_R1W1 13 212 213 static inline void 214 ufs_qcom_get_controller_revision(struct ufs_hba *hba, 215 u8 *major, u16 *minor, u16 *step) 216 { 217 u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION); 218 219 *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); 220 *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); 221 *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver); 222 }; 223 224 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) 225 { 226 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1); 227 228 /* 229 * Dummy read to ensure the write takes effect before doing any sort 230 * of delay 231 */ 232 ufshcd_readl(hba, REG_UFS_CFG1); 233 } 234 235 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) 236 { 237 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1); 238 239 /* 240 * Dummy read to ensure the write takes effect before doing any sort 241 * of delay 242 */ 243 ufshcd_readl(hba, REG_UFS_CFG1); 244 } 245 246 /* Host controller hardware version: major.minor.step */ 247 struct ufs_hw_version { 248 u16 step; 249 u16 minor; 250 u8 major; 251 }; 252 253 struct ufs_qcom_testbus { 254 u8 select_major; 255 u8 select_minor; 256 }; 257 258 struct gpio_desc; 259 260 struct ufs_qcom_host { 261 struct phy *generic_phy; 262 struct ufs_hba *hba; 263 struct ufs_pa_layer_attr dev_req_params; 264 struct clk_bulk_data *clks; 265 u32 num_clks; 266 bool is_lane_clks_enabled; 267 268 struct icc_path *icc_ddr; 269 struct icc_path *icc_cpu; 270 271 #ifdef CONFIG_SCSI_UFS_CRYPTO 272 struct qcom_ice *ice; 273 #endif 274 u32 caps; 275 void __iomem *dev_ref_clk_ctrl_mmio; 276 bool is_dev_ref_clk_enabled; 277 struct ufs_hw_version hw_ver; 278 279 u32 dev_ref_clk_en_mask; 280 281 struct ufs_qcom_testbus testbus; 282 283 /* Reset control of HCI */ 284 struct reset_control *core_reset; 285 struct reset_controller_dev rcdev; 286 287 struct gpio_desc *device_reset; 288 289 struct ufs_host_params host_params; 290 u32 phy_gear; 291 292 bool esi_enabled; 293 }; 294 295 struct ufs_qcom_drvdata { 296 enum ufshcd_quirks quirks; 297 bool no_phy_retention; 298 }; 299 300 static inline u32 301 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg) 302 { 303 if (host->hw_ver.major <= 0x02) 304 return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg); 305 306 return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg); 307 }; 308 309 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba) 310 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba) 311 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba) 312 #define ceil(freq, div) ((freq) % (div) == 0 ? ((freq)/(div)) : ((freq)/(div) + 1)) 313 314 int ufs_qcom_testbus_config(struct ufs_qcom_host *host); 315 316 #endif /* UFS_QCOM_H_ */ 317