1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef UFS_QCOM_H_ 6 #define UFS_QCOM_H_ 7 8 #include <linux/reset-controller.h> 9 #include <linux/reset.h> 10 #include <soc/qcom/ice.h> 11 #include <ufs/ufshcd.h> 12 13 #define MPHY_TX_FSM_STATE 0x41 14 #define TX_FSM_HIBERN8 0x1 15 #define HBRN8_POLL_TOUT_MS 100 16 #define DEFAULT_CLK_RATE_HZ 1000000 17 #define MAX_SUPP_MAC 64 18 #define MAX_ESI_VEC 32 19 20 #define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) 21 #define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) 22 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0) 23 #define UFS_DEV_VER_MAJOR_MASK GENMASK(7, 4) 24 25 #define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B 26 27 /* QCOM UFS host controller vendor specific registers */ 28 enum { 29 REG_UFS_SYS1CLK_1US = 0xC0, 30 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4, 31 REG_UFS_LOCAL_PORT_ID_REG = 0xC8, 32 REG_UFS_PA_ERR_CODE = 0xCC, 33 /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ 34 REG_UFS_PARAM0 = 0xD0, 35 /* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */ 36 REG_UFS_CFG0 = 0xD8, 37 REG_UFS_CFG1 = 0xDC, 38 REG_UFS_CFG2 = 0xE0, 39 REG_UFS_HW_VERSION = 0xE4, 40 41 UFS_TEST_BUS = 0xE8, 42 UFS_TEST_BUS_CTRL_0 = 0xEC, 43 UFS_TEST_BUS_CTRL_1 = 0xF0, 44 UFS_TEST_BUS_CTRL_2 = 0xF4, 45 UFS_UNIPRO_CFG = 0xF8, 46 47 /* 48 * QCOM UFS host controller vendor specific registers 49 * added in HW Version 3.0.0 50 */ 51 UFS_AH8_CFG = 0xFC, 52 53 UFS_RD_REG_MCQ = 0xD00, 54 55 REG_UFS_MEM_ICE_CONFIG = 0x260C, 56 REG_UFS_MEM_ICE_NUM_CORE = 0x2664, 57 58 REG_UFS_CFG3 = 0x271C, 59 60 REG_UFS_DEBUG_SPARE_CFG = 0x284C, 61 }; 62 63 /* QCOM UFS host controller vendor specific debug registers */ 64 enum { 65 UFS_DBG_RD_REG_UAWM = 0x100, 66 UFS_DBG_RD_REG_UARM = 0x200, 67 UFS_DBG_RD_REG_TXUC = 0x300, 68 UFS_DBG_RD_REG_RXUC = 0x400, 69 UFS_DBG_RD_REG_DFC = 0x500, 70 UFS_DBG_RD_REG_TRLUT = 0x600, 71 UFS_DBG_RD_REG_TMRLUT = 0x700, 72 UFS_UFS_DBG_RD_REG_OCSC = 0x800, 73 74 UFS_UFS_DBG_RD_DESC_RAM = 0x1500, 75 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700, 76 UFS_UFS_DBG_RD_RESP_RAM = 0x1800, 77 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900, 78 }; 79 80 /* QCOM UFS HC vendor specific Hibern8 count registers */ 81 enum { 82 REG_UFS_HW_H8_ENTER_CNT = 0x2700, 83 REG_UFS_SW_H8_ENTER_CNT = 0x2704, 84 REG_UFS_SW_AFTER_HW_H8_ENTER_CNT = 0x2708, 85 REG_UFS_HW_H8_EXIT_CNT = 0x270C, 86 REG_UFS_SW_H8_EXIT_CNT = 0x2710, 87 }; 88 89 enum { 90 UFS_MEM_CQIS_VS = 0x8, 91 }; 92 93 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x) 94 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) 95 96 /* bit definitions for REG_UFS_CFG0 register */ 97 #define QUNIPRO_G4_SEL BIT(5) 98 99 /* bit definitions for REG_UFS_CFG1 register */ 100 #define QUNIPRO_SEL BIT(0) 101 #define UFS_PHY_SOFT_RESET BIT(1) 102 #define UTP_DBG_RAMS_EN BIT(17) 103 #define TEST_BUS_EN BIT(18) 104 #define TEST_BUS_SEL GENMASK(22, 19) 105 #define UFS_REG_TEST_BUS_EN BIT(30) 106 107 /* bit definitions for REG_UFS_CFG2 register */ 108 #define UAWM_HW_CGC_EN BIT(0) 109 #define UARM_HW_CGC_EN BIT(1) 110 #define TXUC_HW_CGC_EN BIT(2) 111 #define RXUC_HW_CGC_EN BIT(3) 112 #define DFC_HW_CGC_EN BIT(4) 113 #define TRLUT_HW_CGC_EN BIT(5) 114 #define TMRLUT_HW_CGC_EN BIT(6) 115 #define OCSC_HW_CGC_EN BIT(7) 116 117 /* bit definitions for REG_UFS_CFG3 register */ 118 #define ESI_VEC_MASK GENMASK(22, 12) 119 120 /* bit definitions for REG_UFS_PARAM0 */ 121 #define MAX_HS_GEAR_MASK GENMASK(6, 4) 122 #define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) 123 124 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ 125 #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */ 126 127 /* bit definition for UFS Shared ICE config */ 128 #define UFS_QCOM_CAP_ICE_CONFIG BIT(0) 129 130 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ 131 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ 132 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\ 133 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) 134 135 /* QUniPro Vendor specific attributes */ 136 #define PA_TX_HSG1_SYNC_LENGTH 0x1552 137 #define PA_VS_CONFIG_REG1 0x9000 138 #define DME_VS_CORE_CLK_CTRL 0xD002 139 #define TX_HS_EQUALIZER 0x0037 140 141 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ 142 #define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16) 143 #define CLK_1US_CYCLES_MASK GENMASK(7, 0) 144 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) 145 #define PA_VS_CORE_CLK_40NS_CYCLES 0x9007 146 #define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0) 147 148 149 /* QCOM UFS host controller core clk frequencies */ 150 #define UNIPRO_CORE_CLK_FREQ_37_5_MHZ 38 151 #define UNIPRO_CORE_CLK_FREQ_75_MHZ 75 152 #define UNIPRO_CORE_CLK_FREQ_100_MHZ 100 153 #define UNIPRO_CORE_CLK_FREQ_150_MHZ 150 154 #define UNIPRO_CORE_CLK_FREQ_300_MHZ 300 155 #define UNIPRO_CORE_CLK_FREQ_201_5_MHZ 202 156 #define UNIPRO_CORE_CLK_FREQ_403_MHZ 403 157 158 /* TX_HSG1_SYNC_LENGTH attr value */ 159 #define PA_TX_HSG1_SYNC_LENGTH_VAL 0x4A 160 161 /* 162 * Some ufs device vendors need a different TSync length. 163 * Enable this quirk to give an additional TX_HS_SYNC_LENGTH. 164 */ 165 #define UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH BIT(16) 166 167 /* 168 * Some ufs device vendors need a different Deemphasis setting. 169 * Enable this quirk to tune TX Deemphasis parameters. 170 */ 171 #define UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING BIT(17) 172 173 /* ICE allocator type to share AES engines among TX stream and RX stream */ 174 #define ICE_ALLOCATOR_TYPE 2 175 176 /* 177 * Number of cores allocated for RX stream when Read data block received and 178 * Write data block is not in progress 179 */ 180 #define NUM_RX_R1W0 28 181 182 /* 183 * Number of cores allocated for TX stream when Device asked to send write 184 * data block and Read data block is not in progress 185 */ 186 #define NUM_TX_R0W1 28 187 188 /* 189 * Number of cores allocated for RX stream when Read data block received and 190 * Write data block is in progress 191 * OR 192 * Device asked to send write data block and Read data block is in progress 193 */ 194 #define NUM_RX_R1W1 15 195 196 /* 197 * Number of cores allocated for TX stream (UFS write) when Read data block 198 * received and Write data block is in progress 199 * OR 200 * Device asked to send write data block and Read data block is in progress 201 */ 202 #define NUM_TX_R1W1 13 203 204 static inline void 205 ufs_qcom_get_controller_revision(struct ufs_hba *hba, 206 u8 *major, u16 *minor, u16 *step) 207 { 208 u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION); 209 210 *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); 211 *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); 212 *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver); 213 }; 214 215 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) 216 { 217 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1); 218 219 /* 220 * Dummy read to ensure the write takes effect before doing any sort 221 * of delay 222 */ 223 ufshcd_readl(hba, REG_UFS_CFG1); 224 } 225 226 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) 227 { 228 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1); 229 230 /* 231 * Dummy read to ensure the write takes effect before doing any sort 232 * of delay 233 */ 234 ufshcd_readl(hba, REG_UFS_CFG1); 235 } 236 237 /* Host controller hardware version: major.minor.step */ 238 struct ufs_hw_version { 239 u16 step; 240 u16 minor; 241 u8 major; 242 }; 243 244 struct ufs_qcom_testbus { 245 u8 select_major; 246 u8 select_minor; 247 }; 248 249 struct gpio_desc; 250 251 struct ufs_qcom_host { 252 struct phy *generic_phy; 253 struct ufs_hba *hba; 254 struct ufs_pa_layer_attr dev_req_params; 255 struct clk_bulk_data *clks; 256 u32 num_clks; 257 bool is_lane_clks_enabled; 258 259 struct icc_path *icc_ddr; 260 struct icc_path *icc_cpu; 261 262 #ifdef CONFIG_SCSI_UFS_CRYPTO 263 struct qcom_ice *ice; 264 #endif 265 u32 caps; 266 void __iomem *dev_ref_clk_ctrl_mmio; 267 bool is_dev_ref_clk_enabled; 268 struct ufs_hw_version hw_ver; 269 270 u32 dev_ref_clk_en_mask; 271 272 struct ufs_qcom_testbus testbus; 273 274 /* Reset control of HCI */ 275 struct reset_control *core_reset; 276 struct reset_controller_dev rcdev; 277 278 struct gpio_desc *device_reset; 279 280 struct ufs_host_params host_params; 281 u32 phy_gear; 282 283 bool esi_enabled; 284 }; 285 286 struct ufs_qcom_drvdata { 287 enum ufshcd_quirks quirks; 288 bool no_phy_retention; 289 }; 290 291 static inline u32 292 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg) 293 { 294 if (host->hw_ver.major <= 0x02) 295 return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg); 296 297 return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg); 298 }; 299 300 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba) 301 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba) 302 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba) 303 #define ceil(freq, div) ((freq) % (div) == 0 ? ((freq)/(div)) : ((freq)/(div) + 1)) 304 305 int ufs_qcom_testbus_config(struct ufs_qcom_host *host); 306 307 #endif /* UFS_QCOM_H_ */ 308