1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/clk.h> 8 #include <linux/cleanup.h> 9 #include <linux/delay.h> 10 #include <linux/devfreq.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/interconnect.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/reset-controller.h> 18 #include <linux/time.h> 19 #include <linux/unaligned.h> 20 #include <linux/units.h> 21 22 #include <soc/qcom/ice.h> 23 24 #include <ufs/ufshcd.h> 25 #include <ufs/ufshci.h> 26 #include <ufs/ufs_quirks.h> 27 #include <ufs/unipro.h> 28 #include "ufshcd-pltfrm.h" 29 #include "ufs-qcom.h" 30 31 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 32 #define MCQ_QCFGPTR_UNIT 0x200 33 #define MCQ_SQATTR_OFFSET(c) \ 34 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 35 #define MCQ_QCFG_SIZE 0x40 36 37 /* De-emphasis for gear-5 */ 38 #define DEEMPHASIS_3_5_dB 0x04 39 #define NO_DEEMPHASIS 0x0 40 41 enum { 42 TSTBUS_UAWM, 43 TSTBUS_UARM, 44 TSTBUS_TXUC, 45 TSTBUS_RXUC, 46 TSTBUS_DFC, 47 TSTBUS_TRLUT, 48 TSTBUS_TMRLUT, 49 TSTBUS_OCSC, 50 TSTBUS_UTP_HCI, 51 TSTBUS_COMBINED, 52 TSTBUS_WRAPPER, 53 TSTBUS_UNIPRO, 54 TSTBUS_MAX, 55 }; 56 57 #define QCOM_UFS_MAX_GEAR 5 58 #define QCOM_UFS_MAX_LANE 2 59 60 enum { 61 MODE_MIN, 62 MODE_PWM, 63 MODE_HS_RA, 64 MODE_HS_RB, 65 MODE_MAX, 66 }; 67 68 static const struct __ufs_qcom_bw_table { 69 u32 mem_bw; 70 u32 cfg_bw; 71 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 72 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 73 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 74 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 75 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 76 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 77 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 }, 78 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 79 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 80 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 81 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 82 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 }, 83 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 84 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 85 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 86 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 87 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 88 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 89 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 90 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 91 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 92 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 93 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 94 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 95 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 96 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 97 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 98 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 99 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 100 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 101 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 102 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 103 [MODE_MAX][0][0] = { 7643136, 819200 }, 104 }; 105 106 static const struct { 107 int nminor; 108 char *prefix; 109 } testbus_info[TSTBUS_MAX] = { 110 [TSTBUS_UAWM] = {32, "TSTBUS_UAWM"}, 111 [TSTBUS_UARM] = {32, "TSTBUS_UARM"}, 112 [TSTBUS_TXUC] = {32, "TSTBUS_TXUC"}, 113 [TSTBUS_RXUC] = {32, "TSTBUS_RXUC"}, 114 [TSTBUS_DFC] = {32, "TSTBUS_DFC"}, 115 [TSTBUS_TRLUT] = {32, "TSTBUS_TRLUT"}, 116 [TSTBUS_TMRLUT] = {32, "TSTBUS_TMRLUT"}, 117 [TSTBUS_OCSC] = {32, "TSTBUS_OCSC"}, 118 [TSTBUS_UTP_HCI] = {32, "TSTBUS_UTP_HCI"}, 119 [TSTBUS_COMBINED] = {32, "TSTBUS_COMBINED"}, 120 [TSTBUS_WRAPPER] = {32, "TSTBUS_WRAPPER"}, 121 [TSTBUS_UNIPRO] = {256, "TSTBUS_UNIPRO"}, 122 }; 123 124 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 125 static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba, 126 unsigned long freq, char *name); 127 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq); 128 129 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 130 { 131 return container_of(rcd, struct ufs_qcom_host, rcdev); 132 } 133 134 #ifdef CONFIG_SCSI_UFS_CRYPTO 135 /** 136 * ufs_qcom_config_ice_allocator() - ICE core allocator configuration 137 * 138 * @host: pointer to qcom specific variant structure. 139 */ 140 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) 141 { 142 struct ufs_hba *hba = host->hba; 143 static const uint8_t val[4] = { NUM_RX_R1W0, NUM_TX_R0W1, NUM_RX_R1W1, NUM_TX_R1W1 }; 144 u32 config; 145 146 if (!(host->caps & UFS_QCOM_CAP_ICE_CONFIG) || 147 !(host->hba->caps & UFSHCD_CAP_CRYPTO)) 148 return; 149 150 config = get_unaligned_le32(val); 151 152 ufshcd_writel(hba, ICE_ALLOCATOR_TYPE, REG_UFS_MEM_ICE_CONFIG); 153 ufshcd_writel(hba, config, REG_UFS_MEM_ICE_NUM_CORE); 154 } 155 156 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 157 { 158 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 159 qcom_ice_enable(host->ice); 160 } 161 162 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops; /* forward decl */ 163 164 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 165 { 166 struct ufs_hba *hba = host->hba; 167 struct blk_crypto_profile *profile = &hba->crypto_profile; 168 struct device *dev = hba->dev; 169 struct qcom_ice *ice; 170 union ufs_crypto_capabilities caps; 171 union ufs_crypto_cap_entry cap; 172 int err; 173 int i; 174 175 ice = devm_of_qcom_ice_get(dev); 176 if (ice == ERR_PTR(-EOPNOTSUPP)) { 177 dev_warn(dev, "Disabling inline encryption support\n"); 178 ice = NULL; 179 } 180 181 if (IS_ERR_OR_NULL(ice)) 182 return PTR_ERR_OR_ZERO(ice); 183 184 host->ice = ice; 185 186 /* Initialize the blk_crypto_profile */ 187 188 caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP)); 189 190 /* The number of keyslots supported is (CFGC+1) */ 191 err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1); 192 if (err) 193 return err; 194 195 profile->ll_ops = ufs_qcom_crypto_ops; 196 profile->max_dun_bytes_supported = 8; 197 profile->key_types_supported = qcom_ice_get_supported_key_type(ice); 198 profile->dev = dev; 199 200 /* 201 * Currently this driver only supports AES-256-XTS. All known versions 202 * of ICE support it, but to be safe make sure it is really declared in 203 * the crypto capability registers. The crypto capability registers 204 * also give the supported data unit size(s). 205 */ 206 for (i = 0; i < caps.num_crypto_cap; i++) { 207 cap.reg_val = cpu_to_le32(ufshcd_readl(hba, 208 REG_UFS_CRYPTOCAP + 209 i * sizeof(__le32))); 210 if (cap.algorithm_id == UFS_CRYPTO_ALG_AES_XTS && 211 cap.key_size == UFS_CRYPTO_KEY_SIZE_256) 212 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |= 213 cap.sdus_mask * 512; 214 } 215 216 hba->caps |= UFSHCD_CAP_CRYPTO; 217 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE; 218 return 0; 219 } 220 221 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 222 { 223 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 224 return qcom_ice_resume(host->ice); 225 226 return 0; 227 } 228 229 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 230 { 231 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 232 return qcom_ice_suspend(host->ice); 233 234 return 0; 235 } 236 237 static int ufs_qcom_ice_keyslot_program(struct blk_crypto_profile *profile, 238 const struct blk_crypto_key *key, 239 unsigned int slot) 240 { 241 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 242 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 243 int err; 244 245 ufshcd_hold(hba); 246 err = qcom_ice_program_key(host->ice, slot, key); 247 ufshcd_release(hba); 248 return err; 249 } 250 251 static int ufs_qcom_ice_keyslot_evict(struct blk_crypto_profile *profile, 252 const struct blk_crypto_key *key, 253 unsigned int slot) 254 { 255 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 256 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 257 int err; 258 259 ufshcd_hold(hba); 260 err = qcom_ice_evict_key(host->ice, slot); 261 ufshcd_release(hba); 262 return err; 263 } 264 265 static int ufs_qcom_ice_derive_sw_secret(struct blk_crypto_profile *profile, 266 const u8 *eph_key, size_t eph_key_size, 267 u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE]) 268 { 269 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 270 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 271 272 return qcom_ice_derive_sw_secret(host->ice, eph_key, eph_key_size, 273 sw_secret); 274 } 275 276 static int ufs_qcom_ice_import_key(struct blk_crypto_profile *profile, 277 const u8 *raw_key, size_t raw_key_size, 278 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 279 { 280 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 281 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 282 283 return qcom_ice_import_key(host->ice, raw_key, raw_key_size, lt_key); 284 } 285 286 static int ufs_qcom_ice_generate_key(struct blk_crypto_profile *profile, 287 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 288 { 289 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 290 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 291 292 return qcom_ice_generate_key(host->ice, lt_key); 293 } 294 295 static int ufs_qcom_ice_prepare_key(struct blk_crypto_profile *profile, 296 const u8 *lt_key, size_t lt_key_size, 297 u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 298 { 299 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 300 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 301 302 return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key); 303 } 304 305 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = { 306 .keyslot_program = ufs_qcom_ice_keyslot_program, 307 .keyslot_evict = ufs_qcom_ice_keyslot_evict, 308 .derive_sw_secret = ufs_qcom_ice_derive_sw_secret, 309 .import_key = ufs_qcom_ice_import_key, 310 .generate_key = ufs_qcom_ice_generate_key, 311 .prepare_key = ufs_qcom_ice_prepare_key, 312 }; 313 314 #else 315 316 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 317 { 318 } 319 320 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 321 { 322 return 0; 323 } 324 325 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 326 { 327 return 0; 328 } 329 330 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 331 { 332 return 0; 333 } 334 335 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) 336 { 337 } 338 339 #endif 340 341 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 342 { 343 if (!host->is_lane_clks_enabled) 344 return; 345 346 clk_bulk_disable_unprepare(host->num_clks, host->clks); 347 348 host->is_lane_clks_enabled = false; 349 } 350 351 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 352 { 353 int err; 354 355 err = clk_bulk_prepare_enable(host->num_clks, host->clks); 356 if (err) 357 return err; 358 359 host->is_lane_clks_enabled = true; 360 361 return 0; 362 } 363 364 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 365 { 366 int err; 367 struct device *dev = host->hba->dev; 368 369 if (has_acpi_companion(dev)) 370 return 0; 371 372 err = devm_clk_bulk_get_all(dev, &host->clks); 373 if (err <= 0) 374 return err; 375 376 host->num_clks = err; 377 378 return 0; 379 } 380 381 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 382 { 383 int err; 384 u32 tx_fsm_val; 385 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 386 387 do { 388 err = ufshcd_dme_get(hba, 389 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 390 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 391 &tx_fsm_val); 392 if (err || tx_fsm_val == TX_FSM_HIBERN8) 393 break; 394 395 /* sleep for max. 200us */ 396 usleep_range(100, 200); 397 } while (time_before(jiffies, timeout)); 398 399 /* 400 * we might have scheduled out for long during polling so 401 * check the state again. 402 */ 403 if (time_after(jiffies, timeout)) 404 err = ufshcd_dme_get(hba, 405 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 406 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 407 &tx_fsm_val); 408 409 if (err) { 410 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 411 __func__, err); 412 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 413 err = tx_fsm_val; 414 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 415 __func__, err); 416 } 417 418 return err; 419 } 420 421 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 422 { 423 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); 424 425 if (host->hw_ver.major >= 0x05) 426 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 427 } 428 429 /* 430 * ufs_qcom_host_reset - reset host controller and PHY 431 */ 432 static int ufs_qcom_host_reset(struct ufs_hba *hba) 433 { 434 int ret; 435 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 436 bool reenable_intr; 437 438 if (!host->core_reset) 439 return 0; 440 441 reenable_intr = hba->is_irq_enabled; 442 ufshcd_disable_irq(hba); 443 444 ret = reset_control_assert(host->core_reset); 445 if (ret) { 446 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 447 __func__, ret); 448 return ret; 449 } 450 451 /* 452 * The hardware requirement for delay between assert/deassert 453 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 454 * ~125us (4/32768). To be on the safe side add 200us delay. 455 */ 456 usleep_range(200, 210); 457 458 ret = reset_control_deassert(host->core_reset); 459 if (ret) { 460 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 461 __func__, ret); 462 return ret; 463 } 464 465 usleep_range(1000, 1100); 466 467 if (reenable_intr) 468 ufshcd_enable_irq(hba); 469 470 return 0; 471 } 472 473 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 474 { 475 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 476 477 if (host->hw_ver.major >= 0x4) 478 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 479 480 /* Default is HS-G3 */ 481 return UFS_HS_G3; 482 } 483 484 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 485 { 486 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 487 struct ufs_host_params *host_params = &host->host_params; 488 struct phy *phy = host->generic_phy; 489 enum phy_mode mode; 490 int ret; 491 492 /* 493 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. 494 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, 495 * so that the subsequent power mode change shall stick to Rate-A. 496 */ 497 if (host->hw_ver.major == 0x5) { 498 if (host->phy_gear == UFS_HS_G5) 499 host_params->hs_rate = PA_HS_MODE_A; 500 else 501 host_params->hs_rate = PA_HS_MODE_B; 502 } 503 504 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; 505 506 /* Reset UFS Host Controller and PHY */ 507 ret = ufs_qcom_host_reset(hba); 508 if (ret) 509 return ret; 510 511 if (phy->power_count) 512 phy_power_off(phy); 513 514 515 /* phy initialization - calibrate the phy */ 516 ret = phy_init(phy); 517 if (ret) { 518 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 519 __func__, ret); 520 return ret; 521 } 522 523 ret = phy_set_mode_ext(phy, mode, host->phy_gear); 524 if (ret) 525 goto out_disable_phy; 526 527 /* power on phy - start serdes and phy's power and clocks */ 528 ret = phy_power_on(phy); 529 if (ret) { 530 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 531 __func__, ret); 532 goto out_disable_phy; 533 } 534 535 ufs_qcom_select_unipro_mode(host); 536 537 return 0; 538 539 out_disable_phy: 540 phy_exit(phy); 541 542 return ret; 543 } 544 545 /* 546 * The UTP controller has a number of internal clock gating cells (CGCs). 547 * Internal hardware sub-modules within the UTP controller control the CGCs. 548 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 549 * in a specific operation, UTP controller CGCs are by default disabled and 550 * this function enables them (after every UFS link startup) to save some power 551 * leakage. 552 */ 553 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 554 { 555 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, 556 REG_UFS_CFG2); 557 558 /* Ensure that HW clock gating is enabled before next operations */ 559 ufshcd_readl(hba, REG_UFS_CFG2); 560 } 561 562 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 563 enum ufs_notify_change_status status) 564 { 565 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 566 int err; 567 568 switch (status) { 569 case PRE_CHANGE: 570 err = ufs_qcom_power_up_sequence(hba); 571 if (err) 572 return err; 573 574 /* 575 * The PHY PLL output is the source of tx/rx lane symbol 576 * clocks, hence, enable the lane clocks only after PHY 577 * is initialized. 578 */ 579 err = ufs_qcom_enable_lane_clks(host); 580 break; 581 case POST_CHANGE: 582 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 583 err = ufs_qcom_check_hibern8(hba); 584 ufs_qcom_enable_hw_clk_gating(hba); 585 ufs_qcom_ice_enable(host); 586 ufs_qcom_config_ice_allocator(host); 587 break; 588 default: 589 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 590 err = -EINVAL; 591 break; 592 } 593 return err; 594 } 595 596 /** 597 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers 598 * 599 * @hba: host controller instance 600 * @is_pre_scale_up: flag to check if pre scale up condition. 601 * @freq: target opp freq 602 * Return: zero for success and non-zero in case of a failure. 603 */ 604 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsigned long freq) 605 { 606 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 607 struct ufs_clk_info *clki; 608 unsigned long clk_freq = 0; 609 u32 core_clk_cycles_per_us; 610 611 /* 612 * UTP controller uses SYS1CLK_1US_REG register for Interrupt 613 * Aggregation logic. 614 * It is mandatory to write SYS1CLK_1US_REG register on UFS host 615 * controller V4.0.0 onwards. 616 */ 617 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) 618 return 0; 619 620 if (hba->use_pm_opp && freq != ULONG_MAX) { 621 clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk"); 622 if (clk_freq) 623 goto cfg_timers; 624 } 625 626 list_for_each_entry(clki, &hba->clk_list_head, list) { 627 if (!strcmp(clki->name, "core_clk")) { 628 if (freq == ULONG_MAX) { 629 clk_freq = clki->max_freq; 630 break; 631 } 632 633 if (is_pre_scale_up) 634 clk_freq = clki->max_freq; 635 else 636 clk_freq = clk_get_rate(clki->clk); 637 break; 638 } 639 640 } 641 642 cfg_timers: 643 /* If frequency is smaller than 1MHz, set to 1MHz */ 644 if (clk_freq < DEFAULT_CLK_RATE_HZ) 645 clk_freq = DEFAULT_CLK_RATE_HZ; 646 647 core_clk_cycles_per_us = clk_freq / USEC_PER_SEC; 648 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 649 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 650 /* 651 * make sure above write gets applied before we return from 652 * this function. 653 */ 654 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US); 655 } 656 657 return 0; 658 } 659 660 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 661 enum ufs_notify_change_status status) 662 { 663 int err = 0; 664 665 switch (status) { 666 case PRE_CHANGE: 667 if (ufs_qcom_cfg_timers(hba, false, ULONG_MAX)) { 668 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 669 __func__); 670 return -EINVAL; 671 } 672 673 err = ufs_qcom_set_core_clk_ctrl(hba, true, ULONG_MAX); 674 if (err) 675 dev_err(hba->dev, "cfg core clk ctrl failed\n"); 676 /* 677 * Some UFS devices (and may be host) have issues if LCC is 678 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 679 * before link startup which will make sure that both host 680 * and device TX LCC are disabled once link startup is 681 * completed. 682 */ 683 err = ufshcd_disable_host_tx_lcc(hba); 684 685 break; 686 default: 687 break; 688 } 689 690 return err; 691 } 692 693 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 694 { 695 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 696 697 /* reset gpio is optional */ 698 if (!host->device_reset) 699 return; 700 701 gpiod_set_value_cansleep(host->device_reset, asserted); 702 } 703 704 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 705 enum ufs_notify_change_status status) 706 { 707 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 708 struct phy *phy = host->generic_phy; 709 710 if (status == PRE_CHANGE) 711 return 0; 712 713 if (ufs_qcom_is_link_off(hba)) { 714 /* 715 * Disable the tx/rx lane symbol clocks before PHY is 716 * powered down as the PLL source should be disabled 717 * after downstream clocks are disabled. 718 */ 719 ufs_qcom_disable_lane_clks(host); 720 phy_power_off(phy); 721 722 /* reset the connected UFS device during power down */ 723 ufs_qcom_device_reset_ctrl(hba, true); 724 725 } else if (!ufs_qcom_is_link_active(hba)) { 726 ufs_qcom_disable_lane_clks(host); 727 } 728 729 return ufs_qcom_ice_suspend(host); 730 } 731 732 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 733 { 734 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 735 struct phy *phy = host->generic_phy; 736 int err; 737 738 if (ufs_qcom_is_link_off(hba)) { 739 err = phy_power_on(phy); 740 if (err) { 741 dev_err(hba->dev, "%s: failed PHY power on: %d\n", 742 __func__, err); 743 return err; 744 } 745 746 err = ufs_qcom_enable_lane_clks(host); 747 if (err) 748 return err; 749 750 } else if (!ufs_qcom_is_link_active(hba)) { 751 err = ufs_qcom_enable_lane_clks(host); 752 if (err) 753 return err; 754 } 755 756 return ufs_qcom_ice_resume(host); 757 } 758 759 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 760 { 761 if (host->dev_ref_clk_ctrl_mmio && 762 (enable ^ host->is_dev_ref_clk_enabled)) { 763 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 764 765 if (enable) 766 temp |= host->dev_ref_clk_en_mask; 767 else 768 temp &= ~host->dev_ref_clk_en_mask; 769 770 /* 771 * If we are here to disable this clock it might be immediately 772 * after entering into hibern8 in which case we need to make 773 * sure that device ref_clk is active for specific time after 774 * hibern8 enter. 775 */ 776 if (!enable) { 777 unsigned long gating_wait; 778 779 gating_wait = host->hba->dev_info.clk_gating_wait_us; 780 if (!gating_wait) { 781 udelay(1); 782 } else { 783 /* 784 * bRefClkGatingWaitTime defines the minimum 785 * time for which the reference clock is 786 * required by device during transition from 787 * HS-MODE to LS-MODE or HIBERN8 state. Give it 788 * more delay to be on the safe side. 789 */ 790 gating_wait += 10; 791 usleep_range(gating_wait, gating_wait + 10); 792 } 793 } 794 795 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 796 797 /* 798 * Make sure the write to ref_clk reaches the destination and 799 * not stored in a Write Buffer (WB). 800 */ 801 readl(host->dev_ref_clk_ctrl_mmio); 802 803 /* 804 * If we call hibern8 exit after this, we need to make sure that 805 * device ref_clk is stable for at least 1us before the hibern8 806 * exit command. 807 */ 808 if (enable) 809 udelay(1); 810 811 host->is_dev_ref_clk_enabled = enable; 812 } 813 } 814 815 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 816 { 817 struct device *dev = host->hba->dev; 818 int ret; 819 820 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 821 if (ret < 0) { 822 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 823 return ret; 824 } 825 826 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 827 if (ret < 0) { 828 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 829 return ret; 830 } 831 832 return 0; 833 } 834 835 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 836 { 837 struct ufs_pa_layer_attr *p = &host->dev_req_params; 838 int gear = max_t(u32, p->gear_rx, p->gear_tx); 839 int lane = max_t(u32, p->lane_rx, p->lane_tx); 840 841 if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR, 842 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n", 843 gear, QCOM_UFS_MAX_GEAR)) 844 gear = QCOM_UFS_MAX_GEAR; 845 846 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE, 847 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n", 848 lane, QCOM_UFS_MAX_LANE)) 849 lane = QCOM_UFS_MAX_LANE; 850 851 if (ufshcd_is_hs_mode(p)) { 852 if (p->hs_rate == PA_HS_MODE_B) 853 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 854 else 855 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 856 } else { 857 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 858 } 859 } 860 861 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 862 { 863 struct __ufs_qcom_bw_table bw_table; 864 865 bw_table = ufs_qcom_get_bw_table(host); 866 867 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 868 } 869 870 static void ufs_qcom_set_tx_hs_equalizer(struct ufs_hba *hba, u32 gear, u32 tx_lanes) 871 { 872 u32 equalizer_val; 873 int ret, i; 874 875 /* Determine the equalizer value based on the gear */ 876 equalizer_val = (gear == 5) ? DEEMPHASIS_3_5_dB : NO_DEEMPHASIS; 877 878 for (i = 0; i < tx_lanes; i++) { 879 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HS_EQUALIZER, i), 880 equalizer_val); 881 if (ret) 882 dev_err(hba->dev, "%s: failed equalizer lane %d\n", 883 __func__, i); 884 } 885 } 886 887 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 888 enum ufs_notify_change_status status, 889 const struct ufs_pa_layer_attr *dev_max_params, 890 struct ufs_pa_layer_attr *dev_req_params) 891 { 892 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 893 struct ufs_host_params *host_params = &host->host_params; 894 int ret = 0; 895 896 if (!dev_req_params) { 897 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 898 return -EINVAL; 899 } 900 901 switch (status) { 902 case PRE_CHANGE: 903 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); 904 if (ret) { 905 dev_err(hba->dev, "%s: failed to determine capabilities\n", 906 __func__); 907 return ret; 908 } 909 910 /* 911 * During UFS driver probe, always update the PHY gear to match the negotiated 912 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled, 913 * the second init can program the optimal PHY settings. This allows one to start 914 * the first init with either the minimum or the maximum support gear. 915 */ 916 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { 917 /* 918 * Skip REINIT if the negotiated gear matches with the 919 * initial phy_gear. Otherwise, update the phy_gear to 920 * program the optimal gear setting during REINIT. 921 */ 922 if (host->phy_gear == dev_req_params->gear_tx) 923 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 924 else 925 host->phy_gear = dev_req_params->gear_tx; 926 } 927 928 /* enable the device ref clock before changing to HS mode */ 929 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 930 ufshcd_is_hs_mode(dev_req_params)) 931 ufs_qcom_dev_ref_clk_ctrl(host, true); 932 933 if (host->hw_ver.major >= 0x4) { 934 ufshcd_dme_configure_adapt(hba, 935 dev_req_params->gear_tx, 936 PA_INITIAL_ADAPT); 937 } 938 939 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING) 940 ufs_qcom_set_tx_hs_equalizer(hba, 941 dev_req_params->gear_tx, dev_req_params->lane_tx); 942 943 break; 944 case POST_CHANGE: 945 /* cache the power mode parameters to use internally */ 946 memcpy(&host->dev_req_params, 947 dev_req_params, sizeof(*dev_req_params)); 948 949 ufs_qcom_icc_update_bw(host); 950 951 /* disable the device ref clock if entered PWM mode */ 952 if (ufshcd_is_hs_mode(&hba->pwr_info) && 953 !ufshcd_is_hs_mode(dev_req_params)) 954 ufs_qcom_dev_ref_clk_ctrl(host, false); 955 break; 956 default: 957 ret = -EINVAL; 958 break; 959 } 960 961 return ret; 962 } 963 964 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 965 { 966 int err; 967 u32 pa_vs_config_reg1; 968 969 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 970 &pa_vs_config_reg1); 971 if (err) 972 return err; 973 974 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 975 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 976 (pa_vs_config_reg1 | (1 << 12))); 977 } 978 979 static void ufs_qcom_override_pa_tx_hsg1_sync_len(struct ufs_hba *hba) 980 { 981 int err; 982 983 err = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TX_HSG1_SYNC_LENGTH), 984 PA_TX_HSG1_SYNC_LENGTH_VAL); 985 if (err) 986 dev_err(hba->dev, "Failed (%d) set PA_TX_HSG1_SYNC_LENGTH\n", err); 987 } 988 989 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 990 { 991 int err = 0; 992 993 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 994 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 995 996 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH) 997 ufs_qcom_override_pa_tx_hsg1_sync_len(hba); 998 999 return err; 1000 } 1001 1002 /* UFS device-specific quirks */ 1003 static struct ufs_dev_quirk ufs_qcom_dev_fixups[] = { 1004 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 1005 .model = UFS_ANY_MODEL, 1006 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 1007 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 1008 .model = UFS_ANY_MODEL, 1009 .quirk = UFS_DEVICE_QUIRK_DELAY_AFTER_LPM }, 1010 { .wmanufacturerid = UFS_VENDOR_WDC, 1011 .model = UFS_ANY_MODEL, 1012 .quirk = UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE }, 1013 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 1014 .model = UFS_ANY_MODEL, 1015 .quirk = UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH | 1016 UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING }, 1017 {} 1018 }; 1019 1020 static void ufs_qcom_fixup_dev_quirks(struct ufs_hba *hba) 1021 { 1022 ufshcd_fixup_dev_quirks(hba, ufs_qcom_dev_fixups); 1023 } 1024 1025 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 1026 { 1027 return ufshci_version(2, 0); 1028 } 1029 1030 /** 1031 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 1032 * @hba: host controller instance 1033 * 1034 * QCOM UFS host controller might have some non standard behaviours (quirks) 1035 * than what is specified by UFSHCI specification. Advertise all such 1036 * quirks to standard UFS host controller driver so standard takes them into 1037 * account. 1038 */ 1039 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 1040 { 1041 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); 1042 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1043 1044 if (host->hw_ver.major == 0x2) 1045 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 1046 1047 if (host->hw_ver.major > 0x3) 1048 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1049 1050 if (drvdata && drvdata->quirks) 1051 hba->quirks |= drvdata->quirks; 1052 } 1053 1054 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) 1055 { 1056 struct ufs_host_params *host_params = &host->host_params; 1057 u32 val, dev_major; 1058 1059 /* 1060 * Default to powering up the PHY to the max gear possible, which is 1061 * backwards compatible with lower gears but not optimal from 1062 * a power usage point of view. After device negotiation, if the 1063 * gear is lower a reinit will be performed to program the PHY 1064 * to the ideal gear for this combo of controller and device. 1065 */ 1066 host->phy_gear = host_params->hs_tx_gear; 1067 1068 if (host->hw_ver.major < 0x4) { 1069 /* 1070 * These controllers only have one PHY init sequence, 1071 * let's power up the PHY using that (the minimum supported 1072 * gear, UFS_HS_G2). 1073 */ 1074 host->phy_gear = UFS_HS_G2; 1075 } else if (host->hw_ver.major >= 0x5) { 1076 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); 1077 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val); 1078 1079 /* 1080 * Since the UFS device version is populated, let's remove the 1081 * REINIT quirk as the negotiated gear won't change during boot. 1082 * So there is no need to do reinit. 1083 */ 1084 if (dev_major != 0x0) 1085 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1086 1087 /* 1088 * For UFS 3.1 device and older, power up the PHY using HS-G4 1089 * PHY gear to save power. 1090 */ 1091 if (dev_major > 0x0 && dev_major < 0x4) 1092 host->phy_gear = UFS_HS_G4; 1093 } 1094 } 1095 1096 static void ufs_qcom_set_host_params(struct ufs_hba *hba) 1097 { 1098 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1099 struct ufs_host_params *host_params = &host->host_params; 1100 1101 ufshcd_init_host_params(host_params); 1102 1103 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 1104 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); 1105 } 1106 1107 static void ufs_qcom_set_host_caps(struct ufs_hba *hba) 1108 { 1109 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1110 1111 if (host->hw_ver.major >= 0x5) 1112 host->caps |= UFS_QCOM_CAP_ICE_CONFIG; 1113 } 1114 1115 static void ufs_qcom_set_caps(struct ufs_hba *hba) 1116 { 1117 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1118 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 1119 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1120 hba->caps |= UFSHCD_CAP_WB_EN; 1121 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 1122 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 1123 1124 ufs_qcom_set_host_caps(hba); 1125 } 1126 1127 /** 1128 * ufs_qcom_setup_clocks - enables/disable clocks 1129 * @hba: host controller instance 1130 * @on: If true, enable clocks else disable them. 1131 * @status: PRE_CHANGE or POST_CHANGE notify 1132 * 1133 * Return: 0 on success, non-zero on failure. 1134 */ 1135 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 1136 enum ufs_notify_change_status status) 1137 { 1138 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1139 1140 /* 1141 * In case ufs_qcom_init() is not yet done, simply ignore. 1142 * This ufs_qcom_setup_clocks() shall be called from 1143 * ufs_qcom_init() after init is done. 1144 */ 1145 if (!host) 1146 return 0; 1147 1148 switch (status) { 1149 case PRE_CHANGE: 1150 if (on) { 1151 ufs_qcom_icc_update_bw(host); 1152 } else { 1153 if (!ufs_qcom_is_link_active(hba)) { 1154 /* disable device ref_clk */ 1155 ufs_qcom_dev_ref_clk_ctrl(host, false); 1156 } 1157 } 1158 break; 1159 case POST_CHANGE: 1160 if (on) { 1161 /* enable the device ref clock for HS mode*/ 1162 if (ufshcd_is_hs_mode(&hba->pwr_info)) 1163 ufs_qcom_dev_ref_clk_ctrl(host, true); 1164 } else { 1165 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 1166 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 1167 } 1168 break; 1169 } 1170 1171 return 0; 1172 } 1173 1174 static int 1175 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 1176 { 1177 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1178 1179 ufs_qcom_assert_reset(host->hba); 1180 /* provide 1ms delay to let the reset pulse propagate. */ 1181 usleep_range(1000, 1100); 1182 return 0; 1183 } 1184 1185 static int 1186 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 1187 { 1188 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1189 1190 ufs_qcom_deassert_reset(host->hba); 1191 1192 /* 1193 * after reset deassertion, phy will need all ref clocks, 1194 * voltage, current to settle down before starting serdes. 1195 */ 1196 usleep_range(1000, 1100); 1197 return 0; 1198 } 1199 1200 static const struct reset_control_ops ufs_qcom_reset_ops = { 1201 .assert = ufs_qcom_reset_assert, 1202 .deassert = ufs_qcom_reset_deassert, 1203 }; 1204 1205 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 1206 { 1207 struct device *dev = host->hba->dev; 1208 int ret; 1209 1210 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 1211 if (IS_ERR(host->icc_ddr)) 1212 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 1213 "failed to acquire interconnect path\n"); 1214 1215 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1216 if (IS_ERR(host->icc_cpu)) 1217 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1218 "failed to acquire interconnect path\n"); 1219 1220 /* 1221 * Set Maximum bandwidth vote before initializing the UFS controller and 1222 * device. Ideally, a minimal interconnect vote would suffice for the 1223 * initialization, but a max vote would allow faster initialization. 1224 */ 1225 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1226 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1227 if (ret < 0) 1228 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1229 1230 return 0; 1231 } 1232 1233 /** 1234 * ufs_qcom_init - bind phy with controller 1235 * @hba: host controller instance 1236 * 1237 * Binds PHY with controller and powers up PHY enabling clocks 1238 * and regulators. 1239 * 1240 * Return: -EPROBE_DEFER if binding fails, returns negative error 1241 * on phy power up failure and returns zero on success. 1242 */ 1243 static int ufs_qcom_init(struct ufs_hba *hba) 1244 { 1245 int err; 1246 struct device *dev = hba->dev; 1247 struct ufs_qcom_host *host; 1248 struct ufs_clk_info *clki; 1249 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); 1250 1251 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1252 if (!host) 1253 return -ENOMEM; 1254 1255 /* Make a two way bind between the qcom host and the hba */ 1256 host->hba = hba; 1257 ufshcd_set_variant(hba, host); 1258 1259 /* Setup the optional reset control of HCI */ 1260 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1261 if (IS_ERR(host->core_reset)) { 1262 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1263 "Failed to get reset control\n"); 1264 goto out_variant_clear; 1265 } 1266 1267 /* Fire up the reset controller. Failure here is non-fatal. */ 1268 host->rcdev.of_node = dev->of_node; 1269 host->rcdev.ops = &ufs_qcom_reset_ops; 1270 host->rcdev.owner = dev->driver->owner; 1271 host->rcdev.nr_resets = 1; 1272 err = devm_reset_controller_register(dev, &host->rcdev); 1273 if (err) 1274 dev_warn(dev, "Failed to register reset controller\n"); 1275 1276 if (!has_acpi_companion(dev)) { 1277 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1278 if (IS_ERR(host->generic_phy)) { 1279 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1280 goto out_variant_clear; 1281 } 1282 } 1283 1284 err = ufs_qcom_icc_init(host); 1285 if (err) 1286 goto out_variant_clear; 1287 1288 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1289 GPIOD_OUT_HIGH); 1290 if (IS_ERR(host->device_reset)) { 1291 err = dev_err_probe(dev, PTR_ERR(host->device_reset), 1292 "Failed to acquire device reset gpio\n"); 1293 goto out_variant_clear; 1294 } 1295 1296 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1297 &host->hw_ver.minor, &host->hw_ver.step); 1298 1299 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1300 host->dev_ref_clk_en_mask = BIT(26); 1301 1302 list_for_each_entry(clki, &hba->clk_list_head, list) { 1303 if (!strcmp(clki->name, "core_clk_unipro")) 1304 clki->keep_link_active = true; 1305 } 1306 1307 err = ufs_qcom_init_lane_clks(host); 1308 if (err) 1309 goto out_variant_clear; 1310 1311 ufs_qcom_set_caps(hba); 1312 ufs_qcom_advertise_quirks(hba); 1313 ufs_qcom_set_host_params(hba); 1314 ufs_qcom_set_phy_gear(host); 1315 1316 err = ufs_qcom_ice_init(host); 1317 if (err) 1318 goto out_variant_clear; 1319 1320 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1321 1322 ufs_qcom_get_default_testbus_cfg(host); 1323 err = ufs_qcom_testbus_config(host); 1324 if (err) 1325 /* Failure is non-fatal */ 1326 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1327 __func__, err); 1328 1329 if (drvdata && drvdata->no_phy_retention) 1330 hba->spm_lvl = UFS_PM_LVL_5; 1331 1332 return 0; 1333 1334 out_variant_clear: 1335 ufshcd_set_variant(hba, NULL); 1336 1337 return err; 1338 } 1339 1340 static void ufs_qcom_exit(struct ufs_hba *hba) 1341 { 1342 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1343 1344 ufs_qcom_disable_lane_clks(host); 1345 phy_power_off(host->generic_phy); 1346 phy_exit(host->generic_phy); 1347 } 1348 1349 /** 1350 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles 1351 * 1352 * @hba: host controller instance 1353 * @cycles_in_1us: No of cycles in 1us to be configured 1354 * 1355 * Returns error if dme get/set configuration for 40ns fails 1356 * and returns zero on success. 1357 */ 1358 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, 1359 u32 cycles_in_1us) 1360 { 1361 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1362 u32 cycles_in_40ns; 1363 u32 reg; 1364 int err; 1365 1366 /* 1367 * UFS host controller V4.0.0 onwards needs to program 1368 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed 1369 * frequency of unipro core clk of UFS host controller. 1370 */ 1371 if (host->hw_ver.major < 4) 1372 return 0; 1373 1374 /* 1375 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not 1376 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will 1377 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware 1378 * specification expect to be 16. Hence use exact hardware spec 1379 * mandated value for cycles_in_40ns instead of calculating using 1380 * generic formulae. 1381 */ 1382 switch (cycles_in_1us) { 1383 case UNIPRO_CORE_CLK_FREQ_403_MHZ: 1384 cycles_in_40ns = 16; 1385 break; 1386 case UNIPRO_CORE_CLK_FREQ_300_MHZ: 1387 cycles_in_40ns = 12; 1388 break; 1389 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ: 1390 cycles_in_40ns = 8; 1391 break; 1392 case UNIPRO_CORE_CLK_FREQ_150_MHZ: 1393 cycles_in_40ns = 6; 1394 break; 1395 case UNIPRO_CORE_CLK_FREQ_100_MHZ: 1396 cycles_in_40ns = 4; 1397 break; 1398 case UNIPRO_CORE_CLK_FREQ_75_MHZ: 1399 cycles_in_40ns = 3; 1400 break; 1401 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ: 1402 cycles_in_40ns = 2; 1403 break; 1404 default: 1405 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", 1406 cycles_in_1us); 1407 return -EINVAL; 1408 } 1409 1410 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); 1411 if (err) 1412 return err; 1413 1414 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; 1415 reg |= cycles_in_40ns; 1416 1417 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); 1418 } 1419 1420 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq) 1421 { 1422 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1423 struct list_head *head = &hba->clk_list_head; 1424 struct ufs_clk_info *clki; 1425 u32 cycles_in_1us = 0; 1426 u32 core_clk_ctrl_reg; 1427 unsigned long clk_freq; 1428 int err; 1429 1430 if (hba->use_pm_opp && freq != ULONG_MAX) { 1431 clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro"); 1432 if (clk_freq) { 1433 cycles_in_1us = ceil(clk_freq, HZ_PER_MHZ); 1434 goto set_core_clk_ctrl; 1435 } 1436 } 1437 1438 list_for_each_entry(clki, head, list) { 1439 if (!IS_ERR_OR_NULL(clki->clk) && 1440 !strcmp(clki->name, "core_clk_unipro")) { 1441 if (!clki->max_freq) { 1442 cycles_in_1us = 150; /* default for backwards compatibility */ 1443 break; 1444 } 1445 1446 if (freq == ULONG_MAX) { 1447 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); 1448 break; 1449 } 1450 1451 if (is_scale_up) 1452 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); 1453 else 1454 cycles_in_1us = ceil(clk_get_rate(clki->clk), HZ_PER_MHZ); 1455 break; 1456 } 1457 } 1458 1459 set_core_clk_ctrl: 1460 err = ufshcd_dme_get(hba, 1461 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1462 &core_clk_ctrl_reg); 1463 if (err) 1464 return err; 1465 1466 /* Bit mask is different for UFS host controller V4.0.0 onwards */ 1467 if (host->hw_ver.major >= 4) { 1468 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us)) 1469 return -ERANGE; 1470 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4; 1471 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us); 1472 } else { 1473 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us)) 1474 return -ERANGE; 1475 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK; 1476 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); 1477 } 1478 1479 /* Clear CORE_CLK_DIV_EN */ 1480 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1481 1482 err = ufshcd_dme_set(hba, 1483 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1484 core_clk_ctrl_reg); 1485 if (err) 1486 return err; 1487 1488 /* Configure unipro core clk 40ns attribute */ 1489 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); 1490 } 1491 1492 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long freq) 1493 { 1494 int ret; 1495 1496 ret = ufs_qcom_cfg_timers(hba, true, freq); 1497 if (ret) { 1498 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); 1499 return ret; 1500 } 1501 /* set unipro core clock attributes and clear clock divider */ 1502 return ufs_qcom_set_core_clk_ctrl(hba, true, freq); 1503 } 1504 1505 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1506 { 1507 return 0; 1508 } 1509 1510 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1511 { 1512 int err; 1513 u32 core_clk_ctrl_reg; 1514 1515 err = ufshcd_dme_get(hba, 1516 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1517 &core_clk_ctrl_reg); 1518 1519 /* make sure CORE_CLK_DIV_EN is cleared */ 1520 if (!err && 1521 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1522 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1523 err = ufshcd_dme_set(hba, 1524 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1525 core_clk_ctrl_reg); 1526 } 1527 1528 return err; 1529 } 1530 1531 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq) 1532 { 1533 int ret; 1534 1535 ret = ufs_qcom_cfg_timers(hba, false, freq); 1536 if (ret) { 1537 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); 1538 return ret; 1539 } 1540 /* set unipro core clock attributes and clear clock divider */ 1541 return ufs_qcom_set_core_clk_ctrl(hba, false, freq); 1542 } 1543 1544 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, 1545 unsigned long target_freq, 1546 enum ufs_notify_change_status status) 1547 { 1548 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1549 int err; 1550 1551 /* check the host controller state before sending hibern8 cmd */ 1552 if (!ufshcd_is_hba_active(hba)) 1553 return 0; 1554 1555 if (status == PRE_CHANGE) { 1556 err = ufshcd_uic_hibern8_enter(hba); 1557 if (err) 1558 return err; 1559 if (scale_up) 1560 err = ufs_qcom_clk_scale_up_pre_change(hba, target_freq); 1561 else 1562 err = ufs_qcom_clk_scale_down_pre_change(hba); 1563 1564 if (err) { 1565 ufshcd_uic_hibern8_exit(hba); 1566 return err; 1567 } 1568 } else { 1569 if (scale_up) 1570 err = ufs_qcom_clk_scale_up_post_change(hba); 1571 else 1572 err = ufs_qcom_clk_scale_down_post_change(hba, target_freq); 1573 1574 1575 if (err) { 1576 ufshcd_uic_hibern8_exit(hba); 1577 return err; 1578 } 1579 1580 ufs_qcom_icc_update_bw(host); 1581 ufshcd_uic_hibern8_exit(hba); 1582 } 1583 1584 return 0; 1585 } 1586 1587 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1588 { 1589 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1590 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1591 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1592 } 1593 1594 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1595 { 1596 /* provide a legal default configuration */ 1597 host->testbus.select_major = TSTBUS_UNIPRO; 1598 host->testbus.select_minor = 37; 1599 } 1600 1601 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1602 { 1603 if (host->testbus.select_major >= TSTBUS_MAX) { 1604 dev_err(host->hba->dev, 1605 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1606 __func__, host->testbus.select_major); 1607 return false; 1608 } 1609 1610 return true; 1611 } 1612 1613 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1614 { 1615 int reg; 1616 int offset; 1617 u32 mask = TEST_BUS_SUB_SEL_MASK; 1618 1619 if (!host) 1620 return -EINVAL; 1621 1622 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1623 return -EPERM; 1624 1625 switch (host->testbus.select_major) { 1626 case TSTBUS_UAWM: 1627 reg = UFS_TEST_BUS_CTRL_0; 1628 offset = 24; 1629 break; 1630 case TSTBUS_UARM: 1631 reg = UFS_TEST_BUS_CTRL_0; 1632 offset = 16; 1633 break; 1634 case TSTBUS_TXUC: 1635 reg = UFS_TEST_BUS_CTRL_0; 1636 offset = 8; 1637 break; 1638 case TSTBUS_RXUC: 1639 reg = UFS_TEST_BUS_CTRL_0; 1640 offset = 0; 1641 break; 1642 case TSTBUS_DFC: 1643 reg = UFS_TEST_BUS_CTRL_1; 1644 offset = 24; 1645 break; 1646 case TSTBUS_TRLUT: 1647 reg = UFS_TEST_BUS_CTRL_1; 1648 offset = 16; 1649 break; 1650 case TSTBUS_TMRLUT: 1651 reg = UFS_TEST_BUS_CTRL_1; 1652 offset = 8; 1653 break; 1654 case TSTBUS_OCSC: 1655 reg = UFS_TEST_BUS_CTRL_1; 1656 offset = 0; 1657 break; 1658 case TSTBUS_WRAPPER: 1659 reg = UFS_TEST_BUS_CTRL_2; 1660 offset = 16; 1661 break; 1662 case TSTBUS_COMBINED: 1663 reg = UFS_TEST_BUS_CTRL_2; 1664 offset = 8; 1665 break; 1666 case TSTBUS_UTP_HCI: 1667 reg = UFS_TEST_BUS_CTRL_2; 1668 offset = 0; 1669 break; 1670 case TSTBUS_UNIPRO: 1671 reg = UFS_UNIPRO_CFG; 1672 offset = 20; 1673 mask = 0xFFF; 1674 break; 1675 /* 1676 * No need for a default case, since 1677 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 1678 * is legal 1679 */ 1680 } 1681 mask <<= offset; 1682 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 1683 (u32)host->testbus.select_major << 19, 1684 REG_UFS_CFG1); 1685 ufshcd_rmwl(host->hba, mask, 1686 (u32)host->testbus.select_minor << offset, 1687 reg); 1688 ufs_qcom_enable_test_bus(host); 1689 1690 return 0; 1691 } 1692 1693 static void ufs_qcom_dump_testbus(struct ufs_hba *hba) 1694 { 1695 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1696 int i, j, nminor = 0, testbus_len = 0; 1697 u32 *testbus __free(kfree) = NULL; 1698 char *prefix; 1699 1700 testbus = kmalloc_array(256, sizeof(u32), GFP_KERNEL); 1701 if (!testbus) 1702 return; 1703 1704 for (j = 0; j < TSTBUS_MAX; j++) { 1705 nminor = testbus_info[j].nminor; 1706 prefix = testbus_info[j].prefix; 1707 host->testbus.select_major = j; 1708 testbus_len = nminor * sizeof(u32); 1709 for (i = 0; i < nminor; i++) { 1710 host->testbus.select_minor = i; 1711 ufs_qcom_testbus_config(host); 1712 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS); 1713 } 1714 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 1715 16, 4, testbus, testbus_len, false); 1716 } 1717 } 1718 1719 static int ufs_qcom_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1720 const char *prefix, enum ufshcd_res id) 1721 { 1722 u32 *regs __free(kfree) = NULL; 1723 size_t pos; 1724 1725 if (offset % 4 != 0 || len % 4 != 0) 1726 return -EINVAL; 1727 1728 regs = kzalloc(len, GFP_ATOMIC); 1729 if (!regs) 1730 return -ENOMEM; 1731 1732 for (pos = 0; pos < len; pos += 4) 1733 regs[pos / 4] = readl(hba->res[id].base + offset + pos); 1734 1735 print_hex_dump(KERN_ERR, prefix, 1736 len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE, 1737 16, 4, regs, len, false); 1738 1739 return 0; 1740 } 1741 1742 static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba) 1743 { 1744 struct dump_info { 1745 size_t offset; 1746 size_t len; 1747 const char *prefix; 1748 enum ufshcd_res id; 1749 }; 1750 1751 struct dump_info mcq_dumps[] = { 1752 {0x0, 256 * 4, "MCQ HCI-0 ", RES_MCQ}, 1753 {0x400, 256 * 4, "MCQ HCI-1 ", RES_MCQ}, 1754 {0x0, 5 * 4, "MCQ VS-0 ", RES_MCQ_VS}, 1755 {0x0, 256 * 4, "MCQ SQD-0 ", RES_MCQ_SQD}, 1756 {0x400, 256 * 4, "MCQ SQD-1 ", RES_MCQ_SQD}, 1757 {0x800, 256 * 4, "MCQ SQD-2 ", RES_MCQ_SQD}, 1758 {0xc00, 256 * 4, "MCQ SQD-3 ", RES_MCQ_SQD}, 1759 {0x1000, 256 * 4, "MCQ SQD-4 ", RES_MCQ_SQD}, 1760 {0x1400, 256 * 4, "MCQ SQD-5 ", RES_MCQ_SQD}, 1761 {0x1800, 256 * 4, "MCQ SQD-6 ", RES_MCQ_SQD}, 1762 {0x1c00, 256 * 4, "MCQ SQD-7 ", RES_MCQ_SQD}, 1763 }; 1764 1765 for (int i = 0; i < ARRAY_SIZE(mcq_dumps); i++) { 1766 ufs_qcom_dump_regs(hba, mcq_dumps[i].offset, mcq_dumps[i].len, 1767 mcq_dumps[i].prefix, mcq_dumps[i].id); 1768 cond_resched(); 1769 } 1770 } 1771 1772 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 1773 { 1774 u32 reg; 1775 struct ufs_qcom_host *host; 1776 1777 host = ufshcd_get_variant(hba); 1778 1779 dev_err(hba->dev, "HW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_ENTER_CNT)); 1780 dev_err(hba->dev, "HW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_EXIT_CNT)); 1781 1782 dev_err(hba->dev, "SW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_ENTER_CNT)); 1783 dev_err(hba->dev, "SW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_EXIT_CNT)); 1784 1785 dev_err(hba->dev, "SW_AFTER_HW_H8_ENTER_CNT=%d\n", 1786 ufshcd_readl(hba, REG_UFS_SW_AFTER_HW_H8_ENTER_CNT)); 1787 1788 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 1789 "HCI Vendor Specific Registers "); 1790 1791 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 1792 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 1793 1794 reg = ufshcd_readl(hba, REG_UFS_CFG1); 1795 reg |= UTP_DBG_RAMS_EN; 1796 ufshcd_writel(hba, reg, REG_UFS_CFG1); 1797 1798 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 1799 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 1800 1801 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 1802 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 1803 1804 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 1805 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 1806 1807 /* clear bit 17 - UTP_DBG_RAMS_EN */ 1808 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 1809 1810 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 1811 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 1812 1813 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 1814 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 1815 1816 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 1817 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 1818 1819 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 1820 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 1821 1822 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 1823 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 1824 1825 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 1826 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 1827 1828 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 1829 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 1830 1831 if (hba->mcq_enabled) { 1832 reg = ufs_qcom_get_debug_reg_offset(host, UFS_RD_REG_MCQ); 1833 ufshcd_dump_regs(hba, reg, 64 * 4, "HCI MCQ Debug Registers "); 1834 } 1835 1836 /* ensure below dumps occur only in task context due to blocking calls. */ 1837 if (in_task()) { 1838 /* Dump MCQ Host Vendor Specific Registers */ 1839 if (hba->mcq_enabled) 1840 ufs_qcom_dump_mcq_hci_regs(hba); 1841 1842 /* voluntarily yield the CPU as we are dumping too much data */ 1843 ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS "); 1844 cond_resched(); 1845 ufs_qcom_dump_testbus(hba); 1846 } 1847 } 1848 1849 /** 1850 * ufs_qcom_device_reset() - toggle the (optional) device reset line 1851 * @hba: per-adapter instance 1852 * 1853 * Toggles the (optional) reset line to reset the attached device. 1854 */ 1855 static int ufs_qcom_device_reset(struct ufs_hba *hba) 1856 { 1857 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1858 1859 /* reset gpio is optional */ 1860 if (!host->device_reset) 1861 return -EOPNOTSUPP; 1862 1863 /* 1864 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 1865 * be on the safe side. 1866 */ 1867 ufs_qcom_device_reset_ctrl(hba, true); 1868 usleep_range(10, 15); 1869 1870 ufs_qcom_device_reset_ctrl(hba, false); 1871 usleep_range(10, 15); 1872 1873 return 0; 1874 } 1875 1876 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) 1877 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1878 struct devfreq_dev_profile *p, 1879 struct devfreq_simple_ondemand_data *d) 1880 { 1881 p->polling_ms = 60; 1882 p->timer = DEVFREQ_TIMER_DELAYED; 1883 d->upthreshold = 70; 1884 d->downdifferential = 5; 1885 1886 hba->clk_scaling.suspend_on_no_request = true; 1887 } 1888 #else 1889 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1890 struct devfreq_dev_profile *p, 1891 struct devfreq_simple_ondemand_data *data) 1892 { 1893 } 1894 #endif 1895 1896 /* Resources */ 1897 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { 1898 {.name = "ufs_mem",}, 1899 {.name = "mcq",}, 1900 /* Submission Queue DAO */ 1901 {.name = "mcq_sqd",}, 1902 /* Submission Queue Interrupt Status */ 1903 {.name = "mcq_sqis",}, 1904 /* Completion Queue DAO */ 1905 {.name = "mcq_cqd",}, 1906 /* Completion Queue Interrupt Status */ 1907 {.name = "mcq_cqis",}, 1908 /* MCQ vendor specific */ 1909 {.name = "mcq_vs",}, 1910 }; 1911 1912 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 1913 { 1914 struct platform_device *pdev = to_platform_device(hba->dev); 1915 struct ufshcd_res_info *res; 1916 struct resource *res_mem, *res_mcq; 1917 int i, ret; 1918 1919 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); 1920 1921 for (i = 0; i < RES_MAX; i++) { 1922 res = &hba->res[i]; 1923 res->resource = platform_get_resource_byname(pdev, 1924 IORESOURCE_MEM, 1925 res->name); 1926 if (!res->resource) { 1927 dev_info(hba->dev, "Resource %s not provided\n", res->name); 1928 if (i == RES_UFS) 1929 return -ENODEV; 1930 continue; 1931 } else if (i == RES_UFS) { 1932 res_mem = res->resource; 1933 res->base = hba->mmio_base; 1934 continue; 1935 } 1936 1937 res->base = devm_ioremap_resource(hba->dev, res->resource); 1938 if (IS_ERR(res->base)) { 1939 dev_err(hba->dev, "Failed to map res %s, err=%d\n", 1940 res->name, (int)PTR_ERR(res->base)); 1941 ret = PTR_ERR(res->base); 1942 res->base = NULL; 1943 return ret; 1944 } 1945 } 1946 1947 /* MCQ resource provided in DT */ 1948 res = &hba->res[RES_MCQ]; 1949 /* Bail if MCQ resource is provided */ 1950 if (res->base) 1951 goto out; 1952 1953 /* Explicitly allocate MCQ resource from ufs_mem */ 1954 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); 1955 if (!res_mcq) 1956 return -ENOMEM; 1957 1958 res_mcq->start = res_mem->start + 1959 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); 1960 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; 1961 res_mcq->flags = res_mem->flags; 1962 res_mcq->name = "mcq"; 1963 1964 ret = insert_resource(&iomem_resource, res_mcq); 1965 if (ret) { 1966 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", 1967 ret); 1968 return ret; 1969 } 1970 1971 res->base = devm_ioremap_resource(hba->dev, res_mcq); 1972 if (IS_ERR(res->base)) { 1973 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", 1974 (int)PTR_ERR(res->base)); 1975 ret = PTR_ERR(res->base); 1976 goto ioremap_err; 1977 } 1978 1979 out: 1980 hba->mcq_base = res->base; 1981 return 0; 1982 ioremap_err: 1983 res->base = NULL; 1984 remove_resource(res_mcq); 1985 return ret; 1986 } 1987 1988 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 1989 { 1990 struct ufshcd_res_info *mem_res, *sqdao_res; 1991 struct ufshcd_mcq_opr_info_t *opr; 1992 int i; 1993 1994 mem_res = &hba->res[RES_UFS]; 1995 sqdao_res = &hba->res[RES_MCQ_SQD]; 1996 1997 if (!mem_res->base || !sqdao_res->base) 1998 return -EINVAL; 1999 2000 for (i = 0; i < OPR_MAX; i++) { 2001 opr = &hba->mcq_opr[i]; 2002 opr->offset = sqdao_res->resource->start - 2003 mem_res->resource->start + 0x40 * i; 2004 opr->stride = 0x100; 2005 opr->base = sqdao_res->base + 0x40 * i; 2006 } 2007 2008 return 0; 2009 } 2010 2011 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 2012 { 2013 /* Qualcomm HC supports up to 64 */ 2014 return MAX_SUPP_MAC; 2015 } 2016 2017 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 2018 unsigned long *ocqs) 2019 { 2020 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; 2021 2022 if (!mcq_vs_res->base) 2023 return -EINVAL; 2024 2025 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); 2026 2027 return 0; 2028 } 2029 2030 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 2031 { 2032 struct device *dev = msi_desc_to_dev(desc); 2033 struct ufs_hba *hba = dev_get_drvdata(dev); 2034 2035 ufshcd_mcq_config_esi(hba, msg); 2036 } 2037 2038 struct ufs_qcom_irq { 2039 unsigned int irq; 2040 unsigned int idx; 2041 struct ufs_hba *hba; 2042 }; 2043 2044 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 2045 { 2046 struct ufs_qcom_irq *qi = data; 2047 struct ufs_hba *hba = qi->hba; 2048 struct ufs_hw_queue *hwq = &hba->uhq[qi->idx]; 2049 2050 ufshcd_mcq_write_cqis(hba, 0x1, qi->idx); 2051 ufshcd_mcq_poll_cqe_lock(hba, hwq); 2052 2053 return IRQ_HANDLED; 2054 } 2055 2056 static void ufs_qcom_irq_free(struct ufs_qcom_irq *uqi) 2057 { 2058 for (struct ufs_qcom_irq *q = uqi; q->irq; q++) 2059 devm_free_irq(q->hba->dev, q->irq, q->hba); 2060 2061 platform_device_msi_free_irqs_all(uqi->hba->dev); 2062 devm_kfree(uqi->hba->dev, uqi); 2063 } 2064 2065 DEFINE_FREE(ufs_qcom_irq, struct ufs_qcom_irq *, if (_T) ufs_qcom_irq_free(_T)) 2066 2067 static int ufs_qcom_config_esi(struct ufs_hba *hba) 2068 { 2069 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2070 int nr_irqs, ret; 2071 2072 if (host->esi_enabled) 2073 return 0; 2074 2075 /* 2076 * 1. We only handle CQs as of now. 2077 * 2. Poll queues do not need ESI. 2078 */ 2079 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 2080 2081 struct ufs_qcom_irq *qi __free(ufs_qcom_irq) = 2082 devm_kcalloc(hba->dev, nr_irqs, sizeof(*qi), GFP_KERNEL); 2083 if (!qi) 2084 return -ENOMEM; 2085 /* Preset so __free() has a pointer to hba in all error paths */ 2086 qi[0].hba = hba; 2087 2088 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, 2089 ufs_qcom_write_msi_msg); 2090 if (ret) { 2091 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); 2092 return ret; 2093 } 2094 2095 for (int idx = 0; idx < nr_irqs; idx++) { 2096 qi[idx].irq = msi_get_virq(hba->dev, idx); 2097 qi[idx].idx = idx; 2098 qi[idx].hba = hba; 2099 2100 ret = devm_request_irq(hba->dev, qi[idx].irq, ufs_qcom_mcq_esi_handler, 2101 IRQF_SHARED, "qcom-mcq-esi", qi + idx); 2102 if (ret) { 2103 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", 2104 __func__, qi[idx].irq, ret); 2105 qi[idx].irq = 0; 2106 return ret; 2107 } 2108 } 2109 2110 retain_and_null_ptr(qi); 2111 2112 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && 2113 host->hw_ver.step == 0) { 2114 ufshcd_rmwl(hba, ESI_VEC_MASK, FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), 2115 REG_UFS_CFG3); 2116 } 2117 ufshcd_mcq_enable_esi(hba); 2118 host->esi_enabled = true; 2119 return 0; 2120 } 2121 2122 static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba, 2123 unsigned long freq, char *name) 2124 { 2125 struct ufs_clk_info *clki; 2126 struct dev_pm_opp *opp; 2127 unsigned long clk_freq; 2128 int idx = 0; 2129 bool found = false; 2130 2131 opp = dev_pm_opp_find_freq_exact_indexed(hba->dev, freq, 0, true); 2132 if (IS_ERR(opp)) { 2133 dev_err(hba->dev, "Failed to find OPP for exact frequency %lu\n", freq); 2134 return 0; 2135 } 2136 2137 list_for_each_entry(clki, &hba->clk_list_head, list) { 2138 if (!strcmp(clki->name, name)) { 2139 found = true; 2140 break; 2141 } 2142 2143 idx++; 2144 } 2145 2146 if (!found) { 2147 dev_err(hba->dev, "Failed to find clock '%s' in clk list\n", name); 2148 dev_pm_opp_put(opp); 2149 return 0; 2150 } 2151 2152 clk_freq = dev_pm_opp_get_freq_indexed(opp, idx); 2153 2154 dev_pm_opp_put(opp); 2155 2156 return clk_freq; 2157 } 2158 2159 static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) 2160 { 2161 u32 gear = UFS_HS_DONT_CHANGE; 2162 unsigned long unipro_freq; 2163 2164 if (!hba->use_pm_opp) 2165 return gear; 2166 2167 unipro_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro"); 2168 switch (unipro_freq) { 2169 case 403000000: 2170 gear = UFS_HS_G5; 2171 break; 2172 case 300000000: 2173 gear = UFS_HS_G4; 2174 break; 2175 case 201500000: 2176 gear = UFS_HS_G3; 2177 break; 2178 case 150000000: 2179 case 100000000: 2180 gear = UFS_HS_G2; 2181 break; 2182 case 75000000: 2183 case 37500000: 2184 gear = UFS_HS_G1; 2185 break; 2186 default: 2187 dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq); 2188 return UFS_HS_DONT_CHANGE; 2189 } 2190 2191 return min_t(u32, gear, hba->max_pwr_info.info.gear_rx); 2192 } 2193 2194 /* 2195 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 2196 * 2197 * The variant operations configure the necessary controller and PHY 2198 * handshake during initialization. 2199 */ 2200 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 2201 .name = "qcom", 2202 .init = ufs_qcom_init, 2203 .exit = ufs_qcom_exit, 2204 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 2205 .clk_scale_notify = ufs_qcom_clk_scale_notify, 2206 .setup_clocks = ufs_qcom_setup_clocks, 2207 .hce_enable_notify = ufs_qcom_hce_enable_notify, 2208 .link_startup_notify = ufs_qcom_link_startup_notify, 2209 .pwr_change_notify = ufs_qcom_pwr_change_notify, 2210 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 2211 .fixup_dev_quirks = ufs_qcom_fixup_dev_quirks, 2212 .suspend = ufs_qcom_suspend, 2213 .resume = ufs_qcom_resume, 2214 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 2215 .device_reset = ufs_qcom_device_reset, 2216 .config_scaling_param = ufs_qcom_config_scaling_param, 2217 .mcq_config_resource = ufs_qcom_mcq_config_resource, 2218 .get_hba_mac = ufs_qcom_get_hba_mac, 2219 .op_runtime_config = ufs_qcom_op_runtime_config, 2220 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 2221 .config_esi = ufs_qcom_config_esi, 2222 .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, 2223 }; 2224 2225 /** 2226 * ufs_qcom_probe - probe routine of the driver 2227 * @pdev: pointer to Platform device handle 2228 * 2229 * Return: zero for success and non-zero for failure. 2230 */ 2231 static int ufs_qcom_probe(struct platform_device *pdev) 2232 { 2233 int err; 2234 struct device *dev = &pdev->dev; 2235 2236 /* Perform generic probe */ 2237 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); 2238 if (err) 2239 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 2240 2241 return 0; 2242 } 2243 2244 /** 2245 * ufs_qcom_remove - set driver_data of the device to NULL 2246 * @pdev: pointer to platform device handle 2247 * 2248 * Always returns 0 2249 */ 2250 static void ufs_qcom_remove(struct platform_device *pdev) 2251 { 2252 struct ufs_hba *hba = platform_get_drvdata(pdev); 2253 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2254 2255 ufshcd_pltfrm_remove(pdev); 2256 if (host->esi_enabled) 2257 platform_device_msi_free_irqs_all(hba->dev); 2258 } 2259 2260 static const struct ufs_qcom_drvdata ufs_qcom_sm8550_drvdata = { 2261 .quirks = UFSHCD_QUIRK_BROKEN_LSDBS_CAP, 2262 .no_phy_retention = true, 2263 }; 2264 2265 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 2266 { .compatible = "qcom,ufshc" }, 2267 { .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata }, 2268 { .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata }, 2269 {}, 2270 }; 2271 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 2272 2273 #ifdef CONFIG_ACPI 2274 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 2275 { "QCOM24A5" }, 2276 { }, 2277 }; 2278 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 2279 #endif 2280 2281 static const struct dev_pm_ops ufs_qcom_pm_ops = { 2282 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 2283 .prepare = ufshcd_suspend_prepare, 2284 .complete = ufshcd_resume_complete, 2285 #ifdef CONFIG_PM_SLEEP 2286 .suspend = ufshcd_system_suspend, 2287 .resume = ufshcd_system_resume, 2288 .freeze = ufshcd_system_freeze, 2289 .restore = ufshcd_system_restore, 2290 .thaw = ufshcd_system_thaw, 2291 #endif 2292 }; 2293 2294 static struct platform_driver ufs_qcom_pltform = { 2295 .probe = ufs_qcom_probe, 2296 .remove = ufs_qcom_remove, 2297 .driver = { 2298 .name = "ufshcd-qcom", 2299 .pm = &ufs_qcom_pm_ops, 2300 .of_match_table = of_match_ptr(ufs_qcom_of_match), 2301 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 2302 }, 2303 }; 2304 module_platform_driver(ufs_qcom_pltform); 2305 2306 MODULE_DESCRIPTION("Qualcomm UFS host controller driver"); 2307 MODULE_LICENSE("GPL v2"); 2308