1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/devfreq.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/interconnect.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/reset-controller.h> 17 #include <linux/time.h> 18 19 #include <soc/qcom/ice.h> 20 21 #include <ufs/ufshcd.h> 22 #include <ufs/ufshci.h> 23 #include <ufs/ufs_quirks.h> 24 #include <ufs/unipro.h> 25 #include "ufshcd-pltfrm.h" 26 #include "ufs-qcom.h" 27 28 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 29 #define MCQ_QCFGPTR_UNIT 0x200 30 #define MCQ_SQATTR_OFFSET(c) \ 31 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 32 #define MCQ_QCFG_SIZE 0x40 33 34 enum { 35 TSTBUS_UAWM, 36 TSTBUS_UARM, 37 TSTBUS_TXUC, 38 TSTBUS_RXUC, 39 TSTBUS_DFC, 40 TSTBUS_TRLUT, 41 TSTBUS_TMRLUT, 42 TSTBUS_OCSC, 43 TSTBUS_UTP_HCI, 44 TSTBUS_COMBINED, 45 TSTBUS_WRAPPER, 46 TSTBUS_UNIPRO, 47 TSTBUS_MAX, 48 }; 49 50 #define QCOM_UFS_MAX_GEAR 4 51 #define QCOM_UFS_MAX_LANE 2 52 53 enum { 54 MODE_MIN, 55 MODE_PWM, 56 MODE_HS_RA, 57 MODE_HS_RB, 58 MODE_MAX, 59 }; 60 61 static const struct __ufs_qcom_bw_table { 62 u32 mem_bw; 63 u32 cfg_bw; 64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 65 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 66 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 67 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 68 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 69 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 70 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 71 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 72 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 73 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 74 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 75 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 76 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 77 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 78 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 79 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 80 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 81 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 82 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 83 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 84 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 85 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 86 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 87 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 88 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 89 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 90 [MODE_MAX][0][0] = { 7643136, 307200 }, 91 }; 92 93 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 94 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up); 95 96 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 97 { 98 return container_of(rcd, struct ufs_qcom_host, rcdev); 99 } 100 101 #ifdef CONFIG_SCSI_UFS_CRYPTO 102 103 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 104 { 105 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 106 qcom_ice_enable(host->ice); 107 } 108 109 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 110 { 111 struct ufs_hba *hba = host->hba; 112 struct device *dev = hba->dev; 113 struct qcom_ice *ice; 114 115 ice = of_qcom_ice_get(dev); 116 if (ice == ERR_PTR(-EOPNOTSUPP)) { 117 dev_warn(dev, "Disabling inline encryption support\n"); 118 ice = NULL; 119 } 120 121 if (IS_ERR_OR_NULL(ice)) 122 return PTR_ERR_OR_ZERO(ice); 123 124 host->ice = ice; 125 hba->caps |= UFSHCD_CAP_CRYPTO; 126 127 return 0; 128 } 129 130 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 131 { 132 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 133 return qcom_ice_resume(host->ice); 134 135 return 0; 136 } 137 138 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 139 { 140 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 141 return qcom_ice_suspend(host->ice); 142 143 return 0; 144 } 145 146 static int ufs_qcom_ice_program_key(struct ufs_hba *hba, 147 const union ufs_crypto_cfg_entry *cfg, 148 int slot) 149 { 150 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 151 union ufs_crypto_cap_entry cap; 152 bool config_enable = 153 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; 154 155 /* Only AES-256-XTS has been tested so far. */ 156 cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; 157 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || 158 cap.key_size != UFS_CRYPTO_KEY_SIZE_256) 159 return -EOPNOTSUPP; 160 161 if (config_enable) 162 return qcom_ice_program_key(host->ice, 163 QCOM_ICE_CRYPTO_ALG_AES_XTS, 164 QCOM_ICE_CRYPTO_KEY_SIZE_256, 165 cfg->crypto_key, 166 cfg->data_unit_size, slot); 167 else 168 return qcom_ice_evict_key(host->ice, slot); 169 } 170 171 #else 172 173 #define ufs_qcom_ice_program_key NULL 174 175 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 176 { 177 } 178 179 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 180 { 181 return 0; 182 } 183 184 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 185 { 186 return 0; 187 } 188 189 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 190 { 191 return 0; 192 } 193 #endif 194 195 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 196 { 197 if (!host->is_lane_clks_enabled) 198 return; 199 200 clk_bulk_disable_unprepare(host->num_clks, host->clks); 201 202 host->is_lane_clks_enabled = false; 203 } 204 205 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 206 { 207 int err; 208 209 err = clk_bulk_prepare_enable(host->num_clks, host->clks); 210 if (err) 211 return err; 212 213 host->is_lane_clks_enabled = true; 214 215 return 0; 216 } 217 218 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 219 { 220 int err; 221 struct device *dev = host->hba->dev; 222 223 if (has_acpi_companion(dev)) 224 return 0; 225 226 err = devm_clk_bulk_get_all(dev, &host->clks); 227 if (err <= 0) 228 return err; 229 230 host->num_clks = err; 231 232 return 0; 233 } 234 235 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 236 { 237 int err; 238 u32 tx_fsm_val; 239 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 240 241 do { 242 err = ufshcd_dme_get(hba, 243 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 244 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 245 &tx_fsm_val); 246 if (err || tx_fsm_val == TX_FSM_HIBERN8) 247 break; 248 249 /* sleep for max. 200us */ 250 usleep_range(100, 200); 251 } while (time_before(jiffies, timeout)); 252 253 /* 254 * we might have scheduled out for long during polling so 255 * check the state again. 256 */ 257 if (time_after(jiffies, timeout)) 258 err = ufshcd_dme_get(hba, 259 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 260 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 261 &tx_fsm_val); 262 263 if (err) { 264 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 265 __func__, err); 266 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 267 err = tx_fsm_val; 268 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 269 __func__, err); 270 } 271 272 return err; 273 } 274 275 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 276 { 277 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); 278 279 if (host->hw_ver.major >= 0x05) 280 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 281 282 /* make sure above configuration is applied before we return */ 283 mb(); 284 } 285 286 /* 287 * ufs_qcom_host_reset - reset host controller and PHY 288 */ 289 static int ufs_qcom_host_reset(struct ufs_hba *hba) 290 { 291 int ret; 292 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 293 bool reenable_intr; 294 295 if (!host->core_reset) 296 return 0; 297 298 reenable_intr = hba->is_irq_enabled; 299 ufshcd_disable_irq(hba); 300 301 ret = reset_control_assert(host->core_reset); 302 if (ret) { 303 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 304 __func__, ret); 305 return ret; 306 } 307 308 /* 309 * The hardware requirement for delay between assert/deassert 310 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 311 * ~125us (4/32768). To be on the safe side add 200us delay. 312 */ 313 usleep_range(200, 210); 314 315 ret = reset_control_deassert(host->core_reset); 316 if (ret) { 317 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 318 __func__, ret); 319 return ret; 320 } 321 322 usleep_range(1000, 1100); 323 324 if (reenable_intr) 325 ufshcd_enable_irq(hba); 326 327 return 0; 328 } 329 330 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 331 { 332 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 333 334 if (host->hw_ver.major >= 0x4) 335 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 336 337 /* Default is HS-G3 */ 338 return UFS_HS_G3; 339 } 340 341 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 342 { 343 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 344 struct ufs_host_params *host_params = &host->host_params; 345 struct phy *phy = host->generic_phy; 346 enum phy_mode mode; 347 int ret; 348 349 /* 350 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. 351 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, 352 * so that the subsequent power mode change shall stick to Rate-A. 353 */ 354 if (host->hw_ver.major == 0x5) { 355 if (host->phy_gear == UFS_HS_G5) 356 host_params->hs_rate = PA_HS_MODE_A; 357 else 358 host_params->hs_rate = PA_HS_MODE_B; 359 } 360 361 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; 362 363 /* Reset UFS Host Controller and PHY */ 364 ret = ufs_qcom_host_reset(hba); 365 if (ret) 366 return ret; 367 368 /* phy initialization - calibrate the phy */ 369 ret = phy_init(phy); 370 if (ret) { 371 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 372 __func__, ret); 373 return ret; 374 } 375 376 ret = phy_set_mode_ext(phy, mode, host->phy_gear); 377 if (ret) 378 goto out_disable_phy; 379 380 /* power on phy - start serdes and phy's power and clocks */ 381 ret = phy_power_on(phy); 382 if (ret) { 383 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 384 __func__, ret); 385 goto out_disable_phy; 386 } 387 388 ufs_qcom_select_unipro_mode(host); 389 390 return 0; 391 392 out_disable_phy: 393 phy_exit(phy); 394 395 return ret; 396 } 397 398 /* 399 * The UTP controller has a number of internal clock gating cells (CGCs). 400 * Internal hardware sub-modules within the UTP controller control the CGCs. 401 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 402 * in a specific operation, UTP controller CGCs are by default disabled and 403 * this function enables them (after every UFS link startup) to save some power 404 * leakage. 405 */ 406 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 407 { 408 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, 409 REG_UFS_CFG2); 410 411 /* Ensure that HW clock gating is enabled before next operations */ 412 mb(); 413 } 414 415 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 416 enum ufs_notify_change_status status) 417 { 418 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 419 int err; 420 421 switch (status) { 422 case PRE_CHANGE: 423 err = ufs_qcom_power_up_sequence(hba); 424 if (err) 425 return err; 426 427 /* 428 * The PHY PLL output is the source of tx/rx lane symbol 429 * clocks, hence, enable the lane clocks only after PHY 430 * is initialized. 431 */ 432 err = ufs_qcom_enable_lane_clks(host); 433 break; 434 case POST_CHANGE: 435 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 436 err = ufs_qcom_check_hibern8(hba); 437 ufs_qcom_enable_hw_clk_gating(hba); 438 ufs_qcom_ice_enable(host); 439 break; 440 default: 441 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 442 err = -EINVAL; 443 break; 444 } 445 return err; 446 } 447 448 /** 449 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers 450 * 451 * @hba: host controller instance 452 * @gear: Current operating gear 453 * @hs: current power mode 454 * @rate: current operating rate (A or B) 455 * @update_link_startup_timer: indicate if link_start ongoing 456 * @is_pre_scale_up: flag to check if pre scale up condition. 457 * Return: zero for success and non-zero in case of a failure. 458 */ 459 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, 460 u32 hs, u32 rate, bool update_link_startup_timer, 461 bool is_pre_scale_up) 462 { 463 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 464 struct ufs_clk_info *clki; 465 unsigned long core_clk_rate = 0; 466 u32 core_clk_cycles_per_us; 467 468 /* 469 * UTP controller uses SYS1CLK_1US_REG register for Interrupt 470 * Aggregation logic. 471 * It is mandatory to write SYS1CLK_1US_REG register on UFS host 472 * controller V4.0.0 onwards. 473 */ 474 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) 475 return 0; 476 477 if (gear == 0) { 478 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); 479 return -EINVAL; 480 } 481 482 list_for_each_entry(clki, &hba->clk_list_head, list) { 483 if (!strcmp(clki->name, "core_clk")) { 484 if (is_pre_scale_up) 485 core_clk_rate = clki->max_freq; 486 else 487 core_clk_rate = clk_get_rate(clki->clk); 488 break; 489 } 490 491 } 492 493 /* If frequency is smaller than 1MHz, set to 1MHz */ 494 if (core_clk_rate < DEFAULT_CLK_RATE_HZ) 495 core_clk_rate = DEFAULT_CLK_RATE_HZ; 496 497 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; 498 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 499 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 500 /* 501 * make sure above write gets applied before we return from 502 * this function. 503 */ 504 mb(); 505 } 506 507 return 0; 508 } 509 510 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 511 enum ufs_notify_change_status status) 512 { 513 int err = 0; 514 515 switch (status) { 516 case PRE_CHANGE: 517 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, 518 0, true, false)) { 519 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 520 __func__); 521 return -EINVAL; 522 } 523 524 err = ufs_qcom_set_core_clk_ctrl(hba, true); 525 if (err) 526 dev_err(hba->dev, "cfg core clk ctrl failed\n"); 527 /* 528 * Some UFS devices (and may be host) have issues if LCC is 529 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 530 * before link startup which will make sure that both host 531 * and device TX LCC are disabled once link startup is 532 * completed. 533 */ 534 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41) 535 err = ufshcd_disable_host_tx_lcc(hba); 536 537 break; 538 default: 539 break; 540 } 541 542 return err; 543 } 544 545 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 546 { 547 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 548 549 /* reset gpio is optional */ 550 if (!host->device_reset) 551 return; 552 553 gpiod_set_value_cansleep(host->device_reset, asserted); 554 } 555 556 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 557 enum ufs_notify_change_status status) 558 { 559 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 560 struct phy *phy = host->generic_phy; 561 562 if (status == PRE_CHANGE) 563 return 0; 564 565 if (ufs_qcom_is_link_off(hba)) { 566 /* 567 * Disable the tx/rx lane symbol clocks before PHY is 568 * powered down as the PLL source should be disabled 569 * after downstream clocks are disabled. 570 */ 571 ufs_qcom_disable_lane_clks(host); 572 phy_power_off(phy); 573 574 /* reset the connected UFS device during power down */ 575 ufs_qcom_device_reset_ctrl(hba, true); 576 577 } else if (!ufs_qcom_is_link_active(hba)) { 578 ufs_qcom_disable_lane_clks(host); 579 } 580 581 return ufs_qcom_ice_suspend(host); 582 } 583 584 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 585 { 586 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 587 struct phy *phy = host->generic_phy; 588 int err; 589 590 if (ufs_qcom_is_link_off(hba)) { 591 err = phy_power_on(phy); 592 if (err) { 593 dev_err(hba->dev, "%s: failed PHY power on: %d\n", 594 __func__, err); 595 return err; 596 } 597 598 err = ufs_qcom_enable_lane_clks(host); 599 if (err) 600 return err; 601 602 } else if (!ufs_qcom_is_link_active(hba)) { 603 err = ufs_qcom_enable_lane_clks(host); 604 if (err) 605 return err; 606 } 607 608 return ufs_qcom_ice_resume(host); 609 } 610 611 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 612 { 613 if (host->dev_ref_clk_ctrl_mmio && 614 (enable ^ host->is_dev_ref_clk_enabled)) { 615 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 616 617 if (enable) 618 temp |= host->dev_ref_clk_en_mask; 619 else 620 temp &= ~host->dev_ref_clk_en_mask; 621 622 /* 623 * If we are here to disable this clock it might be immediately 624 * after entering into hibern8 in which case we need to make 625 * sure that device ref_clk is active for specific time after 626 * hibern8 enter. 627 */ 628 if (!enable) { 629 unsigned long gating_wait; 630 631 gating_wait = host->hba->dev_info.clk_gating_wait_us; 632 if (!gating_wait) { 633 udelay(1); 634 } else { 635 /* 636 * bRefClkGatingWaitTime defines the minimum 637 * time for which the reference clock is 638 * required by device during transition from 639 * HS-MODE to LS-MODE or HIBERN8 state. Give it 640 * more delay to be on the safe side. 641 */ 642 gating_wait += 10; 643 usleep_range(gating_wait, gating_wait + 10); 644 } 645 } 646 647 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 648 649 /* 650 * Make sure the write to ref_clk reaches the destination and 651 * not stored in a Write Buffer (WB). 652 */ 653 readl(host->dev_ref_clk_ctrl_mmio); 654 655 /* 656 * If we call hibern8 exit after this, we need to make sure that 657 * device ref_clk is stable for at least 1us before the hibern8 658 * exit command. 659 */ 660 if (enable) 661 udelay(1); 662 663 host->is_dev_ref_clk_enabled = enable; 664 } 665 } 666 667 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 668 { 669 struct device *dev = host->hba->dev; 670 int ret; 671 672 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 673 if (ret < 0) { 674 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 675 return ret; 676 } 677 678 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 679 if (ret < 0) { 680 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 681 return ret; 682 } 683 684 return 0; 685 } 686 687 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 688 { 689 struct ufs_pa_layer_attr *p = &host->dev_req_params; 690 int gear = max_t(u32, p->gear_rx, p->gear_tx); 691 int lane = max_t(u32, p->lane_rx, p->lane_tx); 692 693 if (ufshcd_is_hs_mode(p)) { 694 if (p->hs_rate == PA_HS_MODE_B) 695 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 696 else 697 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 698 } else { 699 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 700 } 701 } 702 703 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 704 { 705 struct __ufs_qcom_bw_table bw_table; 706 707 bw_table = ufs_qcom_get_bw_table(host); 708 709 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 710 } 711 712 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 713 enum ufs_notify_change_status status, 714 struct ufs_pa_layer_attr *dev_max_params, 715 struct ufs_pa_layer_attr *dev_req_params) 716 { 717 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 718 struct ufs_host_params *host_params = &host->host_params; 719 int ret = 0; 720 721 if (!dev_req_params) { 722 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 723 return -EINVAL; 724 } 725 726 switch (status) { 727 case PRE_CHANGE: 728 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); 729 if (ret) { 730 dev_err(hba->dev, "%s: failed to determine capabilities\n", 731 __func__); 732 return ret; 733 } 734 735 /* 736 * During UFS driver probe, always update the PHY gear to match the negotiated 737 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled, 738 * the second init can program the optimal PHY settings. This allows one to start 739 * the first init with either the minimum or the maximum support gear. 740 */ 741 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { 742 /* 743 * Skip REINIT if the negotiated gear matches with the 744 * initial phy_gear. Otherwise, update the phy_gear to 745 * program the optimal gear setting during REINIT. 746 */ 747 if (host->phy_gear == dev_req_params->gear_tx) 748 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 749 else 750 host->phy_gear = dev_req_params->gear_tx; 751 } 752 753 /* enable the device ref clock before changing to HS mode */ 754 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 755 ufshcd_is_hs_mode(dev_req_params)) 756 ufs_qcom_dev_ref_clk_ctrl(host, true); 757 758 if (host->hw_ver.major >= 0x4) { 759 ufshcd_dme_configure_adapt(hba, 760 dev_req_params->gear_tx, 761 PA_INITIAL_ADAPT); 762 } 763 break; 764 case POST_CHANGE: 765 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, 766 dev_req_params->pwr_rx, 767 dev_req_params->hs_rate, false, false)) { 768 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 769 __func__); 770 /* 771 * we return error code at the end of the routine, 772 * but continue to configure UFS_PHY_TX_LANE_ENABLE 773 * and bus voting as usual 774 */ 775 ret = -EINVAL; 776 } 777 778 /* cache the power mode parameters to use internally */ 779 memcpy(&host->dev_req_params, 780 dev_req_params, sizeof(*dev_req_params)); 781 782 ufs_qcom_icc_update_bw(host); 783 784 /* disable the device ref clock if entered PWM mode */ 785 if (ufshcd_is_hs_mode(&hba->pwr_info) && 786 !ufshcd_is_hs_mode(dev_req_params)) 787 ufs_qcom_dev_ref_clk_ctrl(host, false); 788 break; 789 default: 790 ret = -EINVAL; 791 break; 792 } 793 794 return ret; 795 } 796 797 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 798 { 799 int err; 800 u32 pa_vs_config_reg1; 801 802 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 803 &pa_vs_config_reg1); 804 if (err) 805 return err; 806 807 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 808 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 809 (pa_vs_config_reg1 | (1 << 12))); 810 } 811 812 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 813 { 814 int err = 0; 815 816 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 817 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 818 819 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) 820 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; 821 822 return err; 823 } 824 825 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 826 { 827 return ufshci_version(2, 0); 828 } 829 830 /** 831 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 832 * @hba: host controller instance 833 * 834 * QCOM UFS host controller might have some non standard behaviours (quirks) 835 * than what is specified by UFSHCI specification. Advertise all such 836 * quirks to standard UFS host controller driver so standard takes them into 837 * account. 838 */ 839 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 840 { 841 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 842 843 if (host->hw_ver.major == 0x2) 844 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 845 846 if (host->hw_ver.major > 0x3) 847 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 848 } 849 850 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) 851 { 852 struct ufs_host_params *host_params = &host->host_params; 853 u32 val, dev_major; 854 855 /* 856 * Default to powering up the PHY to the max gear possible, which is 857 * backwards compatible with lower gears but not optimal from 858 * a power usage point of view. After device negotiation, if the 859 * gear is lower a reinit will be performed to program the PHY 860 * to the ideal gear for this combo of controller and device. 861 */ 862 host->phy_gear = host_params->hs_tx_gear; 863 864 if (host->hw_ver.major < 0x4) { 865 /* 866 * These controllers only have one PHY init sequence, 867 * let's power up the PHY using that (the minimum supported 868 * gear, UFS_HS_G2). 869 */ 870 host->phy_gear = UFS_HS_G2; 871 } else if (host->hw_ver.major >= 0x5) { 872 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); 873 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val); 874 875 /* 876 * Since the UFS device version is populated, let's remove the 877 * REINIT quirk as the negotiated gear won't change during boot. 878 * So there is no need to do reinit. 879 */ 880 if (dev_major != 0x0) 881 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 882 883 /* 884 * For UFS 3.1 device and older, power up the PHY using HS-G4 885 * PHY gear to save power. 886 */ 887 if (dev_major > 0x0 && dev_major < 0x4) 888 host->phy_gear = UFS_HS_G4; 889 } 890 } 891 892 static void ufs_qcom_set_host_params(struct ufs_hba *hba) 893 { 894 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 895 struct ufs_host_params *host_params = &host->host_params; 896 897 ufshcd_init_host_params(host_params); 898 899 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 900 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); 901 } 902 903 static void ufs_qcom_set_caps(struct ufs_hba *hba) 904 { 905 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 906 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 907 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 908 hba->caps |= UFSHCD_CAP_WB_EN; 909 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 910 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 911 } 912 913 /** 914 * ufs_qcom_setup_clocks - enables/disable clocks 915 * @hba: host controller instance 916 * @on: If true, enable clocks else disable them. 917 * @status: PRE_CHANGE or POST_CHANGE notify 918 * 919 * Return: 0 on success, non-zero on failure. 920 */ 921 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 922 enum ufs_notify_change_status status) 923 { 924 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 925 926 /* 927 * In case ufs_qcom_init() is not yet done, simply ignore. 928 * This ufs_qcom_setup_clocks() shall be called from 929 * ufs_qcom_init() after init is done. 930 */ 931 if (!host) 932 return 0; 933 934 switch (status) { 935 case PRE_CHANGE: 936 if (on) { 937 ufs_qcom_icc_update_bw(host); 938 } else { 939 if (!ufs_qcom_is_link_active(hba)) { 940 /* disable device ref_clk */ 941 ufs_qcom_dev_ref_clk_ctrl(host, false); 942 } 943 } 944 break; 945 case POST_CHANGE: 946 if (on) { 947 /* enable the device ref clock for HS mode*/ 948 if (ufshcd_is_hs_mode(&hba->pwr_info)) 949 ufs_qcom_dev_ref_clk_ctrl(host, true); 950 } else { 951 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 952 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 953 } 954 break; 955 } 956 957 return 0; 958 } 959 960 static int 961 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 962 { 963 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 964 965 ufs_qcom_assert_reset(host->hba); 966 /* provide 1ms delay to let the reset pulse propagate. */ 967 usleep_range(1000, 1100); 968 return 0; 969 } 970 971 static int 972 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 973 { 974 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 975 976 ufs_qcom_deassert_reset(host->hba); 977 978 /* 979 * after reset deassertion, phy will need all ref clocks, 980 * voltage, current to settle down before starting serdes. 981 */ 982 usleep_range(1000, 1100); 983 return 0; 984 } 985 986 static const struct reset_control_ops ufs_qcom_reset_ops = { 987 .assert = ufs_qcom_reset_assert, 988 .deassert = ufs_qcom_reset_deassert, 989 }; 990 991 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 992 { 993 struct device *dev = host->hba->dev; 994 int ret; 995 996 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 997 if (IS_ERR(host->icc_ddr)) 998 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 999 "failed to acquire interconnect path\n"); 1000 1001 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1002 if (IS_ERR(host->icc_cpu)) 1003 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1004 "failed to acquire interconnect path\n"); 1005 1006 /* 1007 * Set Maximum bandwidth vote before initializing the UFS controller and 1008 * device. Ideally, a minimal interconnect vote would suffice for the 1009 * initialization, but a max vote would allow faster initialization. 1010 */ 1011 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1012 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1013 if (ret < 0) 1014 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1015 1016 return 0; 1017 } 1018 1019 /** 1020 * ufs_qcom_init - bind phy with controller 1021 * @hba: host controller instance 1022 * 1023 * Binds PHY with controller and powers up PHY enabling clocks 1024 * and regulators. 1025 * 1026 * Return: -EPROBE_DEFER if binding fails, returns negative error 1027 * on phy power up failure and returns zero on success. 1028 */ 1029 static int ufs_qcom_init(struct ufs_hba *hba) 1030 { 1031 int err; 1032 struct device *dev = hba->dev; 1033 struct ufs_qcom_host *host; 1034 struct ufs_clk_info *clki; 1035 1036 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1037 if (!host) 1038 return -ENOMEM; 1039 1040 /* Make a two way bind between the qcom host and the hba */ 1041 host->hba = hba; 1042 ufshcd_set_variant(hba, host); 1043 1044 /* Setup the optional reset control of HCI */ 1045 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1046 if (IS_ERR(host->core_reset)) { 1047 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1048 "Failed to get reset control\n"); 1049 goto out_variant_clear; 1050 } 1051 1052 /* Fire up the reset controller. Failure here is non-fatal. */ 1053 host->rcdev.of_node = dev->of_node; 1054 host->rcdev.ops = &ufs_qcom_reset_ops; 1055 host->rcdev.owner = dev->driver->owner; 1056 host->rcdev.nr_resets = 1; 1057 err = devm_reset_controller_register(dev, &host->rcdev); 1058 if (err) 1059 dev_warn(dev, "Failed to register reset controller\n"); 1060 1061 if (!has_acpi_companion(dev)) { 1062 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1063 if (IS_ERR(host->generic_phy)) { 1064 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1065 goto out_variant_clear; 1066 } 1067 } 1068 1069 err = ufs_qcom_icc_init(host); 1070 if (err) 1071 goto out_variant_clear; 1072 1073 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1074 GPIOD_OUT_HIGH); 1075 if (IS_ERR(host->device_reset)) { 1076 err = dev_err_probe(dev, PTR_ERR(host->device_reset), 1077 "Failed to acquire device reset gpio\n"); 1078 goto out_variant_clear; 1079 } 1080 1081 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1082 &host->hw_ver.minor, &host->hw_ver.step); 1083 1084 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1085 host->dev_ref_clk_en_mask = BIT(26); 1086 1087 list_for_each_entry(clki, &hba->clk_list_head, list) { 1088 if (!strcmp(clki->name, "core_clk_unipro")) 1089 clki->keep_link_active = true; 1090 } 1091 1092 err = ufs_qcom_init_lane_clks(host); 1093 if (err) 1094 goto out_variant_clear; 1095 1096 ufs_qcom_set_caps(hba); 1097 ufs_qcom_advertise_quirks(hba); 1098 ufs_qcom_set_host_params(hba); 1099 ufs_qcom_set_phy_gear(host); 1100 1101 err = ufs_qcom_ice_init(host); 1102 if (err) 1103 goto out_variant_clear; 1104 1105 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1106 1107 ufs_qcom_get_default_testbus_cfg(host); 1108 err = ufs_qcom_testbus_config(host); 1109 if (err) 1110 /* Failure is non-fatal */ 1111 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1112 __func__, err); 1113 1114 return 0; 1115 1116 out_variant_clear: 1117 ufshcd_set_variant(hba, NULL); 1118 1119 return err; 1120 } 1121 1122 static void ufs_qcom_exit(struct ufs_hba *hba) 1123 { 1124 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1125 1126 ufs_qcom_disable_lane_clks(host); 1127 phy_power_off(host->generic_phy); 1128 phy_exit(host->generic_phy); 1129 } 1130 1131 /** 1132 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles 1133 * 1134 * @hba: host controller instance 1135 * @cycles_in_1us: No of cycles in 1us to be configured 1136 * 1137 * Returns error if dme get/set configuration for 40ns fails 1138 * and returns zero on success. 1139 */ 1140 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, 1141 u32 cycles_in_1us) 1142 { 1143 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1144 u32 cycles_in_40ns; 1145 u32 reg; 1146 int err; 1147 1148 /* 1149 * UFS host controller V4.0.0 onwards needs to program 1150 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed 1151 * frequency of unipro core clk of UFS host controller. 1152 */ 1153 if (host->hw_ver.major < 4) 1154 return 0; 1155 1156 /* 1157 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not 1158 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will 1159 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware 1160 * specification expect to be 16. Hence use exact hardware spec 1161 * mandated value for cycles_in_40ns instead of calculating using 1162 * generic formulae. 1163 */ 1164 switch (cycles_in_1us) { 1165 case UNIPRO_CORE_CLK_FREQ_403_MHZ: 1166 cycles_in_40ns = 16; 1167 break; 1168 case UNIPRO_CORE_CLK_FREQ_300_MHZ: 1169 cycles_in_40ns = 12; 1170 break; 1171 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ: 1172 cycles_in_40ns = 8; 1173 break; 1174 case UNIPRO_CORE_CLK_FREQ_150_MHZ: 1175 cycles_in_40ns = 6; 1176 break; 1177 case UNIPRO_CORE_CLK_FREQ_100_MHZ: 1178 cycles_in_40ns = 4; 1179 break; 1180 case UNIPRO_CORE_CLK_FREQ_75_MHZ: 1181 cycles_in_40ns = 3; 1182 break; 1183 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ: 1184 cycles_in_40ns = 2; 1185 break; 1186 default: 1187 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", 1188 cycles_in_1us); 1189 return -EINVAL; 1190 } 1191 1192 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); 1193 if (err) 1194 return err; 1195 1196 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; 1197 reg |= cycles_in_40ns; 1198 1199 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); 1200 } 1201 1202 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) 1203 { 1204 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1205 struct list_head *head = &hba->clk_list_head; 1206 struct ufs_clk_info *clki; 1207 u32 cycles_in_1us = 0; 1208 u32 core_clk_ctrl_reg; 1209 int err; 1210 1211 list_for_each_entry(clki, head, list) { 1212 if (!IS_ERR_OR_NULL(clki->clk) && 1213 !strcmp(clki->name, "core_clk_unipro")) { 1214 if (is_scale_up) 1215 cycles_in_1us = ceil(clki->max_freq, (1000 * 1000)); 1216 else 1217 cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000)); 1218 break; 1219 } 1220 } 1221 1222 err = ufshcd_dme_get(hba, 1223 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1224 &core_clk_ctrl_reg); 1225 if (err) 1226 return err; 1227 1228 /* Bit mask is different for UFS host controller V4.0.0 onwards */ 1229 if (host->hw_ver.major >= 4) { 1230 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us)) 1231 return -ERANGE; 1232 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4; 1233 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us); 1234 } else { 1235 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us)) 1236 return -ERANGE; 1237 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK; 1238 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); 1239 } 1240 1241 /* Clear CORE_CLK_DIV_EN */ 1242 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1243 1244 err = ufshcd_dme_set(hba, 1245 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1246 core_clk_ctrl_reg); 1247 if (err) 1248 return err; 1249 1250 /* Configure unipro core clk 40ns attribute */ 1251 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); 1252 } 1253 1254 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) 1255 { 1256 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1257 struct ufs_pa_layer_attr *attr = &host->dev_req_params; 1258 int ret; 1259 1260 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx, 1261 attr->hs_rate, false, true); 1262 if (ret) { 1263 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); 1264 return ret; 1265 } 1266 /* set unipro core clock attributes and clear clock divider */ 1267 return ufs_qcom_set_core_clk_ctrl(hba, true); 1268 } 1269 1270 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1271 { 1272 return 0; 1273 } 1274 1275 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1276 { 1277 int err; 1278 u32 core_clk_ctrl_reg; 1279 1280 err = ufshcd_dme_get(hba, 1281 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1282 &core_clk_ctrl_reg); 1283 1284 /* make sure CORE_CLK_DIV_EN is cleared */ 1285 if (!err && 1286 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1287 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1288 err = ufshcd_dme_set(hba, 1289 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1290 core_clk_ctrl_reg); 1291 } 1292 1293 return err; 1294 } 1295 1296 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) 1297 { 1298 /* set unipro core clock attributes and clear clock divider */ 1299 return ufs_qcom_set_core_clk_ctrl(hba, false); 1300 } 1301 1302 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, 1303 bool scale_up, enum ufs_notify_change_status status) 1304 { 1305 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1306 int err; 1307 1308 /* check the host controller state before sending hibern8 cmd */ 1309 if (!ufshcd_is_hba_active(hba)) 1310 return 0; 1311 1312 if (status == PRE_CHANGE) { 1313 err = ufshcd_uic_hibern8_enter(hba); 1314 if (err) 1315 return err; 1316 if (scale_up) 1317 err = ufs_qcom_clk_scale_up_pre_change(hba); 1318 else 1319 err = ufs_qcom_clk_scale_down_pre_change(hba); 1320 1321 if (err) { 1322 ufshcd_uic_hibern8_exit(hba); 1323 return err; 1324 } 1325 } else { 1326 if (scale_up) 1327 err = ufs_qcom_clk_scale_up_post_change(hba); 1328 else 1329 err = ufs_qcom_clk_scale_down_post_change(hba); 1330 1331 1332 if (err) { 1333 ufshcd_uic_hibern8_exit(hba); 1334 return err; 1335 } 1336 1337 ufs_qcom_icc_update_bw(host); 1338 ufshcd_uic_hibern8_exit(hba); 1339 } 1340 1341 return 0; 1342 } 1343 1344 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1345 { 1346 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1347 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1348 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1349 } 1350 1351 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1352 { 1353 /* provide a legal default configuration */ 1354 host->testbus.select_major = TSTBUS_UNIPRO; 1355 host->testbus.select_minor = 37; 1356 } 1357 1358 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1359 { 1360 if (host->testbus.select_major >= TSTBUS_MAX) { 1361 dev_err(host->hba->dev, 1362 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1363 __func__, host->testbus.select_major); 1364 return false; 1365 } 1366 1367 return true; 1368 } 1369 1370 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1371 { 1372 int reg; 1373 int offset; 1374 u32 mask = TEST_BUS_SUB_SEL_MASK; 1375 1376 if (!host) 1377 return -EINVAL; 1378 1379 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1380 return -EPERM; 1381 1382 switch (host->testbus.select_major) { 1383 case TSTBUS_UAWM: 1384 reg = UFS_TEST_BUS_CTRL_0; 1385 offset = 24; 1386 break; 1387 case TSTBUS_UARM: 1388 reg = UFS_TEST_BUS_CTRL_0; 1389 offset = 16; 1390 break; 1391 case TSTBUS_TXUC: 1392 reg = UFS_TEST_BUS_CTRL_0; 1393 offset = 8; 1394 break; 1395 case TSTBUS_RXUC: 1396 reg = UFS_TEST_BUS_CTRL_0; 1397 offset = 0; 1398 break; 1399 case TSTBUS_DFC: 1400 reg = UFS_TEST_BUS_CTRL_1; 1401 offset = 24; 1402 break; 1403 case TSTBUS_TRLUT: 1404 reg = UFS_TEST_BUS_CTRL_1; 1405 offset = 16; 1406 break; 1407 case TSTBUS_TMRLUT: 1408 reg = UFS_TEST_BUS_CTRL_1; 1409 offset = 8; 1410 break; 1411 case TSTBUS_OCSC: 1412 reg = UFS_TEST_BUS_CTRL_1; 1413 offset = 0; 1414 break; 1415 case TSTBUS_WRAPPER: 1416 reg = UFS_TEST_BUS_CTRL_2; 1417 offset = 16; 1418 break; 1419 case TSTBUS_COMBINED: 1420 reg = UFS_TEST_BUS_CTRL_2; 1421 offset = 8; 1422 break; 1423 case TSTBUS_UTP_HCI: 1424 reg = UFS_TEST_BUS_CTRL_2; 1425 offset = 0; 1426 break; 1427 case TSTBUS_UNIPRO: 1428 reg = UFS_UNIPRO_CFG; 1429 offset = 20; 1430 mask = 0xFFF; 1431 break; 1432 /* 1433 * No need for a default case, since 1434 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 1435 * is legal 1436 */ 1437 } 1438 mask <<= offset; 1439 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 1440 (u32)host->testbus.select_major << 19, 1441 REG_UFS_CFG1); 1442 ufshcd_rmwl(host->hba, mask, 1443 (u32)host->testbus.select_minor << offset, 1444 reg); 1445 ufs_qcom_enable_test_bus(host); 1446 /* 1447 * Make sure the test bus configuration is 1448 * committed before returning. 1449 */ 1450 mb(); 1451 1452 return 0; 1453 } 1454 1455 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 1456 { 1457 u32 reg; 1458 struct ufs_qcom_host *host; 1459 1460 host = ufshcd_get_variant(hba); 1461 1462 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 1463 "HCI Vendor Specific Registers "); 1464 1465 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 1466 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 1467 1468 reg = ufshcd_readl(hba, REG_UFS_CFG1); 1469 reg |= UTP_DBG_RAMS_EN; 1470 ufshcd_writel(hba, reg, REG_UFS_CFG1); 1471 1472 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 1473 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 1474 1475 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 1476 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 1477 1478 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 1479 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 1480 1481 /* clear bit 17 - UTP_DBG_RAMS_EN */ 1482 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 1483 1484 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 1485 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 1486 1487 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 1488 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 1489 1490 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 1491 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 1492 1493 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 1494 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 1495 1496 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 1497 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 1498 1499 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 1500 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 1501 1502 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 1503 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 1504 } 1505 1506 /** 1507 * ufs_qcom_device_reset() - toggle the (optional) device reset line 1508 * @hba: per-adapter instance 1509 * 1510 * Toggles the (optional) reset line to reset the attached device. 1511 */ 1512 static int ufs_qcom_device_reset(struct ufs_hba *hba) 1513 { 1514 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1515 1516 /* reset gpio is optional */ 1517 if (!host->device_reset) 1518 return -EOPNOTSUPP; 1519 1520 /* 1521 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 1522 * be on the safe side. 1523 */ 1524 ufs_qcom_device_reset_ctrl(hba, true); 1525 usleep_range(10, 15); 1526 1527 ufs_qcom_device_reset_ctrl(hba, false); 1528 usleep_range(10, 15); 1529 1530 return 0; 1531 } 1532 1533 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) 1534 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1535 struct devfreq_dev_profile *p, 1536 struct devfreq_simple_ondemand_data *d) 1537 { 1538 p->polling_ms = 60; 1539 p->timer = DEVFREQ_TIMER_DELAYED; 1540 d->upthreshold = 70; 1541 d->downdifferential = 5; 1542 } 1543 #else 1544 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1545 struct devfreq_dev_profile *p, 1546 struct devfreq_simple_ondemand_data *data) 1547 { 1548 } 1549 #endif 1550 1551 static void ufs_qcom_reinit_notify(struct ufs_hba *hba) 1552 { 1553 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1554 1555 phy_power_off(host->generic_phy); 1556 } 1557 1558 /* Resources */ 1559 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { 1560 {.name = "ufs_mem",}, 1561 {.name = "mcq",}, 1562 /* Submission Queue DAO */ 1563 {.name = "mcq_sqd",}, 1564 /* Submission Queue Interrupt Status */ 1565 {.name = "mcq_sqis",}, 1566 /* Completion Queue DAO */ 1567 {.name = "mcq_cqd",}, 1568 /* Completion Queue Interrupt Status */ 1569 {.name = "mcq_cqis",}, 1570 /* MCQ vendor specific */ 1571 {.name = "mcq_vs",}, 1572 }; 1573 1574 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 1575 { 1576 struct platform_device *pdev = to_platform_device(hba->dev); 1577 struct ufshcd_res_info *res; 1578 struct resource *res_mem, *res_mcq; 1579 int i, ret; 1580 1581 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); 1582 1583 for (i = 0; i < RES_MAX; i++) { 1584 res = &hba->res[i]; 1585 res->resource = platform_get_resource_byname(pdev, 1586 IORESOURCE_MEM, 1587 res->name); 1588 if (!res->resource) { 1589 dev_info(hba->dev, "Resource %s not provided\n", res->name); 1590 if (i == RES_UFS) 1591 return -ENODEV; 1592 continue; 1593 } else if (i == RES_UFS) { 1594 res_mem = res->resource; 1595 res->base = hba->mmio_base; 1596 continue; 1597 } 1598 1599 res->base = devm_ioremap_resource(hba->dev, res->resource); 1600 if (IS_ERR(res->base)) { 1601 dev_err(hba->dev, "Failed to map res %s, err=%d\n", 1602 res->name, (int)PTR_ERR(res->base)); 1603 ret = PTR_ERR(res->base); 1604 res->base = NULL; 1605 return ret; 1606 } 1607 } 1608 1609 /* MCQ resource provided in DT */ 1610 res = &hba->res[RES_MCQ]; 1611 /* Bail if MCQ resource is provided */ 1612 if (res->base) 1613 goto out; 1614 1615 /* Explicitly allocate MCQ resource from ufs_mem */ 1616 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); 1617 if (!res_mcq) 1618 return -ENOMEM; 1619 1620 res_mcq->start = res_mem->start + 1621 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); 1622 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; 1623 res_mcq->flags = res_mem->flags; 1624 res_mcq->name = "mcq"; 1625 1626 ret = insert_resource(&iomem_resource, res_mcq); 1627 if (ret) { 1628 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", 1629 ret); 1630 return ret; 1631 } 1632 1633 res->base = devm_ioremap_resource(hba->dev, res_mcq); 1634 if (IS_ERR(res->base)) { 1635 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", 1636 (int)PTR_ERR(res->base)); 1637 ret = PTR_ERR(res->base); 1638 goto ioremap_err; 1639 } 1640 1641 out: 1642 hba->mcq_base = res->base; 1643 return 0; 1644 ioremap_err: 1645 res->base = NULL; 1646 remove_resource(res_mcq); 1647 return ret; 1648 } 1649 1650 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 1651 { 1652 struct ufshcd_res_info *mem_res, *sqdao_res; 1653 struct ufshcd_mcq_opr_info_t *opr; 1654 int i; 1655 1656 mem_res = &hba->res[RES_UFS]; 1657 sqdao_res = &hba->res[RES_MCQ_SQD]; 1658 1659 if (!mem_res->base || !sqdao_res->base) 1660 return -EINVAL; 1661 1662 for (i = 0; i < OPR_MAX; i++) { 1663 opr = &hba->mcq_opr[i]; 1664 opr->offset = sqdao_res->resource->start - 1665 mem_res->resource->start + 0x40 * i; 1666 opr->stride = 0x100; 1667 opr->base = sqdao_res->base + 0x40 * i; 1668 } 1669 1670 return 0; 1671 } 1672 1673 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 1674 { 1675 /* Qualcomm HC supports up to 64 */ 1676 return MAX_SUPP_MAC; 1677 } 1678 1679 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 1680 unsigned long *ocqs) 1681 { 1682 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; 1683 1684 if (!mcq_vs_res->base) 1685 return -EINVAL; 1686 1687 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); 1688 1689 return 0; 1690 } 1691 1692 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 1693 { 1694 struct device *dev = msi_desc_to_dev(desc); 1695 struct ufs_hba *hba = dev_get_drvdata(dev); 1696 1697 ufshcd_mcq_config_esi(hba, msg); 1698 } 1699 1700 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 1701 { 1702 struct msi_desc *desc = data; 1703 struct device *dev = msi_desc_to_dev(desc); 1704 struct ufs_hba *hba = dev_get_drvdata(dev); 1705 u32 id = desc->msi_index; 1706 struct ufs_hw_queue *hwq = &hba->uhq[id]; 1707 1708 ufshcd_mcq_write_cqis(hba, 0x1, id); 1709 ufshcd_mcq_poll_cqe_lock(hba, hwq); 1710 1711 return IRQ_HANDLED; 1712 } 1713 1714 static int ufs_qcom_config_esi(struct ufs_hba *hba) 1715 { 1716 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1717 struct msi_desc *desc; 1718 struct msi_desc *failed_desc = NULL; 1719 int nr_irqs, ret; 1720 1721 if (host->esi_enabled) 1722 return 0; 1723 1724 /* 1725 * 1. We only handle CQs as of now. 1726 * 2. Poll queues do not need ESI. 1727 */ 1728 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 1729 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, 1730 ufs_qcom_write_msi_msg); 1731 if (ret) { 1732 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); 1733 return ret; 1734 } 1735 1736 msi_lock_descs(hba->dev); 1737 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1738 ret = devm_request_irq(hba->dev, desc->irq, 1739 ufs_qcom_mcq_esi_handler, 1740 IRQF_SHARED, "qcom-mcq-esi", desc); 1741 if (ret) { 1742 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", 1743 __func__, desc->irq, ret); 1744 failed_desc = desc; 1745 break; 1746 } 1747 } 1748 msi_unlock_descs(hba->dev); 1749 1750 if (ret) { 1751 /* Rewind */ 1752 msi_lock_descs(hba->dev); 1753 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1754 if (desc == failed_desc) 1755 break; 1756 devm_free_irq(hba->dev, desc->irq, hba); 1757 } 1758 msi_unlock_descs(hba->dev); 1759 platform_device_msi_free_irqs_all(hba->dev); 1760 } else { 1761 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && 1762 host->hw_ver.step == 0) 1763 ufshcd_rmwl(hba, ESI_VEC_MASK, 1764 FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), 1765 REG_UFS_CFG3); 1766 ufshcd_mcq_enable_esi(hba); 1767 host->esi_enabled = true; 1768 } 1769 1770 return ret; 1771 } 1772 1773 /* 1774 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 1775 * 1776 * The variant operations configure the necessary controller and PHY 1777 * handshake during initialization. 1778 */ 1779 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 1780 .name = "qcom", 1781 .init = ufs_qcom_init, 1782 .exit = ufs_qcom_exit, 1783 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 1784 .clk_scale_notify = ufs_qcom_clk_scale_notify, 1785 .setup_clocks = ufs_qcom_setup_clocks, 1786 .hce_enable_notify = ufs_qcom_hce_enable_notify, 1787 .link_startup_notify = ufs_qcom_link_startup_notify, 1788 .pwr_change_notify = ufs_qcom_pwr_change_notify, 1789 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 1790 .suspend = ufs_qcom_suspend, 1791 .resume = ufs_qcom_resume, 1792 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 1793 .device_reset = ufs_qcom_device_reset, 1794 .config_scaling_param = ufs_qcom_config_scaling_param, 1795 .program_key = ufs_qcom_ice_program_key, 1796 .reinit_notify = ufs_qcom_reinit_notify, 1797 .mcq_config_resource = ufs_qcom_mcq_config_resource, 1798 .get_hba_mac = ufs_qcom_get_hba_mac, 1799 .op_runtime_config = ufs_qcom_op_runtime_config, 1800 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 1801 .config_esi = ufs_qcom_config_esi, 1802 }; 1803 1804 /** 1805 * ufs_qcom_probe - probe routine of the driver 1806 * @pdev: pointer to Platform device handle 1807 * 1808 * Return: zero for success and non-zero for failure. 1809 */ 1810 static int ufs_qcom_probe(struct platform_device *pdev) 1811 { 1812 int err; 1813 struct device *dev = &pdev->dev; 1814 1815 /* Perform generic probe */ 1816 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); 1817 if (err) 1818 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 1819 1820 return 0; 1821 } 1822 1823 /** 1824 * ufs_qcom_remove - set driver_data of the device to NULL 1825 * @pdev: pointer to platform device handle 1826 * 1827 * Always returns 0 1828 */ 1829 static void ufs_qcom_remove(struct platform_device *pdev) 1830 { 1831 struct ufs_hba *hba = platform_get_drvdata(pdev); 1832 1833 pm_runtime_get_sync(&(pdev)->dev); 1834 ufshcd_remove(hba); 1835 platform_device_msi_free_irqs_all(hba->dev); 1836 } 1837 1838 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 1839 { .compatible = "qcom,ufshc"}, 1840 {}, 1841 }; 1842 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 1843 1844 #ifdef CONFIG_ACPI 1845 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 1846 { "QCOM24A5" }, 1847 { }, 1848 }; 1849 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 1850 #endif 1851 1852 static const struct dev_pm_ops ufs_qcom_pm_ops = { 1853 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 1854 .prepare = ufshcd_suspend_prepare, 1855 .complete = ufshcd_resume_complete, 1856 #ifdef CONFIG_PM_SLEEP 1857 .suspend = ufshcd_system_suspend, 1858 .resume = ufshcd_system_resume, 1859 .freeze = ufshcd_system_freeze, 1860 .restore = ufshcd_system_restore, 1861 .thaw = ufshcd_system_thaw, 1862 #endif 1863 }; 1864 1865 static struct platform_driver ufs_qcom_pltform = { 1866 .probe = ufs_qcom_probe, 1867 .remove_new = ufs_qcom_remove, 1868 .driver = { 1869 .name = "ufshcd-qcom", 1870 .pm = &ufs_qcom_pm_ops, 1871 .of_match_table = of_match_ptr(ufs_qcom_of_match), 1872 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 1873 }, 1874 }; 1875 module_platform_driver(ufs_qcom_pltform); 1876 1877 MODULE_LICENSE("GPL v2"); 1878