1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/time.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/interconnect.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/phy/phy.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/reset-controller.h> 17 #include <linux/devfreq.h> 18 19 #include <soc/qcom/ice.h> 20 21 #include <ufs/ufshcd.h> 22 #include "ufshcd-pltfrm.h" 23 #include <ufs/unipro.h> 24 #include "ufs-qcom.h" 25 #include <ufs/ufshci.h> 26 #include <ufs/ufs_quirks.h> 27 28 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 29 #define MCQ_QCFGPTR_UNIT 0x200 30 #define MCQ_SQATTR_OFFSET(c) \ 31 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 32 #define MCQ_QCFG_SIZE 0x40 33 34 enum { 35 TSTBUS_UAWM, 36 TSTBUS_UARM, 37 TSTBUS_TXUC, 38 TSTBUS_RXUC, 39 TSTBUS_DFC, 40 TSTBUS_TRLUT, 41 TSTBUS_TMRLUT, 42 TSTBUS_OCSC, 43 TSTBUS_UTP_HCI, 44 TSTBUS_COMBINED, 45 TSTBUS_WRAPPER, 46 TSTBUS_UNIPRO, 47 TSTBUS_MAX, 48 }; 49 50 #define QCOM_UFS_MAX_GEAR 4 51 #define QCOM_UFS_MAX_LANE 2 52 53 enum { 54 MODE_MIN, 55 MODE_PWM, 56 MODE_HS_RA, 57 MODE_HS_RB, 58 MODE_MAX, 59 }; 60 61 static const struct __ufs_qcom_bw_table { 62 u32 mem_bw; 63 u32 cfg_bw; 64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 65 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 66 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 67 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 68 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 69 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 70 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 71 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 72 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 73 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 74 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 75 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 76 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 77 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 78 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 79 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 80 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 81 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 82 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 83 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 84 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 85 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 86 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 87 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 88 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 89 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 90 [MODE_MAX][0][0] = { 7643136, 307200 }, 91 }; 92 93 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; 94 95 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 96 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up); 97 98 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 99 { 100 return container_of(rcd, struct ufs_qcom_host, rcdev); 101 } 102 103 #ifdef CONFIG_SCSI_UFS_CRYPTO 104 105 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 106 { 107 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 108 qcom_ice_enable(host->ice); 109 } 110 111 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 112 { 113 struct ufs_hba *hba = host->hba; 114 struct device *dev = hba->dev; 115 struct qcom_ice *ice; 116 117 ice = of_qcom_ice_get(dev); 118 if (ice == ERR_PTR(-EOPNOTSUPP)) { 119 dev_warn(dev, "Disabling inline encryption support\n"); 120 ice = NULL; 121 } 122 123 if (IS_ERR_OR_NULL(ice)) 124 return PTR_ERR_OR_ZERO(ice); 125 126 host->ice = ice; 127 hba->caps |= UFSHCD_CAP_CRYPTO; 128 129 return 0; 130 } 131 132 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 133 { 134 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 135 return qcom_ice_resume(host->ice); 136 137 return 0; 138 } 139 140 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 141 { 142 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 143 return qcom_ice_suspend(host->ice); 144 145 return 0; 146 } 147 148 static int ufs_qcom_ice_program_key(struct ufs_hba *hba, 149 const union ufs_crypto_cfg_entry *cfg, 150 int slot) 151 { 152 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 153 union ufs_crypto_cap_entry cap; 154 bool config_enable = 155 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; 156 157 /* Only AES-256-XTS has been tested so far. */ 158 cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; 159 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || 160 cap.key_size != UFS_CRYPTO_KEY_SIZE_256) 161 return -EINVAL; 162 163 if (config_enable) 164 return qcom_ice_program_key(host->ice, 165 QCOM_ICE_CRYPTO_ALG_AES_XTS, 166 QCOM_ICE_CRYPTO_KEY_SIZE_256, 167 cfg->crypto_key, 168 cfg->data_unit_size, slot); 169 else 170 return qcom_ice_evict_key(host->ice, slot); 171 } 172 173 #else 174 175 #define ufs_qcom_ice_program_key NULL 176 177 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 178 { 179 } 180 181 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 182 { 183 return 0; 184 } 185 186 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 187 { 188 return 0; 189 } 190 191 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 192 { 193 return 0; 194 } 195 #endif 196 197 static int ufs_qcom_host_clk_get(struct device *dev, 198 const char *name, struct clk **clk_out, bool optional) 199 { 200 struct clk *clk; 201 int err = 0; 202 203 clk = devm_clk_get(dev, name); 204 if (!IS_ERR(clk)) { 205 *clk_out = clk; 206 return 0; 207 } 208 209 err = PTR_ERR(clk); 210 211 if (optional && err == -ENOENT) { 212 *clk_out = NULL; 213 return 0; 214 } 215 216 if (err != -EPROBE_DEFER) 217 dev_err(dev, "failed to get %s err %d\n", name, err); 218 219 return err; 220 } 221 222 static int ufs_qcom_host_clk_enable(struct device *dev, 223 const char *name, struct clk *clk) 224 { 225 int err = 0; 226 227 err = clk_prepare_enable(clk); 228 if (err) 229 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err); 230 231 return err; 232 } 233 234 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 235 { 236 if (!host->is_lane_clks_enabled) 237 return; 238 239 clk_disable_unprepare(host->tx_l1_sync_clk); 240 clk_disable_unprepare(host->tx_l0_sync_clk); 241 clk_disable_unprepare(host->rx_l1_sync_clk); 242 clk_disable_unprepare(host->rx_l0_sync_clk); 243 244 host->is_lane_clks_enabled = false; 245 } 246 247 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 248 { 249 int err; 250 struct device *dev = host->hba->dev; 251 252 if (host->is_lane_clks_enabled) 253 return 0; 254 255 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", 256 host->rx_l0_sync_clk); 257 if (err) 258 return err; 259 260 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", 261 host->tx_l0_sync_clk); 262 if (err) 263 goto disable_rx_l0; 264 265 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk", 266 host->rx_l1_sync_clk); 267 if (err) 268 goto disable_tx_l0; 269 270 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk", 271 host->tx_l1_sync_clk); 272 if (err) 273 goto disable_rx_l1; 274 275 host->is_lane_clks_enabled = true; 276 277 return 0; 278 279 disable_rx_l1: 280 clk_disable_unprepare(host->rx_l1_sync_clk); 281 disable_tx_l0: 282 clk_disable_unprepare(host->tx_l0_sync_clk); 283 disable_rx_l0: 284 clk_disable_unprepare(host->rx_l0_sync_clk); 285 286 return err; 287 } 288 289 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 290 { 291 int err = 0; 292 struct device *dev = host->hba->dev; 293 294 if (has_acpi_companion(dev)) 295 return 0; 296 297 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", 298 &host->rx_l0_sync_clk, false); 299 if (err) 300 return err; 301 302 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", 303 &host->tx_l0_sync_clk, false); 304 if (err) 305 return err; 306 307 /* In case of single lane per direction, don't read lane1 clocks */ 308 if (host->hba->lanes_per_direction > 1) { 309 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", 310 &host->rx_l1_sync_clk, false); 311 if (err) 312 return err; 313 314 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", 315 &host->tx_l1_sync_clk, true); 316 } 317 318 return 0; 319 } 320 321 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 322 { 323 int err; 324 u32 tx_fsm_val = 0; 325 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 326 327 do { 328 err = ufshcd_dme_get(hba, 329 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 330 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 331 &tx_fsm_val); 332 if (err || tx_fsm_val == TX_FSM_HIBERN8) 333 break; 334 335 /* sleep for max. 200us */ 336 usleep_range(100, 200); 337 } while (time_before(jiffies, timeout)); 338 339 /* 340 * we might have scheduled out for long during polling so 341 * check the state again. 342 */ 343 if (time_after(jiffies, timeout)) 344 err = ufshcd_dme_get(hba, 345 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 346 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 347 &tx_fsm_val); 348 349 if (err) { 350 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 351 __func__, err); 352 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 353 err = tx_fsm_val; 354 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 355 __func__, err); 356 } 357 358 return err; 359 } 360 361 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 362 { 363 ufshcd_rmwl(host->hba, QUNIPRO_SEL, 364 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0, 365 REG_UFS_CFG1); 366 367 if (host->hw_ver.major >= 0x05) 368 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 369 370 /* make sure above configuration is applied before we return */ 371 mb(); 372 } 373 374 /* 375 * ufs_qcom_host_reset - reset host controller and PHY 376 */ 377 static int ufs_qcom_host_reset(struct ufs_hba *hba) 378 { 379 int ret = 0; 380 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 381 bool reenable_intr = false; 382 383 if (!host->core_reset) { 384 dev_warn(hba->dev, "%s: reset control not set\n", __func__); 385 return 0; 386 } 387 388 reenable_intr = hba->is_irq_enabled; 389 disable_irq(hba->irq); 390 hba->is_irq_enabled = false; 391 392 ret = reset_control_assert(host->core_reset); 393 if (ret) { 394 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 395 __func__, ret); 396 return ret; 397 } 398 399 /* 400 * The hardware requirement for delay between assert/deassert 401 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 402 * ~125us (4/32768). To be on the safe side add 200us delay. 403 */ 404 usleep_range(200, 210); 405 406 ret = reset_control_deassert(host->core_reset); 407 if (ret) 408 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 409 __func__, ret); 410 411 usleep_range(1000, 1100); 412 413 if (reenable_intr) { 414 enable_irq(hba->irq); 415 hba->is_irq_enabled = true; 416 } 417 418 return 0; 419 } 420 421 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 422 { 423 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 424 425 if (host->hw_ver.major == 0x1) { 426 /* 427 * HS-G3 operations may not reliably work on legacy QCOM 428 * UFS host controller hardware even though capability 429 * exchange during link startup phase may end up 430 * negotiating maximum supported gear as G3. 431 * Hence downgrade the maximum supported gear to HS-G2. 432 */ 433 return UFS_HS_G2; 434 } else if (host->hw_ver.major >= 0x4) { 435 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 436 } 437 438 /* Default is HS-G3 */ 439 return UFS_HS_G3; 440 } 441 442 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 443 { 444 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 445 struct ufs_host_params *host_params = &host->host_params; 446 struct phy *phy = host->generic_phy; 447 enum phy_mode mode; 448 int ret; 449 450 /* 451 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. 452 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, 453 * so that the subsequent power mode change shall stick to Rate-A. 454 */ 455 if (host->hw_ver.major == 0x5) { 456 if (host->phy_gear == UFS_HS_G5) 457 host_params->hs_rate = PA_HS_MODE_A; 458 else 459 host_params->hs_rate = PA_HS_MODE_B; 460 } 461 462 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; 463 464 /* Reset UFS Host Controller and PHY */ 465 ret = ufs_qcom_host_reset(hba); 466 if (ret) 467 dev_warn(hba->dev, "%s: host reset returned %d\n", 468 __func__, ret); 469 470 /* phy initialization - calibrate the phy */ 471 ret = phy_init(phy); 472 if (ret) { 473 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 474 __func__, ret); 475 return ret; 476 } 477 478 ret = phy_set_mode_ext(phy, mode, host->phy_gear); 479 if (ret) 480 goto out_disable_phy; 481 482 /* power on phy - start serdes and phy's power and clocks */ 483 ret = phy_power_on(phy); 484 if (ret) { 485 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 486 __func__, ret); 487 goto out_disable_phy; 488 } 489 490 ufs_qcom_select_unipro_mode(host); 491 492 return 0; 493 494 out_disable_phy: 495 phy_exit(phy); 496 497 return ret; 498 } 499 500 /* 501 * The UTP controller has a number of internal clock gating cells (CGCs). 502 * Internal hardware sub-modules within the UTP controller control the CGCs. 503 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 504 * in a specific operation, UTP controller CGCs are by default disabled and 505 * this function enables them (after every UFS link startup) to save some power 506 * leakage. 507 */ 508 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 509 { 510 ufshcd_writel(hba, 511 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL, 512 REG_UFS_CFG2); 513 514 /* Ensure that HW clock gating is enabled before next operations */ 515 mb(); 516 } 517 518 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 519 enum ufs_notify_change_status status) 520 { 521 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 522 int err = 0; 523 524 switch (status) { 525 case PRE_CHANGE: 526 ufs_qcom_power_up_sequence(hba); 527 /* 528 * The PHY PLL output is the source of tx/rx lane symbol 529 * clocks, hence, enable the lane clocks only after PHY 530 * is initialized. 531 */ 532 err = ufs_qcom_enable_lane_clks(host); 533 break; 534 case POST_CHANGE: 535 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 536 err = ufs_qcom_check_hibern8(hba); 537 ufs_qcom_enable_hw_clk_gating(hba); 538 ufs_qcom_ice_enable(host); 539 break; 540 default: 541 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 542 err = -EINVAL; 543 break; 544 } 545 return err; 546 } 547 548 /** 549 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers 550 * 551 * @hba: host controller instance 552 * @gear: Current operating gear 553 * @hs: current power mode 554 * @rate: current operating rate (A or B) 555 * @update_link_startup_timer: indicate if link_start ongoing 556 * @is_pre_scale_up: flag to check if pre scale up condition. 557 * Return: zero for success and non-zero in case of a failure. 558 */ 559 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, 560 u32 hs, u32 rate, bool update_link_startup_timer, 561 bool is_pre_scale_up) 562 { 563 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 564 struct ufs_clk_info *clki; 565 u32 core_clk_period_in_ns; 566 u32 tx_clk_cycles_per_us = 0; 567 unsigned long core_clk_rate = 0; 568 u32 core_clk_cycles_per_us = 0; 569 570 static u32 pwm_fr_table[][2] = { 571 {UFS_PWM_G1, 0x1}, 572 {UFS_PWM_G2, 0x1}, 573 {UFS_PWM_G3, 0x1}, 574 {UFS_PWM_G4, 0x1}, 575 }; 576 577 static u32 hs_fr_table_rA[][2] = { 578 {UFS_HS_G1, 0x1F}, 579 {UFS_HS_G2, 0x3e}, 580 {UFS_HS_G3, 0x7D}, 581 }; 582 583 static u32 hs_fr_table_rB[][2] = { 584 {UFS_HS_G1, 0x24}, 585 {UFS_HS_G2, 0x49}, 586 {UFS_HS_G3, 0x92}, 587 }; 588 589 /* 590 * The Qunipro controller does not use following registers: 591 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG & 592 * UFS_REG_PA_LINK_STARTUP_TIMER. 593 * However UTP controller uses SYS1CLK_1US_REG register for Interrupt 594 * Aggregation logic. 595 * It is mandatory to write SYS1CLK_1US_REG register on UFS host 596 * controller V4.0.0 onwards. 597 */ 598 if (host->hw_ver.major < 4 && ufs_qcom_cap_qunipro(host) && 599 !ufshcd_is_intr_aggr_allowed(hba)) 600 return 0; 601 602 if (gear == 0) { 603 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); 604 return -EINVAL; 605 } 606 607 list_for_each_entry(clki, &hba->clk_list_head, list) { 608 if (!strcmp(clki->name, "core_clk")) { 609 if (is_pre_scale_up) 610 core_clk_rate = clki->max_freq; 611 else 612 core_clk_rate = clk_get_rate(clki->clk); 613 break; 614 } 615 616 } 617 618 /* If frequency is smaller than 1MHz, set to 1MHz */ 619 if (core_clk_rate < DEFAULT_CLK_RATE_HZ) 620 core_clk_rate = DEFAULT_CLK_RATE_HZ; 621 622 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; 623 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 624 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 625 /* 626 * make sure above write gets applied before we return from 627 * this function. 628 */ 629 mb(); 630 } 631 632 if (ufs_qcom_cap_qunipro(host)) 633 return 0; 634 635 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate; 636 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG; 637 core_clk_period_in_ns &= MASK_CLK_NS_REG; 638 639 switch (hs) { 640 case FASTAUTO_MODE: 641 case FAST_MODE: 642 if (rate == PA_HS_MODE_A) { 643 if (gear > ARRAY_SIZE(hs_fr_table_rA)) { 644 dev_err(hba->dev, 645 "%s: index %d exceeds table size %zu\n", 646 __func__, gear, 647 ARRAY_SIZE(hs_fr_table_rA)); 648 return -EINVAL; 649 } 650 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1]; 651 } else if (rate == PA_HS_MODE_B) { 652 if (gear > ARRAY_SIZE(hs_fr_table_rB)) { 653 dev_err(hba->dev, 654 "%s: index %d exceeds table size %zu\n", 655 __func__, gear, 656 ARRAY_SIZE(hs_fr_table_rB)); 657 return -EINVAL; 658 } 659 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1]; 660 } else { 661 dev_err(hba->dev, "%s: invalid rate = %d\n", 662 __func__, rate); 663 return -EINVAL; 664 } 665 break; 666 case SLOWAUTO_MODE: 667 case SLOW_MODE: 668 if (gear > ARRAY_SIZE(pwm_fr_table)) { 669 dev_err(hba->dev, 670 "%s: index %d exceeds table size %zu\n", 671 __func__, gear, 672 ARRAY_SIZE(pwm_fr_table)); 673 return -EINVAL; 674 } 675 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1]; 676 break; 677 case UNCHANGED: 678 default: 679 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs); 680 return -EINVAL; 681 } 682 683 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) != 684 (core_clk_period_in_ns | tx_clk_cycles_per_us)) { 685 /* this register 2 fields shall be written at once */ 686 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us, 687 REG_UFS_TX_SYMBOL_CLK_NS_US); 688 /* 689 * make sure above write gets applied before we return from 690 * this function. 691 */ 692 mb(); 693 } 694 695 if (update_link_startup_timer && host->hw_ver.major != 0x5) { 696 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), 697 REG_UFS_CFG0); 698 /* 699 * make sure that this configuration is applied before 700 * we return 701 */ 702 mb(); 703 } 704 705 return 0; 706 } 707 708 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 709 enum ufs_notify_change_status status) 710 { 711 int err = 0; 712 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 713 714 switch (status) { 715 case PRE_CHANGE: 716 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, 717 0, true, false)) { 718 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 719 __func__); 720 return -EINVAL; 721 } 722 723 if (ufs_qcom_cap_qunipro(host)) { 724 err = ufs_qcom_set_core_clk_ctrl(hba, true); 725 if (err) 726 dev_err(hba->dev, "cfg core clk ctrl failed\n"); 727 } 728 /* 729 * Some UFS devices (and may be host) have issues if LCC is 730 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 731 * before link startup which will make sure that both host 732 * and device TX LCC are disabled once link startup is 733 * completed. 734 */ 735 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41) 736 err = ufshcd_disable_host_tx_lcc(hba); 737 738 break; 739 default: 740 break; 741 } 742 743 return err; 744 } 745 746 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 747 { 748 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 749 750 /* reset gpio is optional */ 751 if (!host->device_reset) 752 return; 753 754 gpiod_set_value_cansleep(host->device_reset, asserted); 755 } 756 757 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 758 enum ufs_notify_change_status status) 759 { 760 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 761 struct phy *phy = host->generic_phy; 762 763 if (status == PRE_CHANGE) 764 return 0; 765 766 if (ufs_qcom_is_link_off(hba)) { 767 /* 768 * Disable the tx/rx lane symbol clocks before PHY is 769 * powered down as the PLL source should be disabled 770 * after downstream clocks are disabled. 771 */ 772 ufs_qcom_disable_lane_clks(host); 773 phy_power_off(phy); 774 775 /* reset the connected UFS device during power down */ 776 ufs_qcom_device_reset_ctrl(hba, true); 777 778 } else if (!ufs_qcom_is_link_active(hba)) { 779 ufs_qcom_disable_lane_clks(host); 780 } 781 782 return ufs_qcom_ice_suspend(host); 783 } 784 785 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 786 { 787 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 788 struct phy *phy = host->generic_phy; 789 int err; 790 791 if (ufs_qcom_is_link_off(hba)) { 792 err = phy_power_on(phy); 793 if (err) { 794 dev_err(hba->dev, "%s: failed PHY power on: %d\n", 795 __func__, err); 796 return err; 797 } 798 799 err = ufs_qcom_enable_lane_clks(host); 800 if (err) 801 return err; 802 803 } else if (!ufs_qcom_is_link_active(hba)) { 804 err = ufs_qcom_enable_lane_clks(host); 805 if (err) 806 return err; 807 } 808 809 return ufs_qcom_ice_resume(host); 810 } 811 812 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 813 { 814 if (host->dev_ref_clk_ctrl_mmio && 815 (enable ^ host->is_dev_ref_clk_enabled)) { 816 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 817 818 if (enable) 819 temp |= host->dev_ref_clk_en_mask; 820 else 821 temp &= ~host->dev_ref_clk_en_mask; 822 823 /* 824 * If we are here to disable this clock it might be immediately 825 * after entering into hibern8 in which case we need to make 826 * sure that device ref_clk is active for specific time after 827 * hibern8 enter. 828 */ 829 if (!enable) { 830 unsigned long gating_wait; 831 832 gating_wait = host->hba->dev_info.clk_gating_wait_us; 833 if (!gating_wait) { 834 udelay(1); 835 } else { 836 /* 837 * bRefClkGatingWaitTime defines the minimum 838 * time for which the reference clock is 839 * required by device during transition from 840 * HS-MODE to LS-MODE or HIBERN8 state. Give it 841 * more delay to be on the safe side. 842 */ 843 gating_wait += 10; 844 usleep_range(gating_wait, gating_wait + 10); 845 } 846 } 847 848 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 849 850 /* 851 * Make sure the write to ref_clk reaches the destination and 852 * not stored in a Write Buffer (WB). 853 */ 854 readl(host->dev_ref_clk_ctrl_mmio); 855 856 /* 857 * If we call hibern8 exit after this, we need to make sure that 858 * device ref_clk is stable for at least 1us before the hibern8 859 * exit command. 860 */ 861 if (enable) 862 udelay(1); 863 864 host->is_dev_ref_clk_enabled = enable; 865 } 866 } 867 868 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 869 { 870 struct device *dev = host->hba->dev; 871 int ret; 872 873 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 874 if (ret < 0) { 875 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 876 return ret; 877 } 878 879 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 880 if (ret < 0) { 881 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 882 return ret; 883 } 884 885 return 0; 886 } 887 888 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 889 { 890 struct ufs_pa_layer_attr *p = &host->dev_req_params; 891 int gear = max_t(u32, p->gear_rx, p->gear_tx); 892 int lane = max_t(u32, p->lane_rx, p->lane_tx); 893 894 if (ufshcd_is_hs_mode(p)) { 895 if (p->hs_rate == PA_HS_MODE_B) 896 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 897 else 898 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 899 } else { 900 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 901 } 902 } 903 904 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 905 { 906 struct __ufs_qcom_bw_table bw_table; 907 908 bw_table = ufs_qcom_get_bw_table(host); 909 910 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 911 } 912 913 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 914 enum ufs_notify_change_status status, 915 struct ufs_pa_layer_attr *dev_max_params, 916 struct ufs_pa_layer_attr *dev_req_params) 917 { 918 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 919 struct ufs_host_params *host_params = &host->host_params; 920 int ret = 0; 921 922 if (!dev_req_params) { 923 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 924 return -EINVAL; 925 } 926 927 switch (status) { 928 case PRE_CHANGE: 929 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); 930 if (ret) { 931 dev_err(hba->dev, "%s: failed to determine capabilities\n", 932 __func__); 933 return ret; 934 } 935 936 /* 937 * During UFS driver probe, always update the PHY gear to match the negotiated 938 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled, 939 * the second init can program the optimal PHY settings. This allows one to start 940 * the first init with either the minimum or the maximum support gear. 941 */ 942 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 943 host->phy_gear = dev_req_params->gear_tx; 944 945 /* enable the device ref clock before changing to HS mode */ 946 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 947 ufshcd_is_hs_mode(dev_req_params)) 948 ufs_qcom_dev_ref_clk_ctrl(host, true); 949 950 if (host->hw_ver.major >= 0x4) { 951 ufshcd_dme_configure_adapt(hba, 952 dev_req_params->gear_tx, 953 PA_INITIAL_ADAPT); 954 } 955 break; 956 case POST_CHANGE: 957 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, 958 dev_req_params->pwr_rx, 959 dev_req_params->hs_rate, false, false)) { 960 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 961 __func__); 962 /* 963 * we return error code at the end of the routine, 964 * but continue to configure UFS_PHY_TX_LANE_ENABLE 965 * and bus voting as usual 966 */ 967 ret = -EINVAL; 968 } 969 970 /* cache the power mode parameters to use internally */ 971 memcpy(&host->dev_req_params, 972 dev_req_params, sizeof(*dev_req_params)); 973 974 ufs_qcom_icc_update_bw(host); 975 976 /* disable the device ref clock if entered PWM mode */ 977 if (ufshcd_is_hs_mode(&hba->pwr_info) && 978 !ufshcd_is_hs_mode(dev_req_params)) 979 ufs_qcom_dev_ref_clk_ctrl(host, false); 980 break; 981 default: 982 ret = -EINVAL; 983 break; 984 } 985 986 return ret; 987 } 988 989 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 990 { 991 int err; 992 u32 pa_vs_config_reg1; 993 994 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 995 &pa_vs_config_reg1); 996 if (err) 997 return err; 998 999 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 1000 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 1001 (pa_vs_config_reg1 | (1 << 12))); 1002 } 1003 1004 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 1005 { 1006 int err = 0; 1007 1008 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 1009 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 1010 1011 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) 1012 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; 1013 1014 return err; 1015 } 1016 1017 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 1018 { 1019 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1020 1021 if (host->hw_ver.major == 0x1) 1022 return ufshci_version(1, 1); 1023 else 1024 return ufshci_version(2, 0); 1025 } 1026 1027 /** 1028 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 1029 * @hba: host controller instance 1030 * 1031 * QCOM UFS host controller might have some non standard behaviours (quirks) 1032 * than what is specified by UFSHCI specification. Advertise all such 1033 * quirks to standard UFS host controller driver so standard takes them into 1034 * account. 1035 */ 1036 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 1037 { 1038 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1039 1040 if (host->hw_ver.major == 0x01) { 1041 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 1042 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP 1043 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE; 1044 1045 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001) 1046 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR; 1047 1048 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC; 1049 } 1050 1051 if (host->hw_ver.major == 0x2) { 1052 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 1053 1054 if (!ufs_qcom_cap_qunipro(host)) 1055 /* Legacy UniPro mode still need following quirks */ 1056 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 1057 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE 1058 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); 1059 } 1060 1061 if (host->hw_ver.major > 0x3) 1062 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1063 } 1064 1065 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) 1066 { 1067 struct ufs_host_params *host_params = &host->host_params; 1068 1069 host->phy_gear = host_params->hs_tx_gear; 1070 1071 /* 1072 * For controllers whose major HW version is < 4, power up the PHY using 1073 * minimum supported gear (UFS_HS_G2). Switching to max gear will be 1074 * performed during reinit if supported. For newer controllers, whose 1075 * major HW version is >= 4, power up the PHY using max supported gear. 1076 */ 1077 if (host->hw_ver.major < 0x4) 1078 host->phy_gear = UFS_HS_G2; 1079 } 1080 1081 static void ufs_qcom_set_host_params(struct ufs_hba *hba) 1082 { 1083 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1084 struct ufs_host_params *host_params = &host->host_params; 1085 1086 ufshcd_init_host_params(host_params); 1087 1088 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 1089 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); 1090 } 1091 1092 static void ufs_qcom_set_caps(struct ufs_hba *hba) 1093 { 1094 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1095 1096 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1097 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 1098 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1099 hba->caps |= UFSHCD_CAP_WB_EN; 1100 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 1101 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 1102 1103 if (host->hw_ver.major >= 0x2) { 1104 host->caps = UFS_QCOM_CAP_QUNIPRO | 1105 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE; 1106 } 1107 } 1108 1109 /** 1110 * ufs_qcom_setup_clocks - enables/disable clocks 1111 * @hba: host controller instance 1112 * @on: If true, enable clocks else disable them. 1113 * @status: PRE_CHANGE or POST_CHANGE notify 1114 * 1115 * Return: 0 on success, non-zero on failure. 1116 */ 1117 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 1118 enum ufs_notify_change_status status) 1119 { 1120 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1121 1122 /* 1123 * In case ufs_qcom_init() is not yet done, simply ignore. 1124 * This ufs_qcom_setup_clocks() shall be called from 1125 * ufs_qcom_init() after init is done. 1126 */ 1127 if (!host) 1128 return 0; 1129 1130 switch (status) { 1131 case PRE_CHANGE: 1132 if (on) { 1133 ufs_qcom_icc_update_bw(host); 1134 } else { 1135 if (!ufs_qcom_is_link_active(hba)) { 1136 /* disable device ref_clk */ 1137 ufs_qcom_dev_ref_clk_ctrl(host, false); 1138 } 1139 } 1140 break; 1141 case POST_CHANGE: 1142 if (on) { 1143 /* enable the device ref clock for HS mode*/ 1144 if (ufshcd_is_hs_mode(&hba->pwr_info)) 1145 ufs_qcom_dev_ref_clk_ctrl(host, true); 1146 } else { 1147 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 1148 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 1149 } 1150 break; 1151 } 1152 1153 return 0; 1154 } 1155 1156 static int 1157 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 1158 { 1159 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1160 1161 ufs_qcom_assert_reset(host->hba); 1162 /* provide 1ms delay to let the reset pulse propagate. */ 1163 usleep_range(1000, 1100); 1164 return 0; 1165 } 1166 1167 static int 1168 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 1169 { 1170 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1171 1172 ufs_qcom_deassert_reset(host->hba); 1173 1174 /* 1175 * after reset deassertion, phy will need all ref clocks, 1176 * voltage, current to settle down before starting serdes. 1177 */ 1178 usleep_range(1000, 1100); 1179 return 0; 1180 } 1181 1182 static const struct reset_control_ops ufs_qcom_reset_ops = { 1183 .assert = ufs_qcom_reset_assert, 1184 .deassert = ufs_qcom_reset_deassert, 1185 }; 1186 1187 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 1188 { 1189 struct device *dev = host->hba->dev; 1190 int ret; 1191 1192 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 1193 if (IS_ERR(host->icc_ddr)) 1194 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 1195 "failed to acquire interconnect path\n"); 1196 1197 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1198 if (IS_ERR(host->icc_cpu)) 1199 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1200 "failed to acquire interconnect path\n"); 1201 1202 /* 1203 * Set Maximum bandwidth vote before initializing the UFS controller and 1204 * device. Ideally, a minimal interconnect vote would suffice for the 1205 * initialization, but a max vote would allow faster initialization. 1206 */ 1207 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1208 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1209 if (ret < 0) 1210 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1211 1212 return 0; 1213 } 1214 1215 /** 1216 * ufs_qcom_init - bind phy with controller 1217 * @hba: host controller instance 1218 * 1219 * Binds PHY with controller and powers up PHY enabling clocks 1220 * and regulators. 1221 * 1222 * Return: -EPROBE_DEFER if binding fails, returns negative error 1223 * on phy power up failure and returns zero on success. 1224 */ 1225 static int ufs_qcom_init(struct ufs_hba *hba) 1226 { 1227 int err; 1228 struct device *dev = hba->dev; 1229 struct platform_device *pdev = to_platform_device(dev); 1230 struct ufs_qcom_host *host; 1231 struct resource *res; 1232 struct ufs_clk_info *clki; 1233 1234 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1235 if (!host) { 1236 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); 1237 return -ENOMEM; 1238 } 1239 1240 /* Make a two way bind between the qcom host and the hba */ 1241 host->hba = hba; 1242 ufshcd_set_variant(hba, host); 1243 1244 /* Setup the optional reset control of HCI */ 1245 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1246 if (IS_ERR(host->core_reset)) { 1247 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1248 "Failed to get reset control\n"); 1249 goto out_variant_clear; 1250 } 1251 1252 /* Fire up the reset controller. Failure here is non-fatal. */ 1253 host->rcdev.of_node = dev->of_node; 1254 host->rcdev.ops = &ufs_qcom_reset_ops; 1255 host->rcdev.owner = dev->driver->owner; 1256 host->rcdev.nr_resets = 1; 1257 err = devm_reset_controller_register(dev, &host->rcdev); 1258 if (err) 1259 dev_warn(dev, "Failed to register reset controller\n"); 1260 1261 if (!has_acpi_companion(dev)) { 1262 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1263 if (IS_ERR(host->generic_phy)) { 1264 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1265 goto out_variant_clear; 1266 } 1267 } 1268 1269 err = ufs_qcom_icc_init(host); 1270 if (err) 1271 goto out_variant_clear; 1272 1273 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1274 GPIOD_OUT_HIGH); 1275 if (IS_ERR(host->device_reset)) { 1276 err = PTR_ERR(host->device_reset); 1277 if (err != -EPROBE_DEFER) 1278 dev_err(dev, "failed to acquire reset gpio: %d\n", err); 1279 goto out_variant_clear; 1280 } 1281 1282 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1283 &host->hw_ver.minor, &host->hw_ver.step); 1284 1285 /* 1286 * for newer controllers, device reference clock control bit has 1287 * moved inside UFS controller register address space itself. 1288 */ 1289 if (host->hw_ver.major >= 0x02) { 1290 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1291 host->dev_ref_clk_en_mask = BIT(26); 1292 } else { 1293 /* "dev_ref_clk_ctrl_mem" is optional resource */ 1294 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1295 "dev_ref_clk_ctrl_mem"); 1296 if (res) { 1297 host->dev_ref_clk_ctrl_mmio = 1298 devm_ioremap_resource(dev, res); 1299 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) 1300 host->dev_ref_clk_ctrl_mmio = NULL; 1301 host->dev_ref_clk_en_mask = BIT(5); 1302 } 1303 } 1304 1305 list_for_each_entry(clki, &hba->clk_list_head, list) { 1306 if (!strcmp(clki->name, "core_clk_unipro")) 1307 clki->keep_link_active = true; 1308 } 1309 1310 err = ufs_qcom_init_lane_clks(host); 1311 if (err) 1312 goto out_variant_clear; 1313 1314 ufs_qcom_set_caps(hba); 1315 ufs_qcom_advertise_quirks(hba); 1316 ufs_qcom_set_host_params(hba); 1317 ufs_qcom_set_phy_gear(host); 1318 1319 err = ufs_qcom_ice_init(host); 1320 if (err) 1321 goto out_variant_clear; 1322 1323 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1324 1325 if (hba->dev->id < MAX_UFS_QCOM_HOSTS) 1326 ufs_qcom_hosts[hba->dev->id] = host; 1327 1328 ufs_qcom_get_default_testbus_cfg(host); 1329 err = ufs_qcom_testbus_config(host); 1330 if (err) 1331 /* Failure is non-fatal */ 1332 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1333 __func__, err); 1334 1335 return 0; 1336 1337 out_variant_clear: 1338 ufshcd_set_variant(hba, NULL); 1339 1340 return err; 1341 } 1342 1343 static void ufs_qcom_exit(struct ufs_hba *hba) 1344 { 1345 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1346 1347 ufs_qcom_disable_lane_clks(host); 1348 phy_power_off(host->generic_phy); 1349 phy_exit(host->generic_phy); 1350 } 1351 1352 /** 1353 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles 1354 * 1355 * @hba: host controller instance 1356 * @cycles_in_1us: No of cycles in 1us to be configured 1357 * 1358 * Returns error if dme get/set configuration for 40ns fails 1359 * and returns zero on success. 1360 */ 1361 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, 1362 u32 cycles_in_1us) 1363 { 1364 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1365 u32 cycles_in_40ns; 1366 u32 reg; 1367 int err; 1368 1369 /* 1370 * UFS host controller V4.0.0 onwards needs to program 1371 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed 1372 * frequency of unipro core clk of UFS host controller. 1373 */ 1374 if (host->hw_ver.major < 4) 1375 return 0; 1376 1377 /* 1378 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not 1379 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will 1380 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware 1381 * specification expect to be 16. Hence use exact hardware spec 1382 * mandated value for cycles_in_40ns instead of calculating using 1383 * generic formulae. 1384 */ 1385 switch (cycles_in_1us) { 1386 case UNIPRO_CORE_CLK_FREQ_403_MHZ: 1387 cycles_in_40ns = 16; 1388 break; 1389 case UNIPRO_CORE_CLK_FREQ_300_MHZ: 1390 cycles_in_40ns = 12; 1391 break; 1392 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ: 1393 cycles_in_40ns = 8; 1394 break; 1395 case UNIPRO_CORE_CLK_FREQ_150_MHZ: 1396 cycles_in_40ns = 6; 1397 break; 1398 case UNIPRO_CORE_CLK_FREQ_100_MHZ: 1399 cycles_in_40ns = 4; 1400 break; 1401 case UNIPRO_CORE_CLK_FREQ_75_MHZ: 1402 cycles_in_40ns = 3; 1403 break; 1404 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ: 1405 cycles_in_40ns = 2; 1406 break; 1407 default: 1408 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", 1409 cycles_in_1us); 1410 return -EINVAL; 1411 } 1412 1413 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); 1414 if (err) 1415 return err; 1416 1417 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; 1418 reg |= cycles_in_40ns; 1419 1420 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); 1421 } 1422 1423 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) 1424 { 1425 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1426 struct list_head *head = &hba->clk_list_head; 1427 struct ufs_clk_info *clki; 1428 u32 cycles_in_1us; 1429 u32 core_clk_ctrl_reg; 1430 int err; 1431 1432 list_for_each_entry(clki, head, list) { 1433 if (!IS_ERR_OR_NULL(clki->clk) && 1434 !strcmp(clki->name, "core_clk_unipro")) { 1435 if (is_scale_up) 1436 cycles_in_1us = ceil(clki->max_freq, (1000 * 1000)); 1437 else 1438 cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000)); 1439 break; 1440 } 1441 } 1442 1443 err = ufshcd_dme_get(hba, 1444 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1445 &core_clk_ctrl_reg); 1446 if (err) 1447 return err; 1448 1449 /* Bit mask is different for UFS host controller V4.0.0 onwards */ 1450 if (host->hw_ver.major >= 4) { 1451 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us)) 1452 return -ERANGE; 1453 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4; 1454 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us); 1455 } else { 1456 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us)) 1457 return -ERANGE; 1458 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK; 1459 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); 1460 } 1461 1462 /* Clear CORE_CLK_DIV_EN */ 1463 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1464 1465 err = ufshcd_dme_set(hba, 1466 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1467 core_clk_ctrl_reg); 1468 if (err) 1469 return err; 1470 1471 /* Configure unipro core clk 40ns attribute */ 1472 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); 1473 } 1474 1475 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) 1476 { 1477 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1478 struct ufs_pa_layer_attr *attr = &host->dev_req_params; 1479 int ret; 1480 1481 if (!ufs_qcom_cap_qunipro(host)) 1482 return 0; 1483 1484 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx, 1485 attr->hs_rate, false, true); 1486 if (ret) { 1487 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); 1488 return ret; 1489 } 1490 /* set unipro core clock attributes and clear clock divider */ 1491 return ufs_qcom_set_core_clk_ctrl(hba, true); 1492 } 1493 1494 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1495 { 1496 return 0; 1497 } 1498 1499 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1500 { 1501 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1502 int err; 1503 u32 core_clk_ctrl_reg; 1504 1505 if (!ufs_qcom_cap_qunipro(host)) 1506 return 0; 1507 1508 err = ufshcd_dme_get(hba, 1509 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1510 &core_clk_ctrl_reg); 1511 1512 /* make sure CORE_CLK_DIV_EN is cleared */ 1513 if (!err && 1514 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1515 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1516 err = ufshcd_dme_set(hba, 1517 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1518 core_clk_ctrl_reg); 1519 } 1520 1521 return err; 1522 } 1523 1524 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) 1525 { 1526 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1527 1528 if (!ufs_qcom_cap_qunipro(host)) 1529 return 0; 1530 1531 /* set unipro core clock attributes and clear clock divider */ 1532 return ufs_qcom_set_core_clk_ctrl(hba, false); 1533 } 1534 1535 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, 1536 bool scale_up, enum ufs_notify_change_status status) 1537 { 1538 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1539 int err = 0; 1540 1541 /* check the host controller state before sending hibern8 cmd */ 1542 if (!ufshcd_is_hba_active(hba)) 1543 return 0; 1544 1545 if (status == PRE_CHANGE) { 1546 err = ufshcd_uic_hibern8_enter(hba); 1547 if (err) 1548 return err; 1549 if (scale_up) 1550 err = ufs_qcom_clk_scale_up_pre_change(hba); 1551 else 1552 err = ufs_qcom_clk_scale_down_pre_change(hba); 1553 if (err) 1554 ufshcd_uic_hibern8_exit(hba); 1555 1556 } else { 1557 if (scale_up) 1558 err = ufs_qcom_clk_scale_up_post_change(hba); 1559 else 1560 err = ufs_qcom_clk_scale_down_post_change(hba); 1561 1562 1563 if (err) { 1564 ufshcd_uic_hibern8_exit(hba); 1565 return err; 1566 } 1567 1568 ufs_qcom_icc_update_bw(host); 1569 ufshcd_uic_hibern8_exit(hba); 1570 } 1571 1572 return 0; 1573 } 1574 1575 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1576 { 1577 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1578 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1579 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1580 } 1581 1582 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1583 { 1584 /* provide a legal default configuration */ 1585 host->testbus.select_major = TSTBUS_UNIPRO; 1586 host->testbus.select_minor = 37; 1587 } 1588 1589 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1590 { 1591 if (host->testbus.select_major >= TSTBUS_MAX) { 1592 dev_err(host->hba->dev, 1593 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1594 __func__, host->testbus.select_major); 1595 return false; 1596 } 1597 1598 return true; 1599 } 1600 1601 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1602 { 1603 int reg; 1604 int offset; 1605 u32 mask = TEST_BUS_SUB_SEL_MASK; 1606 1607 if (!host) 1608 return -EINVAL; 1609 1610 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1611 return -EPERM; 1612 1613 switch (host->testbus.select_major) { 1614 case TSTBUS_UAWM: 1615 reg = UFS_TEST_BUS_CTRL_0; 1616 offset = 24; 1617 break; 1618 case TSTBUS_UARM: 1619 reg = UFS_TEST_BUS_CTRL_0; 1620 offset = 16; 1621 break; 1622 case TSTBUS_TXUC: 1623 reg = UFS_TEST_BUS_CTRL_0; 1624 offset = 8; 1625 break; 1626 case TSTBUS_RXUC: 1627 reg = UFS_TEST_BUS_CTRL_0; 1628 offset = 0; 1629 break; 1630 case TSTBUS_DFC: 1631 reg = UFS_TEST_BUS_CTRL_1; 1632 offset = 24; 1633 break; 1634 case TSTBUS_TRLUT: 1635 reg = UFS_TEST_BUS_CTRL_1; 1636 offset = 16; 1637 break; 1638 case TSTBUS_TMRLUT: 1639 reg = UFS_TEST_BUS_CTRL_1; 1640 offset = 8; 1641 break; 1642 case TSTBUS_OCSC: 1643 reg = UFS_TEST_BUS_CTRL_1; 1644 offset = 0; 1645 break; 1646 case TSTBUS_WRAPPER: 1647 reg = UFS_TEST_BUS_CTRL_2; 1648 offset = 16; 1649 break; 1650 case TSTBUS_COMBINED: 1651 reg = UFS_TEST_BUS_CTRL_2; 1652 offset = 8; 1653 break; 1654 case TSTBUS_UTP_HCI: 1655 reg = UFS_TEST_BUS_CTRL_2; 1656 offset = 0; 1657 break; 1658 case TSTBUS_UNIPRO: 1659 reg = UFS_UNIPRO_CFG; 1660 offset = 20; 1661 mask = 0xFFF; 1662 break; 1663 /* 1664 * No need for a default case, since 1665 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 1666 * is legal 1667 */ 1668 } 1669 mask <<= offset; 1670 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 1671 (u32)host->testbus.select_major << 19, 1672 REG_UFS_CFG1); 1673 ufshcd_rmwl(host->hba, mask, 1674 (u32)host->testbus.select_minor << offset, 1675 reg); 1676 ufs_qcom_enable_test_bus(host); 1677 /* 1678 * Make sure the test bus configuration is 1679 * committed before returning. 1680 */ 1681 mb(); 1682 1683 return 0; 1684 } 1685 1686 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 1687 { 1688 u32 reg; 1689 struct ufs_qcom_host *host; 1690 1691 host = ufshcd_get_variant(hba); 1692 1693 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 1694 "HCI Vendor Specific Registers "); 1695 1696 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 1697 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 1698 1699 reg = ufshcd_readl(hba, REG_UFS_CFG1); 1700 reg |= UTP_DBG_RAMS_EN; 1701 ufshcd_writel(hba, reg, REG_UFS_CFG1); 1702 1703 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 1704 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 1705 1706 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 1707 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 1708 1709 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 1710 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 1711 1712 /* clear bit 17 - UTP_DBG_RAMS_EN */ 1713 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 1714 1715 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 1716 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 1717 1718 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 1719 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 1720 1721 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 1722 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 1723 1724 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 1725 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 1726 1727 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 1728 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 1729 1730 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 1731 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 1732 1733 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 1734 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 1735 } 1736 1737 /** 1738 * ufs_qcom_device_reset() - toggle the (optional) device reset line 1739 * @hba: per-adapter instance 1740 * 1741 * Toggles the (optional) reset line to reset the attached device. 1742 */ 1743 static int ufs_qcom_device_reset(struct ufs_hba *hba) 1744 { 1745 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1746 1747 /* reset gpio is optional */ 1748 if (!host->device_reset) 1749 return -EOPNOTSUPP; 1750 1751 /* 1752 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 1753 * be on the safe side. 1754 */ 1755 ufs_qcom_device_reset_ctrl(hba, true); 1756 usleep_range(10, 15); 1757 1758 ufs_qcom_device_reset_ctrl(hba, false); 1759 usleep_range(10, 15); 1760 1761 return 0; 1762 } 1763 1764 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) 1765 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1766 struct devfreq_dev_profile *p, 1767 struct devfreq_simple_ondemand_data *d) 1768 { 1769 p->polling_ms = 60; 1770 p->timer = DEVFREQ_TIMER_DELAYED; 1771 d->upthreshold = 70; 1772 d->downdifferential = 5; 1773 } 1774 #else 1775 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1776 struct devfreq_dev_profile *p, 1777 struct devfreq_simple_ondemand_data *data) 1778 { 1779 } 1780 #endif 1781 1782 static void ufs_qcom_reinit_notify(struct ufs_hba *hba) 1783 { 1784 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1785 1786 phy_power_off(host->generic_phy); 1787 } 1788 1789 /* Resources */ 1790 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { 1791 {.name = "ufs_mem",}, 1792 {.name = "mcq",}, 1793 /* Submission Queue DAO */ 1794 {.name = "mcq_sqd",}, 1795 /* Submission Queue Interrupt Status */ 1796 {.name = "mcq_sqis",}, 1797 /* Completion Queue DAO */ 1798 {.name = "mcq_cqd",}, 1799 /* Completion Queue Interrupt Status */ 1800 {.name = "mcq_cqis",}, 1801 /* MCQ vendor specific */ 1802 {.name = "mcq_vs",}, 1803 }; 1804 1805 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 1806 { 1807 struct platform_device *pdev = to_platform_device(hba->dev); 1808 struct ufshcd_res_info *res; 1809 struct resource *res_mem, *res_mcq; 1810 int i, ret = 0; 1811 1812 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); 1813 1814 for (i = 0; i < RES_MAX; i++) { 1815 res = &hba->res[i]; 1816 res->resource = platform_get_resource_byname(pdev, 1817 IORESOURCE_MEM, 1818 res->name); 1819 if (!res->resource) { 1820 dev_info(hba->dev, "Resource %s not provided\n", res->name); 1821 if (i == RES_UFS) 1822 return -ENOMEM; 1823 continue; 1824 } else if (i == RES_UFS) { 1825 res_mem = res->resource; 1826 res->base = hba->mmio_base; 1827 continue; 1828 } 1829 1830 res->base = devm_ioremap_resource(hba->dev, res->resource); 1831 if (IS_ERR(res->base)) { 1832 dev_err(hba->dev, "Failed to map res %s, err=%d\n", 1833 res->name, (int)PTR_ERR(res->base)); 1834 ret = PTR_ERR(res->base); 1835 res->base = NULL; 1836 return ret; 1837 } 1838 } 1839 1840 /* MCQ resource provided in DT */ 1841 res = &hba->res[RES_MCQ]; 1842 /* Bail if MCQ resource is provided */ 1843 if (res->base) 1844 goto out; 1845 1846 /* Explicitly allocate MCQ resource from ufs_mem */ 1847 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); 1848 if (!res_mcq) 1849 return -ENOMEM; 1850 1851 res_mcq->start = res_mem->start + 1852 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); 1853 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; 1854 res_mcq->flags = res_mem->flags; 1855 res_mcq->name = "mcq"; 1856 1857 ret = insert_resource(&iomem_resource, res_mcq); 1858 if (ret) { 1859 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", 1860 ret); 1861 return ret; 1862 } 1863 1864 res->base = devm_ioremap_resource(hba->dev, res_mcq); 1865 if (IS_ERR(res->base)) { 1866 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", 1867 (int)PTR_ERR(res->base)); 1868 ret = PTR_ERR(res->base); 1869 goto ioremap_err; 1870 } 1871 1872 out: 1873 hba->mcq_base = res->base; 1874 return 0; 1875 ioremap_err: 1876 res->base = NULL; 1877 remove_resource(res_mcq); 1878 return ret; 1879 } 1880 1881 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 1882 { 1883 struct ufshcd_res_info *mem_res, *sqdao_res; 1884 struct ufshcd_mcq_opr_info_t *opr; 1885 int i; 1886 1887 mem_res = &hba->res[RES_UFS]; 1888 sqdao_res = &hba->res[RES_MCQ_SQD]; 1889 1890 if (!mem_res->base || !sqdao_res->base) 1891 return -EINVAL; 1892 1893 for (i = 0; i < OPR_MAX; i++) { 1894 opr = &hba->mcq_opr[i]; 1895 opr->offset = sqdao_res->resource->start - 1896 mem_res->resource->start + 0x40 * i; 1897 opr->stride = 0x100; 1898 opr->base = sqdao_res->base + 0x40 * i; 1899 } 1900 1901 return 0; 1902 } 1903 1904 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 1905 { 1906 /* Qualcomm HC supports up to 64 */ 1907 return MAX_SUPP_MAC; 1908 } 1909 1910 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 1911 unsigned long *ocqs) 1912 { 1913 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; 1914 1915 if (!mcq_vs_res->base) 1916 return -EINVAL; 1917 1918 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); 1919 1920 return 0; 1921 } 1922 1923 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 1924 { 1925 struct device *dev = msi_desc_to_dev(desc); 1926 struct ufs_hba *hba = dev_get_drvdata(dev); 1927 1928 ufshcd_mcq_config_esi(hba, msg); 1929 } 1930 1931 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 1932 { 1933 struct msi_desc *desc = data; 1934 struct device *dev = msi_desc_to_dev(desc); 1935 struct ufs_hba *hba = dev_get_drvdata(dev); 1936 u32 id = desc->msi_index; 1937 struct ufs_hw_queue *hwq = &hba->uhq[id]; 1938 1939 ufshcd_mcq_write_cqis(hba, 0x1, id); 1940 ufshcd_mcq_poll_cqe_lock(hba, hwq); 1941 1942 return IRQ_HANDLED; 1943 } 1944 1945 static int ufs_qcom_config_esi(struct ufs_hba *hba) 1946 { 1947 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1948 struct msi_desc *desc; 1949 struct msi_desc *failed_desc = NULL; 1950 int nr_irqs, ret; 1951 1952 if (host->esi_enabled) 1953 return 0; 1954 1955 /* 1956 * 1. We only handle CQs as of now. 1957 * 2. Poll queues do not need ESI. 1958 */ 1959 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 1960 ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs, 1961 ufs_qcom_write_msi_msg); 1962 if (ret) { 1963 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); 1964 goto out; 1965 } 1966 1967 msi_lock_descs(hba->dev); 1968 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1969 ret = devm_request_irq(hba->dev, desc->irq, 1970 ufs_qcom_mcq_esi_handler, 1971 IRQF_SHARED, "qcom-mcq-esi", desc); 1972 if (ret) { 1973 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", 1974 __func__, desc->irq, ret); 1975 failed_desc = desc; 1976 break; 1977 } 1978 } 1979 msi_unlock_descs(hba->dev); 1980 1981 if (ret) { 1982 /* Rewind */ 1983 msi_lock_descs(hba->dev); 1984 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1985 if (desc == failed_desc) 1986 break; 1987 devm_free_irq(hba->dev, desc->irq, hba); 1988 } 1989 msi_unlock_descs(hba->dev); 1990 platform_msi_domain_free_irqs(hba->dev); 1991 } else { 1992 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && 1993 host->hw_ver.step == 0) { 1994 ufshcd_writel(hba, 1995 ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000, 1996 REG_UFS_CFG3); 1997 } 1998 ufshcd_mcq_enable_esi(hba); 1999 } 2000 2001 out: 2002 if (!ret) 2003 host->esi_enabled = true; 2004 2005 return ret; 2006 } 2007 2008 /* 2009 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 2010 * 2011 * The variant operations configure the necessary controller and PHY 2012 * handshake during initialization. 2013 */ 2014 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 2015 .name = "qcom", 2016 .init = ufs_qcom_init, 2017 .exit = ufs_qcom_exit, 2018 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 2019 .clk_scale_notify = ufs_qcom_clk_scale_notify, 2020 .setup_clocks = ufs_qcom_setup_clocks, 2021 .hce_enable_notify = ufs_qcom_hce_enable_notify, 2022 .link_startup_notify = ufs_qcom_link_startup_notify, 2023 .pwr_change_notify = ufs_qcom_pwr_change_notify, 2024 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 2025 .suspend = ufs_qcom_suspend, 2026 .resume = ufs_qcom_resume, 2027 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 2028 .device_reset = ufs_qcom_device_reset, 2029 .config_scaling_param = ufs_qcom_config_scaling_param, 2030 .program_key = ufs_qcom_ice_program_key, 2031 .reinit_notify = ufs_qcom_reinit_notify, 2032 .mcq_config_resource = ufs_qcom_mcq_config_resource, 2033 .get_hba_mac = ufs_qcom_get_hba_mac, 2034 .op_runtime_config = ufs_qcom_op_runtime_config, 2035 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 2036 .config_esi = ufs_qcom_config_esi, 2037 }; 2038 2039 /** 2040 * ufs_qcom_probe - probe routine of the driver 2041 * @pdev: pointer to Platform device handle 2042 * 2043 * Return: zero for success and non-zero for failure. 2044 */ 2045 static int ufs_qcom_probe(struct platform_device *pdev) 2046 { 2047 int err; 2048 struct device *dev = &pdev->dev; 2049 2050 /* Perform generic probe */ 2051 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); 2052 if (err) 2053 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 2054 2055 return 0; 2056 } 2057 2058 /** 2059 * ufs_qcom_remove - set driver_data of the device to NULL 2060 * @pdev: pointer to platform device handle 2061 * 2062 * Always returns 0 2063 */ 2064 static void ufs_qcom_remove(struct platform_device *pdev) 2065 { 2066 struct ufs_hba *hba = platform_get_drvdata(pdev); 2067 2068 pm_runtime_get_sync(&(pdev)->dev); 2069 ufshcd_remove(hba); 2070 platform_msi_domain_free_irqs(hba->dev); 2071 } 2072 2073 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 2074 { .compatible = "qcom,ufshc"}, 2075 {}, 2076 }; 2077 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 2078 2079 #ifdef CONFIG_ACPI 2080 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 2081 { "QCOM24A5" }, 2082 { }, 2083 }; 2084 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 2085 #endif 2086 2087 static const struct dev_pm_ops ufs_qcom_pm_ops = { 2088 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 2089 .prepare = ufshcd_suspend_prepare, 2090 .complete = ufshcd_resume_complete, 2091 #ifdef CONFIG_PM_SLEEP 2092 .suspend = ufshcd_system_suspend, 2093 .resume = ufshcd_system_resume, 2094 .freeze = ufshcd_system_freeze, 2095 .restore = ufshcd_system_restore, 2096 .thaw = ufshcd_system_thaw, 2097 #endif 2098 }; 2099 2100 static struct platform_driver ufs_qcom_pltform = { 2101 .probe = ufs_qcom_probe, 2102 .remove_new = ufs_qcom_remove, 2103 .driver = { 2104 .name = "ufshcd-qcom", 2105 .pm = &ufs_qcom_pm_ops, 2106 .of_match_table = of_match_ptr(ufs_qcom_of_match), 2107 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 2108 }, 2109 }; 2110 module_platform_driver(ufs_qcom_pltform); 2111 2112 MODULE_LICENSE("GPL v2"); 2113