1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/devfreq.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/interconnect.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/reset-controller.h> 17 #include <linux/time.h> 18 19 #include <soc/qcom/ice.h> 20 21 #include <ufs/ufshcd.h> 22 #include <ufs/ufshci.h> 23 #include <ufs/ufs_quirks.h> 24 #include <ufs/unipro.h> 25 #include "ufshcd-pltfrm.h" 26 #include "ufs-qcom.h" 27 28 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 29 #define MCQ_QCFGPTR_UNIT 0x200 30 #define MCQ_SQATTR_OFFSET(c) \ 31 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 32 #define MCQ_QCFG_SIZE 0x40 33 34 enum { 35 TSTBUS_UAWM, 36 TSTBUS_UARM, 37 TSTBUS_TXUC, 38 TSTBUS_RXUC, 39 TSTBUS_DFC, 40 TSTBUS_TRLUT, 41 TSTBUS_TMRLUT, 42 TSTBUS_OCSC, 43 TSTBUS_UTP_HCI, 44 TSTBUS_COMBINED, 45 TSTBUS_WRAPPER, 46 TSTBUS_UNIPRO, 47 TSTBUS_MAX, 48 }; 49 50 #define QCOM_UFS_MAX_GEAR 5 51 #define QCOM_UFS_MAX_LANE 2 52 53 enum { 54 MODE_MIN, 55 MODE_PWM, 56 MODE_HS_RA, 57 MODE_HS_RB, 58 MODE_MAX, 59 }; 60 61 static const struct __ufs_qcom_bw_table { 62 u32 mem_bw; 63 u32 cfg_bw; 64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 65 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 66 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 67 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 68 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 69 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 70 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 }, 71 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 72 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 73 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 74 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 75 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 }, 76 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 77 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 78 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 79 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 80 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 81 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 82 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 83 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 84 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 85 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 86 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 87 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 88 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 89 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 90 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 91 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 92 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 93 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 94 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 95 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 96 [MODE_MAX][0][0] = { 7643136, 307200 }, 97 }; 98 99 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 100 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up); 101 102 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 103 { 104 return container_of(rcd, struct ufs_qcom_host, rcdev); 105 } 106 107 #ifdef CONFIG_SCSI_UFS_CRYPTO 108 109 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 110 { 111 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 112 qcom_ice_enable(host->ice); 113 } 114 115 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 116 { 117 struct ufs_hba *hba = host->hba; 118 struct device *dev = hba->dev; 119 struct qcom_ice *ice; 120 121 ice = of_qcom_ice_get(dev); 122 if (ice == ERR_PTR(-EOPNOTSUPP)) { 123 dev_warn(dev, "Disabling inline encryption support\n"); 124 ice = NULL; 125 } 126 127 if (IS_ERR_OR_NULL(ice)) 128 return PTR_ERR_OR_ZERO(ice); 129 130 host->ice = ice; 131 hba->caps |= UFSHCD_CAP_CRYPTO; 132 133 return 0; 134 } 135 136 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 137 { 138 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 139 return qcom_ice_resume(host->ice); 140 141 return 0; 142 } 143 144 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 145 { 146 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 147 return qcom_ice_suspend(host->ice); 148 149 return 0; 150 } 151 152 static int ufs_qcom_ice_program_key(struct ufs_hba *hba, 153 const union ufs_crypto_cfg_entry *cfg, 154 int slot) 155 { 156 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 157 union ufs_crypto_cap_entry cap; 158 bool config_enable = 159 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; 160 161 /* Only AES-256-XTS has been tested so far. */ 162 cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; 163 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || 164 cap.key_size != UFS_CRYPTO_KEY_SIZE_256) 165 return -EOPNOTSUPP; 166 167 if (config_enable) 168 return qcom_ice_program_key(host->ice, 169 QCOM_ICE_CRYPTO_ALG_AES_XTS, 170 QCOM_ICE_CRYPTO_KEY_SIZE_256, 171 cfg->crypto_key, 172 cfg->data_unit_size, slot); 173 else 174 return qcom_ice_evict_key(host->ice, slot); 175 } 176 177 #else 178 179 #define ufs_qcom_ice_program_key NULL 180 181 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 182 { 183 } 184 185 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 186 { 187 return 0; 188 } 189 190 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 191 { 192 return 0; 193 } 194 195 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 196 { 197 return 0; 198 } 199 #endif 200 201 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 202 { 203 if (!host->is_lane_clks_enabled) 204 return; 205 206 clk_bulk_disable_unprepare(host->num_clks, host->clks); 207 208 host->is_lane_clks_enabled = false; 209 } 210 211 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 212 { 213 int err; 214 215 err = clk_bulk_prepare_enable(host->num_clks, host->clks); 216 if (err) 217 return err; 218 219 host->is_lane_clks_enabled = true; 220 221 return 0; 222 } 223 224 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 225 { 226 int err; 227 struct device *dev = host->hba->dev; 228 229 if (has_acpi_companion(dev)) 230 return 0; 231 232 err = devm_clk_bulk_get_all(dev, &host->clks); 233 if (err <= 0) 234 return err; 235 236 host->num_clks = err; 237 238 return 0; 239 } 240 241 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 242 { 243 int err; 244 u32 tx_fsm_val; 245 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 246 247 do { 248 err = ufshcd_dme_get(hba, 249 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 250 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 251 &tx_fsm_val); 252 if (err || tx_fsm_val == TX_FSM_HIBERN8) 253 break; 254 255 /* sleep for max. 200us */ 256 usleep_range(100, 200); 257 } while (time_before(jiffies, timeout)); 258 259 /* 260 * we might have scheduled out for long during polling so 261 * check the state again. 262 */ 263 if (time_after(jiffies, timeout)) 264 err = ufshcd_dme_get(hba, 265 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 266 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 267 &tx_fsm_val); 268 269 if (err) { 270 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 271 __func__, err); 272 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 273 err = tx_fsm_val; 274 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 275 __func__, err); 276 } 277 278 return err; 279 } 280 281 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 282 { 283 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); 284 285 if (host->hw_ver.major >= 0x05) 286 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 287 } 288 289 /* 290 * ufs_qcom_host_reset - reset host controller and PHY 291 */ 292 static int ufs_qcom_host_reset(struct ufs_hba *hba) 293 { 294 int ret; 295 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 296 bool reenable_intr; 297 298 if (!host->core_reset) 299 return 0; 300 301 reenable_intr = hba->is_irq_enabled; 302 ufshcd_disable_irq(hba); 303 304 ret = reset_control_assert(host->core_reset); 305 if (ret) { 306 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 307 __func__, ret); 308 return ret; 309 } 310 311 /* 312 * The hardware requirement for delay between assert/deassert 313 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 314 * ~125us (4/32768). To be on the safe side add 200us delay. 315 */ 316 usleep_range(200, 210); 317 318 ret = reset_control_deassert(host->core_reset); 319 if (ret) { 320 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 321 __func__, ret); 322 return ret; 323 } 324 325 usleep_range(1000, 1100); 326 327 if (reenable_intr) 328 ufshcd_enable_irq(hba); 329 330 return 0; 331 } 332 333 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 334 { 335 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 336 337 if (host->hw_ver.major >= 0x4) 338 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 339 340 /* Default is HS-G3 */ 341 return UFS_HS_G3; 342 } 343 344 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 345 { 346 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 347 struct ufs_host_params *host_params = &host->host_params; 348 struct phy *phy = host->generic_phy; 349 enum phy_mode mode; 350 int ret; 351 352 /* 353 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. 354 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, 355 * so that the subsequent power mode change shall stick to Rate-A. 356 */ 357 if (host->hw_ver.major == 0x5) { 358 if (host->phy_gear == UFS_HS_G5) 359 host_params->hs_rate = PA_HS_MODE_A; 360 else 361 host_params->hs_rate = PA_HS_MODE_B; 362 } 363 364 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; 365 366 /* Reset UFS Host Controller and PHY */ 367 ret = ufs_qcom_host_reset(hba); 368 if (ret) 369 return ret; 370 371 /* phy initialization - calibrate the phy */ 372 ret = phy_init(phy); 373 if (ret) { 374 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 375 __func__, ret); 376 return ret; 377 } 378 379 ret = phy_set_mode_ext(phy, mode, host->phy_gear); 380 if (ret) 381 goto out_disable_phy; 382 383 /* power on phy - start serdes and phy's power and clocks */ 384 ret = phy_power_on(phy); 385 if (ret) { 386 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 387 __func__, ret); 388 goto out_disable_phy; 389 } 390 391 ufs_qcom_select_unipro_mode(host); 392 393 return 0; 394 395 out_disable_phy: 396 phy_exit(phy); 397 398 return ret; 399 } 400 401 /* 402 * The UTP controller has a number of internal clock gating cells (CGCs). 403 * Internal hardware sub-modules within the UTP controller control the CGCs. 404 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 405 * in a specific operation, UTP controller CGCs are by default disabled and 406 * this function enables them (after every UFS link startup) to save some power 407 * leakage. 408 */ 409 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 410 { 411 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, 412 REG_UFS_CFG2); 413 414 /* Ensure that HW clock gating is enabled before next operations */ 415 ufshcd_readl(hba, REG_UFS_CFG2); 416 } 417 418 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 419 enum ufs_notify_change_status status) 420 { 421 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 422 int err; 423 424 switch (status) { 425 case PRE_CHANGE: 426 err = ufs_qcom_power_up_sequence(hba); 427 if (err) 428 return err; 429 430 /* 431 * The PHY PLL output is the source of tx/rx lane symbol 432 * clocks, hence, enable the lane clocks only after PHY 433 * is initialized. 434 */ 435 err = ufs_qcom_enable_lane_clks(host); 436 break; 437 case POST_CHANGE: 438 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 439 err = ufs_qcom_check_hibern8(hba); 440 ufs_qcom_enable_hw_clk_gating(hba); 441 ufs_qcom_ice_enable(host); 442 break; 443 default: 444 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 445 err = -EINVAL; 446 break; 447 } 448 return err; 449 } 450 451 /** 452 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers 453 * 454 * @hba: host controller instance 455 * @gear: Current operating gear 456 * @hs: current power mode 457 * @rate: current operating rate (A or B) 458 * @update_link_startup_timer: indicate if link_start ongoing 459 * @is_pre_scale_up: flag to check if pre scale up condition. 460 * Return: zero for success and non-zero in case of a failure. 461 */ 462 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, 463 u32 hs, u32 rate, bool update_link_startup_timer, 464 bool is_pre_scale_up) 465 { 466 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 467 struct ufs_clk_info *clki; 468 unsigned long core_clk_rate = 0; 469 u32 core_clk_cycles_per_us; 470 471 /* 472 * UTP controller uses SYS1CLK_1US_REG register for Interrupt 473 * Aggregation logic. 474 * It is mandatory to write SYS1CLK_1US_REG register on UFS host 475 * controller V4.0.0 onwards. 476 */ 477 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) 478 return 0; 479 480 if (gear == 0) { 481 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); 482 return -EINVAL; 483 } 484 485 list_for_each_entry(clki, &hba->clk_list_head, list) { 486 if (!strcmp(clki->name, "core_clk")) { 487 if (is_pre_scale_up) 488 core_clk_rate = clki->max_freq; 489 else 490 core_clk_rate = clk_get_rate(clki->clk); 491 break; 492 } 493 494 } 495 496 /* If frequency is smaller than 1MHz, set to 1MHz */ 497 if (core_clk_rate < DEFAULT_CLK_RATE_HZ) 498 core_clk_rate = DEFAULT_CLK_RATE_HZ; 499 500 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; 501 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 502 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 503 /* 504 * make sure above write gets applied before we return from 505 * this function. 506 */ 507 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US); 508 } 509 510 return 0; 511 } 512 513 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 514 enum ufs_notify_change_status status) 515 { 516 int err = 0; 517 518 switch (status) { 519 case PRE_CHANGE: 520 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, 521 0, true, false)) { 522 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 523 __func__); 524 return -EINVAL; 525 } 526 527 err = ufs_qcom_set_core_clk_ctrl(hba, true); 528 if (err) 529 dev_err(hba->dev, "cfg core clk ctrl failed\n"); 530 /* 531 * Some UFS devices (and may be host) have issues if LCC is 532 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 533 * before link startup which will make sure that both host 534 * and device TX LCC are disabled once link startup is 535 * completed. 536 */ 537 err = ufshcd_disable_host_tx_lcc(hba); 538 539 break; 540 default: 541 break; 542 } 543 544 return err; 545 } 546 547 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 548 { 549 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 550 551 /* reset gpio is optional */ 552 if (!host->device_reset) 553 return; 554 555 gpiod_set_value_cansleep(host->device_reset, asserted); 556 } 557 558 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 559 enum ufs_notify_change_status status) 560 { 561 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 562 struct phy *phy = host->generic_phy; 563 564 if (status == PRE_CHANGE) 565 return 0; 566 567 if (ufs_qcom_is_link_off(hba)) { 568 /* 569 * Disable the tx/rx lane symbol clocks before PHY is 570 * powered down as the PLL source should be disabled 571 * after downstream clocks are disabled. 572 */ 573 ufs_qcom_disable_lane_clks(host); 574 phy_power_off(phy); 575 576 /* reset the connected UFS device during power down */ 577 ufs_qcom_device_reset_ctrl(hba, true); 578 579 } else if (!ufs_qcom_is_link_active(hba)) { 580 ufs_qcom_disable_lane_clks(host); 581 } 582 583 return ufs_qcom_ice_suspend(host); 584 } 585 586 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 587 { 588 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 589 struct phy *phy = host->generic_phy; 590 int err; 591 592 if (ufs_qcom_is_link_off(hba)) { 593 err = phy_power_on(phy); 594 if (err) { 595 dev_err(hba->dev, "%s: failed PHY power on: %d\n", 596 __func__, err); 597 return err; 598 } 599 600 err = ufs_qcom_enable_lane_clks(host); 601 if (err) 602 return err; 603 604 } else if (!ufs_qcom_is_link_active(hba)) { 605 err = ufs_qcom_enable_lane_clks(host); 606 if (err) 607 return err; 608 } 609 610 return ufs_qcom_ice_resume(host); 611 } 612 613 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 614 { 615 if (host->dev_ref_clk_ctrl_mmio && 616 (enable ^ host->is_dev_ref_clk_enabled)) { 617 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 618 619 if (enable) 620 temp |= host->dev_ref_clk_en_mask; 621 else 622 temp &= ~host->dev_ref_clk_en_mask; 623 624 /* 625 * If we are here to disable this clock it might be immediately 626 * after entering into hibern8 in which case we need to make 627 * sure that device ref_clk is active for specific time after 628 * hibern8 enter. 629 */ 630 if (!enable) { 631 unsigned long gating_wait; 632 633 gating_wait = host->hba->dev_info.clk_gating_wait_us; 634 if (!gating_wait) { 635 udelay(1); 636 } else { 637 /* 638 * bRefClkGatingWaitTime defines the minimum 639 * time for which the reference clock is 640 * required by device during transition from 641 * HS-MODE to LS-MODE or HIBERN8 state. Give it 642 * more delay to be on the safe side. 643 */ 644 gating_wait += 10; 645 usleep_range(gating_wait, gating_wait + 10); 646 } 647 } 648 649 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 650 651 /* 652 * Make sure the write to ref_clk reaches the destination and 653 * not stored in a Write Buffer (WB). 654 */ 655 readl(host->dev_ref_clk_ctrl_mmio); 656 657 /* 658 * If we call hibern8 exit after this, we need to make sure that 659 * device ref_clk is stable for at least 1us before the hibern8 660 * exit command. 661 */ 662 if (enable) 663 udelay(1); 664 665 host->is_dev_ref_clk_enabled = enable; 666 } 667 } 668 669 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 670 { 671 struct device *dev = host->hba->dev; 672 int ret; 673 674 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 675 if (ret < 0) { 676 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 677 return ret; 678 } 679 680 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 681 if (ret < 0) { 682 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 683 return ret; 684 } 685 686 return 0; 687 } 688 689 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 690 { 691 struct ufs_pa_layer_attr *p = &host->dev_req_params; 692 int gear = max_t(u32, p->gear_rx, p->gear_tx); 693 int lane = max_t(u32, p->lane_rx, p->lane_tx); 694 695 if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR, 696 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n", 697 gear, QCOM_UFS_MAX_GEAR)) 698 gear = QCOM_UFS_MAX_GEAR; 699 700 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE, 701 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n", 702 lane, QCOM_UFS_MAX_LANE)) 703 lane = QCOM_UFS_MAX_LANE; 704 705 if (ufshcd_is_hs_mode(p)) { 706 if (p->hs_rate == PA_HS_MODE_B) 707 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 708 else 709 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 710 } else { 711 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 712 } 713 } 714 715 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 716 { 717 struct __ufs_qcom_bw_table bw_table; 718 719 bw_table = ufs_qcom_get_bw_table(host); 720 721 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 722 } 723 724 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 725 enum ufs_notify_change_status status, 726 struct ufs_pa_layer_attr *dev_max_params, 727 struct ufs_pa_layer_attr *dev_req_params) 728 { 729 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 730 struct ufs_host_params *host_params = &host->host_params; 731 int ret = 0; 732 733 if (!dev_req_params) { 734 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 735 return -EINVAL; 736 } 737 738 switch (status) { 739 case PRE_CHANGE: 740 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); 741 if (ret) { 742 dev_err(hba->dev, "%s: failed to determine capabilities\n", 743 __func__); 744 return ret; 745 } 746 747 /* 748 * During UFS driver probe, always update the PHY gear to match the negotiated 749 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled, 750 * the second init can program the optimal PHY settings. This allows one to start 751 * the first init with either the minimum or the maximum support gear. 752 */ 753 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { 754 /* 755 * Skip REINIT if the negotiated gear matches with the 756 * initial phy_gear. Otherwise, update the phy_gear to 757 * program the optimal gear setting during REINIT. 758 */ 759 if (host->phy_gear == dev_req_params->gear_tx) 760 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 761 else 762 host->phy_gear = dev_req_params->gear_tx; 763 } 764 765 /* enable the device ref clock before changing to HS mode */ 766 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 767 ufshcd_is_hs_mode(dev_req_params)) 768 ufs_qcom_dev_ref_clk_ctrl(host, true); 769 770 if (host->hw_ver.major >= 0x4) { 771 ufshcd_dme_configure_adapt(hba, 772 dev_req_params->gear_tx, 773 PA_INITIAL_ADAPT); 774 } 775 break; 776 case POST_CHANGE: 777 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, 778 dev_req_params->pwr_rx, 779 dev_req_params->hs_rate, false, false)) { 780 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 781 __func__); 782 /* 783 * we return error code at the end of the routine, 784 * but continue to configure UFS_PHY_TX_LANE_ENABLE 785 * and bus voting as usual 786 */ 787 ret = -EINVAL; 788 } 789 790 /* cache the power mode parameters to use internally */ 791 memcpy(&host->dev_req_params, 792 dev_req_params, sizeof(*dev_req_params)); 793 794 ufs_qcom_icc_update_bw(host); 795 796 /* disable the device ref clock if entered PWM mode */ 797 if (ufshcd_is_hs_mode(&hba->pwr_info) && 798 !ufshcd_is_hs_mode(dev_req_params)) 799 ufs_qcom_dev_ref_clk_ctrl(host, false); 800 break; 801 default: 802 ret = -EINVAL; 803 break; 804 } 805 806 return ret; 807 } 808 809 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 810 { 811 int err; 812 u32 pa_vs_config_reg1; 813 814 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 815 &pa_vs_config_reg1); 816 if (err) 817 return err; 818 819 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 820 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 821 (pa_vs_config_reg1 | (1 << 12))); 822 } 823 824 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 825 { 826 int err = 0; 827 828 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 829 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 830 831 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) 832 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; 833 834 return err; 835 } 836 837 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 838 { 839 return ufshci_version(2, 0); 840 } 841 842 /** 843 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 844 * @hba: host controller instance 845 * 846 * QCOM UFS host controller might have some non standard behaviours (quirks) 847 * than what is specified by UFSHCI specification. Advertise all such 848 * quirks to standard UFS host controller driver so standard takes them into 849 * account. 850 */ 851 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 852 { 853 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 854 855 if (host->hw_ver.major == 0x2) 856 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 857 858 if (host->hw_ver.major > 0x3) 859 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 860 } 861 862 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) 863 { 864 struct ufs_host_params *host_params = &host->host_params; 865 u32 val, dev_major; 866 867 /* 868 * Default to powering up the PHY to the max gear possible, which is 869 * backwards compatible with lower gears but not optimal from 870 * a power usage point of view. After device negotiation, if the 871 * gear is lower a reinit will be performed to program the PHY 872 * to the ideal gear for this combo of controller and device. 873 */ 874 host->phy_gear = host_params->hs_tx_gear; 875 876 if (host->hw_ver.major < 0x4) { 877 /* 878 * These controllers only have one PHY init sequence, 879 * let's power up the PHY using that (the minimum supported 880 * gear, UFS_HS_G2). 881 */ 882 host->phy_gear = UFS_HS_G2; 883 } else if (host->hw_ver.major >= 0x5) { 884 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); 885 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val); 886 887 /* 888 * Since the UFS device version is populated, let's remove the 889 * REINIT quirk as the negotiated gear won't change during boot. 890 * So there is no need to do reinit. 891 */ 892 if (dev_major != 0x0) 893 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 894 895 /* 896 * For UFS 3.1 device and older, power up the PHY using HS-G4 897 * PHY gear to save power. 898 */ 899 if (dev_major > 0x0 && dev_major < 0x4) 900 host->phy_gear = UFS_HS_G4; 901 } 902 } 903 904 static void ufs_qcom_set_host_params(struct ufs_hba *hba) 905 { 906 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 907 struct ufs_host_params *host_params = &host->host_params; 908 909 ufshcd_init_host_params(host_params); 910 911 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 912 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); 913 } 914 915 static void ufs_qcom_set_caps(struct ufs_hba *hba) 916 { 917 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 918 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 919 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 920 hba->caps |= UFSHCD_CAP_WB_EN; 921 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 922 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 923 } 924 925 /** 926 * ufs_qcom_setup_clocks - enables/disable clocks 927 * @hba: host controller instance 928 * @on: If true, enable clocks else disable them. 929 * @status: PRE_CHANGE or POST_CHANGE notify 930 * 931 * Return: 0 on success, non-zero on failure. 932 */ 933 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 934 enum ufs_notify_change_status status) 935 { 936 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 937 938 /* 939 * In case ufs_qcom_init() is not yet done, simply ignore. 940 * This ufs_qcom_setup_clocks() shall be called from 941 * ufs_qcom_init() after init is done. 942 */ 943 if (!host) 944 return 0; 945 946 switch (status) { 947 case PRE_CHANGE: 948 if (on) { 949 ufs_qcom_icc_update_bw(host); 950 } else { 951 if (!ufs_qcom_is_link_active(hba)) { 952 /* disable device ref_clk */ 953 ufs_qcom_dev_ref_clk_ctrl(host, false); 954 } 955 } 956 break; 957 case POST_CHANGE: 958 if (on) { 959 /* enable the device ref clock for HS mode*/ 960 if (ufshcd_is_hs_mode(&hba->pwr_info)) 961 ufs_qcom_dev_ref_clk_ctrl(host, true); 962 } else { 963 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 964 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 965 } 966 break; 967 } 968 969 return 0; 970 } 971 972 static int 973 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 974 { 975 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 976 977 ufs_qcom_assert_reset(host->hba); 978 /* provide 1ms delay to let the reset pulse propagate. */ 979 usleep_range(1000, 1100); 980 return 0; 981 } 982 983 static int 984 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 985 { 986 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 987 988 ufs_qcom_deassert_reset(host->hba); 989 990 /* 991 * after reset deassertion, phy will need all ref clocks, 992 * voltage, current to settle down before starting serdes. 993 */ 994 usleep_range(1000, 1100); 995 return 0; 996 } 997 998 static const struct reset_control_ops ufs_qcom_reset_ops = { 999 .assert = ufs_qcom_reset_assert, 1000 .deassert = ufs_qcom_reset_deassert, 1001 }; 1002 1003 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 1004 { 1005 struct device *dev = host->hba->dev; 1006 int ret; 1007 1008 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 1009 if (IS_ERR(host->icc_ddr)) 1010 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 1011 "failed to acquire interconnect path\n"); 1012 1013 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1014 if (IS_ERR(host->icc_cpu)) 1015 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1016 "failed to acquire interconnect path\n"); 1017 1018 /* 1019 * Set Maximum bandwidth vote before initializing the UFS controller and 1020 * device. Ideally, a minimal interconnect vote would suffice for the 1021 * initialization, but a max vote would allow faster initialization. 1022 */ 1023 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1024 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1025 if (ret < 0) 1026 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1027 1028 return 0; 1029 } 1030 1031 /** 1032 * ufs_qcom_init - bind phy with controller 1033 * @hba: host controller instance 1034 * 1035 * Binds PHY with controller and powers up PHY enabling clocks 1036 * and regulators. 1037 * 1038 * Return: -EPROBE_DEFER if binding fails, returns negative error 1039 * on phy power up failure and returns zero on success. 1040 */ 1041 static int ufs_qcom_init(struct ufs_hba *hba) 1042 { 1043 int err; 1044 struct device *dev = hba->dev; 1045 struct ufs_qcom_host *host; 1046 struct ufs_clk_info *clki; 1047 1048 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1049 if (!host) 1050 return -ENOMEM; 1051 1052 /* Make a two way bind between the qcom host and the hba */ 1053 host->hba = hba; 1054 ufshcd_set_variant(hba, host); 1055 1056 /* Setup the optional reset control of HCI */ 1057 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1058 if (IS_ERR(host->core_reset)) { 1059 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1060 "Failed to get reset control\n"); 1061 goto out_variant_clear; 1062 } 1063 1064 /* Fire up the reset controller. Failure here is non-fatal. */ 1065 host->rcdev.of_node = dev->of_node; 1066 host->rcdev.ops = &ufs_qcom_reset_ops; 1067 host->rcdev.owner = dev->driver->owner; 1068 host->rcdev.nr_resets = 1; 1069 err = devm_reset_controller_register(dev, &host->rcdev); 1070 if (err) 1071 dev_warn(dev, "Failed to register reset controller\n"); 1072 1073 if (!has_acpi_companion(dev)) { 1074 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1075 if (IS_ERR(host->generic_phy)) { 1076 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1077 goto out_variant_clear; 1078 } 1079 } 1080 1081 err = ufs_qcom_icc_init(host); 1082 if (err) 1083 goto out_variant_clear; 1084 1085 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1086 GPIOD_OUT_HIGH); 1087 if (IS_ERR(host->device_reset)) { 1088 err = dev_err_probe(dev, PTR_ERR(host->device_reset), 1089 "Failed to acquire device reset gpio\n"); 1090 goto out_variant_clear; 1091 } 1092 1093 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1094 &host->hw_ver.minor, &host->hw_ver.step); 1095 1096 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1097 host->dev_ref_clk_en_mask = BIT(26); 1098 1099 list_for_each_entry(clki, &hba->clk_list_head, list) { 1100 if (!strcmp(clki->name, "core_clk_unipro")) 1101 clki->keep_link_active = true; 1102 } 1103 1104 err = ufs_qcom_init_lane_clks(host); 1105 if (err) 1106 goto out_variant_clear; 1107 1108 ufs_qcom_set_caps(hba); 1109 ufs_qcom_advertise_quirks(hba); 1110 ufs_qcom_set_host_params(hba); 1111 ufs_qcom_set_phy_gear(host); 1112 1113 err = ufs_qcom_ice_init(host); 1114 if (err) 1115 goto out_variant_clear; 1116 1117 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1118 1119 ufs_qcom_get_default_testbus_cfg(host); 1120 err = ufs_qcom_testbus_config(host); 1121 if (err) 1122 /* Failure is non-fatal */ 1123 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1124 __func__, err); 1125 1126 return 0; 1127 1128 out_variant_clear: 1129 ufshcd_set_variant(hba, NULL); 1130 1131 return err; 1132 } 1133 1134 static void ufs_qcom_exit(struct ufs_hba *hba) 1135 { 1136 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1137 1138 ufs_qcom_disable_lane_clks(host); 1139 phy_power_off(host->generic_phy); 1140 phy_exit(host->generic_phy); 1141 } 1142 1143 /** 1144 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles 1145 * 1146 * @hba: host controller instance 1147 * @cycles_in_1us: No of cycles in 1us to be configured 1148 * 1149 * Returns error if dme get/set configuration for 40ns fails 1150 * and returns zero on success. 1151 */ 1152 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, 1153 u32 cycles_in_1us) 1154 { 1155 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1156 u32 cycles_in_40ns; 1157 u32 reg; 1158 int err; 1159 1160 /* 1161 * UFS host controller V4.0.0 onwards needs to program 1162 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed 1163 * frequency of unipro core clk of UFS host controller. 1164 */ 1165 if (host->hw_ver.major < 4) 1166 return 0; 1167 1168 /* 1169 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not 1170 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will 1171 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware 1172 * specification expect to be 16. Hence use exact hardware spec 1173 * mandated value for cycles_in_40ns instead of calculating using 1174 * generic formulae. 1175 */ 1176 switch (cycles_in_1us) { 1177 case UNIPRO_CORE_CLK_FREQ_403_MHZ: 1178 cycles_in_40ns = 16; 1179 break; 1180 case UNIPRO_CORE_CLK_FREQ_300_MHZ: 1181 cycles_in_40ns = 12; 1182 break; 1183 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ: 1184 cycles_in_40ns = 8; 1185 break; 1186 case UNIPRO_CORE_CLK_FREQ_150_MHZ: 1187 cycles_in_40ns = 6; 1188 break; 1189 case UNIPRO_CORE_CLK_FREQ_100_MHZ: 1190 cycles_in_40ns = 4; 1191 break; 1192 case UNIPRO_CORE_CLK_FREQ_75_MHZ: 1193 cycles_in_40ns = 3; 1194 break; 1195 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ: 1196 cycles_in_40ns = 2; 1197 break; 1198 default: 1199 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", 1200 cycles_in_1us); 1201 return -EINVAL; 1202 } 1203 1204 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); 1205 if (err) 1206 return err; 1207 1208 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; 1209 reg |= cycles_in_40ns; 1210 1211 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); 1212 } 1213 1214 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) 1215 { 1216 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1217 struct list_head *head = &hba->clk_list_head; 1218 struct ufs_clk_info *clki; 1219 u32 cycles_in_1us = 0; 1220 u32 core_clk_ctrl_reg; 1221 int err; 1222 1223 list_for_each_entry(clki, head, list) { 1224 if (!IS_ERR_OR_NULL(clki->clk) && 1225 !strcmp(clki->name, "core_clk_unipro")) { 1226 if (!clki->max_freq) 1227 cycles_in_1us = 150; /* default for backwards compatibility */ 1228 else if (is_scale_up) 1229 cycles_in_1us = ceil(clki->max_freq, (1000 * 1000)); 1230 else 1231 cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000)); 1232 break; 1233 } 1234 } 1235 1236 err = ufshcd_dme_get(hba, 1237 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1238 &core_clk_ctrl_reg); 1239 if (err) 1240 return err; 1241 1242 /* Bit mask is different for UFS host controller V4.0.0 onwards */ 1243 if (host->hw_ver.major >= 4) { 1244 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us)) 1245 return -ERANGE; 1246 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4; 1247 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us); 1248 } else { 1249 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us)) 1250 return -ERANGE; 1251 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK; 1252 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); 1253 } 1254 1255 /* Clear CORE_CLK_DIV_EN */ 1256 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1257 1258 err = ufshcd_dme_set(hba, 1259 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1260 core_clk_ctrl_reg); 1261 if (err) 1262 return err; 1263 1264 /* Configure unipro core clk 40ns attribute */ 1265 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); 1266 } 1267 1268 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) 1269 { 1270 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1271 struct ufs_pa_layer_attr *attr = &host->dev_req_params; 1272 int ret; 1273 1274 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx, 1275 attr->hs_rate, false, true); 1276 if (ret) { 1277 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); 1278 return ret; 1279 } 1280 /* set unipro core clock attributes and clear clock divider */ 1281 return ufs_qcom_set_core_clk_ctrl(hba, true); 1282 } 1283 1284 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1285 { 1286 return 0; 1287 } 1288 1289 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1290 { 1291 int err; 1292 u32 core_clk_ctrl_reg; 1293 1294 err = ufshcd_dme_get(hba, 1295 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1296 &core_clk_ctrl_reg); 1297 1298 /* make sure CORE_CLK_DIV_EN is cleared */ 1299 if (!err && 1300 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1301 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1302 err = ufshcd_dme_set(hba, 1303 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1304 core_clk_ctrl_reg); 1305 } 1306 1307 return err; 1308 } 1309 1310 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) 1311 { 1312 /* set unipro core clock attributes and clear clock divider */ 1313 return ufs_qcom_set_core_clk_ctrl(hba, false); 1314 } 1315 1316 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, 1317 bool scale_up, enum ufs_notify_change_status status) 1318 { 1319 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1320 int err; 1321 1322 /* check the host controller state before sending hibern8 cmd */ 1323 if (!ufshcd_is_hba_active(hba)) 1324 return 0; 1325 1326 if (status == PRE_CHANGE) { 1327 err = ufshcd_uic_hibern8_enter(hba); 1328 if (err) 1329 return err; 1330 if (scale_up) 1331 err = ufs_qcom_clk_scale_up_pre_change(hba); 1332 else 1333 err = ufs_qcom_clk_scale_down_pre_change(hba); 1334 1335 if (err) { 1336 ufshcd_uic_hibern8_exit(hba); 1337 return err; 1338 } 1339 } else { 1340 if (scale_up) 1341 err = ufs_qcom_clk_scale_up_post_change(hba); 1342 else 1343 err = ufs_qcom_clk_scale_down_post_change(hba); 1344 1345 1346 if (err) { 1347 ufshcd_uic_hibern8_exit(hba); 1348 return err; 1349 } 1350 1351 ufs_qcom_icc_update_bw(host); 1352 ufshcd_uic_hibern8_exit(hba); 1353 } 1354 1355 return 0; 1356 } 1357 1358 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1359 { 1360 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1361 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1362 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1363 } 1364 1365 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1366 { 1367 /* provide a legal default configuration */ 1368 host->testbus.select_major = TSTBUS_UNIPRO; 1369 host->testbus.select_minor = 37; 1370 } 1371 1372 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1373 { 1374 if (host->testbus.select_major >= TSTBUS_MAX) { 1375 dev_err(host->hba->dev, 1376 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1377 __func__, host->testbus.select_major); 1378 return false; 1379 } 1380 1381 return true; 1382 } 1383 1384 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1385 { 1386 int reg; 1387 int offset; 1388 u32 mask = TEST_BUS_SUB_SEL_MASK; 1389 1390 if (!host) 1391 return -EINVAL; 1392 1393 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1394 return -EPERM; 1395 1396 switch (host->testbus.select_major) { 1397 case TSTBUS_UAWM: 1398 reg = UFS_TEST_BUS_CTRL_0; 1399 offset = 24; 1400 break; 1401 case TSTBUS_UARM: 1402 reg = UFS_TEST_BUS_CTRL_0; 1403 offset = 16; 1404 break; 1405 case TSTBUS_TXUC: 1406 reg = UFS_TEST_BUS_CTRL_0; 1407 offset = 8; 1408 break; 1409 case TSTBUS_RXUC: 1410 reg = UFS_TEST_BUS_CTRL_0; 1411 offset = 0; 1412 break; 1413 case TSTBUS_DFC: 1414 reg = UFS_TEST_BUS_CTRL_1; 1415 offset = 24; 1416 break; 1417 case TSTBUS_TRLUT: 1418 reg = UFS_TEST_BUS_CTRL_1; 1419 offset = 16; 1420 break; 1421 case TSTBUS_TMRLUT: 1422 reg = UFS_TEST_BUS_CTRL_1; 1423 offset = 8; 1424 break; 1425 case TSTBUS_OCSC: 1426 reg = UFS_TEST_BUS_CTRL_1; 1427 offset = 0; 1428 break; 1429 case TSTBUS_WRAPPER: 1430 reg = UFS_TEST_BUS_CTRL_2; 1431 offset = 16; 1432 break; 1433 case TSTBUS_COMBINED: 1434 reg = UFS_TEST_BUS_CTRL_2; 1435 offset = 8; 1436 break; 1437 case TSTBUS_UTP_HCI: 1438 reg = UFS_TEST_BUS_CTRL_2; 1439 offset = 0; 1440 break; 1441 case TSTBUS_UNIPRO: 1442 reg = UFS_UNIPRO_CFG; 1443 offset = 20; 1444 mask = 0xFFF; 1445 break; 1446 /* 1447 * No need for a default case, since 1448 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 1449 * is legal 1450 */ 1451 } 1452 mask <<= offset; 1453 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 1454 (u32)host->testbus.select_major << 19, 1455 REG_UFS_CFG1); 1456 ufshcd_rmwl(host->hba, mask, 1457 (u32)host->testbus.select_minor << offset, 1458 reg); 1459 ufs_qcom_enable_test_bus(host); 1460 1461 return 0; 1462 } 1463 1464 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 1465 { 1466 u32 reg; 1467 struct ufs_qcom_host *host; 1468 1469 host = ufshcd_get_variant(hba); 1470 1471 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 1472 "HCI Vendor Specific Registers "); 1473 1474 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 1475 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 1476 1477 reg = ufshcd_readl(hba, REG_UFS_CFG1); 1478 reg |= UTP_DBG_RAMS_EN; 1479 ufshcd_writel(hba, reg, REG_UFS_CFG1); 1480 1481 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 1482 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 1483 1484 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 1485 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 1486 1487 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 1488 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 1489 1490 /* clear bit 17 - UTP_DBG_RAMS_EN */ 1491 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 1492 1493 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 1494 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 1495 1496 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 1497 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 1498 1499 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 1500 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 1501 1502 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 1503 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 1504 1505 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 1506 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 1507 1508 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 1509 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 1510 1511 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 1512 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 1513 } 1514 1515 /** 1516 * ufs_qcom_device_reset() - toggle the (optional) device reset line 1517 * @hba: per-adapter instance 1518 * 1519 * Toggles the (optional) reset line to reset the attached device. 1520 */ 1521 static int ufs_qcom_device_reset(struct ufs_hba *hba) 1522 { 1523 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1524 1525 /* reset gpio is optional */ 1526 if (!host->device_reset) 1527 return -EOPNOTSUPP; 1528 1529 /* 1530 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 1531 * be on the safe side. 1532 */ 1533 ufs_qcom_device_reset_ctrl(hba, true); 1534 usleep_range(10, 15); 1535 1536 ufs_qcom_device_reset_ctrl(hba, false); 1537 usleep_range(10, 15); 1538 1539 return 0; 1540 } 1541 1542 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) 1543 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1544 struct devfreq_dev_profile *p, 1545 struct devfreq_simple_ondemand_data *d) 1546 { 1547 p->polling_ms = 60; 1548 p->timer = DEVFREQ_TIMER_DELAYED; 1549 d->upthreshold = 70; 1550 d->downdifferential = 5; 1551 } 1552 #else 1553 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1554 struct devfreq_dev_profile *p, 1555 struct devfreq_simple_ondemand_data *data) 1556 { 1557 } 1558 #endif 1559 1560 static void ufs_qcom_reinit_notify(struct ufs_hba *hba) 1561 { 1562 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1563 1564 phy_power_off(host->generic_phy); 1565 } 1566 1567 /* Resources */ 1568 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { 1569 {.name = "ufs_mem",}, 1570 {.name = "mcq",}, 1571 /* Submission Queue DAO */ 1572 {.name = "mcq_sqd",}, 1573 /* Submission Queue Interrupt Status */ 1574 {.name = "mcq_sqis",}, 1575 /* Completion Queue DAO */ 1576 {.name = "mcq_cqd",}, 1577 /* Completion Queue Interrupt Status */ 1578 {.name = "mcq_cqis",}, 1579 /* MCQ vendor specific */ 1580 {.name = "mcq_vs",}, 1581 }; 1582 1583 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 1584 { 1585 struct platform_device *pdev = to_platform_device(hba->dev); 1586 struct ufshcd_res_info *res; 1587 struct resource *res_mem, *res_mcq; 1588 int i, ret; 1589 1590 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); 1591 1592 for (i = 0; i < RES_MAX; i++) { 1593 res = &hba->res[i]; 1594 res->resource = platform_get_resource_byname(pdev, 1595 IORESOURCE_MEM, 1596 res->name); 1597 if (!res->resource) { 1598 dev_info(hba->dev, "Resource %s not provided\n", res->name); 1599 if (i == RES_UFS) 1600 return -ENODEV; 1601 continue; 1602 } else if (i == RES_UFS) { 1603 res_mem = res->resource; 1604 res->base = hba->mmio_base; 1605 continue; 1606 } 1607 1608 res->base = devm_ioremap_resource(hba->dev, res->resource); 1609 if (IS_ERR(res->base)) { 1610 dev_err(hba->dev, "Failed to map res %s, err=%d\n", 1611 res->name, (int)PTR_ERR(res->base)); 1612 ret = PTR_ERR(res->base); 1613 res->base = NULL; 1614 return ret; 1615 } 1616 } 1617 1618 /* MCQ resource provided in DT */ 1619 res = &hba->res[RES_MCQ]; 1620 /* Bail if MCQ resource is provided */ 1621 if (res->base) 1622 goto out; 1623 1624 /* Explicitly allocate MCQ resource from ufs_mem */ 1625 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); 1626 if (!res_mcq) 1627 return -ENOMEM; 1628 1629 res_mcq->start = res_mem->start + 1630 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); 1631 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; 1632 res_mcq->flags = res_mem->flags; 1633 res_mcq->name = "mcq"; 1634 1635 ret = insert_resource(&iomem_resource, res_mcq); 1636 if (ret) { 1637 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", 1638 ret); 1639 return ret; 1640 } 1641 1642 res->base = devm_ioremap_resource(hba->dev, res_mcq); 1643 if (IS_ERR(res->base)) { 1644 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", 1645 (int)PTR_ERR(res->base)); 1646 ret = PTR_ERR(res->base); 1647 goto ioremap_err; 1648 } 1649 1650 out: 1651 hba->mcq_base = res->base; 1652 return 0; 1653 ioremap_err: 1654 res->base = NULL; 1655 remove_resource(res_mcq); 1656 return ret; 1657 } 1658 1659 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 1660 { 1661 struct ufshcd_res_info *mem_res, *sqdao_res; 1662 struct ufshcd_mcq_opr_info_t *opr; 1663 int i; 1664 1665 mem_res = &hba->res[RES_UFS]; 1666 sqdao_res = &hba->res[RES_MCQ_SQD]; 1667 1668 if (!mem_res->base || !sqdao_res->base) 1669 return -EINVAL; 1670 1671 for (i = 0; i < OPR_MAX; i++) { 1672 opr = &hba->mcq_opr[i]; 1673 opr->offset = sqdao_res->resource->start - 1674 mem_res->resource->start + 0x40 * i; 1675 opr->stride = 0x100; 1676 opr->base = sqdao_res->base + 0x40 * i; 1677 } 1678 1679 return 0; 1680 } 1681 1682 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 1683 { 1684 /* Qualcomm HC supports up to 64 */ 1685 return MAX_SUPP_MAC; 1686 } 1687 1688 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 1689 unsigned long *ocqs) 1690 { 1691 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; 1692 1693 if (!mcq_vs_res->base) 1694 return -EINVAL; 1695 1696 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); 1697 1698 return 0; 1699 } 1700 1701 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 1702 { 1703 struct device *dev = msi_desc_to_dev(desc); 1704 struct ufs_hba *hba = dev_get_drvdata(dev); 1705 1706 ufshcd_mcq_config_esi(hba, msg); 1707 } 1708 1709 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 1710 { 1711 struct msi_desc *desc = data; 1712 struct device *dev = msi_desc_to_dev(desc); 1713 struct ufs_hba *hba = dev_get_drvdata(dev); 1714 u32 id = desc->msi_index; 1715 struct ufs_hw_queue *hwq = &hba->uhq[id]; 1716 1717 ufshcd_mcq_write_cqis(hba, 0x1, id); 1718 ufshcd_mcq_poll_cqe_lock(hba, hwq); 1719 1720 return IRQ_HANDLED; 1721 } 1722 1723 static int ufs_qcom_config_esi(struct ufs_hba *hba) 1724 { 1725 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1726 struct msi_desc *desc; 1727 struct msi_desc *failed_desc = NULL; 1728 int nr_irqs, ret; 1729 1730 if (host->esi_enabled) 1731 return 0; 1732 1733 /* 1734 * 1. We only handle CQs as of now. 1735 * 2. Poll queues do not need ESI. 1736 */ 1737 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 1738 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, 1739 ufs_qcom_write_msi_msg); 1740 if (ret) { 1741 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); 1742 return ret; 1743 } 1744 1745 msi_lock_descs(hba->dev); 1746 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1747 ret = devm_request_irq(hba->dev, desc->irq, 1748 ufs_qcom_mcq_esi_handler, 1749 IRQF_SHARED, "qcom-mcq-esi", desc); 1750 if (ret) { 1751 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", 1752 __func__, desc->irq, ret); 1753 failed_desc = desc; 1754 break; 1755 } 1756 } 1757 msi_unlock_descs(hba->dev); 1758 1759 if (ret) { 1760 /* Rewind */ 1761 msi_lock_descs(hba->dev); 1762 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1763 if (desc == failed_desc) 1764 break; 1765 devm_free_irq(hba->dev, desc->irq, hba); 1766 } 1767 msi_unlock_descs(hba->dev); 1768 platform_device_msi_free_irqs_all(hba->dev); 1769 } else { 1770 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && 1771 host->hw_ver.step == 0) 1772 ufshcd_rmwl(hba, ESI_VEC_MASK, 1773 FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), 1774 REG_UFS_CFG3); 1775 ufshcd_mcq_enable_esi(hba); 1776 host->esi_enabled = true; 1777 } 1778 1779 return ret; 1780 } 1781 1782 /* 1783 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 1784 * 1785 * The variant operations configure the necessary controller and PHY 1786 * handshake during initialization. 1787 */ 1788 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 1789 .name = "qcom", 1790 .init = ufs_qcom_init, 1791 .exit = ufs_qcom_exit, 1792 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 1793 .clk_scale_notify = ufs_qcom_clk_scale_notify, 1794 .setup_clocks = ufs_qcom_setup_clocks, 1795 .hce_enable_notify = ufs_qcom_hce_enable_notify, 1796 .link_startup_notify = ufs_qcom_link_startup_notify, 1797 .pwr_change_notify = ufs_qcom_pwr_change_notify, 1798 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 1799 .suspend = ufs_qcom_suspend, 1800 .resume = ufs_qcom_resume, 1801 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 1802 .device_reset = ufs_qcom_device_reset, 1803 .config_scaling_param = ufs_qcom_config_scaling_param, 1804 .program_key = ufs_qcom_ice_program_key, 1805 .reinit_notify = ufs_qcom_reinit_notify, 1806 .mcq_config_resource = ufs_qcom_mcq_config_resource, 1807 .get_hba_mac = ufs_qcom_get_hba_mac, 1808 .op_runtime_config = ufs_qcom_op_runtime_config, 1809 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 1810 .config_esi = ufs_qcom_config_esi, 1811 }; 1812 1813 /** 1814 * ufs_qcom_probe - probe routine of the driver 1815 * @pdev: pointer to Platform device handle 1816 * 1817 * Return: zero for success and non-zero for failure. 1818 */ 1819 static int ufs_qcom_probe(struct platform_device *pdev) 1820 { 1821 int err; 1822 struct device *dev = &pdev->dev; 1823 1824 /* Perform generic probe */ 1825 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); 1826 if (err) 1827 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 1828 1829 return 0; 1830 } 1831 1832 /** 1833 * ufs_qcom_remove - set driver_data of the device to NULL 1834 * @pdev: pointer to platform device handle 1835 * 1836 * Always returns 0 1837 */ 1838 static void ufs_qcom_remove(struct platform_device *pdev) 1839 { 1840 struct ufs_hba *hba = platform_get_drvdata(pdev); 1841 1842 pm_runtime_get_sync(&(pdev)->dev); 1843 ufshcd_remove(hba); 1844 platform_device_msi_free_irqs_all(hba->dev); 1845 } 1846 1847 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 1848 { .compatible = "qcom,ufshc"}, 1849 {}, 1850 }; 1851 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 1852 1853 #ifdef CONFIG_ACPI 1854 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 1855 { "QCOM24A5" }, 1856 { }, 1857 }; 1858 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 1859 #endif 1860 1861 static const struct dev_pm_ops ufs_qcom_pm_ops = { 1862 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 1863 .prepare = ufshcd_suspend_prepare, 1864 .complete = ufshcd_resume_complete, 1865 #ifdef CONFIG_PM_SLEEP 1866 .suspend = ufshcd_system_suspend, 1867 .resume = ufshcd_system_resume, 1868 .freeze = ufshcd_system_freeze, 1869 .restore = ufshcd_system_restore, 1870 .thaw = ufshcd_system_thaw, 1871 #endif 1872 }; 1873 1874 static struct platform_driver ufs_qcom_pltform = { 1875 .probe = ufs_qcom_probe, 1876 .remove_new = ufs_qcom_remove, 1877 .driver = { 1878 .name = "ufshcd-qcom", 1879 .pm = &ufs_qcom_pm_ops, 1880 .of_match_table = of_match_ptr(ufs_qcom_of_match), 1881 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 1882 }, 1883 }; 1884 module_platform_driver(ufs_qcom_pltform); 1885 1886 MODULE_LICENSE("GPL v2"); 1887