1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/clk.h> 8 #include <linux/cleanup.h> 9 #include <linux/delay.h> 10 #include <linux/devfreq.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/interconnect.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/reset-controller.h> 18 #include <linux/time.h> 19 #include <linux/unaligned.h> 20 #include <linux/units.h> 21 22 #include <soc/qcom/ice.h> 23 24 #include <ufs/ufshcd.h> 25 #include <ufs/ufshci.h> 26 #include <ufs/ufs_quirks.h> 27 #include <ufs/unipro.h> 28 #include "ufshcd-pltfrm.h" 29 #include "ufs-qcom.h" 30 31 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 32 #define MCQ_QCFGPTR_UNIT 0x200 33 #define MCQ_SQATTR_OFFSET(c) \ 34 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 35 #define MCQ_QCFG_SIZE 0x40 36 37 /* De-emphasis for gear-5 */ 38 #define DEEMPHASIS_3_5_dB 0x04 39 #define NO_DEEMPHASIS 0x0 40 41 enum { 42 TSTBUS_UAWM, 43 TSTBUS_UARM, 44 TSTBUS_TXUC, 45 TSTBUS_RXUC, 46 TSTBUS_DFC, 47 TSTBUS_TRLUT, 48 TSTBUS_TMRLUT, 49 TSTBUS_OCSC, 50 TSTBUS_UTP_HCI, 51 TSTBUS_COMBINED, 52 TSTBUS_WRAPPER, 53 TSTBUS_UNIPRO, 54 TSTBUS_MAX, 55 }; 56 57 #define QCOM_UFS_MAX_GEAR 5 58 #define QCOM_UFS_MAX_LANE 2 59 60 enum { 61 MODE_MIN, 62 MODE_PWM, 63 MODE_HS_RA, 64 MODE_HS_RB, 65 MODE_MAX, 66 }; 67 68 static const struct __ufs_qcom_bw_table { 69 u32 mem_bw; 70 u32 cfg_bw; 71 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 72 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 73 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 74 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 75 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 76 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 77 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 }, 78 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 79 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 80 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 81 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 82 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 }, 83 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 84 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 85 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 86 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 87 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 88 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 89 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 90 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 91 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 92 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 93 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 94 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 95 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 96 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 97 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 98 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 99 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 100 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 101 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 102 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 103 [MODE_MAX][0][0] = { 7643136, 819200 }, 104 }; 105 106 static const struct { 107 int nminor; 108 char *prefix; 109 } testbus_info[TSTBUS_MAX] = { 110 [TSTBUS_UAWM] = {32, "TSTBUS_UAWM"}, 111 [TSTBUS_UARM] = {32, "TSTBUS_UARM"}, 112 [TSTBUS_TXUC] = {32, "TSTBUS_TXUC"}, 113 [TSTBUS_RXUC] = {32, "TSTBUS_RXUC"}, 114 [TSTBUS_DFC] = {32, "TSTBUS_DFC"}, 115 [TSTBUS_TRLUT] = {32, "TSTBUS_TRLUT"}, 116 [TSTBUS_TMRLUT] = {32, "TSTBUS_TMRLUT"}, 117 [TSTBUS_OCSC] = {32, "TSTBUS_OCSC"}, 118 [TSTBUS_UTP_HCI] = {32, "TSTBUS_UTP_HCI"}, 119 [TSTBUS_COMBINED] = {32, "TSTBUS_COMBINED"}, 120 [TSTBUS_WRAPPER] = {32, "TSTBUS_WRAPPER"}, 121 [TSTBUS_UNIPRO] = {256, "TSTBUS_UNIPRO"}, 122 }; 123 124 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 125 static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba, 126 unsigned long freq, char *name); 127 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq); 128 129 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 130 { 131 return container_of(rcd, struct ufs_qcom_host, rcdev); 132 } 133 134 #ifdef CONFIG_SCSI_UFS_CRYPTO 135 /** 136 * ufs_qcom_config_ice_allocator() - ICE core allocator configuration 137 * 138 * @host: pointer to qcom specific variant structure. 139 */ 140 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) 141 { 142 struct ufs_hba *hba = host->hba; 143 static const uint8_t val[4] = { NUM_RX_R1W0, NUM_TX_R0W1, NUM_RX_R1W1, NUM_TX_R1W1 }; 144 u32 config; 145 146 if (!(host->caps & UFS_QCOM_CAP_ICE_CONFIG) || 147 !(host->hba->caps & UFSHCD_CAP_CRYPTO)) 148 return; 149 150 config = get_unaligned_le32(val); 151 152 ufshcd_writel(hba, ICE_ALLOCATOR_TYPE, REG_UFS_MEM_ICE_CONFIG); 153 ufshcd_writel(hba, config, REG_UFS_MEM_ICE_NUM_CORE); 154 } 155 156 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 157 { 158 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 159 qcom_ice_enable(host->ice); 160 } 161 162 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops; /* forward decl */ 163 164 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 165 { 166 struct ufs_hba *hba = host->hba; 167 struct blk_crypto_profile *profile = &hba->crypto_profile; 168 struct device *dev = hba->dev; 169 struct qcom_ice *ice; 170 union ufs_crypto_capabilities caps; 171 union ufs_crypto_cap_entry cap; 172 int err; 173 int i; 174 175 ice = devm_of_qcom_ice_get(dev); 176 if (ice == ERR_PTR(-EOPNOTSUPP)) { 177 dev_warn(dev, "Disabling inline encryption support\n"); 178 ice = NULL; 179 } 180 181 if (IS_ERR_OR_NULL(ice)) 182 return PTR_ERR_OR_ZERO(ice); 183 184 host->ice = ice; 185 186 /* Initialize the blk_crypto_profile */ 187 188 caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP)); 189 190 /* The number of keyslots supported is (CFGC+1) */ 191 err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1); 192 if (err) 193 return err; 194 195 profile->ll_ops = ufs_qcom_crypto_ops; 196 profile->max_dun_bytes_supported = 8; 197 profile->key_types_supported = qcom_ice_get_supported_key_type(ice); 198 profile->dev = dev; 199 200 /* 201 * Currently this driver only supports AES-256-XTS. All known versions 202 * of ICE support it, but to be safe make sure it is really declared in 203 * the crypto capability registers. The crypto capability registers 204 * also give the supported data unit size(s). 205 */ 206 for (i = 0; i < caps.num_crypto_cap; i++) { 207 cap.reg_val = cpu_to_le32(ufshcd_readl(hba, 208 REG_UFS_CRYPTOCAP + 209 i * sizeof(__le32))); 210 if (cap.algorithm_id == UFS_CRYPTO_ALG_AES_XTS && 211 cap.key_size == UFS_CRYPTO_KEY_SIZE_256) 212 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |= 213 cap.sdus_mask * 512; 214 } 215 216 hba->caps |= UFSHCD_CAP_CRYPTO; 217 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE; 218 return 0; 219 } 220 221 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 222 { 223 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 224 return qcom_ice_resume(host->ice); 225 226 return 0; 227 } 228 229 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 230 { 231 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 232 return qcom_ice_suspend(host->ice); 233 234 return 0; 235 } 236 237 static int ufs_qcom_ice_keyslot_program(struct blk_crypto_profile *profile, 238 const struct blk_crypto_key *key, 239 unsigned int slot) 240 { 241 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 242 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 243 int err; 244 245 ufshcd_hold(hba); 246 err = qcom_ice_program_key(host->ice, slot, key); 247 ufshcd_release(hba); 248 return err; 249 } 250 251 static int ufs_qcom_ice_keyslot_evict(struct blk_crypto_profile *profile, 252 const struct blk_crypto_key *key, 253 unsigned int slot) 254 { 255 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 256 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 257 int err; 258 259 ufshcd_hold(hba); 260 err = qcom_ice_evict_key(host->ice, slot); 261 ufshcd_release(hba); 262 return err; 263 } 264 265 static int ufs_qcom_ice_derive_sw_secret(struct blk_crypto_profile *profile, 266 const u8 *eph_key, size_t eph_key_size, 267 u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE]) 268 { 269 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 270 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 271 272 return qcom_ice_derive_sw_secret(host->ice, eph_key, eph_key_size, 273 sw_secret); 274 } 275 276 static int ufs_qcom_ice_import_key(struct blk_crypto_profile *profile, 277 const u8 *raw_key, size_t raw_key_size, 278 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 279 { 280 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 281 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 282 283 return qcom_ice_import_key(host->ice, raw_key, raw_key_size, lt_key); 284 } 285 286 static int ufs_qcom_ice_generate_key(struct blk_crypto_profile *profile, 287 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 288 { 289 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 290 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 291 292 return qcom_ice_generate_key(host->ice, lt_key); 293 } 294 295 static int ufs_qcom_ice_prepare_key(struct blk_crypto_profile *profile, 296 const u8 *lt_key, size_t lt_key_size, 297 u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 298 { 299 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 300 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 301 302 return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key); 303 } 304 305 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = { 306 .keyslot_program = ufs_qcom_ice_keyslot_program, 307 .keyslot_evict = ufs_qcom_ice_keyslot_evict, 308 .derive_sw_secret = ufs_qcom_ice_derive_sw_secret, 309 .import_key = ufs_qcom_ice_import_key, 310 .generate_key = ufs_qcom_ice_generate_key, 311 .prepare_key = ufs_qcom_ice_prepare_key, 312 }; 313 314 #else 315 316 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 317 { 318 } 319 320 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 321 { 322 return 0; 323 } 324 325 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 326 { 327 return 0; 328 } 329 330 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 331 { 332 return 0; 333 } 334 335 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) 336 { 337 } 338 339 #endif 340 341 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 342 { 343 if (!host->is_lane_clks_enabled) 344 return; 345 346 clk_bulk_disable_unprepare(host->num_clks, host->clks); 347 348 host->is_lane_clks_enabled = false; 349 } 350 351 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 352 { 353 int err; 354 355 err = clk_bulk_prepare_enable(host->num_clks, host->clks); 356 if (err) 357 return err; 358 359 host->is_lane_clks_enabled = true; 360 361 return 0; 362 } 363 364 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 365 { 366 int err; 367 struct device *dev = host->hba->dev; 368 369 if (has_acpi_companion(dev)) 370 return 0; 371 372 err = devm_clk_bulk_get_all(dev, &host->clks); 373 if (err <= 0) 374 return err; 375 376 host->num_clks = err; 377 378 return 0; 379 } 380 381 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 382 { 383 int err; 384 u32 tx_fsm_val; 385 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 386 387 do { 388 err = ufshcd_dme_get(hba, 389 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 390 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 391 &tx_fsm_val); 392 if (err || tx_fsm_val == TX_FSM_HIBERN8) 393 break; 394 395 /* sleep for max. 200us */ 396 usleep_range(100, 200); 397 } while (time_before(jiffies, timeout)); 398 399 /* 400 * we might have scheduled out for long during polling so 401 * check the state again. 402 */ 403 if (time_after(jiffies, timeout)) 404 err = ufshcd_dme_get(hba, 405 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 406 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 407 &tx_fsm_val); 408 409 if (err) { 410 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 411 __func__, err); 412 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 413 err = tx_fsm_val; 414 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 415 __func__, err); 416 } 417 418 return err; 419 } 420 421 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 422 { 423 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); 424 425 if (host->hw_ver.major >= 0x05) 426 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 427 } 428 429 /* 430 * ufs_qcom_host_reset - reset host controller and PHY 431 */ 432 static int ufs_qcom_host_reset(struct ufs_hba *hba) 433 { 434 int ret; 435 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 436 bool reenable_intr; 437 438 if (!host->core_reset) 439 return 0; 440 441 reenable_intr = hba->is_irq_enabled; 442 ufshcd_disable_irq(hba); 443 444 ret = reset_control_assert(host->core_reset); 445 if (ret) { 446 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 447 __func__, ret); 448 return ret; 449 } 450 451 /* 452 * The hardware requirement for delay between assert/deassert 453 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 454 * ~125us (4/32768). To be on the safe side add 200us delay. 455 */ 456 usleep_range(200, 210); 457 458 ret = reset_control_deassert(host->core_reset); 459 if (ret) { 460 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 461 __func__, ret); 462 return ret; 463 } 464 465 usleep_range(1000, 1100); 466 467 if (reenable_intr) 468 ufshcd_enable_irq(hba); 469 470 return 0; 471 } 472 473 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 474 { 475 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 476 477 if (host->hw_ver.major >= 0x4) 478 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 479 480 /* Default is HS-G3 */ 481 return UFS_HS_G3; 482 } 483 484 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 485 { 486 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 487 struct ufs_host_params *host_params = &host->host_params; 488 struct phy *phy = host->generic_phy; 489 enum phy_mode mode; 490 int ret; 491 492 /* 493 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. 494 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, 495 * so that the subsequent power mode change shall stick to Rate-A. 496 */ 497 if (host->hw_ver.major == 0x5) { 498 if (host->phy_gear == UFS_HS_G5) 499 host_params->hs_rate = PA_HS_MODE_A; 500 else 501 host_params->hs_rate = PA_HS_MODE_B; 502 } 503 504 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; 505 506 /* Reset UFS Host Controller and PHY */ 507 ret = ufs_qcom_host_reset(hba); 508 if (ret) 509 return ret; 510 511 if (phy->power_count) 512 phy_power_off(phy); 513 514 515 /* phy initialization - calibrate the phy */ 516 ret = phy_init(phy); 517 if (ret) { 518 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 519 __func__, ret); 520 return ret; 521 } 522 523 ret = phy_set_mode_ext(phy, mode, host->phy_gear); 524 if (ret) 525 goto out_disable_phy; 526 527 /* power on phy - start serdes and phy's power and clocks */ 528 ret = phy_power_on(phy); 529 if (ret) { 530 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 531 __func__, ret); 532 goto out_disable_phy; 533 } 534 535 ret = phy_calibrate(phy); 536 if (ret) { 537 dev_err(hba->dev, "Failed to calibrate PHY: %d\n", ret); 538 goto out_disable_phy; 539 } 540 541 ufs_qcom_select_unipro_mode(host); 542 543 return 0; 544 545 out_disable_phy: 546 phy_exit(phy); 547 548 return ret; 549 } 550 551 /* 552 * The UTP controller has a number of internal clock gating cells (CGCs). 553 * Internal hardware sub-modules within the UTP controller control the CGCs. 554 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 555 * in a specific operation, UTP controller CGCs are by default disabled and 556 * this function enables them (after every UFS link startup) to save some power 557 * leakage. 558 */ 559 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 560 { 561 int err; 562 563 /* Enable UTP internal clock gating */ 564 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, 565 REG_UFS_CFG2); 566 567 /* Ensure that HW clock gating is enabled before next operations */ 568 ufshcd_readl(hba, REG_UFS_CFG2); 569 570 /* Enable Unipro internal clock gating */ 571 err = ufshcd_dme_rmw(hba, DL_VS_CLK_CFG_MASK, 572 DL_VS_CLK_CFG_MASK, DL_VS_CLK_CFG); 573 if (err) 574 goto out; 575 576 err = ufshcd_dme_rmw(hba, PA_VS_CLK_CFG_REG_MASK, 577 PA_VS_CLK_CFG_REG_MASK, PA_VS_CLK_CFG_REG); 578 if (err) 579 goto out; 580 581 err = ufshcd_dme_rmw(hba, DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN, 582 DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN, 583 DME_VS_CORE_CLK_CTRL); 584 out: 585 if (err) 586 dev_err(hba->dev, "hw clk gating enabled failed\n"); 587 } 588 589 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 590 enum ufs_notify_change_status status) 591 { 592 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 593 int err; 594 595 switch (status) { 596 case PRE_CHANGE: 597 err = ufs_qcom_power_up_sequence(hba); 598 if (err) 599 return err; 600 601 /* 602 * The PHY PLL output is the source of tx/rx lane symbol 603 * clocks, hence, enable the lane clocks only after PHY 604 * is initialized. 605 */ 606 err = ufs_qcom_enable_lane_clks(host); 607 break; 608 case POST_CHANGE: 609 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 610 err = ufs_qcom_check_hibern8(hba); 611 ufs_qcom_enable_hw_clk_gating(hba); 612 ufs_qcom_ice_enable(host); 613 ufs_qcom_config_ice_allocator(host); 614 break; 615 default: 616 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 617 err = -EINVAL; 618 break; 619 } 620 return err; 621 } 622 623 /** 624 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers 625 * 626 * @hba: host controller instance 627 * @is_pre_scale_up: flag to check if pre scale up condition. 628 * @freq: target opp freq 629 * Return: zero for success and non-zero in case of a failure. 630 */ 631 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsigned long freq) 632 { 633 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 634 struct ufs_clk_info *clki; 635 unsigned long clk_freq = 0; 636 u32 core_clk_cycles_per_us; 637 638 /* 639 * UTP controller uses SYS1CLK_1US_REG register for Interrupt 640 * Aggregation logic. 641 * It is mandatory to write SYS1CLK_1US_REG register on UFS host 642 * controller V4.0.0 onwards. 643 */ 644 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) 645 return 0; 646 647 if (hba->use_pm_opp && freq != ULONG_MAX) { 648 clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk"); 649 if (clk_freq) 650 goto cfg_timers; 651 } 652 653 list_for_each_entry(clki, &hba->clk_list_head, list) { 654 if (!strcmp(clki->name, "core_clk")) { 655 if (freq == ULONG_MAX) { 656 clk_freq = clki->max_freq; 657 break; 658 } 659 660 if (is_pre_scale_up) 661 clk_freq = clki->max_freq; 662 else 663 clk_freq = clk_get_rate(clki->clk); 664 break; 665 } 666 667 } 668 669 cfg_timers: 670 /* If frequency is smaller than 1MHz, set to 1MHz */ 671 if (clk_freq < DEFAULT_CLK_RATE_HZ) 672 clk_freq = DEFAULT_CLK_RATE_HZ; 673 674 core_clk_cycles_per_us = clk_freq / USEC_PER_SEC; 675 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 676 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 677 /* 678 * make sure above write gets applied before we return from 679 * this function. 680 */ 681 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US); 682 } 683 684 return 0; 685 } 686 687 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 688 enum ufs_notify_change_status status) 689 { 690 int err = 0; 691 692 switch (status) { 693 case PRE_CHANGE: 694 if (ufs_qcom_cfg_timers(hba, false, ULONG_MAX)) { 695 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 696 __func__); 697 return -EINVAL; 698 } 699 700 err = ufs_qcom_set_core_clk_ctrl(hba, true, ULONG_MAX); 701 if (err) 702 dev_err(hba->dev, "cfg core clk ctrl failed\n"); 703 /* 704 * Some UFS devices (and may be host) have issues if LCC is 705 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 706 * before link startup which will make sure that both host 707 * and device TX LCC are disabled once link startup is 708 * completed. 709 */ 710 err = ufshcd_disable_host_tx_lcc(hba); 711 712 break; 713 default: 714 break; 715 } 716 717 return err; 718 } 719 720 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 721 { 722 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 723 724 /* reset gpio is optional */ 725 if (!host->device_reset) 726 return; 727 728 gpiod_set_value_cansleep(host->device_reset, asserted); 729 } 730 731 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 732 enum ufs_notify_change_status status) 733 { 734 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 735 736 if (status == PRE_CHANGE) 737 return 0; 738 739 if (!ufs_qcom_is_link_active(hba)) 740 ufs_qcom_disable_lane_clks(host); 741 742 743 /* reset the connected UFS device during power down */ 744 if (ufs_qcom_is_link_off(hba) && host->device_reset) 745 ufs_qcom_device_reset_ctrl(hba, true); 746 747 return ufs_qcom_ice_suspend(host); 748 } 749 750 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 751 { 752 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 753 int err; 754 755 err = ufs_qcom_enable_lane_clks(host); 756 if (err) 757 return err; 758 759 return ufs_qcom_ice_resume(host); 760 } 761 762 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 763 { 764 if (host->dev_ref_clk_ctrl_mmio && 765 (enable ^ host->is_dev_ref_clk_enabled)) { 766 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 767 768 if (enable) 769 temp |= host->dev_ref_clk_en_mask; 770 else 771 temp &= ~host->dev_ref_clk_en_mask; 772 773 /* 774 * If we are here to disable this clock it might be immediately 775 * after entering into hibern8 in which case we need to make 776 * sure that device ref_clk is active for specific time after 777 * hibern8 enter. 778 */ 779 if (!enable) { 780 unsigned long gating_wait; 781 782 gating_wait = host->hba->dev_info.clk_gating_wait_us; 783 if (!gating_wait) { 784 udelay(1); 785 } else { 786 /* 787 * bRefClkGatingWaitTime defines the minimum 788 * time for which the reference clock is 789 * required by device during transition from 790 * HS-MODE to LS-MODE or HIBERN8 state. Give it 791 * more delay to be on the safe side. 792 */ 793 gating_wait += 10; 794 usleep_range(gating_wait, gating_wait + 10); 795 } 796 } 797 798 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 799 800 /* 801 * Make sure the write to ref_clk reaches the destination and 802 * not stored in a Write Buffer (WB). 803 */ 804 readl(host->dev_ref_clk_ctrl_mmio); 805 806 /* 807 * If we call hibern8 exit after this, we need to make sure that 808 * device ref_clk is stable for at least 1us before the hibern8 809 * exit command. 810 */ 811 if (enable) 812 udelay(1); 813 814 host->is_dev_ref_clk_enabled = enable; 815 } 816 } 817 818 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 819 { 820 struct device *dev = host->hba->dev; 821 int ret; 822 823 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 824 if (ret < 0) { 825 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 826 return ret; 827 } 828 829 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 830 if (ret < 0) { 831 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 832 return ret; 833 } 834 835 return 0; 836 } 837 838 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 839 { 840 struct ufs_pa_layer_attr *p = &host->dev_req_params; 841 int gear = max_t(u32, p->gear_rx, p->gear_tx); 842 int lane = max_t(u32, p->lane_rx, p->lane_tx); 843 844 if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR, 845 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n", 846 gear, QCOM_UFS_MAX_GEAR)) 847 gear = QCOM_UFS_MAX_GEAR; 848 849 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE, 850 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n", 851 lane, QCOM_UFS_MAX_LANE)) 852 lane = QCOM_UFS_MAX_LANE; 853 854 if (ufshcd_is_hs_mode(p)) { 855 if (p->hs_rate == PA_HS_MODE_B) 856 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 857 else 858 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 859 } else { 860 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 861 } 862 } 863 864 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 865 { 866 struct __ufs_qcom_bw_table bw_table; 867 868 bw_table = ufs_qcom_get_bw_table(host); 869 870 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 871 } 872 873 static void ufs_qcom_set_tx_hs_equalizer(struct ufs_hba *hba, u32 gear, u32 tx_lanes) 874 { 875 u32 equalizer_val; 876 int ret, i; 877 878 /* Determine the equalizer value based on the gear */ 879 equalizer_val = (gear == 5) ? DEEMPHASIS_3_5_dB : NO_DEEMPHASIS; 880 881 for (i = 0; i < tx_lanes; i++) { 882 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HS_EQUALIZER, i), 883 equalizer_val); 884 if (ret) 885 dev_err(hba->dev, "%s: failed equalizer lane %d\n", 886 __func__, i); 887 } 888 } 889 890 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 891 enum ufs_notify_change_status status, 892 const struct ufs_pa_layer_attr *dev_max_params, 893 struct ufs_pa_layer_attr *dev_req_params) 894 { 895 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 896 struct ufs_host_params *host_params = &host->host_params; 897 int ret = 0; 898 899 if (!dev_req_params) { 900 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 901 return -EINVAL; 902 } 903 904 switch (status) { 905 case PRE_CHANGE: 906 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); 907 if (ret) { 908 dev_err(hba->dev, "%s: failed to determine capabilities\n", 909 __func__); 910 return ret; 911 } 912 913 /* 914 * During UFS driver probe, always update the PHY gear to match the negotiated 915 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled, 916 * the second init can program the optimal PHY settings. This allows one to start 917 * the first init with either the minimum or the maximum support gear. 918 */ 919 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { 920 /* 921 * Skip REINIT if the negotiated gear matches with the 922 * initial phy_gear. Otherwise, update the phy_gear to 923 * program the optimal gear setting during REINIT. 924 */ 925 if (host->phy_gear == dev_req_params->gear_tx) 926 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 927 else 928 host->phy_gear = dev_req_params->gear_tx; 929 } 930 931 /* enable the device ref clock before changing to HS mode */ 932 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 933 ufshcd_is_hs_mode(dev_req_params)) 934 ufs_qcom_dev_ref_clk_ctrl(host, true); 935 936 if (host->hw_ver.major >= 0x4) { 937 ufshcd_dme_configure_adapt(hba, 938 dev_req_params->gear_tx, 939 PA_INITIAL_ADAPT); 940 } 941 942 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING) 943 ufs_qcom_set_tx_hs_equalizer(hba, 944 dev_req_params->gear_tx, dev_req_params->lane_tx); 945 946 break; 947 case POST_CHANGE: 948 /* cache the power mode parameters to use internally */ 949 memcpy(&host->dev_req_params, 950 dev_req_params, sizeof(*dev_req_params)); 951 952 ufs_qcom_icc_update_bw(host); 953 954 /* disable the device ref clock if entered PWM mode */ 955 if (ufshcd_is_hs_mode(&hba->pwr_info) && 956 !ufshcd_is_hs_mode(dev_req_params)) 957 ufs_qcom_dev_ref_clk_ctrl(host, false); 958 break; 959 default: 960 ret = -EINVAL; 961 break; 962 } 963 964 return ret; 965 } 966 967 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 968 { 969 int err; 970 u32 pa_vs_config_reg1; 971 972 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 973 &pa_vs_config_reg1); 974 if (err) 975 return err; 976 977 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 978 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 979 (pa_vs_config_reg1 | (1 << 12))); 980 } 981 982 static void ufs_qcom_override_pa_tx_hsg1_sync_len(struct ufs_hba *hba) 983 { 984 int err; 985 986 err = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TX_HSG1_SYNC_LENGTH), 987 PA_TX_HSG1_SYNC_LENGTH_VAL); 988 if (err) 989 dev_err(hba->dev, "Failed (%d) set PA_TX_HSG1_SYNC_LENGTH\n", err); 990 } 991 992 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 993 { 994 int err = 0; 995 996 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 997 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 998 999 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH) 1000 ufs_qcom_override_pa_tx_hsg1_sync_len(hba); 1001 1002 return err; 1003 } 1004 1005 /* UFS device-specific quirks */ 1006 static struct ufs_dev_quirk ufs_qcom_dev_fixups[] = { 1007 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 1008 .model = UFS_ANY_MODEL, 1009 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 1010 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 1011 .model = UFS_ANY_MODEL, 1012 .quirk = UFS_DEVICE_QUIRK_DELAY_AFTER_LPM }, 1013 { .wmanufacturerid = UFS_VENDOR_WDC, 1014 .model = UFS_ANY_MODEL, 1015 .quirk = UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE }, 1016 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 1017 .model = UFS_ANY_MODEL, 1018 .quirk = UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH | 1019 UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING }, 1020 {} 1021 }; 1022 1023 static void ufs_qcom_fixup_dev_quirks(struct ufs_hba *hba) 1024 { 1025 ufshcd_fixup_dev_quirks(hba, ufs_qcom_dev_fixups); 1026 } 1027 1028 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 1029 { 1030 return ufshci_version(2, 0); 1031 } 1032 1033 /** 1034 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 1035 * @hba: host controller instance 1036 * 1037 * QCOM UFS host controller might have some non standard behaviours (quirks) 1038 * than what is specified by UFSHCI specification. Advertise all such 1039 * quirks to standard UFS host controller driver so standard takes them into 1040 * account. 1041 */ 1042 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 1043 { 1044 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); 1045 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1046 1047 if (host->hw_ver.major == 0x2) 1048 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 1049 1050 if (host->hw_ver.major > 0x3) 1051 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1052 1053 if (drvdata && drvdata->quirks) 1054 hba->quirks |= drvdata->quirks; 1055 } 1056 1057 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) 1058 { 1059 struct ufs_host_params *host_params = &host->host_params; 1060 u32 val, dev_major; 1061 1062 /* 1063 * Default to powering up the PHY to the max gear possible, which is 1064 * backwards compatible with lower gears but not optimal from 1065 * a power usage point of view. After device negotiation, if the 1066 * gear is lower a reinit will be performed to program the PHY 1067 * to the ideal gear for this combo of controller and device. 1068 */ 1069 host->phy_gear = host_params->hs_tx_gear; 1070 1071 if (host->hw_ver.major < 0x4) { 1072 /* 1073 * These controllers only have one PHY init sequence, 1074 * let's power up the PHY using that (the minimum supported 1075 * gear, UFS_HS_G2). 1076 */ 1077 host->phy_gear = UFS_HS_G2; 1078 } else if (host->hw_ver.major >= 0x5) { 1079 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); 1080 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val); 1081 1082 /* 1083 * Since the UFS device version is populated, let's remove the 1084 * REINIT quirk as the negotiated gear won't change during boot. 1085 * So there is no need to do reinit. 1086 */ 1087 if (dev_major != 0x0) 1088 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1089 1090 /* 1091 * For UFS 3.1 device and older, power up the PHY using HS-G4 1092 * PHY gear to save power. 1093 */ 1094 if (dev_major > 0x0 && dev_major < 0x4) 1095 host->phy_gear = UFS_HS_G4; 1096 } 1097 } 1098 1099 static void ufs_qcom_set_host_params(struct ufs_hba *hba) 1100 { 1101 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1102 struct ufs_host_params *host_params = &host->host_params; 1103 1104 ufshcd_init_host_params(host_params); 1105 1106 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 1107 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); 1108 } 1109 1110 static void ufs_qcom_set_host_caps(struct ufs_hba *hba) 1111 { 1112 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1113 1114 if (host->hw_ver.major >= 0x5) 1115 host->caps |= UFS_QCOM_CAP_ICE_CONFIG; 1116 } 1117 1118 static void ufs_qcom_set_caps(struct ufs_hba *hba) 1119 { 1120 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1121 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 1122 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1123 hba->caps |= UFSHCD_CAP_WB_EN; 1124 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 1125 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 1126 1127 ufs_qcom_set_host_caps(hba); 1128 } 1129 1130 /** 1131 * ufs_qcom_setup_clocks - enables/disable clocks 1132 * @hba: host controller instance 1133 * @on: If true, enable clocks else disable them. 1134 * @status: PRE_CHANGE or POST_CHANGE notify 1135 * 1136 * There are certain clocks which comes from the PHY so it needs 1137 * to be managed together along with controller clocks which also 1138 * provides a better power saving. Hence keep phy_power_off/on calls 1139 * in ufs_qcom_setup_clocks, so that PHY's regulators & clks can be 1140 * turned on/off along with UFS's clocks. 1141 * 1142 * Return: 0 on success, non-zero on failure. 1143 */ 1144 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 1145 enum ufs_notify_change_status status) 1146 { 1147 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1148 struct phy *phy; 1149 int err; 1150 1151 /* 1152 * In case ufs_qcom_init() is not yet done, simply ignore. 1153 * This ufs_qcom_setup_clocks() shall be called from 1154 * ufs_qcom_init() after init is done. 1155 */ 1156 if (!host) 1157 return 0; 1158 1159 phy = host->generic_phy; 1160 1161 switch (status) { 1162 case PRE_CHANGE: 1163 if (on) { 1164 ufs_qcom_icc_update_bw(host); 1165 } else { 1166 if (!ufs_qcom_is_link_active(hba)) { 1167 /* disable device ref_clk */ 1168 ufs_qcom_dev_ref_clk_ctrl(host, false); 1169 } 1170 1171 err = phy_power_off(phy); 1172 if (err) { 1173 dev_err(hba->dev, "phy power off failed, ret=%d\n", err); 1174 return err; 1175 } 1176 } 1177 break; 1178 case POST_CHANGE: 1179 if (on) { 1180 err = phy_power_on(phy); 1181 if (err) { 1182 dev_err(hba->dev, "phy power on failed, ret = %d\n", err); 1183 return err; 1184 } 1185 1186 /* enable the device ref clock for HS mode*/ 1187 if (ufshcd_is_hs_mode(&hba->pwr_info)) 1188 ufs_qcom_dev_ref_clk_ctrl(host, true); 1189 } else { 1190 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 1191 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 1192 } 1193 break; 1194 } 1195 1196 return 0; 1197 } 1198 1199 static int 1200 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 1201 { 1202 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1203 1204 ufs_qcom_assert_reset(host->hba); 1205 /* provide 1ms delay to let the reset pulse propagate. */ 1206 usleep_range(1000, 1100); 1207 return 0; 1208 } 1209 1210 static int 1211 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 1212 { 1213 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1214 1215 ufs_qcom_deassert_reset(host->hba); 1216 1217 /* 1218 * after reset deassertion, phy will need all ref clocks, 1219 * voltage, current to settle down before starting serdes. 1220 */ 1221 usleep_range(1000, 1100); 1222 return 0; 1223 } 1224 1225 static const struct reset_control_ops ufs_qcom_reset_ops = { 1226 .assert = ufs_qcom_reset_assert, 1227 .deassert = ufs_qcom_reset_deassert, 1228 }; 1229 1230 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 1231 { 1232 struct device *dev = host->hba->dev; 1233 int ret; 1234 1235 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 1236 if (IS_ERR(host->icc_ddr)) 1237 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 1238 "failed to acquire interconnect path\n"); 1239 1240 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1241 if (IS_ERR(host->icc_cpu)) 1242 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1243 "failed to acquire interconnect path\n"); 1244 1245 /* 1246 * Set Maximum bandwidth vote before initializing the UFS controller and 1247 * device. Ideally, a minimal interconnect vote would suffice for the 1248 * initialization, but a max vote would allow faster initialization. 1249 */ 1250 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1251 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1252 if (ret < 0) 1253 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1254 1255 return 0; 1256 } 1257 1258 /** 1259 * ufs_qcom_init - bind phy with controller 1260 * @hba: host controller instance 1261 * 1262 * Binds PHY with controller and powers up PHY enabling clocks 1263 * and regulators. 1264 * 1265 * Return: -EPROBE_DEFER if binding fails, returns negative error 1266 * on phy power up failure and returns zero on success. 1267 */ 1268 static int ufs_qcom_init(struct ufs_hba *hba) 1269 { 1270 int err; 1271 struct device *dev = hba->dev; 1272 struct ufs_qcom_host *host; 1273 struct ufs_clk_info *clki; 1274 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); 1275 1276 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1277 if (!host) 1278 return -ENOMEM; 1279 1280 /* Make a two way bind between the qcom host and the hba */ 1281 host->hba = hba; 1282 ufshcd_set_variant(hba, host); 1283 1284 /* Setup the optional reset control of HCI */ 1285 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1286 if (IS_ERR(host->core_reset)) { 1287 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1288 "Failed to get reset control\n"); 1289 goto out_variant_clear; 1290 } 1291 1292 /* Fire up the reset controller. Failure here is non-fatal. */ 1293 host->rcdev.of_node = dev->of_node; 1294 host->rcdev.ops = &ufs_qcom_reset_ops; 1295 host->rcdev.owner = dev->driver->owner; 1296 host->rcdev.nr_resets = 1; 1297 err = devm_reset_controller_register(dev, &host->rcdev); 1298 if (err) 1299 dev_warn(dev, "Failed to register reset controller\n"); 1300 1301 if (!has_acpi_companion(dev)) { 1302 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1303 if (IS_ERR(host->generic_phy)) { 1304 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1305 goto out_variant_clear; 1306 } 1307 } 1308 1309 err = ufs_qcom_icc_init(host); 1310 if (err) 1311 goto out_variant_clear; 1312 1313 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1314 GPIOD_OUT_HIGH); 1315 if (IS_ERR(host->device_reset)) { 1316 err = dev_err_probe(dev, PTR_ERR(host->device_reset), 1317 "Failed to acquire device reset gpio\n"); 1318 goto out_variant_clear; 1319 } 1320 1321 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1322 &host->hw_ver.minor, &host->hw_ver.step); 1323 1324 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1325 host->dev_ref_clk_en_mask = BIT(26); 1326 1327 list_for_each_entry(clki, &hba->clk_list_head, list) { 1328 if (!strcmp(clki->name, "core_clk_unipro")) 1329 clki->keep_link_active = true; 1330 } 1331 1332 err = ufs_qcom_init_lane_clks(host); 1333 if (err) 1334 goto out_variant_clear; 1335 1336 ufs_qcom_set_caps(hba); 1337 ufs_qcom_advertise_quirks(hba); 1338 ufs_qcom_set_host_params(hba); 1339 ufs_qcom_set_phy_gear(host); 1340 1341 err = ufs_qcom_ice_init(host); 1342 if (err) 1343 goto out_variant_clear; 1344 1345 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1346 1347 ufs_qcom_get_default_testbus_cfg(host); 1348 err = ufs_qcom_testbus_config(host); 1349 if (err) 1350 /* Failure is non-fatal */ 1351 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1352 __func__, err); 1353 1354 if (drvdata && drvdata->no_phy_retention) 1355 hba->spm_lvl = UFS_PM_LVL_5; 1356 1357 return 0; 1358 1359 out_variant_clear: 1360 ufshcd_set_variant(hba, NULL); 1361 1362 return err; 1363 } 1364 1365 static void ufs_qcom_exit(struct ufs_hba *hba) 1366 { 1367 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1368 1369 ufs_qcom_disable_lane_clks(host); 1370 phy_power_off(host->generic_phy); 1371 phy_exit(host->generic_phy); 1372 } 1373 1374 /** 1375 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles 1376 * 1377 * @hba: host controller instance 1378 * @cycles_in_1us: No of cycles in 1us to be configured 1379 * 1380 * Returns error if dme get/set configuration for 40ns fails 1381 * and returns zero on success. 1382 */ 1383 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, 1384 u32 cycles_in_1us) 1385 { 1386 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1387 u32 cycles_in_40ns; 1388 u32 reg; 1389 int err; 1390 1391 /* 1392 * UFS host controller V4.0.0 onwards needs to program 1393 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed 1394 * frequency of unipro core clk of UFS host controller. 1395 */ 1396 if (host->hw_ver.major < 4) 1397 return 0; 1398 1399 /* 1400 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not 1401 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will 1402 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware 1403 * specification expect to be 16. Hence use exact hardware spec 1404 * mandated value for cycles_in_40ns instead of calculating using 1405 * generic formulae. 1406 */ 1407 switch (cycles_in_1us) { 1408 case UNIPRO_CORE_CLK_FREQ_403_MHZ: 1409 cycles_in_40ns = 16; 1410 break; 1411 case UNIPRO_CORE_CLK_FREQ_300_MHZ: 1412 cycles_in_40ns = 12; 1413 break; 1414 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ: 1415 cycles_in_40ns = 8; 1416 break; 1417 case UNIPRO_CORE_CLK_FREQ_150_MHZ: 1418 cycles_in_40ns = 6; 1419 break; 1420 case UNIPRO_CORE_CLK_FREQ_100_MHZ: 1421 cycles_in_40ns = 4; 1422 break; 1423 case UNIPRO_CORE_CLK_FREQ_75_MHZ: 1424 cycles_in_40ns = 3; 1425 break; 1426 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ: 1427 cycles_in_40ns = 2; 1428 break; 1429 default: 1430 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", 1431 cycles_in_1us); 1432 return -EINVAL; 1433 } 1434 1435 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); 1436 if (err) 1437 return err; 1438 1439 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; 1440 reg |= cycles_in_40ns; 1441 1442 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); 1443 } 1444 1445 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq) 1446 { 1447 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1448 struct list_head *head = &hba->clk_list_head; 1449 struct ufs_clk_info *clki; 1450 u32 cycles_in_1us = 0; 1451 u32 core_clk_ctrl_reg; 1452 unsigned long clk_freq; 1453 int err; 1454 1455 if (hba->use_pm_opp && freq != ULONG_MAX) { 1456 clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro"); 1457 if (clk_freq) { 1458 cycles_in_1us = ceil(clk_freq, HZ_PER_MHZ); 1459 goto set_core_clk_ctrl; 1460 } 1461 } 1462 1463 list_for_each_entry(clki, head, list) { 1464 if (!IS_ERR_OR_NULL(clki->clk) && 1465 !strcmp(clki->name, "core_clk_unipro")) { 1466 if (!clki->max_freq) { 1467 cycles_in_1us = 150; /* default for backwards compatibility */ 1468 break; 1469 } 1470 1471 if (freq == ULONG_MAX) { 1472 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); 1473 break; 1474 } 1475 1476 if (is_scale_up) 1477 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); 1478 else 1479 cycles_in_1us = ceil(clk_get_rate(clki->clk), HZ_PER_MHZ); 1480 break; 1481 } 1482 } 1483 1484 set_core_clk_ctrl: 1485 err = ufshcd_dme_get(hba, 1486 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1487 &core_clk_ctrl_reg); 1488 if (err) 1489 return err; 1490 1491 /* Bit mask is different for UFS host controller V4.0.0 onwards */ 1492 if (host->hw_ver.major >= 4) { 1493 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us)) 1494 return -ERANGE; 1495 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4; 1496 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us); 1497 } else { 1498 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us)) 1499 return -ERANGE; 1500 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK; 1501 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); 1502 } 1503 1504 /* Clear CORE_CLK_DIV_EN */ 1505 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1506 1507 err = ufshcd_dme_set(hba, 1508 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1509 core_clk_ctrl_reg); 1510 if (err) 1511 return err; 1512 1513 /* Configure unipro core clk 40ns attribute */ 1514 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); 1515 } 1516 1517 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long freq) 1518 { 1519 int ret; 1520 1521 ret = ufs_qcom_cfg_timers(hba, true, freq); 1522 if (ret) { 1523 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); 1524 return ret; 1525 } 1526 /* set unipro core clock attributes and clear clock divider */ 1527 return ufs_qcom_set_core_clk_ctrl(hba, true, freq); 1528 } 1529 1530 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1531 { 1532 return 0; 1533 } 1534 1535 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1536 { 1537 int err; 1538 u32 core_clk_ctrl_reg; 1539 1540 err = ufshcd_dme_get(hba, 1541 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1542 &core_clk_ctrl_reg); 1543 1544 /* make sure CORE_CLK_DIV_EN is cleared */ 1545 if (!err && 1546 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1547 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1548 err = ufshcd_dme_set(hba, 1549 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1550 core_clk_ctrl_reg); 1551 } 1552 1553 return err; 1554 } 1555 1556 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq) 1557 { 1558 int ret; 1559 1560 ret = ufs_qcom_cfg_timers(hba, false, freq); 1561 if (ret) { 1562 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); 1563 return ret; 1564 } 1565 /* set unipro core clock attributes and clear clock divider */ 1566 return ufs_qcom_set_core_clk_ctrl(hba, false, freq); 1567 } 1568 1569 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, 1570 unsigned long target_freq, 1571 enum ufs_notify_change_status status) 1572 { 1573 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1574 int err; 1575 1576 /* check the host controller state before sending hibern8 cmd */ 1577 if (!ufshcd_is_hba_active(hba)) 1578 return 0; 1579 1580 if (status == PRE_CHANGE) { 1581 err = ufshcd_uic_hibern8_enter(hba); 1582 if (err) 1583 return err; 1584 if (scale_up) 1585 err = ufs_qcom_clk_scale_up_pre_change(hba, target_freq); 1586 else 1587 err = ufs_qcom_clk_scale_down_pre_change(hba); 1588 1589 if (err) { 1590 ufshcd_uic_hibern8_exit(hba); 1591 return err; 1592 } 1593 } else { 1594 if (scale_up) 1595 err = ufs_qcom_clk_scale_up_post_change(hba); 1596 else 1597 err = ufs_qcom_clk_scale_down_post_change(hba, target_freq); 1598 1599 1600 if (err) { 1601 ufshcd_uic_hibern8_exit(hba); 1602 return err; 1603 } 1604 1605 ufs_qcom_icc_update_bw(host); 1606 ufshcd_uic_hibern8_exit(hba); 1607 } 1608 1609 return 0; 1610 } 1611 1612 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1613 { 1614 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1615 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1616 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1617 } 1618 1619 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1620 { 1621 /* provide a legal default configuration */ 1622 host->testbus.select_major = TSTBUS_UNIPRO; 1623 host->testbus.select_minor = 37; 1624 } 1625 1626 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1627 { 1628 if (host->testbus.select_major >= TSTBUS_MAX) { 1629 dev_err(host->hba->dev, 1630 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1631 __func__, host->testbus.select_major); 1632 return false; 1633 } 1634 1635 return true; 1636 } 1637 1638 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1639 { 1640 int reg; 1641 int offset; 1642 u32 mask = TEST_BUS_SUB_SEL_MASK; 1643 1644 if (!host) 1645 return -EINVAL; 1646 1647 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1648 return -EPERM; 1649 1650 switch (host->testbus.select_major) { 1651 case TSTBUS_UAWM: 1652 reg = UFS_TEST_BUS_CTRL_0; 1653 offset = 24; 1654 break; 1655 case TSTBUS_UARM: 1656 reg = UFS_TEST_BUS_CTRL_0; 1657 offset = 16; 1658 break; 1659 case TSTBUS_TXUC: 1660 reg = UFS_TEST_BUS_CTRL_0; 1661 offset = 8; 1662 break; 1663 case TSTBUS_RXUC: 1664 reg = UFS_TEST_BUS_CTRL_0; 1665 offset = 0; 1666 break; 1667 case TSTBUS_DFC: 1668 reg = UFS_TEST_BUS_CTRL_1; 1669 offset = 24; 1670 break; 1671 case TSTBUS_TRLUT: 1672 reg = UFS_TEST_BUS_CTRL_1; 1673 offset = 16; 1674 break; 1675 case TSTBUS_TMRLUT: 1676 reg = UFS_TEST_BUS_CTRL_1; 1677 offset = 8; 1678 break; 1679 case TSTBUS_OCSC: 1680 reg = UFS_TEST_BUS_CTRL_1; 1681 offset = 0; 1682 break; 1683 case TSTBUS_WRAPPER: 1684 reg = UFS_TEST_BUS_CTRL_2; 1685 offset = 16; 1686 break; 1687 case TSTBUS_COMBINED: 1688 reg = UFS_TEST_BUS_CTRL_2; 1689 offset = 8; 1690 break; 1691 case TSTBUS_UTP_HCI: 1692 reg = UFS_TEST_BUS_CTRL_2; 1693 offset = 0; 1694 break; 1695 case TSTBUS_UNIPRO: 1696 reg = UFS_UNIPRO_CFG; 1697 offset = 20; 1698 mask = 0xFFF; 1699 break; 1700 /* 1701 * No need for a default case, since 1702 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 1703 * is legal 1704 */ 1705 } 1706 mask <<= offset; 1707 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 1708 (u32)host->testbus.select_major << 19, 1709 REG_UFS_CFG1); 1710 ufshcd_rmwl(host->hba, mask, 1711 (u32)host->testbus.select_minor << offset, 1712 reg); 1713 ufs_qcom_enable_test_bus(host); 1714 1715 return 0; 1716 } 1717 1718 static void ufs_qcom_dump_testbus(struct ufs_hba *hba) 1719 { 1720 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1721 int i, j, nminor = 0, testbus_len = 0; 1722 u32 *testbus __free(kfree) = NULL; 1723 char *prefix; 1724 1725 testbus = kmalloc_array(256, sizeof(u32), GFP_KERNEL); 1726 if (!testbus) 1727 return; 1728 1729 for (j = 0; j < TSTBUS_MAX; j++) { 1730 nminor = testbus_info[j].nminor; 1731 prefix = testbus_info[j].prefix; 1732 host->testbus.select_major = j; 1733 testbus_len = nminor * sizeof(u32); 1734 for (i = 0; i < nminor; i++) { 1735 host->testbus.select_minor = i; 1736 ufs_qcom_testbus_config(host); 1737 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS); 1738 } 1739 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 1740 16, 4, testbus, testbus_len, false); 1741 } 1742 } 1743 1744 static int ufs_qcom_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1745 const char *prefix, enum ufshcd_res id) 1746 { 1747 u32 *regs __free(kfree) = NULL; 1748 size_t pos; 1749 1750 if (offset % 4 != 0 || len % 4 != 0) 1751 return -EINVAL; 1752 1753 regs = kzalloc(len, GFP_ATOMIC); 1754 if (!regs) 1755 return -ENOMEM; 1756 1757 for (pos = 0; pos < len; pos += 4) 1758 regs[pos / 4] = readl(hba->res[id].base + offset + pos); 1759 1760 print_hex_dump(KERN_ERR, prefix, 1761 len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE, 1762 16, 4, regs, len, false); 1763 1764 return 0; 1765 } 1766 1767 static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba) 1768 { 1769 struct dump_info { 1770 size_t offset; 1771 size_t len; 1772 const char *prefix; 1773 enum ufshcd_res id; 1774 }; 1775 1776 struct dump_info mcq_dumps[] = { 1777 {0x0, 256 * 4, "MCQ HCI-0 ", RES_MCQ}, 1778 {0x400, 256 * 4, "MCQ HCI-1 ", RES_MCQ}, 1779 {0x0, 5 * 4, "MCQ VS-0 ", RES_MCQ_VS}, 1780 {0x0, 256 * 4, "MCQ SQD-0 ", RES_MCQ_SQD}, 1781 {0x400, 256 * 4, "MCQ SQD-1 ", RES_MCQ_SQD}, 1782 {0x800, 256 * 4, "MCQ SQD-2 ", RES_MCQ_SQD}, 1783 {0xc00, 256 * 4, "MCQ SQD-3 ", RES_MCQ_SQD}, 1784 {0x1000, 256 * 4, "MCQ SQD-4 ", RES_MCQ_SQD}, 1785 {0x1400, 256 * 4, "MCQ SQD-5 ", RES_MCQ_SQD}, 1786 {0x1800, 256 * 4, "MCQ SQD-6 ", RES_MCQ_SQD}, 1787 {0x1c00, 256 * 4, "MCQ SQD-7 ", RES_MCQ_SQD}, 1788 }; 1789 1790 for (int i = 0; i < ARRAY_SIZE(mcq_dumps); i++) { 1791 ufs_qcom_dump_regs(hba, mcq_dumps[i].offset, mcq_dumps[i].len, 1792 mcq_dumps[i].prefix, mcq_dumps[i].id); 1793 cond_resched(); 1794 } 1795 } 1796 1797 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 1798 { 1799 u32 reg; 1800 struct ufs_qcom_host *host; 1801 1802 host = ufshcd_get_variant(hba); 1803 1804 dev_err(hba->dev, "HW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_ENTER_CNT)); 1805 dev_err(hba->dev, "HW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_EXIT_CNT)); 1806 1807 dev_err(hba->dev, "SW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_ENTER_CNT)); 1808 dev_err(hba->dev, "SW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_EXIT_CNT)); 1809 1810 dev_err(hba->dev, "SW_AFTER_HW_H8_ENTER_CNT=%d\n", 1811 ufshcd_readl(hba, REG_UFS_SW_AFTER_HW_H8_ENTER_CNT)); 1812 1813 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 1814 "HCI Vendor Specific Registers "); 1815 1816 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 1817 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 1818 1819 reg = ufshcd_readl(hba, REG_UFS_CFG1); 1820 reg |= UTP_DBG_RAMS_EN; 1821 ufshcd_writel(hba, reg, REG_UFS_CFG1); 1822 1823 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 1824 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 1825 1826 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 1827 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 1828 1829 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 1830 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 1831 1832 /* clear bit 17 - UTP_DBG_RAMS_EN */ 1833 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 1834 1835 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 1836 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 1837 1838 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 1839 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 1840 1841 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 1842 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 1843 1844 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 1845 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 1846 1847 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 1848 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 1849 1850 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 1851 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 1852 1853 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 1854 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 1855 1856 if (hba->mcq_enabled) { 1857 reg = ufs_qcom_get_debug_reg_offset(host, UFS_RD_REG_MCQ); 1858 ufshcd_dump_regs(hba, reg, 64 * 4, "HCI MCQ Debug Registers "); 1859 } 1860 1861 /* ensure below dumps occur only in task context due to blocking calls. */ 1862 if (in_task()) { 1863 /* Dump MCQ Host Vendor Specific Registers */ 1864 if (hba->mcq_enabled) 1865 ufs_qcom_dump_mcq_hci_regs(hba); 1866 1867 /* voluntarily yield the CPU as we are dumping too much data */ 1868 ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS "); 1869 cond_resched(); 1870 ufs_qcom_dump_testbus(hba); 1871 } 1872 } 1873 1874 /** 1875 * ufs_qcom_device_reset() - toggle the (optional) device reset line 1876 * @hba: per-adapter instance 1877 * 1878 * Toggles the (optional) reset line to reset the attached device. 1879 */ 1880 static int ufs_qcom_device_reset(struct ufs_hba *hba) 1881 { 1882 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1883 1884 /* reset gpio is optional */ 1885 if (!host->device_reset) 1886 return -EOPNOTSUPP; 1887 1888 /* 1889 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 1890 * be on the safe side. 1891 */ 1892 ufs_qcom_device_reset_ctrl(hba, true); 1893 usleep_range(10, 15); 1894 1895 ufs_qcom_device_reset_ctrl(hba, false); 1896 usleep_range(10, 15); 1897 1898 return 0; 1899 } 1900 1901 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1902 struct devfreq_dev_profile *p, 1903 struct devfreq_simple_ondemand_data *d) 1904 { 1905 p->polling_ms = 60; 1906 p->timer = DEVFREQ_TIMER_DELAYED; 1907 d->upthreshold = 70; 1908 d->downdifferential = 5; 1909 1910 hba->clk_scaling.suspend_on_no_request = true; 1911 } 1912 1913 /* Resources */ 1914 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { 1915 {.name = "ufs_mem",}, 1916 {.name = "mcq",}, 1917 /* Submission Queue DAO */ 1918 {.name = "mcq_sqd",}, 1919 /* Submission Queue Interrupt Status */ 1920 {.name = "mcq_sqis",}, 1921 /* Completion Queue DAO */ 1922 {.name = "mcq_cqd",}, 1923 /* Completion Queue Interrupt Status */ 1924 {.name = "mcq_cqis",}, 1925 /* MCQ vendor specific */ 1926 {.name = "mcq_vs",}, 1927 }; 1928 1929 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 1930 { 1931 struct platform_device *pdev = to_platform_device(hba->dev); 1932 struct ufshcd_res_info *res; 1933 struct resource *res_mem, *res_mcq; 1934 int i, ret; 1935 1936 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); 1937 1938 for (i = 0; i < RES_MAX; i++) { 1939 res = &hba->res[i]; 1940 res->resource = platform_get_resource_byname(pdev, 1941 IORESOURCE_MEM, 1942 res->name); 1943 if (!res->resource) { 1944 dev_info(hba->dev, "Resource %s not provided\n", res->name); 1945 if (i == RES_UFS) 1946 return -ENODEV; 1947 continue; 1948 } else if (i == RES_UFS) { 1949 res_mem = res->resource; 1950 res->base = hba->mmio_base; 1951 continue; 1952 } 1953 1954 res->base = devm_ioremap_resource(hba->dev, res->resource); 1955 if (IS_ERR(res->base)) { 1956 dev_err(hba->dev, "Failed to map res %s, err=%d\n", 1957 res->name, (int)PTR_ERR(res->base)); 1958 ret = PTR_ERR(res->base); 1959 res->base = NULL; 1960 return ret; 1961 } 1962 } 1963 1964 /* MCQ resource provided in DT */ 1965 res = &hba->res[RES_MCQ]; 1966 /* Bail if MCQ resource is provided */ 1967 if (res->base) 1968 goto out; 1969 1970 /* Explicitly allocate MCQ resource from ufs_mem */ 1971 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); 1972 if (!res_mcq) 1973 return -ENOMEM; 1974 1975 res_mcq->start = res_mem->start + 1976 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); 1977 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; 1978 res_mcq->flags = res_mem->flags; 1979 res_mcq->name = "mcq"; 1980 1981 ret = insert_resource(&iomem_resource, res_mcq); 1982 if (ret) { 1983 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", 1984 ret); 1985 return ret; 1986 } 1987 1988 res->base = devm_ioremap_resource(hba->dev, res_mcq); 1989 if (IS_ERR(res->base)) { 1990 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", 1991 (int)PTR_ERR(res->base)); 1992 ret = PTR_ERR(res->base); 1993 goto ioremap_err; 1994 } 1995 1996 out: 1997 hba->mcq_base = res->base; 1998 return 0; 1999 ioremap_err: 2000 res->base = NULL; 2001 remove_resource(res_mcq); 2002 return ret; 2003 } 2004 2005 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 2006 { 2007 struct ufshcd_res_info *mem_res, *sqdao_res; 2008 struct ufshcd_mcq_opr_info_t *opr; 2009 int i; 2010 2011 mem_res = &hba->res[RES_UFS]; 2012 sqdao_res = &hba->res[RES_MCQ_SQD]; 2013 2014 if (!mem_res->base || !sqdao_res->base) 2015 return -EINVAL; 2016 2017 for (i = 0; i < OPR_MAX; i++) { 2018 opr = &hba->mcq_opr[i]; 2019 opr->offset = sqdao_res->resource->start - 2020 mem_res->resource->start + 0x40 * i; 2021 opr->stride = 0x100; 2022 opr->base = sqdao_res->base + 0x40 * i; 2023 } 2024 2025 return 0; 2026 } 2027 2028 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 2029 { 2030 /* Qualcomm HC supports up to 64 */ 2031 return MAX_SUPP_MAC; 2032 } 2033 2034 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 2035 unsigned long *ocqs) 2036 { 2037 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; 2038 2039 if (!mcq_vs_res->base) 2040 return -EINVAL; 2041 2042 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); 2043 2044 return 0; 2045 } 2046 2047 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 2048 { 2049 struct device *dev = msi_desc_to_dev(desc); 2050 struct ufs_hba *hba = dev_get_drvdata(dev); 2051 2052 ufshcd_mcq_config_esi(hba, msg); 2053 } 2054 2055 struct ufs_qcom_irq { 2056 unsigned int irq; 2057 unsigned int idx; 2058 struct ufs_hba *hba; 2059 }; 2060 2061 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 2062 { 2063 struct ufs_qcom_irq *qi = data; 2064 struct ufs_hba *hba = qi->hba; 2065 struct ufs_hw_queue *hwq = &hba->uhq[qi->idx]; 2066 2067 ufshcd_mcq_write_cqis(hba, 0x1, qi->idx); 2068 ufshcd_mcq_poll_cqe_lock(hba, hwq); 2069 2070 return IRQ_HANDLED; 2071 } 2072 2073 static void ufs_qcom_irq_free(struct ufs_qcom_irq *uqi) 2074 { 2075 for (struct ufs_qcom_irq *q = uqi; q->irq; q++) 2076 devm_free_irq(q->hba->dev, q->irq, q->hba); 2077 2078 platform_device_msi_free_irqs_all(uqi->hba->dev); 2079 devm_kfree(uqi->hba->dev, uqi); 2080 } 2081 2082 DEFINE_FREE(ufs_qcom_irq, struct ufs_qcom_irq *, if (_T) ufs_qcom_irq_free(_T)) 2083 2084 static int ufs_qcom_config_esi(struct ufs_hba *hba) 2085 { 2086 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2087 int nr_irqs, ret; 2088 2089 if (host->esi_enabled) 2090 return 0; 2091 2092 /* 2093 * 1. We only handle CQs as of now. 2094 * 2. Poll queues do not need ESI. 2095 */ 2096 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 2097 2098 struct ufs_qcom_irq *qi __free(ufs_qcom_irq) = 2099 devm_kcalloc(hba->dev, nr_irqs, sizeof(*qi), GFP_KERNEL); 2100 if (!qi) 2101 return -ENOMEM; 2102 /* Preset so __free() has a pointer to hba in all error paths */ 2103 qi[0].hba = hba; 2104 2105 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, 2106 ufs_qcom_write_msi_msg); 2107 if (ret) { 2108 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); 2109 return ret; 2110 } 2111 2112 for (int idx = 0; idx < nr_irqs; idx++) { 2113 qi[idx].irq = msi_get_virq(hba->dev, idx); 2114 qi[idx].idx = idx; 2115 qi[idx].hba = hba; 2116 2117 ret = devm_request_irq(hba->dev, qi[idx].irq, ufs_qcom_mcq_esi_handler, 2118 IRQF_SHARED, "qcom-mcq-esi", qi + idx); 2119 if (ret) { 2120 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", 2121 __func__, qi[idx].irq, ret); 2122 qi[idx].irq = 0; 2123 return ret; 2124 } 2125 } 2126 2127 retain_and_null_ptr(qi); 2128 2129 if (host->hw_ver.major >= 6) { 2130 ufshcd_rmwl(hba, ESI_VEC_MASK, FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), 2131 REG_UFS_CFG3); 2132 } 2133 ufshcd_mcq_enable_esi(hba); 2134 host->esi_enabled = true; 2135 return 0; 2136 } 2137 2138 static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba, 2139 unsigned long freq, char *name) 2140 { 2141 struct ufs_clk_info *clki; 2142 struct dev_pm_opp *opp; 2143 unsigned long clk_freq; 2144 int idx = 0; 2145 bool found = false; 2146 2147 opp = dev_pm_opp_find_freq_exact_indexed(hba->dev, freq, 0, true); 2148 if (IS_ERR(opp)) { 2149 dev_err(hba->dev, "Failed to find OPP for exact frequency %lu\n", freq); 2150 return 0; 2151 } 2152 2153 list_for_each_entry(clki, &hba->clk_list_head, list) { 2154 if (!strcmp(clki->name, name)) { 2155 found = true; 2156 break; 2157 } 2158 2159 idx++; 2160 } 2161 2162 if (!found) { 2163 dev_err(hba->dev, "Failed to find clock '%s' in clk list\n", name); 2164 dev_pm_opp_put(opp); 2165 return 0; 2166 } 2167 2168 clk_freq = dev_pm_opp_get_freq_indexed(opp, idx); 2169 2170 dev_pm_opp_put(opp); 2171 2172 return clk_freq; 2173 } 2174 2175 static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) 2176 { 2177 u32 gear = UFS_HS_DONT_CHANGE; 2178 unsigned long unipro_freq; 2179 2180 if (!hba->use_pm_opp) 2181 return gear; 2182 2183 unipro_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro"); 2184 switch (unipro_freq) { 2185 case 403000000: 2186 gear = UFS_HS_G5; 2187 break; 2188 case 300000000: 2189 gear = UFS_HS_G4; 2190 break; 2191 case 201500000: 2192 gear = UFS_HS_G3; 2193 break; 2194 case 150000000: 2195 case 100000000: 2196 gear = UFS_HS_G2; 2197 break; 2198 case 75000000: 2199 case 37500000: 2200 gear = UFS_HS_G1; 2201 break; 2202 default: 2203 dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq); 2204 return UFS_HS_DONT_CHANGE; 2205 } 2206 2207 return min_t(u32, gear, hba->max_pwr_info.info.gear_rx); 2208 } 2209 2210 /* 2211 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 2212 * 2213 * The variant operations configure the necessary controller and PHY 2214 * handshake during initialization. 2215 */ 2216 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 2217 .name = "qcom", 2218 .init = ufs_qcom_init, 2219 .exit = ufs_qcom_exit, 2220 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 2221 .clk_scale_notify = ufs_qcom_clk_scale_notify, 2222 .setup_clocks = ufs_qcom_setup_clocks, 2223 .hce_enable_notify = ufs_qcom_hce_enable_notify, 2224 .link_startup_notify = ufs_qcom_link_startup_notify, 2225 .pwr_change_notify = ufs_qcom_pwr_change_notify, 2226 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 2227 .fixup_dev_quirks = ufs_qcom_fixup_dev_quirks, 2228 .suspend = ufs_qcom_suspend, 2229 .resume = ufs_qcom_resume, 2230 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 2231 .device_reset = ufs_qcom_device_reset, 2232 .config_scaling_param = ufs_qcom_config_scaling_param, 2233 .mcq_config_resource = ufs_qcom_mcq_config_resource, 2234 .get_hba_mac = ufs_qcom_get_hba_mac, 2235 .op_runtime_config = ufs_qcom_op_runtime_config, 2236 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 2237 .config_esi = ufs_qcom_config_esi, 2238 .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, 2239 }; 2240 2241 /** 2242 * ufs_qcom_probe - probe routine of the driver 2243 * @pdev: pointer to Platform device handle 2244 * 2245 * Return: zero for success and non-zero for failure. 2246 */ 2247 static int ufs_qcom_probe(struct platform_device *pdev) 2248 { 2249 int err; 2250 struct device *dev = &pdev->dev; 2251 2252 /* Perform generic probe */ 2253 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); 2254 if (err) 2255 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 2256 2257 return 0; 2258 } 2259 2260 /** 2261 * ufs_qcom_remove - set driver_data of the device to NULL 2262 * @pdev: pointer to platform device handle 2263 * 2264 * Always returns 0 2265 */ 2266 static void ufs_qcom_remove(struct platform_device *pdev) 2267 { 2268 struct ufs_hba *hba = platform_get_drvdata(pdev); 2269 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2270 2271 ufshcd_pltfrm_remove(pdev); 2272 if (host->esi_enabled) 2273 platform_device_msi_free_irqs_all(hba->dev); 2274 } 2275 2276 static const struct ufs_qcom_drvdata ufs_qcom_sm8550_drvdata = { 2277 .quirks = UFSHCD_QUIRK_BROKEN_LSDBS_CAP, 2278 .no_phy_retention = true, 2279 }; 2280 2281 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 2282 { .compatible = "qcom,ufshc" }, 2283 { .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata }, 2284 { .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata }, 2285 {}, 2286 }; 2287 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 2288 2289 #ifdef CONFIG_ACPI 2290 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 2291 { "QCOM24A5" }, 2292 { }, 2293 }; 2294 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 2295 #endif 2296 2297 static const struct dev_pm_ops ufs_qcom_pm_ops = { 2298 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 2299 .prepare = ufshcd_suspend_prepare, 2300 .complete = ufshcd_resume_complete, 2301 #ifdef CONFIG_PM_SLEEP 2302 .suspend = ufshcd_system_suspend, 2303 .resume = ufshcd_system_resume, 2304 .freeze = ufshcd_system_freeze, 2305 .restore = ufshcd_system_restore, 2306 .thaw = ufshcd_system_thaw, 2307 #endif 2308 }; 2309 2310 static struct platform_driver ufs_qcom_pltform = { 2311 .probe = ufs_qcom_probe, 2312 .remove = ufs_qcom_remove, 2313 .driver = { 2314 .name = "ufshcd-qcom", 2315 .pm = &ufs_qcom_pm_ops, 2316 .of_match_table = of_match_ptr(ufs_qcom_of_match), 2317 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 2318 }, 2319 }; 2320 module_platform_driver(ufs_qcom_pltform); 2321 2322 MODULE_DESCRIPTION("Qualcomm UFS host controller driver"); 2323 MODULE_LICENSE("GPL v2"); 2324