1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/clk.h> 8 #include <linux/cleanup.h> 9 #include <linux/delay.h> 10 #include <linux/devfreq.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/interconnect.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/reset-controller.h> 18 #include <linux/time.h> 19 #include <linux/unaligned.h> 20 #include <linux/units.h> 21 22 #include <soc/qcom/ice.h> 23 24 #include <ufs/ufshcd.h> 25 #include <ufs/ufshci.h> 26 #include <ufs/ufs_quirks.h> 27 #include <ufs/unipro.h> 28 #include "ufshcd-pltfrm.h" 29 #include "ufs-qcom.h" 30 31 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 32 #define MCQ_QCFGPTR_UNIT 0x200 33 #define MCQ_SQATTR_OFFSET(c) \ 34 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 35 #define MCQ_QCFG_SIZE 0x40 36 37 /* De-emphasis for gear-5 */ 38 #define DEEMPHASIS_3_5_dB 0x04 39 #define NO_DEEMPHASIS 0x0 40 41 #define UFS_ICE_SYNC_RST_SEL BIT(3) 42 #define UFS_ICE_SYNC_RST_SW BIT(4) 43 44 enum { 45 TSTBUS_UAWM, 46 TSTBUS_UARM, 47 TSTBUS_TXUC, 48 TSTBUS_RXUC, 49 TSTBUS_DFC, 50 TSTBUS_TRLUT, 51 TSTBUS_TMRLUT, 52 TSTBUS_OCSC, 53 TSTBUS_UTP_HCI, 54 TSTBUS_COMBINED, 55 TSTBUS_WRAPPER, 56 TSTBUS_UNIPRO, 57 TSTBUS_MAX, 58 }; 59 60 #define QCOM_UFS_MAX_GEAR 5 61 #define QCOM_UFS_MAX_LANE 2 62 63 enum { 64 MODE_MIN, 65 MODE_PWM, 66 MODE_HS_RA, 67 MODE_HS_RB, 68 MODE_MAX, 69 }; 70 71 static const struct __ufs_qcom_bw_table { 72 u32 mem_bw; 73 u32 cfg_bw; 74 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 75 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 76 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 77 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 78 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 79 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 80 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 }, 81 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 82 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 83 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 84 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 85 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 }, 86 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 87 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 88 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 89 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 90 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 91 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 92 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 93 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 94 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 95 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 96 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 97 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 98 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 99 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 100 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 101 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 102 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 103 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 104 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 105 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 106 [MODE_MAX][0][0] = { 7643136, 819200 }, 107 }; 108 109 static const struct { 110 int nminor; 111 char *prefix; 112 } testbus_info[TSTBUS_MAX] = { 113 [TSTBUS_UAWM] = {32, "TSTBUS_UAWM"}, 114 [TSTBUS_UARM] = {32, "TSTBUS_UARM"}, 115 [TSTBUS_TXUC] = {32, "TSTBUS_TXUC"}, 116 [TSTBUS_RXUC] = {32, "TSTBUS_RXUC"}, 117 [TSTBUS_DFC] = {32, "TSTBUS_DFC"}, 118 [TSTBUS_TRLUT] = {32, "TSTBUS_TRLUT"}, 119 [TSTBUS_TMRLUT] = {32, "TSTBUS_TMRLUT"}, 120 [TSTBUS_OCSC] = {32, "TSTBUS_OCSC"}, 121 [TSTBUS_UTP_HCI] = {32, "TSTBUS_UTP_HCI"}, 122 [TSTBUS_COMBINED] = {32, "TSTBUS_COMBINED"}, 123 [TSTBUS_WRAPPER] = {32, "TSTBUS_WRAPPER"}, 124 [TSTBUS_UNIPRO] = {256, "TSTBUS_UNIPRO"}, 125 }; 126 127 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 128 static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba, 129 unsigned long freq, char *name); 130 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq); 131 132 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 133 { 134 return container_of(rcd, struct ufs_qcom_host, rcdev); 135 } 136 137 #ifdef CONFIG_SCSI_UFS_CRYPTO 138 /** 139 * ufs_qcom_config_ice_allocator() - ICE core allocator configuration 140 * 141 * @host: pointer to qcom specific variant structure. 142 */ 143 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) 144 { 145 struct ufs_hba *hba = host->hba; 146 static const uint8_t val[4] = { NUM_RX_R1W0, NUM_TX_R0W1, NUM_RX_R1W1, NUM_TX_R1W1 }; 147 u32 config; 148 149 if (!(host->caps & UFS_QCOM_CAP_ICE_CONFIG) || 150 !(host->hba->caps & UFSHCD_CAP_CRYPTO)) 151 return; 152 153 config = get_unaligned_le32(val); 154 155 ufshcd_writel(hba, ICE_ALLOCATOR_TYPE, REG_UFS_MEM_ICE_CONFIG); 156 ufshcd_writel(hba, config, REG_UFS_MEM_ICE_NUM_CORE); 157 } 158 159 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 160 { 161 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 162 qcom_ice_enable(host->ice); 163 } 164 165 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops; /* forward decl */ 166 167 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 168 { 169 struct ufs_hba *hba = host->hba; 170 struct blk_crypto_profile *profile = &hba->crypto_profile; 171 struct device *dev = hba->dev; 172 struct qcom_ice *ice; 173 union ufs_crypto_capabilities caps; 174 union ufs_crypto_cap_entry cap; 175 int err; 176 int i; 177 178 ice = devm_of_qcom_ice_get(dev); 179 if (ice == ERR_PTR(-EOPNOTSUPP)) { 180 dev_warn(dev, "Disabling inline encryption support\n"); 181 ice = NULL; 182 } 183 184 if (IS_ERR_OR_NULL(ice)) 185 return PTR_ERR_OR_ZERO(ice); 186 187 host->ice = ice; 188 189 /* Initialize the blk_crypto_profile */ 190 191 caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP)); 192 193 /* The number of keyslots supported is (CFGC+1) */ 194 err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1); 195 if (err) 196 return err; 197 198 profile->ll_ops = ufs_qcom_crypto_ops; 199 profile->max_dun_bytes_supported = 8; 200 profile->key_types_supported = qcom_ice_get_supported_key_type(ice); 201 profile->dev = dev; 202 203 /* 204 * Currently this driver only supports AES-256-XTS. All known versions 205 * of ICE support it, but to be safe make sure it is really declared in 206 * the crypto capability registers. The crypto capability registers 207 * also give the supported data unit size(s). 208 */ 209 for (i = 0; i < caps.num_crypto_cap; i++) { 210 cap.reg_val = cpu_to_le32(ufshcd_readl(hba, 211 REG_UFS_CRYPTOCAP + 212 i * sizeof(__le32))); 213 if (cap.algorithm_id == UFS_CRYPTO_ALG_AES_XTS && 214 cap.key_size == UFS_CRYPTO_KEY_SIZE_256) 215 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |= 216 cap.sdus_mask * 512; 217 } 218 219 hba->caps |= UFSHCD_CAP_CRYPTO; 220 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE; 221 return 0; 222 } 223 224 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 225 { 226 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 227 return qcom_ice_resume(host->ice); 228 229 return 0; 230 } 231 232 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 233 { 234 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 235 return qcom_ice_suspend(host->ice); 236 237 return 0; 238 } 239 240 static int ufs_qcom_ice_keyslot_program(struct blk_crypto_profile *profile, 241 const struct blk_crypto_key *key, 242 unsigned int slot) 243 { 244 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 245 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 246 int err; 247 248 ufshcd_hold(hba); 249 err = qcom_ice_program_key(host->ice, slot, key); 250 ufshcd_release(hba); 251 return err; 252 } 253 254 static int ufs_qcom_ice_keyslot_evict(struct blk_crypto_profile *profile, 255 const struct blk_crypto_key *key, 256 unsigned int slot) 257 { 258 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 259 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 260 int err; 261 262 ufshcd_hold(hba); 263 err = qcom_ice_evict_key(host->ice, slot); 264 ufshcd_release(hba); 265 return err; 266 } 267 268 static int ufs_qcom_ice_derive_sw_secret(struct blk_crypto_profile *profile, 269 const u8 *eph_key, size_t eph_key_size, 270 u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE]) 271 { 272 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 273 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 274 275 return qcom_ice_derive_sw_secret(host->ice, eph_key, eph_key_size, 276 sw_secret); 277 } 278 279 static int ufs_qcom_ice_import_key(struct blk_crypto_profile *profile, 280 const u8 *raw_key, size_t raw_key_size, 281 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 282 { 283 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 284 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 285 286 return qcom_ice_import_key(host->ice, raw_key, raw_key_size, lt_key); 287 } 288 289 static int ufs_qcom_ice_generate_key(struct blk_crypto_profile *profile, 290 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 291 { 292 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 293 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 294 295 return qcom_ice_generate_key(host->ice, lt_key); 296 } 297 298 static int ufs_qcom_ice_prepare_key(struct blk_crypto_profile *profile, 299 const u8 *lt_key, size_t lt_key_size, 300 u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 301 { 302 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 303 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 304 305 return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key); 306 } 307 308 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = { 309 .keyslot_program = ufs_qcom_ice_keyslot_program, 310 .keyslot_evict = ufs_qcom_ice_keyslot_evict, 311 .derive_sw_secret = ufs_qcom_ice_derive_sw_secret, 312 .import_key = ufs_qcom_ice_import_key, 313 .generate_key = ufs_qcom_ice_generate_key, 314 .prepare_key = ufs_qcom_ice_prepare_key, 315 }; 316 317 #else 318 319 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 320 { 321 } 322 323 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 324 { 325 return 0; 326 } 327 328 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 329 { 330 return 0; 331 } 332 333 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 334 { 335 return 0; 336 } 337 338 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) 339 { 340 } 341 342 #endif 343 344 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 345 { 346 if (!host->is_lane_clks_enabled) 347 return; 348 349 clk_bulk_disable_unprepare(host->num_clks, host->clks); 350 351 host->is_lane_clks_enabled = false; 352 } 353 354 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 355 { 356 int err; 357 358 err = clk_bulk_prepare_enable(host->num_clks, host->clks); 359 if (err) 360 return err; 361 362 host->is_lane_clks_enabled = true; 363 364 return 0; 365 } 366 367 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 368 { 369 int err; 370 struct device *dev = host->hba->dev; 371 372 if (has_acpi_companion(dev)) 373 return 0; 374 375 err = devm_clk_bulk_get_all(dev, &host->clks); 376 if (err <= 0) 377 return err; 378 379 host->num_clks = err; 380 381 return 0; 382 } 383 384 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 385 { 386 int err; 387 u32 tx_fsm_val; 388 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 389 390 do { 391 err = ufshcd_dme_get(hba, 392 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 393 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 394 &tx_fsm_val); 395 if (err || tx_fsm_val == TX_FSM_HIBERN8) 396 break; 397 398 /* sleep for max. 200us */ 399 usleep_range(100, 200); 400 } while (time_before(jiffies, timeout)); 401 402 /* 403 * we might have scheduled out for long during polling so 404 * check the state again. 405 */ 406 if (time_after(jiffies, timeout)) 407 err = ufshcd_dme_get(hba, 408 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 409 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 410 &tx_fsm_val); 411 412 if (err) { 413 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 414 __func__, err); 415 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 416 err = tx_fsm_val; 417 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 418 __func__, err); 419 } 420 421 return err; 422 } 423 424 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 425 { 426 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); 427 428 if (host->hw_ver.major >= 0x05) 429 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 430 } 431 432 /* 433 * ufs_qcom_host_reset - reset host controller and PHY 434 */ 435 static int ufs_qcom_host_reset(struct ufs_hba *hba) 436 { 437 int ret; 438 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 439 bool reenable_intr; 440 441 if (!host->core_reset) 442 return 0; 443 444 reenable_intr = hba->is_irq_enabled; 445 ufshcd_disable_irq(hba); 446 447 ret = reset_control_assert(host->core_reset); 448 if (ret) { 449 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 450 __func__, ret); 451 return ret; 452 } 453 454 /* 455 * The hardware requirement for delay between assert/deassert 456 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 457 * ~125us (4/32768). To be on the safe side add 200us delay. 458 */ 459 usleep_range(200, 210); 460 461 ret = reset_control_deassert(host->core_reset); 462 if (ret) { 463 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 464 __func__, ret); 465 return ret; 466 } 467 468 usleep_range(1000, 1100); 469 470 if (reenable_intr) 471 ufshcd_enable_irq(hba); 472 473 return 0; 474 } 475 476 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 477 { 478 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 479 480 if (host->hw_ver.major >= 0x4) 481 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 482 483 /* Default is HS-G3 */ 484 return UFS_HS_G3; 485 } 486 487 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 488 { 489 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 490 struct ufs_host_params *host_params = &host->host_params; 491 struct phy *phy = host->generic_phy; 492 enum phy_mode mode; 493 int ret; 494 495 /* 496 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. 497 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, 498 * so that the subsequent power mode change shall stick to Rate-A. 499 */ 500 if (host->hw_ver.major == 0x5 && host->phy_gear == UFS_HS_G5) 501 host_params->hs_rate = PA_HS_MODE_A; 502 503 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; 504 505 /* Reset UFS Host Controller and PHY */ 506 ret = ufs_qcom_host_reset(hba); 507 if (ret) 508 return ret; 509 510 if (phy->power_count) 511 phy_power_off(phy); 512 513 514 /* phy initialization - calibrate the phy */ 515 ret = phy_init(phy); 516 if (ret) { 517 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 518 __func__, ret); 519 return ret; 520 } 521 522 ret = phy_set_mode_ext(phy, mode, host->phy_gear); 523 if (ret) 524 goto out_disable_phy; 525 526 /* power on phy - start serdes and phy's power and clocks */ 527 ret = phy_power_on(phy); 528 if (ret) { 529 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 530 __func__, ret); 531 goto out_disable_phy; 532 } 533 534 ret = phy_calibrate(phy); 535 if (ret) { 536 dev_err(hba->dev, "Failed to calibrate PHY: %d\n", ret); 537 goto out_disable_phy; 538 } 539 540 ufs_qcom_select_unipro_mode(host); 541 542 return 0; 543 544 out_disable_phy: 545 phy_exit(phy); 546 547 return ret; 548 } 549 550 /* 551 * The UTP controller has a number of internal clock gating cells (CGCs). 552 * Internal hardware sub-modules within the UTP controller control the CGCs. 553 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 554 * in a specific operation, UTP controller CGCs are by default disabled and 555 * this function enables them (after every UFS link startup) to save some power 556 * leakage. 557 */ 558 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 559 { 560 int err; 561 562 /* Enable UTP internal clock gating */ 563 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, 564 REG_UFS_CFG2); 565 566 /* Ensure that HW clock gating is enabled before next operations */ 567 ufshcd_readl(hba, REG_UFS_CFG2); 568 569 /* Enable Unipro internal clock gating */ 570 err = ufshcd_dme_rmw(hba, DL_VS_CLK_CFG_MASK, 571 DL_VS_CLK_CFG_MASK, DL_VS_CLK_CFG); 572 if (err) 573 goto out; 574 575 err = ufshcd_dme_rmw(hba, PA_VS_CLK_CFG_REG_MASK, 576 PA_VS_CLK_CFG_REG_MASK, PA_VS_CLK_CFG_REG); 577 if (err) 578 goto out; 579 580 err = ufshcd_dme_rmw(hba, DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN, 581 DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN, 582 DME_VS_CORE_CLK_CTRL); 583 out: 584 if (err) 585 dev_err(hba->dev, "hw clk gating enabled failed\n"); 586 } 587 588 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 589 enum ufs_notify_change_status status) 590 { 591 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 592 int err; 593 594 switch (status) { 595 case PRE_CHANGE: 596 err = ufs_qcom_power_up_sequence(hba); 597 if (err) 598 return err; 599 600 /* 601 * The PHY PLL output is the source of tx/rx lane symbol 602 * clocks, hence, enable the lane clocks only after PHY 603 * is initialized. 604 */ 605 err = ufs_qcom_enable_lane_clks(host); 606 break; 607 case POST_CHANGE: 608 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 609 err = ufs_qcom_check_hibern8(hba); 610 ufs_qcom_enable_hw_clk_gating(hba); 611 ufs_qcom_ice_enable(host); 612 ufs_qcom_config_ice_allocator(host); 613 break; 614 default: 615 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 616 err = -EINVAL; 617 break; 618 } 619 return err; 620 } 621 622 /** 623 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers 624 * 625 * @hba: host controller instance 626 * @is_pre_scale_up: flag to check if pre scale up condition. 627 * @freq: target opp freq 628 * Return: zero for success and non-zero in case of a failure. 629 */ 630 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsigned long freq) 631 { 632 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 633 struct ufs_clk_info *clki; 634 unsigned long clk_freq = 0; 635 u32 core_clk_cycles_per_us; 636 637 /* 638 * UTP controller uses SYS1CLK_1US_REG register for Interrupt 639 * Aggregation logic. 640 * It is mandatory to write SYS1CLK_1US_REG register on UFS host 641 * controller V4.0.0 onwards. 642 */ 643 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) 644 return 0; 645 646 if (hba->use_pm_opp && freq != ULONG_MAX) { 647 clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk"); 648 if (clk_freq) 649 goto cfg_timers; 650 } 651 652 list_for_each_entry(clki, &hba->clk_list_head, list) { 653 if (!strcmp(clki->name, "core_clk")) { 654 if (freq == ULONG_MAX) { 655 clk_freq = clki->max_freq; 656 break; 657 } 658 659 if (is_pre_scale_up) 660 clk_freq = clki->max_freq; 661 else 662 clk_freq = clk_get_rate(clki->clk); 663 break; 664 } 665 666 } 667 668 cfg_timers: 669 /* If frequency is smaller than 1MHz, set to 1MHz */ 670 if (clk_freq < DEFAULT_CLK_RATE_HZ) 671 clk_freq = DEFAULT_CLK_RATE_HZ; 672 673 core_clk_cycles_per_us = clk_freq / USEC_PER_SEC; 674 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 675 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 676 /* 677 * make sure above write gets applied before we return from 678 * this function. 679 */ 680 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US); 681 } 682 683 return 0; 684 } 685 686 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 687 enum ufs_notify_change_status status) 688 { 689 int err = 0; 690 691 switch (status) { 692 case PRE_CHANGE: 693 if (ufs_qcom_cfg_timers(hba, false, ULONG_MAX)) { 694 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 695 __func__); 696 return -EINVAL; 697 } 698 699 err = ufs_qcom_set_core_clk_ctrl(hba, true, ULONG_MAX); 700 if (err) 701 dev_err(hba->dev, "cfg core clk ctrl failed\n"); 702 /* 703 * Some UFS devices (and may be host) have issues if LCC is 704 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 705 * before link startup which will make sure that both host 706 * and device TX LCC are disabled once link startup is 707 * completed. 708 */ 709 err = ufshcd_disable_host_tx_lcc(hba); 710 711 break; 712 default: 713 break; 714 } 715 716 return err; 717 } 718 719 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 720 { 721 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 722 723 /* reset gpio is optional */ 724 if (!host->device_reset) 725 return; 726 727 gpiod_set_value_cansleep(host->device_reset, asserted); 728 } 729 730 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 731 enum ufs_notify_change_status status) 732 { 733 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 734 735 if (status == PRE_CHANGE) 736 return 0; 737 738 if (!ufs_qcom_is_link_active(hba)) 739 ufs_qcom_disable_lane_clks(host); 740 741 742 /* reset the connected UFS device during power down */ 743 if (ufs_qcom_is_link_off(hba) && host->device_reset) 744 ufs_qcom_device_reset_ctrl(hba, true); 745 746 return ufs_qcom_ice_suspend(host); 747 } 748 749 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 750 { 751 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 752 int err; 753 u32 reg_val; 754 755 err = ufs_qcom_enable_lane_clks(host); 756 if (err) 757 return err; 758 759 if ((!ufs_qcom_is_link_active(hba)) && 760 host->hw_ver.major == 5 && 761 host->hw_ver.minor == 0 && 762 host->hw_ver.step == 0) { 763 ufshcd_writel(hba, UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW, UFS_MEM_ICE_CFG); 764 reg_val = ufshcd_readl(hba, UFS_MEM_ICE_CFG); 765 reg_val &= ~(UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW); 766 /* 767 * HW documentation doesn't recommend any delay between the 768 * reset set and clear. But we are enforcing an arbitrary delay 769 * to give flops enough time to settle in. 770 */ 771 usleep_range(50, 100); 772 ufshcd_writel(hba, reg_val, UFS_MEM_ICE_CFG); 773 ufshcd_readl(hba, UFS_MEM_ICE_CFG); 774 } 775 776 return ufs_qcom_ice_resume(host); 777 } 778 779 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 780 { 781 if (host->dev_ref_clk_ctrl_mmio && 782 (enable ^ host->is_dev_ref_clk_enabled)) { 783 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 784 785 if (enable) 786 temp |= host->dev_ref_clk_en_mask; 787 else 788 temp &= ~host->dev_ref_clk_en_mask; 789 790 /* 791 * If we are here to disable this clock it might be immediately 792 * after entering into hibern8 in which case we need to make 793 * sure that device ref_clk is active for specific time after 794 * hibern8 enter. 795 */ 796 if (!enable) { 797 unsigned long gating_wait; 798 799 gating_wait = host->hba->dev_info.clk_gating_wait_us; 800 if (!gating_wait) { 801 udelay(1); 802 } else { 803 /* 804 * bRefClkGatingWaitTime defines the minimum 805 * time for which the reference clock is 806 * required by device during transition from 807 * HS-MODE to LS-MODE or HIBERN8 state. Give it 808 * more delay to be on the safe side. 809 */ 810 gating_wait += 10; 811 usleep_range(gating_wait, gating_wait + 10); 812 } 813 } 814 815 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 816 817 /* 818 * Make sure the write to ref_clk reaches the destination and 819 * not stored in a Write Buffer (WB). 820 */ 821 readl(host->dev_ref_clk_ctrl_mmio); 822 823 /* 824 * If we call hibern8 exit after this, we need to make sure that 825 * device ref_clk is stable for at least 1us before the hibern8 826 * exit command. 827 */ 828 if (enable) 829 udelay(1); 830 831 host->is_dev_ref_clk_enabled = enable; 832 } 833 } 834 835 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 836 { 837 struct device *dev = host->hba->dev; 838 int ret; 839 840 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 841 if (ret < 0) { 842 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 843 return ret; 844 } 845 846 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 847 if (ret < 0) { 848 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 849 return ret; 850 } 851 852 return 0; 853 } 854 855 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 856 { 857 struct ufs_pa_layer_attr *p = &host->dev_req_params; 858 int gear = max_t(u32, p->gear_rx, p->gear_tx); 859 int lane = max_t(u32, p->lane_rx, p->lane_tx); 860 861 if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR, 862 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n", 863 gear, QCOM_UFS_MAX_GEAR)) 864 gear = QCOM_UFS_MAX_GEAR; 865 866 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE, 867 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n", 868 lane, QCOM_UFS_MAX_LANE)) 869 lane = QCOM_UFS_MAX_LANE; 870 871 if (ufshcd_is_hs_mode(p)) { 872 if (p->hs_rate == PA_HS_MODE_B) 873 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 874 else 875 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 876 } else { 877 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 878 } 879 } 880 881 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 882 { 883 struct __ufs_qcom_bw_table bw_table; 884 885 bw_table = ufs_qcom_get_bw_table(host); 886 887 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 888 } 889 890 static void ufs_qcom_set_tx_hs_equalizer(struct ufs_hba *hba, u32 gear, u32 tx_lanes) 891 { 892 u32 equalizer_val; 893 int ret, i; 894 895 /* Determine the equalizer value based on the gear */ 896 equalizer_val = (gear == 5) ? DEEMPHASIS_3_5_dB : NO_DEEMPHASIS; 897 898 for (i = 0; i < tx_lanes; i++) { 899 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HS_EQUALIZER, i), 900 equalizer_val); 901 if (ret) 902 dev_err(hba->dev, "%s: failed equalizer lane %d\n", 903 __func__, i); 904 } 905 } 906 907 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 908 enum ufs_notify_change_status status, 909 const struct ufs_pa_layer_attr *dev_max_params, 910 struct ufs_pa_layer_attr *dev_req_params) 911 { 912 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 913 struct ufs_host_params *host_params = &host->host_params; 914 int ret = 0; 915 916 if (!dev_req_params) { 917 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 918 return -EINVAL; 919 } 920 921 switch (status) { 922 case PRE_CHANGE: 923 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); 924 if (ret) { 925 dev_err(hba->dev, "%s: failed to determine capabilities\n", 926 __func__); 927 return ret; 928 } 929 930 /* 931 * During UFS driver probe, always update the PHY gear to match the negotiated 932 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled, 933 * the second init can program the optimal PHY settings. This allows one to start 934 * the first init with either the minimum or the maximum support gear. 935 */ 936 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { 937 /* 938 * Skip REINIT if the negotiated gear matches with the 939 * initial phy_gear. Otherwise, update the phy_gear to 940 * program the optimal gear setting during REINIT. 941 */ 942 if (host->phy_gear == dev_req_params->gear_tx) 943 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 944 else 945 host->phy_gear = dev_req_params->gear_tx; 946 } 947 948 /* enable the device ref clock before changing to HS mode */ 949 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 950 ufshcd_is_hs_mode(dev_req_params)) 951 ufs_qcom_dev_ref_clk_ctrl(host, true); 952 953 if (host->hw_ver.major >= 0x4) { 954 ufshcd_dme_configure_adapt(hba, 955 dev_req_params->gear_tx, 956 PA_INITIAL_ADAPT); 957 } 958 959 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING) 960 ufs_qcom_set_tx_hs_equalizer(hba, 961 dev_req_params->gear_tx, dev_req_params->lane_tx); 962 963 break; 964 case POST_CHANGE: 965 /* cache the power mode parameters to use internally */ 966 memcpy(&host->dev_req_params, 967 dev_req_params, sizeof(*dev_req_params)); 968 969 ufs_qcom_icc_update_bw(host); 970 971 /* disable the device ref clock if entered PWM mode */ 972 if (ufshcd_is_hs_mode(&hba->pwr_info) && 973 !ufshcd_is_hs_mode(dev_req_params)) 974 ufs_qcom_dev_ref_clk_ctrl(host, false); 975 break; 976 default: 977 ret = -EINVAL; 978 break; 979 } 980 981 return ret; 982 } 983 984 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 985 { 986 int err; 987 u32 pa_vs_config_reg1; 988 989 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 990 &pa_vs_config_reg1); 991 if (err) 992 return err; 993 994 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 995 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 996 (pa_vs_config_reg1 | (1 << 12))); 997 } 998 999 static void ufs_qcom_override_pa_tx_hsg1_sync_len(struct ufs_hba *hba) 1000 { 1001 int err; 1002 1003 err = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TX_HSG1_SYNC_LENGTH), 1004 PA_TX_HSG1_SYNC_LENGTH_VAL); 1005 if (err) 1006 dev_err(hba->dev, "Failed (%d) set PA_TX_HSG1_SYNC_LENGTH\n", err); 1007 } 1008 1009 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 1010 { 1011 int err = 0; 1012 1013 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 1014 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 1015 1016 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH) 1017 ufs_qcom_override_pa_tx_hsg1_sync_len(hba); 1018 1019 return err; 1020 } 1021 1022 /* UFS device-specific quirks */ 1023 static struct ufs_dev_quirk ufs_qcom_dev_fixups[] = { 1024 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 1025 .model = UFS_ANY_MODEL, 1026 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 1027 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 1028 .model = UFS_ANY_MODEL, 1029 .quirk = UFS_DEVICE_QUIRK_DELAY_AFTER_LPM }, 1030 { .wmanufacturerid = UFS_VENDOR_WDC, 1031 .model = UFS_ANY_MODEL, 1032 .quirk = UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE }, 1033 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 1034 .model = UFS_ANY_MODEL, 1035 .quirk = UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH | 1036 UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING }, 1037 {} 1038 }; 1039 1040 static void ufs_qcom_fixup_dev_quirks(struct ufs_hba *hba) 1041 { 1042 ufshcd_fixup_dev_quirks(hba, ufs_qcom_dev_fixups); 1043 } 1044 1045 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 1046 { 1047 return ufshci_version(2, 0); 1048 } 1049 1050 /** 1051 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 1052 * @hba: host controller instance 1053 * 1054 * QCOM UFS host controller might have some non standard behaviours (quirks) 1055 * than what is specified by UFSHCI specification. Advertise all such 1056 * quirks to standard UFS host controller driver so standard takes them into 1057 * account. 1058 */ 1059 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 1060 { 1061 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); 1062 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1063 1064 if (host->hw_ver.major == 0x2) 1065 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 1066 1067 if (host->hw_ver.major > 0x3) 1068 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1069 1070 if (drvdata && drvdata->quirks) 1071 hba->quirks |= drvdata->quirks; 1072 } 1073 1074 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) 1075 { 1076 struct ufs_host_params *host_params = &host->host_params; 1077 u32 val, dev_major; 1078 1079 /* 1080 * Default to powering up the PHY to the max gear possible, which is 1081 * backwards compatible with lower gears but not optimal from 1082 * a power usage point of view. After device negotiation, if the 1083 * gear is lower a reinit will be performed to program the PHY 1084 * to the ideal gear for this combo of controller and device. 1085 */ 1086 host->phy_gear = host_params->hs_tx_gear; 1087 1088 if (host->hw_ver.major < 0x4) { 1089 /* 1090 * These controllers only have one PHY init sequence, 1091 * let's power up the PHY using that (the minimum supported 1092 * gear, UFS_HS_G2). 1093 */ 1094 host->phy_gear = UFS_HS_G2; 1095 } else if (host->hw_ver.major >= 0x5) { 1096 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); 1097 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val); 1098 1099 /* 1100 * Since the UFS device version is populated, let's remove the 1101 * REINIT quirk as the negotiated gear won't change during boot. 1102 * So there is no need to do reinit. 1103 */ 1104 if (dev_major != 0x0) 1105 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1106 1107 /* 1108 * For UFS 3.1 device and older, power up the PHY using HS-G4 1109 * PHY gear to save power. 1110 */ 1111 if (dev_major > 0x0 && dev_major < 0x4) 1112 host->phy_gear = UFS_HS_G4; 1113 } 1114 } 1115 1116 static void ufs_qcom_parse_gear_limits(struct ufs_hba *hba) 1117 { 1118 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1119 struct ufs_host_params *host_params = &host->host_params; 1120 u32 hs_gear_old = host_params->hs_tx_gear; 1121 1122 ufshcd_parse_gear_limits(hba, host_params); 1123 if (host_params->hs_tx_gear != hs_gear_old) { 1124 host->phy_gear = host_params->hs_tx_gear; 1125 } 1126 } 1127 1128 static void ufs_qcom_set_host_params(struct ufs_hba *hba) 1129 { 1130 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1131 struct ufs_host_params *host_params = &host->host_params; 1132 1133 ufshcd_init_host_params(host_params); 1134 1135 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 1136 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); 1137 } 1138 1139 static void ufs_qcom_set_host_caps(struct ufs_hba *hba) 1140 { 1141 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1142 1143 if (host->hw_ver.major >= 0x5) 1144 host->caps |= UFS_QCOM_CAP_ICE_CONFIG; 1145 } 1146 1147 static void ufs_qcom_set_caps(struct ufs_hba *hba) 1148 { 1149 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1150 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 1151 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1152 hba->caps |= UFSHCD_CAP_WB_EN; 1153 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 1154 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 1155 1156 ufs_qcom_set_host_caps(hba); 1157 } 1158 1159 /** 1160 * ufs_qcom_setup_clocks - enables/disable clocks 1161 * @hba: host controller instance 1162 * @on: If true, enable clocks else disable them. 1163 * @status: PRE_CHANGE or POST_CHANGE notify 1164 * 1165 * There are certain clocks which comes from the PHY so it needs 1166 * to be managed together along with controller clocks which also 1167 * provides a better power saving. Hence keep phy_power_off/on calls 1168 * in ufs_qcom_setup_clocks, so that PHY's regulators & clks can be 1169 * turned on/off along with UFS's clocks. 1170 * 1171 * Return: 0 on success, non-zero on failure. 1172 */ 1173 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 1174 enum ufs_notify_change_status status) 1175 { 1176 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1177 struct phy *phy; 1178 int err; 1179 1180 /* 1181 * In case ufs_qcom_init() is not yet done, simply ignore. 1182 * This ufs_qcom_setup_clocks() shall be called from 1183 * ufs_qcom_init() after init is done. 1184 */ 1185 if (!host) 1186 return 0; 1187 1188 phy = host->generic_phy; 1189 1190 switch (status) { 1191 case PRE_CHANGE: 1192 if (on) { 1193 ufs_qcom_icc_update_bw(host); 1194 if (ufs_qcom_is_link_hibern8(hba)) { 1195 err = ufs_qcom_enable_lane_clks(host); 1196 if (err) { 1197 dev_err(hba->dev, "enable lane clks failed, ret=%d\n", err); 1198 return err; 1199 } 1200 } 1201 } else { 1202 if (!ufs_qcom_is_link_active(hba)) { 1203 /* disable device ref_clk */ 1204 ufs_qcom_dev_ref_clk_ctrl(host, false); 1205 } 1206 1207 err = phy_power_off(phy); 1208 if (err) { 1209 dev_err(hba->dev, "phy power off failed, ret=%d\n", err); 1210 return err; 1211 } 1212 } 1213 break; 1214 case POST_CHANGE: 1215 if (on) { 1216 err = phy_power_on(phy); 1217 if (err) { 1218 dev_err(hba->dev, "phy power on failed, ret = %d\n", err); 1219 return err; 1220 } 1221 1222 /* enable the device ref clock for HS mode*/ 1223 if (ufshcd_is_hs_mode(&hba->pwr_info)) 1224 ufs_qcom_dev_ref_clk_ctrl(host, true); 1225 } else { 1226 if (ufs_qcom_is_link_hibern8(hba)) 1227 ufs_qcom_disable_lane_clks(host); 1228 1229 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 1230 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 1231 } 1232 break; 1233 } 1234 1235 return 0; 1236 } 1237 1238 static int 1239 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 1240 { 1241 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1242 1243 ufs_qcom_assert_reset(host->hba); 1244 /* provide 1ms delay to let the reset pulse propagate. */ 1245 usleep_range(1000, 1100); 1246 return 0; 1247 } 1248 1249 static int 1250 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 1251 { 1252 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1253 1254 ufs_qcom_deassert_reset(host->hba); 1255 1256 /* 1257 * after reset deassertion, phy will need all ref clocks, 1258 * voltage, current to settle down before starting serdes. 1259 */ 1260 usleep_range(1000, 1100); 1261 return 0; 1262 } 1263 1264 static const struct reset_control_ops ufs_qcom_reset_ops = { 1265 .assert = ufs_qcom_reset_assert, 1266 .deassert = ufs_qcom_reset_deassert, 1267 }; 1268 1269 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 1270 { 1271 struct device *dev = host->hba->dev; 1272 int ret; 1273 1274 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 1275 if (IS_ERR(host->icc_ddr)) 1276 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 1277 "failed to acquire interconnect path\n"); 1278 1279 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1280 if (IS_ERR(host->icc_cpu)) 1281 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1282 "failed to acquire interconnect path\n"); 1283 1284 /* 1285 * Set Maximum bandwidth vote before initializing the UFS controller and 1286 * device. Ideally, a minimal interconnect vote would suffice for the 1287 * initialization, but a max vote would allow faster initialization. 1288 */ 1289 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1290 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1291 if (ret < 0) 1292 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1293 1294 return 0; 1295 } 1296 1297 /** 1298 * ufs_qcom_init - bind phy with controller 1299 * @hba: host controller instance 1300 * 1301 * Binds PHY with controller and powers up PHY enabling clocks 1302 * and regulators. 1303 * 1304 * Return: -EPROBE_DEFER if binding fails, returns negative error 1305 * on phy power up failure and returns zero on success. 1306 */ 1307 static int ufs_qcom_init(struct ufs_hba *hba) 1308 { 1309 int err; 1310 struct device *dev = hba->dev; 1311 struct ufs_qcom_host *host; 1312 struct ufs_clk_info *clki; 1313 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); 1314 1315 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1316 if (!host) 1317 return -ENOMEM; 1318 1319 /* Make a two way bind between the qcom host and the hba */ 1320 host->hba = hba; 1321 ufshcd_set_variant(hba, host); 1322 1323 /* Setup the optional reset control of HCI */ 1324 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1325 if (IS_ERR(host->core_reset)) { 1326 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1327 "Failed to get reset control\n"); 1328 goto out_variant_clear; 1329 } 1330 1331 /* Fire up the reset controller. Failure here is non-fatal. */ 1332 host->rcdev.of_node = dev->of_node; 1333 host->rcdev.ops = &ufs_qcom_reset_ops; 1334 host->rcdev.owner = dev->driver->owner; 1335 host->rcdev.nr_resets = 1; 1336 err = devm_reset_controller_register(dev, &host->rcdev); 1337 if (err) 1338 dev_warn(dev, "Failed to register reset controller\n"); 1339 1340 if (!has_acpi_companion(dev)) { 1341 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1342 if (IS_ERR(host->generic_phy)) { 1343 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1344 goto out_variant_clear; 1345 } 1346 } 1347 1348 err = ufs_qcom_icc_init(host); 1349 if (err) 1350 goto out_variant_clear; 1351 1352 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1353 GPIOD_OUT_HIGH); 1354 if (IS_ERR(host->device_reset)) { 1355 err = dev_err_probe(dev, PTR_ERR(host->device_reset), 1356 "Failed to acquire device reset gpio\n"); 1357 goto out_variant_clear; 1358 } 1359 1360 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1361 &host->hw_ver.minor, &host->hw_ver.step); 1362 1363 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1364 host->dev_ref_clk_en_mask = BIT(26); 1365 1366 list_for_each_entry(clki, &hba->clk_list_head, list) { 1367 if (!strcmp(clki->name, "core_clk_unipro")) 1368 clki->keep_link_active = true; 1369 } 1370 1371 err = ufs_qcom_init_lane_clks(host); 1372 if (err) 1373 goto out_variant_clear; 1374 1375 ufs_qcom_set_caps(hba); 1376 ufs_qcom_advertise_quirks(hba); 1377 ufs_qcom_set_host_params(hba); 1378 ufs_qcom_set_phy_gear(host); 1379 ufs_qcom_parse_gear_limits(hba); 1380 1381 err = ufs_qcom_ice_init(host); 1382 if (err) 1383 goto out_variant_clear; 1384 1385 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1386 1387 ufs_qcom_get_default_testbus_cfg(host); 1388 err = ufs_qcom_testbus_config(host); 1389 if (err) 1390 /* Failure is non-fatal */ 1391 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1392 __func__, err); 1393 1394 if (drvdata && drvdata->no_phy_retention) 1395 hba->spm_lvl = UFS_PM_LVL_5; 1396 1397 return 0; 1398 1399 out_variant_clear: 1400 ufshcd_set_variant(hba, NULL); 1401 1402 return err; 1403 } 1404 1405 static void ufs_qcom_exit(struct ufs_hba *hba) 1406 { 1407 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1408 1409 ufs_qcom_disable_lane_clks(host); 1410 phy_power_off(host->generic_phy); 1411 phy_exit(host->generic_phy); 1412 } 1413 1414 /** 1415 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles 1416 * 1417 * @hba: host controller instance 1418 * @cycles_in_1us: No of cycles in 1us to be configured 1419 * 1420 * Returns error if dme get/set configuration for 40ns fails 1421 * and returns zero on success. 1422 */ 1423 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, 1424 u32 cycles_in_1us) 1425 { 1426 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1427 u32 cycles_in_40ns; 1428 u32 reg; 1429 int err; 1430 1431 /* 1432 * UFS host controller V4.0.0 onwards needs to program 1433 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed 1434 * frequency of unipro core clk of UFS host controller. 1435 */ 1436 if (host->hw_ver.major < 4) 1437 return 0; 1438 1439 /* 1440 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not 1441 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will 1442 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware 1443 * specification expect to be 16. Hence use exact hardware spec 1444 * mandated value for cycles_in_40ns instead of calculating using 1445 * generic formulae. 1446 */ 1447 switch (cycles_in_1us) { 1448 case UNIPRO_CORE_CLK_FREQ_403_MHZ: 1449 cycles_in_40ns = 16; 1450 break; 1451 case UNIPRO_CORE_CLK_FREQ_300_MHZ: 1452 cycles_in_40ns = 12; 1453 break; 1454 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ: 1455 cycles_in_40ns = 8; 1456 break; 1457 case UNIPRO_CORE_CLK_FREQ_150_MHZ: 1458 cycles_in_40ns = 6; 1459 break; 1460 case UNIPRO_CORE_CLK_FREQ_100_MHZ: 1461 cycles_in_40ns = 4; 1462 break; 1463 case UNIPRO_CORE_CLK_FREQ_75_MHZ: 1464 cycles_in_40ns = 3; 1465 break; 1466 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ: 1467 cycles_in_40ns = 2; 1468 break; 1469 default: 1470 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", 1471 cycles_in_1us); 1472 return -EINVAL; 1473 } 1474 1475 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); 1476 if (err) 1477 return err; 1478 1479 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; 1480 reg |= cycles_in_40ns; 1481 1482 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); 1483 } 1484 1485 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq) 1486 { 1487 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1488 struct list_head *head = &hba->clk_list_head; 1489 struct ufs_clk_info *clki; 1490 u32 cycles_in_1us = 0; 1491 u32 core_clk_ctrl_reg; 1492 unsigned long clk_freq; 1493 int err; 1494 1495 if (hba->use_pm_opp && freq != ULONG_MAX) { 1496 clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro"); 1497 if (clk_freq) { 1498 cycles_in_1us = ceil(clk_freq, HZ_PER_MHZ); 1499 goto set_core_clk_ctrl; 1500 } 1501 } 1502 1503 list_for_each_entry(clki, head, list) { 1504 if (!IS_ERR_OR_NULL(clki->clk) && 1505 !strcmp(clki->name, "core_clk_unipro")) { 1506 if (!clki->max_freq) { 1507 cycles_in_1us = 150; /* default for backwards compatibility */ 1508 break; 1509 } 1510 1511 if (freq == ULONG_MAX) { 1512 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); 1513 break; 1514 } 1515 1516 if (is_scale_up) 1517 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); 1518 else 1519 cycles_in_1us = ceil(clk_get_rate(clki->clk), HZ_PER_MHZ); 1520 break; 1521 } 1522 } 1523 1524 set_core_clk_ctrl: 1525 err = ufshcd_dme_get(hba, 1526 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1527 &core_clk_ctrl_reg); 1528 if (err) 1529 return err; 1530 1531 /* Bit mask is different for UFS host controller V4.0.0 onwards */ 1532 if (host->hw_ver.major >= 4) { 1533 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us)) 1534 return -ERANGE; 1535 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4; 1536 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us); 1537 } else { 1538 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us)) 1539 return -ERANGE; 1540 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK; 1541 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); 1542 } 1543 1544 /* Clear CORE_CLK_DIV_EN */ 1545 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1546 1547 err = ufshcd_dme_set(hba, 1548 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1549 core_clk_ctrl_reg); 1550 if (err) 1551 return err; 1552 1553 /* Configure unipro core clk 40ns attribute */ 1554 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); 1555 } 1556 1557 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long freq) 1558 { 1559 int ret; 1560 1561 ret = ufs_qcom_cfg_timers(hba, true, freq); 1562 if (ret) { 1563 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); 1564 return ret; 1565 } 1566 /* set unipro core clock attributes and clear clock divider */ 1567 return ufs_qcom_set_core_clk_ctrl(hba, true, freq); 1568 } 1569 1570 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1571 { 1572 return 0; 1573 } 1574 1575 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1576 { 1577 int err; 1578 u32 core_clk_ctrl_reg; 1579 1580 err = ufshcd_dme_get(hba, 1581 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1582 &core_clk_ctrl_reg); 1583 1584 /* make sure CORE_CLK_DIV_EN is cleared */ 1585 if (!err && 1586 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1587 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1588 err = ufshcd_dme_set(hba, 1589 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1590 core_clk_ctrl_reg); 1591 } 1592 1593 return err; 1594 } 1595 1596 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq) 1597 { 1598 int ret; 1599 1600 ret = ufs_qcom_cfg_timers(hba, false, freq); 1601 if (ret) { 1602 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); 1603 return ret; 1604 } 1605 /* set unipro core clock attributes and clear clock divider */ 1606 return ufs_qcom_set_core_clk_ctrl(hba, false, freq); 1607 } 1608 1609 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, 1610 unsigned long target_freq, 1611 enum ufs_notify_change_status status) 1612 { 1613 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1614 int err; 1615 1616 /* check the host controller state before sending hibern8 cmd */ 1617 if (!ufshcd_is_hba_active(hba)) 1618 return 0; 1619 1620 if (status == PRE_CHANGE) { 1621 err = ufshcd_uic_hibern8_enter(hba); 1622 if (err) 1623 return err; 1624 if (scale_up) 1625 err = ufs_qcom_clk_scale_up_pre_change(hba, target_freq); 1626 else 1627 err = ufs_qcom_clk_scale_down_pre_change(hba); 1628 1629 if (err) { 1630 ufshcd_uic_hibern8_exit(hba); 1631 return err; 1632 } 1633 } else { 1634 if (scale_up) 1635 err = ufs_qcom_clk_scale_up_post_change(hba); 1636 else 1637 err = ufs_qcom_clk_scale_down_post_change(hba, target_freq); 1638 1639 1640 if (err) { 1641 ufshcd_uic_hibern8_exit(hba); 1642 return err; 1643 } 1644 1645 ufs_qcom_icc_update_bw(host); 1646 ufshcd_uic_hibern8_exit(hba); 1647 } 1648 1649 return 0; 1650 } 1651 1652 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1653 { 1654 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1655 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1656 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1657 } 1658 1659 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1660 { 1661 /* provide a legal default configuration */ 1662 host->testbus.select_major = TSTBUS_UNIPRO; 1663 host->testbus.select_minor = 37; 1664 } 1665 1666 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1667 { 1668 if (host->testbus.select_major >= TSTBUS_MAX) { 1669 dev_err(host->hba->dev, 1670 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1671 __func__, host->testbus.select_major); 1672 return false; 1673 } 1674 1675 return true; 1676 } 1677 1678 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1679 { 1680 int reg; 1681 int offset; 1682 u32 mask = TEST_BUS_SUB_SEL_MASK; 1683 1684 if (!host) 1685 return -EINVAL; 1686 1687 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1688 return -EPERM; 1689 1690 switch (host->testbus.select_major) { 1691 case TSTBUS_UAWM: 1692 reg = UFS_TEST_BUS_CTRL_0; 1693 offset = 24; 1694 break; 1695 case TSTBUS_UARM: 1696 reg = UFS_TEST_BUS_CTRL_0; 1697 offset = 16; 1698 break; 1699 case TSTBUS_TXUC: 1700 reg = UFS_TEST_BUS_CTRL_0; 1701 offset = 8; 1702 break; 1703 case TSTBUS_RXUC: 1704 reg = UFS_TEST_BUS_CTRL_0; 1705 offset = 0; 1706 break; 1707 case TSTBUS_DFC: 1708 reg = UFS_TEST_BUS_CTRL_1; 1709 offset = 24; 1710 break; 1711 case TSTBUS_TRLUT: 1712 reg = UFS_TEST_BUS_CTRL_1; 1713 offset = 16; 1714 break; 1715 case TSTBUS_TMRLUT: 1716 reg = UFS_TEST_BUS_CTRL_1; 1717 offset = 8; 1718 break; 1719 case TSTBUS_OCSC: 1720 reg = UFS_TEST_BUS_CTRL_1; 1721 offset = 0; 1722 break; 1723 case TSTBUS_WRAPPER: 1724 reg = UFS_TEST_BUS_CTRL_2; 1725 offset = 16; 1726 break; 1727 case TSTBUS_COMBINED: 1728 reg = UFS_TEST_BUS_CTRL_2; 1729 offset = 8; 1730 break; 1731 case TSTBUS_UTP_HCI: 1732 reg = UFS_TEST_BUS_CTRL_2; 1733 offset = 0; 1734 break; 1735 case TSTBUS_UNIPRO: 1736 reg = UFS_UNIPRO_CFG; 1737 offset = 20; 1738 mask = 0xFFF; 1739 break; 1740 /* 1741 * No need for a default case, since 1742 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 1743 * is legal 1744 */ 1745 } 1746 mask <<= offset; 1747 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 1748 (u32)host->testbus.select_major << 19, 1749 REG_UFS_CFG1); 1750 ufshcd_rmwl(host->hba, mask, 1751 (u32)host->testbus.select_minor << offset, 1752 reg); 1753 ufs_qcom_enable_test_bus(host); 1754 1755 return 0; 1756 } 1757 1758 static void ufs_qcom_dump_testbus(struct ufs_hba *hba) 1759 { 1760 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1761 int i, j, nminor = 0, testbus_len = 0; 1762 u32 *testbus __free(kfree) = NULL; 1763 char *prefix; 1764 1765 testbus = kmalloc_array(256, sizeof(u32), GFP_KERNEL); 1766 if (!testbus) 1767 return; 1768 1769 for (j = 0; j < TSTBUS_MAX; j++) { 1770 nminor = testbus_info[j].nminor; 1771 prefix = testbus_info[j].prefix; 1772 host->testbus.select_major = j; 1773 testbus_len = nminor * sizeof(u32); 1774 for (i = 0; i < nminor; i++) { 1775 host->testbus.select_minor = i; 1776 ufs_qcom_testbus_config(host); 1777 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS); 1778 } 1779 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 1780 16, 4, testbus, testbus_len, false); 1781 } 1782 } 1783 1784 static int ufs_qcom_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1785 const char *prefix, void __iomem *base) 1786 { 1787 u32 *regs __free(kfree) = NULL; 1788 size_t pos; 1789 1790 if (offset % 4 != 0 || len % 4 != 0) 1791 return -EINVAL; 1792 1793 regs = kzalloc(len, GFP_ATOMIC); 1794 if (!regs) 1795 return -ENOMEM; 1796 1797 for (pos = 0; pos < len; pos += 4) 1798 regs[pos / 4] = readl(base + offset + pos); 1799 1800 print_hex_dump(KERN_ERR, prefix, 1801 len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE, 1802 16, 4, regs, len, false); 1803 1804 return 0; 1805 } 1806 1807 static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba) 1808 { 1809 struct ufshcd_mcq_opr_info_t *opr = &hba->mcq_opr[0]; 1810 void __iomem *mcq_vs_base = hba->mcq_base + UFS_MEM_VS_BASE; 1811 1812 struct dump_info { 1813 void __iomem *base; 1814 size_t offset; 1815 size_t len; 1816 const char *prefix; 1817 }; 1818 1819 struct dump_info mcq_dumps[] = { 1820 {hba->mcq_base, 0x0, 256 * 4, "MCQ HCI-0 "}, 1821 {hba->mcq_base, 0x400, 256 * 4, "MCQ HCI-1 "}, 1822 {mcq_vs_base, 0x0, 5 * 4, "MCQ VS-0 "}, 1823 {opr->base, 0x0, 256 * 4, "MCQ SQD-0 "}, 1824 {opr->base, 0x400, 256 * 4, "MCQ SQD-1 "}, 1825 {opr->base, 0x800, 256 * 4, "MCQ SQD-2 "}, 1826 {opr->base, 0xc00, 256 * 4, "MCQ SQD-3 "}, 1827 {opr->base, 0x1000, 256 * 4, "MCQ SQD-4 "}, 1828 {opr->base, 0x1400, 256 * 4, "MCQ SQD-5 "}, 1829 {opr->base, 0x1800, 256 * 4, "MCQ SQD-6 "}, 1830 {opr->base, 0x1c00, 256 * 4, "MCQ SQD-7 "}, 1831 1832 }; 1833 1834 for (int i = 0; i < ARRAY_SIZE(mcq_dumps); i++) { 1835 ufs_qcom_dump_regs(hba, mcq_dumps[i].offset, mcq_dumps[i].len, 1836 mcq_dumps[i].prefix, mcq_dumps[i].base); 1837 cond_resched(); 1838 } 1839 } 1840 1841 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 1842 { 1843 u32 reg; 1844 struct ufs_qcom_host *host; 1845 1846 host = ufshcd_get_variant(hba); 1847 1848 dev_err(hba->dev, "HW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_ENTER_CNT)); 1849 dev_err(hba->dev, "HW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_EXIT_CNT)); 1850 1851 dev_err(hba->dev, "SW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_ENTER_CNT)); 1852 dev_err(hba->dev, "SW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_EXIT_CNT)); 1853 1854 dev_err(hba->dev, "SW_AFTER_HW_H8_ENTER_CNT=%d\n", 1855 ufshcd_readl(hba, REG_UFS_SW_AFTER_HW_H8_ENTER_CNT)); 1856 1857 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 1858 "HCI Vendor Specific Registers "); 1859 1860 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 1861 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 1862 1863 reg = ufshcd_readl(hba, REG_UFS_CFG1); 1864 reg |= UTP_DBG_RAMS_EN; 1865 ufshcd_writel(hba, reg, REG_UFS_CFG1); 1866 1867 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 1868 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 1869 1870 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 1871 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 1872 1873 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 1874 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 1875 1876 /* clear bit 17 - UTP_DBG_RAMS_EN */ 1877 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 1878 1879 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 1880 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 1881 1882 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 1883 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 1884 1885 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 1886 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 1887 1888 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 1889 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 1890 1891 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 1892 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 1893 1894 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 1895 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 1896 1897 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 1898 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 1899 1900 if (hba->mcq_enabled) { 1901 reg = ufs_qcom_get_debug_reg_offset(host, UFS_RD_REG_MCQ); 1902 ufshcd_dump_regs(hba, reg, 64 * 4, "HCI MCQ Debug Registers "); 1903 } 1904 1905 /* ensure below dumps occur only in task context due to blocking calls. */ 1906 if (in_task()) { 1907 /* Dump MCQ Host Vendor Specific Registers */ 1908 if (hba->mcq_enabled) 1909 ufs_qcom_dump_mcq_hci_regs(hba); 1910 1911 /* voluntarily yield the CPU as we are dumping too much data */ 1912 ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS "); 1913 cond_resched(); 1914 ufs_qcom_dump_testbus(hba); 1915 } 1916 } 1917 1918 /** 1919 * ufs_qcom_device_reset() - toggle the (optional) device reset line 1920 * @hba: per-adapter instance 1921 * 1922 * Toggles the (optional) reset line to reset the attached device. 1923 */ 1924 static int ufs_qcom_device_reset(struct ufs_hba *hba) 1925 { 1926 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1927 1928 /* reset gpio is optional */ 1929 if (!host->device_reset) 1930 return -EOPNOTSUPP; 1931 1932 /* 1933 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 1934 * be on the safe side. 1935 */ 1936 ufs_qcom_device_reset_ctrl(hba, true); 1937 usleep_range(10, 15); 1938 1939 ufs_qcom_device_reset_ctrl(hba, false); 1940 usleep_range(10, 15); 1941 1942 return 0; 1943 } 1944 1945 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1946 struct devfreq_dev_profile *p, 1947 struct devfreq_simple_ondemand_data *d) 1948 { 1949 p->polling_ms = 60; 1950 p->timer = DEVFREQ_TIMER_DELAYED; 1951 d->upthreshold = 70; 1952 d->downdifferential = 5; 1953 1954 hba->clk_scaling.suspend_on_no_request = true; 1955 } 1956 1957 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 1958 { 1959 struct platform_device *pdev = to_platform_device(hba->dev); 1960 struct resource *res; 1961 1962 /* Map the MCQ configuration region */ 1963 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mcq"); 1964 if (!res) { 1965 dev_err(hba->dev, "MCQ resource not found in device tree\n"); 1966 return -ENODEV; 1967 } 1968 1969 hba->mcq_base = devm_ioremap_resource(hba->dev, res); 1970 if (IS_ERR(hba->mcq_base)) { 1971 dev_err(hba->dev, "Failed to map MCQ region: %ld\n", 1972 PTR_ERR(hba->mcq_base)); 1973 return PTR_ERR(hba->mcq_base); 1974 } 1975 1976 return 0; 1977 } 1978 1979 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 1980 { 1981 struct ufshcd_mcq_opr_info_t *opr; 1982 int i; 1983 u32 doorbell_offsets[OPR_MAX]; 1984 1985 /* 1986 * Configure doorbell address offsets in MCQ configuration registers. 1987 * These values are offsets relative to mmio_base (UFS_HCI_BASE). 1988 * 1989 * Memory Layout: 1990 * - mmio_base = UFS_HCI_BASE 1991 * - mcq_base = MCQ_CONFIG_BASE = mmio_base + (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) 1992 * - Doorbell registers are at: mmio_base + (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) + 1993 * - UFS_QCOM_MCQ_SQD_OFFSET 1994 * - Which is also: mcq_base + UFS_QCOM_MCQ_SQD_OFFSET 1995 */ 1996 1997 doorbell_offsets[OPR_SQD] = UFS_QCOM_SQD_ADDR_OFFSET; 1998 doorbell_offsets[OPR_SQIS] = UFS_QCOM_SQIS_ADDR_OFFSET; 1999 doorbell_offsets[OPR_CQD] = UFS_QCOM_CQD_ADDR_OFFSET; 2000 doorbell_offsets[OPR_CQIS] = UFS_QCOM_CQIS_ADDR_OFFSET; 2001 2002 /* 2003 * Configure MCQ operation registers. 2004 * 2005 * The doorbell registers are physically located within the MCQ region: 2006 * - doorbell_physical_addr = mmio_base + doorbell_offset 2007 * - doorbell_physical_addr = mcq_base + (doorbell_offset - MCQ_CONFIG_OFFSET) 2008 */ 2009 for (i = 0; i < OPR_MAX; i++) { 2010 opr = &hba->mcq_opr[i]; 2011 opr->offset = doorbell_offsets[i]; /* Offset relative to mmio_base */ 2012 opr->stride = UFS_QCOM_MCQ_STRIDE; /* 256 bytes between queues */ 2013 2014 /* 2015 * Calculate the actual doorbell base address within MCQ region: 2016 * base = mcq_base + (doorbell_offset - MCQ_CONFIG_OFFSET) 2017 */ 2018 opr->base = hba->mcq_base + (opr->offset - UFS_QCOM_MCQ_CONFIG_OFFSET); 2019 } 2020 2021 return 0; 2022 } 2023 2024 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 2025 { 2026 /* Qualcomm HC supports up to 64 */ 2027 return MAX_SUPP_MAC; 2028 } 2029 2030 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 2031 unsigned long *ocqs) 2032 { 2033 /* Read from MCQ vendor-specific register in MCQ region */ 2034 *ocqs = readl(hba->mcq_base + UFS_MEM_CQIS_VS); 2035 2036 return 0; 2037 } 2038 2039 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 2040 { 2041 struct device *dev = msi_desc_to_dev(desc); 2042 struct ufs_hba *hba = dev_get_drvdata(dev); 2043 2044 ufshcd_mcq_config_esi(hba, msg); 2045 } 2046 2047 struct ufs_qcom_irq { 2048 unsigned int irq; 2049 unsigned int idx; 2050 struct ufs_hba *hba; 2051 }; 2052 2053 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 2054 { 2055 struct ufs_qcom_irq *qi = data; 2056 struct ufs_hba *hba = qi->hba; 2057 struct ufs_hw_queue *hwq = &hba->uhq[qi->idx]; 2058 2059 ufshcd_mcq_write_cqis(hba, 0x1, qi->idx); 2060 ufshcd_mcq_poll_cqe_lock(hba, hwq); 2061 2062 return IRQ_HANDLED; 2063 } 2064 2065 static int ufs_qcom_config_esi(struct ufs_hba *hba) 2066 { 2067 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2068 int nr_irqs, ret; 2069 2070 if (host->esi_enabled) 2071 return 0; 2072 2073 /* 2074 * 1. We only handle CQs as of now. 2075 * 2. Poll queues do not need ESI. 2076 */ 2077 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 2078 2079 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, 2080 ufs_qcom_write_msi_msg); 2081 if (ret) { 2082 dev_warn(hba->dev, "Platform MSI not supported or failed, continuing without ESI\n"); 2083 return ret; /* Continue without ESI */ 2084 } 2085 2086 struct ufs_qcom_irq *qi = devm_kcalloc(hba->dev, nr_irqs, sizeof(*qi), GFP_KERNEL); 2087 2088 if (!qi) { 2089 platform_device_msi_free_irqs_all(hba->dev); 2090 return -ENOMEM; 2091 } 2092 2093 for (int idx = 0; idx < nr_irqs; idx++) { 2094 qi[idx].irq = msi_get_virq(hba->dev, idx); 2095 qi[idx].idx = idx; 2096 qi[idx].hba = hba; 2097 2098 ret = devm_request_irq(hba->dev, qi[idx].irq, ufs_qcom_mcq_esi_handler, 2099 IRQF_SHARED, "qcom-mcq-esi", qi + idx); 2100 if (ret) { 2101 dev_err(hba->dev, "%s: Failed to request IRQ for %d, err = %d\n", 2102 __func__, qi[idx].irq, ret); 2103 /* Free previously allocated IRQs */ 2104 for (int j = 0; j < idx; j++) 2105 devm_free_irq(hba->dev, qi[j].irq, qi + j); 2106 platform_device_msi_free_irqs_all(hba->dev); 2107 devm_kfree(hba->dev, qi); 2108 return ret; 2109 } 2110 } 2111 2112 if (host->hw_ver.major >= 6) { 2113 ufshcd_rmwl(hba, ESI_VEC_MASK, FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), 2114 REG_UFS_CFG3); 2115 } 2116 ufshcd_mcq_enable_esi(hba); 2117 host->esi_enabled = true; 2118 return 0; 2119 } 2120 2121 static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba, 2122 unsigned long freq, char *name) 2123 { 2124 struct ufs_clk_info *clki; 2125 struct dev_pm_opp *opp; 2126 unsigned long clk_freq; 2127 int idx = 0; 2128 bool found = false; 2129 2130 opp = dev_pm_opp_find_freq_exact_indexed(hba->dev, freq, 0, true); 2131 if (IS_ERR(opp)) { 2132 dev_err(hba->dev, "Failed to find OPP for exact frequency %lu\n", freq); 2133 return 0; 2134 } 2135 2136 list_for_each_entry(clki, &hba->clk_list_head, list) { 2137 if (!strcmp(clki->name, name)) { 2138 found = true; 2139 break; 2140 } 2141 2142 idx++; 2143 } 2144 2145 if (!found) { 2146 dev_err(hba->dev, "Failed to find clock '%s' in clk list\n", name); 2147 dev_pm_opp_put(opp); 2148 return 0; 2149 } 2150 2151 clk_freq = dev_pm_opp_get_freq_indexed(opp, idx); 2152 2153 dev_pm_opp_put(opp); 2154 2155 return clk_freq; 2156 } 2157 2158 static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) 2159 { 2160 u32 gear = UFS_HS_DONT_CHANGE; 2161 unsigned long unipro_freq; 2162 2163 if (!hba->use_pm_opp) 2164 return gear; 2165 2166 unipro_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro"); 2167 switch (unipro_freq) { 2168 case 403000000: 2169 gear = UFS_HS_G5; 2170 break; 2171 case 300000000: 2172 gear = UFS_HS_G4; 2173 break; 2174 case 201500000: 2175 gear = UFS_HS_G3; 2176 break; 2177 case 150000000: 2178 case 100000000: 2179 gear = UFS_HS_G2; 2180 break; 2181 case 75000000: 2182 case 37500000: 2183 gear = UFS_HS_G1; 2184 break; 2185 default: 2186 dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq); 2187 return UFS_HS_DONT_CHANGE; 2188 } 2189 2190 return min_t(u32, gear, hba->max_pwr_info.info.gear_rx); 2191 } 2192 2193 /* 2194 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 2195 * 2196 * The variant operations configure the necessary controller and PHY 2197 * handshake during initialization. 2198 */ 2199 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 2200 .name = "qcom", 2201 .init = ufs_qcom_init, 2202 .exit = ufs_qcom_exit, 2203 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 2204 .clk_scale_notify = ufs_qcom_clk_scale_notify, 2205 .setup_clocks = ufs_qcom_setup_clocks, 2206 .hce_enable_notify = ufs_qcom_hce_enable_notify, 2207 .link_startup_notify = ufs_qcom_link_startup_notify, 2208 .pwr_change_notify = ufs_qcom_pwr_change_notify, 2209 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 2210 .fixup_dev_quirks = ufs_qcom_fixup_dev_quirks, 2211 .suspend = ufs_qcom_suspend, 2212 .resume = ufs_qcom_resume, 2213 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 2214 .device_reset = ufs_qcom_device_reset, 2215 .config_scaling_param = ufs_qcom_config_scaling_param, 2216 .mcq_config_resource = ufs_qcom_mcq_config_resource, 2217 .get_hba_mac = ufs_qcom_get_hba_mac, 2218 .op_runtime_config = ufs_qcom_op_runtime_config, 2219 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 2220 .config_esi = ufs_qcom_config_esi, 2221 .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, 2222 }; 2223 2224 /** 2225 * ufs_qcom_probe - probe routine of the driver 2226 * @pdev: pointer to Platform device handle 2227 * 2228 * Return: zero for success and non-zero for failure. 2229 */ 2230 static int ufs_qcom_probe(struct platform_device *pdev) 2231 { 2232 int err; 2233 struct device *dev = &pdev->dev; 2234 2235 /* Perform generic probe */ 2236 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); 2237 if (err) 2238 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 2239 2240 return 0; 2241 } 2242 2243 /** 2244 * ufs_qcom_remove - set driver_data of the device to NULL 2245 * @pdev: pointer to platform device handle 2246 * 2247 * Always returns 0 2248 */ 2249 static void ufs_qcom_remove(struct platform_device *pdev) 2250 { 2251 struct ufs_hba *hba = platform_get_drvdata(pdev); 2252 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2253 2254 ufshcd_pltfrm_remove(pdev); 2255 if (host->esi_enabled) 2256 platform_device_msi_free_irqs_all(hba->dev); 2257 } 2258 2259 static const struct ufs_qcom_drvdata ufs_qcom_sm8550_drvdata = { 2260 .quirks = UFSHCD_QUIRK_BROKEN_LSDBS_CAP, 2261 .no_phy_retention = true, 2262 }; 2263 2264 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 2265 { .compatible = "qcom,ufshc" }, 2266 { .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata }, 2267 { .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata }, 2268 {}, 2269 }; 2270 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 2271 2272 #ifdef CONFIG_ACPI 2273 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 2274 { "QCOM24A5" }, 2275 { }, 2276 }; 2277 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 2278 #endif 2279 2280 static const struct dev_pm_ops ufs_qcom_pm_ops = { 2281 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 2282 .prepare = ufshcd_suspend_prepare, 2283 .complete = ufshcd_resume_complete, 2284 #ifdef CONFIG_PM_SLEEP 2285 .suspend = ufshcd_system_suspend, 2286 .resume = ufshcd_system_resume, 2287 .freeze = ufshcd_system_freeze, 2288 .restore = ufshcd_system_restore, 2289 .thaw = ufshcd_system_thaw, 2290 #endif 2291 }; 2292 2293 static struct platform_driver ufs_qcom_pltform = { 2294 .probe = ufs_qcom_probe, 2295 .remove = ufs_qcom_remove, 2296 .driver = { 2297 .name = "ufshcd-qcom", 2298 .pm = &ufs_qcom_pm_ops, 2299 .of_match_table = of_match_ptr(ufs_qcom_of_match), 2300 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 2301 }, 2302 }; 2303 module_platform_driver(ufs_qcom_pltform); 2304 2305 MODULE_DESCRIPTION("Qualcomm UFS host controller driver"); 2306 MODULE_LICENSE("GPL v2"); 2307