1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/clk.h> 8 #include <linux/cleanup.h> 9 #include <linux/delay.h> 10 #include <linux/devfreq.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/interconnect.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/reset-controller.h> 18 #include <linux/time.h> 19 #include <linux/unaligned.h> 20 #include <linux/units.h> 21 22 #include <soc/qcom/ice.h> 23 24 #include <ufs/ufshcd.h> 25 #include <ufs/ufshci.h> 26 #include <ufs/ufs_quirks.h> 27 #include <ufs/unipro.h> 28 #include "ufshcd-pltfrm.h" 29 #include "ufs-qcom.h" 30 31 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 32 #define MCQ_QCFGPTR_UNIT 0x200 33 #define MCQ_SQATTR_OFFSET(c) \ 34 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 35 #define MCQ_QCFG_SIZE 0x40 36 37 /* De-emphasis for gear-5 */ 38 #define DEEMPHASIS_3_5_dB 0x04 39 #define NO_DEEMPHASIS 0x0 40 41 enum { 42 TSTBUS_UAWM, 43 TSTBUS_UARM, 44 TSTBUS_TXUC, 45 TSTBUS_RXUC, 46 TSTBUS_DFC, 47 TSTBUS_TRLUT, 48 TSTBUS_TMRLUT, 49 TSTBUS_OCSC, 50 TSTBUS_UTP_HCI, 51 TSTBUS_COMBINED, 52 TSTBUS_WRAPPER, 53 TSTBUS_UNIPRO, 54 TSTBUS_MAX, 55 }; 56 57 #define QCOM_UFS_MAX_GEAR 5 58 #define QCOM_UFS_MAX_LANE 2 59 60 enum { 61 MODE_MIN, 62 MODE_PWM, 63 MODE_HS_RA, 64 MODE_HS_RB, 65 MODE_MAX, 66 }; 67 68 static const struct __ufs_qcom_bw_table { 69 u32 mem_bw; 70 u32 cfg_bw; 71 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 72 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 73 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 74 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 75 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 76 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 77 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 }, 78 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 79 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 80 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 81 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 82 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 }, 83 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 84 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 85 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 86 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 87 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 88 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 89 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 90 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 91 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 92 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 93 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 94 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 95 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 96 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 97 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 98 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 99 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 100 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 101 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 102 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 103 [MODE_MAX][0][0] = { 7643136, 819200 }, 104 }; 105 106 static const struct { 107 int nminor; 108 char *prefix; 109 } testbus_info[TSTBUS_MAX] = { 110 [TSTBUS_UAWM] = {32, "TSTBUS_UAWM"}, 111 [TSTBUS_UARM] = {32, "TSTBUS_UARM"}, 112 [TSTBUS_TXUC] = {32, "TSTBUS_TXUC"}, 113 [TSTBUS_RXUC] = {32, "TSTBUS_RXUC"}, 114 [TSTBUS_DFC] = {32, "TSTBUS_DFC"}, 115 [TSTBUS_TRLUT] = {32, "TSTBUS_TRLUT"}, 116 [TSTBUS_TMRLUT] = {32, "TSTBUS_TMRLUT"}, 117 [TSTBUS_OCSC] = {32, "TSTBUS_OCSC"}, 118 [TSTBUS_UTP_HCI] = {32, "TSTBUS_UTP_HCI"}, 119 [TSTBUS_COMBINED] = {32, "TSTBUS_COMBINED"}, 120 [TSTBUS_WRAPPER] = {32, "TSTBUS_WRAPPER"}, 121 [TSTBUS_UNIPRO] = {256, "TSTBUS_UNIPRO"}, 122 }; 123 124 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 125 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq); 126 127 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 128 { 129 return container_of(rcd, struct ufs_qcom_host, rcdev); 130 } 131 132 #ifdef CONFIG_SCSI_UFS_CRYPTO 133 /** 134 * ufs_qcom_config_ice_allocator() - ICE core allocator configuration 135 * 136 * @host: pointer to qcom specific variant structure. 137 */ 138 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) 139 { 140 struct ufs_hba *hba = host->hba; 141 static const uint8_t val[4] = { NUM_RX_R1W0, NUM_TX_R0W1, NUM_RX_R1W1, NUM_TX_R1W1 }; 142 u32 config; 143 144 if (!(host->caps & UFS_QCOM_CAP_ICE_CONFIG) || 145 !(host->hba->caps & UFSHCD_CAP_CRYPTO)) 146 return; 147 148 config = get_unaligned_le32(val); 149 150 ufshcd_writel(hba, ICE_ALLOCATOR_TYPE, REG_UFS_MEM_ICE_CONFIG); 151 ufshcd_writel(hba, config, REG_UFS_MEM_ICE_NUM_CORE); 152 } 153 154 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 155 { 156 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 157 qcom_ice_enable(host->ice); 158 } 159 160 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops; /* forward decl */ 161 162 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 163 { 164 struct ufs_hba *hba = host->hba; 165 struct blk_crypto_profile *profile = &hba->crypto_profile; 166 struct device *dev = hba->dev; 167 struct qcom_ice *ice; 168 union ufs_crypto_capabilities caps; 169 union ufs_crypto_cap_entry cap; 170 int err; 171 int i; 172 173 ice = devm_of_qcom_ice_get(dev); 174 if (ice == ERR_PTR(-EOPNOTSUPP)) { 175 dev_warn(dev, "Disabling inline encryption support\n"); 176 ice = NULL; 177 } 178 179 if (IS_ERR_OR_NULL(ice)) 180 return PTR_ERR_OR_ZERO(ice); 181 182 host->ice = ice; 183 184 /* Initialize the blk_crypto_profile */ 185 186 caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP)); 187 188 /* The number of keyslots supported is (CFGC+1) */ 189 err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1); 190 if (err) 191 return err; 192 193 profile->ll_ops = ufs_qcom_crypto_ops; 194 profile->max_dun_bytes_supported = 8; 195 profile->key_types_supported = qcom_ice_get_supported_key_type(ice); 196 profile->dev = dev; 197 198 /* 199 * Currently this driver only supports AES-256-XTS. All known versions 200 * of ICE support it, but to be safe make sure it is really declared in 201 * the crypto capability registers. The crypto capability registers 202 * also give the supported data unit size(s). 203 */ 204 for (i = 0; i < caps.num_crypto_cap; i++) { 205 cap.reg_val = cpu_to_le32(ufshcd_readl(hba, 206 REG_UFS_CRYPTOCAP + 207 i * sizeof(__le32))); 208 if (cap.algorithm_id == UFS_CRYPTO_ALG_AES_XTS && 209 cap.key_size == UFS_CRYPTO_KEY_SIZE_256) 210 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |= 211 cap.sdus_mask * 512; 212 } 213 214 hba->caps |= UFSHCD_CAP_CRYPTO; 215 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE; 216 return 0; 217 } 218 219 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 220 { 221 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 222 return qcom_ice_resume(host->ice); 223 224 return 0; 225 } 226 227 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 228 { 229 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 230 return qcom_ice_suspend(host->ice); 231 232 return 0; 233 } 234 235 static int ufs_qcom_ice_keyslot_program(struct blk_crypto_profile *profile, 236 const struct blk_crypto_key *key, 237 unsigned int slot) 238 { 239 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 240 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 241 int err; 242 243 ufshcd_hold(hba); 244 err = qcom_ice_program_key(host->ice, slot, key); 245 ufshcd_release(hba); 246 return err; 247 } 248 249 static int ufs_qcom_ice_keyslot_evict(struct blk_crypto_profile *profile, 250 const struct blk_crypto_key *key, 251 unsigned int slot) 252 { 253 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 254 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 255 int err; 256 257 ufshcd_hold(hba); 258 err = qcom_ice_evict_key(host->ice, slot); 259 ufshcd_release(hba); 260 return err; 261 } 262 263 static int ufs_qcom_ice_derive_sw_secret(struct blk_crypto_profile *profile, 264 const u8 *eph_key, size_t eph_key_size, 265 u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE]) 266 { 267 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 268 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 269 270 return qcom_ice_derive_sw_secret(host->ice, eph_key, eph_key_size, 271 sw_secret); 272 } 273 274 static int ufs_qcom_ice_import_key(struct blk_crypto_profile *profile, 275 const u8 *raw_key, size_t raw_key_size, 276 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 277 { 278 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 279 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 280 281 return qcom_ice_import_key(host->ice, raw_key, raw_key_size, lt_key); 282 } 283 284 static int ufs_qcom_ice_generate_key(struct blk_crypto_profile *profile, 285 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 286 { 287 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 288 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 289 290 return qcom_ice_generate_key(host->ice, lt_key); 291 } 292 293 static int ufs_qcom_ice_prepare_key(struct blk_crypto_profile *profile, 294 const u8 *lt_key, size_t lt_key_size, 295 u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 296 { 297 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 298 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 299 300 return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key); 301 } 302 303 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = { 304 .keyslot_program = ufs_qcom_ice_keyslot_program, 305 .keyslot_evict = ufs_qcom_ice_keyslot_evict, 306 .derive_sw_secret = ufs_qcom_ice_derive_sw_secret, 307 .import_key = ufs_qcom_ice_import_key, 308 .generate_key = ufs_qcom_ice_generate_key, 309 .prepare_key = ufs_qcom_ice_prepare_key, 310 }; 311 312 #else 313 314 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 315 { 316 } 317 318 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 319 { 320 return 0; 321 } 322 323 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 324 { 325 return 0; 326 } 327 328 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 329 { 330 return 0; 331 } 332 333 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) 334 { 335 } 336 337 #endif 338 339 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 340 { 341 if (!host->is_lane_clks_enabled) 342 return; 343 344 clk_bulk_disable_unprepare(host->num_clks, host->clks); 345 346 host->is_lane_clks_enabled = false; 347 } 348 349 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 350 { 351 int err; 352 353 err = clk_bulk_prepare_enable(host->num_clks, host->clks); 354 if (err) 355 return err; 356 357 host->is_lane_clks_enabled = true; 358 359 return 0; 360 } 361 362 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 363 { 364 int err; 365 struct device *dev = host->hba->dev; 366 367 if (has_acpi_companion(dev)) 368 return 0; 369 370 err = devm_clk_bulk_get_all(dev, &host->clks); 371 if (err <= 0) 372 return err; 373 374 host->num_clks = err; 375 376 return 0; 377 } 378 379 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 380 { 381 int err; 382 u32 tx_fsm_val; 383 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 384 385 do { 386 err = ufshcd_dme_get(hba, 387 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 388 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 389 &tx_fsm_val); 390 if (err || tx_fsm_val == TX_FSM_HIBERN8) 391 break; 392 393 /* sleep for max. 200us */ 394 usleep_range(100, 200); 395 } while (time_before(jiffies, timeout)); 396 397 /* 398 * we might have scheduled out for long during polling so 399 * check the state again. 400 */ 401 if (time_after(jiffies, timeout)) 402 err = ufshcd_dme_get(hba, 403 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 404 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 405 &tx_fsm_val); 406 407 if (err) { 408 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 409 __func__, err); 410 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 411 err = tx_fsm_val; 412 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 413 __func__, err); 414 } 415 416 return err; 417 } 418 419 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 420 { 421 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); 422 423 if (host->hw_ver.major >= 0x05) 424 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 425 } 426 427 /* 428 * ufs_qcom_host_reset - reset host controller and PHY 429 */ 430 static int ufs_qcom_host_reset(struct ufs_hba *hba) 431 { 432 int ret; 433 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 434 bool reenable_intr; 435 436 if (!host->core_reset) 437 return 0; 438 439 reenable_intr = hba->is_irq_enabled; 440 ufshcd_disable_irq(hba); 441 442 ret = reset_control_assert(host->core_reset); 443 if (ret) { 444 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 445 __func__, ret); 446 return ret; 447 } 448 449 /* 450 * The hardware requirement for delay between assert/deassert 451 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 452 * ~125us (4/32768). To be on the safe side add 200us delay. 453 */ 454 usleep_range(200, 210); 455 456 ret = reset_control_deassert(host->core_reset); 457 if (ret) { 458 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 459 __func__, ret); 460 return ret; 461 } 462 463 usleep_range(1000, 1100); 464 465 if (reenable_intr) 466 ufshcd_enable_irq(hba); 467 468 return 0; 469 } 470 471 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 472 { 473 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 474 475 if (host->hw_ver.major >= 0x4) 476 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 477 478 /* Default is HS-G3 */ 479 return UFS_HS_G3; 480 } 481 482 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 483 { 484 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 485 struct ufs_host_params *host_params = &host->host_params; 486 struct phy *phy = host->generic_phy; 487 enum phy_mode mode; 488 int ret; 489 490 /* 491 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. 492 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, 493 * so that the subsequent power mode change shall stick to Rate-A. 494 */ 495 if (host->hw_ver.major == 0x5) { 496 if (host->phy_gear == UFS_HS_G5) 497 host_params->hs_rate = PA_HS_MODE_A; 498 else 499 host_params->hs_rate = PA_HS_MODE_B; 500 } 501 502 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; 503 504 /* Reset UFS Host Controller and PHY */ 505 ret = ufs_qcom_host_reset(hba); 506 if (ret) 507 return ret; 508 509 if (phy->power_count) { 510 phy_power_off(phy); 511 phy_exit(phy); 512 } 513 514 /* phy initialization - calibrate the phy */ 515 ret = phy_init(phy); 516 if (ret) { 517 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 518 __func__, ret); 519 return ret; 520 } 521 522 ret = phy_set_mode_ext(phy, mode, host->phy_gear); 523 if (ret) 524 goto out_disable_phy; 525 526 /* power on phy - start serdes and phy's power and clocks */ 527 ret = phy_power_on(phy); 528 if (ret) { 529 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 530 __func__, ret); 531 goto out_disable_phy; 532 } 533 534 ufs_qcom_select_unipro_mode(host); 535 536 return 0; 537 538 out_disable_phy: 539 phy_exit(phy); 540 541 return ret; 542 } 543 544 /* 545 * The UTP controller has a number of internal clock gating cells (CGCs). 546 * Internal hardware sub-modules within the UTP controller control the CGCs. 547 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 548 * in a specific operation, UTP controller CGCs are by default disabled and 549 * this function enables them (after every UFS link startup) to save some power 550 * leakage. 551 */ 552 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 553 { 554 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, 555 REG_UFS_CFG2); 556 557 /* Ensure that HW clock gating is enabled before next operations */ 558 ufshcd_readl(hba, REG_UFS_CFG2); 559 } 560 561 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 562 enum ufs_notify_change_status status) 563 { 564 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 565 int err; 566 567 switch (status) { 568 case PRE_CHANGE: 569 err = ufs_qcom_power_up_sequence(hba); 570 if (err) 571 return err; 572 573 /* 574 * The PHY PLL output is the source of tx/rx lane symbol 575 * clocks, hence, enable the lane clocks only after PHY 576 * is initialized. 577 */ 578 err = ufs_qcom_enable_lane_clks(host); 579 break; 580 case POST_CHANGE: 581 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 582 err = ufs_qcom_check_hibern8(hba); 583 ufs_qcom_enable_hw_clk_gating(hba); 584 ufs_qcom_ice_enable(host); 585 ufs_qcom_config_ice_allocator(host); 586 break; 587 default: 588 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 589 err = -EINVAL; 590 break; 591 } 592 return err; 593 } 594 595 /** 596 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers 597 * 598 * @hba: host controller instance 599 * @is_pre_scale_up: flag to check if pre scale up condition. 600 * Return: zero for success and non-zero in case of a failure. 601 */ 602 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up) 603 { 604 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 605 struct ufs_clk_info *clki; 606 unsigned long core_clk_rate = 0; 607 u32 core_clk_cycles_per_us; 608 609 /* 610 * UTP controller uses SYS1CLK_1US_REG register for Interrupt 611 * Aggregation logic. 612 * It is mandatory to write SYS1CLK_1US_REG register on UFS host 613 * controller V4.0.0 onwards. 614 */ 615 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) 616 return 0; 617 618 list_for_each_entry(clki, &hba->clk_list_head, list) { 619 if (!strcmp(clki->name, "core_clk")) { 620 if (is_pre_scale_up) 621 core_clk_rate = clki->max_freq; 622 else 623 core_clk_rate = clk_get_rate(clki->clk); 624 break; 625 } 626 627 } 628 629 /* If frequency is smaller than 1MHz, set to 1MHz */ 630 if (core_clk_rate < DEFAULT_CLK_RATE_HZ) 631 core_clk_rate = DEFAULT_CLK_RATE_HZ; 632 633 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; 634 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 635 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 636 /* 637 * make sure above write gets applied before we return from 638 * this function. 639 */ 640 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US); 641 } 642 643 return 0; 644 } 645 646 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 647 enum ufs_notify_change_status status) 648 { 649 int err = 0; 650 651 switch (status) { 652 case PRE_CHANGE: 653 if (ufs_qcom_cfg_timers(hba, false)) { 654 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 655 __func__); 656 return -EINVAL; 657 } 658 659 err = ufs_qcom_set_core_clk_ctrl(hba, ULONG_MAX); 660 if (err) 661 dev_err(hba->dev, "cfg core clk ctrl failed\n"); 662 /* 663 * Some UFS devices (and may be host) have issues if LCC is 664 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 665 * before link startup which will make sure that both host 666 * and device TX LCC are disabled once link startup is 667 * completed. 668 */ 669 err = ufshcd_disable_host_tx_lcc(hba); 670 671 break; 672 default: 673 break; 674 } 675 676 return err; 677 } 678 679 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 680 { 681 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 682 683 /* reset gpio is optional */ 684 if (!host->device_reset) 685 return; 686 687 gpiod_set_value_cansleep(host->device_reset, asserted); 688 } 689 690 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 691 enum ufs_notify_change_status status) 692 { 693 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 694 struct phy *phy = host->generic_phy; 695 696 if (status == PRE_CHANGE) 697 return 0; 698 699 if (ufs_qcom_is_link_off(hba)) { 700 /* 701 * Disable the tx/rx lane symbol clocks before PHY is 702 * powered down as the PLL source should be disabled 703 * after downstream clocks are disabled. 704 */ 705 ufs_qcom_disable_lane_clks(host); 706 phy_power_off(phy); 707 708 /* reset the connected UFS device during power down */ 709 ufs_qcom_device_reset_ctrl(hba, true); 710 711 } else if (!ufs_qcom_is_link_active(hba)) { 712 ufs_qcom_disable_lane_clks(host); 713 } 714 715 return ufs_qcom_ice_suspend(host); 716 } 717 718 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 719 { 720 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 721 struct phy *phy = host->generic_phy; 722 int err; 723 724 if (ufs_qcom_is_link_off(hba)) { 725 err = phy_power_on(phy); 726 if (err) { 727 dev_err(hba->dev, "%s: failed PHY power on: %d\n", 728 __func__, err); 729 return err; 730 } 731 732 err = ufs_qcom_enable_lane_clks(host); 733 if (err) 734 return err; 735 736 } else if (!ufs_qcom_is_link_active(hba)) { 737 err = ufs_qcom_enable_lane_clks(host); 738 if (err) 739 return err; 740 } 741 742 return ufs_qcom_ice_resume(host); 743 } 744 745 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 746 { 747 if (host->dev_ref_clk_ctrl_mmio && 748 (enable ^ host->is_dev_ref_clk_enabled)) { 749 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 750 751 if (enable) 752 temp |= host->dev_ref_clk_en_mask; 753 else 754 temp &= ~host->dev_ref_clk_en_mask; 755 756 /* 757 * If we are here to disable this clock it might be immediately 758 * after entering into hibern8 in which case we need to make 759 * sure that device ref_clk is active for specific time after 760 * hibern8 enter. 761 */ 762 if (!enable) { 763 unsigned long gating_wait; 764 765 gating_wait = host->hba->dev_info.clk_gating_wait_us; 766 if (!gating_wait) { 767 udelay(1); 768 } else { 769 /* 770 * bRefClkGatingWaitTime defines the minimum 771 * time for which the reference clock is 772 * required by device during transition from 773 * HS-MODE to LS-MODE or HIBERN8 state. Give it 774 * more delay to be on the safe side. 775 */ 776 gating_wait += 10; 777 usleep_range(gating_wait, gating_wait + 10); 778 } 779 } 780 781 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 782 783 /* 784 * Make sure the write to ref_clk reaches the destination and 785 * not stored in a Write Buffer (WB). 786 */ 787 readl(host->dev_ref_clk_ctrl_mmio); 788 789 /* 790 * If we call hibern8 exit after this, we need to make sure that 791 * device ref_clk is stable for at least 1us before the hibern8 792 * exit command. 793 */ 794 if (enable) 795 udelay(1); 796 797 host->is_dev_ref_clk_enabled = enable; 798 } 799 } 800 801 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 802 { 803 struct device *dev = host->hba->dev; 804 int ret; 805 806 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 807 if (ret < 0) { 808 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 809 return ret; 810 } 811 812 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 813 if (ret < 0) { 814 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 815 return ret; 816 } 817 818 return 0; 819 } 820 821 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 822 { 823 struct ufs_pa_layer_attr *p = &host->dev_req_params; 824 int gear = max_t(u32, p->gear_rx, p->gear_tx); 825 int lane = max_t(u32, p->lane_rx, p->lane_tx); 826 827 if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR, 828 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n", 829 gear, QCOM_UFS_MAX_GEAR)) 830 gear = QCOM_UFS_MAX_GEAR; 831 832 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE, 833 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n", 834 lane, QCOM_UFS_MAX_LANE)) 835 lane = QCOM_UFS_MAX_LANE; 836 837 if (ufshcd_is_hs_mode(p)) { 838 if (p->hs_rate == PA_HS_MODE_B) 839 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 840 else 841 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 842 } else { 843 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 844 } 845 } 846 847 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 848 { 849 struct __ufs_qcom_bw_table bw_table; 850 851 bw_table = ufs_qcom_get_bw_table(host); 852 853 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 854 } 855 856 static void ufs_qcom_set_tx_hs_equalizer(struct ufs_hba *hba, u32 gear, u32 tx_lanes) 857 { 858 u32 equalizer_val; 859 int ret, i; 860 861 /* Determine the equalizer value based on the gear */ 862 equalizer_val = (gear == 5) ? DEEMPHASIS_3_5_dB : NO_DEEMPHASIS; 863 864 for (i = 0; i < tx_lanes; i++) { 865 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HS_EQUALIZER, i), 866 equalizer_val); 867 if (ret) 868 dev_err(hba->dev, "%s: failed equalizer lane %d\n", 869 __func__, i); 870 } 871 } 872 873 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 874 enum ufs_notify_change_status status, 875 const struct ufs_pa_layer_attr *dev_max_params, 876 struct ufs_pa_layer_attr *dev_req_params) 877 { 878 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 879 struct ufs_host_params *host_params = &host->host_params; 880 int ret = 0; 881 882 if (!dev_req_params) { 883 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 884 return -EINVAL; 885 } 886 887 switch (status) { 888 case PRE_CHANGE: 889 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); 890 if (ret) { 891 dev_err(hba->dev, "%s: failed to determine capabilities\n", 892 __func__); 893 return ret; 894 } 895 896 /* 897 * During UFS driver probe, always update the PHY gear to match the negotiated 898 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled, 899 * the second init can program the optimal PHY settings. This allows one to start 900 * the first init with either the minimum or the maximum support gear. 901 */ 902 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { 903 /* 904 * Skip REINIT if the negotiated gear matches with the 905 * initial phy_gear. Otherwise, update the phy_gear to 906 * program the optimal gear setting during REINIT. 907 */ 908 if (host->phy_gear == dev_req_params->gear_tx) 909 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 910 else 911 host->phy_gear = dev_req_params->gear_tx; 912 } 913 914 /* enable the device ref clock before changing to HS mode */ 915 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 916 ufshcd_is_hs_mode(dev_req_params)) 917 ufs_qcom_dev_ref_clk_ctrl(host, true); 918 919 if (host->hw_ver.major >= 0x4) { 920 ufshcd_dme_configure_adapt(hba, 921 dev_req_params->gear_tx, 922 PA_INITIAL_ADAPT); 923 } 924 925 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING) 926 ufs_qcom_set_tx_hs_equalizer(hba, 927 dev_req_params->gear_tx, dev_req_params->lane_tx); 928 929 break; 930 case POST_CHANGE: 931 if (ufs_qcom_cfg_timers(hba, false)) { 932 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 933 __func__); 934 /* 935 * we return error code at the end of the routine, 936 * but continue to configure UFS_PHY_TX_LANE_ENABLE 937 * and bus voting as usual 938 */ 939 ret = -EINVAL; 940 } 941 942 /* cache the power mode parameters to use internally */ 943 memcpy(&host->dev_req_params, 944 dev_req_params, sizeof(*dev_req_params)); 945 946 ufs_qcom_icc_update_bw(host); 947 948 /* disable the device ref clock if entered PWM mode */ 949 if (ufshcd_is_hs_mode(&hba->pwr_info) && 950 !ufshcd_is_hs_mode(dev_req_params)) 951 ufs_qcom_dev_ref_clk_ctrl(host, false); 952 break; 953 default: 954 ret = -EINVAL; 955 break; 956 } 957 958 return ret; 959 } 960 961 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 962 { 963 int err; 964 u32 pa_vs_config_reg1; 965 966 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 967 &pa_vs_config_reg1); 968 if (err) 969 return err; 970 971 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 972 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 973 (pa_vs_config_reg1 | (1 << 12))); 974 } 975 976 static void ufs_qcom_override_pa_tx_hsg1_sync_len(struct ufs_hba *hba) 977 { 978 int err; 979 980 err = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TX_HSG1_SYNC_LENGTH), 981 PA_TX_HSG1_SYNC_LENGTH_VAL); 982 if (err) 983 dev_err(hba->dev, "Failed (%d) set PA_TX_HSG1_SYNC_LENGTH\n", err); 984 } 985 986 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 987 { 988 int err = 0; 989 990 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 991 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 992 993 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH) 994 ufs_qcom_override_pa_tx_hsg1_sync_len(hba); 995 996 return err; 997 } 998 999 /* UFS device-specific quirks */ 1000 static struct ufs_dev_quirk ufs_qcom_dev_fixups[] = { 1001 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 1002 .model = UFS_ANY_MODEL, 1003 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 1004 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 1005 .model = UFS_ANY_MODEL, 1006 .quirk = UFS_DEVICE_QUIRK_DELAY_AFTER_LPM }, 1007 { .wmanufacturerid = UFS_VENDOR_WDC, 1008 .model = UFS_ANY_MODEL, 1009 .quirk = UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE }, 1010 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 1011 .model = UFS_ANY_MODEL, 1012 .quirk = UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH | 1013 UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING }, 1014 {} 1015 }; 1016 1017 static void ufs_qcom_fixup_dev_quirks(struct ufs_hba *hba) 1018 { 1019 ufshcd_fixup_dev_quirks(hba, ufs_qcom_dev_fixups); 1020 } 1021 1022 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 1023 { 1024 return ufshci_version(2, 0); 1025 } 1026 1027 /** 1028 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 1029 * @hba: host controller instance 1030 * 1031 * QCOM UFS host controller might have some non standard behaviours (quirks) 1032 * than what is specified by UFSHCI specification. Advertise all such 1033 * quirks to standard UFS host controller driver so standard takes them into 1034 * account. 1035 */ 1036 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 1037 { 1038 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); 1039 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1040 1041 if (host->hw_ver.major == 0x2) 1042 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 1043 1044 if (host->hw_ver.major > 0x3) 1045 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1046 1047 if (drvdata && drvdata->quirks) 1048 hba->quirks |= drvdata->quirks; 1049 } 1050 1051 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) 1052 { 1053 struct ufs_host_params *host_params = &host->host_params; 1054 u32 val, dev_major; 1055 1056 /* 1057 * Default to powering up the PHY to the max gear possible, which is 1058 * backwards compatible with lower gears but not optimal from 1059 * a power usage point of view. After device negotiation, if the 1060 * gear is lower a reinit will be performed to program the PHY 1061 * to the ideal gear for this combo of controller and device. 1062 */ 1063 host->phy_gear = host_params->hs_tx_gear; 1064 1065 if (host->hw_ver.major < 0x4) { 1066 /* 1067 * These controllers only have one PHY init sequence, 1068 * let's power up the PHY using that (the minimum supported 1069 * gear, UFS_HS_G2). 1070 */ 1071 host->phy_gear = UFS_HS_G2; 1072 } else if (host->hw_ver.major >= 0x5) { 1073 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); 1074 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val); 1075 1076 /* 1077 * Since the UFS device version is populated, let's remove the 1078 * REINIT quirk as the negotiated gear won't change during boot. 1079 * So there is no need to do reinit. 1080 */ 1081 if (dev_major != 0x0) 1082 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1083 1084 /* 1085 * For UFS 3.1 device and older, power up the PHY using HS-G4 1086 * PHY gear to save power. 1087 */ 1088 if (dev_major > 0x0 && dev_major < 0x4) 1089 host->phy_gear = UFS_HS_G4; 1090 } 1091 } 1092 1093 static void ufs_qcom_set_host_params(struct ufs_hba *hba) 1094 { 1095 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1096 struct ufs_host_params *host_params = &host->host_params; 1097 1098 ufshcd_init_host_params(host_params); 1099 1100 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 1101 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); 1102 } 1103 1104 static void ufs_qcom_set_host_caps(struct ufs_hba *hba) 1105 { 1106 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1107 1108 if (host->hw_ver.major >= 0x5) 1109 host->caps |= UFS_QCOM_CAP_ICE_CONFIG; 1110 } 1111 1112 static void ufs_qcom_set_caps(struct ufs_hba *hba) 1113 { 1114 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1115 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 1116 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1117 hba->caps |= UFSHCD_CAP_WB_EN; 1118 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 1119 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 1120 1121 ufs_qcom_set_host_caps(hba); 1122 } 1123 1124 /** 1125 * ufs_qcom_setup_clocks - enables/disable clocks 1126 * @hba: host controller instance 1127 * @on: If true, enable clocks else disable them. 1128 * @status: PRE_CHANGE or POST_CHANGE notify 1129 * 1130 * Return: 0 on success, non-zero on failure. 1131 */ 1132 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 1133 enum ufs_notify_change_status status) 1134 { 1135 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1136 1137 /* 1138 * In case ufs_qcom_init() is not yet done, simply ignore. 1139 * This ufs_qcom_setup_clocks() shall be called from 1140 * ufs_qcom_init() after init is done. 1141 */ 1142 if (!host) 1143 return 0; 1144 1145 switch (status) { 1146 case PRE_CHANGE: 1147 if (on) { 1148 ufs_qcom_icc_update_bw(host); 1149 } else { 1150 if (!ufs_qcom_is_link_active(hba)) { 1151 /* disable device ref_clk */ 1152 ufs_qcom_dev_ref_clk_ctrl(host, false); 1153 } 1154 } 1155 break; 1156 case POST_CHANGE: 1157 if (on) { 1158 /* enable the device ref clock for HS mode*/ 1159 if (ufshcd_is_hs_mode(&hba->pwr_info)) 1160 ufs_qcom_dev_ref_clk_ctrl(host, true); 1161 } else { 1162 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 1163 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 1164 } 1165 break; 1166 } 1167 1168 return 0; 1169 } 1170 1171 static int 1172 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 1173 { 1174 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1175 1176 ufs_qcom_assert_reset(host->hba); 1177 /* provide 1ms delay to let the reset pulse propagate. */ 1178 usleep_range(1000, 1100); 1179 return 0; 1180 } 1181 1182 static int 1183 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 1184 { 1185 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1186 1187 ufs_qcom_deassert_reset(host->hba); 1188 1189 /* 1190 * after reset deassertion, phy will need all ref clocks, 1191 * voltage, current to settle down before starting serdes. 1192 */ 1193 usleep_range(1000, 1100); 1194 return 0; 1195 } 1196 1197 static const struct reset_control_ops ufs_qcom_reset_ops = { 1198 .assert = ufs_qcom_reset_assert, 1199 .deassert = ufs_qcom_reset_deassert, 1200 }; 1201 1202 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 1203 { 1204 struct device *dev = host->hba->dev; 1205 int ret; 1206 1207 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 1208 if (IS_ERR(host->icc_ddr)) 1209 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 1210 "failed to acquire interconnect path\n"); 1211 1212 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1213 if (IS_ERR(host->icc_cpu)) 1214 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1215 "failed to acquire interconnect path\n"); 1216 1217 /* 1218 * Set Maximum bandwidth vote before initializing the UFS controller and 1219 * device. Ideally, a minimal interconnect vote would suffice for the 1220 * initialization, but a max vote would allow faster initialization. 1221 */ 1222 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1223 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1224 if (ret < 0) 1225 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1226 1227 return 0; 1228 } 1229 1230 /** 1231 * ufs_qcom_init - bind phy with controller 1232 * @hba: host controller instance 1233 * 1234 * Binds PHY with controller and powers up PHY enabling clocks 1235 * and regulators. 1236 * 1237 * Return: -EPROBE_DEFER if binding fails, returns negative error 1238 * on phy power up failure and returns zero on success. 1239 */ 1240 static int ufs_qcom_init(struct ufs_hba *hba) 1241 { 1242 int err; 1243 struct device *dev = hba->dev; 1244 struct ufs_qcom_host *host; 1245 struct ufs_clk_info *clki; 1246 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); 1247 1248 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1249 if (!host) 1250 return -ENOMEM; 1251 1252 /* Make a two way bind between the qcom host and the hba */ 1253 host->hba = hba; 1254 ufshcd_set_variant(hba, host); 1255 1256 /* Setup the optional reset control of HCI */ 1257 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1258 if (IS_ERR(host->core_reset)) { 1259 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1260 "Failed to get reset control\n"); 1261 goto out_variant_clear; 1262 } 1263 1264 /* Fire up the reset controller. Failure here is non-fatal. */ 1265 host->rcdev.of_node = dev->of_node; 1266 host->rcdev.ops = &ufs_qcom_reset_ops; 1267 host->rcdev.owner = dev->driver->owner; 1268 host->rcdev.nr_resets = 1; 1269 err = devm_reset_controller_register(dev, &host->rcdev); 1270 if (err) 1271 dev_warn(dev, "Failed to register reset controller\n"); 1272 1273 if (!has_acpi_companion(dev)) { 1274 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1275 if (IS_ERR(host->generic_phy)) { 1276 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1277 goto out_variant_clear; 1278 } 1279 } 1280 1281 err = ufs_qcom_icc_init(host); 1282 if (err) 1283 goto out_variant_clear; 1284 1285 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1286 GPIOD_OUT_HIGH); 1287 if (IS_ERR(host->device_reset)) { 1288 err = dev_err_probe(dev, PTR_ERR(host->device_reset), 1289 "Failed to acquire device reset gpio\n"); 1290 goto out_variant_clear; 1291 } 1292 1293 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1294 &host->hw_ver.minor, &host->hw_ver.step); 1295 1296 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1297 host->dev_ref_clk_en_mask = BIT(26); 1298 1299 list_for_each_entry(clki, &hba->clk_list_head, list) { 1300 if (!strcmp(clki->name, "core_clk_unipro")) 1301 clki->keep_link_active = true; 1302 } 1303 1304 err = ufs_qcom_init_lane_clks(host); 1305 if (err) 1306 goto out_variant_clear; 1307 1308 ufs_qcom_set_caps(hba); 1309 ufs_qcom_advertise_quirks(hba); 1310 ufs_qcom_set_host_params(hba); 1311 ufs_qcom_set_phy_gear(host); 1312 1313 err = ufs_qcom_ice_init(host); 1314 if (err) 1315 goto out_variant_clear; 1316 1317 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1318 1319 ufs_qcom_get_default_testbus_cfg(host); 1320 err = ufs_qcom_testbus_config(host); 1321 if (err) 1322 /* Failure is non-fatal */ 1323 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1324 __func__, err); 1325 1326 if (drvdata && drvdata->no_phy_retention) 1327 hba->spm_lvl = UFS_PM_LVL_5; 1328 1329 return 0; 1330 1331 out_variant_clear: 1332 ufshcd_set_variant(hba, NULL); 1333 1334 return err; 1335 } 1336 1337 static void ufs_qcom_exit(struct ufs_hba *hba) 1338 { 1339 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1340 1341 ufs_qcom_disable_lane_clks(host); 1342 phy_power_off(host->generic_phy); 1343 phy_exit(host->generic_phy); 1344 } 1345 1346 /** 1347 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles 1348 * 1349 * @hba: host controller instance 1350 * @cycles_in_1us: No of cycles in 1us to be configured 1351 * 1352 * Returns error if dme get/set configuration for 40ns fails 1353 * and returns zero on success. 1354 */ 1355 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, 1356 u32 cycles_in_1us) 1357 { 1358 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1359 u32 cycles_in_40ns; 1360 u32 reg; 1361 int err; 1362 1363 /* 1364 * UFS host controller V4.0.0 onwards needs to program 1365 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed 1366 * frequency of unipro core clk of UFS host controller. 1367 */ 1368 if (host->hw_ver.major < 4) 1369 return 0; 1370 1371 /* 1372 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not 1373 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will 1374 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware 1375 * specification expect to be 16. Hence use exact hardware spec 1376 * mandated value for cycles_in_40ns instead of calculating using 1377 * generic formulae. 1378 */ 1379 switch (cycles_in_1us) { 1380 case UNIPRO_CORE_CLK_FREQ_403_MHZ: 1381 cycles_in_40ns = 16; 1382 break; 1383 case UNIPRO_CORE_CLK_FREQ_300_MHZ: 1384 cycles_in_40ns = 12; 1385 break; 1386 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ: 1387 cycles_in_40ns = 8; 1388 break; 1389 case UNIPRO_CORE_CLK_FREQ_150_MHZ: 1390 cycles_in_40ns = 6; 1391 break; 1392 case UNIPRO_CORE_CLK_FREQ_100_MHZ: 1393 cycles_in_40ns = 4; 1394 break; 1395 case UNIPRO_CORE_CLK_FREQ_75_MHZ: 1396 cycles_in_40ns = 3; 1397 break; 1398 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ: 1399 cycles_in_40ns = 2; 1400 break; 1401 default: 1402 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", 1403 cycles_in_1us); 1404 return -EINVAL; 1405 } 1406 1407 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); 1408 if (err) 1409 return err; 1410 1411 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; 1412 reg |= cycles_in_40ns; 1413 1414 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); 1415 } 1416 1417 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq) 1418 { 1419 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1420 struct list_head *head = &hba->clk_list_head; 1421 struct ufs_clk_info *clki; 1422 u32 cycles_in_1us = 0; 1423 u32 core_clk_ctrl_reg; 1424 int err; 1425 1426 list_for_each_entry(clki, head, list) { 1427 if (!IS_ERR_OR_NULL(clki->clk) && 1428 !strcmp(clki->name, "core_clk_unipro")) { 1429 if (!clki->max_freq) 1430 cycles_in_1us = 150; /* default for backwards compatibility */ 1431 else if (freq == ULONG_MAX) 1432 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); 1433 else 1434 cycles_in_1us = ceil(freq, HZ_PER_MHZ); 1435 1436 break; 1437 } 1438 } 1439 1440 err = ufshcd_dme_get(hba, 1441 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1442 &core_clk_ctrl_reg); 1443 if (err) 1444 return err; 1445 1446 /* Bit mask is different for UFS host controller V4.0.0 onwards */ 1447 if (host->hw_ver.major >= 4) { 1448 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us)) 1449 return -ERANGE; 1450 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4; 1451 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us); 1452 } else { 1453 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us)) 1454 return -ERANGE; 1455 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK; 1456 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); 1457 } 1458 1459 /* Clear CORE_CLK_DIV_EN */ 1460 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1461 1462 err = ufshcd_dme_set(hba, 1463 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1464 core_clk_ctrl_reg); 1465 if (err) 1466 return err; 1467 1468 /* Configure unipro core clk 40ns attribute */ 1469 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); 1470 } 1471 1472 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long freq) 1473 { 1474 int ret; 1475 1476 ret = ufs_qcom_cfg_timers(hba, true); 1477 if (ret) { 1478 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); 1479 return ret; 1480 } 1481 /* set unipro core clock attributes and clear clock divider */ 1482 return ufs_qcom_set_core_clk_ctrl(hba, freq); 1483 } 1484 1485 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1486 { 1487 return 0; 1488 } 1489 1490 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1491 { 1492 int err; 1493 u32 core_clk_ctrl_reg; 1494 1495 err = ufshcd_dme_get(hba, 1496 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1497 &core_clk_ctrl_reg); 1498 1499 /* make sure CORE_CLK_DIV_EN is cleared */ 1500 if (!err && 1501 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1502 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1503 err = ufshcd_dme_set(hba, 1504 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1505 core_clk_ctrl_reg); 1506 } 1507 1508 return err; 1509 } 1510 1511 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq) 1512 { 1513 /* set unipro core clock attributes and clear clock divider */ 1514 return ufs_qcom_set_core_clk_ctrl(hba, freq); 1515 } 1516 1517 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, 1518 unsigned long target_freq, 1519 enum ufs_notify_change_status status) 1520 { 1521 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1522 int err; 1523 1524 /* check the host controller state before sending hibern8 cmd */ 1525 if (!ufshcd_is_hba_active(hba)) 1526 return 0; 1527 1528 if (status == PRE_CHANGE) { 1529 err = ufshcd_uic_hibern8_enter(hba); 1530 if (err) 1531 return err; 1532 if (scale_up) 1533 err = ufs_qcom_clk_scale_up_pre_change(hba, target_freq); 1534 else 1535 err = ufs_qcom_clk_scale_down_pre_change(hba); 1536 1537 if (err) { 1538 ufshcd_uic_hibern8_exit(hba); 1539 return err; 1540 } 1541 } else { 1542 if (scale_up) 1543 err = ufs_qcom_clk_scale_up_post_change(hba); 1544 else 1545 err = ufs_qcom_clk_scale_down_post_change(hba, target_freq); 1546 1547 1548 if (err) { 1549 ufshcd_uic_hibern8_exit(hba); 1550 return err; 1551 } 1552 1553 ufs_qcom_icc_update_bw(host); 1554 ufshcd_uic_hibern8_exit(hba); 1555 } 1556 1557 return 0; 1558 } 1559 1560 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1561 { 1562 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1563 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1564 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1565 } 1566 1567 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1568 { 1569 /* provide a legal default configuration */ 1570 host->testbus.select_major = TSTBUS_UNIPRO; 1571 host->testbus.select_minor = 37; 1572 } 1573 1574 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1575 { 1576 if (host->testbus.select_major >= TSTBUS_MAX) { 1577 dev_err(host->hba->dev, 1578 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1579 __func__, host->testbus.select_major); 1580 return false; 1581 } 1582 1583 return true; 1584 } 1585 1586 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1587 { 1588 int reg; 1589 int offset; 1590 u32 mask = TEST_BUS_SUB_SEL_MASK; 1591 1592 if (!host) 1593 return -EINVAL; 1594 1595 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1596 return -EPERM; 1597 1598 switch (host->testbus.select_major) { 1599 case TSTBUS_UAWM: 1600 reg = UFS_TEST_BUS_CTRL_0; 1601 offset = 24; 1602 break; 1603 case TSTBUS_UARM: 1604 reg = UFS_TEST_BUS_CTRL_0; 1605 offset = 16; 1606 break; 1607 case TSTBUS_TXUC: 1608 reg = UFS_TEST_BUS_CTRL_0; 1609 offset = 8; 1610 break; 1611 case TSTBUS_RXUC: 1612 reg = UFS_TEST_BUS_CTRL_0; 1613 offset = 0; 1614 break; 1615 case TSTBUS_DFC: 1616 reg = UFS_TEST_BUS_CTRL_1; 1617 offset = 24; 1618 break; 1619 case TSTBUS_TRLUT: 1620 reg = UFS_TEST_BUS_CTRL_1; 1621 offset = 16; 1622 break; 1623 case TSTBUS_TMRLUT: 1624 reg = UFS_TEST_BUS_CTRL_1; 1625 offset = 8; 1626 break; 1627 case TSTBUS_OCSC: 1628 reg = UFS_TEST_BUS_CTRL_1; 1629 offset = 0; 1630 break; 1631 case TSTBUS_WRAPPER: 1632 reg = UFS_TEST_BUS_CTRL_2; 1633 offset = 16; 1634 break; 1635 case TSTBUS_COMBINED: 1636 reg = UFS_TEST_BUS_CTRL_2; 1637 offset = 8; 1638 break; 1639 case TSTBUS_UTP_HCI: 1640 reg = UFS_TEST_BUS_CTRL_2; 1641 offset = 0; 1642 break; 1643 case TSTBUS_UNIPRO: 1644 reg = UFS_UNIPRO_CFG; 1645 offset = 20; 1646 mask = 0xFFF; 1647 break; 1648 /* 1649 * No need for a default case, since 1650 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 1651 * is legal 1652 */ 1653 } 1654 mask <<= offset; 1655 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 1656 (u32)host->testbus.select_major << 19, 1657 REG_UFS_CFG1); 1658 ufshcd_rmwl(host->hba, mask, 1659 (u32)host->testbus.select_minor << offset, 1660 reg); 1661 ufs_qcom_enable_test_bus(host); 1662 1663 return 0; 1664 } 1665 1666 static void ufs_qcom_dump_testbus(struct ufs_hba *hba) 1667 { 1668 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1669 int i, j, nminor = 0, testbus_len = 0; 1670 u32 *testbus __free(kfree) = NULL; 1671 char *prefix; 1672 1673 testbus = kmalloc_array(256, sizeof(u32), GFP_KERNEL); 1674 if (!testbus) 1675 return; 1676 1677 for (j = 0; j < TSTBUS_MAX; j++) { 1678 nminor = testbus_info[j].nminor; 1679 prefix = testbus_info[j].prefix; 1680 host->testbus.select_major = j; 1681 testbus_len = nminor * sizeof(u32); 1682 for (i = 0; i < nminor; i++) { 1683 host->testbus.select_minor = i; 1684 ufs_qcom_testbus_config(host); 1685 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS); 1686 } 1687 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 1688 16, 4, testbus, testbus_len, false); 1689 } 1690 } 1691 1692 static int ufs_qcom_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1693 const char *prefix, enum ufshcd_res id) 1694 { 1695 u32 *regs __free(kfree) = NULL; 1696 size_t pos; 1697 1698 if (offset % 4 != 0 || len % 4 != 0) 1699 return -EINVAL; 1700 1701 regs = kzalloc(len, GFP_ATOMIC); 1702 if (!regs) 1703 return -ENOMEM; 1704 1705 for (pos = 0; pos < len; pos += 4) 1706 regs[pos / 4] = readl(hba->res[id].base + offset + pos); 1707 1708 print_hex_dump(KERN_ERR, prefix, 1709 len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE, 1710 16, 4, regs, len, false); 1711 1712 return 0; 1713 } 1714 1715 static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba) 1716 { 1717 struct dump_info { 1718 size_t offset; 1719 size_t len; 1720 const char *prefix; 1721 enum ufshcd_res id; 1722 }; 1723 1724 struct dump_info mcq_dumps[] = { 1725 {0x0, 256 * 4, "MCQ HCI-0 ", RES_MCQ}, 1726 {0x400, 256 * 4, "MCQ HCI-1 ", RES_MCQ}, 1727 {0x0, 5 * 4, "MCQ VS-0 ", RES_MCQ_VS}, 1728 {0x0, 256 * 4, "MCQ SQD-0 ", RES_MCQ_SQD}, 1729 {0x400, 256 * 4, "MCQ SQD-1 ", RES_MCQ_SQD}, 1730 {0x800, 256 * 4, "MCQ SQD-2 ", RES_MCQ_SQD}, 1731 {0xc00, 256 * 4, "MCQ SQD-3 ", RES_MCQ_SQD}, 1732 {0x1000, 256 * 4, "MCQ SQD-4 ", RES_MCQ_SQD}, 1733 {0x1400, 256 * 4, "MCQ SQD-5 ", RES_MCQ_SQD}, 1734 {0x1800, 256 * 4, "MCQ SQD-6 ", RES_MCQ_SQD}, 1735 {0x1c00, 256 * 4, "MCQ SQD-7 ", RES_MCQ_SQD}, 1736 }; 1737 1738 for (int i = 0; i < ARRAY_SIZE(mcq_dumps); i++) { 1739 ufs_qcom_dump_regs(hba, mcq_dumps[i].offset, mcq_dumps[i].len, 1740 mcq_dumps[i].prefix, mcq_dumps[i].id); 1741 cond_resched(); 1742 } 1743 } 1744 1745 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 1746 { 1747 u32 reg; 1748 struct ufs_qcom_host *host; 1749 1750 host = ufshcd_get_variant(hba); 1751 1752 dev_err(hba->dev, "HW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_ENTER_CNT)); 1753 dev_err(hba->dev, "HW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_EXIT_CNT)); 1754 1755 dev_err(hba->dev, "SW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_ENTER_CNT)); 1756 dev_err(hba->dev, "SW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_EXIT_CNT)); 1757 1758 dev_err(hba->dev, "SW_AFTER_HW_H8_ENTER_CNT=%d\n", 1759 ufshcd_readl(hba, REG_UFS_SW_AFTER_HW_H8_ENTER_CNT)); 1760 1761 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 1762 "HCI Vendor Specific Registers "); 1763 1764 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 1765 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 1766 1767 reg = ufshcd_readl(hba, REG_UFS_CFG1); 1768 reg |= UTP_DBG_RAMS_EN; 1769 ufshcd_writel(hba, reg, REG_UFS_CFG1); 1770 1771 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 1772 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 1773 1774 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 1775 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 1776 1777 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 1778 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 1779 1780 /* clear bit 17 - UTP_DBG_RAMS_EN */ 1781 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 1782 1783 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 1784 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 1785 1786 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 1787 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 1788 1789 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 1790 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 1791 1792 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 1793 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 1794 1795 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 1796 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 1797 1798 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 1799 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 1800 1801 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 1802 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 1803 1804 if (hba->mcq_enabled) { 1805 reg = ufs_qcom_get_debug_reg_offset(host, UFS_RD_REG_MCQ); 1806 ufshcd_dump_regs(hba, reg, 64 * 4, "HCI MCQ Debug Registers "); 1807 } 1808 1809 /* ensure below dumps occur only in task context due to blocking calls. */ 1810 if (in_task()) { 1811 /* Dump MCQ Host Vendor Specific Registers */ 1812 if (hba->mcq_enabled) 1813 ufs_qcom_dump_mcq_hci_regs(hba); 1814 1815 /* voluntarily yield the CPU as we are dumping too much data */ 1816 ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS "); 1817 cond_resched(); 1818 ufs_qcom_dump_testbus(hba); 1819 } 1820 } 1821 1822 /** 1823 * ufs_qcom_device_reset() - toggle the (optional) device reset line 1824 * @hba: per-adapter instance 1825 * 1826 * Toggles the (optional) reset line to reset the attached device. 1827 */ 1828 static int ufs_qcom_device_reset(struct ufs_hba *hba) 1829 { 1830 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1831 1832 /* reset gpio is optional */ 1833 if (!host->device_reset) 1834 return -EOPNOTSUPP; 1835 1836 /* 1837 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 1838 * be on the safe side. 1839 */ 1840 ufs_qcom_device_reset_ctrl(hba, true); 1841 usleep_range(10, 15); 1842 1843 ufs_qcom_device_reset_ctrl(hba, false); 1844 usleep_range(10, 15); 1845 1846 return 0; 1847 } 1848 1849 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) 1850 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1851 struct devfreq_dev_profile *p, 1852 struct devfreq_simple_ondemand_data *d) 1853 { 1854 p->polling_ms = 60; 1855 p->timer = DEVFREQ_TIMER_DELAYED; 1856 d->upthreshold = 70; 1857 d->downdifferential = 5; 1858 1859 hba->clk_scaling.suspend_on_no_request = true; 1860 } 1861 #else 1862 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1863 struct devfreq_dev_profile *p, 1864 struct devfreq_simple_ondemand_data *data) 1865 { 1866 } 1867 #endif 1868 1869 /* Resources */ 1870 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { 1871 {.name = "ufs_mem",}, 1872 {.name = "mcq",}, 1873 /* Submission Queue DAO */ 1874 {.name = "mcq_sqd",}, 1875 /* Submission Queue Interrupt Status */ 1876 {.name = "mcq_sqis",}, 1877 /* Completion Queue DAO */ 1878 {.name = "mcq_cqd",}, 1879 /* Completion Queue Interrupt Status */ 1880 {.name = "mcq_cqis",}, 1881 /* MCQ vendor specific */ 1882 {.name = "mcq_vs",}, 1883 }; 1884 1885 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 1886 { 1887 struct platform_device *pdev = to_platform_device(hba->dev); 1888 struct ufshcd_res_info *res; 1889 struct resource *res_mem, *res_mcq; 1890 int i, ret; 1891 1892 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); 1893 1894 for (i = 0; i < RES_MAX; i++) { 1895 res = &hba->res[i]; 1896 res->resource = platform_get_resource_byname(pdev, 1897 IORESOURCE_MEM, 1898 res->name); 1899 if (!res->resource) { 1900 dev_info(hba->dev, "Resource %s not provided\n", res->name); 1901 if (i == RES_UFS) 1902 return -ENODEV; 1903 continue; 1904 } else if (i == RES_UFS) { 1905 res_mem = res->resource; 1906 res->base = hba->mmio_base; 1907 continue; 1908 } 1909 1910 res->base = devm_ioremap_resource(hba->dev, res->resource); 1911 if (IS_ERR(res->base)) { 1912 dev_err(hba->dev, "Failed to map res %s, err=%d\n", 1913 res->name, (int)PTR_ERR(res->base)); 1914 ret = PTR_ERR(res->base); 1915 res->base = NULL; 1916 return ret; 1917 } 1918 } 1919 1920 /* MCQ resource provided in DT */ 1921 res = &hba->res[RES_MCQ]; 1922 /* Bail if MCQ resource is provided */ 1923 if (res->base) 1924 goto out; 1925 1926 /* Explicitly allocate MCQ resource from ufs_mem */ 1927 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); 1928 if (!res_mcq) 1929 return -ENOMEM; 1930 1931 res_mcq->start = res_mem->start + 1932 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); 1933 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; 1934 res_mcq->flags = res_mem->flags; 1935 res_mcq->name = "mcq"; 1936 1937 ret = insert_resource(&iomem_resource, res_mcq); 1938 if (ret) { 1939 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", 1940 ret); 1941 return ret; 1942 } 1943 1944 res->base = devm_ioremap_resource(hba->dev, res_mcq); 1945 if (IS_ERR(res->base)) { 1946 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", 1947 (int)PTR_ERR(res->base)); 1948 ret = PTR_ERR(res->base); 1949 goto ioremap_err; 1950 } 1951 1952 out: 1953 hba->mcq_base = res->base; 1954 return 0; 1955 ioremap_err: 1956 res->base = NULL; 1957 remove_resource(res_mcq); 1958 return ret; 1959 } 1960 1961 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 1962 { 1963 struct ufshcd_res_info *mem_res, *sqdao_res; 1964 struct ufshcd_mcq_opr_info_t *opr; 1965 int i; 1966 1967 mem_res = &hba->res[RES_UFS]; 1968 sqdao_res = &hba->res[RES_MCQ_SQD]; 1969 1970 if (!mem_res->base || !sqdao_res->base) 1971 return -EINVAL; 1972 1973 for (i = 0; i < OPR_MAX; i++) { 1974 opr = &hba->mcq_opr[i]; 1975 opr->offset = sqdao_res->resource->start - 1976 mem_res->resource->start + 0x40 * i; 1977 opr->stride = 0x100; 1978 opr->base = sqdao_res->base + 0x40 * i; 1979 } 1980 1981 return 0; 1982 } 1983 1984 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 1985 { 1986 /* Qualcomm HC supports up to 64 */ 1987 return MAX_SUPP_MAC; 1988 } 1989 1990 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 1991 unsigned long *ocqs) 1992 { 1993 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; 1994 1995 if (!mcq_vs_res->base) 1996 return -EINVAL; 1997 1998 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); 1999 2000 return 0; 2001 } 2002 2003 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 2004 { 2005 struct device *dev = msi_desc_to_dev(desc); 2006 struct ufs_hba *hba = dev_get_drvdata(dev); 2007 2008 ufshcd_mcq_config_esi(hba, msg); 2009 } 2010 2011 struct ufs_qcom_irq { 2012 unsigned int irq; 2013 unsigned int idx; 2014 struct ufs_hba *hba; 2015 }; 2016 2017 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 2018 { 2019 struct ufs_qcom_irq *qi = data; 2020 struct ufs_hba *hba = qi->hba; 2021 struct ufs_hw_queue *hwq = &hba->uhq[qi->idx]; 2022 2023 ufshcd_mcq_write_cqis(hba, 0x1, qi->idx); 2024 ufshcd_mcq_poll_cqe_lock(hba, hwq); 2025 2026 return IRQ_HANDLED; 2027 } 2028 2029 static void ufs_qcom_irq_free(struct ufs_qcom_irq *uqi) 2030 { 2031 for (struct ufs_qcom_irq *q = uqi; q->irq; q++) 2032 devm_free_irq(q->hba->dev, q->irq, q->hba); 2033 2034 platform_device_msi_free_irqs_all(uqi->hba->dev); 2035 devm_kfree(uqi->hba->dev, uqi); 2036 } 2037 2038 DEFINE_FREE(ufs_qcom_irq, struct ufs_qcom_irq *, if (_T) ufs_qcom_irq_free(_T)) 2039 2040 static int ufs_qcom_config_esi(struct ufs_hba *hba) 2041 { 2042 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2043 int nr_irqs, ret; 2044 2045 if (host->esi_enabled) 2046 return 0; 2047 2048 /* 2049 * 1. We only handle CQs as of now. 2050 * 2. Poll queues do not need ESI. 2051 */ 2052 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 2053 2054 struct ufs_qcom_irq *qi __free(ufs_qcom_irq) = 2055 devm_kcalloc(hba->dev, nr_irqs, sizeof(*qi), GFP_KERNEL); 2056 if (!qi) 2057 return -ENOMEM; 2058 /* Preset so __free() has a pointer to hba in all error paths */ 2059 qi[0].hba = hba; 2060 2061 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, 2062 ufs_qcom_write_msi_msg); 2063 if (ret) { 2064 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); 2065 return ret; 2066 } 2067 2068 for (int idx = 0; idx < nr_irqs; idx++) { 2069 qi[idx].irq = msi_get_virq(hba->dev, idx); 2070 qi[idx].idx = idx; 2071 qi[idx].hba = hba; 2072 2073 ret = devm_request_irq(hba->dev, qi[idx].irq, ufs_qcom_mcq_esi_handler, 2074 IRQF_SHARED, "qcom-mcq-esi", qi + idx); 2075 if (ret) { 2076 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", 2077 __func__, qi[idx].irq, ret); 2078 qi[idx].irq = 0; 2079 return ret; 2080 } 2081 } 2082 2083 retain_and_null_ptr(qi); 2084 2085 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && 2086 host->hw_ver.step == 0) { 2087 ufshcd_rmwl(hba, ESI_VEC_MASK, FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), 2088 REG_UFS_CFG3); 2089 } 2090 ufshcd_mcq_enable_esi(hba); 2091 host->esi_enabled = true; 2092 return 0; 2093 } 2094 2095 static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) 2096 { 2097 u32 gear = 0; 2098 2099 switch (freq) { 2100 case 403000000: 2101 gear = UFS_HS_G5; 2102 break; 2103 case 300000000: 2104 gear = UFS_HS_G4; 2105 break; 2106 case 201500000: 2107 gear = UFS_HS_G3; 2108 break; 2109 case 150000000: 2110 case 100000000: 2111 gear = UFS_HS_G2; 2112 break; 2113 case 75000000: 2114 case 37500000: 2115 gear = UFS_HS_G1; 2116 break; 2117 default: 2118 dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq); 2119 break; 2120 } 2121 2122 return gear; 2123 } 2124 2125 /* 2126 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 2127 * 2128 * The variant operations configure the necessary controller and PHY 2129 * handshake during initialization. 2130 */ 2131 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 2132 .name = "qcom", 2133 .init = ufs_qcom_init, 2134 .exit = ufs_qcom_exit, 2135 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 2136 .clk_scale_notify = ufs_qcom_clk_scale_notify, 2137 .setup_clocks = ufs_qcom_setup_clocks, 2138 .hce_enable_notify = ufs_qcom_hce_enable_notify, 2139 .link_startup_notify = ufs_qcom_link_startup_notify, 2140 .pwr_change_notify = ufs_qcom_pwr_change_notify, 2141 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 2142 .fixup_dev_quirks = ufs_qcom_fixup_dev_quirks, 2143 .suspend = ufs_qcom_suspend, 2144 .resume = ufs_qcom_resume, 2145 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 2146 .device_reset = ufs_qcom_device_reset, 2147 .config_scaling_param = ufs_qcom_config_scaling_param, 2148 .mcq_config_resource = ufs_qcom_mcq_config_resource, 2149 .get_hba_mac = ufs_qcom_get_hba_mac, 2150 .op_runtime_config = ufs_qcom_op_runtime_config, 2151 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 2152 .config_esi = ufs_qcom_config_esi, 2153 .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, 2154 }; 2155 2156 /** 2157 * ufs_qcom_probe - probe routine of the driver 2158 * @pdev: pointer to Platform device handle 2159 * 2160 * Return: zero for success and non-zero for failure. 2161 */ 2162 static int ufs_qcom_probe(struct platform_device *pdev) 2163 { 2164 int err; 2165 struct device *dev = &pdev->dev; 2166 2167 /* Perform generic probe */ 2168 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); 2169 if (err) 2170 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 2171 2172 return 0; 2173 } 2174 2175 /** 2176 * ufs_qcom_remove - set driver_data of the device to NULL 2177 * @pdev: pointer to platform device handle 2178 * 2179 * Always returns 0 2180 */ 2181 static void ufs_qcom_remove(struct platform_device *pdev) 2182 { 2183 struct ufs_hba *hba = platform_get_drvdata(pdev); 2184 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2185 2186 ufshcd_pltfrm_remove(pdev); 2187 if (host->esi_enabled) 2188 platform_device_msi_free_irqs_all(hba->dev); 2189 } 2190 2191 static const struct ufs_qcom_drvdata ufs_qcom_sm8550_drvdata = { 2192 .quirks = UFSHCD_QUIRK_BROKEN_LSDBS_CAP, 2193 .no_phy_retention = true, 2194 }; 2195 2196 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 2197 { .compatible = "qcom,ufshc" }, 2198 { .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata }, 2199 { .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata }, 2200 {}, 2201 }; 2202 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 2203 2204 #ifdef CONFIG_ACPI 2205 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 2206 { "QCOM24A5" }, 2207 { }, 2208 }; 2209 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 2210 #endif 2211 2212 static const struct dev_pm_ops ufs_qcom_pm_ops = { 2213 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 2214 .prepare = ufshcd_suspend_prepare, 2215 .complete = ufshcd_resume_complete, 2216 #ifdef CONFIG_PM_SLEEP 2217 .suspend = ufshcd_system_suspend, 2218 .resume = ufshcd_system_resume, 2219 .freeze = ufshcd_system_freeze, 2220 .restore = ufshcd_system_restore, 2221 .thaw = ufshcd_system_thaw, 2222 #endif 2223 }; 2224 2225 static struct platform_driver ufs_qcom_pltform = { 2226 .probe = ufs_qcom_probe, 2227 .remove = ufs_qcom_remove, 2228 .driver = { 2229 .name = "ufshcd-qcom", 2230 .pm = &ufs_qcom_pm_ops, 2231 .of_match_table = of_match_ptr(ufs_qcom_of_match), 2232 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 2233 }, 2234 }; 2235 module_platform_driver(ufs_qcom_pltform); 2236 2237 MODULE_DESCRIPTION("Qualcomm UFS host controller driver"); 2238 MODULE_LICENSE("GPL v2"); 2239