1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/time.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/interconnect.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/phy/phy.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/reset-controller.h> 17 #include <linux/devfreq.h> 18 19 #include <soc/qcom/ice.h> 20 21 #include <ufs/ufshcd.h> 22 #include "ufshcd-pltfrm.h" 23 #include <ufs/unipro.h> 24 #include "ufs-qcom.h" 25 #include <ufs/ufshci.h> 26 #include <ufs/ufs_quirks.h> 27 28 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 29 #define MCQ_QCFGPTR_UNIT 0x200 30 #define MCQ_SQATTR_OFFSET(c) \ 31 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 32 #define MCQ_QCFG_SIZE 0x40 33 34 enum { 35 TSTBUS_UAWM, 36 TSTBUS_UARM, 37 TSTBUS_TXUC, 38 TSTBUS_RXUC, 39 TSTBUS_DFC, 40 TSTBUS_TRLUT, 41 TSTBUS_TMRLUT, 42 TSTBUS_OCSC, 43 TSTBUS_UTP_HCI, 44 TSTBUS_COMBINED, 45 TSTBUS_WRAPPER, 46 TSTBUS_UNIPRO, 47 TSTBUS_MAX, 48 }; 49 50 #define QCOM_UFS_MAX_GEAR 4 51 #define QCOM_UFS_MAX_LANE 2 52 53 enum { 54 MODE_MIN, 55 MODE_PWM, 56 MODE_HS_RA, 57 MODE_HS_RB, 58 MODE_MAX, 59 }; 60 61 static const struct __ufs_qcom_bw_table { 62 u32 mem_bw; 63 u32 cfg_bw; 64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 65 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 66 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 67 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 68 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 69 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 70 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 71 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 72 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 73 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 74 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 75 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 76 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 77 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 78 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 79 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 80 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 81 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 82 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 83 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 84 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 85 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 86 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 87 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 88 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 89 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 90 [MODE_MAX][0][0] = { 7643136, 307200 }, 91 }; 92 93 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; 94 95 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 96 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up); 97 98 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 99 { 100 return container_of(rcd, struct ufs_qcom_host, rcdev); 101 } 102 103 #ifdef CONFIG_SCSI_UFS_CRYPTO 104 105 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 106 { 107 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 108 qcom_ice_enable(host->ice); 109 } 110 111 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 112 { 113 struct ufs_hba *hba = host->hba; 114 struct device *dev = hba->dev; 115 struct qcom_ice *ice; 116 117 ice = of_qcom_ice_get(dev); 118 if (ice == ERR_PTR(-EOPNOTSUPP)) { 119 dev_warn(dev, "Disabling inline encryption support\n"); 120 ice = NULL; 121 } 122 123 if (IS_ERR_OR_NULL(ice)) 124 return PTR_ERR_OR_ZERO(ice); 125 126 host->ice = ice; 127 hba->caps |= UFSHCD_CAP_CRYPTO; 128 129 return 0; 130 } 131 132 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 133 { 134 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 135 return qcom_ice_resume(host->ice); 136 137 return 0; 138 } 139 140 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 141 { 142 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 143 return qcom_ice_suspend(host->ice); 144 145 return 0; 146 } 147 148 static int ufs_qcom_ice_program_key(struct ufs_hba *hba, 149 const union ufs_crypto_cfg_entry *cfg, 150 int slot) 151 { 152 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 153 union ufs_crypto_cap_entry cap; 154 bool config_enable = 155 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; 156 157 /* Only AES-256-XTS has been tested so far. */ 158 cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; 159 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || 160 cap.key_size != UFS_CRYPTO_KEY_SIZE_256) 161 return -EINVAL; 162 163 if (config_enable) 164 return qcom_ice_program_key(host->ice, 165 QCOM_ICE_CRYPTO_ALG_AES_XTS, 166 QCOM_ICE_CRYPTO_KEY_SIZE_256, 167 cfg->crypto_key, 168 cfg->data_unit_size, slot); 169 else 170 return qcom_ice_evict_key(host->ice, slot); 171 } 172 173 #else 174 175 #define ufs_qcom_ice_program_key NULL 176 177 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 178 { 179 } 180 181 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 182 { 183 return 0; 184 } 185 186 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 187 { 188 return 0; 189 } 190 191 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 192 { 193 return 0; 194 } 195 #endif 196 197 static int ufs_qcom_host_clk_get(struct device *dev, 198 const char *name, struct clk **clk_out, bool optional) 199 { 200 struct clk *clk; 201 int err = 0; 202 203 clk = devm_clk_get(dev, name); 204 if (!IS_ERR(clk)) { 205 *clk_out = clk; 206 return 0; 207 } 208 209 err = PTR_ERR(clk); 210 211 if (optional && err == -ENOENT) { 212 *clk_out = NULL; 213 return 0; 214 } 215 216 if (err != -EPROBE_DEFER) 217 dev_err(dev, "failed to get %s err %d\n", name, err); 218 219 return err; 220 } 221 222 static int ufs_qcom_host_clk_enable(struct device *dev, 223 const char *name, struct clk *clk) 224 { 225 int err = 0; 226 227 err = clk_prepare_enable(clk); 228 if (err) 229 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err); 230 231 return err; 232 } 233 234 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 235 { 236 if (!host->is_lane_clks_enabled) 237 return; 238 239 clk_disable_unprepare(host->tx_l1_sync_clk); 240 clk_disable_unprepare(host->tx_l0_sync_clk); 241 clk_disable_unprepare(host->rx_l1_sync_clk); 242 clk_disable_unprepare(host->rx_l0_sync_clk); 243 244 host->is_lane_clks_enabled = false; 245 } 246 247 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 248 { 249 int err; 250 struct device *dev = host->hba->dev; 251 252 if (host->is_lane_clks_enabled) 253 return 0; 254 255 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", 256 host->rx_l0_sync_clk); 257 if (err) 258 return err; 259 260 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", 261 host->tx_l0_sync_clk); 262 if (err) 263 goto disable_rx_l0; 264 265 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk", 266 host->rx_l1_sync_clk); 267 if (err) 268 goto disable_tx_l0; 269 270 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk", 271 host->tx_l1_sync_clk); 272 if (err) 273 goto disable_rx_l1; 274 275 host->is_lane_clks_enabled = true; 276 277 return 0; 278 279 disable_rx_l1: 280 clk_disable_unprepare(host->rx_l1_sync_clk); 281 disable_tx_l0: 282 clk_disable_unprepare(host->tx_l0_sync_clk); 283 disable_rx_l0: 284 clk_disable_unprepare(host->rx_l0_sync_clk); 285 286 return err; 287 } 288 289 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 290 { 291 int err = 0; 292 struct device *dev = host->hba->dev; 293 294 if (has_acpi_companion(dev)) 295 return 0; 296 297 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", 298 &host->rx_l0_sync_clk, false); 299 if (err) 300 return err; 301 302 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", 303 &host->tx_l0_sync_clk, false); 304 if (err) 305 return err; 306 307 /* In case of single lane per direction, don't read lane1 clocks */ 308 if (host->hba->lanes_per_direction > 1) { 309 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", 310 &host->rx_l1_sync_clk, false); 311 if (err) 312 return err; 313 314 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", 315 &host->tx_l1_sync_clk, true); 316 } 317 318 return 0; 319 } 320 321 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 322 { 323 int err; 324 u32 tx_fsm_val = 0; 325 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 326 327 do { 328 err = ufshcd_dme_get(hba, 329 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 330 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 331 &tx_fsm_val); 332 if (err || tx_fsm_val == TX_FSM_HIBERN8) 333 break; 334 335 /* sleep for max. 200us */ 336 usleep_range(100, 200); 337 } while (time_before(jiffies, timeout)); 338 339 /* 340 * we might have scheduled out for long during polling so 341 * check the state again. 342 */ 343 if (time_after(jiffies, timeout)) 344 err = ufshcd_dme_get(hba, 345 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 346 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 347 &tx_fsm_val); 348 349 if (err) { 350 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 351 __func__, err); 352 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 353 err = tx_fsm_val; 354 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 355 __func__, err); 356 } 357 358 return err; 359 } 360 361 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 362 { 363 ufshcd_rmwl(host->hba, QUNIPRO_SEL, 364 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0, 365 REG_UFS_CFG1); 366 367 if (host->hw_ver.major >= 0x05) 368 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 369 370 /* make sure above configuration is applied before we return */ 371 mb(); 372 } 373 374 /* 375 * ufs_qcom_host_reset - reset host controller and PHY 376 */ 377 static int ufs_qcom_host_reset(struct ufs_hba *hba) 378 { 379 int ret = 0; 380 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 381 bool reenable_intr = false; 382 383 if (!host->core_reset) { 384 dev_warn(hba->dev, "%s: reset control not set\n", __func__); 385 return 0; 386 } 387 388 reenable_intr = hba->is_irq_enabled; 389 disable_irq(hba->irq); 390 hba->is_irq_enabled = false; 391 392 ret = reset_control_assert(host->core_reset); 393 if (ret) { 394 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 395 __func__, ret); 396 return ret; 397 } 398 399 /* 400 * The hardware requirement for delay between assert/deassert 401 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 402 * ~125us (4/32768). To be on the safe side add 200us delay. 403 */ 404 usleep_range(200, 210); 405 406 ret = reset_control_deassert(host->core_reset); 407 if (ret) 408 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 409 __func__, ret); 410 411 usleep_range(1000, 1100); 412 413 if (reenable_intr) { 414 enable_irq(hba->irq); 415 hba->is_irq_enabled = true; 416 } 417 418 return 0; 419 } 420 421 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 422 { 423 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 424 425 if (host->hw_ver.major == 0x1) { 426 /* 427 * HS-G3 operations may not reliably work on legacy QCOM 428 * UFS host controller hardware even though capability 429 * exchange during link startup phase may end up 430 * negotiating maximum supported gear as G3. 431 * Hence downgrade the maximum supported gear to HS-G2. 432 */ 433 return UFS_HS_G2; 434 } else if (host->hw_ver.major >= 0x4) { 435 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 436 } 437 438 /* Default is HS-G3 */ 439 return UFS_HS_G3; 440 } 441 442 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 443 { 444 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 445 struct phy *phy = host->generic_phy; 446 int ret; 447 448 /* Reset UFS Host Controller and PHY */ 449 ret = ufs_qcom_host_reset(hba); 450 if (ret) 451 dev_warn(hba->dev, "%s: host reset returned %d\n", 452 __func__, ret); 453 454 /* phy initialization - calibrate the phy */ 455 ret = phy_init(phy); 456 if (ret) { 457 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 458 __func__, ret); 459 return ret; 460 } 461 462 phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear); 463 464 /* power on phy - start serdes and phy's power and clocks */ 465 ret = phy_power_on(phy); 466 if (ret) { 467 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 468 __func__, ret); 469 goto out_disable_phy; 470 } 471 472 ufs_qcom_select_unipro_mode(host); 473 474 return 0; 475 476 out_disable_phy: 477 phy_exit(phy); 478 479 return ret; 480 } 481 482 /* 483 * The UTP controller has a number of internal clock gating cells (CGCs). 484 * Internal hardware sub-modules within the UTP controller control the CGCs. 485 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 486 * in a specific operation, UTP controller CGCs are by default disabled and 487 * this function enables them (after every UFS link startup) to save some power 488 * leakage. 489 */ 490 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 491 { 492 ufshcd_writel(hba, 493 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL, 494 REG_UFS_CFG2); 495 496 /* Ensure that HW clock gating is enabled before next operations */ 497 mb(); 498 } 499 500 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 501 enum ufs_notify_change_status status) 502 { 503 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 504 int err = 0; 505 506 switch (status) { 507 case PRE_CHANGE: 508 ufs_qcom_power_up_sequence(hba); 509 /* 510 * The PHY PLL output is the source of tx/rx lane symbol 511 * clocks, hence, enable the lane clocks only after PHY 512 * is initialized. 513 */ 514 err = ufs_qcom_enable_lane_clks(host); 515 break; 516 case POST_CHANGE: 517 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 518 err = ufs_qcom_check_hibern8(hba); 519 ufs_qcom_enable_hw_clk_gating(hba); 520 ufs_qcom_ice_enable(host); 521 break; 522 default: 523 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 524 err = -EINVAL; 525 break; 526 } 527 return err; 528 } 529 530 /** 531 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers 532 * 533 * @hba: host controller instance 534 * @gear: Current operating gear 535 * @hs: current power mode 536 * @rate: current operating rate (A or B) 537 * @update_link_startup_timer: indicate if link_start ongoing 538 * @is_pre_scale_up: flag to check if pre scale up condition. 539 * Return: zero for success and non-zero in case of a failure. 540 */ 541 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, 542 u32 hs, u32 rate, bool update_link_startup_timer, 543 bool is_pre_scale_up) 544 { 545 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 546 struct ufs_clk_info *clki; 547 u32 core_clk_period_in_ns; 548 u32 tx_clk_cycles_per_us = 0; 549 unsigned long core_clk_rate = 0; 550 u32 core_clk_cycles_per_us = 0; 551 552 static u32 pwm_fr_table[][2] = { 553 {UFS_PWM_G1, 0x1}, 554 {UFS_PWM_G2, 0x1}, 555 {UFS_PWM_G3, 0x1}, 556 {UFS_PWM_G4, 0x1}, 557 }; 558 559 static u32 hs_fr_table_rA[][2] = { 560 {UFS_HS_G1, 0x1F}, 561 {UFS_HS_G2, 0x3e}, 562 {UFS_HS_G3, 0x7D}, 563 }; 564 565 static u32 hs_fr_table_rB[][2] = { 566 {UFS_HS_G1, 0x24}, 567 {UFS_HS_G2, 0x49}, 568 {UFS_HS_G3, 0x92}, 569 }; 570 571 /* 572 * The Qunipro controller does not use following registers: 573 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG & 574 * UFS_REG_PA_LINK_STARTUP_TIMER. 575 * However UTP controller uses SYS1CLK_1US_REG register for Interrupt 576 * Aggregation logic. 577 * It is mandatory to write SYS1CLK_1US_REG register on UFS host 578 * controller V4.0.0 onwards. 579 */ 580 if (host->hw_ver.major < 4 && ufs_qcom_cap_qunipro(host) && 581 !ufshcd_is_intr_aggr_allowed(hba)) 582 return 0; 583 584 if (gear == 0) { 585 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); 586 return -EINVAL; 587 } 588 589 list_for_each_entry(clki, &hba->clk_list_head, list) { 590 if (!strcmp(clki->name, "core_clk")) { 591 if (is_pre_scale_up) 592 core_clk_rate = clki->max_freq; 593 else 594 core_clk_rate = clk_get_rate(clki->clk); 595 break; 596 } 597 598 } 599 600 /* If frequency is smaller than 1MHz, set to 1MHz */ 601 if (core_clk_rate < DEFAULT_CLK_RATE_HZ) 602 core_clk_rate = DEFAULT_CLK_RATE_HZ; 603 604 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; 605 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 606 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 607 /* 608 * make sure above write gets applied before we return from 609 * this function. 610 */ 611 mb(); 612 } 613 614 if (ufs_qcom_cap_qunipro(host)) 615 return 0; 616 617 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate; 618 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG; 619 core_clk_period_in_ns &= MASK_CLK_NS_REG; 620 621 switch (hs) { 622 case FASTAUTO_MODE: 623 case FAST_MODE: 624 if (rate == PA_HS_MODE_A) { 625 if (gear > ARRAY_SIZE(hs_fr_table_rA)) { 626 dev_err(hba->dev, 627 "%s: index %d exceeds table size %zu\n", 628 __func__, gear, 629 ARRAY_SIZE(hs_fr_table_rA)); 630 return -EINVAL; 631 } 632 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1]; 633 } else if (rate == PA_HS_MODE_B) { 634 if (gear > ARRAY_SIZE(hs_fr_table_rB)) { 635 dev_err(hba->dev, 636 "%s: index %d exceeds table size %zu\n", 637 __func__, gear, 638 ARRAY_SIZE(hs_fr_table_rB)); 639 return -EINVAL; 640 } 641 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1]; 642 } else { 643 dev_err(hba->dev, "%s: invalid rate = %d\n", 644 __func__, rate); 645 return -EINVAL; 646 } 647 break; 648 case SLOWAUTO_MODE: 649 case SLOW_MODE: 650 if (gear > ARRAY_SIZE(pwm_fr_table)) { 651 dev_err(hba->dev, 652 "%s: index %d exceeds table size %zu\n", 653 __func__, gear, 654 ARRAY_SIZE(pwm_fr_table)); 655 return -EINVAL; 656 } 657 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1]; 658 break; 659 case UNCHANGED: 660 default: 661 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs); 662 return -EINVAL; 663 } 664 665 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) != 666 (core_clk_period_in_ns | tx_clk_cycles_per_us)) { 667 /* this register 2 fields shall be written at once */ 668 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us, 669 REG_UFS_TX_SYMBOL_CLK_NS_US); 670 /* 671 * make sure above write gets applied before we return from 672 * this function. 673 */ 674 mb(); 675 } 676 677 if (update_link_startup_timer && host->hw_ver.major != 0x5) { 678 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), 679 REG_UFS_CFG0); 680 /* 681 * make sure that this configuration is applied before 682 * we return 683 */ 684 mb(); 685 } 686 687 return 0; 688 } 689 690 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 691 enum ufs_notify_change_status status) 692 { 693 int err = 0; 694 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 695 696 switch (status) { 697 case PRE_CHANGE: 698 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, 699 0, true, false)) { 700 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 701 __func__); 702 return -EINVAL; 703 } 704 705 if (ufs_qcom_cap_qunipro(host)) { 706 err = ufs_qcom_set_core_clk_ctrl(hba, true); 707 if (err) 708 dev_err(hba->dev, "cfg core clk ctrl failed\n"); 709 } 710 /* 711 * Some UFS devices (and may be host) have issues if LCC is 712 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 713 * before link startup which will make sure that both host 714 * and device TX LCC are disabled once link startup is 715 * completed. 716 */ 717 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41) 718 err = ufshcd_disable_host_tx_lcc(hba); 719 720 break; 721 default: 722 break; 723 } 724 725 return err; 726 } 727 728 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 729 { 730 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 731 732 /* reset gpio is optional */ 733 if (!host->device_reset) 734 return; 735 736 gpiod_set_value_cansleep(host->device_reset, asserted); 737 } 738 739 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 740 enum ufs_notify_change_status status) 741 { 742 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 743 struct phy *phy = host->generic_phy; 744 745 if (status == PRE_CHANGE) 746 return 0; 747 748 if (ufs_qcom_is_link_off(hba)) { 749 /* 750 * Disable the tx/rx lane symbol clocks before PHY is 751 * powered down as the PLL source should be disabled 752 * after downstream clocks are disabled. 753 */ 754 ufs_qcom_disable_lane_clks(host); 755 phy_power_off(phy); 756 757 /* reset the connected UFS device during power down */ 758 ufs_qcom_device_reset_ctrl(hba, true); 759 760 } else if (!ufs_qcom_is_link_active(hba)) { 761 ufs_qcom_disable_lane_clks(host); 762 } 763 764 return ufs_qcom_ice_suspend(host); 765 } 766 767 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 768 { 769 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 770 struct phy *phy = host->generic_phy; 771 int err; 772 773 if (ufs_qcom_is_link_off(hba)) { 774 err = phy_power_on(phy); 775 if (err) { 776 dev_err(hba->dev, "%s: failed PHY power on: %d\n", 777 __func__, err); 778 return err; 779 } 780 781 err = ufs_qcom_enable_lane_clks(host); 782 if (err) 783 return err; 784 785 } else if (!ufs_qcom_is_link_active(hba)) { 786 err = ufs_qcom_enable_lane_clks(host); 787 if (err) 788 return err; 789 } 790 791 return ufs_qcom_ice_resume(host); 792 } 793 794 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 795 { 796 if (host->dev_ref_clk_ctrl_mmio && 797 (enable ^ host->is_dev_ref_clk_enabled)) { 798 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 799 800 if (enable) 801 temp |= host->dev_ref_clk_en_mask; 802 else 803 temp &= ~host->dev_ref_clk_en_mask; 804 805 /* 806 * If we are here to disable this clock it might be immediately 807 * after entering into hibern8 in which case we need to make 808 * sure that device ref_clk is active for specific time after 809 * hibern8 enter. 810 */ 811 if (!enable) { 812 unsigned long gating_wait; 813 814 gating_wait = host->hba->dev_info.clk_gating_wait_us; 815 if (!gating_wait) { 816 udelay(1); 817 } else { 818 /* 819 * bRefClkGatingWaitTime defines the minimum 820 * time for which the reference clock is 821 * required by device during transition from 822 * HS-MODE to LS-MODE or HIBERN8 state. Give it 823 * more delay to be on the safe side. 824 */ 825 gating_wait += 10; 826 usleep_range(gating_wait, gating_wait + 10); 827 } 828 } 829 830 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 831 832 /* 833 * Make sure the write to ref_clk reaches the destination and 834 * not stored in a Write Buffer (WB). 835 */ 836 readl(host->dev_ref_clk_ctrl_mmio); 837 838 /* 839 * If we call hibern8 exit after this, we need to make sure that 840 * device ref_clk is stable for at least 1us before the hibern8 841 * exit command. 842 */ 843 if (enable) 844 udelay(1); 845 846 host->is_dev_ref_clk_enabled = enable; 847 } 848 } 849 850 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 851 { 852 struct device *dev = host->hba->dev; 853 int ret; 854 855 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 856 if (ret < 0) { 857 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 858 return ret; 859 } 860 861 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 862 if (ret < 0) { 863 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 864 return ret; 865 } 866 867 return 0; 868 } 869 870 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 871 { 872 struct ufs_pa_layer_attr *p = &host->dev_req_params; 873 int gear = max_t(u32, p->gear_rx, p->gear_tx); 874 int lane = max_t(u32, p->lane_rx, p->lane_tx); 875 876 if (ufshcd_is_hs_mode(p)) { 877 if (p->hs_rate == PA_HS_MODE_B) 878 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 879 else 880 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 881 } else { 882 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 883 } 884 } 885 886 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 887 { 888 struct __ufs_qcom_bw_table bw_table; 889 890 bw_table = ufs_qcom_get_bw_table(host); 891 892 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 893 } 894 895 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 896 enum ufs_notify_change_status status, 897 struct ufs_pa_layer_attr *dev_max_params, 898 struct ufs_pa_layer_attr *dev_req_params) 899 { 900 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 901 struct ufs_dev_params ufs_qcom_cap; 902 int ret = 0; 903 904 if (!dev_req_params) { 905 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 906 return -EINVAL; 907 } 908 909 switch (status) { 910 case PRE_CHANGE: 911 ufshcd_init_pwr_dev_param(&ufs_qcom_cap); 912 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE; 913 914 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 915 ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba); 916 917 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap, 918 dev_max_params, 919 dev_req_params); 920 if (ret) { 921 dev_err(hba->dev, "%s: failed to determine capabilities\n", 922 __func__); 923 return ret; 924 } 925 926 /* 927 * Update phy_gear only when the gears are scaled to a higher value. This is 928 * because, the PHY gear settings are backwards compatible and we only need to 929 * change the PHY gear settings while scaling to higher gears. 930 */ 931 if (dev_req_params->gear_tx > host->phy_gear) 932 host->phy_gear = dev_req_params->gear_tx; 933 934 /* enable the device ref clock before changing to HS mode */ 935 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 936 ufshcd_is_hs_mode(dev_req_params)) 937 ufs_qcom_dev_ref_clk_ctrl(host, true); 938 939 if (host->hw_ver.major >= 0x4) { 940 ufshcd_dme_configure_adapt(hba, 941 dev_req_params->gear_tx, 942 PA_INITIAL_ADAPT); 943 } 944 break; 945 case POST_CHANGE: 946 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, 947 dev_req_params->pwr_rx, 948 dev_req_params->hs_rate, false, false)) { 949 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 950 __func__); 951 /* 952 * we return error code at the end of the routine, 953 * but continue to configure UFS_PHY_TX_LANE_ENABLE 954 * and bus voting as usual 955 */ 956 ret = -EINVAL; 957 } 958 959 /* cache the power mode parameters to use internally */ 960 memcpy(&host->dev_req_params, 961 dev_req_params, sizeof(*dev_req_params)); 962 963 ufs_qcom_icc_update_bw(host); 964 965 /* disable the device ref clock if entered PWM mode */ 966 if (ufshcd_is_hs_mode(&hba->pwr_info) && 967 !ufshcd_is_hs_mode(dev_req_params)) 968 ufs_qcom_dev_ref_clk_ctrl(host, false); 969 break; 970 default: 971 ret = -EINVAL; 972 break; 973 } 974 975 return ret; 976 } 977 978 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 979 { 980 int err; 981 u32 pa_vs_config_reg1; 982 983 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 984 &pa_vs_config_reg1); 985 if (err) 986 return err; 987 988 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 989 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 990 (pa_vs_config_reg1 | (1 << 12))); 991 } 992 993 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 994 { 995 int err = 0; 996 997 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 998 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 999 1000 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) 1001 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; 1002 1003 return err; 1004 } 1005 1006 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 1007 { 1008 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1009 1010 if (host->hw_ver.major == 0x1) 1011 return ufshci_version(1, 1); 1012 else 1013 return ufshci_version(2, 0); 1014 } 1015 1016 /** 1017 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 1018 * @hba: host controller instance 1019 * 1020 * QCOM UFS host controller might have some non standard behaviours (quirks) 1021 * than what is specified by UFSHCI specification. Advertise all such 1022 * quirks to standard UFS host controller driver so standard takes them into 1023 * account. 1024 */ 1025 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 1026 { 1027 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1028 1029 if (host->hw_ver.major == 0x01) { 1030 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 1031 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP 1032 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE; 1033 1034 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001) 1035 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR; 1036 1037 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC; 1038 } 1039 1040 if (host->hw_ver.major == 0x2) { 1041 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 1042 1043 if (!ufs_qcom_cap_qunipro(host)) 1044 /* Legacy UniPro mode still need following quirks */ 1045 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 1046 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE 1047 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); 1048 } 1049 1050 if (host->hw_ver.major > 0x3) 1051 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1052 } 1053 1054 static void ufs_qcom_set_caps(struct ufs_hba *hba) 1055 { 1056 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1057 1058 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1059 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 1060 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1061 hba->caps |= UFSHCD_CAP_WB_EN; 1062 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 1063 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 1064 1065 if (host->hw_ver.major >= 0x2) { 1066 host->caps = UFS_QCOM_CAP_QUNIPRO | 1067 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE; 1068 } 1069 } 1070 1071 /** 1072 * ufs_qcom_setup_clocks - enables/disable clocks 1073 * @hba: host controller instance 1074 * @on: If true, enable clocks else disable them. 1075 * @status: PRE_CHANGE or POST_CHANGE notify 1076 * 1077 * Return: 0 on success, non-zero on failure. 1078 */ 1079 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 1080 enum ufs_notify_change_status status) 1081 { 1082 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1083 1084 /* 1085 * In case ufs_qcom_init() is not yet done, simply ignore. 1086 * This ufs_qcom_setup_clocks() shall be called from 1087 * ufs_qcom_init() after init is done. 1088 */ 1089 if (!host) 1090 return 0; 1091 1092 switch (status) { 1093 case PRE_CHANGE: 1094 if (on) { 1095 ufs_qcom_icc_update_bw(host); 1096 } else { 1097 if (!ufs_qcom_is_link_active(hba)) { 1098 /* disable device ref_clk */ 1099 ufs_qcom_dev_ref_clk_ctrl(host, false); 1100 } 1101 } 1102 break; 1103 case POST_CHANGE: 1104 if (on) { 1105 /* enable the device ref clock for HS mode*/ 1106 if (ufshcd_is_hs_mode(&hba->pwr_info)) 1107 ufs_qcom_dev_ref_clk_ctrl(host, true); 1108 } else { 1109 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 1110 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 1111 } 1112 break; 1113 } 1114 1115 return 0; 1116 } 1117 1118 static int 1119 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 1120 { 1121 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1122 1123 ufs_qcom_assert_reset(host->hba); 1124 /* provide 1ms delay to let the reset pulse propagate. */ 1125 usleep_range(1000, 1100); 1126 return 0; 1127 } 1128 1129 static int 1130 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 1131 { 1132 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1133 1134 ufs_qcom_deassert_reset(host->hba); 1135 1136 /* 1137 * after reset deassertion, phy will need all ref clocks, 1138 * voltage, current to settle down before starting serdes. 1139 */ 1140 usleep_range(1000, 1100); 1141 return 0; 1142 } 1143 1144 static const struct reset_control_ops ufs_qcom_reset_ops = { 1145 .assert = ufs_qcom_reset_assert, 1146 .deassert = ufs_qcom_reset_deassert, 1147 }; 1148 1149 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 1150 { 1151 struct device *dev = host->hba->dev; 1152 int ret; 1153 1154 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 1155 if (IS_ERR(host->icc_ddr)) 1156 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 1157 "failed to acquire interconnect path\n"); 1158 1159 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1160 if (IS_ERR(host->icc_cpu)) 1161 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1162 "failed to acquire interconnect path\n"); 1163 1164 /* 1165 * Set Maximum bandwidth vote before initializing the UFS controller and 1166 * device. Ideally, a minimal interconnect vote would suffice for the 1167 * initialization, but a max vote would allow faster initialization. 1168 */ 1169 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1170 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1171 if (ret < 0) 1172 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1173 1174 return 0; 1175 } 1176 1177 /** 1178 * ufs_qcom_init - bind phy with controller 1179 * @hba: host controller instance 1180 * 1181 * Binds PHY with controller and powers up PHY enabling clocks 1182 * and regulators. 1183 * 1184 * Return: -EPROBE_DEFER if binding fails, returns negative error 1185 * on phy power up failure and returns zero on success. 1186 */ 1187 static int ufs_qcom_init(struct ufs_hba *hba) 1188 { 1189 int err; 1190 struct device *dev = hba->dev; 1191 struct platform_device *pdev = to_platform_device(dev); 1192 struct ufs_qcom_host *host; 1193 struct resource *res; 1194 struct ufs_clk_info *clki; 1195 1196 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1197 if (!host) { 1198 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); 1199 return -ENOMEM; 1200 } 1201 1202 /* Make a two way bind between the qcom host and the hba */ 1203 host->hba = hba; 1204 ufshcd_set_variant(hba, host); 1205 1206 /* Setup the optional reset control of HCI */ 1207 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1208 if (IS_ERR(host->core_reset)) { 1209 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1210 "Failed to get reset control\n"); 1211 goto out_variant_clear; 1212 } 1213 1214 /* Fire up the reset controller. Failure here is non-fatal. */ 1215 host->rcdev.of_node = dev->of_node; 1216 host->rcdev.ops = &ufs_qcom_reset_ops; 1217 host->rcdev.owner = dev->driver->owner; 1218 host->rcdev.nr_resets = 1; 1219 err = devm_reset_controller_register(dev, &host->rcdev); 1220 if (err) 1221 dev_warn(dev, "Failed to register reset controller\n"); 1222 1223 if (!has_acpi_companion(dev)) { 1224 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1225 if (IS_ERR(host->generic_phy)) { 1226 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1227 goto out_variant_clear; 1228 } 1229 } 1230 1231 err = ufs_qcom_icc_init(host); 1232 if (err) 1233 goto out_variant_clear; 1234 1235 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1236 GPIOD_OUT_HIGH); 1237 if (IS_ERR(host->device_reset)) { 1238 err = PTR_ERR(host->device_reset); 1239 if (err != -EPROBE_DEFER) 1240 dev_err(dev, "failed to acquire reset gpio: %d\n", err); 1241 goto out_variant_clear; 1242 } 1243 1244 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1245 &host->hw_ver.minor, &host->hw_ver.step); 1246 1247 /* 1248 * for newer controllers, device reference clock control bit has 1249 * moved inside UFS controller register address space itself. 1250 */ 1251 if (host->hw_ver.major >= 0x02) { 1252 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1253 host->dev_ref_clk_en_mask = BIT(26); 1254 } else { 1255 /* "dev_ref_clk_ctrl_mem" is optional resource */ 1256 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1257 "dev_ref_clk_ctrl_mem"); 1258 if (res) { 1259 host->dev_ref_clk_ctrl_mmio = 1260 devm_ioremap_resource(dev, res); 1261 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) 1262 host->dev_ref_clk_ctrl_mmio = NULL; 1263 host->dev_ref_clk_en_mask = BIT(5); 1264 } 1265 } 1266 1267 list_for_each_entry(clki, &hba->clk_list_head, list) { 1268 if (!strcmp(clki->name, "core_clk_unipro")) 1269 clki->keep_link_active = true; 1270 } 1271 1272 err = ufs_qcom_init_lane_clks(host); 1273 if (err) 1274 goto out_variant_clear; 1275 1276 ufs_qcom_set_caps(hba); 1277 ufs_qcom_advertise_quirks(hba); 1278 1279 err = ufs_qcom_ice_init(host); 1280 if (err) 1281 goto out_variant_clear; 1282 1283 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1284 1285 if (hba->dev->id < MAX_UFS_QCOM_HOSTS) 1286 ufs_qcom_hosts[hba->dev->id] = host; 1287 1288 ufs_qcom_get_default_testbus_cfg(host); 1289 err = ufs_qcom_testbus_config(host); 1290 if (err) 1291 /* Failure is non-fatal */ 1292 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1293 __func__, err); 1294 1295 /* 1296 * Power up the PHY using the minimum supported gear (UFS_HS_G2). 1297 * Switching to max gear will be performed during reinit if supported. 1298 */ 1299 host->phy_gear = UFS_HS_G2; 1300 1301 return 0; 1302 1303 out_variant_clear: 1304 ufshcd_set_variant(hba, NULL); 1305 1306 return err; 1307 } 1308 1309 static void ufs_qcom_exit(struct ufs_hba *hba) 1310 { 1311 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1312 1313 ufs_qcom_disable_lane_clks(host); 1314 phy_power_off(host->generic_phy); 1315 phy_exit(host->generic_phy); 1316 } 1317 1318 /** 1319 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles 1320 * 1321 * @hba: host controller instance 1322 * @cycles_in_1us: No of cycles in 1us to be configured 1323 * 1324 * Returns error if dme get/set configuration for 40ns fails 1325 * and returns zero on success. 1326 */ 1327 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, 1328 u32 cycles_in_1us) 1329 { 1330 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1331 u32 cycles_in_40ns; 1332 u32 reg; 1333 int err; 1334 1335 /* 1336 * UFS host controller V4.0.0 onwards needs to program 1337 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed 1338 * frequency of unipro core clk of UFS host controller. 1339 */ 1340 if (host->hw_ver.major < 4) 1341 return 0; 1342 1343 /* 1344 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not 1345 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will 1346 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware 1347 * specification expect to be 16. Hence use exact hardware spec 1348 * mandated value for cycles_in_40ns instead of calculating using 1349 * generic formulae. 1350 */ 1351 switch (cycles_in_1us) { 1352 case UNIPRO_CORE_CLK_FREQ_403_MHZ: 1353 cycles_in_40ns = 16; 1354 break; 1355 case UNIPRO_CORE_CLK_FREQ_300_MHZ: 1356 cycles_in_40ns = 12; 1357 break; 1358 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ: 1359 cycles_in_40ns = 8; 1360 break; 1361 case UNIPRO_CORE_CLK_FREQ_150_MHZ: 1362 cycles_in_40ns = 6; 1363 break; 1364 case UNIPRO_CORE_CLK_FREQ_100_MHZ: 1365 cycles_in_40ns = 4; 1366 break; 1367 case UNIPRO_CORE_CLK_FREQ_75_MHZ: 1368 cycles_in_40ns = 3; 1369 break; 1370 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ: 1371 cycles_in_40ns = 2; 1372 break; 1373 default: 1374 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", 1375 cycles_in_1us); 1376 return -EINVAL; 1377 } 1378 1379 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); 1380 if (err) 1381 return err; 1382 1383 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; 1384 reg |= cycles_in_40ns; 1385 1386 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); 1387 } 1388 1389 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) 1390 { 1391 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1392 struct list_head *head = &hba->clk_list_head; 1393 struct ufs_clk_info *clki; 1394 u32 cycles_in_1us; 1395 u32 core_clk_ctrl_reg; 1396 int err; 1397 1398 list_for_each_entry(clki, head, list) { 1399 if (!IS_ERR_OR_NULL(clki->clk) && 1400 !strcmp(clki->name, "core_clk_unipro")) { 1401 if (is_scale_up) 1402 cycles_in_1us = ceil(clki->max_freq, (1000 * 1000)); 1403 else 1404 cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000)); 1405 break; 1406 } 1407 } 1408 1409 err = ufshcd_dme_get(hba, 1410 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1411 &core_clk_ctrl_reg); 1412 if (err) 1413 return err; 1414 1415 /* Bit mask is different for UFS host controller V4.0.0 onwards */ 1416 if (host->hw_ver.major >= 4) { 1417 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us)) 1418 return -ERANGE; 1419 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4; 1420 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us); 1421 } else { 1422 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us)) 1423 return -ERANGE; 1424 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK; 1425 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); 1426 } 1427 1428 /* Clear CORE_CLK_DIV_EN */ 1429 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1430 1431 err = ufshcd_dme_set(hba, 1432 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1433 core_clk_ctrl_reg); 1434 if (err) 1435 return err; 1436 1437 /* Configure unipro core clk 40ns attribute */ 1438 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); 1439 } 1440 1441 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) 1442 { 1443 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1444 struct ufs_pa_layer_attr *attr = &host->dev_req_params; 1445 int ret; 1446 1447 if (!ufs_qcom_cap_qunipro(host)) 1448 return 0; 1449 1450 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx, 1451 attr->hs_rate, false, true); 1452 if (ret) { 1453 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); 1454 return ret; 1455 } 1456 /* set unipro core clock attributes and clear clock divider */ 1457 return ufs_qcom_set_core_clk_ctrl(hba, true); 1458 } 1459 1460 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1461 { 1462 return 0; 1463 } 1464 1465 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1466 { 1467 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1468 int err; 1469 u32 core_clk_ctrl_reg; 1470 1471 if (!ufs_qcom_cap_qunipro(host)) 1472 return 0; 1473 1474 err = ufshcd_dme_get(hba, 1475 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1476 &core_clk_ctrl_reg); 1477 1478 /* make sure CORE_CLK_DIV_EN is cleared */ 1479 if (!err && 1480 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1481 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1482 err = ufshcd_dme_set(hba, 1483 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1484 core_clk_ctrl_reg); 1485 } 1486 1487 return err; 1488 } 1489 1490 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) 1491 { 1492 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1493 1494 if (!ufs_qcom_cap_qunipro(host)) 1495 return 0; 1496 1497 /* set unipro core clock attributes and clear clock divider */ 1498 return ufs_qcom_set_core_clk_ctrl(hba, false); 1499 } 1500 1501 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, 1502 bool scale_up, enum ufs_notify_change_status status) 1503 { 1504 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1505 int err = 0; 1506 1507 /* check the host controller state before sending hibern8 cmd */ 1508 if (!ufshcd_is_hba_active(hba)) 1509 return 0; 1510 1511 if (status == PRE_CHANGE) { 1512 err = ufshcd_uic_hibern8_enter(hba); 1513 if (err) 1514 return err; 1515 if (scale_up) 1516 err = ufs_qcom_clk_scale_up_pre_change(hba); 1517 else 1518 err = ufs_qcom_clk_scale_down_pre_change(hba); 1519 if (err) 1520 ufshcd_uic_hibern8_exit(hba); 1521 1522 } else { 1523 if (scale_up) 1524 err = ufs_qcom_clk_scale_up_post_change(hba); 1525 else 1526 err = ufs_qcom_clk_scale_down_post_change(hba); 1527 1528 1529 if (err) { 1530 ufshcd_uic_hibern8_exit(hba); 1531 return err; 1532 } 1533 1534 ufs_qcom_icc_update_bw(host); 1535 ufshcd_uic_hibern8_exit(hba); 1536 } 1537 1538 return 0; 1539 } 1540 1541 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1542 { 1543 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1544 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1545 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1546 } 1547 1548 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1549 { 1550 /* provide a legal default configuration */ 1551 host->testbus.select_major = TSTBUS_UNIPRO; 1552 host->testbus.select_minor = 37; 1553 } 1554 1555 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1556 { 1557 if (host->testbus.select_major >= TSTBUS_MAX) { 1558 dev_err(host->hba->dev, 1559 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1560 __func__, host->testbus.select_major); 1561 return false; 1562 } 1563 1564 return true; 1565 } 1566 1567 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1568 { 1569 int reg; 1570 int offset; 1571 u32 mask = TEST_BUS_SUB_SEL_MASK; 1572 1573 if (!host) 1574 return -EINVAL; 1575 1576 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1577 return -EPERM; 1578 1579 switch (host->testbus.select_major) { 1580 case TSTBUS_UAWM: 1581 reg = UFS_TEST_BUS_CTRL_0; 1582 offset = 24; 1583 break; 1584 case TSTBUS_UARM: 1585 reg = UFS_TEST_BUS_CTRL_0; 1586 offset = 16; 1587 break; 1588 case TSTBUS_TXUC: 1589 reg = UFS_TEST_BUS_CTRL_0; 1590 offset = 8; 1591 break; 1592 case TSTBUS_RXUC: 1593 reg = UFS_TEST_BUS_CTRL_0; 1594 offset = 0; 1595 break; 1596 case TSTBUS_DFC: 1597 reg = UFS_TEST_BUS_CTRL_1; 1598 offset = 24; 1599 break; 1600 case TSTBUS_TRLUT: 1601 reg = UFS_TEST_BUS_CTRL_1; 1602 offset = 16; 1603 break; 1604 case TSTBUS_TMRLUT: 1605 reg = UFS_TEST_BUS_CTRL_1; 1606 offset = 8; 1607 break; 1608 case TSTBUS_OCSC: 1609 reg = UFS_TEST_BUS_CTRL_1; 1610 offset = 0; 1611 break; 1612 case TSTBUS_WRAPPER: 1613 reg = UFS_TEST_BUS_CTRL_2; 1614 offset = 16; 1615 break; 1616 case TSTBUS_COMBINED: 1617 reg = UFS_TEST_BUS_CTRL_2; 1618 offset = 8; 1619 break; 1620 case TSTBUS_UTP_HCI: 1621 reg = UFS_TEST_BUS_CTRL_2; 1622 offset = 0; 1623 break; 1624 case TSTBUS_UNIPRO: 1625 reg = UFS_UNIPRO_CFG; 1626 offset = 20; 1627 mask = 0xFFF; 1628 break; 1629 /* 1630 * No need for a default case, since 1631 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 1632 * is legal 1633 */ 1634 } 1635 mask <<= offset; 1636 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 1637 (u32)host->testbus.select_major << 19, 1638 REG_UFS_CFG1); 1639 ufshcd_rmwl(host->hba, mask, 1640 (u32)host->testbus.select_minor << offset, 1641 reg); 1642 ufs_qcom_enable_test_bus(host); 1643 /* 1644 * Make sure the test bus configuration is 1645 * committed before returning. 1646 */ 1647 mb(); 1648 1649 return 0; 1650 } 1651 1652 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 1653 { 1654 u32 reg; 1655 struct ufs_qcom_host *host; 1656 1657 host = ufshcd_get_variant(hba); 1658 1659 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 1660 "HCI Vendor Specific Registers "); 1661 1662 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 1663 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 1664 1665 reg = ufshcd_readl(hba, REG_UFS_CFG1); 1666 reg |= UTP_DBG_RAMS_EN; 1667 ufshcd_writel(hba, reg, REG_UFS_CFG1); 1668 1669 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 1670 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 1671 1672 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 1673 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 1674 1675 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 1676 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 1677 1678 /* clear bit 17 - UTP_DBG_RAMS_EN */ 1679 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 1680 1681 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 1682 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 1683 1684 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 1685 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 1686 1687 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 1688 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 1689 1690 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 1691 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 1692 1693 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 1694 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 1695 1696 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 1697 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 1698 1699 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 1700 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 1701 } 1702 1703 /** 1704 * ufs_qcom_device_reset() - toggle the (optional) device reset line 1705 * @hba: per-adapter instance 1706 * 1707 * Toggles the (optional) reset line to reset the attached device. 1708 */ 1709 static int ufs_qcom_device_reset(struct ufs_hba *hba) 1710 { 1711 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1712 1713 /* reset gpio is optional */ 1714 if (!host->device_reset) 1715 return -EOPNOTSUPP; 1716 1717 /* 1718 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 1719 * be on the safe side. 1720 */ 1721 ufs_qcom_device_reset_ctrl(hba, true); 1722 usleep_range(10, 15); 1723 1724 ufs_qcom_device_reset_ctrl(hba, false); 1725 usleep_range(10, 15); 1726 1727 return 0; 1728 } 1729 1730 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) 1731 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1732 struct devfreq_dev_profile *p, 1733 struct devfreq_simple_ondemand_data *d) 1734 { 1735 p->polling_ms = 60; 1736 p->timer = DEVFREQ_TIMER_DELAYED; 1737 d->upthreshold = 70; 1738 d->downdifferential = 5; 1739 } 1740 #else 1741 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1742 struct devfreq_dev_profile *p, 1743 struct devfreq_simple_ondemand_data *data) 1744 { 1745 } 1746 #endif 1747 1748 static void ufs_qcom_reinit_notify(struct ufs_hba *hba) 1749 { 1750 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1751 1752 phy_power_off(host->generic_phy); 1753 } 1754 1755 /* Resources */ 1756 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { 1757 {.name = "ufs_mem",}, 1758 {.name = "mcq",}, 1759 /* Submission Queue DAO */ 1760 {.name = "mcq_sqd",}, 1761 /* Submission Queue Interrupt Status */ 1762 {.name = "mcq_sqis",}, 1763 /* Completion Queue DAO */ 1764 {.name = "mcq_cqd",}, 1765 /* Completion Queue Interrupt Status */ 1766 {.name = "mcq_cqis",}, 1767 /* MCQ vendor specific */ 1768 {.name = "mcq_vs",}, 1769 }; 1770 1771 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 1772 { 1773 struct platform_device *pdev = to_platform_device(hba->dev); 1774 struct ufshcd_res_info *res; 1775 struct resource *res_mem, *res_mcq; 1776 int i, ret = 0; 1777 1778 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); 1779 1780 for (i = 0; i < RES_MAX; i++) { 1781 res = &hba->res[i]; 1782 res->resource = platform_get_resource_byname(pdev, 1783 IORESOURCE_MEM, 1784 res->name); 1785 if (!res->resource) { 1786 dev_info(hba->dev, "Resource %s not provided\n", res->name); 1787 if (i == RES_UFS) 1788 return -ENOMEM; 1789 continue; 1790 } else if (i == RES_UFS) { 1791 res_mem = res->resource; 1792 res->base = hba->mmio_base; 1793 continue; 1794 } 1795 1796 res->base = devm_ioremap_resource(hba->dev, res->resource); 1797 if (IS_ERR(res->base)) { 1798 dev_err(hba->dev, "Failed to map res %s, err=%d\n", 1799 res->name, (int)PTR_ERR(res->base)); 1800 ret = PTR_ERR(res->base); 1801 res->base = NULL; 1802 return ret; 1803 } 1804 } 1805 1806 /* MCQ resource provided in DT */ 1807 res = &hba->res[RES_MCQ]; 1808 /* Bail if MCQ resource is provided */ 1809 if (res->base) 1810 goto out; 1811 1812 /* Explicitly allocate MCQ resource from ufs_mem */ 1813 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); 1814 if (!res_mcq) 1815 return -ENOMEM; 1816 1817 res_mcq->start = res_mem->start + 1818 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); 1819 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; 1820 res_mcq->flags = res_mem->flags; 1821 res_mcq->name = "mcq"; 1822 1823 ret = insert_resource(&iomem_resource, res_mcq); 1824 if (ret) { 1825 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", 1826 ret); 1827 return ret; 1828 } 1829 1830 res->base = devm_ioremap_resource(hba->dev, res_mcq); 1831 if (IS_ERR(res->base)) { 1832 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", 1833 (int)PTR_ERR(res->base)); 1834 ret = PTR_ERR(res->base); 1835 goto ioremap_err; 1836 } 1837 1838 out: 1839 hba->mcq_base = res->base; 1840 return 0; 1841 ioremap_err: 1842 res->base = NULL; 1843 remove_resource(res_mcq); 1844 return ret; 1845 } 1846 1847 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 1848 { 1849 struct ufshcd_res_info *mem_res, *sqdao_res; 1850 struct ufshcd_mcq_opr_info_t *opr; 1851 int i; 1852 1853 mem_res = &hba->res[RES_UFS]; 1854 sqdao_res = &hba->res[RES_MCQ_SQD]; 1855 1856 if (!mem_res->base || !sqdao_res->base) 1857 return -EINVAL; 1858 1859 for (i = 0; i < OPR_MAX; i++) { 1860 opr = &hba->mcq_opr[i]; 1861 opr->offset = sqdao_res->resource->start - 1862 mem_res->resource->start + 0x40 * i; 1863 opr->stride = 0x100; 1864 opr->base = sqdao_res->base + 0x40 * i; 1865 } 1866 1867 return 0; 1868 } 1869 1870 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 1871 { 1872 /* Qualcomm HC supports up to 64 */ 1873 return MAX_SUPP_MAC; 1874 } 1875 1876 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 1877 unsigned long *ocqs) 1878 { 1879 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; 1880 1881 if (!mcq_vs_res->base) 1882 return -EINVAL; 1883 1884 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); 1885 1886 return 0; 1887 } 1888 1889 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 1890 { 1891 struct device *dev = msi_desc_to_dev(desc); 1892 struct ufs_hba *hba = dev_get_drvdata(dev); 1893 1894 ufshcd_mcq_config_esi(hba, msg); 1895 } 1896 1897 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 1898 { 1899 struct msi_desc *desc = data; 1900 struct device *dev = msi_desc_to_dev(desc); 1901 struct ufs_hba *hba = dev_get_drvdata(dev); 1902 u32 id = desc->msi_index; 1903 struct ufs_hw_queue *hwq = &hba->uhq[id]; 1904 1905 ufshcd_mcq_write_cqis(hba, 0x1, id); 1906 ufshcd_mcq_poll_cqe_lock(hba, hwq); 1907 1908 return IRQ_HANDLED; 1909 } 1910 1911 static int ufs_qcom_config_esi(struct ufs_hba *hba) 1912 { 1913 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1914 struct msi_desc *desc; 1915 struct msi_desc *failed_desc = NULL; 1916 int nr_irqs, ret; 1917 1918 if (host->esi_enabled) 1919 return 0; 1920 1921 /* 1922 * 1. We only handle CQs as of now. 1923 * 2. Poll queues do not need ESI. 1924 */ 1925 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 1926 ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs, 1927 ufs_qcom_write_msi_msg); 1928 if (ret) { 1929 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); 1930 goto out; 1931 } 1932 1933 msi_lock_descs(hba->dev); 1934 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1935 ret = devm_request_irq(hba->dev, desc->irq, 1936 ufs_qcom_mcq_esi_handler, 1937 IRQF_SHARED, "qcom-mcq-esi", desc); 1938 if (ret) { 1939 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", 1940 __func__, desc->irq, ret); 1941 failed_desc = desc; 1942 break; 1943 } 1944 } 1945 msi_unlock_descs(hba->dev); 1946 1947 if (ret) { 1948 /* Rewind */ 1949 msi_lock_descs(hba->dev); 1950 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1951 if (desc == failed_desc) 1952 break; 1953 devm_free_irq(hba->dev, desc->irq, hba); 1954 } 1955 msi_unlock_descs(hba->dev); 1956 platform_msi_domain_free_irqs(hba->dev); 1957 } else { 1958 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && 1959 host->hw_ver.step == 0) { 1960 ufshcd_writel(hba, 1961 ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000, 1962 REG_UFS_CFG3); 1963 } 1964 ufshcd_mcq_enable_esi(hba); 1965 } 1966 1967 out: 1968 if (!ret) 1969 host->esi_enabled = true; 1970 1971 return ret; 1972 } 1973 1974 /* 1975 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 1976 * 1977 * The variant operations configure the necessary controller and PHY 1978 * handshake during initialization. 1979 */ 1980 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 1981 .name = "qcom", 1982 .init = ufs_qcom_init, 1983 .exit = ufs_qcom_exit, 1984 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 1985 .clk_scale_notify = ufs_qcom_clk_scale_notify, 1986 .setup_clocks = ufs_qcom_setup_clocks, 1987 .hce_enable_notify = ufs_qcom_hce_enable_notify, 1988 .link_startup_notify = ufs_qcom_link_startup_notify, 1989 .pwr_change_notify = ufs_qcom_pwr_change_notify, 1990 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 1991 .suspend = ufs_qcom_suspend, 1992 .resume = ufs_qcom_resume, 1993 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 1994 .device_reset = ufs_qcom_device_reset, 1995 .config_scaling_param = ufs_qcom_config_scaling_param, 1996 .program_key = ufs_qcom_ice_program_key, 1997 .reinit_notify = ufs_qcom_reinit_notify, 1998 .mcq_config_resource = ufs_qcom_mcq_config_resource, 1999 .get_hba_mac = ufs_qcom_get_hba_mac, 2000 .op_runtime_config = ufs_qcom_op_runtime_config, 2001 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 2002 .config_esi = ufs_qcom_config_esi, 2003 }; 2004 2005 /** 2006 * ufs_qcom_probe - probe routine of the driver 2007 * @pdev: pointer to Platform device handle 2008 * 2009 * Return: zero for success and non-zero for failure. 2010 */ 2011 static int ufs_qcom_probe(struct platform_device *pdev) 2012 { 2013 int err; 2014 struct device *dev = &pdev->dev; 2015 2016 /* Perform generic probe */ 2017 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); 2018 if (err) 2019 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 2020 2021 return 0; 2022 } 2023 2024 /** 2025 * ufs_qcom_remove - set driver_data of the device to NULL 2026 * @pdev: pointer to platform device handle 2027 * 2028 * Always returns 0 2029 */ 2030 static void ufs_qcom_remove(struct platform_device *pdev) 2031 { 2032 struct ufs_hba *hba = platform_get_drvdata(pdev); 2033 2034 pm_runtime_get_sync(&(pdev)->dev); 2035 ufshcd_remove(hba); 2036 platform_msi_domain_free_irqs(hba->dev); 2037 } 2038 2039 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 2040 { .compatible = "qcom,ufshc"}, 2041 {}, 2042 }; 2043 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 2044 2045 #ifdef CONFIG_ACPI 2046 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 2047 { "QCOM24A5" }, 2048 { }, 2049 }; 2050 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 2051 #endif 2052 2053 static const struct dev_pm_ops ufs_qcom_pm_ops = { 2054 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 2055 .prepare = ufshcd_suspend_prepare, 2056 .complete = ufshcd_resume_complete, 2057 #ifdef CONFIG_PM_SLEEP 2058 .suspend = ufshcd_system_suspend, 2059 .resume = ufshcd_system_resume, 2060 .freeze = ufshcd_system_freeze, 2061 .restore = ufshcd_system_restore, 2062 .thaw = ufshcd_system_thaw, 2063 #endif 2064 }; 2065 2066 static struct platform_driver ufs_qcom_pltform = { 2067 .probe = ufs_qcom_probe, 2068 .remove_new = ufs_qcom_remove, 2069 .driver = { 2070 .name = "ufshcd-qcom", 2071 .pm = &ufs_qcom_pm_ops, 2072 .of_match_table = of_match_ptr(ufs_qcom_of_match), 2073 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 2074 }, 2075 }; 2076 module_platform_driver(ufs_qcom_pltform); 2077 2078 MODULE_LICENSE("GPL v2"); 2079