1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * UFS Host Controller driver for Exynos specific extensions 4 * 5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd. 6 * Author: Seungwon Jeon <essuuj@gmail.com> 7 * Author: Alim Akhtar <alim.akhtar@samsung.com> 8 * 9 */ 10 11 #include <asm/unaligned.h> 12 #include <crypto/aes.h> 13 #include <linux/arm-smccc.h> 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 24 #include <ufs/ufshcd.h> 25 #include "ufshcd-pltfrm.h" 26 #include <ufs/ufshci.h> 27 #include <ufs/unipro.h> 28 29 #include "ufs-exynos.h" 30 31 #define DATA_UNIT_SIZE 4096 32 33 /* 34 * Exynos's Vendor specific registers for UFSHCI 35 */ 36 #define HCI_TXPRDT_ENTRY_SIZE 0x00 37 #define PRDT_PREFECT_EN BIT(31) 38 #define HCI_RXPRDT_ENTRY_SIZE 0x04 39 #define HCI_1US_TO_CNT_VAL 0x0C 40 #define CNT_VAL_1US_MASK 0x3FF 41 #define HCI_UTRL_NEXUS_TYPE 0x40 42 #define HCI_UTMRL_NEXUS_TYPE 0x44 43 #define HCI_SW_RST 0x50 44 #define UFS_LINK_SW_RST BIT(0) 45 #define UFS_UNIPRO_SW_RST BIT(1) 46 #define UFS_SW_RST_MASK (UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST) 47 #define HCI_DATA_REORDER 0x60 48 #define HCI_UNIPRO_APB_CLK_CTRL 0x68 49 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF)) 50 #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C 51 #define HCI_GPIO_OUT 0x70 52 #define HCI_ERR_EN_PA_LAYER 0x78 53 #define HCI_ERR_EN_DL_LAYER 0x7C 54 #define HCI_ERR_EN_N_LAYER 0x80 55 #define HCI_ERR_EN_T_LAYER 0x84 56 #define HCI_ERR_EN_DME_LAYER 0x88 57 #define HCI_V2P1_CTRL 0x8C 58 #define IA_TICK_SEL BIT(16) 59 #define HCI_CLKSTOP_CTRL 0xB0 60 #define REFCLKOUT_STOP BIT(4) 61 #define MPHY_APBCLK_STOP BIT(3) 62 #define REFCLK_STOP BIT(2) 63 #define UNIPRO_MCLK_STOP BIT(1) 64 #define UNIPRO_PCLK_STOP BIT(0) 65 #define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\ 66 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\ 67 UNIPRO_PCLK_STOP) 68 /* HCI_MISC is also known as HCI_FORCE_HCS */ 69 #define HCI_MISC 0xB4 70 #define REFCLK_CTRL_EN BIT(7) 71 #define UNIPRO_PCLK_CTRL_EN BIT(6) 72 #define UNIPRO_MCLK_CTRL_EN BIT(5) 73 #define HCI_CORECLK_CTRL_EN BIT(4) 74 #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\ 75 UNIPRO_PCLK_CTRL_EN |\ 76 UNIPRO_MCLK_CTRL_EN) 77 /* Device fatal error */ 78 #define DFES_ERR_EN BIT(31) 79 #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\ 80 UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 81 #define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPORTED_HEADER_TYPE |\ 82 UIC_NETWORK_BAD_DEVICEID_ENC |\ 83 UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING) 84 #define DFES_DEF_L4_ERRS (UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE |\ 85 UIC_TRANSPORT_UNKNOWN_CPORTID |\ 86 UIC_TRANSPORT_NO_CONNECTION_RX |\ 87 UIC_TRANSPORT_BAD_TC) 88 89 /* FSYS UFS Shareability */ 90 #define UFS_WR_SHARABLE BIT(2) 91 #define UFS_RD_SHARABLE BIT(1) 92 #define UFS_SHARABLE (UFS_WR_SHARABLE | UFS_RD_SHARABLE) 93 #define UFS_SHAREABILITY_OFFSET 0x710 94 95 /* Multi-host registers */ 96 #define MHCTRL 0xC4 97 #define MHCTRL_EN_VH_MASK (0xE) 98 #define MHCTRL_EN_VH(vh) (vh << 1) 99 #define PH2VH_MBOX 0xD8 100 101 #define MH_MSG_MASK (0xFF) 102 103 #define MH_MSG(id, msg) ((id << 8) | (msg & 0xFF)) 104 #define MH_MSG_PH_READY 0x1 105 #define MH_MSG_VH_READY 0x2 106 107 #define ALLOW_INQUIRY BIT(25) 108 #define ALLOW_MODE_SELECT BIT(24) 109 #define ALLOW_MODE_SENSE BIT(23) 110 #define ALLOW_PRE_FETCH GENMASK(22, 21) 111 #define ALLOW_READ_CMD_ALL GENMASK(20, 18) /* read_6/10/16 */ 112 #define ALLOW_READ_BUFFER BIT(17) 113 #define ALLOW_READ_CAPACITY GENMASK(16, 15) 114 #define ALLOW_REPORT_LUNS BIT(14) 115 #define ALLOW_REQUEST_SENSE BIT(13) 116 #define ALLOW_SYNCHRONIZE_CACHE GENMASK(8, 7) 117 #define ALLOW_TEST_UNIT_READY BIT(6) 118 #define ALLOW_UNMAP BIT(5) 119 #define ALLOW_VERIFY BIT(4) 120 #define ALLOW_WRITE_CMD_ALL GENMASK(3, 1) /* write_6/10/16 */ 121 122 #define ALLOW_TRANS_VH_DEFAULT (ALLOW_INQUIRY | ALLOW_MODE_SELECT | \ 123 ALLOW_MODE_SENSE | ALLOW_PRE_FETCH | \ 124 ALLOW_READ_CMD_ALL | ALLOW_READ_BUFFER | \ 125 ALLOW_READ_CAPACITY | ALLOW_REPORT_LUNS | \ 126 ALLOW_REQUEST_SENSE | ALLOW_SYNCHRONIZE_CACHE | \ 127 ALLOW_TEST_UNIT_READY | ALLOW_UNMAP | \ 128 ALLOW_VERIFY | ALLOW_WRITE_CMD_ALL) 129 130 #define HCI_MH_ALLOWABLE_TRAN_OF_VH 0x30C 131 #define HCI_MH_IID_IN_TASK_TAG 0X308 132 133 #define PH_READY_TIMEOUT_MS (5 * MSEC_PER_SEC) 134 135 enum { 136 UNIPRO_L1_5 = 0,/* PHY Adapter */ 137 UNIPRO_L2, /* Data Link */ 138 UNIPRO_L3, /* Network */ 139 UNIPRO_L4, /* Transport */ 140 UNIPRO_DME, /* DME */ 141 }; 142 143 /* 144 * UNIPRO registers 145 */ 146 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0 0x7888 147 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1 0x788c 148 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2 0x7890 149 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8 150 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC 151 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0 152 153 /* 154 * UFS Protector registers 155 */ 156 #define UFSPRSECURITY 0x010 157 #define NSSMU BIT(14) 158 #define UFSPSBEGIN0 0x200 159 #define UFSPSEND0 0x204 160 #define UFSPSLUN0 0x208 161 #define UFSPSCTRL0 0x20C 162 163 #define CNTR_DIV_VAL 40 164 165 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en); 166 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en); 167 168 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs) 169 { 170 exynos_ufs_auto_ctrl_hcc(ufs, true); 171 } 172 173 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs) 174 { 175 exynos_ufs_auto_ctrl_hcc(ufs, false); 176 } 177 178 static inline void exynos_ufs_disable_auto_ctrl_hcc_save( 179 struct exynos_ufs *ufs, u32 *val) 180 { 181 *val = hci_readl(ufs, HCI_MISC); 182 exynos_ufs_auto_ctrl_hcc(ufs, false); 183 } 184 185 static inline void exynos_ufs_auto_ctrl_hcc_restore( 186 struct exynos_ufs *ufs, u32 *val) 187 { 188 hci_writel(ufs, *val, HCI_MISC); 189 } 190 191 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs) 192 { 193 exynos_ufs_ctrl_clkstop(ufs, true); 194 } 195 196 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs) 197 { 198 exynos_ufs_ctrl_clkstop(ufs, false); 199 } 200 201 static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) 202 { 203 return 0; 204 } 205 206 static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) 207 { 208 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 209 210 /* IO Coherency setting */ 211 if (ufs->sysreg) { 212 return regmap_update_bits(ufs->sysreg, 213 ufs->shareability_reg_offset, 214 UFS_SHARABLE, UFS_SHARABLE); 215 } 216 217 attr->tx_dif_p_nsec = 3200000; 218 219 return 0; 220 } 221 222 static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs) 223 { 224 struct ufs_hba *hba = ufs->hba; 225 226 /* Enable Virtual Host #1 */ 227 ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL); 228 /* Default VH Transfer permissions */ 229 hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT, HCI_MH_ALLOWABLE_TRAN_OF_VH); 230 /* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */ 231 hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG); 232 233 return 0; 234 } 235 236 static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs) 237 { 238 struct ufs_hba *hba = ufs->hba; 239 int i; 240 u32 tx_line_reset_period, rx_line_reset_period; 241 242 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; 243 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; 244 245 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 246 for_each_ufs_rx_lane(ufs, i) { 247 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), 248 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 249 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); 250 251 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), 252 (rx_line_reset_period >> 16) & 0xFF); 253 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), 254 (rx_line_reset_period >> 8) & 0xFF); 255 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), 256 (rx_line_reset_period) & 0xFF); 257 258 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79); 259 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); 260 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); 261 } 262 263 for_each_ufs_tx_lane(ufs, i) { 264 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), 265 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 266 /* Not to affect VND_TX_LINERESET_PVALUE to VND_TX_CLK_PRD */ 267 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), 268 0x02); 269 270 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), 271 (tx_line_reset_period >> 16) & 0xFF); 272 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), 273 (tx_line_reset_period >> 8) & 0xFF); 274 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), 275 (tx_line_reset_period) & 0xFF); 276 277 /* TX PWM Gear Capability / PWM_G1_ONLY */ 278 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1); 279 } 280 281 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 282 283 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 284 285 ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000); 286 287 return 0; 288 } 289 290 static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs, 291 struct ufs_pa_layer_attr *pwr) 292 { 293 struct ufs_hba *hba = ufs->hba; 294 295 /* PACP_PWR_req and delivered to the remote DME */ 296 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 297 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 298 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 299 300 return 0; 301 } 302 303 static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs, 304 struct ufs_pa_layer_attr *pwr) 305 { 306 struct ufs_hba *hba = ufs->hba; 307 u32 enabled_vh; 308 309 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK; 310 311 /* Send physical host ready message to virtual hosts */ 312 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX); 313 314 return 0; 315 } 316 317 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs) 318 { 319 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 320 u32 val = attr->pa_dbg_opt_suite1_val; 321 struct ufs_hba *hba = ufs->hba; 322 int i; 323 324 exynos_ufs_enable_ov_tm(hba); 325 for_each_ufs_tx_lane(ufs, i) 326 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); 327 for_each_ufs_rx_lane(ufs, i) { 328 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); 329 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); 330 } 331 exynos_ufs_disable_ov_tm(hba); 332 333 for_each_ufs_tx_lane(ufs, i) 334 ufshcd_dme_set(hba, 335 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); 336 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); 337 udelay(1); 338 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 339 val | (1 << 12)); 340 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); 341 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); 342 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); 343 udelay(1600); 344 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val); 345 346 return 0; 347 } 348 349 static int exynos7_ufs_post_link(struct exynos_ufs *ufs) 350 { 351 struct ufs_hba *hba = ufs->hba; 352 int i; 353 354 exynos_ufs_enable_ov_tm(hba); 355 for_each_ufs_tx_lane(ufs, i) { 356 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); 357 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); 358 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), 359 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000))); 360 } 361 exynos_ufs_disable_ov_tm(hba); 362 363 exynos_ufs_enable_dbg_mode(hba); 364 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8); 365 exynos_ufs_disable_dbg_mode(hba); 366 367 return 0; 368 } 369 370 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs, 371 struct ufs_pa_layer_attr *pwr) 372 { 373 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE); 374 375 return 0; 376 } 377 378 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs, 379 struct ufs_pa_layer_attr *pwr) 380 { 381 struct ufs_hba *hba = ufs->hba; 382 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx); 383 384 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1); 385 386 if (lanes == 1) { 387 exynos_ufs_enable_dbg_mode(hba); 388 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1); 389 exynos_ufs_disable_dbg_mode(hba); 390 } 391 392 return 0; 393 } 394 395 /* 396 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w 397 * Control should be disabled in the below cases 398 * - Before host controller S/W reset 399 * - Access to UFS protector's register 400 */ 401 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en) 402 { 403 u32 misc = hci_readl(ufs, HCI_MISC); 404 405 if (en) 406 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC); 407 else 408 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC); 409 } 410 411 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en) 412 { 413 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL); 414 u32 misc = hci_readl(ufs, HCI_MISC); 415 416 if (en) { 417 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC); 418 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL); 419 } else { 420 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL); 421 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC); 422 } 423 } 424 425 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs) 426 { 427 struct ufs_hba *hba = ufs->hba; 428 struct list_head *head = &hba->clk_list_head; 429 struct ufs_clk_info *clki; 430 unsigned long pclk_rate; 431 u32 f_min, f_max; 432 u8 div = 0; 433 int ret = 0; 434 435 if (list_empty(head)) 436 goto out; 437 438 list_for_each_entry(clki, head, list) { 439 if (!IS_ERR(clki->clk)) { 440 if (!strcmp(clki->name, "core_clk")) 441 ufs->clk_hci_core = clki->clk; 442 else if (!strcmp(clki->name, "sclk_unipro_main")) 443 ufs->clk_unipro_main = clki->clk; 444 } 445 } 446 447 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) { 448 dev_err(hba->dev, "failed to get clk info\n"); 449 ret = -EINVAL; 450 goto out; 451 } 452 453 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main); 454 pclk_rate = clk_get_rate(ufs->clk_hci_core); 455 f_min = ufs->pclk_avail_min; 456 f_max = ufs->pclk_avail_max; 457 458 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { 459 do { 460 pclk_rate /= (div + 1); 461 462 if (pclk_rate <= f_max) 463 break; 464 div++; 465 } while (pclk_rate >= f_min); 466 } 467 468 if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) { 469 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); 470 ret = -EINVAL; 471 goto out; 472 } 473 474 ufs->pclk_rate = pclk_rate; 475 ufs->pclk_div = div; 476 477 out: 478 return ret; 479 } 480 481 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs) 482 { 483 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { 484 u32 val; 485 486 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL); 487 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div), 488 HCI_UNIPRO_APB_CLK_CTRL); 489 } 490 } 491 492 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs) 493 { 494 struct ufs_hba *hba = ufs->hba; 495 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 496 497 ufshcd_dme_set(hba, 498 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl); 499 } 500 501 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs) 502 { 503 struct ufs_hba *hba = ufs->hba; 504 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 505 const unsigned int div = 30, mult = 20; 506 const unsigned long pwm_min = 3 * 1000 * 1000; 507 const unsigned long pwm_max = 9 * 1000 * 1000; 508 const int divs[] = {32, 16, 8, 4}; 509 unsigned long clk = 0, _clk, clk_period; 510 int i = 0, clk_idx = -1; 511 512 clk_period = UNIPRO_PCLK_PERIOD(ufs); 513 for (i = 0; i < ARRAY_SIZE(divs); i++) { 514 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div); 515 if (_clk >= pwm_min && _clk <= pwm_max) { 516 if (_clk > clk) { 517 clk_idx = i; 518 clk = _clk; 519 } 520 } 521 } 522 523 if (clk_idx == -1) { 524 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx); 525 dev_err(hba->dev, 526 "failed to decide pwm clock divider, will not change\n"); 527 } 528 529 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK; 530 } 531 532 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period) 533 { 534 const int precise = 10; 535 long pclk_rate = ufs->pclk_rate; 536 long clk_period, fraction; 537 538 clk_period = UNIPRO_PCLK_PERIOD(ufs); 539 fraction = ((NSEC_PER_SEC % pclk_rate) * precise) / pclk_rate; 540 541 return (period * precise) / ((clk_period * precise) + fraction); 542 } 543 544 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs) 545 { 546 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 547 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; 548 549 t_cfg->tx_linereset_p = 550 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); 551 t_cfg->tx_linereset_n = 552 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec); 553 t_cfg->tx_high_z_cnt = 554 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec); 555 t_cfg->tx_base_n_val = 556 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec); 557 t_cfg->tx_gran_n_val = 558 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec); 559 t_cfg->tx_sleep_cnt = 560 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt); 561 562 t_cfg->rx_linereset = 563 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec); 564 t_cfg->rx_hibern8_wait = 565 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec); 566 t_cfg->rx_base_n_val = 567 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec); 568 t_cfg->rx_gran_n_val = 569 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec); 570 t_cfg->rx_sleep_cnt = 571 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt); 572 t_cfg->rx_stall_cnt = 573 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt); 574 } 575 576 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs) 577 { 578 struct ufs_hba *hba = ufs->hba; 579 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; 580 int i; 581 582 exynos_ufs_set_pwm_clk_div(ufs); 583 584 exynos_ufs_enable_ov_tm(hba); 585 586 for_each_ufs_rx_lane(ufs, i) { 587 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), 588 ufs->drv_data->uic_attr->rx_filler_enable); 589 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), 590 RX_LINERESET(t_cfg->rx_linereset)); 591 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), 592 RX_BASE_NVAL_L(t_cfg->rx_base_n_val)); 593 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), 594 RX_BASE_NVAL_H(t_cfg->rx_base_n_val)); 595 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), 596 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val)); 597 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), 598 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val)); 599 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), 600 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt)); 601 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), 602 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt)); 603 } 604 605 for_each_ufs_tx_lane(ufs, i) { 606 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), 607 TX_LINERESET_P(t_cfg->tx_linereset_p)); 608 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), 609 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt)); 610 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), 611 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt)); 612 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), 613 TX_BASE_NVAL_L(t_cfg->tx_base_n_val)); 614 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), 615 TX_BASE_NVAL_H(t_cfg->tx_base_n_val)); 616 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), 617 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val)); 618 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), 619 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val)); 620 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), 621 TX_OV_H8_ENTER_EN | 622 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt)); 623 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), 624 ufs->drv_data->uic_attr->tx_min_activatetime); 625 } 626 627 exynos_ufs_disable_ov_tm(hba); 628 } 629 630 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs) 631 { 632 struct ufs_hba *hba = ufs->hba; 633 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 634 int i; 635 636 exynos_ufs_enable_ov_tm(hba); 637 638 for_each_ufs_rx_lane(ufs, i) { 639 ufshcd_dme_set(hba, 640 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i), 641 attr->rx_hs_g1_sync_len_cap); 642 ufshcd_dme_set(hba, 643 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i), 644 attr->rx_hs_g2_sync_len_cap); 645 ufshcd_dme_set(hba, 646 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i), 647 attr->rx_hs_g3_sync_len_cap); 648 ufshcd_dme_set(hba, 649 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i), 650 attr->rx_hs_g1_prep_sync_len_cap); 651 ufshcd_dme_set(hba, 652 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i), 653 attr->rx_hs_g2_prep_sync_len_cap); 654 ufshcd_dme_set(hba, 655 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i), 656 attr->rx_hs_g3_prep_sync_len_cap); 657 } 658 659 if (attr->rx_adv_fine_gran_sup_en == 0) { 660 for_each_ufs_rx_lane(ufs, i) { 661 ufshcd_dme_set(hba, 662 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0); 663 664 if (attr->rx_min_actv_time_cap) 665 ufshcd_dme_set(hba, 666 UIC_ARG_MIB_SEL( 667 RX_MIN_ACTIVATETIME_CAPABILITY, i), 668 attr->rx_min_actv_time_cap); 669 670 if (attr->rx_hibern8_time_cap) 671 ufshcd_dme_set(hba, 672 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i), 673 attr->rx_hibern8_time_cap); 674 } 675 } else if (attr->rx_adv_fine_gran_sup_en == 1) { 676 for_each_ufs_rx_lane(ufs, i) { 677 if (attr->rx_adv_fine_gran_step) 678 ufshcd_dme_set(hba, 679 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, 680 i), RX_ADV_FINE_GRAN_STEP( 681 attr->rx_adv_fine_gran_step)); 682 683 if (attr->rx_adv_min_actv_time_cap) 684 ufshcd_dme_set(hba, 685 UIC_ARG_MIB_SEL( 686 RX_ADV_MIN_ACTIVATETIME_CAP, i), 687 attr->rx_adv_min_actv_time_cap); 688 689 if (attr->rx_adv_hibern8_time_cap) 690 ufshcd_dme_set(hba, 691 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP, 692 i), 693 attr->rx_adv_hibern8_time_cap); 694 } 695 } 696 697 exynos_ufs_disable_ov_tm(hba); 698 } 699 700 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs) 701 { 702 struct ufs_hba *hba = ufs->hba; 703 enum { 704 DEV_ID = 0x00, 705 PEER_DEV_ID = 0x01, 706 PEER_CPORT_ID = 0x00, 707 TRAFFIC_CLASS = 0x00, 708 }; 709 710 /* allow cport attributes to be set */ 711 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE); 712 713 /* local unipro attributes */ 714 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID); 715 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), true); 716 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID); 717 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID); 718 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS); 719 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS); 720 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); 721 } 722 723 static void exynos_ufs_config_smu(struct exynos_ufs *ufs) 724 { 725 u32 reg, val; 726 727 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); 728 729 /* make encryption disabled by default */ 730 reg = ufsp_readl(ufs, UFSPRSECURITY); 731 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY); 732 ufsp_writel(ufs, 0x0, UFSPSBEGIN0); 733 ufsp_writel(ufs, 0xffffffff, UFSPSEND0); 734 ufsp_writel(ufs, 0xff, UFSPSLUN0); 735 ufsp_writel(ufs, 0xf1, UFSPSCTRL0); 736 737 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); 738 } 739 740 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs, 741 struct ufs_pa_layer_attr *pwr) 742 { 743 struct ufs_hba *hba = ufs->hba; 744 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx); 745 u32 mask, sync_len; 746 enum { 747 SYNC_LEN_G1 = 80 * 1000, /* 80us */ 748 SYNC_LEN_G2 = 40 * 1000, /* 44us */ 749 SYNC_LEN_G3 = 20 * 1000, /* 20us */ 750 }; 751 int i; 752 753 if (g == 1) 754 sync_len = SYNC_LEN_G1; 755 else if (g == 2) 756 sync_len = SYNC_LEN_G2; 757 else if (g == 3) 758 sync_len = SYNC_LEN_G3; 759 else 760 return; 761 762 mask = exynos_ufs_calc_time_cntr(ufs, sync_len); 763 mask = (mask >> 8) & 0xff; 764 765 exynos_ufs_enable_ov_tm(hba); 766 767 for_each_ufs_rx_lane(ufs, i) 768 ufshcd_dme_set(hba, 769 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask); 770 771 exynos_ufs_disable_ov_tm(hba); 772 } 773 774 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, 775 struct ufs_pa_layer_attr *dev_max_params, 776 struct ufs_pa_layer_attr *dev_req_params) 777 { 778 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 779 struct phy *generic_phy = ufs->phy; 780 struct ufs_host_params host_params; 781 int ret; 782 783 if (!dev_req_params) { 784 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 785 ret = -EINVAL; 786 goto out; 787 } 788 789 ufshcd_init_host_params(&host_params); 790 791 ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); 792 if (ret) { 793 pr_err("%s: failed to determine capabilities\n", __func__); 794 goto out; 795 } 796 797 if (ufs->drv_data->pre_pwr_change) 798 ufs->drv_data->pre_pwr_change(ufs, dev_req_params); 799 800 if (ufshcd_is_hs_mode(dev_req_params)) { 801 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params); 802 803 switch (dev_req_params->hs_rate) { 804 case PA_HS_MODE_A: 805 case PA_HS_MODE_B: 806 phy_calibrate(generic_phy); 807 break; 808 } 809 } 810 811 /* setting for three timeout values for traffic class #0 */ 812 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064); 813 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224); 814 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160); 815 816 return 0; 817 out: 818 return ret; 819 } 820 821 #define PWR_MODE_STR_LEN 64 822 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba, 823 struct ufs_pa_layer_attr *pwr_req) 824 { 825 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 826 struct phy *generic_phy = ufs->phy; 827 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx); 828 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx); 829 char pwr_str[PWR_MODE_STR_LEN] = ""; 830 831 /* let default be PWM Gear 1, Lane 1 */ 832 if (!gear) 833 gear = 1; 834 835 if (!lanes) 836 lanes = 1; 837 838 if (ufs->drv_data->post_pwr_change) 839 ufs->drv_data->post_pwr_change(ufs, pwr_req); 840 841 if ((ufshcd_is_hs_mode(pwr_req))) { 842 switch (pwr_req->hs_rate) { 843 case PA_HS_MODE_A: 844 case PA_HS_MODE_B: 845 phy_calibrate(generic_phy); 846 break; 847 } 848 849 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s series_%s G_%d L_%d", 850 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B", 851 gear, lanes); 852 } else { 853 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s G_%d L_%d", 854 "SLOW", gear, lanes); 855 } 856 857 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); 858 859 return 0; 860 } 861 862 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba, 863 int tag, bool is_scsi_cmd) 864 { 865 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 866 u32 type; 867 868 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE); 869 870 if (is_scsi_cmd) 871 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE); 872 else 873 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE); 874 } 875 876 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba, 877 int tag, u8 func) 878 { 879 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 880 u32 type; 881 882 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE); 883 884 switch (func) { 885 case UFS_ABORT_TASK: 886 case UFS_QUERY_TASK: 887 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE); 888 break; 889 case UFS_ABORT_TASK_SET: 890 case UFS_CLEAR_TASK_SET: 891 case UFS_LOGICAL_RESET: 892 case UFS_QUERY_TASK_SET: 893 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE); 894 break; 895 } 896 } 897 898 static int exynos_ufs_phy_init(struct exynos_ufs *ufs) 899 { 900 struct ufs_hba *hba = ufs->hba; 901 struct phy *generic_phy = ufs->phy; 902 int ret = 0; 903 904 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) { 905 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES), 906 &ufs->avail_ln_rx); 907 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES), 908 &ufs->avail_ln_tx); 909 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx, 910 "available data lane is not equal(rx:%d, tx:%d)\n", 911 ufs->avail_ln_rx, ufs->avail_ln_tx); 912 } 913 914 phy_set_bus_width(generic_phy, ufs->avail_ln_rx); 915 ret = phy_init(generic_phy); 916 if (ret) { 917 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 918 __func__, ret); 919 return ret; 920 } 921 922 ret = phy_power_on(generic_phy); 923 if (ret) 924 goto out_exit_phy; 925 926 return 0; 927 928 out_exit_phy: 929 phy_exit(generic_phy); 930 931 return ret; 932 } 933 934 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs) 935 { 936 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 937 struct ufs_hba *hba = ufs->hba; 938 939 if (attr->pa_dbg_clk_period_off) 940 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), 941 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 942 943 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), 944 ufs->drv_data->uic_attr->tx_trailingclks); 945 946 if (attr->pa_dbg_opt_suite1_off) 947 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 948 attr->pa_dbg_opt_suite1_val); 949 950 if (attr->pa_dbg_opt_suite2_off) 951 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off), 952 attr->pa_dbg_opt_suite2_val); 953 } 954 955 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index) 956 { 957 switch (index) { 958 case UNIPRO_L1_5: 959 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER); 960 break; 961 case UNIPRO_L2: 962 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER); 963 break; 964 case UNIPRO_L3: 965 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER); 966 break; 967 case UNIPRO_L4: 968 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER); 969 break; 970 case UNIPRO_DME: 971 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER); 972 break; 973 } 974 } 975 976 static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on, 977 enum ufs_notify_change_status status) 978 { 979 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 980 981 if (!ufs) 982 return 0; 983 984 if (on && status == PRE_CHANGE) { 985 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 986 exynos_ufs_disable_auto_ctrl_hcc(ufs); 987 exynos_ufs_ungate_clks(ufs); 988 } else if (!on && status == POST_CHANGE) { 989 exynos_ufs_gate_clks(ufs); 990 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 991 exynos_ufs_enable_auto_ctrl_hcc(ufs); 992 } 993 994 return 0; 995 } 996 997 static int exynos_ufs_pre_link(struct ufs_hba *hba) 998 { 999 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1000 1001 /* hci */ 1002 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2); 1003 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3); 1004 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4); 1005 exynos_ufs_set_unipro_pclk_div(ufs); 1006 1007 /* unipro */ 1008 exynos_ufs_config_unipro(ufs); 1009 1010 /* m-phy */ 1011 exynos_ufs_phy_init(ufs); 1012 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) { 1013 exynos_ufs_config_phy_time_attr(ufs); 1014 exynos_ufs_config_phy_cap_attr(ufs); 1015 } 1016 1017 exynos_ufs_setup_clocks(hba, true, PRE_CHANGE); 1018 1019 if (ufs->drv_data->pre_link) 1020 ufs->drv_data->pre_link(ufs); 1021 1022 return 0; 1023 } 1024 1025 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs) 1026 { 1027 u32 val; 1028 1029 /* Select function clock (mclk) for timer tick */ 1030 if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) { 1031 val = hci_readl(ufs, HCI_V2P1_CTRL); 1032 val |= IA_TICK_SEL; 1033 hci_writel(ufs, val, HCI_V2P1_CTRL); 1034 } 1035 1036 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL); 1037 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL); 1038 } 1039 1040 static int exynos_ufs_post_link(struct ufs_hba *hba) 1041 { 1042 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1043 struct phy *generic_phy = ufs->phy; 1044 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1045 1046 exynos_ufs_establish_connt(ufs); 1047 exynos_ufs_fit_aggr_timeout(ufs); 1048 1049 hci_writel(ufs, 0xa, HCI_DATA_REORDER); 1050 hci_writel(ufs, ilog2(DATA_UNIT_SIZE), HCI_TXPRDT_ENTRY_SIZE); 1051 hci_writel(ufs, ilog2(DATA_UNIT_SIZE), HCI_RXPRDT_ENTRY_SIZE); 1052 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); 1053 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); 1054 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN); 1055 1056 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB) 1057 ufshcd_dme_set(hba, 1058 UIC_ARG_MIB(T_DBG_SKIP_INIT_HIBERN8_EXIT), true); 1059 1060 if (attr->pa_granularity) { 1061 exynos_ufs_enable_dbg_mode(hba); 1062 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY), 1063 attr->pa_granularity); 1064 exynos_ufs_disable_dbg_mode(hba); 1065 1066 if (attr->pa_tactivate) 1067 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 1068 attr->pa_tactivate); 1069 if (attr->pa_hibern8time && 1070 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER)) 1071 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1072 attr->pa_hibern8time); 1073 } 1074 1075 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { 1076 if (!attr->pa_granularity) 1077 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 1078 &attr->pa_granularity); 1079 if (!attr->pa_hibern8time) 1080 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1081 &attr->pa_hibern8time); 1082 /* 1083 * not wait for HIBERN8 time to exit hibernation 1084 */ 1085 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0); 1086 1087 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) { 1088 /* Valid range for granularity: 1 ~ 6 */ 1089 dev_warn(hba->dev, 1090 "%s: pa_granularity %d is invalid, assuming backwards compatibility\n", 1091 __func__, 1092 attr->pa_granularity); 1093 attr->pa_granularity = 6; 1094 } 1095 } 1096 1097 phy_calibrate(generic_phy); 1098 1099 if (ufs->drv_data->post_link) 1100 ufs->drv_data->post_link(ufs); 1101 1102 return 0; 1103 } 1104 1105 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs) 1106 { 1107 struct device_node *np = dev->of_node; 1108 struct exynos_ufs_uic_attr *attr; 1109 int ret = 0; 1110 1111 ufs->drv_data = device_get_match_data(dev); 1112 1113 if (ufs->drv_data && ufs->drv_data->uic_attr) { 1114 attr = ufs->drv_data->uic_attr; 1115 } else { 1116 dev_err(dev, "failed to get uic attributes\n"); 1117 ret = -EINVAL; 1118 goto out; 1119 } 1120 1121 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); 1122 if (IS_ERR(ufs->sysreg)) 1123 ufs->sysreg = NULL; 1124 else { 1125 if (of_property_read_u32_index(np, "samsung,sysreg", 1, 1126 &ufs->shareability_reg_offset)) { 1127 dev_warn(dev, "can't get an offset from sysreg. Set to default value\n"); 1128 ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET; 1129 } 1130 } 1131 1132 ufs->pclk_avail_min = PCLK_AVAIL_MIN; 1133 ufs->pclk_avail_max = PCLK_AVAIL_MAX; 1134 1135 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN; 1136 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL; 1137 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP; 1138 attr->pa_granularity = PA_GRANULARITY_VAL; 1139 attr->pa_tactivate = PA_TACTIVATE_VAL; 1140 attr->pa_hibern8time = PA_HIBERN8TIME_VAL; 1141 1142 out: 1143 return ret; 1144 } 1145 1146 static inline void exynos_ufs_priv_init(struct ufs_hba *hba, 1147 struct exynos_ufs *ufs) 1148 { 1149 ufs->hba = hba; 1150 ufs->opts = ufs->drv_data->opts; 1151 ufs->rx_sel_idx = PA_MAXDATALANES; 1152 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX) 1153 ufs->rx_sel_idx = 0; 1154 hba->priv = (void *)ufs; 1155 hba->quirks = ufs->drv_data->quirks; 1156 } 1157 1158 #ifdef CONFIG_SCSI_UFS_CRYPTO 1159 1160 /* 1161 * Support for Flash Memory Protector (FMP), which is the inline encryption 1162 * hardware on Exynos and Exynos-based SoCs. The interface to this hardware is 1163 * not compatible with the standard UFS crypto. It requires that encryption be 1164 * configured in the PRDT using a nonstandard extension. 1165 */ 1166 1167 enum fmp_crypto_algo_mode { 1168 FMP_BYPASS_MODE = 0, 1169 FMP_ALGO_MODE_AES_CBC = 1, 1170 FMP_ALGO_MODE_AES_XTS = 2, 1171 }; 1172 enum fmp_crypto_key_length { 1173 FMP_KEYLEN_256BIT = 1, 1174 }; 1175 1176 /** 1177 * struct fmp_sg_entry - nonstandard format of PRDT entries when FMP is enabled 1178 * 1179 * @base: The standard PRDT entry, but with nonstandard bitfields in the high 1180 * bits of the 'size' field, i.e. the last 32-bit word. When these 1181 * nonstandard bitfields are zero, the data segment won't be encrypted or 1182 * decrypted. Otherwise they specify the algorithm and key length with 1183 * which the data segment will be encrypted or decrypted. 1184 * @file_iv: The initialization vector (IV) with all bytes reversed 1185 * @file_enckey: The first half of the AES-XTS key with all bytes reserved 1186 * @file_twkey: The second half of the AES-XTS key with all bytes reserved 1187 * @disk_iv: Unused 1188 * @reserved: Unused 1189 */ 1190 struct fmp_sg_entry { 1191 struct ufshcd_sg_entry base; 1192 __be64 file_iv[2]; 1193 __be64 file_enckey[4]; 1194 __be64 file_twkey[4]; 1195 __be64 disk_iv[2]; 1196 __be64 reserved[2]; 1197 }; 1198 1199 #define SMC_CMD_FMP_SECURITY \ 1200 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ 1201 ARM_SMCCC_OWNER_SIP, 0x1810) 1202 #define SMC_CMD_SMU \ 1203 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ 1204 ARM_SMCCC_OWNER_SIP, 0x1850) 1205 #define SMC_CMD_FMP_SMU_RESUME \ 1206 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ 1207 ARM_SMCCC_OWNER_SIP, 0x1860) 1208 #define SMU_EMBEDDED 0 1209 #define SMU_INIT 0 1210 #define CFG_DESCTYPE_3 3 1211 1212 static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs) 1213 { 1214 struct blk_crypto_profile *profile = &hba->crypto_profile; 1215 struct arm_smccc_res res; 1216 int err; 1217 1218 /* 1219 * Check for the standard crypto support bit, since it's available even 1220 * though the rest of the interface to FMP is nonstandard. 1221 * 1222 * This check should have the effect of preventing the driver from 1223 * trying to use FMP on old Exynos SoCs that don't have FMP. 1224 */ 1225 if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) & 1226 MASK_CRYPTO_SUPPORT)) 1227 return; 1228 1229 /* 1230 * The below sequence of SMC calls to enable FMP can be found in the 1231 * downstream driver source for gs101 and other Exynos-based SoCs. It 1232 * is the only way to enable FMP that works on SoCs such as gs101 that 1233 * don't make the FMP registers accessible to Linux. It probably works 1234 * on other Exynos-based SoCs too, and might even still be the only way 1235 * that works. But this hasn't been properly tested, and this code is 1236 * mutually exclusive with exynos_ufs_config_smu(). So for now only 1237 * enable FMP support on SoCs with EXYNOS_UFS_OPT_UFSPR_SECURE. 1238 */ 1239 if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) 1240 return; 1241 1242 /* 1243 * This call (which sets DESCTYPE to 0x3 in the FMPSECURITY0 register) 1244 * is needed to make the hardware use the larger PRDT entry size. 1245 */ 1246 BUILD_BUG_ON(sizeof(struct fmp_sg_entry) != 128); 1247 arm_smccc_smc(SMC_CMD_FMP_SECURITY, 0, SMU_EMBEDDED, CFG_DESCTYPE_3, 1248 0, 0, 0, 0, &res); 1249 if (res.a0) { 1250 dev_warn(hba->dev, 1251 "SMC_CMD_FMP_SECURITY failed on init: %ld. Disabling FMP support.\n", 1252 res.a0); 1253 return; 1254 } 1255 ufshcd_set_sg_entry_size(hba, sizeof(struct fmp_sg_entry)); 1256 1257 /* 1258 * This is needed to initialize FMP. Without it, errors occur when 1259 * inline encryption is used. 1260 */ 1261 arm_smccc_smc(SMC_CMD_SMU, SMU_INIT, SMU_EMBEDDED, 0, 0, 0, 0, 0, &res); 1262 if (res.a0) { 1263 dev_err(hba->dev, 1264 "SMC_CMD_SMU(SMU_INIT) failed: %ld. Disabling FMP support.\n", 1265 res.a0); 1266 return; 1267 } 1268 1269 /* Advertise crypto capabilities to the block layer. */ 1270 err = devm_blk_crypto_profile_init(hba->dev, profile, 0); 1271 if (err) { 1272 /* Only ENOMEM should be possible here. */ 1273 dev_err(hba->dev, "Failed to initialize crypto profile: %d\n", 1274 err); 1275 return; 1276 } 1277 profile->max_dun_bytes_supported = AES_BLOCK_SIZE; 1278 profile->dev = hba->dev; 1279 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] = 1280 DATA_UNIT_SIZE; 1281 1282 /* Advertise crypto support to ufshcd-core. */ 1283 hba->caps |= UFSHCD_CAP_CRYPTO; 1284 1285 /* Advertise crypto quirks to ufshcd-core. */ 1286 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE | 1287 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE | 1288 UFSHCD_QUIRK_KEYS_IN_PRDT; 1289 1290 } 1291 1292 static void exynos_ufs_fmp_resume(struct ufs_hba *hba) 1293 { 1294 struct arm_smccc_res res; 1295 1296 if (!(hba->caps & UFSHCD_CAP_CRYPTO)) 1297 return; 1298 1299 arm_smccc_smc(SMC_CMD_FMP_SECURITY, 0, SMU_EMBEDDED, CFG_DESCTYPE_3, 1300 0, 0, 0, 0, &res); 1301 if (res.a0) 1302 dev_err(hba->dev, 1303 "SMC_CMD_FMP_SECURITY failed on resume: %ld\n", res.a0); 1304 1305 arm_smccc_smc(SMC_CMD_FMP_SMU_RESUME, 0, SMU_EMBEDDED, 0, 0, 0, 0, 0, 1306 &res); 1307 if (res.a0) 1308 dev_err(hba->dev, 1309 "SMC_CMD_FMP_SMU_RESUME failed: %ld\n", res.a0); 1310 } 1311 1312 static inline __be64 fmp_key_word(const u8 *key, int j) 1313 { 1314 return cpu_to_be64(get_unaligned_le64( 1315 key + AES_KEYSIZE_256 - (j + 1) * sizeof(u64))); 1316 } 1317 1318 /* Fill the PRDT for a request according to the given encryption context. */ 1319 static int exynos_ufs_fmp_fill_prdt(struct ufs_hba *hba, 1320 const struct bio_crypt_ctx *crypt_ctx, 1321 void *prdt, unsigned int num_segments) 1322 { 1323 struct fmp_sg_entry *fmp_prdt = prdt; 1324 const u8 *enckey = crypt_ctx->bc_key->raw; 1325 const u8 *twkey = enckey + AES_KEYSIZE_256; 1326 u64 dun_lo = crypt_ctx->bc_dun[0]; 1327 u64 dun_hi = crypt_ctx->bc_dun[1]; 1328 unsigned int i; 1329 1330 /* If FMP wasn't enabled, we shouldn't get any encrypted requests. */ 1331 if (WARN_ON_ONCE(!(hba->caps & UFSHCD_CAP_CRYPTO))) 1332 return -EIO; 1333 1334 /* Configure FMP on each segment of the request. */ 1335 for (i = 0; i < num_segments; i++) { 1336 struct fmp_sg_entry *prd = &fmp_prdt[i]; 1337 int j; 1338 1339 /* Each segment must be exactly one data unit. */ 1340 if (prd->base.size != cpu_to_le32(DATA_UNIT_SIZE - 1)) { 1341 dev_err(hba->dev, 1342 "data segment is misaligned for FMP\n"); 1343 return -EIO; 1344 } 1345 1346 /* Set the algorithm and key length. */ 1347 prd->base.size |= cpu_to_le32((FMP_ALGO_MODE_AES_XTS << 28) | 1348 (FMP_KEYLEN_256BIT << 26)); 1349 1350 /* Set the IV. */ 1351 prd->file_iv[0] = cpu_to_be64(dun_hi); 1352 prd->file_iv[1] = cpu_to_be64(dun_lo); 1353 1354 /* Set the key. */ 1355 for (j = 0; j < AES_KEYSIZE_256 / sizeof(u64); j++) { 1356 prd->file_enckey[j] = fmp_key_word(enckey, j); 1357 prd->file_twkey[j] = fmp_key_word(twkey, j); 1358 } 1359 1360 /* Increment the data unit number. */ 1361 dun_lo++; 1362 if (dun_lo == 0) 1363 dun_hi++; 1364 } 1365 return 0; 1366 } 1367 1368 #else /* CONFIG_SCSI_UFS_CRYPTO */ 1369 1370 static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs) 1371 { 1372 } 1373 1374 static void exynos_ufs_fmp_resume(struct ufs_hba *hba) 1375 { 1376 } 1377 1378 #define exynos_ufs_fmp_fill_prdt NULL 1379 1380 #endif /* !CONFIG_SCSI_UFS_CRYPTO */ 1381 1382 static int exynos_ufs_init(struct ufs_hba *hba) 1383 { 1384 struct device *dev = hba->dev; 1385 struct platform_device *pdev = to_platform_device(dev); 1386 struct exynos_ufs *ufs; 1387 int ret; 1388 1389 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); 1390 if (!ufs) 1391 return -ENOMEM; 1392 1393 /* exynos-specific hci */ 1394 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); 1395 if (IS_ERR(ufs->reg_hci)) { 1396 dev_err(dev, "cannot ioremap for hci vendor register\n"); 1397 return PTR_ERR(ufs->reg_hci); 1398 } 1399 1400 /* unipro */ 1401 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro"); 1402 if (IS_ERR(ufs->reg_unipro)) { 1403 dev_err(dev, "cannot ioremap for unipro register\n"); 1404 return PTR_ERR(ufs->reg_unipro); 1405 } 1406 1407 /* ufs protector */ 1408 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp"); 1409 if (IS_ERR(ufs->reg_ufsp)) { 1410 dev_err(dev, "cannot ioremap for ufs protector register\n"); 1411 return PTR_ERR(ufs->reg_ufsp); 1412 } 1413 1414 ret = exynos_ufs_parse_dt(dev, ufs); 1415 if (ret) { 1416 dev_err(dev, "failed to get dt info.\n"); 1417 goto out; 1418 } 1419 1420 ufs->phy = devm_phy_get(dev, "ufs-phy"); 1421 if (IS_ERR(ufs->phy)) { 1422 ret = PTR_ERR(ufs->phy); 1423 dev_err(dev, "failed to get ufs-phy\n"); 1424 goto out; 1425 } 1426 1427 exynos_ufs_priv_init(hba, ufs); 1428 1429 exynos_ufs_fmp_init(hba, ufs); 1430 1431 if (ufs->drv_data->drv_init) { 1432 ret = ufs->drv_data->drv_init(dev, ufs); 1433 if (ret) { 1434 dev_err(dev, "failed to init drv-data\n"); 1435 goto out; 1436 } 1437 } 1438 1439 ret = exynos_ufs_get_clk_info(ufs); 1440 if (ret) 1441 goto out; 1442 exynos_ufs_specify_phy_time_attr(ufs); 1443 if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) 1444 exynos_ufs_config_smu(ufs); 1445 1446 hba->host->dma_alignment = DATA_UNIT_SIZE - 1; 1447 return 0; 1448 1449 out: 1450 hba->priv = NULL; 1451 return ret; 1452 } 1453 1454 static int exynos_ufs_host_reset(struct ufs_hba *hba) 1455 { 1456 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1457 unsigned long timeout = jiffies + msecs_to_jiffies(1); 1458 u32 val; 1459 int ret = 0; 1460 1461 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); 1462 1463 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST); 1464 1465 do { 1466 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK)) 1467 goto out; 1468 } while (time_before(jiffies, timeout)); 1469 1470 dev_err(hba->dev, "timeout host sw-reset\n"); 1471 ret = -ETIMEDOUT; 1472 1473 out: 1474 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); 1475 return ret; 1476 } 1477 1478 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba) 1479 { 1480 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1481 1482 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT); 1483 udelay(5); 1484 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT); 1485 } 1486 1487 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, u8 enter) 1488 { 1489 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1490 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1491 1492 if (!enter) { 1493 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1494 exynos_ufs_disable_auto_ctrl_hcc(ufs); 1495 exynos_ufs_ungate_clks(ufs); 1496 1497 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { 1498 static const unsigned int granularity_tbl[] = { 1499 1, 4, 8, 16, 32, 100 1500 }; 1501 int h8_time = attr->pa_hibern8time * 1502 granularity_tbl[attr->pa_granularity - 1]; 1503 unsigned long us; 1504 s64 delta; 1505 1506 do { 1507 delta = h8_time - ktime_us_delta(ktime_get(), 1508 ufs->entry_hibern8_t); 1509 if (delta <= 0) 1510 break; 1511 1512 us = min_t(s64, delta, USEC_PER_MSEC); 1513 if (us >= 10) 1514 usleep_range(us, us + 10); 1515 } while (1); 1516 } 1517 } 1518 } 1519 1520 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, u8 enter) 1521 { 1522 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1523 1524 if (!enter) { 1525 u32 cur_mode = 0; 1526 u32 pwrmode; 1527 1528 if (ufshcd_is_hs_mode(&ufs->dev_req_params)) 1529 pwrmode = FAST_MODE; 1530 else 1531 pwrmode = SLOW_MODE; 1532 1533 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode); 1534 if (cur_mode != (pwrmode << 4 | pwrmode)) { 1535 dev_warn(hba->dev, "%s: power mode change\n", __func__); 1536 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf; 1537 hba->pwr_info.pwr_tx = cur_mode & 0xf; 1538 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 1539 } 1540 1541 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)) 1542 exynos_ufs_establish_connt(ufs); 1543 } else { 1544 ufs->entry_hibern8_t = ktime_get(); 1545 exynos_ufs_gate_clks(ufs); 1546 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1547 exynos_ufs_enable_auto_ctrl_hcc(ufs); 1548 } 1549 } 1550 1551 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba, 1552 enum ufs_notify_change_status status) 1553 { 1554 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1555 int ret = 0; 1556 1557 switch (status) { 1558 case PRE_CHANGE: 1559 /* 1560 * The maximum segment size must be set after scsi_host_alloc() 1561 * has been called and before LUN scanning starts 1562 * (ufshcd_async_scan()). Note: this callback may also be called 1563 * from other functions than ufshcd_init(). 1564 */ 1565 hba->host->max_segment_size = DATA_UNIT_SIZE; 1566 1567 if (ufs->drv_data->pre_hce_enable) { 1568 ret = ufs->drv_data->pre_hce_enable(ufs); 1569 if (ret) 1570 return ret; 1571 } 1572 1573 ret = exynos_ufs_host_reset(hba); 1574 if (ret) 1575 return ret; 1576 exynos_ufs_dev_hw_reset(hba); 1577 break; 1578 case POST_CHANGE: 1579 exynos_ufs_calc_pwm_clk_div(ufs); 1580 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)) 1581 exynos_ufs_enable_auto_ctrl_hcc(ufs); 1582 1583 if (ufs->drv_data->post_hce_enable) 1584 ret = ufs->drv_data->post_hce_enable(ufs); 1585 1586 break; 1587 } 1588 1589 return ret; 1590 } 1591 1592 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba, 1593 enum ufs_notify_change_status status) 1594 { 1595 int ret = 0; 1596 1597 switch (status) { 1598 case PRE_CHANGE: 1599 ret = exynos_ufs_pre_link(hba); 1600 break; 1601 case POST_CHANGE: 1602 ret = exynos_ufs_post_link(hba); 1603 break; 1604 } 1605 1606 return ret; 1607 } 1608 1609 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, 1610 enum ufs_notify_change_status status, 1611 struct ufs_pa_layer_attr *dev_max_params, 1612 struct ufs_pa_layer_attr *dev_req_params) 1613 { 1614 int ret = 0; 1615 1616 switch (status) { 1617 case PRE_CHANGE: 1618 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params, 1619 dev_req_params); 1620 break; 1621 case POST_CHANGE: 1622 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params); 1623 break; 1624 } 1625 1626 return ret; 1627 } 1628 1629 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba, 1630 enum uic_cmd_dme enter, 1631 enum ufs_notify_change_status notify) 1632 { 1633 switch ((u8)notify) { 1634 case PRE_CHANGE: 1635 exynos_ufs_pre_hibern8(hba, enter); 1636 break; 1637 case POST_CHANGE: 1638 exynos_ufs_post_hibern8(hba, enter); 1639 break; 1640 } 1641 } 1642 1643 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 1644 enum ufs_notify_change_status status) 1645 { 1646 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1647 1648 if (status == PRE_CHANGE) 1649 return 0; 1650 1651 if (!ufshcd_is_link_active(hba)) 1652 phy_power_off(ufs->phy); 1653 1654 return 0; 1655 } 1656 1657 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 1658 { 1659 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1660 1661 if (!ufshcd_is_link_active(hba)) 1662 phy_power_on(ufs->phy); 1663 1664 exynos_ufs_config_smu(ufs); 1665 exynos_ufs_fmp_resume(hba); 1666 return 0; 1667 } 1668 1669 static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba, 1670 enum ufs_notify_change_status status) 1671 { 1672 if (status == POST_CHANGE) { 1673 ufshcd_set_link_active(hba); 1674 ufshcd_set_ufs_dev_active(hba); 1675 } 1676 1677 return 0; 1678 } 1679 1680 static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba) 1681 { 1682 u32 mbox; 1683 ktime_t start, stop; 1684 1685 start = ktime_get(); 1686 stop = ktime_add(start, ms_to_ktime(PH_READY_TIMEOUT_MS)); 1687 1688 do { 1689 mbox = ufshcd_readl(hba, PH2VH_MBOX); 1690 /* TODO: Mailbox message protocols between the PH and VHs are 1691 * not implemented yet. This will be supported later 1692 */ 1693 if ((mbox & MH_MSG_MASK) == MH_MSG_PH_READY) 1694 return 0; 1695 1696 usleep_range(40, 50); 1697 } while (ktime_before(ktime_get(), stop)); 1698 1699 return -ETIME; 1700 } 1701 1702 static int exynosauto_ufs_vh_init(struct ufs_hba *hba) 1703 { 1704 struct device *dev = hba->dev; 1705 struct platform_device *pdev = to_platform_device(dev); 1706 struct exynos_ufs *ufs; 1707 int ret; 1708 1709 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); 1710 if (!ufs) 1711 return -ENOMEM; 1712 1713 /* exynos-specific hci */ 1714 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); 1715 if (IS_ERR(ufs->reg_hci)) { 1716 dev_err(dev, "cannot ioremap for hci vendor register\n"); 1717 return PTR_ERR(ufs->reg_hci); 1718 } 1719 1720 ret = exynosauto_ufs_vh_wait_ph_ready(hba); 1721 if (ret) 1722 return ret; 1723 1724 ufs->drv_data = device_get_match_data(dev); 1725 if (!ufs->drv_data) 1726 return -ENODEV; 1727 1728 exynos_ufs_priv_init(hba, ufs); 1729 1730 return 0; 1731 } 1732 1733 static int fsd_ufs_pre_link(struct exynos_ufs *ufs) 1734 { 1735 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1736 struct ufs_hba *hba = ufs->hba; 1737 int i; 1738 1739 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), 1740 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1741 ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12); 1742 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1743 1744 for_each_ufs_tx_lane(ufs, i) { 1745 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1746 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1747 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F); 1748 } 1749 1750 for_each_ufs_rx_lane(ufs, i) { 1751 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1752 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1753 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38); 1754 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0); 1755 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1); 1756 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1); 1757 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0); 1758 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0); 1759 } 1760 1761 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1762 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20); 1763 1764 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 1765 0x2e820183); 1766 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 1767 1768 exynos_ufs_establish_connt(ufs); 1769 1770 return 0; 1771 } 1772 1773 static int fsd_ufs_post_link(struct exynos_ufs *ufs) 1774 { 1775 int i; 1776 struct ufs_hba *hba = ufs->hba; 1777 u32 hw_cap_min_tactivate; 1778 u32 peer_rx_min_actv_time_cap; 1779 u32 max_rx_hibern8_time_cap; 1780 1781 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4), 1782 &hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */ 1783 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 1784 &peer_rx_min_actv_time_cap); /* PA_TActivate */ 1785 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1786 &max_rx_hibern8_time_cap); /* PA_Hibern8Time */ 1787 1788 if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate) 1789 ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 1790 peer_rx_min_actv_time_cap + 1); 1791 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), max_rx_hibern8_time_cap + 1); 1792 1793 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x01); 1794 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xFA); 1795 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x00); 1796 1797 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1798 1799 for_each_ufs_rx_lane(ufs, i) { 1800 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05); 1801 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01); 1802 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02); 1803 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC); 1804 } 1805 1806 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1807 1808 return 0; 1809 } 1810 1811 static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs, 1812 struct ufs_pa_layer_attr *pwr) 1813 { 1814 struct ufs_hba *hba = ufs->hba; 1815 1816 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1); 1817 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1); 1818 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 1819 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 1820 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 1821 1822 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0); 1823 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1); 1824 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2); 1825 1826 return 0; 1827 } 1828 1829 static inline u32 get_mclk_period_unipro_18(struct exynos_ufs *ufs) 1830 { 1831 return (16 * 1000 * 1000000UL / ufs->mclk_rate); 1832 } 1833 1834 static int gs101_ufs_pre_link(struct exynos_ufs *ufs) 1835 { 1836 struct ufs_hba *hba = ufs->hba; 1837 int i; 1838 u32 tx_line_reset_period, rx_line_reset_period; 1839 1840 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) 1841 / NSEC_PER_MSEC; 1842 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) 1843 / NSEC_PER_MSEC; 1844 1845 unipro_writel(ufs, get_mclk_period_unipro_18(ufs), COMP_CLK_PERIOD); 1846 1847 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1848 1849 for_each_ufs_rx_lane(ufs, i) { 1850 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), 1851 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1852 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); 1853 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), 1854 (rx_line_reset_period >> 16) & 0xFF); 1855 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), 1856 (rx_line_reset_period >> 8) & 0xFF); 1857 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), 1858 (rx_line_reset_period) & 0xFF); 1859 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69); 1860 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); 1861 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); 1862 } 1863 1864 for_each_ufs_tx_lane(ufs, i) { 1865 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), 1866 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1867 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), 1868 0x02); 1869 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), 1870 (tx_line_reset_period >> 16) & 0xFF); 1871 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), 1872 (tx_line_reset_period >> 8) & 0xFF); 1873 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), 1874 (tx_line_reset_period) & 0xFF); 1875 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 1); 1876 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7F, i), 0); 1877 } 1878 1879 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1880 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 1881 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), 0x0); 1882 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), 0x1); 1883 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), 0x1); 1884 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); 1885 ufshcd_dme_set(hba, UIC_ARG_MIB(0xA006), 0x8000); 1886 1887 return 0; 1888 } 1889 1890 static int gs101_ufs_post_link(struct exynos_ufs *ufs) 1891 { 1892 struct ufs_hba *hba = ufs->hba; 1893 1894 exynos_ufs_enable_dbg_mode(hba); 1895 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8); 1896 exynos_ufs_disable_dbg_mode(hba); 1897 1898 return 0; 1899 } 1900 1901 static int gs101_ufs_pre_pwr_change(struct exynos_ufs *ufs, 1902 struct ufs_pa_layer_attr *pwr) 1903 { 1904 struct ufs_hba *hba = ufs->hba; 1905 1906 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 1907 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 1908 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 1909 unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0); 1910 unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1); 1911 unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2); 1912 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0); 1913 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1); 1914 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2); 1915 1916 return 0; 1917 } 1918 1919 static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = { 1920 .name = "exynos_ufs", 1921 .init = exynos_ufs_init, 1922 .hce_enable_notify = exynos_ufs_hce_enable_notify, 1923 .link_startup_notify = exynos_ufs_link_startup_notify, 1924 .pwr_change_notify = exynos_ufs_pwr_change_notify, 1925 .setup_clocks = exynos_ufs_setup_clocks, 1926 .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req, 1927 .setup_task_mgmt = exynos_ufs_specify_nexus_t_tm_req, 1928 .hibern8_notify = exynos_ufs_hibern8_notify, 1929 .suspend = exynos_ufs_suspend, 1930 .resume = exynos_ufs_resume, 1931 .fill_crypto_prdt = exynos_ufs_fmp_fill_prdt, 1932 }; 1933 1934 static struct ufs_hba_variant_ops ufs_hba_exynosauto_vh_ops = { 1935 .name = "exynosauto_ufs_vh", 1936 .init = exynosauto_ufs_vh_init, 1937 .link_startup_notify = exynosauto_ufs_vh_link_startup_notify, 1938 }; 1939 1940 static int exynos_ufs_probe(struct platform_device *pdev) 1941 { 1942 int err; 1943 struct device *dev = &pdev->dev; 1944 const struct ufs_hba_variant_ops *vops = &ufs_hba_exynos_ops; 1945 const struct exynos_ufs_drv_data *drv_data = 1946 device_get_match_data(dev); 1947 1948 if (drv_data && drv_data->vops) 1949 vops = drv_data->vops; 1950 1951 err = ufshcd_pltfrm_init(pdev, vops); 1952 if (err) 1953 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err); 1954 1955 return err; 1956 } 1957 1958 static void exynos_ufs_remove(struct platform_device *pdev) 1959 { 1960 struct ufs_hba *hba = platform_get_drvdata(pdev); 1961 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1962 1963 pm_runtime_get_sync(&(pdev)->dev); 1964 ufshcd_remove(hba); 1965 1966 phy_power_off(ufs->phy); 1967 phy_exit(ufs->phy); 1968 } 1969 1970 static struct exynos_ufs_uic_attr exynos7_uic_attr = { 1971 .tx_trailingclks = 0x10, 1972 .tx_dif_p_nsec = 3000000, /* unit: ns */ 1973 .tx_dif_n_nsec = 1000000, /* unit: ns */ 1974 .tx_high_z_cnt_nsec = 20000, /* unit: ns */ 1975 .tx_base_unit_nsec = 100000, /* unit: ns */ 1976 .tx_gran_unit_nsec = 4000, /* unit: ns */ 1977 .tx_sleep_cnt = 1000, /* unit: ns */ 1978 .tx_min_activatetime = 0xa, 1979 .rx_filler_enable = 0x2, 1980 .rx_dif_p_nsec = 1000000, /* unit: ns */ 1981 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ 1982 .rx_base_unit_nsec = 100000, /* unit: ns */ 1983 .rx_gran_unit_nsec = 4000, /* unit: ns */ 1984 .rx_sleep_cnt = 1280, /* unit: ns */ 1985 .rx_stall_cnt = 320, /* unit: ns */ 1986 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), 1987 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), 1988 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), 1989 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), 1990 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), 1991 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), 1992 .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, 1993 .pa_dbg_opt_suite1_val = 0x30103, 1994 .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, 1995 }; 1996 1997 static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = { 1998 .uic_attr = &exynos7_uic_attr, 1999 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2000 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2001 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2002 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2003 .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 2004 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 2005 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 2006 .drv_init = exynosauto_ufs_drv_init, 2007 .post_hce_enable = exynosauto_ufs_post_hce_enable, 2008 .pre_link = exynosauto_ufs_pre_link, 2009 .pre_pwr_change = exynosauto_ufs_pre_pwr_change, 2010 .post_pwr_change = exynosauto_ufs_post_pwr_change, 2011 }; 2012 2013 static const struct exynos_ufs_drv_data exynosauto_ufs_vh_drvs = { 2014 .vops = &ufs_hba_exynosauto_vh_ops, 2015 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2016 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2017 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2018 UFSHCI_QUIRK_BROKEN_HCE | 2019 UFSHCD_QUIRK_BROKEN_UIC_CMD | 2020 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION | 2021 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2022 .opts = EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 2023 }; 2024 2025 static const struct exynos_ufs_drv_data exynos_ufs_drvs = { 2026 .uic_attr = &exynos7_uic_attr, 2027 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2028 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 2029 UFSHCI_QUIRK_BROKEN_HCE | 2030 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2031 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2032 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | 2033 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2034 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL | 2035 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 2036 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX | 2037 EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB | 2038 EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER, 2039 .drv_init = exynos7_ufs_drv_init, 2040 .pre_link = exynos7_ufs_pre_link, 2041 .post_link = exynos7_ufs_post_link, 2042 .pre_pwr_change = exynos7_ufs_pre_pwr_change, 2043 .post_pwr_change = exynos7_ufs_post_pwr_change, 2044 }; 2045 2046 static struct exynos_ufs_uic_attr gs101_uic_attr = { 2047 .tx_trailingclks = 0xff, 2048 .tx_dif_p_nsec = 3000000, /* unit: ns */ 2049 .tx_dif_n_nsec = 1000000, /* unit: ns */ 2050 .tx_high_z_cnt_nsec = 20000, /* unit: ns */ 2051 .tx_base_unit_nsec = 100000, /* unit: ns */ 2052 .tx_gran_unit_nsec = 4000, /* unit: ns */ 2053 .tx_sleep_cnt = 1000, /* unit: ns */ 2054 .tx_min_activatetime = 0xa, 2055 .rx_filler_enable = 0x2, 2056 .rx_dif_p_nsec = 1000000, /* unit: ns */ 2057 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ 2058 .rx_base_unit_nsec = 100000, /* unit: ns */ 2059 .rx_gran_unit_nsec = 4000, /* unit: ns */ 2060 .rx_sleep_cnt = 1280, /* unit: ns */ 2061 .rx_stall_cnt = 320, /* unit: ns */ 2062 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), 2063 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), 2064 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), 2065 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), 2066 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), 2067 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), 2068 .pa_dbg_opt_suite1_val = 0x90913C1C, 2069 .pa_dbg_opt_suite1_off = PA_GS101_DBG_OPTION_SUITE1, 2070 .pa_dbg_opt_suite2_val = 0xE01C115F, 2071 .pa_dbg_opt_suite2_off = PA_GS101_DBG_OPTION_SUITE2, 2072 }; 2073 2074 static struct exynos_ufs_uic_attr fsd_uic_attr = { 2075 .tx_trailingclks = 0x10, 2076 .tx_dif_p_nsec = 3000000, /* unit: ns */ 2077 .tx_dif_n_nsec = 1000000, /* unit: ns */ 2078 .tx_high_z_cnt_nsec = 20000, /* unit: ns */ 2079 .tx_base_unit_nsec = 100000, /* unit: ns */ 2080 .tx_gran_unit_nsec = 4000, /* unit: ns */ 2081 .tx_sleep_cnt = 1000, /* unit: ns */ 2082 .tx_min_activatetime = 0xa, 2083 .rx_filler_enable = 0x2, 2084 .rx_dif_p_nsec = 1000000, /* unit: ns */ 2085 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ 2086 .rx_base_unit_nsec = 100000, /* unit: ns */ 2087 .rx_gran_unit_nsec = 4000, /* unit: ns */ 2088 .rx_sleep_cnt = 1280, /* unit: ns */ 2089 .rx_stall_cnt = 320, /* unit: ns */ 2090 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), 2091 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), 2092 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), 2093 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), 2094 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), 2095 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), 2096 .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, 2097 .pa_dbg_opt_suite1_val = 0x2E820183, 2098 .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, 2099 }; 2100 2101 static const struct exynos_ufs_drv_data fsd_ufs_drvs = { 2102 .uic_attr = &fsd_uic_attr, 2103 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2104 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 2105 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2106 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING | 2107 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR, 2108 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL | 2109 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 2110 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 2111 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 2112 .pre_link = fsd_ufs_pre_link, 2113 .post_link = fsd_ufs_post_link, 2114 .pre_pwr_change = fsd_ufs_pre_pwr_change, 2115 }; 2116 2117 static const struct exynos_ufs_drv_data gs101_ufs_drvs = { 2118 .uic_attr = &gs101_uic_attr, 2119 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2120 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2121 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 2122 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2123 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | 2124 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2125 .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 2126 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 2127 EXYNOS_UFS_OPT_UFSPR_SECURE | 2128 EXYNOS_UFS_OPT_TIMER_TICK_SELECT, 2129 .drv_init = exynosauto_ufs_drv_init, 2130 .pre_link = gs101_ufs_pre_link, 2131 .post_link = gs101_ufs_post_link, 2132 .pre_pwr_change = gs101_ufs_pre_pwr_change, 2133 }; 2134 2135 static const struct of_device_id exynos_ufs_of_match[] = { 2136 { .compatible = "google,gs101-ufs", 2137 .data = &gs101_ufs_drvs }, 2138 { .compatible = "samsung,exynos7-ufs", 2139 .data = &exynos_ufs_drvs }, 2140 { .compatible = "samsung,exynosautov9-ufs", 2141 .data = &exynosauto_ufs_drvs }, 2142 { .compatible = "samsung,exynosautov9-ufs-vh", 2143 .data = &exynosauto_ufs_vh_drvs }, 2144 { .compatible = "tesla,fsd-ufs", 2145 .data = &fsd_ufs_drvs }, 2146 {}, 2147 }; 2148 MODULE_DEVICE_TABLE(of, exynos_ufs_of_match); 2149 2150 static const struct dev_pm_ops exynos_ufs_pm_ops = { 2151 SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume) 2152 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 2153 .prepare = ufshcd_suspend_prepare, 2154 .complete = ufshcd_resume_complete, 2155 }; 2156 2157 static struct platform_driver exynos_ufs_pltform = { 2158 .probe = exynos_ufs_probe, 2159 .remove_new = exynos_ufs_remove, 2160 .driver = { 2161 .name = "exynos-ufshc", 2162 .pm = &exynos_ufs_pm_ops, 2163 .of_match_table = exynos_ufs_of_match, 2164 }, 2165 }; 2166 module_platform_driver(exynos_ufs_pltform); 2167 2168 MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>"); 2169 MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>"); 2170 MODULE_DESCRIPTION("Exynos UFS HCI Driver"); 2171 MODULE_LICENSE("GPL v2"); 2172