1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * UFS Host Controller driver for Exynos specific extensions 4 * 5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd. 6 * Author: Seungwon Jeon <essuuj@gmail.com> 7 * Author: Alim Akhtar <alim.akhtar@samsung.com> 8 * 9 */ 10 11 #include <linux/unaligned.h> 12 #include <crypto/aes.h> 13 #include <linux/arm-smccc.h> 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 24 #include <ufs/ufshcd.h> 25 #include "ufshcd-pltfrm.h" 26 #include <ufs/ufshci.h> 27 #include <ufs/unipro.h> 28 29 #include "ufs-exynos.h" 30 31 #define DATA_UNIT_SIZE 4096 32 33 /* 34 * Exynos's Vendor specific registers for UFSHCI 35 */ 36 #define HCI_TXPRDT_ENTRY_SIZE 0x00 37 #define PRDT_PREFECT_EN BIT(31) 38 #define HCI_RXPRDT_ENTRY_SIZE 0x04 39 #define HCI_1US_TO_CNT_VAL 0x0C 40 #define CNT_VAL_1US_MASK 0x3FF 41 #define HCI_UTRL_NEXUS_TYPE 0x40 42 #define HCI_UTMRL_NEXUS_TYPE 0x44 43 #define HCI_SW_RST 0x50 44 #define UFS_LINK_SW_RST BIT(0) 45 #define UFS_UNIPRO_SW_RST BIT(1) 46 #define UFS_SW_RST_MASK (UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST) 47 #define HCI_DATA_REORDER 0x60 48 #define HCI_UNIPRO_APB_CLK_CTRL 0x68 49 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF)) 50 #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C 51 #define WLU_EN BIT(31) 52 #define WLU_BURST_LEN(x) ((x) << 27 | ((x) & 0xF)) 53 #define HCI_GPIO_OUT 0x70 54 #define HCI_ERR_EN_PA_LAYER 0x78 55 #define HCI_ERR_EN_DL_LAYER 0x7C 56 #define HCI_ERR_EN_N_LAYER 0x80 57 #define HCI_ERR_EN_T_LAYER 0x84 58 #define HCI_ERR_EN_DME_LAYER 0x88 59 #define HCI_V2P1_CTRL 0x8C 60 #define IA_TICK_SEL BIT(16) 61 #define HCI_CLKSTOP_CTRL 0xB0 62 #define REFCLKOUT_STOP BIT(4) 63 #define MPHY_APBCLK_STOP BIT(3) 64 #define REFCLK_STOP BIT(2) 65 #define UNIPRO_MCLK_STOP BIT(1) 66 #define UNIPRO_PCLK_STOP BIT(0) 67 #define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\ 68 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\ 69 UNIPRO_PCLK_STOP) 70 /* HCI_MISC is also known as HCI_FORCE_HCS */ 71 #define HCI_MISC 0xB4 72 #define REFCLK_CTRL_EN BIT(7) 73 #define UNIPRO_PCLK_CTRL_EN BIT(6) 74 #define UNIPRO_MCLK_CTRL_EN BIT(5) 75 #define HCI_CORECLK_CTRL_EN BIT(4) 76 #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\ 77 UNIPRO_PCLK_CTRL_EN |\ 78 UNIPRO_MCLK_CTRL_EN) 79 80 #define HCI_IOP_ACG_DISABLE 0x100 81 #define HCI_IOP_ACG_DISABLE_EN BIT(0) 82 83 /* Device fatal error */ 84 #define DFES_ERR_EN BIT(31) 85 #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\ 86 UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 87 #define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPORTED_HEADER_TYPE |\ 88 UIC_NETWORK_BAD_DEVICEID_ENC |\ 89 UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING) 90 #define DFES_DEF_L4_ERRS (UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE |\ 91 UIC_TRANSPORT_UNKNOWN_CPORTID |\ 92 UIC_TRANSPORT_NO_CONNECTION_RX |\ 93 UIC_TRANSPORT_BAD_TC) 94 95 /* FSYS UFS Shareability */ 96 #define UFS_WR_SHARABLE BIT(2) 97 #define UFS_RD_SHARABLE BIT(1) 98 #define UFS_SHARABLE (UFS_WR_SHARABLE | UFS_RD_SHARABLE) 99 #define UFS_SHAREABILITY_OFFSET 0x710 100 101 /* Multi-host registers */ 102 #define MHCTRL 0xC4 103 #define MHCTRL_EN_VH_MASK (0xE) 104 #define MHCTRL_EN_VH(vh) (vh << 1) 105 #define PH2VH_MBOX 0xD8 106 107 #define MH_MSG_MASK (0xFF) 108 109 #define MH_MSG(id, msg) ((id << 8) | (msg & 0xFF)) 110 #define MH_MSG_PH_READY 0x1 111 #define MH_MSG_VH_READY 0x2 112 113 #define ALLOW_INQUIRY BIT(25) 114 #define ALLOW_MODE_SELECT BIT(24) 115 #define ALLOW_MODE_SENSE BIT(23) 116 #define ALLOW_PRE_FETCH GENMASK(22, 21) 117 #define ALLOW_READ_CMD_ALL GENMASK(20, 18) /* read_6/10/16 */ 118 #define ALLOW_READ_BUFFER BIT(17) 119 #define ALLOW_READ_CAPACITY GENMASK(16, 15) 120 #define ALLOW_REPORT_LUNS BIT(14) 121 #define ALLOW_REQUEST_SENSE BIT(13) 122 #define ALLOW_SYNCHRONIZE_CACHE GENMASK(8, 7) 123 #define ALLOW_TEST_UNIT_READY BIT(6) 124 #define ALLOW_UNMAP BIT(5) 125 #define ALLOW_VERIFY BIT(4) 126 #define ALLOW_WRITE_CMD_ALL GENMASK(3, 1) /* write_6/10/16 */ 127 128 #define ALLOW_TRANS_VH_DEFAULT (ALLOW_INQUIRY | ALLOW_MODE_SELECT | \ 129 ALLOW_MODE_SENSE | ALLOW_PRE_FETCH | \ 130 ALLOW_READ_CMD_ALL | ALLOW_READ_BUFFER | \ 131 ALLOW_READ_CAPACITY | ALLOW_REPORT_LUNS | \ 132 ALLOW_REQUEST_SENSE | ALLOW_SYNCHRONIZE_CACHE | \ 133 ALLOW_TEST_UNIT_READY | ALLOW_UNMAP | \ 134 ALLOW_VERIFY | ALLOW_WRITE_CMD_ALL) 135 136 #define HCI_MH_ALLOWABLE_TRAN_OF_VH 0x30C 137 #define HCI_MH_IID_IN_TASK_TAG 0X308 138 139 #define PH_READY_TIMEOUT_MS (5 * MSEC_PER_SEC) 140 141 enum { 142 UNIPRO_L1_5 = 0,/* PHY Adapter */ 143 UNIPRO_L2, /* Data Link */ 144 UNIPRO_L3, /* Network */ 145 UNIPRO_L4, /* Transport */ 146 UNIPRO_DME, /* DME */ 147 }; 148 149 /* 150 * UNIPRO registers 151 */ 152 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0 0x7888 153 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1 0x788c 154 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2 0x7890 155 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8 156 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC 157 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0 158 159 /* 160 * UFS Protector registers 161 */ 162 #define UFSPRSECURITY 0x010 163 #define NSSMU BIT(14) 164 #define UFSPSBEGIN0 0x200 165 #define UFSPSEND0 0x204 166 #define UFSPSLUN0 0x208 167 #define UFSPSCTRL0 0x20C 168 169 #define CNTR_DIV_VAL 40 170 171 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en); 172 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en); 173 174 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs) 175 { 176 exynos_ufs_auto_ctrl_hcc(ufs, true); 177 } 178 179 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs) 180 { 181 exynos_ufs_auto_ctrl_hcc(ufs, false); 182 } 183 184 static inline void exynos_ufs_disable_auto_ctrl_hcc_save( 185 struct exynos_ufs *ufs, u32 *val) 186 { 187 *val = hci_readl(ufs, HCI_MISC); 188 exynos_ufs_auto_ctrl_hcc(ufs, false); 189 } 190 191 static inline void exynos_ufs_auto_ctrl_hcc_restore( 192 struct exynos_ufs *ufs, u32 *val) 193 { 194 hci_writel(ufs, *val, HCI_MISC); 195 } 196 197 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs) 198 { 199 exynos_ufs_ctrl_clkstop(ufs, true); 200 } 201 202 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs) 203 { 204 exynos_ufs_ctrl_clkstop(ufs, false); 205 } 206 207 static int exynos_ufs_shareability(struct exynos_ufs *ufs) 208 { 209 /* IO Coherency setting */ 210 if (ufs->sysreg) { 211 return regmap_update_bits(ufs->sysreg, 212 ufs->shareability_reg_offset, 213 UFS_SHARABLE, UFS_SHARABLE); 214 } 215 216 return 0; 217 } 218 219 static int gs101_ufs_drv_init(struct exynos_ufs *ufs) 220 { 221 struct ufs_hba *hba = ufs->hba; 222 u32 reg; 223 224 /* Enable WriteBooster */ 225 hba->caps |= UFSHCD_CAP_WB_EN; 226 227 /* Enable clock gating and hibern8 */ 228 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 229 230 /* set ACG to be controlled by UFS_ACG_DISABLE */ 231 reg = hci_readl(ufs, HCI_IOP_ACG_DISABLE); 232 hci_writel(ufs, reg & (~HCI_IOP_ACG_DISABLE_EN), HCI_IOP_ACG_DISABLE); 233 234 return exynos_ufs_shareability(ufs); 235 } 236 237 static int exynosauto_ufs_drv_init(struct exynos_ufs *ufs) 238 { 239 return exynos_ufs_shareability(ufs); 240 } 241 242 static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs) 243 { 244 struct ufs_hba *hba = ufs->hba; 245 246 /* Enable Virtual Host #1 */ 247 ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL); 248 /* Default VH Transfer permissions */ 249 hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT, HCI_MH_ALLOWABLE_TRAN_OF_VH); 250 /* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */ 251 hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG); 252 253 return 0; 254 } 255 256 static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs) 257 { 258 struct ufs_hba *hba = ufs->hba; 259 int i; 260 u32 tx_line_reset_period, rx_line_reset_period; 261 262 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; 263 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; 264 265 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 266 for_each_ufs_rx_lane(ufs, i) { 267 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), 268 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 269 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); 270 271 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), 272 (rx_line_reset_period >> 16) & 0xFF); 273 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), 274 (rx_line_reset_period >> 8) & 0xFF); 275 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), 276 (rx_line_reset_period) & 0xFF); 277 278 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79); 279 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); 280 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); 281 } 282 283 for_each_ufs_tx_lane(ufs, i) { 284 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), 285 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 286 /* Not to affect VND_TX_LINERESET_PVALUE to VND_TX_CLK_PRD */ 287 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), 288 0x02); 289 290 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), 291 (tx_line_reset_period >> 16) & 0xFF); 292 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), 293 (tx_line_reset_period >> 8) & 0xFF); 294 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), 295 (tx_line_reset_period) & 0xFF); 296 297 /* TX PWM Gear Capability / PWM_G1_ONLY */ 298 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1); 299 } 300 301 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 302 303 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 304 305 ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000); 306 307 return 0; 308 } 309 310 static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs, 311 struct ufs_pa_layer_attr *pwr) 312 { 313 struct ufs_hba *hba = ufs->hba; 314 315 /* PACP_PWR_req and delivered to the remote DME */ 316 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 317 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 318 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 319 320 return 0; 321 } 322 323 static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs, 324 struct ufs_pa_layer_attr *pwr) 325 { 326 struct ufs_hba *hba = ufs->hba; 327 u32 enabled_vh; 328 329 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK; 330 331 /* Send physical host ready message to virtual hosts */ 332 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX); 333 334 return 0; 335 } 336 337 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs) 338 { 339 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 340 u32 val = attr->pa_dbg_opt_suite1_val; 341 struct ufs_hba *hba = ufs->hba; 342 int i; 343 344 exynos_ufs_enable_ov_tm(hba); 345 for_each_ufs_tx_lane(ufs, i) 346 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); 347 for_each_ufs_rx_lane(ufs, i) { 348 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); 349 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); 350 } 351 exynos_ufs_disable_ov_tm(hba); 352 353 for_each_ufs_tx_lane(ufs, i) 354 ufshcd_dme_set(hba, 355 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); 356 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); 357 udelay(1); 358 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 359 val | (1 << 12)); 360 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); 361 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); 362 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); 363 udelay(1600); 364 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val); 365 366 return 0; 367 } 368 369 static int exynos7_ufs_post_link(struct exynos_ufs *ufs) 370 { 371 struct ufs_hba *hba = ufs->hba; 372 int i; 373 374 exynos_ufs_enable_ov_tm(hba); 375 for_each_ufs_tx_lane(ufs, i) { 376 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); 377 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); 378 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), 379 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000))); 380 } 381 exynos_ufs_disable_ov_tm(hba); 382 383 exynos_ufs_enable_dbg_mode(hba); 384 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8); 385 exynos_ufs_disable_dbg_mode(hba); 386 387 return 0; 388 } 389 390 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs, 391 struct ufs_pa_layer_attr *pwr) 392 { 393 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE); 394 395 return 0; 396 } 397 398 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs, 399 struct ufs_pa_layer_attr *pwr) 400 { 401 struct ufs_hba *hba = ufs->hba; 402 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx); 403 404 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1); 405 406 if (lanes == 1) { 407 exynos_ufs_enable_dbg_mode(hba); 408 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1); 409 exynos_ufs_disable_dbg_mode(hba); 410 } 411 412 return 0; 413 } 414 415 /* 416 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w 417 * Control should be disabled in the below cases 418 * - Before host controller S/W reset 419 * - Access to UFS protector's register 420 */ 421 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en) 422 { 423 u32 misc = hci_readl(ufs, HCI_MISC); 424 425 if (en) 426 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC); 427 else 428 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC); 429 } 430 431 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en) 432 { 433 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL); 434 u32 misc = hci_readl(ufs, HCI_MISC); 435 436 if (en) { 437 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC); 438 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL); 439 } else { 440 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL); 441 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC); 442 } 443 } 444 445 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs) 446 { 447 struct ufs_hba *hba = ufs->hba; 448 struct list_head *head = &hba->clk_list_head; 449 struct ufs_clk_info *clki; 450 unsigned long pclk_rate; 451 u32 f_min, f_max; 452 u8 div = 0; 453 int ret = 0; 454 455 if (list_empty(head)) 456 goto out; 457 458 list_for_each_entry(clki, head, list) { 459 if (!IS_ERR(clki->clk)) { 460 if (!strcmp(clki->name, "core_clk")) 461 ufs->clk_hci_core = clki->clk; 462 else if (!strcmp(clki->name, "sclk_unipro_main")) 463 ufs->clk_unipro_main = clki->clk; 464 } 465 } 466 467 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) { 468 dev_err(hba->dev, "failed to get clk info\n"); 469 ret = -EINVAL; 470 goto out; 471 } 472 473 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main); 474 pclk_rate = clk_get_rate(ufs->clk_hci_core); 475 f_min = ufs->pclk_avail_min; 476 f_max = ufs->pclk_avail_max; 477 478 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { 479 do { 480 pclk_rate /= (div + 1); 481 482 if (pclk_rate <= f_max) 483 break; 484 div++; 485 } while (pclk_rate >= f_min); 486 } 487 488 if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) { 489 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); 490 ret = -EINVAL; 491 goto out; 492 } 493 494 ufs->pclk_rate = pclk_rate; 495 ufs->pclk_div = div; 496 497 out: 498 return ret; 499 } 500 501 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs) 502 { 503 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { 504 u32 val; 505 506 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL); 507 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div), 508 HCI_UNIPRO_APB_CLK_CTRL); 509 } 510 } 511 512 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs) 513 { 514 struct ufs_hba *hba = ufs->hba; 515 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 516 517 ufshcd_dme_set(hba, 518 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl); 519 } 520 521 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs) 522 { 523 struct ufs_hba *hba = ufs->hba; 524 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 525 const unsigned int div = 30, mult = 20; 526 const unsigned long pwm_min = 3 * 1000 * 1000; 527 const unsigned long pwm_max = 9 * 1000 * 1000; 528 const int divs[] = {32, 16, 8, 4}; 529 unsigned long clk = 0, _clk, clk_period; 530 int i = 0, clk_idx = -1; 531 532 clk_period = UNIPRO_PCLK_PERIOD(ufs); 533 for (i = 0; i < ARRAY_SIZE(divs); i++) { 534 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div); 535 if (_clk >= pwm_min && _clk <= pwm_max) { 536 if (_clk > clk) { 537 clk_idx = i; 538 clk = _clk; 539 } 540 } 541 } 542 543 if (clk_idx == -1) { 544 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx); 545 dev_err(hba->dev, 546 "failed to decide pwm clock divider, will not change\n"); 547 } 548 549 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK; 550 } 551 552 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period) 553 { 554 const int precise = 10; 555 long pclk_rate = ufs->pclk_rate; 556 long clk_period, fraction; 557 558 clk_period = UNIPRO_PCLK_PERIOD(ufs); 559 fraction = ((NSEC_PER_SEC % pclk_rate) * precise) / pclk_rate; 560 561 return (period * precise) / ((clk_period * precise) + fraction); 562 } 563 564 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs) 565 { 566 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 567 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; 568 569 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR) 570 return; 571 572 t_cfg->tx_linereset_p = 573 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); 574 t_cfg->tx_linereset_n = 575 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec); 576 t_cfg->tx_high_z_cnt = 577 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec); 578 t_cfg->tx_base_n_val = 579 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec); 580 t_cfg->tx_gran_n_val = 581 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec); 582 t_cfg->tx_sleep_cnt = 583 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt); 584 585 t_cfg->rx_linereset = 586 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec); 587 t_cfg->rx_hibern8_wait = 588 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec); 589 t_cfg->rx_base_n_val = 590 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec); 591 t_cfg->rx_gran_n_val = 592 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec); 593 t_cfg->rx_sleep_cnt = 594 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt); 595 t_cfg->rx_stall_cnt = 596 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt); 597 } 598 599 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs) 600 { 601 struct ufs_hba *hba = ufs->hba; 602 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; 603 int i; 604 605 exynos_ufs_set_pwm_clk_div(ufs); 606 607 exynos_ufs_enable_ov_tm(hba); 608 609 for_each_ufs_rx_lane(ufs, i) { 610 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), 611 ufs->drv_data->uic_attr->rx_filler_enable); 612 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), 613 RX_LINERESET(t_cfg->rx_linereset)); 614 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), 615 RX_BASE_NVAL_L(t_cfg->rx_base_n_val)); 616 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), 617 RX_BASE_NVAL_H(t_cfg->rx_base_n_val)); 618 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), 619 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val)); 620 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), 621 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val)); 622 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), 623 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt)); 624 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), 625 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt)); 626 } 627 628 for_each_ufs_tx_lane(ufs, i) { 629 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), 630 TX_LINERESET_P(t_cfg->tx_linereset_p)); 631 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), 632 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt)); 633 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), 634 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt)); 635 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), 636 TX_BASE_NVAL_L(t_cfg->tx_base_n_val)); 637 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), 638 TX_BASE_NVAL_H(t_cfg->tx_base_n_val)); 639 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), 640 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val)); 641 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), 642 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val)); 643 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), 644 TX_OV_H8_ENTER_EN | 645 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt)); 646 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), 647 ufs->drv_data->uic_attr->tx_min_activatetime); 648 } 649 650 exynos_ufs_disable_ov_tm(hba); 651 } 652 653 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs) 654 { 655 struct ufs_hba *hba = ufs->hba; 656 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 657 int i; 658 659 exynos_ufs_enable_ov_tm(hba); 660 661 for_each_ufs_rx_lane(ufs, i) { 662 ufshcd_dme_set(hba, 663 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i), 664 attr->rx_hs_g1_sync_len_cap); 665 ufshcd_dme_set(hba, 666 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i), 667 attr->rx_hs_g2_sync_len_cap); 668 ufshcd_dme_set(hba, 669 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i), 670 attr->rx_hs_g3_sync_len_cap); 671 ufshcd_dme_set(hba, 672 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i), 673 attr->rx_hs_g1_prep_sync_len_cap); 674 ufshcd_dme_set(hba, 675 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i), 676 attr->rx_hs_g2_prep_sync_len_cap); 677 ufshcd_dme_set(hba, 678 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i), 679 attr->rx_hs_g3_prep_sync_len_cap); 680 } 681 682 if (attr->rx_adv_fine_gran_sup_en == 0) { 683 for_each_ufs_rx_lane(ufs, i) { 684 ufshcd_dme_set(hba, 685 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0); 686 687 if (attr->rx_min_actv_time_cap) 688 ufshcd_dme_set(hba, 689 UIC_ARG_MIB_SEL( 690 RX_MIN_ACTIVATETIME_CAPABILITY, i), 691 attr->rx_min_actv_time_cap); 692 693 if (attr->rx_hibern8_time_cap) 694 ufshcd_dme_set(hba, 695 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i), 696 attr->rx_hibern8_time_cap); 697 } 698 } else if (attr->rx_adv_fine_gran_sup_en == 1) { 699 for_each_ufs_rx_lane(ufs, i) { 700 if (attr->rx_adv_fine_gran_step) 701 ufshcd_dme_set(hba, 702 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, 703 i), RX_ADV_FINE_GRAN_STEP( 704 attr->rx_adv_fine_gran_step)); 705 706 if (attr->rx_adv_min_actv_time_cap) 707 ufshcd_dme_set(hba, 708 UIC_ARG_MIB_SEL( 709 RX_ADV_MIN_ACTIVATETIME_CAP, i), 710 attr->rx_adv_min_actv_time_cap); 711 712 if (attr->rx_adv_hibern8_time_cap) 713 ufshcd_dme_set(hba, 714 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP, 715 i), 716 attr->rx_adv_hibern8_time_cap); 717 } 718 } 719 720 exynos_ufs_disable_ov_tm(hba); 721 } 722 723 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs) 724 { 725 struct ufs_hba *hba = ufs->hba; 726 enum { 727 DEV_ID = 0x00, 728 PEER_DEV_ID = 0x01, 729 PEER_CPORT_ID = 0x00, 730 TRAFFIC_CLASS = 0x00, 731 }; 732 733 /* allow cport attributes to be set */ 734 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE); 735 736 /* local unipro attributes */ 737 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID); 738 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), true); 739 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID); 740 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID); 741 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS); 742 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS); 743 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); 744 } 745 746 static void exynos_ufs_config_smu(struct exynos_ufs *ufs) 747 { 748 u32 reg, val; 749 750 if (ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE) 751 return; 752 753 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); 754 755 /* make encryption disabled by default */ 756 reg = ufsp_readl(ufs, UFSPRSECURITY); 757 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY); 758 ufsp_writel(ufs, 0x0, UFSPSBEGIN0); 759 ufsp_writel(ufs, 0xffffffff, UFSPSEND0); 760 ufsp_writel(ufs, 0xff, UFSPSLUN0); 761 ufsp_writel(ufs, 0xf1, UFSPSCTRL0); 762 763 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); 764 } 765 766 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs, 767 struct ufs_pa_layer_attr *pwr) 768 { 769 struct ufs_hba *hba = ufs->hba; 770 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx); 771 u32 mask, sync_len; 772 enum { 773 SYNC_LEN_G1 = 80 * 1000, /* 80us */ 774 SYNC_LEN_G2 = 40 * 1000, /* 44us */ 775 SYNC_LEN_G3 = 20 * 1000, /* 20us */ 776 }; 777 int i; 778 779 if (g == 1) 780 sync_len = SYNC_LEN_G1; 781 else if (g == 2) 782 sync_len = SYNC_LEN_G2; 783 else if (g == 3) 784 sync_len = SYNC_LEN_G3; 785 else 786 return; 787 788 mask = exynos_ufs_calc_time_cntr(ufs, sync_len); 789 mask = (mask >> 8) & 0xff; 790 791 exynos_ufs_enable_ov_tm(hba); 792 793 for_each_ufs_rx_lane(ufs, i) 794 ufshcd_dme_set(hba, 795 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask); 796 797 exynos_ufs_disable_ov_tm(hba); 798 } 799 800 #define UFS_HW_VER_MAJOR_MASK GENMASK(15, 8) 801 802 static u32 exynos_ufs_get_hs_gear(struct ufs_hba *hba) 803 { 804 u8 major; 805 806 major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, hba->ufs_version); 807 808 if (major >= 3) 809 return UFS_HS_G4; 810 811 /* Default is HS-G3 */ 812 return UFS_HS_G3; 813 } 814 815 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, 816 struct ufs_pa_layer_attr *dev_max_params, 817 struct ufs_pa_layer_attr *dev_req_params) 818 { 819 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 820 struct phy *generic_phy = ufs->phy; 821 struct ufs_host_params host_params; 822 int ret; 823 824 if (!dev_req_params) { 825 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 826 ret = -EINVAL; 827 goto out; 828 } 829 830 ufshcd_init_host_params(&host_params); 831 832 /* This driver only support symmetric gear setting e.g. hs_tx_gear == hs_rx_gear */ 833 host_params.hs_tx_gear = exynos_ufs_get_hs_gear(hba); 834 host_params.hs_rx_gear = exynos_ufs_get_hs_gear(hba); 835 836 ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); 837 if (ret) { 838 pr_err("%s: failed to determine capabilities\n", __func__); 839 goto out; 840 } 841 842 if (ufs->drv_data->pre_pwr_change) 843 ufs->drv_data->pre_pwr_change(ufs, dev_req_params); 844 845 if (ufshcd_is_hs_mode(dev_req_params)) { 846 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params); 847 848 switch (dev_req_params->hs_rate) { 849 case PA_HS_MODE_A: 850 case PA_HS_MODE_B: 851 phy_calibrate(generic_phy); 852 break; 853 } 854 } 855 856 /* setting for three timeout values for traffic class #0 */ 857 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064); 858 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224); 859 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160); 860 861 return 0; 862 out: 863 return ret; 864 } 865 866 #define PWR_MODE_STR_LEN 64 867 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba, 868 struct ufs_pa_layer_attr *pwr_req) 869 { 870 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 871 struct phy *generic_phy = ufs->phy; 872 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx); 873 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx); 874 char pwr_str[PWR_MODE_STR_LEN] = ""; 875 876 /* let default be PWM Gear 1, Lane 1 */ 877 if (!gear) 878 gear = 1; 879 880 if (!lanes) 881 lanes = 1; 882 883 if (ufs->drv_data->post_pwr_change) 884 ufs->drv_data->post_pwr_change(ufs, pwr_req); 885 886 if ((ufshcd_is_hs_mode(pwr_req))) { 887 switch (pwr_req->hs_rate) { 888 case PA_HS_MODE_A: 889 case PA_HS_MODE_B: 890 phy_calibrate(generic_phy); 891 break; 892 } 893 894 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s series_%s G_%d L_%d", 895 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B", 896 gear, lanes); 897 } else { 898 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s G_%d L_%d", 899 "SLOW", gear, lanes); 900 } 901 902 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); 903 904 return 0; 905 } 906 907 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba, 908 int tag, bool is_scsi_cmd) 909 { 910 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 911 u32 type; 912 913 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE); 914 915 if (is_scsi_cmd) 916 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE); 917 else 918 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE); 919 } 920 921 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba, 922 int tag, u8 func) 923 { 924 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 925 u32 type; 926 927 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE); 928 929 switch (func) { 930 case UFS_ABORT_TASK: 931 case UFS_QUERY_TASK: 932 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE); 933 break; 934 case UFS_ABORT_TASK_SET: 935 case UFS_CLEAR_TASK_SET: 936 case UFS_LOGICAL_RESET: 937 case UFS_QUERY_TASK_SET: 938 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE); 939 break; 940 } 941 } 942 943 static int exynos_ufs_phy_init(struct exynos_ufs *ufs) 944 { 945 struct ufs_hba *hba = ufs->hba; 946 struct phy *generic_phy = ufs->phy; 947 int ret = 0; 948 949 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) { 950 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES), 951 &ufs->avail_ln_rx); 952 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES), 953 &ufs->avail_ln_tx); 954 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx, 955 "available data lane is not equal(rx:%d, tx:%d)\n", 956 ufs->avail_ln_rx, ufs->avail_ln_tx); 957 } 958 959 phy_set_bus_width(generic_phy, ufs->avail_ln_rx); 960 ret = phy_init(generic_phy); 961 if (ret) { 962 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 963 __func__, ret); 964 return ret; 965 } 966 967 ret = phy_power_on(generic_phy); 968 if (ret) 969 goto out_exit_phy; 970 971 return 0; 972 973 out_exit_phy: 974 phy_exit(generic_phy); 975 976 return ret; 977 } 978 979 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs) 980 { 981 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 982 struct ufs_hba *hba = ufs->hba; 983 984 if (attr->pa_dbg_clk_period_off) 985 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), 986 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 987 988 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), 989 ufs->drv_data->uic_attr->tx_trailingclks); 990 991 if (attr->pa_dbg_opt_suite1_off) 992 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 993 attr->pa_dbg_opt_suite1_val); 994 995 if (attr->pa_dbg_opt_suite2_off) 996 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off), 997 attr->pa_dbg_opt_suite2_val); 998 } 999 1000 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index) 1001 { 1002 switch (index) { 1003 case UNIPRO_L1_5: 1004 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER); 1005 break; 1006 case UNIPRO_L2: 1007 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER); 1008 break; 1009 case UNIPRO_L3: 1010 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER); 1011 break; 1012 case UNIPRO_L4: 1013 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER); 1014 break; 1015 case UNIPRO_DME: 1016 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER); 1017 break; 1018 } 1019 } 1020 1021 static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on, 1022 enum ufs_notify_change_status status) 1023 { 1024 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1025 1026 if (!ufs) 1027 return 0; 1028 1029 if (on && status == PRE_CHANGE) { 1030 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1031 exynos_ufs_disable_auto_ctrl_hcc(ufs); 1032 exynos_ufs_ungate_clks(ufs); 1033 } else if (!on && status == POST_CHANGE) { 1034 exynos_ufs_gate_clks(ufs); 1035 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1036 exynos_ufs_enable_auto_ctrl_hcc(ufs); 1037 } 1038 1039 return 0; 1040 } 1041 1042 static int exynos_ufs_pre_link(struct ufs_hba *hba) 1043 { 1044 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1045 1046 /* hci */ 1047 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2); 1048 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3); 1049 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4); 1050 exynos_ufs_set_unipro_pclk_div(ufs); 1051 1052 /* unipro */ 1053 exynos_ufs_config_unipro(ufs); 1054 1055 /* m-phy */ 1056 exynos_ufs_phy_init(ufs); 1057 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) { 1058 exynos_ufs_config_phy_time_attr(ufs); 1059 exynos_ufs_config_phy_cap_attr(ufs); 1060 } 1061 1062 exynos_ufs_setup_clocks(hba, true, PRE_CHANGE); 1063 1064 if (ufs->drv_data->pre_link) 1065 ufs->drv_data->pre_link(ufs); 1066 1067 return 0; 1068 } 1069 1070 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs) 1071 { 1072 u32 val; 1073 1074 /* Select function clock (mclk) for timer tick */ 1075 if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) { 1076 val = hci_readl(ufs, HCI_V2P1_CTRL); 1077 val |= IA_TICK_SEL; 1078 hci_writel(ufs, val, HCI_V2P1_CTRL); 1079 } 1080 1081 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL); 1082 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL); 1083 } 1084 1085 static int exynos_ufs_post_link(struct ufs_hba *hba) 1086 { 1087 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1088 struct phy *generic_phy = ufs->phy; 1089 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1090 1091 exynos_ufs_establish_connt(ufs); 1092 exynos_ufs_fit_aggr_timeout(ufs); 1093 1094 hci_writel(ufs, 0xa, HCI_DATA_REORDER); 1095 hci_writel(ufs, ilog2(DATA_UNIT_SIZE), HCI_TXPRDT_ENTRY_SIZE); 1096 hci_writel(ufs, ilog2(DATA_UNIT_SIZE), HCI_RXPRDT_ENTRY_SIZE); 1097 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); 1098 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); 1099 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN); 1100 1101 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB) 1102 ufshcd_dme_set(hba, 1103 UIC_ARG_MIB(T_DBG_SKIP_INIT_HIBERN8_EXIT), true); 1104 1105 if (attr->pa_granularity) { 1106 exynos_ufs_enable_dbg_mode(hba); 1107 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY), 1108 attr->pa_granularity); 1109 exynos_ufs_disable_dbg_mode(hba); 1110 1111 if (attr->pa_tactivate) 1112 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 1113 attr->pa_tactivate); 1114 if (attr->pa_hibern8time && 1115 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER)) 1116 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1117 attr->pa_hibern8time); 1118 } 1119 1120 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { 1121 if (!attr->pa_granularity) 1122 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 1123 &attr->pa_granularity); 1124 if (!attr->pa_hibern8time) 1125 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1126 &attr->pa_hibern8time); 1127 /* 1128 * not wait for HIBERN8 time to exit hibernation 1129 */ 1130 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0); 1131 1132 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) { 1133 /* Valid range for granularity: 1 ~ 6 */ 1134 dev_warn(hba->dev, 1135 "%s: pa_granularity %d is invalid, assuming backwards compatibility\n", 1136 __func__, 1137 attr->pa_granularity); 1138 attr->pa_granularity = 6; 1139 } 1140 } 1141 1142 phy_calibrate(generic_phy); 1143 1144 if (ufs->drv_data->post_link) 1145 ufs->drv_data->post_link(ufs); 1146 1147 return 0; 1148 } 1149 1150 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs) 1151 { 1152 struct device_node *np = dev->of_node; 1153 struct exynos_ufs_uic_attr *attr; 1154 int ret = 0; 1155 1156 ufs->drv_data = device_get_match_data(dev); 1157 1158 if (ufs->drv_data && ufs->drv_data->uic_attr) { 1159 attr = ufs->drv_data->uic_attr; 1160 } else { 1161 dev_err(dev, "failed to get uic attributes\n"); 1162 ret = -EINVAL; 1163 goto out; 1164 } 1165 1166 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); 1167 if (IS_ERR(ufs->sysreg)) 1168 ufs->sysreg = NULL; 1169 else { 1170 if (of_property_read_u32_index(np, "samsung,sysreg", 1, 1171 &ufs->shareability_reg_offset)) { 1172 dev_warn(dev, "can't get an offset from sysreg. Set to default value\n"); 1173 ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET; 1174 } 1175 } 1176 1177 ufs->pclk_avail_min = PCLK_AVAIL_MIN; 1178 ufs->pclk_avail_max = PCLK_AVAIL_MAX; 1179 1180 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN; 1181 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL; 1182 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP; 1183 attr->pa_granularity = PA_GRANULARITY_VAL; 1184 attr->pa_tactivate = PA_TACTIVATE_VAL; 1185 attr->pa_hibern8time = PA_HIBERN8TIME_VAL; 1186 1187 out: 1188 return ret; 1189 } 1190 1191 static inline void exynos_ufs_priv_init(struct ufs_hba *hba, 1192 struct exynos_ufs *ufs) 1193 { 1194 ufs->hba = hba; 1195 ufs->opts = ufs->drv_data->opts; 1196 ufs->rx_sel_idx = PA_MAXDATALANES; 1197 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX) 1198 ufs->rx_sel_idx = 0; 1199 hba->priv = (void *)ufs; 1200 hba->quirks = ufs->drv_data->quirks; 1201 } 1202 1203 #ifdef CONFIG_SCSI_UFS_CRYPTO 1204 1205 /* 1206 * Support for Flash Memory Protector (FMP), which is the inline encryption 1207 * hardware on Exynos and Exynos-based SoCs. The interface to this hardware is 1208 * not compatible with the standard UFS crypto. It requires that encryption be 1209 * configured in the PRDT using a nonstandard extension. 1210 */ 1211 1212 enum fmp_crypto_algo_mode { 1213 FMP_BYPASS_MODE = 0, 1214 FMP_ALGO_MODE_AES_CBC = 1, 1215 FMP_ALGO_MODE_AES_XTS = 2, 1216 }; 1217 enum fmp_crypto_key_length { 1218 FMP_KEYLEN_256BIT = 1, 1219 }; 1220 1221 /** 1222 * struct fmp_sg_entry - nonstandard format of PRDT entries when FMP is enabled 1223 * 1224 * @base: The standard PRDT entry, but with nonstandard bitfields in the high 1225 * bits of the 'size' field, i.e. the last 32-bit word. When these 1226 * nonstandard bitfields are zero, the data segment won't be encrypted or 1227 * decrypted. Otherwise they specify the algorithm and key length with 1228 * which the data segment will be encrypted or decrypted. 1229 * @file_iv: The initialization vector (IV) with all bytes reversed 1230 * @file_enckey: The first half of the AES-XTS key with all bytes reserved 1231 * @file_twkey: The second half of the AES-XTS key with all bytes reserved 1232 * @disk_iv: Unused 1233 * @reserved: Unused 1234 */ 1235 struct fmp_sg_entry { 1236 struct ufshcd_sg_entry base; 1237 __be64 file_iv[2]; 1238 __be64 file_enckey[4]; 1239 __be64 file_twkey[4]; 1240 __be64 disk_iv[2]; 1241 __be64 reserved[2]; 1242 }; 1243 1244 #define SMC_CMD_FMP_SECURITY \ 1245 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ 1246 ARM_SMCCC_OWNER_SIP, 0x1810) 1247 #define SMC_CMD_SMU \ 1248 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ 1249 ARM_SMCCC_OWNER_SIP, 0x1850) 1250 #define SMC_CMD_FMP_SMU_RESUME \ 1251 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ 1252 ARM_SMCCC_OWNER_SIP, 0x1860) 1253 #define SMU_EMBEDDED 0 1254 #define SMU_INIT 0 1255 #define CFG_DESCTYPE_3 3 1256 1257 static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs) 1258 { 1259 struct blk_crypto_profile *profile = &hba->crypto_profile; 1260 struct arm_smccc_res res; 1261 int err; 1262 1263 /* 1264 * Check for the standard crypto support bit, since it's available even 1265 * though the rest of the interface to FMP is nonstandard. 1266 * 1267 * This check should have the effect of preventing the driver from 1268 * trying to use FMP on old Exynos SoCs that don't have FMP. 1269 */ 1270 if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) & 1271 MASK_CRYPTO_SUPPORT)) 1272 return; 1273 1274 /* 1275 * The below sequence of SMC calls to enable FMP can be found in the 1276 * downstream driver source for gs101 and other Exynos-based SoCs. It 1277 * is the only way to enable FMP that works on SoCs such as gs101 that 1278 * don't make the FMP registers accessible to Linux. It probably works 1279 * on other Exynos-based SoCs too, and might even still be the only way 1280 * that works. But this hasn't been properly tested, and this code is 1281 * mutually exclusive with exynos_ufs_config_smu(). So for now only 1282 * enable FMP support on SoCs with EXYNOS_UFS_OPT_UFSPR_SECURE. 1283 */ 1284 if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) 1285 return; 1286 1287 /* 1288 * This call (which sets DESCTYPE to 0x3 in the FMPSECURITY0 register) 1289 * is needed to make the hardware use the larger PRDT entry size. 1290 */ 1291 BUILD_BUG_ON(sizeof(struct fmp_sg_entry) != 128); 1292 arm_smccc_smc(SMC_CMD_FMP_SECURITY, 0, SMU_EMBEDDED, CFG_DESCTYPE_3, 1293 0, 0, 0, 0, &res); 1294 if (res.a0) { 1295 dev_warn(hba->dev, 1296 "SMC_CMD_FMP_SECURITY failed on init: %ld. Disabling FMP support.\n", 1297 res.a0); 1298 return; 1299 } 1300 ufshcd_set_sg_entry_size(hba, sizeof(struct fmp_sg_entry)); 1301 1302 /* 1303 * This is needed to initialize FMP. Without it, errors occur when 1304 * inline encryption is used. 1305 */ 1306 arm_smccc_smc(SMC_CMD_SMU, SMU_INIT, SMU_EMBEDDED, 0, 0, 0, 0, 0, &res); 1307 if (res.a0) { 1308 dev_err(hba->dev, 1309 "SMC_CMD_SMU(SMU_INIT) failed: %ld. Disabling FMP support.\n", 1310 res.a0); 1311 return; 1312 } 1313 1314 /* Advertise crypto capabilities to the block layer. */ 1315 err = devm_blk_crypto_profile_init(hba->dev, profile, 0); 1316 if (err) { 1317 /* Only ENOMEM should be possible here. */ 1318 dev_err(hba->dev, "Failed to initialize crypto profile: %d\n", 1319 err); 1320 return; 1321 } 1322 profile->max_dun_bytes_supported = AES_BLOCK_SIZE; 1323 profile->dev = hba->dev; 1324 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] = 1325 DATA_UNIT_SIZE; 1326 1327 /* Advertise crypto support to ufshcd-core. */ 1328 hba->caps |= UFSHCD_CAP_CRYPTO; 1329 1330 /* Advertise crypto quirks to ufshcd-core. */ 1331 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE | 1332 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE | 1333 UFSHCD_QUIRK_KEYS_IN_PRDT; 1334 1335 } 1336 1337 static void exynos_ufs_fmp_resume(struct ufs_hba *hba) 1338 { 1339 struct arm_smccc_res res; 1340 1341 if (!(hba->caps & UFSHCD_CAP_CRYPTO)) 1342 return; 1343 1344 arm_smccc_smc(SMC_CMD_FMP_SECURITY, 0, SMU_EMBEDDED, CFG_DESCTYPE_3, 1345 0, 0, 0, 0, &res); 1346 if (res.a0) 1347 dev_err(hba->dev, 1348 "SMC_CMD_FMP_SECURITY failed on resume: %ld\n", res.a0); 1349 1350 arm_smccc_smc(SMC_CMD_FMP_SMU_RESUME, 0, SMU_EMBEDDED, 0, 0, 0, 0, 0, 1351 &res); 1352 if (res.a0) 1353 dev_err(hba->dev, 1354 "SMC_CMD_FMP_SMU_RESUME failed: %ld\n", res.a0); 1355 } 1356 1357 static inline __be64 fmp_key_word(const u8 *key, int j) 1358 { 1359 return cpu_to_be64(get_unaligned_le64( 1360 key + AES_KEYSIZE_256 - (j + 1) * sizeof(u64))); 1361 } 1362 1363 /* Fill the PRDT for a request according to the given encryption context. */ 1364 static int exynos_ufs_fmp_fill_prdt(struct ufs_hba *hba, 1365 const struct bio_crypt_ctx *crypt_ctx, 1366 void *prdt, unsigned int num_segments) 1367 { 1368 struct fmp_sg_entry *fmp_prdt = prdt; 1369 const u8 *enckey = crypt_ctx->bc_key->raw; 1370 const u8 *twkey = enckey + AES_KEYSIZE_256; 1371 u64 dun_lo = crypt_ctx->bc_dun[0]; 1372 u64 dun_hi = crypt_ctx->bc_dun[1]; 1373 unsigned int i; 1374 1375 /* If FMP wasn't enabled, we shouldn't get any encrypted requests. */ 1376 if (WARN_ON_ONCE(!(hba->caps & UFSHCD_CAP_CRYPTO))) 1377 return -EIO; 1378 1379 /* Configure FMP on each segment of the request. */ 1380 for (i = 0; i < num_segments; i++) { 1381 struct fmp_sg_entry *prd = &fmp_prdt[i]; 1382 int j; 1383 1384 /* Each segment must be exactly one data unit. */ 1385 if (prd->base.size != cpu_to_le32(DATA_UNIT_SIZE - 1)) { 1386 dev_err(hba->dev, 1387 "data segment is misaligned for FMP\n"); 1388 return -EIO; 1389 } 1390 1391 /* Set the algorithm and key length. */ 1392 prd->base.size |= cpu_to_le32((FMP_ALGO_MODE_AES_XTS << 28) | 1393 (FMP_KEYLEN_256BIT << 26)); 1394 1395 /* Set the IV. */ 1396 prd->file_iv[0] = cpu_to_be64(dun_hi); 1397 prd->file_iv[1] = cpu_to_be64(dun_lo); 1398 1399 /* Set the key. */ 1400 for (j = 0; j < AES_KEYSIZE_256 / sizeof(u64); j++) { 1401 prd->file_enckey[j] = fmp_key_word(enckey, j); 1402 prd->file_twkey[j] = fmp_key_word(twkey, j); 1403 } 1404 1405 /* Increment the data unit number. */ 1406 dun_lo++; 1407 if (dun_lo == 0) 1408 dun_hi++; 1409 } 1410 return 0; 1411 } 1412 1413 #else /* CONFIG_SCSI_UFS_CRYPTO */ 1414 1415 static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs) 1416 { 1417 } 1418 1419 static void exynos_ufs_fmp_resume(struct ufs_hba *hba) 1420 { 1421 } 1422 1423 #define exynos_ufs_fmp_fill_prdt NULL 1424 1425 #endif /* !CONFIG_SCSI_UFS_CRYPTO */ 1426 1427 static int exynos_ufs_init(struct ufs_hba *hba) 1428 { 1429 struct device *dev = hba->dev; 1430 struct platform_device *pdev = to_platform_device(dev); 1431 struct exynos_ufs *ufs; 1432 int ret; 1433 1434 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); 1435 if (!ufs) 1436 return -ENOMEM; 1437 1438 /* exynos-specific hci */ 1439 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); 1440 if (IS_ERR(ufs->reg_hci)) { 1441 dev_err(dev, "cannot ioremap for hci vendor register\n"); 1442 return PTR_ERR(ufs->reg_hci); 1443 } 1444 1445 /* unipro */ 1446 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro"); 1447 if (IS_ERR(ufs->reg_unipro)) { 1448 dev_err(dev, "cannot ioremap for unipro register\n"); 1449 return PTR_ERR(ufs->reg_unipro); 1450 } 1451 1452 /* ufs protector */ 1453 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp"); 1454 if (IS_ERR(ufs->reg_ufsp)) { 1455 dev_err(dev, "cannot ioremap for ufs protector register\n"); 1456 return PTR_ERR(ufs->reg_ufsp); 1457 } 1458 1459 ret = exynos_ufs_parse_dt(dev, ufs); 1460 if (ret) { 1461 dev_err(dev, "failed to get dt info.\n"); 1462 goto out; 1463 } 1464 1465 ufs->phy = devm_phy_get(dev, "ufs-phy"); 1466 if (IS_ERR(ufs->phy)) { 1467 ret = PTR_ERR(ufs->phy); 1468 dev_err(dev, "failed to get ufs-phy\n"); 1469 goto out; 1470 } 1471 1472 exynos_ufs_priv_init(hba, ufs); 1473 1474 exynos_ufs_fmp_init(hba, ufs); 1475 1476 if (ufs->drv_data->drv_init) { 1477 ret = ufs->drv_data->drv_init(ufs); 1478 if (ret) { 1479 dev_err(dev, "failed to init drv-data\n"); 1480 goto out; 1481 } 1482 } 1483 1484 ret = exynos_ufs_get_clk_info(ufs); 1485 if (ret) 1486 goto out; 1487 exynos_ufs_specify_phy_time_attr(ufs); 1488 1489 exynos_ufs_config_smu(ufs); 1490 1491 hba->host->dma_alignment = DATA_UNIT_SIZE - 1; 1492 return 0; 1493 1494 out: 1495 hba->priv = NULL; 1496 return ret; 1497 } 1498 1499 static int exynos_ufs_host_reset(struct ufs_hba *hba) 1500 { 1501 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1502 unsigned long timeout = jiffies + msecs_to_jiffies(1); 1503 u32 val; 1504 int ret = 0; 1505 1506 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); 1507 1508 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST); 1509 1510 do { 1511 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK)) 1512 goto out; 1513 } while (time_before(jiffies, timeout)); 1514 1515 dev_err(hba->dev, "timeout host sw-reset\n"); 1516 ret = -ETIMEDOUT; 1517 1518 out: 1519 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); 1520 return ret; 1521 } 1522 1523 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba) 1524 { 1525 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1526 1527 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT); 1528 udelay(5); 1529 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT); 1530 } 1531 1532 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd) 1533 { 1534 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1535 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1536 1537 if (cmd == UIC_CMD_DME_HIBER_EXIT) { 1538 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1539 exynos_ufs_disable_auto_ctrl_hcc(ufs); 1540 exynos_ufs_ungate_clks(ufs); 1541 1542 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { 1543 static const unsigned int granularity_tbl[] = { 1544 1, 4, 8, 16, 32, 100 1545 }; 1546 int h8_time = attr->pa_hibern8time * 1547 granularity_tbl[attr->pa_granularity - 1]; 1548 unsigned long us; 1549 s64 delta; 1550 1551 do { 1552 delta = h8_time - ktime_us_delta(ktime_get(), 1553 ufs->entry_hibern8_t); 1554 if (delta <= 0) 1555 break; 1556 1557 us = min_t(s64, delta, USEC_PER_MSEC); 1558 if (us >= 10) 1559 usleep_range(us, us + 10); 1560 } while (1); 1561 } 1562 } 1563 } 1564 1565 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd) 1566 { 1567 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1568 1569 if (cmd == UIC_CMD_DME_HIBER_ENTER) { 1570 ufs->entry_hibern8_t = ktime_get(); 1571 exynos_ufs_gate_clks(ufs); 1572 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1573 exynos_ufs_enable_auto_ctrl_hcc(ufs); 1574 } 1575 } 1576 1577 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba, 1578 enum ufs_notify_change_status status) 1579 { 1580 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1581 int ret = 0; 1582 1583 switch (status) { 1584 case PRE_CHANGE: 1585 /* 1586 * The maximum segment size must be set after scsi_host_alloc() 1587 * has been called and before LUN scanning starts 1588 * (ufshcd_async_scan()). Note: this callback may also be called 1589 * from other functions than ufshcd_init(). 1590 */ 1591 hba->host->max_segment_size = DATA_UNIT_SIZE; 1592 1593 if (ufs->drv_data->pre_hce_enable) { 1594 ret = ufs->drv_data->pre_hce_enable(ufs); 1595 if (ret) 1596 return ret; 1597 } 1598 1599 ret = exynos_ufs_host_reset(hba); 1600 if (ret) 1601 return ret; 1602 exynos_ufs_dev_hw_reset(hba); 1603 break; 1604 case POST_CHANGE: 1605 exynos_ufs_calc_pwm_clk_div(ufs); 1606 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)) 1607 exynos_ufs_enable_auto_ctrl_hcc(ufs); 1608 1609 if (ufs->drv_data->post_hce_enable) 1610 ret = ufs->drv_data->post_hce_enable(ufs); 1611 1612 break; 1613 } 1614 1615 return ret; 1616 } 1617 1618 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba, 1619 enum ufs_notify_change_status status) 1620 { 1621 int ret = 0; 1622 1623 switch (status) { 1624 case PRE_CHANGE: 1625 ret = exynos_ufs_pre_link(hba); 1626 break; 1627 case POST_CHANGE: 1628 ret = exynos_ufs_post_link(hba); 1629 break; 1630 } 1631 1632 return ret; 1633 } 1634 1635 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, 1636 enum ufs_notify_change_status status, 1637 struct ufs_pa_layer_attr *dev_max_params, 1638 struct ufs_pa_layer_attr *dev_req_params) 1639 { 1640 int ret = 0; 1641 1642 switch (status) { 1643 case PRE_CHANGE: 1644 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params, 1645 dev_req_params); 1646 break; 1647 case POST_CHANGE: 1648 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params); 1649 break; 1650 } 1651 1652 return ret; 1653 } 1654 1655 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba, 1656 enum uic_cmd_dme cmd, 1657 enum ufs_notify_change_status notify) 1658 { 1659 switch ((u8)notify) { 1660 case PRE_CHANGE: 1661 exynos_ufs_pre_hibern8(hba, cmd); 1662 break; 1663 case POST_CHANGE: 1664 exynos_ufs_post_hibern8(hba, cmd); 1665 break; 1666 } 1667 } 1668 1669 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 1670 enum ufs_notify_change_status status) 1671 { 1672 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1673 1674 if (status == PRE_CHANGE) 1675 return 0; 1676 1677 if (!ufshcd_is_link_active(hba)) 1678 phy_power_off(ufs->phy); 1679 1680 return 0; 1681 } 1682 1683 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 1684 { 1685 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1686 1687 if (!ufshcd_is_link_active(hba)) 1688 phy_power_on(ufs->phy); 1689 1690 exynos_ufs_config_smu(ufs); 1691 exynos_ufs_fmp_resume(hba); 1692 return 0; 1693 } 1694 1695 static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba, 1696 enum ufs_notify_change_status status) 1697 { 1698 if (status == POST_CHANGE) { 1699 ufshcd_set_link_active(hba); 1700 ufshcd_set_ufs_dev_active(hba); 1701 } 1702 1703 return 0; 1704 } 1705 1706 static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba) 1707 { 1708 u32 mbox; 1709 ktime_t start, stop; 1710 1711 start = ktime_get(); 1712 stop = ktime_add(start, ms_to_ktime(PH_READY_TIMEOUT_MS)); 1713 1714 do { 1715 mbox = ufshcd_readl(hba, PH2VH_MBOX); 1716 /* TODO: Mailbox message protocols between the PH and VHs are 1717 * not implemented yet. This will be supported later 1718 */ 1719 if ((mbox & MH_MSG_MASK) == MH_MSG_PH_READY) 1720 return 0; 1721 1722 usleep_range(40, 50); 1723 } while (ktime_before(ktime_get(), stop)); 1724 1725 return -ETIME; 1726 } 1727 1728 static int exynosauto_ufs_vh_init(struct ufs_hba *hba) 1729 { 1730 struct device *dev = hba->dev; 1731 struct platform_device *pdev = to_platform_device(dev); 1732 struct exynos_ufs *ufs; 1733 int ret; 1734 1735 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); 1736 if (!ufs) 1737 return -ENOMEM; 1738 1739 /* exynos-specific hci */ 1740 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); 1741 if (IS_ERR(ufs->reg_hci)) { 1742 dev_err(dev, "cannot ioremap for hci vendor register\n"); 1743 return PTR_ERR(ufs->reg_hci); 1744 } 1745 1746 ret = exynosauto_ufs_vh_wait_ph_ready(hba); 1747 if (ret) 1748 return ret; 1749 1750 ufs->drv_data = device_get_match_data(dev); 1751 if (!ufs->drv_data) 1752 return -ENODEV; 1753 1754 exynos_ufs_priv_init(hba, ufs); 1755 1756 return 0; 1757 } 1758 1759 static int fsd_ufs_pre_link(struct exynos_ufs *ufs) 1760 { 1761 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1762 struct ufs_hba *hba = ufs->hba; 1763 int i; 1764 1765 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), 1766 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1767 ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12); 1768 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1769 1770 for_each_ufs_tx_lane(ufs, i) { 1771 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1772 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1773 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F); 1774 } 1775 1776 for_each_ufs_rx_lane(ufs, i) { 1777 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1778 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1779 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38); 1780 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0); 1781 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1); 1782 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1); 1783 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0); 1784 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0); 1785 } 1786 1787 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1788 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20); 1789 1790 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 1791 0x2e820183); 1792 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 1793 1794 exynos_ufs_establish_connt(ufs); 1795 1796 return 0; 1797 } 1798 1799 static int fsd_ufs_post_link(struct exynos_ufs *ufs) 1800 { 1801 int i; 1802 struct ufs_hba *hba = ufs->hba; 1803 u32 hw_cap_min_tactivate; 1804 u32 peer_rx_min_actv_time_cap; 1805 u32 max_rx_hibern8_time_cap; 1806 1807 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4), 1808 &hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */ 1809 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 1810 &peer_rx_min_actv_time_cap); /* PA_TActivate */ 1811 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1812 &max_rx_hibern8_time_cap); /* PA_Hibern8Time */ 1813 1814 if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate) 1815 ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 1816 peer_rx_min_actv_time_cap + 1); 1817 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), max_rx_hibern8_time_cap + 1); 1818 1819 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x01); 1820 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xFA); 1821 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x00); 1822 1823 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1824 1825 for_each_ufs_rx_lane(ufs, i) { 1826 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05); 1827 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01); 1828 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02); 1829 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC); 1830 } 1831 1832 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1833 1834 return 0; 1835 } 1836 1837 static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs, 1838 struct ufs_pa_layer_attr *pwr) 1839 { 1840 struct ufs_hba *hba = ufs->hba; 1841 1842 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1); 1843 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1); 1844 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 1845 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 1846 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 1847 1848 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0); 1849 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1); 1850 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2); 1851 1852 return 0; 1853 } 1854 1855 static inline u32 get_mclk_period_unipro_18(struct exynos_ufs *ufs) 1856 { 1857 return (16 * 1000 * 1000000UL / ufs->mclk_rate); 1858 } 1859 1860 static int gs101_ufs_pre_link(struct exynos_ufs *ufs) 1861 { 1862 struct ufs_hba *hba = ufs->hba; 1863 int i; 1864 u32 tx_line_reset_period, rx_line_reset_period; 1865 1866 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) 1867 / NSEC_PER_MSEC; 1868 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) 1869 / NSEC_PER_MSEC; 1870 1871 unipro_writel(ufs, get_mclk_period_unipro_18(ufs), COMP_CLK_PERIOD); 1872 1873 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1874 1875 for_each_ufs_rx_lane(ufs, i) { 1876 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), 1877 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1878 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); 1879 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), 1880 (rx_line_reset_period >> 16) & 0xFF); 1881 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), 1882 (rx_line_reset_period >> 8) & 0xFF); 1883 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), 1884 (rx_line_reset_period) & 0xFF); 1885 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69); 1886 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); 1887 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); 1888 } 1889 1890 for_each_ufs_tx_lane(ufs, i) { 1891 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), 1892 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1893 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), 1894 0x02); 1895 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), 1896 (tx_line_reset_period >> 16) & 0xFF); 1897 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), 1898 (tx_line_reset_period >> 8) & 0xFF); 1899 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), 1900 (tx_line_reset_period) & 0xFF); 1901 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 1); 1902 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7F, i), 0); 1903 } 1904 1905 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1906 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 1907 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), 0x0); 1908 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), 0x1); 1909 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), 0x1); 1910 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); 1911 ufshcd_dme_set(hba, UIC_ARG_MIB(0xA006), 0x8000); 1912 1913 return 0; 1914 } 1915 1916 static int gs101_ufs_post_link(struct exynos_ufs *ufs) 1917 { 1918 struct ufs_hba *hba = ufs->hba; 1919 1920 /* 1921 * Enable Write Line Unique. This field has to be 0x3 1922 * to support Write Line Unique transaction on gs101. 1923 */ 1924 hci_writel(ufs, WLU_EN | WLU_BURST_LEN(3), HCI_AXIDMA_RWDATA_BURST_LEN); 1925 1926 exynos_ufs_enable_dbg_mode(hba); 1927 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8); 1928 exynos_ufs_disable_dbg_mode(hba); 1929 1930 return 0; 1931 } 1932 1933 static int gs101_ufs_pre_pwr_change(struct exynos_ufs *ufs, 1934 struct ufs_pa_layer_attr *pwr) 1935 { 1936 struct ufs_hba *hba = ufs->hba; 1937 1938 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 1939 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 1940 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 1941 unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0); 1942 unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1); 1943 unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2); 1944 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0); 1945 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1); 1946 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2); 1947 1948 return 0; 1949 } 1950 1951 static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = { 1952 .name = "exynos_ufs", 1953 .init = exynos_ufs_init, 1954 .hce_enable_notify = exynos_ufs_hce_enable_notify, 1955 .link_startup_notify = exynos_ufs_link_startup_notify, 1956 .pwr_change_notify = exynos_ufs_pwr_change_notify, 1957 .setup_clocks = exynos_ufs_setup_clocks, 1958 .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req, 1959 .setup_task_mgmt = exynos_ufs_specify_nexus_t_tm_req, 1960 .hibern8_notify = exynos_ufs_hibern8_notify, 1961 .suspend = exynos_ufs_suspend, 1962 .resume = exynos_ufs_resume, 1963 .fill_crypto_prdt = exynos_ufs_fmp_fill_prdt, 1964 }; 1965 1966 static struct ufs_hba_variant_ops ufs_hba_exynosauto_vh_ops = { 1967 .name = "exynosauto_ufs_vh", 1968 .init = exynosauto_ufs_vh_init, 1969 .link_startup_notify = exynosauto_ufs_vh_link_startup_notify, 1970 }; 1971 1972 static int exynos_ufs_probe(struct platform_device *pdev) 1973 { 1974 int err; 1975 struct device *dev = &pdev->dev; 1976 const struct ufs_hba_variant_ops *vops = &ufs_hba_exynos_ops; 1977 const struct exynos_ufs_drv_data *drv_data = 1978 device_get_match_data(dev); 1979 1980 if (drv_data && drv_data->vops) 1981 vops = drv_data->vops; 1982 1983 err = ufshcd_pltfrm_init(pdev, vops); 1984 if (err) 1985 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err); 1986 1987 return err; 1988 } 1989 1990 static void exynos_ufs_remove(struct platform_device *pdev) 1991 { 1992 struct ufs_hba *hba = platform_get_drvdata(pdev); 1993 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1994 1995 ufshcd_pltfrm_remove(pdev); 1996 1997 phy_power_off(ufs->phy); 1998 phy_exit(ufs->phy); 1999 } 2000 2001 static struct exynos_ufs_uic_attr exynos7_uic_attr = { 2002 .tx_trailingclks = 0x10, 2003 .tx_dif_p_nsec = 3000000, /* unit: ns */ 2004 .tx_dif_n_nsec = 1000000, /* unit: ns */ 2005 .tx_high_z_cnt_nsec = 20000, /* unit: ns */ 2006 .tx_base_unit_nsec = 100000, /* unit: ns */ 2007 .tx_gran_unit_nsec = 4000, /* unit: ns */ 2008 .tx_sleep_cnt = 1000, /* unit: ns */ 2009 .tx_min_activatetime = 0xa, 2010 .rx_filler_enable = 0x2, 2011 .rx_dif_p_nsec = 1000000, /* unit: ns */ 2012 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ 2013 .rx_base_unit_nsec = 100000, /* unit: ns */ 2014 .rx_gran_unit_nsec = 4000, /* unit: ns */ 2015 .rx_sleep_cnt = 1280, /* unit: ns */ 2016 .rx_stall_cnt = 320, /* unit: ns */ 2017 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), 2018 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), 2019 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), 2020 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), 2021 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), 2022 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), 2023 .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, 2024 .pa_dbg_opt_suite1_val = 0x30103, 2025 .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, 2026 }; 2027 2028 static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = { 2029 .uic_attr = &exynos7_uic_attr, 2030 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2031 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2032 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2033 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2034 .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 2035 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 2036 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 2037 .drv_init = exynosauto_ufs_drv_init, 2038 .post_hce_enable = exynosauto_ufs_post_hce_enable, 2039 .pre_link = exynosauto_ufs_pre_link, 2040 .pre_pwr_change = exynosauto_ufs_pre_pwr_change, 2041 .post_pwr_change = exynosauto_ufs_post_pwr_change, 2042 }; 2043 2044 static const struct exynos_ufs_drv_data exynosauto_ufs_vh_drvs = { 2045 .vops = &ufs_hba_exynosauto_vh_ops, 2046 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2047 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2048 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2049 UFSHCI_QUIRK_BROKEN_HCE | 2050 UFSHCD_QUIRK_BROKEN_UIC_CMD | 2051 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION | 2052 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2053 .opts = EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 2054 }; 2055 2056 static const struct exynos_ufs_drv_data exynos_ufs_drvs = { 2057 .uic_attr = &exynos7_uic_attr, 2058 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2059 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 2060 UFSHCI_QUIRK_BROKEN_HCE | 2061 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2062 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2063 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | 2064 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2065 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL | 2066 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 2067 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX | 2068 EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB | 2069 EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER, 2070 .pre_link = exynos7_ufs_pre_link, 2071 .post_link = exynos7_ufs_post_link, 2072 .pre_pwr_change = exynos7_ufs_pre_pwr_change, 2073 .post_pwr_change = exynos7_ufs_post_pwr_change, 2074 }; 2075 2076 static struct exynos_ufs_uic_attr gs101_uic_attr = { 2077 .tx_trailingclks = 0xff, 2078 .pa_dbg_opt_suite1_val = 0x90913C1C, 2079 .pa_dbg_opt_suite1_off = PA_GS101_DBG_OPTION_SUITE1, 2080 .pa_dbg_opt_suite2_val = 0xE01C115F, 2081 .pa_dbg_opt_suite2_off = PA_GS101_DBG_OPTION_SUITE2, 2082 }; 2083 2084 static struct exynos_ufs_uic_attr fsd_uic_attr = { 2085 .tx_trailingclks = 0x10, 2086 .tx_dif_p_nsec = 3000000, /* unit: ns */ 2087 .tx_dif_n_nsec = 1000000, /* unit: ns */ 2088 .tx_high_z_cnt_nsec = 20000, /* unit: ns */ 2089 .tx_base_unit_nsec = 100000, /* unit: ns */ 2090 .tx_gran_unit_nsec = 4000, /* unit: ns */ 2091 .tx_sleep_cnt = 1000, /* unit: ns */ 2092 .tx_min_activatetime = 0xa, 2093 .rx_filler_enable = 0x2, 2094 .rx_dif_p_nsec = 1000000, /* unit: ns */ 2095 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ 2096 .rx_base_unit_nsec = 100000, /* unit: ns */ 2097 .rx_gran_unit_nsec = 4000, /* unit: ns */ 2098 .rx_sleep_cnt = 1280, /* unit: ns */ 2099 .rx_stall_cnt = 320, /* unit: ns */ 2100 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), 2101 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), 2102 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), 2103 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), 2104 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), 2105 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), 2106 .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, 2107 .pa_dbg_opt_suite1_val = 0x2E820183, 2108 .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, 2109 }; 2110 2111 static const struct exynos_ufs_drv_data fsd_ufs_drvs = { 2112 .uic_attr = &fsd_uic_attr, 2113 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2114 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 2115 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2116 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING | 2117 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR, 2118 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL | 2119 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 2120 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 2121 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 2122 .pre_link = fsd_ufs_pre_link, 2123 .post_link = fsd_ufs_post_link, 2124 .pre_pwr_change = fsd_ufs_pre_pwr_change, 2125 }; 2126 2127 static const struct exynos_ufs_drv_data gs101_ufs_drvs = { 2128 .uic_attr = &gs101_uic_attr, 2129 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 2130 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 2131 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 2132 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 2133 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | 2134 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 2135 .opts = EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 2136 EXYNOS_UFS_OPT_UFSPR_SECURE | 2137 EXYNOS_UFS_OPT_TIMER_TICK_SELECT, 2138 .drv_init = gs101_ufs_drv_init, 2139 .pre_link = gs101_ufs_pre_link, 2140 .post_link = gs101_ufs_post_link, 2141 .pre_pwr_change = gs101_ufs_pre_pwr_change, 2142 }; 2143 2144 static const struct of_device_id exynos_ufs_of_match[] = { 2145 { .compatible = "google,gs101-ufs", 2146 .data = &gs101_ufs_drvs }, 2147 { .compatible = "samsung,exynos7-ufs", 2148 .data = &exynos_ufs_drvs }, 2149 { .compatible = "samsung,exynosautov9-ufs", 2150 .data = &exynosauto_ufs_drvs }, 2151 { .compatible = "samsung,exynosautov9-ufs-vh", 2152 .data = &exynosauto_ufs_vh_drvs }, 2153 { .compatible = "tesla,fsd-ufs", 2154 .data = &fsd_ufs_drvs }, 2155 {}, 2156 }; 2157 MODULE_DEVICE_TABLE(of, exynos_ufs_of_match); 2158 2159 static const struct dev_pm_ops exynos_ufs_pm_ops = { 2160 SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume) 2161 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 2162 .prepare = ufshcd_suspend_prepare, 2163 .complete = ufshcd_resume_complete, 2164 }; 2165 2166 static struct platform_driver exynos_ufs_pltform = { 2167 .probe = exynos_ufs_probe, 2168 .remove = exynos_ufs_remove, 2169 .driver = { 2170 .name = "exynos-ufshc", 2171 .pm = &exynos_ufs_pm_ops, 2172 .of_match_table = exynos_ufs_of_match, 2173 }, 2174 }; 2175 module_platform_driver(exynos_ufs_pltform); 2176 2177 MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>"); 2178 MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>"); 2179 MODULE_DESCRIPTION("Exynos UFS HCI Driver"); 2180 MODULE_LICENSE("GPL v2"); 2181