1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * UFS Host Controller driver for Exynos specific extensions 4 * 5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd. 6 * Author: Seungwon Jeon <essuuj@gmail.com> 7 * Author: Alim Akhtar <alim.akhtar@samsung.com> 8 * 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 21 #include <ufs/ufshcd.h> 22 #include "ufshcd-pltfrm.h" 23 #include <ufs/ufshci.h> 24 #include <ufs/unipro.h> 25 26 #include "ufs-exynos.h" 27 28 /* 29 * Exynos's Vendor specific registers for UFSHCI 30 */ 31 #define HCI_TXPRDT_ENTRY_SIZE 0x00 32 #define PRDT_PREFECT_EN BIT(31) 33 #define PRDT_SET_SIZE(x) ((x) & 0x1F) 34 #define HCI_RXPRDT_ENTRY_SIZE 0x04 35 #define HCI_1US_TO_CNT_VAL 0x0C 36 #define CNT_VAL_1US_MASK 0x3FF 37 #define HCI_UTRL_NEXUS_TYPE 0x40 38 #define HCI_UTMRL_NEXUS_TYPE 0x44 39 #define HCI_SW_RST 0x50 40 #define UFS_LINK_SW_RST BIT(0) 41 #define UFS_UNIPRO_SW_RST BIT(1) 42 #define UFS_SW_RST_MASK (UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST) 43 #define HCI_DATA_REORDER 0x60 44 #define HCI_UNIPRO_APB_CLK_CTRL 0x68 45 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF)) 46 #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C 47 #define HCI_GPIO_OUT 0x70 48 #define HCI_ERR_EN_PA_LAYER 0x78 49 #define HCI_ERR_EN_DL_LAYER 0x7C 50 #define HCI_ERR_EN_N_LAYER 0x80 51 #define HCI_ERR_EN_T_LAYER 0x84 52 #define HCI_ERR_EN_DME_LAYER 0x88 53 #define HCI_V2P1_CTRL 0x8C 54 #define IA_TICK_SEL BIT(16) 55 #define HCI_CLKSTOP_CTRL 0xB0 56 #define REFCLKOUT_STOP BIT(4) 57 #define MPHY_APBCLK_STOP BIT(3) 58 #define REFCLK_STOP BIT(2) 59 #define UNIPRO_MCLK_STOP BIT(1) 60 #define UNIPRO_PCLK_STOP BIT(0) 61 #define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\ 62 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\ 63 UNIPRO_PCLK_STOP) 64 /* HCI_MISC is also known as HCI_FORCE_HCS */ 65 #define HCI_MISC 0xB4 66 #define REFCLK_CTRL_EN BIT(7) 67 #define UNIPRO_PCLK_CTRL_EN BIT(6) 68 #define UNIPRO_MCLK_CTRL_EN BIT(5) 69 #define HCI_CORECLK_CTRL_EN BIT(4) 70 #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\ 71 UNIPRO_PCLK_CTRL_EN |\ 72 UNIPRO_MCLK_CTRL_EN) 73 /* Device fatal error */ 74 #define DFES_ERR_EN BIT(31) 75 #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\ 76 UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 77 #define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPORTED_HEADER_TYPE |\ 78 UIC_NETWORK_BAD_DEVICEID_ENC |\ 79 UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING) 80 #define DFES_DEF_L4_ERRS (UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE |\ 81 UIC_TRANSPORT_UNKNOWN_CPORTID |\ 82 UIC_TRANSPORT_NO_CONNECTION_RX |\ 83 UIC_TRANSPORT_BAD_TC) 84 85 /* FSYS UFS Shareability */ 86 #define UFS_WR_SHARABLE BIT(2) 87 #define UFS_RD_SHARABLE BIT(1) 88 #define UFS_SHARABLE (UFS_WR_SHARABLE | UFS_RD_SHARABLE) 89 #define UFS_SHAREABILITY_OFFSET 0x710 90 91 /* Multi-host registers */ 92 #define MHCTRL 0xC4 93 #define MHCTRL_EN_VH_MASK (0xE) 94 #define MHCTRL_EN_VH(vh) (vh << 1) 95 #define PH2VH_MBOX 0xD8 96 97 #define MH_MSG_MASK (0xFF) 98 99 #define MH_MSG(id, msg) ((id << 8) | (msg & 0xFF)) 100 #define MH_MSG_PH_READY 0x1 101 #define MH_MSG_VH_READY 0x2 102 103 #define ALLOW_INQUIRY BIT(25) 104 #define ALLOW_MODE_SELECT BIT(24) 105 #define ALLOW_MODE_SENSE BIT(23) 106 #define ALLOW_PRE_FETCH GENMASK(22, 21) 107 #define ALLOW_READ_CMD_ALL GENMASK(20, 18) /* read_6/10/16 */ 108 #define ALLOW_READ_BUFFER BIT(17) 109 #define ALLOW_READ_CAPACITY GENMASK(16, 15) 110 #define ALLOW_REPORT_LUNS BIT(14) 111 #define ALLOW_REQUEST_SENSE BIT(13) 112 #define ALLOW_SYNCHRONIZE_CACHE GENMASK(8, 7) 113 #define ALLOW_TEST_UNIT_READY BIT(6) 114 #define ALLOW_UNMAP BIT(5) 115 #define ALLOW_VERIFY BIT(4) 116 #define ALLOW_WRITE_CMD_ALL GENMASK(3, 1) /* write_6/10/16 */ 117 118 #define ALLOW_TRANS_VH_DEFAULT (ALLOW_INQUIRY | ALLOW_MODE_SELECT | \ 119 ALLOW_MODE_SENSE | ALLOW_PRE_FETCH | \ 120 ALLOW_READ_CMD_ALL | ALLOW_READ_BUFFER | \ 121 ALLOW_READ_CAPACITY | ALLOW_REPORT_LUNS | \ 122 ALLOW_REQUEST_SENSE | ALLOW_SYNCHRONIZE_CACHE | \ 123 ALLOW_TEST_UNIT_READY | ALLOW_UNMAP | \ 124 ALLOW_VERIFY | ALLOW_WRITE_CMD_ALL) 125 126 #define HCI_MH_ALLOWABLE_TRAN_OF_VH 0x30C 127 #define HCI_MH_IID_IN_TASK_TAG 0X308 128 129 #define PH_READY_TIMEOUT_MS (5 * MSEC_PER_SEC) 130 131 enum { 132 UNIPRO_L1_5 = 0,/* PHY Adapter */ 133 UNIPRO_L2, /* Data Link */ 134 UNIPRO_L3, /* Network */ 135 UNIPRO_L4, /* Transport */ 136 UNIPRO_DME, /* DME */ 137 }; 138 139 /* 140 * UNIPRO registers 141 */ 142 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0 0x7888 143 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1 0x788c 144 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2 0x7890 145 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8 146 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC 147 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0 148 149 /* 150 * UFS Protector registers 151 */ 152 #define UFSPRSECURITY 0x010 153 #define NSSMU BIT(14) 154 #define UFSPSBEGIN0 0x200 155 #define UFSPSEND0 0x204 156 #define UFSPSLUN0 0x208 157 #define UFSPSCTRL0 0x20C 158 159 #define CNTR_DIV_VAL 40 160 161 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en); 162 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en); 163 164 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs) 165 { 166 exynos_ufs_auto_ctrl_hcc(ufs, true); 167 } 168 169 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs) 170 { 171 exynos_ufs_auto_ctrl_hcc(ufs, false); 172 } 173 174 static inline void exynos_ufs_disable_auto_ctrl_hcc_save( 175 struct exynos_ufs *ufs, u32 *val) 176 { 177 *val = hci_readl(ufs, HCI_MISC); 178 exynos_ufs_auto_ctrl_hcc(ufs, false); 179 } 180 181 static inline void exynos_ufs_auto_ctrl_hcc_restore( 182 struct exynos_ufs *ufs, u32 *val) 183 { 184 hci_writel(ufs, *val, HCI_MISC); 185 } 186 187 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs) 188 { 189 exynos_ufs_ctrl_clkstop(ufs, true); 190 } 191 192 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs) 193 { 194 exynos_ufs_ctrl_clkstop(ufs, false); 195 } 196 197 static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) 198 { 199 return 0; 200 } 201 202 static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) 203 { 204 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 205 206 /* IO Coherency setting */ 207 if (ufs->sysreg) { 208 return regmap_update_bits(ufs->sysreg, 209 ufs->shareability_reg_offset, 210 UFS_SHARABLE, UFS_SHARABLE); 211 } 212 213 attr->tx_dif_p_nsec = 3200000; 214 215 return 0; 216 } 217 218 static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs) 219 { 220 struct ufs_hba *hba = ufs->hba; 221 222 /* Enable Virtual Host #1 */ 223 ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL); 224 /* Default VH Transfer permissions */ 225 hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT, HCI_MH_ALLOWABLE_TRAN_OF_VH); 226 /* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */ 227 hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG); 228 229 return 0; 230 } 231 232 static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs) 233 { 234 struct ufs_hba *hba = ufs->hba; 235 int i; 236 u32 tx_line_reset_period, rx_line_reset_period; 237 238 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; 239 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; 240 241 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 242 for_each_ufs_rx_lane(ufs, i) { 243 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), 244 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 245 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); 246 247 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), 248 (rx_line_reset_period >> 16) & 0xFF); 249 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), 250 (rx_line_reset_period >> 8) & 0xFF); 251 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), 252 (rx_line_reset_period) & 0xFF); 253 254 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79); 255 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); 256 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); 257 } 258 259 for_each_ufs_tx_lane(ufs, i) { 260 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), 261 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 262 /* Not to affect VND_TX_LINERESET_PVALUE to VND_TX_CLK_PRD */ 263 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), 264 0x02); 265 266 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), 267 (tx_line_reset_period >> 16) & 0xFF); 268 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), 269 (tx_line_reset_period >> 8) & 0xFF); 270 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), 271 (tx_line_reset_period) & 0xFF); 272 273 /* TX PWM Gear Capability / PWM_G1_ONLY */ 274 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1); 275 } 276 277 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 278 279 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 280 281 ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000); 282 283 return 0; 284 } 285 286 static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs, 287 struct ufs_pa_layer_attr *pwr) 288 { 289 struct ufs_hba *hba = ufs->hba; 290 291 /* PACP_PWR_req and delivered to the remote DME */ 292 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 293 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 294 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 295 296 return 0; 297 } 298 299 static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs, 300 struct ufs_pa_layer_attr *pwr) 301 { 302 struct ufs_hba *hba = ufs->hba; 303 u32 enabled_vh; 304 305 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK; 306 307 /* Send physical host ready message to virtual hosts */ 308 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX); 309 310 return 0; 311 } 312 313 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs) 314 { 315 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 316 u32 val = attr->pa_dbg_opt_suite1_val; 317 struct ufs_hba *hba = ufs->hba; 318 int i; 319 320 exynos_ufs_enable_ov_tm(hba); 321 for_each_ufs_tx_lane(ufs, i) 322 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); 323 for_each_ufs_rx_lane(ufs, i) { 324 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); 325 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); 326 } 327 exynos_ufs_disable_ov_tm(hba); 328 329 for_each_ufs_tx_lane(ufs, i) 330 ufshcd_dme_set(hba, 331 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); 332 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); 333 udelay(1); 334 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 335 val | (1 << 12)); 336 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); 337 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); 338 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); 339 udelay(1600); 340 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val); 341 342 return 0; 343 } 344 345 static int exynos7_ufs_post_link(struct exynos_ufs *ufs) 346 { 347 struct ufs_hba *hba = ufs->hba; 348 int i; 349 350 exynos_ufs_enable_ov_tm(hba); 351 for_each_ufs_tx_lane(ufs, i) { 352 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); 353 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); 354 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), 355 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000))); 356 } 357 exynos_ufs_disable_ov_tm(hba); 358 359 exynos_ufs_enable_dbg_mode(hba); 360 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8); 361 exynos_ufs_disable_dbg_mode(hba); 362 363 return 0; 364 } 365 366 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs, 367 struct ufs_pa_layer_attr *pwr) 368 { 369 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE); 370 371 return 0; 372 } 373 374 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs, 375 struct ufs_pa_layer_attr *pwr) 376 { 377 struct ufs_hba *hba = ufs->hba; 378 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx); 379 380 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1); 381 382 if (lanes == 1) { 383 exynos_ufs_enable_dbg_mode(hba); 384 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1); 385 exynos_ufs_disable_dbg_mode(hba); 386 } 387 388 return 0; 389 } 390 391 /* 392 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w 393 * Control should be disabled in the below cases 394 * - Before host controller S/W reset 395 * - Access to UFS protector's register 396 */ 397 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en) 398 { 399 u32 misc = hci_readl(ufs, HCI_MISC); 400 401 if (en) 402 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC); 403 else 404 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC); 405 } 406 407 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en) 408 { 409 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL); 410 u32 misc = hci_readl(ufs, HCI_MISC); 411 412 if (en) { 413 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC); 414 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL); 415 } else { 416 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL); 417 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC); 418 } 419 } 420 421 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs) 422 { 423 struct ufs_hba *hba = ufs->hba; 424 struct list_head *head = &hba->clk_list_head; 425 struct ufs_clk_info *clki; 426 unsigned long pclk_rate; 427 u32 f_min, f_max; 428 u8 div = 0; 429 int ret = 0; 430 431 if (list_empty(head)) 432 goto out; 433 434 list_for_each_entry(clki, head, list) { 435 if (!IS_ERR(clki->clk)) { 436 if (!strcmp(clki->name, "core_clk")) 437 ufs->clk_hci_core = clki->clk; 438 else if (!strcmp(clki->name, "sclk_unipro_main")) 439 ufs->clk_unipro_main = clki->clk; 440 } 441 } 442 443 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) { 444 dev_err(hba->dev, "failed to get clk info\n"); 445 ret = -EINVAL; 446 goto out; 447 } 448 449 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main); 450 pclk_rate = clk_get_rate(ufs->clk_hci_core); 451 f_min = ufs->pclk_avail_min; 452 f_max = ufs->pclk_avail_max; 453 454 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { 455 do { 456 pclk_rate /= (div + 1); 457 458 if (pclk_rate <= f_max) 459 break; 460 div++; 461 } while (pclk_rate >= f_min); 462 } 463 464 if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) { 465 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); 466 ret = -EINVAL; 467 goto out; 468 } 469 470 ufs->pclk_rate = pclk_rate; 471 ufs->pclk_div = div; 472 473 out: 474 return ret; 475 } 476 477 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs) 478 { 479 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { 480 u32 val; 481 482 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL); 483 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div), 484 HCI_UNIPRO_APB_CLK_CTRL); 485 } 486 } 487 488 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs) 489 { 490 struct ufs_hba *hba = ufs->hba; 491 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 492 493 ufshcd_dme_set(hba, 494 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl); 495 } 496 497 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs) 498 { 499 struct ufs_hba *hba = ufs->hba; 500 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 501 const unsigned int div = 30, mult = 20; 502 const unsigned long pwm_min = 3 * 1000 * 1000; 503 const unsigned long pwm_max = 9 * 1000 * 1000; 504 const int divs[] = {32, 16, 8, 4}; 505 unsigned long clk = 0, _clk, clk_period; 506 int i = 0, clk_idx = -1; 507 508 clk_period = UNIPRO_PCLK_PERIOD(ufs); 509 for (i = 0; i < ARRAY_SIZE(divs); i++) { 510 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div); 511 if (_clk >= pwm_min && _clk <= pwm_max) { 512 if (_clk > clk) { 513 clk_idx = i; 514 clk = _clk; 515 } 516 } 517 } 518 519 if (clk_idx == -1) { 520 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx); 521 dev_err(hba->dev, 522 "failed to decide pwm clock divider, will not change\n"); 523 } 524 525 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK; 526 } 527 528 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period) 529 { 530 const int precise = 10; 531 long pclk_rate = ufs->pclk_rate; 532 long clk_period, fraction; 533 534 clk_period = UNIPRO_PCLK_PERIOD(ufs); 535 fraction = ((NSEC_PER_SEC % pclk_rate) * precise) / pclk_rate; 536 537 return (period * precise) / ((clk_period * precise) + fraction); 538 } 539 540 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs) 541 { 542 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 543 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; 544 545 t_cfg->tx_linereset_p = 546 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); 547 t_cfg->tx_linereset_n = 548 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec); 549 t_cfg->tx_high_z_cnt = 550 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec); 551 t_cfg->tx_base_n_val = 552 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec); 553 t_cfg->tx_gran_n_val = 554 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec); 555 t_cfg->tx_sleep_cnt = 556 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt); 557 558 t_cfg->rx_linereset = 559 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec); 560 t_cfg->rx_hibern8_wait = 561 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec); 562 t_cfg->rx_base_n_val = 563 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec); 564 t_cfg->rx_gran_n_val = 565 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec); 566 t_cfg->rx_sleep_cnt = 567 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt); 568 t_cfg->rx_stall_cnt = 569 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt); 570 } 571 572 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs) 573 { 574 struct ufs_hba *hba = ufs->hba; 575 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; 576 int i; 577 578 exynos_ufs_set_pwm_clk_div(ufs); 579 580 exynos_ufs_enable_ov_tm(hba); 581 582 for_each_ufs_rx_lane(ufs, i) { 583 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), 584 ufs->drv_data->uic_attr->rx_filler_enable); 585 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), 586 RX_LINERESET(t_cfg->rx_linereset)); 587 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), 588 RX_BASE_NVAL_L(t_cfg->rx_base_n_val)); 589 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), 590 RX_BASE_NVAL_H(t_cfg->rx_base_n_val)); 591 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), 592 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val)); 593 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), 594 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val)); 595 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), 596 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt)); 597 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), 598 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt)); 599 } 600 601 for_each_ufs_tx_lane(ufs, i) { 602 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), 603 TX_LINERESET_P(t_cfg->tx_linereset_p)); 604 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), 605 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt)); 606 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), 607 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt)); 608 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), 609 TX_BASE_NVAL_L(t_cfg->tx_base_n_val)); 610 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), 611 TX_BASE_NVAL_H(t_cfg->tx_base_n_val)); 612 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), 613 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val)); 614 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), 615 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val)); 616 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), 617 TX_OV_H8_ENTER_EN | 618 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt)); 619 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), 620 ufs->drv_data->uic_attr->tx_min_activatetime); 621 } 622 623 exynos_ufs_disable_ov_tm(hba); 624 } 625 626 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs) 627 { 628 struct ufs_hba *hba = ufs->hba; 629 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 630 int i; 631 632 exynos_ufs_enable_ov_tm(hba); 633 634 for_each_ufs_rx_lane(ufs, i) { 635 ufshcd_dme_set(hba, 636 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i), 637 attr->rx_hs_g1_sync_len_cap); 638 ufshcd_dme_set(hba, 639 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i), 640 attr->rx_hs_g2_sync_len_cap); 641 ufshcd_dme_set(hba, 642 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i), 643 attr->rx_hs_g3_sync_len_cap); 644 ufshcd_dme_set(hba, 645 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i), 646 attr->rx_hs_g1_prep_sync_len_cap); 647 ufshcd_dme_set(hba, 648 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i), 649 attr->rx_hs_g2_prep_sync_len_cap); 650 ufshcd_dme_set(hba, 651 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i), 652 attr->rx_hs_g3_prep_sync_len_cap); 653 } 654 655 if (attr->rx_adv_fine_gran_sup_en == 0) { 656 for_each_ufs_rx_lane(ufs, i) { 657 ufshcd_dme_set(hba, 658 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0); 659 660 if (attr->rx_min_actv_time_cap) 661 ufshcd_dme_set(hba, 662 UIC_ARG_MIB_SEL( 663 RX_MIN_ACTIVATETIME_CAPABILITY, i), 664 attr->rx_min_actv_time_cap); 665 666 if (attr->rx_hibern8_time_cap) 667 ufshcd_dme_set(hba, 668 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i), 669 attr->rx_hibern8_time_cap); 670 } 671 } else if (attr->rx_adv_fine_gran_sup_en == 1) { 672 for_each_ufs_rx_lane(ufs, i) { 673 if (attr->rx_adv_fine_gran_step) 674 ufshcd_dme_set(hba, 675 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, 676 i), RX_ADV_FINE_GRAN_STEP( 677 attr->rx_adv_fine_gran_step)); 678 679 if (attr->rx_adv_min_actv_time_cap) 680 ufshcd_dme_set(hba, 681 UIC_ARG_MIB_SEL( 682 RX_ADV_MIN_ACTIVATETIME_CAP, i), 683 attr->rx_adv_min_actv_time_cap); 684 685 if (attr->rx_adv_hibern8_time_cap) 686 ufshcd_dme_set(hba, 687 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP, 688 i), 689 attr->rx_adv_hibern8_time_cap); 690 } 691 } 692 693 exynos_ufs_disable_ov_tm(hba); 694 } 695 696 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs) 697 { 698 struct ufs_hba *hba = ufs->hba; 699 enum { 700 DEV_ID = 0x00, 701 PEER_DEV_ID = 0x01, 702 PEER_CPORT_ID = 0x00, 703 TRAFFIC_CLASS = 0x00, 704 }; 705 706 /* allow cport attributes to be set */ 707 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE); 708 709 /* local unipro attributes */ 710 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID); 711 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), true); 712 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID); 713 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID); 714 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS); 715 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS); 716 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); 717 } 718 719 static void exynos_ufs_config_smu(struct exynos_ufs *ufs) 720 { 721 u32 reg, val; 722 723 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); 724 725 /* make encryption disabled by default */ 726 reg = ufsp_readl(ufs, UFSPRSECURITY); 727 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY); 728 ufsp_writel(ufs, 0x0, UFSPSBEGIN0); 729 ufsp_writel(ufs, 0xffffffff, UFSPSEND0); 730 ufsp_writel(ufs, 0xff, UFSPSLUN0); 731 ufsp_writel(ufs, 0xf1, UFSPSCTRL0); 732 733 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); 734 } 735 736 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs, 737 struct ufs_pa_layer_attr *pwr) 738 { 739 struct ufs_hba *hba = ufs->hba; 740 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx); 741 u32 mask, sync_len; 742 enum { 743 SYNC_LEN_G1 = 80 * 1000, /* 80us */ 744 SYNC_LEN_G2 = 40 * 1000, /* 44us */ 745 SYNC_LEN_G3 = 20 * 1000, /* 20us */ 746 }; 747 int i; 748 749 if (g == 1) 750 sync_len = SYNC_LEN_G1; 751 else if (g == 2) 752 sync_len = SYNC_LEN_G2; 753 else if (g == 3) 754 sync_len = SYNC_LEN_G3; 755 else 756 return; 757 758 mask = exynos_ufs_calc_time_cntr(ufs, sync_len); 759 mask = (mask >> 8) & 0xff; 760 761 exynos_ufs_enable_ov_tm(hba); 762 763 for_each_ufs_rx_lane(ufs, i) 764 ufshcd_dme_set(hba, 765 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask); 766 767 exynos_ufs_disable_ov_tm(hba); 768 } 769 770 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, 771 struct ufs_pa_layer_attr *dev_max_params, 772 struct ufs_pa_layer_attr *dev_req_params) 773 { 774 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 775 struct phy *generic_phy = ufs->phy; 776 struct ufs_host_params host_params; 777 int ret; 778 779 if (!dev_req_params) { 780 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 781 ret = -EINVAL; 782 goto out; 783 } 784 785 ufshcd_init_host_params(&host_params); 786 787 ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params); 788 if (ret) { 789 pr_err("%s: failed to determine capabilities\n", __func__); 790 goto out; 791 } 792 793 if (ufs->drv_data->pre_pwr_change) 794 ufs->drv_data->pre_pwr_change(ufs, dev_req_params); 795 796 if (ufshcd_is_hs_mode(dev_req_params)) { 797 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params); 798 799 switch (dev_req_params->hs_rate) { 800 case PA_HS_MODE_A: 801 case PA_HS_MODE_B: 802 phy_calibrate(generic_phy); 803 break; 804 } 805 } 806 807 /* setting for three timeout values for traffic class #0 */ 808 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064); 809 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224); 810 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160); 811 812 return 0; 813 out: 814 return ret; 815 } 816 817 #define PWR_MODE_STR_LEN 64 818 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba, 819 struct ufs_pa_layer_attr *pwr_req) 820 { 821 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 822 struct phy *generic_phy = ufs->phy; 823 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx); 824 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx); 825 char pwr_str[PWR_MODE_STR_LEN] = ""; 826 827 /* let default be PWM Gear 1, Lane 1 */ 828 if (!gear) 829 gear = 1; 830 831 if (!lanes) 832 lanes = 1; 833 834 if (ufs->drv_data->post_pwr_change) 835 ufs->drv_data->post_pwr_change(ufs, pwr_req); 836 837 if ((ufshcd_is_hs_mode(pwr_req))) { 838 switch (pwr_req->hs_rate) { 839 case PA_HS_MODE_A: 840 case PA_HS_MODE_B: 841 phy_calibrate(generic_phy); 842 break; 843 } 844 845 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s series_%s G_%d L_%d", 846 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B", 847 gear, lanes); 848 } else { 849 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s G_%d L_%d", 850 "SLOW", gear, lanes); 851 } 852 853 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); 854 855 return 0; 856 } 857 858 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba, 859 int tag, bool is_scsi_cmd) 860 { 861 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 862 u32 type; 863 864 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE); 865 866 if (is_scsi_cmd) 867 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE); 868 else 869 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE); 870 } 871 872 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba, 873 int tag, u8 func) 874 { 875 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 876 u32 type; 877 878 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE); 879 880 switch (func) { 881 case UFS_ABORT_TASK: 882 case UFS_QUERY_TASK: 883 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE); 884 break; 885 case UFS_ABORT_TASK_SET: 886 case UFS_CLEAR_TASK_SET: 887 case UFS_LOGICAL_RESET: 888 case UFS_QUERY_TASK_SET: 889 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE); 890 break; 891 } 892 } 893 894 static int exynos_ufs_phy_init(struct exynos_ufs *ufs) 895 { 896 struct ufs_hba *hba = ufs->hba; 897 struct phy *generic_phy = ufs->phy; 898 int ret = 0; 899 900 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) { 901 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES), 902 &ufs->avail_ln_rx); 903 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES), 904 &ufs->avail_ln_tx); 905 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx, 906 "available data lane is not equal(rx:%d, tx:%d)\n", 907 ufs->avail_ln_rx, ufs->avail_ln_tx); 908 } 909 910 phy_set_bus_width(generic_phy, ufs->avail_ln_rx); 911 ret = phy_init(generic_phy); 912 if (ret) { 913 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 914 __func__, ret); 915 return ret; 916 } 917 918 ret = phy_power_on(generic_phy); 919 if (ret) 920 goto out_exit_phy; 921 922 return 0; 923 924 out_exit_phy: 925 phy_exit(generic_phy); 926 927 return ret; 928 } 929 930 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs) 931 { 932 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 933 struct ufs_hba *hba = ufs->hba; 934 935 if (attr->pa_dbg_clk_period_off) 936 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), 937 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 938 939 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), 940 ufs->drv_data->uic_attr->tx_trailingclks); 941 942 if (attr->pa_dbg_opt_suite1_off) 943 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 944 attr->pa_dbg_opt_suite1_val); 945 946 if (attr->pa_dbg_opt_suite2_off) 947 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off), 948 attr->pa_dbg_opt_suite2_val); 949 } 950 951 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index) 952 { 953 switch (index) { 954 case UNIPRO_L1_5: 955 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER); 956 break; 957 case UNIPRO_L2: 958 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER); 959 break; 960 case UNIPRO_L3: 961 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER); 962 break; 963 case UNIPRO_L4: 964 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER); 965 break; 966 case UNIPRO_DME: 967 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER); 968 break; 969 } 970 } 971 972 static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on, 973 enum ufs_notify_change_status status) 974 { 975 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 976 977 if (!ufs) 978 return 0; 979 980 if (on && status == PRE_CHANGE) { 981 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 982 exynos_ufs_disable_auto_ctrl_hcc(ufs); 983 exynos_ufs_ungate_clks(ufs); 984 } else if (!on && status == POST_CHANGE) { 985 exynos_ufs_gate_clks(ufs); 986 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 987 exynos_ufs_enable_auto_ctrl_hcc(ufs); 988 } 989 990 return 0; 991 } 992 993 static int exynos_ufs_pre_link(struct ufs_hba *hba) 994 { 995 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 996 997 /* hci */ 998 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2); 999 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3); 1000 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4); 1001 exynos_ufs_set_unipro_pclk_div(ufs); 1002 1003 /* unipro */ 1004 exynos_ufs_config_unipro(ufs); 1005 1006 /* m-phy */ 1007 exynos_ufs_phy_init(ufs); 1008 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) { 1009 exynos_ufs_config_phy_time_attr(ufs); 1010 exynos_ufs_config_phy_cap_attr(ufs); 1011 } 1012 1013 exynos_ufs_setup_clocks(hba, true, PRE_CHANGE); 1014 1015 if (ufs->drv_data->pre_link) 1016 ufs->drv_data->pre_link(ufs); 1017 1018 return 0; 1019 } 1020 1021 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs) 1022 { 1023 u32 val; 1024 1025 /* Select function clock (mclk) for timer tick */ 1026 if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) { 1027 val = hci_readl(ufs, HCI_V2P1_CTRL); 1028 val |= IA_TICK_SEL; 1029 hci_writel(ufs, val, HCI_V2P1_CTRL); 1030 } 1031 1032 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL); 1033 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL); 1034 } 1035 1036 static int exynos_ufs_post_link(struct ufs_hba *hba) 1037 { 1038 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1039 struct phy *generic_phy = ufs->phy; 1040 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1041 1042 exynos_ufs_establish_connt(ufs); 1043 exynos_ufs_fit_aggr_timeout(ufs); 1044 1045 hci_writel(ufs, 0xa, HCI_DATA_REORDER); 1046 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_TXPRDT_ENTRY_SIZE); 1047 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_RXPRDT_ENTRY_SIZE); 1048 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); 1049 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); 1050 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN); 1051 1052 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB) 1053 ufshcd_dme_set(hba, 1054 UIC_ARG_MIB(T_DBG_SKIP_INIT_HIBERN8_EXIT), true); 1055 1056 if (attr->pa_granularity) { 1057 exynos_ufs_enable_dbg_mode(hba); 1058 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY), 1059 attr->pa_granularity); 1060 exynos_ufs_disable_dbg_mode(hba); 1061 1062 if (attr->pa_tactivate) 1063 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 1064 attr->pa_tactivate); 1065 if (attr->pa_hibern8time && 1066 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER)) 1067 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1068 attr->pa_hibern8time); 1069 } 1070 1071 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { 1072 if (!attr->pa_granularity) 1073 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 1074 &attr->pa_granularity); 1075 if (!attr->pa_hibern8time) 1076 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1077 &attr->pa_hibern8time); 1078 /* 1079 * not wait for HIBERN8 time to exit hibernation 1080 */ 1081 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0); 1082 1083 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) { 1084 /* Valid range for granularity: 1 ~ 6 */ 1085 dev_warn(hba->dev, 1086 "%s: pa_granularity %d is invalid, assuming backwards compatibility\n", 1087 __func__, 1088 attr->pa_granularity); 1089 attr->pa_granularity = 6; 1090 } 1091 } 1092 1093 phy_calibrate(generic_phy); 1094 1095 if (ufs->drv_data->post_link) 1096 ufs->drv_data->post_link(ufs); 1097 1098 return 0; 1099 } 1100 1101 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs) 1102 { 1103 struct device_node *np = dev->of_node; 1104 struct exynos_ufs_uic_attr *attr; 1105 int ret = 0; 1106 1107 ufs->drv_data = device_get_match_data(dev); 1108 1109 if (ufs->drv_data && ufs->drv_data->uic_attr) { 1110 attr = ufs->drv_data->uic_attr; 1111 } else { 1112 dev_err(dev, "failed to get uic attributes\n"); 1113 ret = -EINVAL; 1114 goto out; 1115 } 1116 1117 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); 1118 if (IS_ERR(ufs->sysreg)) 1119 ufs->sysreg = NULL; 1120 else { 1121 if (of_property_read_u32_index(np, "samsung,sysreg", 1, 1122 &ufs->shareability_reg_offset)) { 1123 dev_warn(dev, "can't get an offset from sysreg. Set to default value\n"); 1124 ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET; 1125 } 1126 } 1127 1128 ufs->pclk_avail_min = PCLK_AVAIL_MIN; 1129 ufs->pclk_avail_max = PCLK_AVAIL_MAX; 1130 1131 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN; 1132 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL; 1133 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP; 1134 attr->pa_granularity = PA_GRANULARITY_VAL; 1135 attr->pa_tactivate = PA_TACTIVATE_VAL; 1136 attr->pa_hibern8time = PA_HIBERN8TIME_VAL; 1137 1138 out: 1139 return ret; 1140 } 1141 1142 static inline void exynos_ufs_priv_init(struct ufs_hba *hba, 1143 struct exynos_ufs *ufs) 1144 { 1145 ufs->hba = hba; 1146 ufs->opts = ufs->drv_data->opts; 1147 ufs->rx_sel_idx = PA_MAXDATALANES; 1148 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX) 1149 ufs->rx_sel_idx = 0; 1150 hba->priv = (void *)ufs; 1151 hba->quirks = ufs->drv_data->quirks; 1152 } 1153 1154 static int exynos_ufs_init(struct ufs_hba *hba) 1155 { 1156 struct device *dev = hba->dev; 1157 struct platform_device *pdev = to_platform_device(dev); 1158 struct exynos_ufs *ufs; 1159 int ret; 1160 1161 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); 1162 if (!ufs) 1163 return -ENOMEM; 1164 1165 /* exynos-specific hci */ 1166 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); 1167 if (IS_ERR(ufs->reg_hci)) { 1168 dev_err(dev, "cannot ioremap for hci vendor register\n"); 1169 return PTR_ERR(ufs->reg_hci); 1170 } 1171 1172 /* unipro */ 1173 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro"); 1174 if (IS_ERR(ufs->reg_unipro)) { 1175 dev_err(dev, "cannot ioremap for unipro register\n"); 1176 return PTR_ERR(ufs->reg_unipro); 1177 } 1178 1179 /* ufs protector */ 1180 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp"); 1181 if (IS_ERR(ufs->reg_ufsp)) { 1182 dev_err(dev, "cannot ioremap for ufs protector register\n"); 1183 return PTR_ERR(ufs->reg_ufsp); 1184 } 1185 1186 ret = exynos_ufs_parse_dt(dev, ufs); 1187 if (ret) { 1188 dev_err(dev, "failed to get dt info.\n"); 1189 goto out; 1190 } 1191 1192 ufs->phy = devm_phy_get(dev, "ufs-phy"); 1193 if (IS_ERR(ufs->phy)) { 1194 ret = PTR_ERR(ufs->phy); 1195 dev_err(dev, "failed to get ufs-phy\n"); 1196 goto out; 1197 } 1198 1199 exynos_ufs_priv_init(hba, ufs); 1200 1201 if (ufs->drv_data->drv_init) { 1202 ret = ufs->drv_data->drv_init(dev, ufs); 1203 if (ret) { 1204 dev_err(dev, "failed to init drv-data\n"); 1205 goto out; 1206 } 1207 } 1208 1209 ret = exynos_ufs_get_clk_info(ufs); 1210 if (ret) 1211 goto out; 1212 exynos_ufs_specify_phy_time_attr(ufs); 1213 if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) 1214 exynos_ufs_config_smu(ufs); 1215 1216 hba->host->dma_alignment = SZ_4K - 1; 1217 return 0; 1218 1219 out: 1220 hba->priv = NULL; 1221 return ret; 1222 } 1223 1224 static int exynos_ufs_host_reset(struct ufs_hba *hba) 1225 { 1226 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1227 unsigned long timeout = jiffies + msecs_to_jiffies(1); 1228 u32 val; 1229 int ret = 0; 1230 1231 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); 1232 1233 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST); 1234 1235 do { 1236 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK)) 1237 goto out; 1238 } while (time_before(jiffies, timeout)); 1239 1240 dev_err(hba->dev, "timeout host sw-reset\n"); 1241 ret = -ETIMEDOUT; 1242 1243 out: 1244 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); 1245 return ret; 1246 } 1247 1248 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba) 1249 { 1250 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1251 1252 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT); 1253 udelay(5); 1254 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT); 1255 } 1256 1257 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, u8 enter) 1258 { 1259 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1260 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1261 1262 if (!enter) { 1263 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1264 exynos_ufs_disable_auto_ctrl_hcc(ufs); 1265 exynos_ufs_ungate_clks(ufs); 1266 1267 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { 1268 static const unsigned int granularity_tbl[] = { 1269 1, 4, 8, 16, 32, 100 1270 }; 1271 int h8_time = attr->pa_hibern8time * 1272 granularity_tbl[attr->pa_granularity - 1]; 1273 unsigned long us; 1274 s64 delta; 1275 1276 do { 1277 delta = h8_time - ktime_us_delta(ktime_get(), 1278 ufs->entry_hibern8_t); 1279 if (delta <= 0) 1280 break; 1281 1282 us = min_t(s64, delta, USEC_PER_MSEC); 1283 if (us >= 10) 1284 usleep_range(us, us + 10); 1285 } while (1); 1286 } 1287 } 1288 } 1289 1290 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, u8 enter) 1291 { 1292 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1293 1294 if (!enter) { 1295 u32 cur_mode = 0; 1296 u32 pwrmode; 1297 1298 if (ufshcd_is_hs_mode(&ufs->dev_req_params)) 1299 pwrmode = FAST_MODE; 1300 else 1301 pwrmode = SLOW_MODE; 1302 1303 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode); 1304 if (cur_mode != (pwrmode << 4 | pwrmode)) { 1305 dev_warn(hba->dev, "%s: power mode change\n", __func__); 1306 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf; 1307 hba->pwr_info.pwr_tx = cur_mode & 0xf; 1308 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 1309 } 1310 1311 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)) 1312 exynos_ufs_establish_connt(ufs); 1313 } else { 1314 ufs->entry_hibern8_t = ktime_get(); 1315 exynos_ufs_gate_clks(ufs); 1316 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) 1317 exynos_ufs_enable_auto_ctrl_hcc(ufs); 1318 } 1319 } 1320 1321 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba, 1322 enum ufs_notify_change_status status) 1323 { 1324 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1325 int ret = 0; 1326 1327 switch (status) { 1328 case PRE_CHANGE: 1329 /* 1330 * The maximum segment size must be set after scsi_host_alloc() 1331 * has been called and before LUN scanning starts 1332 * (ufshcd_async_scan()). Note: this callback may also be called 1333 * from other functions than ufshcd_init(). 1334 */ 1335 hba->host->max_segment_size = SZ_4K; 1336 1337 if (ufs->drv_data->pre_hce_enable) { 1338 ret = ufs->drv_data->pre_hce_enable(ufs); 1339 if (ret) 1340 return ret; 1341 } 1342 1343 ret = exynos_ufs_host_reset(hba); 1344 if (ret) 1345 return ret; 1346 exynos_ufs_dev_hw_reset(hba); 1347 break; 1348 case POST_CHANGE: 1349 exynos_ufs_calc_pwm_clk_div(ufs); 1350 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)) 1351 exynos_ufs_enable_auto_ctrl_hcc(ufs); 1352 1353 if (ufs->drv_data->post_hce_enable) 1354 ret = ufs->drv_data->post_hce_enable(ufs); 1355 1356 break; 1357 } 1358 1359 return ret; 1360 } 1361 1362 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba, 1363 enum ufs_notify_change_status status) 1364 { 1365 int ret = 0; 1366 1367 switch (status) { 1368 case PRE_CHANGE: 1369 ret = exynos_ufs_pre_link(hba); 1370 break; 1371 case POST_CHANGE: 1372 ret = exynos_ufs_post_link(hba); 1373 break; 1374 } 1375 1376 return ret; 1377 } 1378 1379 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, 1380 enum ufs_notify_change_status status, 1381 struct ufs_pa_layer_attr *dev_max_params, 1382 struct ufs_pa_layer_attr *dev_req_params) 1383 { 1384 int ret = 0; 1385 1386 switch (status) { 1387 case PRE_CHANGE: 1388 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params, 1389 dev_req_params); 1390 break; 1391 case POST_CHANGE: 1392 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params); 1393 break; 1394 } 1395 1396 return ret; 1397 } 1398 1399 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba, 1400 enum uic_cmd_dme enter, 1401 enum ufs_notify_change_status notify) 1402 { 1403 switch ((u8)notify) { 1404 case PRE_CHANGE: 1405 exynos_ufs_pre_hibern8(hba, enter); 1406 break; 1407 case POST_CHANGE: 1408 exynos_ufs_post_hibern8(hba, enter); 1409 break; 1410 } 1411 } 1412 1413 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 1414 enum ufs_notify_change_status status) 1415 { 1416 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1417 1418 if (status == PRE_CHANGE) 1419 return 0; 1420 1421 if (!ufshcd_is_link_active(hba)) 1422 phy_power_off(ufs->phy); 1423 1424 return 0; 1425 } 1426 1427 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 1428 { 1429 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1430 1431 if (!ufshcd_is_link_active(hba)) 1432 phy_power_on(ufs->phy); 1433 1434 exynos_ufs_config_smu(ufs); 1435 1436 return 0; 1437 } 1438 1439 static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba, 1440 enum ufs_notify_change_status status) 1441 { 1442 if (status == POST_CHANGE) { 1443 ufshcd_set_link_active(hba); 1444 ufshcd_set_ufs_dev_active(hba); 1445 } 1446 1447 return 0; 1448 } 1449 1450 static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba) 1451 { 1452 u32 mbox; 1453 ktime_t start, stop; 1454 1455 start = ktime_get(); 1456 stop = ktime_add(start, ms_to_ktime(PH_READY_TIMEOUT_MS)); 1457 1458 do { 1459 mbox = ufshcd_readl(hba, PH2VH_MBOX); 1460 /* TODO: Mailbox message protocols between the PH and VHs are 1461 * not implemented yet. This will be supported later 1462 */ 1463 if ((mbox & MH_MSG_MASK) == MH_MSG_PH_READY) 1464 return 0; 1465 1466 usleep_range(40, 50); 1467 } while (ktime_before(ktime_get(), stop)); 1468 1469 return -ETIME; 1470 } 1471 1472 static int exynosauto_ufs_vh_init(struct ufs_hba *hba) 1473 { 1474 struct device *dev = hba->dev; 1475 struct platform_device *pdev = to_platform_device(dev); 1476 struct exynos_ufs *ufs; 1477 int ret; 1478 1479 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); 1480 if (!ufs) 1481 return -ENOMEM; 1482 1483 /* exynos-specific hci */ 1484 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); 1485 if (IS_ERR(ufs->reg_hci)) { 1486 dev_err(dev, "cannot ioremap for hci vendor register\n"); 1487 return PTR_ERR(ufs->reg_hci); 1488 } 1489 1490 ret = exynosauto_ufs_vh_wait_ph_ready(hba); 1491 if (ret) 1492 return ret; 1493 1494 ufs->drv_data = device_get_match_data(dev); 1495 if (!ufs->drv_data) 1496 return -ENODEV; 1497 1498 exynos_ufs_priv_init(hba, ufs); 1499 1500 return 0; 1501 } 1502 1503 static int fsd_ufs_pre_link(struct exynos_ufs *ufs) 1504 { 1505 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; 1506 struct ufs_hba *hba = ufs->hba; 1507 int i; 1508 1509 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), 1510 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1511 ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12); 1512 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1513 1514 for_each_ufs_tx_lane(ufs, i) { 1515 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1516 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1517 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F); 1518 } 1519 1520 for_each_ufs_rx_lane(ufs, i) { 1521 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1522 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1523 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38); 1524 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0); 1525 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1); 1526 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1); 1527 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0); 1528 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0); 1529 } 1530 1531 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1532 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20); 1533 1534 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), 1535 0x2e820183); 1536 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 1537 1538 exynos_ufs_establish_connt(ufs); 1539 1540 return 0; 1541 } 1542 1543 static int fsd_ufs_post_link(struct exynos_ufs *ufs) 1544 { 1545 int i; 1546 struct ufs_hba *hba = ufs->hba; 1547 u32 hw_cap_min_tactivate; 1548 u32 peer_rx_min_actv_time_cap; 1549 u32 max_rx_hibern8_time_cap; 1550 1551 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4), 1552 &hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */ 1553 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 1554 &peer_rx_min_actv_time_cap); /* PA_TActivate */ 1555 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 1556 &max_rx_hibern8_time_cap); /* PA_Hibern8Time */ 1557 1558 if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate) 1559 ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 1560 peer_rx_min_actv_time_cap + 1); 1561 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), max_rx_hibern8_time_cap + 1); 1562 1563 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x01); 1564 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xFA); 1565 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x00); 1566 1567 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1568 1569 for_each_ufs_rx_lane(ufs, i) { 1570 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05); 1571 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01); 1572 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02); 1573 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC); 1574 } 1575 1576 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1577 1578 return 0; 1579 } 1580 1581 static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs, 1582 struct ufs_pa_layer_attr *pwr) 1583 { 1584 struct ufs_hba *hba = ufs->hba; 1585 1586 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1); 1587 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1); 1588 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 1589 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 1590 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 1591 1592 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0); 1593 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1); 1594 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2); 1595 1596 return 0; 1597 } 1598 1599 static inline u32 get_mclk_period_unipro_18(struct exynos_ufs *ufs) 1600 { 1601 return (16 * 1000 * 1000000UL / ufs->mclk_rate); 1602 } 1603 1604 static int gs101_ufs_pre_link(struct exynos_ufs *ufs) 1605 { 1606 struct ufs_hba *hba = ufs->hba; 1607 int i; 1608 u32 tx_line_reset_period, rx_line_reset_period; 1609 1610 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) 1611 / NSEC_PER_MSEC; 1612 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) 1613 / NSEC_PER_MSEC; 1614 1615 unipro_writel(ufs, get_mclk_period_unipro_18(ufs), COMP_CLK_PERIOD); 1616 1617 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); 1618 1619 for_each_ufs_rx_lane(ufs, i) { 1620 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), 1621 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1622 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); 1623 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), 1624 (rx_line_reset_period >> 16) & 0xFF); 1625 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), 1626 (rx_line_reset_period >> 8) & 0xFF); 1627 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), 1628 (rx_line_reset_period) & 0xFF); 1629 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69); 1630 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); 1631 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); 1632 } 1633 1634 for_each_ufs_tx_lane(ufs, i) { 1635 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), 1636 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); 1637 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), 1638 0x02); 1639 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), 1640 (tx_line_reset_period >> 16) & 0xFF); 1641 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), 1642 (tx_line_reset_period >> 8) & 0xFF); 1643 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), 1644 (tx_line_reset_period) & 0xFF); 1645 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 1); 1646 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7F, i), 0); 1647 } 1648 1649 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); 1650 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); 1651 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), 0x0); 1652 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), 0x1); 1653 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), 0x1); 1654 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); 1655 ufshcd_dme_set(hba, UIC_ARG_MIB(0xA006), 0x8000); 1656 1657 return 0; 1658 } 1659 1660 static int gs101_ufs_post_link(struct exynos_ufs *ufs) 1661 { 1662 struct ufs_hba *hba = ufs->hba; 1663 1664 exynos_ufs_enable_dbg_mode(hba); 1665 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8); 1666 exynos_ufs_disable_dbg_mode(hba); 1667 1668 return 0; 1669 } 1670 1671 static int gs101_ufs_pre_pwr_change(struct exynos_ufs *ufs, 1672 struct ufs_pa_layer_attr *pwr) 1673 { 1674 struct ufs_hba *hba = ufs->hba; 1675 1676 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); 1677 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); 1678 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); 1679 unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0); 1680 unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1); 1681 unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2); 1682 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0); 1683 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1); 1684 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2); 1685 1686 return 0; 1687 } 1688 1689 static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = { 1690 .name = "exynos_ufs", 1691 .init = exynos_ufs_init, 1692 .hce_enable_notify = exynos_ufs_hce_enable_notify, 1693 .link_startup_notify = exynos_ufs_link_startup_notify, 1694 .pwr_change_notify = exynos_ufs_pwr_change_notify, 1695 .setup_clocks = exynos_ufs_setup_clocks, 1696 .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req, 1697 .setup_task_mgmt = exynos_ufs_specify_nexus_t_tm_req, 1698 .hibern8_notify = exynos_ufs_hibern8_notify, 1699 .suspend = exynos_ufs_suspend, 1700 .resume = exynos_ufs_resume, 1701 }; 1702 1703 static struct ufs_hba_variant_ops ufs_hba_exynosauto_vh_ops = { 1704 .name = "exynosauto_ufs_vh", 1705 .init = exynosauto_ufs_vh_init, 1706 .link_startup_notify = exynosauto_ufs_vh_link_startup_notify, 1707 }; 1708 1709 static int exynos_ufs_probe(struct platform_device *pdev) 1710 { 1711 int err; 1712 struct device *dev = &pdev->dev; 1713 const struct ufs_hba_variant_ops *vops = &ufs_hba_exynos_ops; 1714 const struct exynos_ufs_drv_data *drv_data = 1715 device_get_match_data(dev); 1716 1717 if (drv_data && drv_data->vops) 1718 vops = drv_data->vops; 1719 1720 err = ufshcd_pltfrm_init(pdev, vops); 1721 if (err) 1722 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err); 1723 1724 return err; 1725 } 1726 1727 static void exynos_ufs_remove(struct platform_device *pdev) 1728 { 1729 struct ufs_hba *hba = platform_get_drvdata(pdev); 1730 struct exynos_ufs *ufs = ufshcd_get_variant(hba); 1731 1732 pm_runtime_get_sync(&(pdev)->dev); 1733 ufshcd_remove(hba); 1734 1735 phy_power_off(ufs->phy); 1736 phy_exit(ufs->phy); 1737 } 1738 1739 static struct exynos_ufs_uic_attr exynos7_uic_attr = { 1740 .tx_trailingclks = 0x10, 1741 .tx_dif_p_nsec = 3000000, /* unit: ns */ 1742 .tx_dif_n_nsec = 1000000, /* unit: ns */ 1743 .tx_high_z_cnt_nsec = 20000, /* unit: ns */ 1744 .tx_base_unit_nsec = 100000, /* unit: ns */ 1745 .tx_gran_unit_nsec = 4000, /* unit: ns */ 1746 .tx_sleep_cnt = 1000, /* unit: ns */ 1747 .tx_min_activatetime = 0xa, 1748 .rx_filler_enable = 0x2, 1749 .rx_dif_p_nsec = 1000000, /* unit: ns */ 1750 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ 1751 .rx_base_unit_nsec = 100000, /* unit: ns */ 1752 .rx_gran_unit_nsec = 4000, /* unit: ns */ 1753 .rx_sleep_cnt = 1280, /* unit: ns */ 1754 .rx_stall_cnt = 320, /* unit: ns */ 1755 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), 1756 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), 1757 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), 1758 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), 1759 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), 1760 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), 1761 .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, 1762 .pa_dbg_opt_suite1_val = 0x30103, 1763 .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, 1764 }; 1765 1766 static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = { 1767 .uic_attr = &exynos7_uic_attr, 1768 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 1769 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 1770 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 1771 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 1772 .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 1773 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 1774 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 1775 .drv_init = exynosauto_ufs_drv_init, 1776 .post_hce_enable = exynosauto_ufs_post_hce_enable, 1777 .pre_link = exynosauto_ufs_pre_link, 1778 .pre_pwr_change = exynosauto_ufs_pre_pwr_change, 1779 .post_pwr_change = exynosauto_ufs_post_pwr_change, 1780 }; 1781 1782 static const struct exynos_ufs_drv_data exynosauto_ufs_vh_drvs = { 1783 .vops = &ufs_hba_exynosauto_vh_ops, 1784 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 1785 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 1786 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 1787 UFSHCI_QUIRK_BROKEN_HCE | 1788 UFSHCD_QUIRK_BROKEN_UIC_CMD | 1789 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION | 1790 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 1791 .opts = EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 1792 }; 1793 1794 static const struct exynos_ufs_drv_data exynos_ufs_drvs = { 1795 .uic_attr = &exynos7_uic_attr, 1796 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 1797 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 1798 UFSHCI_QUIRK_BROKEN_HCE | 1799 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 1800 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 1801 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | 1802 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 1803 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL | 1804 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 1805 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX | 1806 EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB | 1807 EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER, 1808 .drv_init = exynos7_ufs_drv_init, 1809 .pre_link = exynos7_ufs_pre_link, 1810 .post_link = exynos7_ufs_post_link, 1811 .pre_pwr_change = exynos7_ufs_pre_pwr_change, 1812 .post_pwr_change = exynos7_ufs_post_pwr_change, 1813 }; 1814 1815 static struct exynos_ufs_uic_attr gs101_uic_attr = { 1816 .tx_trailingclks = 0xff, 1817 .tx_dif_p_nsec = 3000000, /* unit: ns */ 1818 .tx_dif_n_nsec = 1000000, /* unit: ns */ 1819 .tx_high_z_cnt_nsec = 20000, /* unit: ns */ 1820 .tx_base_unit_nsec = 100000, /* unit: ns */ 1821 .tx_gran_unit_nsec = 4000, /* unit: ns */ 1822 .tx_sleep_cnt = 1000, /* unit: ns */ 1823 .tx_min_activatetime = 0xa, 1824 .rx_filler_enable = 0x2, 1825 .rx_dif_p_nsec = 1000000, /* unit: ns */ 1826 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ 1827 .rx_base_unit_nsec = 100000, /* unit: ns */ 1828 .rx_gran_unit_nsec = 4000, /* unit: ns */ 1829 .rx_sleep_cnt = 1280, /* unit: ns */ 1830 .rx_stall_cnt = 320, /* unit: ns */ 1831 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), 1832 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), 1833 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), 1834 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), 1835 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), 1836 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), 1837 .pa_dbg_opt_suite1_val = 0x90913C1C, 1838 .pa_dbg_opt_suite1_off = PA_GS101_DBG_OPTION_SUITE1, 1839 .pa_dbg_opt_suite2_val = 0xE01C115F, 1840 .pa_dbg_opt_suite2_off = PA_GS101_DBG_OPTION_SUITE2, 1841 }; 1842 1843 static struct exynos_ufs_uic_attr fsd_uic_attr = { 1844 .tx_trailingclks = 0x10, 1845 .tx_dif_p_nsec = 3000000, /* unit: ns */ 1846 .tx_dif_n_nsec = 1000000, /* unit: ns */ 1847 .tx_high_z_cnt_nsec = 20000, /* unit: ns */ 1848 .tx_base_unit_nsec = 100000, /* unit: ns */ 1849 .tx_gran_unit_nsec = 4000, /* unit: ns */ 1850 .tx_sleep_cnt = 1000, /* unit: ns */ 1851 .tx_min_activatetime = 0xa, 1852 .rx_filler_enable = 0x2, 1853 .rx_dif_p_nsec = 1000000, /* unit: ns */ 1854 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ 1855 .rx_base_unit_nsec = 100000, /* unit: ns */ 1856 .rx_gran_unit_nsec = 4000, /* unit: ns */ 1857 .rx_sleep_cnt = 1280, /* unit: ns */ 1858 .rx_stall_cnt = 320, /* unit: ns */ 1859 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), 1860 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), 1861 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), 1862 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), 1863 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), 1864 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), 1865 .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD, 1866 .pa_dbg_opt_suite1_val = 0x2E820183, 1867 .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE, 1868 }; 1869 1870 static const struct exynos_ufs_drv_data fsd_ufs_drvs = { 1871 .uic_attr = &fsd_uic_attr, 1872 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 1873 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 1874 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 1875 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING | 1876 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR, 1877 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL | 1878 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 1879 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 1880 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, 1881 .pre_link = fsd_ufs_pre_link, 1882 .post_link = fsd_ufs_post_link, 1883 .pre_pwr_change = fsd_ufs_pre_pwr_change, 1884 }; 1885 1886 static const struct exynos_ufs_drv_data gs101_ufs_drvs = { 1887 .uic_attr = &gs101_uic_attr, 1888 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | 1889 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR | 1890 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | 1891 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | 1892 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL | 1893 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING, 1894 .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | 1895 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | 1896 EXYNOS_UFS_OPT_UFSPR_SECURE | 1897 EXYNOS_UFS_OPT_TIMER_TICK_SELECT, 1898 .drv_init = exynosauto_ufs_drv_init, 1899 .pre_link = gs101_ufs_pre_link, 1900 .post_link = gs101_ufs_post_link, 1901 .pre_pwr_change = gs101_ufs_pre_pwr_change, 1902 }; 1903 1904 static const struct of_device_id exynos_ufs_of_match[] = { 1905 { .compatible = "google,gs101-ufs", 1906 .data = &gs101_ufs_drvs }, 1907 { .compatible = "samsung,exynos7-ufs", 1908 .data = &exynos_ufs_drvs }, 1909 { .compatible = "samsung,exynosautov9-ufs", 1910 .data = &exynosauto_ufs_drvs }, 1911 { .compatible = "samsung,exynosautov9-ufs-vh", 1912 .data = &exynosauto_ufs_vh_drvs }, 1913 { .compatible = "tesla,fsd-ufs", 1914 .data = &fsd_ufs_drvs }, 1915 {}, 1916 }; 1917 MODULE_DEVICE_TABLE(of, exynos_ufs_of_match); 1918 1919 static const struct dev_pm_ops exynos_ufs_pm_ops = { 1920 SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume) 1921 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 1922 .prepare = ufshcd_suspend_prepare, 1923 .complete = ufshcd_resume_complete, 1924 }; 1925 1926 static struct platform_driver exynos_ufs_pltform = { 1927 .probe = exynos_ufs_probe, 1928 .remove_new = exynos_ufs_remove, 1929 .driver = { 1930 .name = "exynos-ufshc", 1931 .pm = &exynos_ufs_pm_ops, 1932 .of_match_table = exynos_ufs_of_match, 1933 }, 1934 }; 1935 module_platform_driver(exynos_ufs_pltform); 1936 1937 MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>"); 1938 MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>"); 1939 MODULE_DESCRIPTION("Exynos UFS HCI Driver"); 1940 MODULE_LICENSE("GPL v2"); 1941