1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/pm_opp.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/sched/clock.h> 26 #include <linux/iopoll.h> 27 #include <scsi/scsi_cmnd.h> 28 #include <scsi/scsi_dbg.h> 29 #include <scsi/scsi_driver.h> 30 #include <scsi/scsi_eh.h> 31 #include "ufshcd-priv.h" 32 #include <ufs/ufs_quirks.h> 33 #include <ufs/unipro.h> 34 #include "ufs-sysfs.h" 35 #include "ufs-debugfs.h" 36 #include "ufs-fault-injection.h" 37 #include "ufs_bsg.h" 38 #include "ufshcd-crypto.h" 39 #include <linux/unaligned.h> 40 41 #define CREATE_TRACE_POINTS 42 #include "ufs_trace.h" 43 44 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 45 UTP_TASK_REQ_COMPL |\ 46 UFSHCD_ERROR_MASK) 47 48 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 49 UFSHCD_ERROR_MASK |\ 50 MCQ_CQ_EVENT_STATUS) 51 52 53 /* UIC command timeout, unit: ms */ 54 enum { 55 UIC_CMD_TIMEOUT_DEFAULT = 500, 56 UIC_CMD_TIMEOUT_MAX = 2000, 57 }; 58 /* NOP OUT retries waiting for NOP IN response */ 59 #define NOP_OUT_RETRIES 10 60 /* Timeout after 50 msecs if NOP OUT hangs without response */ 61 #define NOP_OUT_TIMEOUT 50 /* msecs */ 62 63 /* Query request retries */ 64 #define QUERY_REQ_RETRIES 3 65 /* Query request timeout */ 66 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 67 68 /* Advanced RPMB request timeout */ 69 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 70 71 /* Task management command timeout */ 72 #define TM_CMD_TIMEOUT 100 /* msecs */ 73 74 /* maximum number of retries for a general UIC command */ 75 #define UFS_UIC_COMMAND_RETRIES 3 76 77 /* maximum number of link-startup retries */ 78 #define DME_LINKSTARTUP_RETRIES 3 79 80 /* maximum number of reset retries before giving up */ 81 #define MAX_HOST_RESET_RETRIES 5 82 83 /* Maximum number of error handler retries before giving up */ 84 #define MAX_ERR_HANDLER_RETRIES 5 85 86 /* Expose the flag value from utp_upiu_query.value */ 87 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 88 89 /* Interrupt aggregation default timeout, unit: 40us */ 90 #define INT_AGGR_DEF_TO 0x02 91 92 /* default delay of autosuspend: 2000 ms */ 93 #define RPM_AUTOSUSPEND_DELAY_MS 2000 94 95 /* Default delay of RPM device flush delayed work */ 96 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 97 98 /* Default value of wait time before gating device ref clock */ 99 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 100 101 /* Polling time to wait for fDeviceInit */ 102 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 103 104 /* Default RTC update every 10 seconds */ 105 #define UFS_RTC_UPDATE_INTERVAL_MS (10 * MSEC_PER_SEC) 106 107 /* bMaxNumOfRTT is equal to two after device manufacturing */ 108 #define DEFAULT_MAX_NUM_RTT 2 109 110 /* UFSHC 4.0 compliant HC support this mode. */ 111 static bool use_mcq_mode = true; 112 113 static bool is_mcq_supported(struct ufs_hba *hba) 114 { 115 return hba->mcq_sup && use_mcq_mode; 116 } 117 118 module_param(use_mcq_mode, bool, 0644); 119 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 120 121 static unsigned int uic_cmd_timeout = UIC_CMD_TIMEOUT_DEFAULT; 122 123 static int uic_cmd_timeout_set(const char *val, const struct kernel_param *kp) 124 { 125 return param_set_uint_minmax(val, kp, UIC_CMD_TIMEOUT_DEFAULT, 126 UIC_CMD_TIMEOUT_MAX); 127 } 128 129 static const struct kernel_param_ops uic_cmd_timeout_ops = { 130 .set = uic_cmd_timeout_set, 131 .get = param_get_uint, 132 }; 133 134 module_param_cb(uic_cmd_timeout, &uic_cmd_timeout_ops, &uic_cmd_timeout, 0644); 135 MODULE_PARM_DESC(uic_cmd_timeout, 136 "UFS UIC command timeout in milliseconds. Defaults to 500ms. Supported values range from 500ms to 2 seconds inclusively"); 137 138 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 139 ({ \ 140 int _ret; \ 141 if (_on) \ 142 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 143 else \ 144 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 145 _ret; \ 146 }) 147 148 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 149 size_t __len = (len); \ 150 print_hex_dump(KERN_ERR, prefix_str, \ 151 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 152 16, 4, buf, __len, false); \ 153 } while (0) 154 155 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 156 const char *prefix) 157 { 158 u32 *regs; 159 size_t pos; 160 161 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 162 return -EINVAL; 163 164 regs = kzalloc(len, GFP_ATOMIC); 165 if (!regs) 166 return -ENOMEM; 167 168 for (pos = 0; pos < len; pos += 4) { 169 if (offset == 0 && 170 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 171 pos <= REG_UIC_ERROR_CODE_DME) 172 continue; 173 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 174 } 175 176 ufshcd_hex_dump(prefix, regs, len); 177 kfree(regs); 178 179 return 0; 180 } 181 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 182 183 enum { 184 UFSHCD_MAX_CHANNEL = 0, 185 UFSHCD_MAX_ID = 1, 186 }; 187 188 static const char *const ufshcd_state_name[] = { 189 [UFSHCD_STATE_RESET] = "reset", 190 [UFSHCD_STATE_OPERATIONAL] = "operational", 191 [UFSHCD_STATE_ERROR] = "error", 192 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 193 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 194 }; 195 196 /* UFSHCD error handling flags */ 197 enum { 198 UFSHCD_EH_IN_PROGRESS = (1 << 0), 199 }; 200 201 /* UFSHCD UIC layer error flags */ 202 enum { 203 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 204 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 205 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 206 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 207 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 208 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 209 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 210 }; 211 212 #define ufshcd_set_eh_in_progress(h) \ 213 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 214 #define ufshcd_eh_in_progress(h) \ 215 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 216 #define ufshcd_clear_eh_in_progress(h) \ 217 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 218 219 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 220 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 221 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 222 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 223 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 224 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 225 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 226 /* 227 * For DeepSleep, the link is first put in hibern8 and then off. 228 * Leaving the link in hibern8 is not supported. 229 */ 230 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 231 }; 232 233 static inline enum ufs_dev_pwr_mode 234 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 235 { 236 return ufs_pm_lvl_states[lvl].dev_state; 237 } 238 239 static inline enum uic_link_state 240 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 241 { 242 return ufs_pm_lvl_states[lvl].link_state; 243 } 244 245 static inline enum ufs_pm_level 246 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 247 enum uic_link_state link_state) 248 { 249 enum ufs_pm_level lvl; 250 251 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 252 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 253 (ufs_pm_lvl_states[lvl].link_state == link_state)) 254 return lvl; 255 } 256 257 /* if no match found, return the level 0 */ 258 return UFS_PM_LVL_0; 259 } 260 261 static bool ufshcd_is_ufs_dev_busy(struct ufs_hba *hba) 262 { 263 return (hba->clk_gating.active_reqs || hba->outstanding_reqs || hba->outstanding_tasks || 264 hba->active_uic_cmd || hba->uic_async_done); 265 } 266 267 static const struct ufs_dev_quirk ufs_fixups[] = { 268 /* UFS cards deviations table */ 269 { .wmanufacturerid = UFS_VENDOR_MICRON, 270 .model = UFS_ANY_MODEL, 271 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 272 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 273 .model = UFS_ANY_MODEL, 274 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 275 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 276 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 277 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 278 .model = UFS_ANY_MODEL, 279 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 280 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 281 .model = "hB8aL1" /*H28U62301AMR*/, 282 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 283 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 284 .model = UFS_ANY_MODEL, 285 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 286 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 287 .model = "THGLF2G9C8KBADG", 288 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 289 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 290 .model = "THGLF2G9D8KBADG", 291 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 292 {} 293 }; 294 295 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 296 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 297 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 298 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 299 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 300 static void ufshcd_hba_exit(struct ufs_hba *hba); 301 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params); 302 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 303 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 304 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 305 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 306 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 307 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 308 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 309 bool scale_up); 310 static irqreturn_t ufshcd_intr(int irq, void *__hba); 311 static int ufshcd_change_power_mode(struct ufs_hba *hba, 312 struct ufs_pa_layer_attr *pwr_mode); 313 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 314 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 315 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 316 struct ufs_vreg *vreg); 317 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 318 bool enable); 319 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 320 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 321 322 void ufshcd_enable_irq(struct ufs_hba *hba) 323 { 324 if (!hba->is_irq_enabled) { 325 enable_irq(hba->irq); 326 hba->is_irq_enabled = true; 327 } 328 } 329 EXPORT_SYMBOL_GPL(ufshcd_enable_irq); 330 331 void ufshcd_disable_irq(struct ufs_hba *hba) 332 { 333 if (hba->is_irq_enabled) { 334 disable_irq(hba->irq); 335 hba->is_irq_enabled = false; 336 } 337 } 338 EXPORT_SYMBOL_GPL(ufshcd_disable_irq); 339 340 static void ufshcd_configure_wb(struct ufs_hba *hba) 341 { 342 if (!ufshcd_is_wb_allowed(hba)) 343 return; 344 345 ufshcd_wb_toggle(hba, true); 346 347 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 348 349 if (ufshcd_is_wb_buf_flush_allowed(hba)) 350 ufshcd_wb_toggle_buf_flush(hba, true); 351 } 352 353 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 354 enum ufs_trace_str_t str_t) 355 { 356 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 357 struct utp_upiu_header *header; 358 359 if (!trace_ufshcd_upiu_enabled()) 360 return; 361 362 if (str_t == UFS_CMD_SEND) 363 header = &rq->header; 364 else 365 header = &hba->lrb[tag].ucd_rsp_ptr->header; 366 367 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 368 UFS_TSF_CDB); 369 } 370 371 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 372 enum ufs_trace_str_t str_t, 373 struct utp_upiu_req *rq_rsp) 374 { 375 if (!trace_ufshcd_upiu_enabled()) 376 return; 377 378 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 379 &rq_rsp->qr, UFS_TSF_OSF); 380 } 381 382 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 383 enum ufs_trace_str_t str_t) 384 { 385 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 386 387 if (!trace_ufshcd_upiu_enabled()) 388 return; 389 390 if (str_t == UFS_TM_SEND) 391 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 392 &descp->upiu_req.req_header, 393 &descp->upiu_req.input_param1, 394 UFS_TSF_TM_INPUT); 395 else 396 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 397 &descp->upiu_rsp.rsp_header, 398 &descp->upiu_rsp.output_param1, 399 UFS_TSF_TM_OUTPUT); 400 } 401 402 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 403 const struct uic_command *ucmd, 404 enum ufs_trace_str_t str_t) 405 { 406 u32 cmd; 407 408 if (!trace_ufshcd_uic_command_enabled()) 409 return; 410 411 if (str_t == UFS_CMD_SEND) 412 cmd = ucmd->command; 413 else 414 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 415 416 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 417 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 418 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 419 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 420 } 421 422 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 423 enum ufs_trace_str_t str_t) 424 { 425 u64 lba = 0; 426 u8 opcode = 0, group_id = 0; 427 u32 doorbell = 0; 428 u32 intr; 429 int hwq_id = -1; 430 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 431 struct scsi_cmnd *cmd = lrbp->cmd; 432 struct request *rq = scsi_cmd_to_rq(cmd); 433 int transfer_len = -1; 434 435 if (!cmd) 436 return; 437 438 /* trace UPIU also */ 439 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 440 if (!trace_ufshcd_command_enabled()) 441 return; 442 443 opcode = cmd->cmnd[0]; 444 445 if (opcode == READ_10 || opcode == WRITE_10) { 446 /* 447 * Currently we only fully trace read(10) and write(10) commands 448 */ 449 transfer_len = 450 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 451 lba = scsi_get_lba(cmd); 452 if (opcode == WRITE_10) 453 group_id = lrbp->cmd->cmnd[6]; 454 } else if (opcode == UNMAP) { 455 /* 456 * The number of Bytes to be unmapped beginning with the lba. 457 */ 458 transfer_len = blk_rq_bytes(rq); 459 lba = scsi_get_lba(cmd); 460 } 461 462 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 463 464 if (hba->mcq_enabled) { 465 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 466 467 hwq_id = hwq->id; 468 } else { 469 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 470 } 471 trace_ufshcd_command(cmd->device, str_t, tag, doorbell, hwq_id, 472 transfer_len, intr, lba, opcode, group_id); 473 } 474 475 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 476 { 477 struct ufs_clk_info *clki; 478 struct list_head *head = &hba->clk_list_head; 479 480 if (list_empty(head)) 481 return; 482 483 list_for_each_entry(clki, head, list) { 484 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 485 clki->max_freq) 486 dev_err(hba->dev, "clk: %s, rate: %u\n", 487 clki->name, clki->curr_freq); 488 } 489 } 490 491 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 492 const char *err_name) 493 { 494 int i; 495 bool found = false; 496 const struct ufs_event_hist *e; 497 498 if (id >= UFS_EVT_CNT) 499 return; 500 501 e = &hba->ufs_stats.event[id]; 502 503 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 504 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 505 506 if (e->tstamp[p] == 0) 507 continue; 508 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 509 e->val[p], div_u64(e->tstamp[p], 1000)); 510 found = true; 511 } 512 513 if (!found) 514 dev_err(hba->dev, "No record of %s\n", err_name); 515 else 516 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 517 } 518 519 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 520 { 521 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 522 523 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 524 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 525 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 526 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 527 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 528 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 529 "auto_hibern8_err"); 530 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 531 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 532 "link_startup_fail"); 533 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 534 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 535 "suspend_fail"); 536 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 537 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 538 "wlun suspend_fail"); 539 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 540 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 541 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 542 543 ufshcd_vops_dbg_register_dump(hba); 544 } 545 546 static 547 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 548 { 549 const struct ufshcd_lrb *lrbp; 550 int prdt_length; 551 552 lrbp = &hba->lrb[tag]; 553 554 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 555 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 556 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 557 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 558 dev_err(hba->dev, 559 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 560 tag, (u64)lrbp->utrd_dma_addr); 561 562 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 563 sizeof(struct utp_transfer_req_desc)); 564 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 565 (u64)lrbp->ucd_req_dma_addr); 566 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 567 sizeof(struct utp_upiu_req)); 568 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 569 (u64)lrbp->ucd_rsp_dma_addr); 570 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 571 sizeof(struct utp_upiu_rsp)); 572 573 prdt_length = le16_to_cpu( 574 lrbp->utr_descriptor_ptr->prd_table_length); 575 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 576 prdt_length /= ufshcd_sg_entry_size(hba); 577 578 dev_err(hba->dev, 579 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 580 tag, prdt_length, 581 (u64)lrbp->ucd_prdt_dma_addr); 582 583 if (pr_prdt) 584 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 585 ufshcd_sg_entry_size(hba) * prdt_length); 586 } 587 588 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 589 { 590 struct scsi_device *sdev = req->q->queuedata; 591 struct Scsi_Host *shost = sdev->host; 592 struct ufs_hba *hba = shost_priv(shost); 593 594 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 595 596 return true; 597 } 598 599 /** 600 * ufshcd_print_trs_all - print trs for all started requests. 601 * @hba: per-adapter instance. 602 * @pr_prdt: need to print prdt or not. 603 */ 604 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 605 { 606 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 607 } 608 609 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 610 { 611 int tag; 612 613 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 614 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 615 616 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 617 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 618 } 619 } 620 621 static void ufshcd_print_host_state(struct ufs_hba *hba) 622 { 623 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 624 625 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 626 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 627 hba->outstanding_reqs, hba->outstanding_tasks); 628 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 629 hba->saved_err, hba->saved_uic_err); 630 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 631 hba->curr_dev_pwr_mode, hba->uic_link_state); 632 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 633 hba->pm_op_in_progress, hba->is_sys_suspended); 634 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 635 hba->auto_bkops_enabled, hba->host->host_self_blocked); 636 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 637 dev_err(hba->dev, 638 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 639 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 640 hba->ufs_stats.hibern8_exit_cnt); 641 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 642 div_u64(hba->ufs_stats.last_intr_ts, 1000), 643 hba->ufs_stats.last_intr_status); 644 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 645 hba->eh_flags, hba->req_abort_count); 646 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 647 hba->ufs_version, hba->capabilities, hba->caps); 648 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 649 hba->dev_quirks); 650 if (sdev_ufs) 651 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 652 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 653 654 ufshcd_print_clk_freqs(hba); 655 } 656 657 /** 658 * ufshcd_print_pwr_info - print power params as saved in hba 659 * power info 660 * @hba: per-adapter instance 661 */ 662 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 663 { 664 static const char * const names[] = { 665 "INVALID MODE", 666 "FAST MODE", 667 "SLOW_MODE", 668 "INVALID MODE", 669 "FASTAUTO_MODE", 670 "SLOWAUTO_MODE", 671 "INVALID MODE", 672 }; 673 674 /* 675 * Using dev_dbg to avoid messages during runtime PM to avoid 676 * never-ending cycles of messages written back to storage by user space 677 * causing runtime resume, causing more messages and so on. 678 */ 679 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 680 __func__, 681 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 682 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 683 names[hba->pwr_info.pwr_rx], 684 names[hba->pwr_info.pwr_tx], 685 hba->pwr_info.hs_rate); 686 } 687 688 static void ufshcd_device_reset(struct ufs_hba *hba) 689 { 690 int err; 691 692 err = ufshcd_vops_device_reset(hba); 693 694 if (!err) { 695 ufshcd_set_ufs_dev_active(hba); 696 if (ufshcd_is_wb_allowed(hba)) { 697 hba->dev_info.wb_enabled = false; 698 hba->dev_info.wb_buf_flush_enabled = false; 699 } 700 if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 701 hba->dev_info.rtc_time_baseline = 0; 702 } 703 if (err != -EOPNOTSUPP) 704 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 705 } 706 707 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 708 { 709 if (!us) 710 return; 711 712 if (us < 10) 713 udelay(us); 714 else 715 usleep_range(us, us + tolerance); 716 } 717 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 718 719 /** 720 * ufshcd_wait_for_register - wait for register value to change 721 * @hba: per-adapter interface 722 * @reg: mmio register offset 723 * @mask: mask to apply to the read register value 724 * @val: value to wait for 725 * @interval_us: polling interval in microseconds 726 * @timeout_ms: timeout in milliseconds 727 * 728 * Return: -ETIMEDOUT on error, zero on success. 729 */ 730 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 731 u32 val, unsigned long interval_us, 732 unsigned long timeout_ms) 733 { 734 u32 v; 735 736 val &= mask; /* ignore bits that we don't intend to wait on */ 737 738 return read_poll_timeout(ufshcd_readl, v, (v & mask) == val, 739 interval_us, timeout_ms * 1000, false, hba, reg); 740 } 741 742 /** 743 * ufshcd_get_intr_mask - Get the interrupt bit mask 744 * @hba: Pointer to adapter instance 745 * 746 * Return: interrupt bit mask per version 747 */ 748 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 749 { 750 if (hba->ufs_version <= ufshci_version(2, 0)) 751 return INTERRUPT_MASK_ALL_VER_11; 752 753 return INTERRUPT_MASK_ALL_VER_21; 754 } 755 756 /** 757 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 758 * @hba: Pointer to adapter instance 759 * 760 * Return: UFSHCI version supported by the controller 761 */ 762 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 763 { 764 u32 ufshci_ver; 765 766 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 767 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 768 else 769 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 770 771 /* 772 * UFSHCI v1.x uses a different version scheme, in order 773 * to allow the use of comparisons with the ufshci_version 774 * function, we convert it to the same scheme as ufs 2.0+. 775 */ 776 if (ufshci_ver & 0x00010000) 777 return ufshci_version(1, ufshci_ver & 0x00000100); 778 779 return ufshci_ver; 780 } 781 782 /** 783 * ufshcd_is_device_present - Check if any device connected to 784 * the host controller 785 * @hba: pointer to adapter instance 786 * 787 * Return: true if device present, false if no device detected 788 */ 789 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 790 { 791 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 792 } 793 794 /** 795 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 796 * @lrbp: pointer to local command reference block 797 * @cqe: pointer to the completion queue entry 798 * 799 * This function is used to get the OCS field from UTRD 800 * 801 * Return: the OCS field in the UTRD. 802 */ 803 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 804 struct cq_entry *cqe) 805 { 806 if (cqe) 807 return le32_to_cpu(cqe->status) & MASK_OCS; 808 809 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 810 } 811 812 /** 813 * ufshcd_utrl_clear() - Clear requests from the controller request list. 814 * @hba: per adapter instance 815 * @mask: mask with one bit set for each request to be cleared 816 */ 817 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 818 { 819 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 820 mask = ~mask; 821 /* 822 * From the UFSHCI specification: "UTP Transfer Request List CLear 823 * Register (UTRLCLR): This field is bit significant. Each bit 824 * corresponds to a slot in the UTP Transfer Request List, where bit 0 825 * corresponds to request slot 0. A bit in this field is set to ‘0’ 826 * by host software to indicate to the host controller that a transfer 827 * request slot is cleared. The host controller 828 * shall free up any resources associated to the request slot 829 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 830 * host software indicates no change to request slots by setting the 831 * associated bits in this field to ‘1’. Bits in this field shall only 832 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 833 */ 834 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 835 } 836 837 /** 838 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 839 * @hba: per adapter instance 840 * @pos: position of the bit to be cleared 841 */ 842 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 843 { 844 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 845 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 846 else 847 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 848 } 849 850 /** 851 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 852 * @reg: Register value of host controller status 853 * 854 * Return: 0 on success; a positive value if failed. 855 */ 856 static inline int ufshcd_get_lists_status(u32 reg) 857 { 858 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 859 } 860 861 /** 862 * ufshcd_get_uic_cmd_result - Get the UIC command result 863 * @hba: Pointer to adapter instance 864 * 865 * This function gets the result of UIC command completion 866 * 867 * Return: 0 on success; non-zero value on error. 868 */ 869 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 870 { 871 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 872 MASK_UIC_COMMAND_RESULT; 873 } 874 875 /** 876 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 877 * @hba: Pointer to adapter instance 878 * 879 * This function gets UIC command argument3 880 * 881 * Return: 0 on success; non-zero value on error. 882 */ 883 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 884 { 885 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 886 } 887 888 /** 889 * ufshcd_get_req_rsp - returns the TR response transaction type 890 * @ucd_rsp_ptr: pointer to response UPIU 891 * 892 * Return: UPIU type. 893 */ 894 static inline enum upiu_response_transaction 895 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 896 { 897 return ucd_rsp_ptr->header.transaction_code; 898 } 899 900 /** 901 * ufshcd_is_exception_event - Check if the device raised an exception event 902 * @ucd_rsp_ptr: pointer to response UPIU 903 * 904 * The function checks if the device raised an exception event indicated in 905 * the Device Information field of response UPIU. 906 * 907 * Return: true if exception is raised, false otherwise. 908 */ 909 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 910 { 911 return ucd_rsp_ptr->header.device_information & 1; 912 } 913 914 /** 915 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 916 * @hba: per adapter instance 917 */ 918 static inline void 919 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 920 { 921 ufshcd_writel(hba, INT_AGGR_ENABLE | 922 INT_AGGR_COUNTER_AND_TIMER_RESET, 923 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 924 } 925 926 /** 927 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 928 * @hba: per adapter instance 929 * @cnt: Interrupt aggregation counter threshold 930 * @tmout: Interrupt aggregation timeout value 931 */ 932 static inline void 933 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 934 { 935 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 936 INT_AGGR_COUNTER_THLD_VAL(cnt) | 937 INT_AGGR_TIMEOUT_VAL(tmout), 938 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 939 } 940 941 /** 942 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 943 * @hba: per adapter instance 944 */ 945 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 946 { 947 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 948 } 949 950 /** 951 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 952 * When run-stop registers are set to 1, it indicates the 953 * host controller that it can process the requests 954 * @hba: per adapter instance 955 */ 956 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 957 { 958 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 959 REG_UTP_TASK_REQ_LIST_RUN_STOP); 960 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 961 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 962 } 963 964 /** 965 * ufshcd_hba_start - Start controller initialization sequence 966 * @hba: per adapter instance 967 */ 968 static inline void ufshcd_hba_start(struct ufs_hba *hba) 969 { 970 u32 val = CONTROLLER_ENABLE; 971 972 if (ufshcd_crypto_enable(hba)) 973 val |= CRYPTO_GENERAL_ENABLE; 974 975 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 976 } 977 978 /** 979 * ufshcd_is_hba_active - Get controller state 980 * @hba: per adapter instance 981 * 982 * Return: true if and only if the controller is active. 983 */ 984 bool ufshcd_is_hba_active(struct ufs_hba *hba) 985 { 986 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 987 } 988 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 989 990 /** 991 * ufshcd_pm_qos_init - initialize PM QoS request 992 * @hba: per adapter instance 993 */ 994 void ufshcd_pm_qos_init(struct ufs_hba *hba) 995 { 996 997 if (hba->pm_qos_enabled) 998 return; 999 1000 cpu_latency_qos_add_request(&hba->pm_qos_req, PM_QOS_DEFAULT_VALUE); 1001 1002 if (cpu_latency_qos_request_active(&hba->pm_qos_req)) 1003 hba->pm_qos_enabled = true; 1004 } 1005 1006 /** 1007 * ufshcd_pm_qos_exit - remove request from PM QoS 1008 * @hba: per adapter instance 1009 */ 1010 void ufshcd_pm_qos_exit(struct ufs_hba *hba) 1011 { 1012 if (!hba->pm_qos_enabled) 1013 return; 1014 1015 cpu_latency_qos_remove_request(&hba->pm_qos_req); 1016 hba->pm_qos_enabled = false; 1017 } 1018 1019 /** 1020 * ufshcd_pm_qos_update - update PM QoS request 1021 * @hba: per adapter instance 1022 * @on: If True, vote for perf PM QoS mode otherwise power save mode 1023 */ 1024 static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) 1025 { 1026 if (!hba->pm_qos_enabled) 1027 return; 1028 1029 cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE); 1030 } 1031 1032 /** 1033 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1034 * @hba: per adapter instance 1035 * @scale_up: If True, set max possible frequency othewise set low frequency 1036 * 1037 * Return: 0 if successful; < 0 upon failure. 1038 */ 1039 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1040 { 1041 int ret = 0; 1042 struct ufs_clk_info *clki; 1043 struct list_head *head = &hba->clk_list_head; 1044 1045 if (list_empty(head)) 1046 goto out; 1047 1048 list_for_each_entry(clki, head, list) { 1049 if (!IS_ERR_OR_NULL(clki->clk)) { 1050 if (scale_up && clki->max_freq) { 1051 if (clki->curr_freq == clki->max_freq) 1052 continue; 1053 1054 ret = clk_set_rate(clki->clk, clki->max_freq); 1055 if (ret) { 1056 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1057 __func__, clki->name, 1058 clki->max_freq, ret); 1059 break; 1060 } 1061 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1062 "scaled up", clki->name, 1063 clki->curr_freq, 1064 clki->max_freq); 1065 1066 clki->curr_freq = clki->max_freq; 1067 1068 } else if (!scale_up && clki->min_freq) { 1069 if (clki->curr_freq == clki->min_freq) 1070 continue; 1071 1072 ret = clk_set_rate(clki->clk, clki->min_freq); 1073 if (ret) { 1074 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1075 __func__, clki->name, 1076 clki->min_freq, ret); 1077 break; 1078 } 1079 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1080 "scaled down", clki->name, 1081 clki->curr_freq, 1082 clki->min_freq); 1083 clki->curr_freq = clki->min_freq; 1084 } 1085 } 1086 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1087 clki->name, clk_get_rate(clki->clk)); 1088 } 1089 1090 out: 1091 return ret; 1092 } 1093 1094 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1095 struct dev_pm_opp *opp, void *data, 1096 bool scaling_down) 1097 { 1098 struct ufs_hba *hba = dev_get_drvdata(dev); 1099 struct list_head *head = &hba->clk_list_head; 1100 struct ufs_clk_info *clki; 1101 unsigned long freq; 1102 u8 idx = 0; 1103 int ret; 1104 1105 list_for_each_entry(clki, head, list) { 1106 if (!IS_ERR_OR_NULL(clki->clk)) { 1107 freq = dev_pm_opp_get_freq_indexed(opp, idx++); 1108 1109 /* Do not set rate for clocks having frequency as 0 */ 1110 if (!freq) 1111 continue; 1112 1113 ret = clk_set_rate(clki->clk, freq); 1114 if (ret) { 1115 dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n", 1116 __func__, clki->name, freq, ret); 1117 return ret; 1118 } 1119 1120 trace_ufshcd_clk_scaling(dev_name(dev), 1121 (scaling_down ? "scaled down" : "scaled up"), 1122 clki->name, hba->clk_scaling.target_freq, freq); 1123 } 1124 } 1125 1126 return 0; 1127 } 1128 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks); 1129 1130 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) 1131 { 1132 struct dev_pm_opp *opp; 1133 int ret; 1134 1135 opp = dev_pm_opp_find_freq_floor_indexed(hba->dev, 1136 &freq, 0); 1137 if (IS_ERR(opp)) 1138 return PTR_ERR(opp); 1139 1140 ret = dev_pm_opp_set_opp(hba->dev, opp); 1141 dev_pm_opp_put(opp); 1142 1143 return ret; 1144 } 1145 1146 /** 1147 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1148 * @hba: per adapter instance 1149 * @freq: frequency to scale 1150 * @scale_up: True if scaling up and false if scaling down 1151 * 1152 * Return: 0 if successful; < 0 upon failure. 1153 */ 1154 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 1155 bool scale_up) 1156 { 1157 int ret = 0; 1158 ktime_t start = ktime_get(); 1159 1160 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1161 if (ret) 1162 goto out; 1163 1164 if (hba->use_pm_opp) 1165 ret = ufshcd_opp_set_rate(hba, freq); 1166 else 1167 ret = ufshcd_set_clk_freq(hba, scale_up); 1168 if (ret) 1169 goto out; 1170 1171 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1172 if (ret) { 1173 if (hba->use_pm_opp) 1174 ufshcd_opp_set_rate(hba, 1175 hba->devfreq->previous_freq); 1176 else 1177 ufshcd_set_clk_freq(hba, !scale_up); 1178 goto out; 1179 } 1180 1181 ufshcd_pm_qos_update(hba, scale_up); 1182 1183 out: 1184 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1185 (scale_up ? "up" : "down"), 1186 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1187 return ret; 1188 } 1189 1190 /** 1191 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1192 * @hba: per adapter instance 1193 * @freq: frequency to scale 1194 * @scale_up: True if scaling up and false if scaling down 1195 * 1196 * Return: true if scaling is required, false otherwise. 1197 */ 1198 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1199 unsigned long freq, bool scale_up) 1200 { 1201 struct ufs_clk_info *clki; 1202 struct list_head *head = &hba->clk_list_head; 1203 1204 if (list_empty(head)) 1205 return false; 1206 1207 if (hba->use_pm_opp) 1208 return freq != hba->clk_scaling.target_freq; 1209 1210 list_for_each_entry(clki, head, list) { 1211 if (!IS_ERR_OR_NULL(clki->clk)) { 1212 if (scale_up && clki->max_freq) { 1213 if (clki->curr_freq == clki->max_freq) 1214 continue; 1215 return true; 1216 } else if (!scale_up && clki->min_freq) { 1217 if (clki->curr_freq == clki->min_freq) 1218 continue; 1219 return true; 1220 } 1221 } 1222 } 1223 1224 return false; 1225 } 1226 1227 /* 1228 * Determine the number of pending commands by counting the bits in the SCSI 1229 * device budget maps. This approach has been selected because a bit is set in 1230 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1231 * flag. The host_self_blocked flag can be modified by calling 1232 * scsi_block_requests() or scsi_unblock_requests(). 1233 */ 1234 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1235 { 1236 const struct scsi_device *sdev; 1237 unsigned long flags; 1238 u32 pending = 0; 1239 1240 spin_lock_irqsave(hba->host->host_lock, flags); 1241 __shost_for_each_device(sdev, hba->host) 1242 pending += sbitmap_weight(&sdev->budget_map); 1243 spin_unlock_irqrestore(hba->host->host_lock, flags); 1244 1245 return pending; 1246 } 1247 1248 /* 1249 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1250 * has expired. 1251 * 1252 * Return: 0 upon success; -EBUSY upon timeout. 1253 */ 1254 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1255 u64 wait_timeout_us) 1256 { 1257 int ret = 0; 1258 u32 tm_doorbell; 1259 u32 tr_pending; 1260 bool timeout = false, do_last_check = false; 1261 ktime_t start; 1262 1263 ufshcd_hold(hba); 1264 /* 1265 * Wait for all the outstanding tasks/transfer requests. 1266 * Verify by checking the doorbell registers are clear. 1267 */ 1268 start = ktime_get(); 1269 do { 1270 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1271 ret = -EBUSY; 1272 goto out; 1273 } 1274 1275 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1276 tr_pending = ufshcd_pending_cmds(hba); 1277 if (!tm_doorbell && !tr_pending) { 1278 timeout = false; 1279 break; 1280 } else if (do_last_check) { 1281 break; 1282 } 1283 1284 io_schedule_timeout(msecs_to_jiffies(20)); 1285 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1286 wait_timeout_us) { 1287 timeout = true; 1288 /* 1289 * We might have scheduled out for long time so make 1290 * sure to check if doorbells are cleared by this time 1291 * or not. 1292 */ 1293 do_last_check = true; 1294 } 1295 } while (tm_doorbell || tr_pending); 1296 1297 if (timeout) { 1298 dev_err(hba->dev, 1299 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1300 __func__, tm_doorbell, tr_pending); 1301 ret = -EBUSY; 1302 } 1303 out: 1304 ufshcd_release(hba); 1305 return ret; 1306 } 1307 1308 /** 1309 * ufshcd_scale_gear - scale up/down UFS gear 1310 * @hba: per adapter instance 1311 * @scale_up: True for scaling up gear and false for scaling down 1312 * 1313 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1314 * non-zero for any other errors. 1315 */ 1316 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1317 { 1318 int ret = 0; 1319 struct ufs_pa_layer_attr new_pwr_info; 1320 1321 if (scale_up) { 1322 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1323 sizeof(struct ufs_pa_layer_attr)); 1324 } else { 1325 memcpy(&new_pwr_info, &hba->pwr_info, 1326 sizeof(struct ufs_pa_layer_attr)); 1327 1328 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1329 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1330 /* save the current power mode */ 1331 memcpy(&hba->clk_scaling.saved_pwr_info, 1332 &hba->pwr_info, 1333 sizeof(struct ufs_pa_layer_attr)); 1334 1335 /* scale down gear */ 1336 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1337 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1338 } 1339 } 1340 1341 /* check if the power mode needs to be changed or not? */ 1342 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1343 if (ret) 1344 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1345 __func__, ret, 1346 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1347 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1348 1349 return ret; 1350 } 1351 1352 /* 1353 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1354 * has expired. 1355 * 1356 * Return: 0 upon success; -EBUSY upon timeout. 1357 */ 1358 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1359 { 1360 int ret = 0; 1361 /* 1362 * make sure that there are no outstanding requests when 1363 * clock scaling is in progress 1364 */ 1365 blk_mq_quiesce_tagset(&hba->host->tag_set); 1366 mutex_lock(&hba->wb_mutex); 1367 down_write(&hba->clk_scaling_lock); 1368 1369 if (!hba->clk_scaling.is_allowed || 1370 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1371 ret = -EBUSY; 1372 up_write(&hba->clk_scaling_lock); 1373 mutex_unlock(&hba->wb_mutex); 1374 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1375 goto out; 1376 } 1377 1378 /* let's not get into low power until clock scaling is completed */ 1379 ufshcd_hold(hba); 1380 1381 out: 1382 return ret; 1383 } 1384 1385 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1386 { 1387 up_write(&hba->clk_scaling_lock); 1388 1389 /* Enable Write Booster if we have scaled up else disable it */ 1390 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1391 ufshcd_wb_toggle(hba, scale_up); 1392 1393 mutex_unlock(&hba->wb_mutex); 1394 1395 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1396 ufshcd_release(hba); 1397 } 1398 1399 /** 1400 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1401 * @hba: per adapter instance 1402 * @freq: frequency to scale 1403 * @scale_up: True for scaling up and false for scalin down 1404 * 1405 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1406 * for any other errors. 1407 */ 1408 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, 1409 bool scale_up) 1410 { 1411 int ret = 0; 1412 1413 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1414 if (ret) 1415 return ret; 1416 1417 /* scale down the gear before scaling down clocks */ 1418 if (!scale_up) { 1419 ret = ufshcd_scale_gear(hba, false); 1420 if (ret) 1421 goto out_unprepare; 1422 } 1423 1424 ret = ufshcd_scale_clks(hba, freq, scale_up); 1425 if (ret) { 1426 if (!scale_up) 1427 ufshcd_scale_gear(hba, true); 1428 goto out_unprepare; 1429 } 1430 1431 /* scale up the gear after scaling up clocks */ 1432 if (scale_up) { 1433 ret = ufshcd_scale_gear(hba, true); 1434 if (ret) { 1435 ufshcd_scale_clks(hba, hba->devfreq->previous_freq, 1436 false); 1437 goto out_unprepare; 1438 } 1439 } 1440 1441 out_unprepare: 1442 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1443 return ret; 1444 } 1445 1446 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1447 { 1448 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1449 clk_scaling.suspend_work); 1450 unsigned long irq_flags; 1451 1452 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1453 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1454 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1455 return; 1456 } 1457 hba->clk_scaling.is_suspended = true; 1458 hba->clk_scaling.window_start_t = 0; 1459 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1460 1461 devfreq_suspend_device(hba->devfreq); 1462 } 1463 1464 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1465 { 1466 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1467 clk_scaling.resume_work); 1468 unsigned long irq_flags; 1469 1470 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1471 if (!hba->clk_scaling.is_suspended) { 1472 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1473 return; 1474 } 1475 hba->clk_scaling.is_suspended = false; 1476 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1477 1478 devfreq_resume_device(hba->devfreq); 1479 } 1480 1481 static int ufshcd_devfreq_target(struct device *dev, 1482 unsigned long *freq, u32 flags) 1483 { 1484 int ret = 0; 1485 struct ufs_hba *hba = dev_get_drvdata(dev); 1486 ktime_t start; 1487 bool scale_up = false, sched_clk_scaling_suspend_work = false; 1488 struct list_head *clk_list = &hba->clk_list_head; 1489 struct ufs_clk_info *clki; 1490 unsigned long irq_flags; 1491 1492 if (!ufshcd_is_clkscaling_supported(hba)) 1493 return -EINVAL; 1494 1495 if (hba->use_pm_opp) { 1496 struct dev_pm_opp *opp; 1497 1498 /* Get the recommended frequency from OPP framework */ 1499 opp = devfreq_recommended_opp(dev, freq, flags); 1500 if (IS_ERR(opp)) 1501 return PTR_ERR(opp); 1502 1503 dev_pm_opp_put(opp); 1504 } else { 1505 /* Override with the closest supported frequency */ 1506 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, 1507 list); 1508 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1509 } 1510 1511 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1512 if (ufshcd_eh_in_progress(hba)) { 1513 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1514 return 0; 1515 } 1516 1517 /* Skip scaling clock when clock scaling is suspended */ 1518 if (hba->clk_scaling.is_suspended) { 1519 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1520 dev_warn(hba->dev, "clock scaling is suspended, skip"); 1521 return 0; 1522 } 1523 1524 if (!hba->clk_scaling.active_reqs) 1525 sched_clk_scaling_suspend_work = true; 1526 1527 if (list_empty(clk_list)) { 1528 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1529 goto out; 1530 } 1531 1532 /* Decide based on the target or rounded-off frequency and update */ 1533 if (hba->use_pm_opp) 1534 scale_up = *freq > hba->clk_scaling.target_freq; 1535 else 1536 scale_up = *freq == clki->max_freq; 1537 1538 if (!hba->use_pm_opp && !scale_up) 1539 *freq = clki->min_freq; 1540 1541 /* Update the frequency */ 1542 if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) { 1543 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1544 ret = 0; 1545 goto out; /* no state change required */ 1546 } 1547 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1548 1549 start = ktime_get(); 1550 ret = ufshcd_devfreq_scale(hba, *freq, scale_up); 1551 if (!ret) 1552 hba->clk_scaling.target_freq = *freq; 1553 1554 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1555 (scale_up ? "up" : "down"), 1556 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1557 1558 out: 1559 if (sched_clk_scaling_suspend_work && 1560 (!scale_up || hba->clk_scaling.suspend_on_no_request)) 1561 queue_work(hba->clk_scaling.workq, 1562 &hba->clk_scaling.suspend_work); 1563 1564 return ret; 1565 } 1566 1567 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1568 struct devfreq_dev_status *stat) 1569 { 1570 struct ufs_hba *hba = dev_get_drvdata(dev); 1571 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1572 unsigned long flags; 1573 ktime_t curr_t; 1574 1575 if (!ufshcd_is_clkscaling_supported(hba)) 1576 return -EINVAL; 1577 1578 memset(stat, 0, sizeof(*stat)); 1579 1580 spin_lock_irqsave(hba->host->host_lock, flags); 1581 curr_t = ktime_get(); 1582 if (!scaling->window_start_t) 1583 goto start_window; 1584 1585 /* 1586 * If current frequency is 0, then the ondemand governor considers 1587 * there's no initial frequency set. And it always requests to set 1588 * to max. frequency. 1589 */ 1590 if (hba->use_pm_opp) { 1591 stat->current_frequency = hba->clk_scaling.target_freq; 1592 } else { 1593 struct list_head *clk_list = &hba->clk_list_head; 1594 struct ufs_clk_info *clki; 1595 1596 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1597 stat->current_frequency = clki->curr_freq; 1598 } 1599 1600 if (scaling->is_busy_started) 1601 scaling->tot_busy_t += ktime_us_delta(curr_t, 1602 scaling->busy_start_t); 1603 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1604 stat->busy_time = scaling->tot_busy_t; 1605 start_window: 1606 scaling->window_start_t = curr_t; 1607 scaling->tot_busy_t = 0; 1608 1609 if (scaling->active_reqs) { 1610 scaling->busy_start_t = curr_t; 1611 scaling->is_busy_started = true; 1612 } else { 1613 scaling->busy_start_t = 0; 1614 scaling->is_busy_started = false; 1615 } 1616 spin_unlock_irqrestore(hba->host->host_lock, flags); 1617 return 0; 1618 } 1619 1620 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1621 { 1622 struct list_head *clk_list = &hba->clk_list_head; 1623 struct ufs_clk_info *clki; 1624 struct devfreq *devfreq; 1625 int ret; 1626 1627 /* Skip devfreq if we don't have any clocks in the list */ 1628 if (list_empty(clk_list)) 1629 return 0; 1630 1631 if (!hba->use_pm_opp) { 1632 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1633 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1634 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1635 } 1636 1637 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1638 &hba->vps->ondemand_data); 1639 devfreq = devfreq_add_device(hba->dev, 1640 &hba->vps->devfreq_profile, 1641 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1642 &hba->vps->ondemand_data); 1643 if (IS_ERR(devfreq)) { 1644 ret = PTR_ERR(devfreq); 1645 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1646 1647 if (!hba->use_pm_opp) { 1648 dev_pm_opp_remove(hba->dev, clki->min_freq); 1649 dev_pm_opp_remove(hba->dev, clki->max_freq); 1650 } 1651 return ret; 1652 } 1653 1654 hba->devfreq = devfreq; 1655 1656 return 0; 1657 } 1658 1659 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1660 { 1661 struct list_head *clk_list = &hba->clk_list_head; 1662 1663 if (!hba->devfreq) 1664 return; 1665 1666 devfreq_remove_device(hba->devfreq); 1667 hba->devfreq = NULL; 1668 1669 if (!hba->use_pm_opp) { 1670 struct ufs_clk_info *clki; 1671 1672 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1673 dev_pm_opp_remove(hba->dev, clki->min_freq); 1674 dev_pm_opp_remove(hba->dev, clki->max_freq); 1675 } 1676 } 1677 1678 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1679 { 1680 unsigned long flags; 1681 bool suspend = false; 1682 1683 cancel_work_sync(&hba->clk_scaling.suspend_work); 1684 cancel_work_sync(&hba->clk_scaling.resume_work); 1685 1686 spin_lock_irqsave(hba->host->host_lock, flags); 1687 if (!hba->clk_scaling.is_suspended) { 1688 suspend = true; 1689 hba->clk_scaling.is_suspended = true; 1690 hba->clk_scaling.window_start_t = 0; 1691 } 1692 spin_unlock_irqrestore(hba->host->host_lock, flags); 1693 1694 if (suspend) 1695 devfreq_suspend_device(hba->devfreq); 1696 } 1697 1698 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1699 { 1700 unsigned long flags; 1701 bool resume = false; 1702 1703 spin_lock_irqsave(hba->host->host_lock, flags); 1704 if (hba->clk_scaling.is_suspended) { 1705 resume = true; 1706 hba->clk_scaling.is_suspended = false; 1707 } 1708 spin_unlock_irqrestore(hba->host->host_lock, flags); 1709 1710 if (resume) 1711 devfreq_resume_device(hba->devfreq); 1712 } 1713 1714 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1715 struct device_attribute *attr, char *buf) 1716 { 1717 struct ufs_hba *hba = dev_get_drvdata(dev); 1718 1719 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1720 } 1721 1722 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1723 struct device_attribute *attr, const char *buf, size_t count) 1724 { 1725 struct ufs_hba *hba = dev_get_drvdata(dev); 1726 u32 value; 1727 int err = 0; 1728 1729 if (kstrtou32(buf, 0, &value)) 1730 return -EINVAL; 1731 1732 down(&hba->host_sem); 1733 if (!ufshcd_is_user_access_allowed(hba)) { 1734 err = -EBUSY; 1735 goto out; 1736 } 1737 1738 value = !!value; 1739 if (value == hba->clk_scaling.is_enabled) 1740 goto out; 1741 1742 ufshcd_rpm_get_sync(hba); 1743 ufshcd_hold(hba); 1744 1745 hba->clk_scaling.is_enabled = value; 1746 1747 if (value) { 1748 ufshcd_resume_clkscaling(hba); 1749 } else { 1750 ufshcd_suspend_clkscaling(hba); 1751 err = ufshcd_devfreq_scale(hba, ULONG_MAX, true); 1752 if (err) 1753 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1754 __func__, err); 1755 } 1756 1757 ufshcd_release(hba); 1758 ufshcd_rpm_put_sync(hba); 1759 out: 1760 up(&hba->host_sem); 1761 return err ? err : count; 1762 } 1763 1764 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1765 { 1766 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1767 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1768 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1769 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1770 hba->clk_scaling.enable_attr.attr.mode = 0644; 1771 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1772 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1773 } 1774 1775 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1776 { 1777 if (hba->clk_scaling.enable_attr.attr.name) 1778 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1779 } 1780 1781 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1782 { 1783 if (!ufshcd_is_clkscaling_supported(hba)) 1784 return; 1785 1786 if (!hba->clk_scaling.min_gear) 1787 hba->clk_scaling.min_gear = UFS_HS_G1; 1788 1789 INIT_WORK(&hba->clk_scaling.suspend_work, 1790 ufshcd_clk_scaling_suspend_work); 1791 INIT_WORK(&hba->clk_scaling.resume_work, 1792 ufshcd_clk_scaling_resume_work); 1793 1794 hba->clk_scaling.workq = alloc_ordered_workqueue( 1795 "ufs_clkscaling_%d", WQ_MEM_RECLAIM, hba->host->host_no); 1796 1797 hba->clk_scaling.is_initialized = true; 1798 } 1799 1800 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1801 { 1802 if (!hba->clk_scaling.is_initialized) 1803 return; 1804 1805 ufshcd_remove_clk_scaling_sysfs(hba); 1806 destroy_workqueue(hba->clk_scaling.workq); 1807 ufshcd_devfreq_remove(hba); 1808 hba->clk_scaling.is_initialized = false; 1809 } 1810 1811 static void ufshcd_ungate_work(struct work_struct *work) 1812 { 1813 int ret; 1814 unsigned long flags; 1815 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1816 clk_gating.ungate_work); 1817 1818 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1819 1820 spin_lock_irqsave(hba->host->host_lock, flags); 1821 if (hba->clk_gating.state == CLKS_ON) { 1822 spin_unlock_irqrestore(hba->host->host_lock, flags); 1823 return; 1824 } 1825 1826 spin_unlock_irqrestore(hba->host->host_lock, flags); 1827 ufshcd_hba_vreg_set_hpm(hba); 1828 ufshcd_setup_clocks(hba, true); 1829 1830 ufshcd_enable_irq(hba); 1831 1832 /* Exit from hibern8 */ 1833 if (ufshcd_can_hibern8_during_gating(hba)) { 1834 /* Prevent gating in this path */ 1835 hba->clk_gating.is_suspended = true; 1836 if (ufshcd_is_link_hibern8(hba)) { 1837 ret = ufshcd_uic_hibern8_exit(hba); 1838 if (ret) 1839 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1840 __func__, ret); 1841 else 1842 ufshcd_set_link_active(hba); 1843 } 1844 hba->clk_gating.is_suspended = false; 1845 } 1846 } 1847 1848 /** 1849 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1850 * Also, exit from hibern8 mode and set the link as active. 1851 * @hba: per adapter instance 1852 */ 1853 void ufshcd_hold(struct ufs_hba *hba) 1854 { 1855 bool flush_result; 1856 unsigned long flags; 1857 1858 if (!ufshcd_is_clkgating_allowed(hba) || 1859 !hba->clk_gating.is_initialized) 1860 return; 1861 spin_lock_irqsave(hba->host->host_lock, flags); 1862 hba->clk_gating.active_reqs++; 1863 1864 start: 1865 switch (hba->clk_gating.state) { 1866 case CLKS_ON: 1867 /* 1868 * Wait for the ungate work to complete if in progress. 1869 * Though the clocks may be in ON state, the link could 1870 * still be in hibner8 state if hibern8 is allowed 1871 * during clock gating. 1872 * Make sure we exit hibern8 state also in addition to 1873 * clocks being ON. 1874 */ 1875 if (ufshcd_can_hibern8_during_gating(hba) && 1876 ufshcd_is_link_hibern8(hba)) { 1877 spin_unlock_irqrestore(hba->host->host_lock, flags); 1878 flush_result = flush_work(&hba->clk_gating.ungate_work); 1879 if (hba->clk_gating.is_suspended && !flush_result) 1880 return; 1881 spin_lock_irqsave(hba->host->host_lock, flags); 1882 goto start; 1883 } 1884 break; 1885 case REQ_CLKS_OFF: 1886 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1887 hba->clk_gating.state = CLKS_ON; 1888 trace_ufshcd_clk_gating(dev_name(hba->dev), 1889 hba->clk_gating.state); 1890 break; 1891 } 1892 /* 1893 * If we are here, it means gating work is either done or 1894 * currently running. Hence, fall through to cancel gating 1895 * work and to enable clocks. 1896 */ 1897 fallthrough; 1898 case CLKS_OFF: 1899 hba->clk_gating.state = REQ_CLKS_ON; 1900 trace_ufshcd_clk_gating(dev_name(hba->dev), 1901 hba->clk_gating.state); 1902 queue_work(hba->clk_gating.clk_gating_workq, 1903 &hba->clk_gating.ungate_work); 1904 /* 1905 * fall through to check if we should wait for this 1906 * work to be done or not. 1907 */ 1908 fallthrough; 1909 case REQ_CLKS_ON: 1910 spin_unlock_irqrestore(hba->host->host_lock, flags); 1911 flush_work(&hba->clk_gating.ungate_work); 1912 /* Make sure state is CLKS_ON before returning */ 1913 spin_lock_irqsave(hba->host->host_lock, flags); 1914 goto start; 1915 default: 1916 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1917 __func__, hba->clk_gating.state); 1918 break; 1919 } 1920 spin_unlock_irqrestore(hba->host->host_lock, flags); 1921 } 1922 EXPORT_SYMBOL_GPL(ufshcd_hold); 1923 1924 static void ufshcd_gate_work(struct work_struct *work) 1925 { 1926 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1927 clk_gating.gate_work.work); 1928 unsigned long flags; 1929 int ret; 1930 1931 spin_lock_irqsave(hba->host->host_lock, flags); 1932 /* 1933 * In case you are here to cancel this work the gating state 1934 * would be marked as REQ_CLKS_ON. In this case save time by 1935 * skipping the gating work and exit after changing the clock 1936 * state to CLKS_ON. 1937 */ 1938 if (hba->clk_gating.is_suspended || 1939 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1940 hba->clk_gating.state = CLKS_ON; 1941 trace_ufshcd_clk_gating(dev_name(hba->dev), 1942 hba->clk_gating.state); 1943 goto rel_lock; 1944 } 1945 1946 if (ufshcd_is_ufs_dev_busy(hba) || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) 1947 goto rel_lock; 1948 1949 spin_unlock_irqrestore(hba->host->host_lock, flags); 1950 1951 /* put the link into hibern8 mode before turning off clocks */ 1952 if (ufshcd_can_hibern8_during_gating(hba)) { 1953 ret = ufshcd_uic_hibern8_enter(hba); 1954 if (ret) { 1955 hba->clk_gating.state = CLKS_ON; 1956 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1957 __func__, ret); 1958 trace_ufshcd_clk_gating(dev_name(hba->dev), 1959 hba->clk_gating.state); 1960 goto out; 1961 } 1962 ufshcd_set_link_hibern8(hba); 1963 } 1964 1965 ufshcd_disable_irq(hba); 1966 1967 ufshcd_setup_clocks(hba, false); 1968 1969 /* Put the host controller in low power mode if possible */ 1970 ufshcd_hba_vreg_set_lpm(hba); 1971 /* 1972 * In case you are here to cancel this work the gating state 1973 * would be marked as REQ_CLKS_ON. In this case keep the state 1974 * as REQ_CLKS_ON which would anyway imply that clocks are off 1975 * and a request to turn them on is pending. By doing this way, 1976 * we keep the state machine in tact and this would ultimately 1977 * prevent from doing cancel work multiple times when there are 1978 * new requests arriving before the current cancel work is done. 1979 */ 1980 spin_lock_irqsave(hba->host->host_lock, flags); 1981 if (hba->clk_gating.state == REQ_CLKS_OFF) { 1982 hba->clk_gating.state = CLKS_OFF; 1983 trace_ufshcd_clk_gating(dev_name(hba->dev), 1984 hba->clk_gating.state); 1985 } 1986 rel_lock: 1987 spin_unlock_irqrestore(hba->host->host_lock, flags); 1988 out: 1989 return; 1990 } 1991 1992 /* host lock must be held before calling this variant */ 1993 static void __ufshcd_release(struct ufs_hba *hba) 1994 { 1995 if (!ufshcd_is_clkgating_allowed(hba)) 1996 return; 1997 1998 hba->clk_gating.active_reqs--; 1999 2000 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 2001 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 2002 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 2003 hba->active_uic_cmd || hba->uic_async_done || 2004 hba->clk_gating.state == CLKS_OFF) 2005 return; 2006 2007 hba->clk_gating.state = REQ_CLKS_OFF; 2008 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 2009 queue_delayed_work(hba->clk_gating.clk_gating_workq, 2010 &hba->clk_gating.gate_work, 2011 msecs_to_jiffies(hba->clk_gating.delay_ms)); 2012 } 2013 2014 void ufshcd_release(struct ufs_hba *hba) 2015 { 2016 unsigned long flags; 2017 2018 spin_lock_irqsave(hba->host->host_lock, flags); 2019 __ufshcd_release(hba); 2020 spin_unlock_irqrestore(hba->host->host_lock, flags); 2021 } 2022 EXPORT_SYMBOL_GPL(ufshcd_release); 2023 2024 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 2025 struct device_attribute *attr, char *buf) 2026 { 2027 struct ufs_hba *hba = dev_get_drvdata(dev); 2028 2029 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 2030 } 2031 2032 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 2033 { 2034 struct ufs_hba *hba = dev_get_drvdata(dev); 2035 unsigned long flags; 2036 2037 spin_lock_irqsave(hba->host->host_lock, flags); 2038 hba->clk_gating.delay_ms = value; 2039 spin_unlock_irqrestore(hba->host->host_lock, flags); 2040 } 2041 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 2042 2043 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 2044 struct device_attribute *attr, const char *buf, size_t count) 2045 { 2046 unsigned long value; 2047 2048 if (kstrtoul(buf, 0, &value)) 2049 return -EINVAL; 2050 2051 ufshcd_clkgate_delay_set(dev, value); 2052 return count; 2053 } 2054 2055 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 2056 struct device_attribute *attr, char *buf) 2057 { 2058 struct ufs_hba *hba = dev_get_drvdata(dev); 2059 2060 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 2061 } 2062 2063 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 2064 struct device_attribute *attr, const char *buf, size_t count) 2065 { 2066 struct ufs_hba *hba = dev_get_drvdata(dev); 2067 unsigned long flags; 2068 u32 value; 2069 2070 if (kstrtou32(buf, 0, &value)) 2071 return -EINVAL; 2072 2073 value = !!value; 2074 2075 spin_lock_irqsave(hba->host->host_lock, flags); 2076 if (value == hba->clk_gating.is_enabled) 2077 goto out; 2078 2079 if (value) 2080 __ufshcd_release(hba); 2081 else 2082 hba->clk_gating.active_reqs++; 2083 2084 hba->clk_gating.is_enabled = value; 2085 out: 2086 spin_unlock_irqrestore(hba->host->host_lock, flags); 2087 return count; 2088 } 2089 2090 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 2091 { 2092 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 2093 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 2094 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 2095 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 2096 hba->clk_gating.delay_attr.attr.mode = 0644; 2097 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 2098 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 2099 2100 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 2101 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 2102 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 2103 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 2104 hba->clk_gating.enable_attr.attr.mode = 0644; 2105 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 2106 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 2107 } 2108 2109 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 2110 { 2111 if (hba->clk_gating.delay_attr.attr.name) 2112 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 2113 if (hba->clk_gating.enable_attr.attr.name) 2114 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 2115 } 2116 2117 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 2118 { 2119 if (!ufshcd_is_clkgating_allowed(hba)) 2120 return; 2121 2122 hba->clk_gating.state = CLKS_ON; 2123 2124 hba->clk_gating.delay_ms = 150; 2125 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2126 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2127 2128 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue( 2129 "ufs_clk_gating_%d", WQ_MEM_RECLAIM | WQ_HIGHPRI, 2130 hba->host->host_no); 2131 2132 ufshcd_init_clk_gating_sysfs(hba); 2133 2134 hba->clk_gating.is_enabled = true; 2135 hba->clk_gating.is_initialized = true; 2136 } 2137 2138 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2139 { 2140 if (!hba->clk_gating.is_initialized) 2141 return; 2142 2143 ufshcd_remove_clk_gating_sysfs(hba); 2144 2145 /* Ungate the clock if necessary. */ 2146 ufshcd_hold(hba); 2147 hba->clk_gating.is_initialized = false; 2148 ufshcd_release(hba); 2149 2150 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2151 } 2152 2153 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2154 { 2155 bool queue_resume_work = false; 2156 ktime_t curr_t = ktime_get(); 2157 unsigned long flags; 2158 2159 if (!ufshcd_is_clkscaling_supported(hba)) 2160 return; 2161 2162 spin_lock_irqsave(hba->host->host_lock, flags); 2163 if (!hba->clk_scaling.active_reqs++) 2164 queue_resume_work = true; 2165 2166 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2167 spin_unlock_irqrestore(hba->host->host_lock, flags); 2168 return; 2169 } 2170 2171 if (queue_resume_work) 2172 queue_work(hba->clk_scaling.workq, 2173 &hba->clk_scaling.resume_work); 2174 2175 if (!hba->clk_scaling.window_start_t) { 2176 hba->clk_scaling.window_start_t = curr_t; 2177 hba->clk_scaling.tot_busy_t = 0; 2178 hba->clk_scaling.is_busy_started = false; 2179 } 2180 2181 if (!hba->clk_scaling.is_busy_started) { 2182 hba->clk_scaling.busy_start_t = curr_t; 2183 hba->clk_scaling.is_busy_started = true; 2184 } 2185 spin_unlock_irqrestore(hba->host->host_lock, flags); 2186 } 2187 2188 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2189 { 2190 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2191 unsigned long flags; 2192 2193 if (!ufshcd_is_clkscaling_supported(hba)) 2194 return; 2195 2196 spin_lock_irqsave(hba->host->host_lock, flags); 2197 hba->clk_scaling.active_reqs--; 2198 if (!scaling->active_reqs && scaling->is_busy_started) { 2199 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2200 scaling->busy_start_t)); 2201 scaling->busy_start_t = 0; 2202 scaling->is_busy_started = false; 2203 } 2204 spin_unlock_irqrestore(hba->host->host_lock, flags); 2205 } 2206 2207 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2208 { 2209 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2210 return READ; 2211 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2212 return WRITE; 2213 else 2214 return -EINVAL; 2215 } 2216 2217 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2218 struct ufshcd_lrb *lrbp) 2219 { 2220 const struct ufs_hba_monitor *m = &hba->monitor; 2221 2222 return (m->enabled && lrbp && lrbp->cmd && 2223 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2224 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2225 } 2226 2227 static void ufshcd_start_monitor(struct ufs_hba *hba, 2228 const struct ufshcd_lrb *lrbp) 2229 { 2230 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2231 unsigned long flags; 2232 2233 spin_lock_irqsave(hba->host->host_lock, flags); 2234 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2235 hba->monitor.busy_start_ts[dir] = ktime_get(); 2236 spin_unlock_irqrestore(hba->host->host_lock, flags); 2237 } 2238 2239 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2240 { 2241 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2242 unsigned long flags; 2243 2244 spin_lock_irqsave(hba->host->host_lock, flags); 2245 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2246 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2247 struct ufs_hba_monitor *m = &hba->monitor; 2248 ktime_t now, inc, lat; 2249 2250 now = lrbp->compl_time_stamp; 2251 inc = ktime_sub(now, m->busy_start_ts[dir]); 2252 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2253 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2254 2255 /* Update latencies */ 2256 m->nr_req[dir]++; 2257 lat = ktime_sub(now, lrbp->issue_time_stamp); 2258 m->lat_sum[dir] += lat; 2259 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2260 m->lat_max[dir] = lat; 2261 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2262 m->lat_min[dir] = lat; 2263 2264 m->nr_queued[dir]--; 2265 /* Push forward the busy start of monitor */ 2266 m->busy_start_ts[dir] = now; 2267 } 2268 spin_unlock_irqrestore(hba->host->host_lock, flags); 2269 } 2270 2271 /** 2272 * ufshcd_send_command - Send SCSI or device management commands 2273 * @hba: per adapter instance 2274 * @task_tag: Task tag of the command 2275 * @hwq: pointer to hardware queue instance 2276 */ 2277 static inline 2278 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2279 struct ufs_hw_queue *hwq) 2280 { 2281 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2282 unsigned long flags; 2283 2284 lrbp->issue_time_stamp = ktime_get(); 2285 lrbp->issue_time_stamp_local_clock = local_clock(); 2286 lrbp->compl_time_stamp = ktime_set(0, 0); 2287 lrbp->compl_time_stamp_local_clock = 0; 2288 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2289 if (lrbp->cmd) 2290 ufshcd_clk_scaling_start_busy(hba); 2291 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2292 ufshcd_start_monitor(hba, lrbp); 2293 2294 if (hba->mcq_enabled) { 2295 int utrd_size = sizeof(struct utp_transfer_req_desc); 2296 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2297 struct utp_transfer_req_desc *dest; 2298 2299 spin_lock(&hwq->sq_lock); 2300 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2301 memcpy(dest, src, utrd_size); 2302 ufshcd_inc_sq_tail(hwq); 2303 spin_unlock(&hwq->sq_lock); 2304 } else { 2305 spin_lock_irqsave(&hba->outstanding_lock, flags); 2306 if (hba->vops && hba->vops->setup_xfer_req) 2307 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2308 !!lrbp->cmd); 2309 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2310 ufshcd_writel(hba, 1 << lrbp->task_tag, 2311 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2312 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2313 } 2314 } 2315 2316 /** 2317 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2318 * @lrbp: pointer to local reference block 2319 */ 2320 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2321 { 2322 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2323 u16 resp_len; 2324 int len; 2325 2326 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2327 if (sense_buffer && resp_len) { 2328 int len_to_copy; 2329 2330 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2331 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2332 2333 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2334 len_to_copy); 2335 } 2336 } 2337 2338 /** 2339 * ufshcd_copy_query_response() - Copy the Query Response and the data 2340 * descriptor 2341 * @hba: per adapter instance 2342 * @lrbp: pointer to local reference block 2343 * 2344 * Return: 0 upon success; < 0 upon failure. 2345 */ 2346 static 2347 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2348 { 2349 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2350 2351 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2352 2353 /* Get the descriptor */ 2354 if (hba->dev_cmd.query.descriptor && 2355 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2356 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2357 GENERAL_UPIU_REQUEST_SIZE; 2358 u16 resp_len; 2359 u16 buf_len; 2360 2361 /* data segment length */ 2362 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2363 .data_segment_length); 2364 buf_len = be16_to_cpu( 2365 hba->dev_cmd.query.request.upiu_req.length); 2366 if (likely(buf_len >= resp_len)) { 2367 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2368 } else { 2369 dev_warn(hba->dev, 2370 "%s: rsp size %d is bigger than buffer size %d", 2371 __func__, resp_len, buf_len); 2372 return -EINVAL; 2373 } 2374 } 2375 2376 return 0; 2377 } 2378 2379 /** 2380 * ufshcd_hba_capabilities - Read controller capabilities 2381 * @hba: per adapter instance 2382 * 2383 * Return: 0 on success, negative on error. 2384 */ 2385 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2386 { 2387 int err; 2388 2389 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2390 2391 /* nutrs and nutmrs are 0 based values */ 2392 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS_SDB) + 1; 2393 hba->nutmrs = 2394 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2395 hba->reserved_slot = hba->nutrs - 1; 2396 2397 hba->nortt = FIELD_GET(MASK_NUMBER_OUTSTANDING_RTT, hba->capabilities) + 1; 2398 2399 /* Read crypto capabilities */ 2400 err = ufshcd_hba_init_crypto_capabilities(hba); 2401 if (err) { 2402 dev_err(hba->dev, "crypto setup failed\n"); 2403 return err; 2404 } 2405 2406 /* 2407 * The UFSHCI 3.0 specification does not define MCQ_SUPPORT and 2408 * LSDB_SUPPORT, but [31:29] as reserved bits with reset value 0s, which 2409 * means we can simply read values regardless of version. 2410 */ 2411 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2412 /* 2413 * 0h: legacy single doorbell support is available 2414 * 1h: indicate that legacy single doorbell support has been removed 2415 */ 2416 if (!(hba->quirks & UFSHCD_QUIRK_BROKEN_LSDBS_CAP)) 2417 hba->lsdb_sup = !FIELD_GET(MASK_LSDB_SUPPORT, hba->capabilities); 2418 else 2419 hba->lsdb_sup = true; 2420 2421 if (!hba->mcq_sup) 2422 return 0; 2423 2424 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2425 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2426 hba->mcq_capabilities); 2427 2428 return 0; 2429 } 2430 2431 /** 2432 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2433 * to accept UIC commands 2434 * @hba: per adapter instance 2435 * 2436 * Return: true on success, else false. 2437 */ 2438 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2439 { 2440 u32 val; 2441 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2442 500, uic_cmd_timeout * 1000, false, hba, 2443 REG_CONTROLLER_STATUS); 2444 return ret == 0; 2445 } 2446 2447 /** 2448 * ufshcd_get_upmcrs - Get the power mode change request status 2449 * @hba: Pointer to adapter instance 2450 * 2451 * This function gets the UPMCRS field of HCS register 2452 * 2453 * Return: value of UPMCRS field. 2454 */ 2455 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2456 { 2457 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2458 } 2459 2460 /** 2461 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2462 * @hba: per adapter instance 2463 * @uic_cmd: UIC command 2464 */ 2465 static inline void 2466 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2467 { 2468 lockdep_assert_held(&hba->uic_cmd_mutex); 2469 2470 WARN_ON(hba->active_uic_cmd); 2471 2472 hba->active_uic_cmd = uic_cmd; 2473 2474 /* Write Args */ 2475 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2476 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2477 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2478 2479 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2480 2481 /* Write UIC Cmd */ 2482 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2483 REG_UIC_COMMAND); 2484 } 2485 2486 /** 2487 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2488 * @hba: per adapter instance 2489 * @uic_cmd: UIC command 2490 * 2491 * Return: 0 only if success. 2492 */ 2493 static int 2494 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2495 { 2496 int ret; 2497 unsigned long flags; 2498 2499 lockdep_assert_held(&hba->uic_cmd_mutex); 2500 2501 if (wait_for_completion_timeout(&uic_cmd->done, 2502 msecs_to_jiffies(uic_cmd_timeout))) { 2503 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2504 } else { 2505 ret = -ETIMEDOUT; 2506 dev_err(hba->dev, 2507 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2508 uic_cmd->command, uic_cmd->argument3); 2509 2510 if (!uic_cmd->cmd_active) { 2511 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2512 __func__); 2513 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2514 } 2515 } 2516 2517 spin_lock_irqsave(hba->host->host_lock, flags); 2518 hba->active_uic_cmd = NULL; 2519 spin_unlock_irqrestore(hba->host->host_lock, flags); 2520 2521 return ret; 2522 } 2523 2524 /** 2525 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2526 * @hba: per adapter instance 2527 * @uic_cmd: UIC command 2528 * 2529 * Return: 0 only if success. 2530 */ 2531 static int 2532 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2533 { 2534 lockdep_assert_held(&hba->uic_cmd_mutex); 2535 2536 if (!ufshcd_ready_for_uic_cmd(hba)) { 2537 dev_err(hba->dev, 2538 "Controller not ready to accept UIC commands\n"); 2539 return -EIO; 2540 } 2541 2542 init_completion(&uic_cmd->done); 2543 2544 uic_cmd->cmd_active = 1; 2545 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2546 2547 return 0; 2548 } 2549 2550 /** 2551 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2552 * @hba: per adapter instance 2553 * @uic_cmd: UIC command 2554 * 2555 * Return: 0 only if success. 2556 */ 2557 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2558 { 2559 int ret; 2560 2561 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2562 return 0; 2563 2564 ufshcd_hold(hba); 2565 mutex_lock(&hba->uic_cmd_mutex); 2566 ufshcd_add_delay_before_dme_cmd(hba); 2567 2568 ret = __ufshcd_send_uic_cmd(hba, uic_cmd); 2569 if (!ret) 2570 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2571 2572 mutex_unlock(&hba->uic_cmd_mutex); 2573 2574 ufshcd_release(hba); 2575 return ret; 2576 } 2577 2578 /** 2579 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2580 * @hba: per-adapter instance 2581 * @lrbp: pointer to local reference block 2582 * @sg_entries: The number of sg lists actually used 2583 * @sg_list: Pointer to SG list 2584 */ 2585 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2586 struct scatterlist *sg_list) 2587 { 2588 struct ufshcd_sg_entry *prd; 2589 struct scatterlist *sg; 2590 int i; 2591 2592 if (sg_entries) { 2593 2594 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2595 lrbp->utr_descriptor_ptr->prd_table_length = 2596 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2597 else 2598 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2599 2600 prd = lrbp->ucd_prdt_ptr; 2601 2602 for_each_sg(sg_list, sg, sg_entries, i) { 2603 const unsigned int len = sg_dma_len(sg); 2604 2605 /* 2606 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2607 * based value that indicates the length, in bytes, of 2608 * the data block. A maximum of length of 256KB may 2609 * exist for any entry. Bits 1:0 of this field shall be 2610 * 11b to indicate Dword granularity. A value of '3' 2611 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2612 */ 2613 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2614 prd->size = cpu_to_le32(len - 1); 2615 prd->addr = cpu_to_le64(sg->dma_address); 2616 prd->reserved = 0; 2617 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2618 } 2619 } else { 2620 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2621 } 2622 } 2623 2624 /** 2625 * ufshcd_map_sg - Map scatter-gather list to prdt 2626 * @hba: per adapter instance 2627 * @lrbp: pointer to local reference block 2628 * 2629 * Return: 0 in case of success, non-zero value in case of failure. 2630 */ 2631 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2632 { 2633 struct scsi_cmnd *cmd = lrbp->cmd; 2634 int sg_segments = scsi_dma_map(cmd); 2635 2636 if (sg_segments < 0) 2637 return sg_segments; 2638 2639 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2640 2641 return ufshcd_crypto_fill_prdt(hba, lrbp); 2642 } 2643 2644 /** 2645 * ufshcd_enable_intr - enable interrupts 2646 * @hba: per adapter instance 2647 * @intrs: interrupt bits 2648 */ 2649 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2650 { 2651 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2652 2653 set |= intrs; 2654 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2655 } 2656 2657 /** 2658 * ufshcd_disable_intr - disable interrupts 2659 * @hba: per adapter instance 2660 * @intrs: interrupt bits 2661 */ 2662 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2663 { 2664 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2665 2666 set &= ~intrs; 2667 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2668 } 2669 2670 /** 2671 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2672 * descriptor according to request 2673 * @hba: per adapter instance 2674 * @lrbp: pointer to local reference block 2675 * @upiu_flags: flags required in the header 2676 * @cmd_dir: requests data direction 2677 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2678 */ 2679 static void 2680 ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 2681 u8 *upiu_flags, enum dma_data_direction cmd_dir, 2682 int ehs_length) 2683 { 2684 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2685 struct request_desc_header *h = &req_desc->header; 2686 enum utp_data_direction data_direction; 2687 2688 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2689 2690 *h = (typeof(*h)){ }; 2691 2692 if (cmd_dir == DMA_FROM_DEVICE) { 2693 data_direction = UTP_DEVICE_TO_HOST; 2694 *upiu_flags = UPIU_CMD_FLAGS_READ; 2695 } else if (cmd_dir == DMA_TO_DEVICE) { 2696 data_direction = UTP_HOST_TO_DEVICE; 2697 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2698 } else { 2699 data_direction = UTP_NO_DATA_TRANSFER; 2700 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2701 } 2702 2703 h->command_type = lrbp->command_type; 2704 h->data_direction = data_direction; 2705 h->ehs_length = ehs_length; 2706 2707 if (lrbp->intr_cmd) 2708 h->interrupt = 1; 2709 2710 /* Prepare crypto related dwords */ 2711 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2712 2713 /* 2714 * assigning invalid value for command status. Controller 2715 * updates OCS on command completion, with the command 2716 * status 2717 */ 2718 h->ocs = OCS_INVALID_COMMAND_STATUS; 2719 2720 req_desc->prd_table_length = 0; 2721 } 2722 2723 /** 2724 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2725 * for scsi commands 2726 * @lrbp: local reference block pointer 2727 * @upiu_flags: flags 2728 */ 2729 static 2730 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2731 { 2732 struct scsi_cmnd *cmd = lrbp->cmd; 2733 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2734 unsigned short cdb_len; 2735 2736 ucd_req_ptr->header = (struct utp_upiu_header){ 2737 .transaction_code = UPIU_TRANSACTION_COMMAND, 2738 .flags = upiu_flags, 2739 .lun = lrbp->lun, 2740 .task_tag = lrbp->task_tag, 2741 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2742 }; 2743 2744 WARN_ON_ONCE(ucd_req_ptr->header.task_tag != lrbp->task_tag); 2745 2746 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2747 2748 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2749 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2750 2751 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2752 } 2753 2754 /** 2755 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2756 * @hba: UFS hba 2757 * @lrbp: local reference block pointer 2758 * @upiu_flags: flags 2759 */ 2760 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2761 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2762 { 2763 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2764 struct ufs_query *query = &hba->dev_cmd.query; 2765 u16 len = be16_to_cpu(query->request.upiu_req.length); 2766 2767 /* Query request header */ 2768 ucd_req_ptr->header = (struct utp_upiu_header){ 2769 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2770 .flags = upiu_flags, 2771 .lun = lrbp->lun, 2772 .task_tag = lrbp->task_tag, 2773 .query_function = query->request.query_func, 2774 /* Data segment length only need for WRITE_DESC */ 2775 .data_segment_length = 2776 query->request.upiu_req.opcode == 2777 UPIU_QUERY_OPCODE_WRITE_DESC ? 2778 cpu_to_be16(len) : 2779 0, 2780 }; 2781 2782 /* Copy the Query Request buffer as is */ 2783 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2784 QUERY_OSF_SIZE); 2785 2786 /* Copy the Descriptor */ 2787 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2788 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2789 2790 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2791 } 2792 2793 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2794 { 2795 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2796 2797 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2798 2799 ucd_req_ptr->header = (struct utp_upiu_header){ 2800 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2801 .task_tag = lrbp->task_tag, 2802 }; 2803 2804 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2805 } 2806 2807 /** 2808 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2809 * for Device Management Purposes 2810 * @hba: per adapter instance 2811 * @lrbp: pointer to local reference block 2812 * 2813 * Return: 0 upon success; < 0 upon failure. 2814 */ 2815 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2816 struct ufshcd_lrb *lrbp) 2817 { 2818 u8 upiu_flags; 2819 int ret = 0; 2820 2821 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 2822 2823 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2824 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2825 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2826 ufshcd_prepare_utp_nop_upiu(lrbp); 2827 else 2828 ret = -EINVAL; 2829 2830 return ret; 2831 } 2832 2833 /** 2834 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2835 * for SCSI Purposes 2836 * @hba: per adapter instance 2837 * @lrbp: pointer to local reference block 2838 */ 2839 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2840 { 2841 struct request *rq = scsi_cmd_to_rq(lrbp->cmd); 2842 unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq)); 2843 u8 upiu_flags; 2844 2845 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0); 2846 if (ioprio_class == IOPRIO_CLASS_RT) 2847 upiu_flags |= UPIU_CMD_FLAGS_CP; 2848 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2849 } 2850 2851 static void __ufshcd_setup_cmd(struct ufshcd_lrb *lrbp, struct scsi_cmnd *cmd, u8 lun, int tag) 2852 { 2853 memset(lrbp->ucd_req_ptr, 0, sizeof(*lrbp->ucd_req_ptr)); 2854 2855 lrbp->cmd = cmd; 2856 lrbp->task_tag = tag; 2857 lrbp->lun = lun; 2858 ufshcd_prepare_lrbp_crypto(cmd ? scsi_cmd_to_rq(cmd) : NULL, lrbp); 2859 } 2860 2861 static void ufshcd_setup_scsi_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 2862 struct scsi_cmnd *cmd, u8 lun, int tag) 2863 { 2864 __ufshcd_setup_cmd(lrbp, cmd, lun, tag); 2865 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 2866 lrbp->req_abort_skip = false; 2867 2868 ufshcd_comp_scsi_upiu(hba, lrbp); 2869 } 2870 2871 /** 2872 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2873 * @upiu_wlun_id: UPIU W-LUN id 2874 * 2875 * Return: SCSI W-LUN id. 2876 */ 2877 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2878 { 2879 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2880 } 2881 2882 static inline bool is_device_wlun(struct scsi_device *sdev) 2883 { 2884 return sdev->lun == 2885 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2886 } 2887 2888 /* 2889 * Associate the UFS controller queue with the default and poll HCTX types. 2890 * Initialize the mq_map[] arrays. 2891 */ 2892 static void ufshcd_map_queues(struct Scsi_Host *shost) 2893 { 2894 struct ufs_hba *hba = shost_priv(shost); 2895 int i, queue_offset = 0; 2896 2897 if (!is_mcq_supported(hba)) { 2898 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2899 hba->nr_queues[HCTX_TYPE_READ] = 0; 2900 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2901 hba->nr_hw_queues = 1; 2902 } 2903 2904 for (i = 0; i < shost->nr_maps; i++) { 2905 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2906 2907 map->nr_queues = hba->nr_queues[i]; 2908 if (!map->nr_queues) 2909 continue; 2910 map->queue_offset = queue_offset; 2911 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2912 map->queue_offset = 0; 2913 2914 blk_mq_map_queues(map); 2915 queue_offset += map->nr_queues; 2916 } 2917 } 2918 2919 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2920 { 2921 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2922 i * ufshcd_get_ucd_size(hba); 2923 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2924 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2925 i * ufshcd_get_ucd_size(hba); 2926 u16 response_offset = le16_to_cpu(utrdlp[i].response_upiu_offset); 2927 u16 prdt_offset = le16_to_cpu(utrdlp[i].prd_table_offset); 2928 2929 lrb->utr_descriptor_ptr = utrdlp + i; 2930 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2931 i * sizeof(struct utp_transfer_req_desc); 2932 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2933 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2934 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2935 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2936 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2937 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2938 } 2939 2940 /** 2941 * ufshcd_queuecommand - main entry point for SCSI requests 2942 * @host: SCSI host pointer 2943 * @cmd: command from SCSI Midlayer 2944 * 2945 * Return: 0 for success, non-zero in case of failure. 2946 */ 2947 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2948 { 2949 struct ufs_hba *hba = shost_priv(host); 2950 int tag = scsi_cmd_to_rq(cmd)->tag; 2951 struct ufshcd_lrb *lrbp; 2952 int err = 0; 2953 struct ufs_hw_queue *hwq = NULL; 2954 2955 switch (hba->ufshcd_state) { 2956 case UFSHCD_STATE_OPERATIONAL: 2957 break; 2958 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2959 /* 2960 * SCSI error handler can call ->queuecommand() while UFS error 2961 * handler is in progress. Error interrupts could change the 2962 * state from UFSHCD_STATE_RESET to 2963 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2964 * being issued in that case. 2965 */ 2966 if (ufshcd_eh_in_progress(hba)) { 2967 err = SCSI_MLQUEUE_HOST_BUSY; 2968 goto out; 2969 } 2970 break; 2971 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2972 /* 2973 * pm_runtime_get_sync() is used at error handling preparation 2974 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2975 * PM ops, it can never be finished if we let SCSI layer keep 2976 * retrying it, which gets err handler stuck forever. Neither 2977 * can we let the scsi cmd pass through, because UFS is in bad 2978 * state, the scsi cmd may eventually time out, which will get 2979 * err handler blocked for too long. So, just fail the scsi cmd 2980 * sent from PM ops, err handler can recover PM error anyways. 2981 */ 2982 if (hba->pm_op_in_progress) { 2983 hba->force_reset = true; 2984 set_host_byte(cmd, DID_BAD_TARGET); 2985 scsi_done(cmd); 2986 goto out; 2987 } 2988 fallthrough; 2989 case UFSHCD_STATE_RESET: 2990 err = SCSI_MLQUEUE_HOST_BUSY; 2991 goto out; 2992 case UFSHCD_STATE_ERROR: 2993 set_host_byte(cmd, DID_ERROR); 2994 scsi_done(cmd); 2995 goto out; 2996 } 2997 2998 hba->req_abort_count = 0; 2999 3000 ufshcd_hold(hba); 3001 3002 lrbp = &hba->lrb[tag]; 3003 3004 ufshcd_setup_scsi_cmd(hba, lrbp, cmd, ufshcd_scsi_to_upiu_lun(cmd->device->lun), tag); 3005 3006 err = ufshcd_map_sg(hba, lrbp); 3007 if (err) { 3008 ufshcd_release(hba); 3009 goto out; 3010 } 3011 3012 if (hba->mcq_enabled) 3013 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 3014 3015 ufshcd_send_command(hba, tag, hwq); 3016 3017 out: 3018 if (ufs_trigger_eh(hba)) { 3019 unsigned long flags; 3020 3021 spin_lock_irqsave(hba->host->host_lock, flags); 3022 ufshcd_schedule_eh_work(hba); 3023 spin_unlock_irqrestore(hba->host->host_lock, flags); 3024 } 3025 3026 return err; 3027 } 3028 3029 static void ufshcd_setup_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3030 enum dev_cmd_type cmd_type, u8 lun, int tag) 3031 { 3032 __ufshcd_setup_cmd(lrbp, NULL, lun, tag); 3033 lrbp->intr_cmd = true; /* No interrupt aggregation */ 3034 hba->dev_cmd.type = cmd_type; 3035 } 3036 3037 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 3038 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 3039 { 3040 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 3041 3042 return ufshcd_compose_devman_upiu(hba, lrbp); 3043 } 3044 3045 /* 3046 * Check with the block layer if the command is inflight 3047 * @cmd: command to check. 3048 * 3049 * Return: true if command is inflight; false if not. 3050 */ 3051 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 3052 { 3053 return cmd && blk_mq_rq_state(scsi_cmd_to_rq(cmd)) == MQ_RQ_IN_FLIGHT; 3054 } 3055 3056 /* 3057 * Clear the pending command in the controller and wait until 3058 * the controller confirms that the command has been cleared. 3059 * @hba: per adapter instance 3060 * @task_tag: The tag number of the command to be cleared. 3061 */ 3062 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 3063 { 3064 u32 mask; 3065 int err; 3066 3067 if (hba->mcq_enabled) { 3068 /* 3069 * MCQ mode. Clean up the MCQ resources similar to 3070 * what the ufshcd_utrl_clear() does for SDB mode. 3071 */ 3072 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 3073 if (err) { 3074 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 3075 __func__, task_tag, err); 3076 return err; 3077 } 3078 return 0; 3079 } 3080 3081 mask = 1U << task_tag; 3082 3083 /* clear outstanding transaction before retry */ 3084 ufshcd_utrl_clear(hba, mask); 3085 3086 /* 3087 * wait for h/w to clear corresponding bit in door-bell. 3088 * max. wait is 1 sec. 3089 */ 3090 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 3091 mask, ~mask, 1000, 1000); 3092 } 3093 3094 /** 3095 * ufshcd_dev_cmd_completion() - handles device management command responses 3096 * @hba: per adapter instance 3097 * @lrbp: pointer to local reference block 3098 * 3099 * Return: 0 upon success; < 0 upon failure. 3100 */ 3101 static int 3102 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 3103 { 3104 enum upiu_response_transaction resp; 3105 int err = 0; 3106 3107 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 3108 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3109 3110 switch (resp) { 3111 case UPIU_TRANSACTION_NOP_IN: 3112 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3113 err = -EINVAL; 3114 dev_err(hba->dev, "%s: unexpected response %x\n", 3115 __func__, resp); 3116 } 3117 break; 3118 case UPIU_TRANSACTION_QUERY_RSP: { 3119 u8 response = lrbp->ucd_rsp_ptr->header.response; 3120 3121 if (response == 0) 3122 err = ufshcd_copy_query_response(hba, lrbp); 3123 break; 3124 } 3125 case UPIU_TRANSACTION_REJECT_UPIU: 3126 /* TODO: handle Reject UPIU Response */ 3127 err = -EPERM; 3128 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3129 __func__); 3130 break; 3131 case UPIU_TRANSACTION_RESPONSE: 3132 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3133 err = -EINVAL; 3134 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3135 } 3136 break; 3137 default: 3138 err = -EINVAL; 3139 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3140 __func__, resp); 3141 break; 3142 } 3143 3144 return err; 3145 } 3146 3147 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3148 struct ufshcd_lrb *lrbp, int max_timeout) 3149 { 3150 unsigned long time_left = msecs_to_jiffies(max_timeout); 3151 unsigned long flags; 3152 bool pending; 3153 int err; 3154 3155 retry: 3156 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3157 time_left); 3158 3159 if (likely(time_left)) { 3160 /* 3161 * The completion handler called complete() and the caller of 3162 * this function still owns the @lrbp tag so the code below does 3163 * not trigger any race conditions. 3164 */ 3165 hba->dev_cmd.complete = NULL; 3166 err = ufshcd_get_tr_ocs(lrbp, NULL); 3167 if (!err) 3168 err = ufshcd_dev_cmd_completion(hba, lrbp); 3169 } else { 3170 err = -ETIMEDOUT; 3171 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3172 __func__, lrbp->task_tag); 3173 3174 /* MCQ mode */ 3175 if (hba->mcq_enabled) { 3176 /* successfully cleared the command, retry if needed */ 3177 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) 3178 err = -EAGAIN; 3179 hba->dev_cmd.complete = NULL; 3180 return err; 3181 } 3182 3183 /* SDB mode */ 3184 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3185 /* successfully cleared the command, retry if needed */ 3186 err = -EAGAIN; 3187 /* 3188 * Since clearing the command succeeded we also need to 3189 * clear the task tag bit from the outstanding_reqs 3190 * variable. 3191 */ 3192 spin_lock_irqsave(&hba->outstanding_lock, flags); 3193 pending = test_bit(lrbp->task_tag, 3194 &hba->outstanding_reqs); 3195 if (pending) { 3196 hba->dev_cmd.complete = NULL; 3197 __clear_bit(lrbp->task_tag, 3198 &hba->outstanding_reqs); 3199 } 3200 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3201 3202 if (!pending) { 3203 /* 3204 * The completion handler ran while we tried to 3205 * clear the command. 3206 */ 3207 time_left = 1; 3208 goto retry; 3209 } 3210 } else { 3211 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3212 __func__, lrbp->task_tag); 3213 3214 spin_lock_irqsave(&hba->outstanding_lock, flags); 3215 pending = test_bit(lrbp->task_tag, 3216 &hba->outstanding_reqs); 3217 if (pending) 3218 hba->dev_cmd.complete = NULL; 3219 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3220 3221 if (!pending) { 3222 /* 3223 * The completion handler ran while we tried to 3224 * clear the command. 3225 */ 3226 time_left = 1; 3227 goto retry; 3228 } 3229 } 3230 } 3231 3232 return err; 3233 } 3234 3235 static void ufshcd_dev_man_lock(struct ufs_hba *hba) 3236 { 3237 ufshcd_hold(hba); 3238 mutex_lock(&hba->dev_cmd.lock); 3239 down_read(&hba->clk_scaling_lock); 3240 } 3241 3242 static void ufshcd_dev_man_unlock(struct ufs_hba *hba) 3243 { 3244 up_read(&hba->clk_scaling_lock); 3245 mutex_unlock(&hba->dev_cmd.lock); 3246 ufshcd_release(hba); 3247 } 3248 3249 static int ufshcd_issue_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3250 const u32 tag, int timeout) 3251 { 3252 DECLARE_COMPLETION_ONSTACK(wait); 3253 int err; 3254 3255 hba->dev_cmd.complete = &wait; 3256 3257 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3258 3259 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3260 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3261 3262 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3263 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3264 3265 return err; 3266 } 3267 3268 /** 3269 * ufshcd_exec_dev_cmd - API for sending device management requests 3270 * @hba: UFS hba 3271 * @cmd_type: specifies the type (NOP, Query...) 3272 * @timeout: timeout in milliseconds 3273 * 3274 * Return: 0 upon success; < 0 upon failure. 3275 * 3276 * NOTE: Since there is only one available tag for device management commands, 3277 * it is expected you hold the hba->dev_cmd.lock mutex. 3278 */ 3279 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3280 enum dev_cmd_type cmd_type, int timeout) 3281 { 3282 const u32 tag = hba->reserved_slot; 3283 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 3284 int err; 3285 3286 /* Protects use of hba->reserved_slot. */ 3287 lockdep_assert_held(&hba->dev_cmd.lock); 3288 3289 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3290 if (unlikely(err)) 3291 return err; 3292 3293 return ufshcd_issue_dev_cmd(hba, lrbp, tag, timeout); 3294 } 3295 3296 /** 3297 * ufshcd_init_query() - init the query response and request parameters 3298 * @hba: per-adapter instance 3299 * @request: address of the request pointer to be initialized 3300 * @response: address of the response pointer to be initialized 3301 * @opcode: operation to perform 3302 * @idn: flag idn to access 3303 * @index: LU number to access 3304 * @selector: query/flag/descriptor further identification 3305 */ 3306 static inline void ufshcd_init_query(struct ufs_hba *hba, 3307 struct ufs_query_req **request, struct ufs_query_res **response, 3308 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3309 { 3310 *request = &hba->dev_cmd.query.request; 3311 *response = &hba->dev_cmd.query.response; 3312 memset(*request, 0, sizeof(struct ufs_query_req)); 3313 memset(*response, 0, sizeof(struct ufs_query_res)); 3314 (*request)->upiu_req.opcode = opcode; 3315 (*request)->upiu_req.idn = idn; 3316 (*request)->upiu_req.index = index; 3317 (*request)->upiu_req.selector = selector; 3318 } 3319 3320 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3321 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3322 { 3323 int ret; 3324 int retries; 3325 3326 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3327 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3328 if (ret) 3329 dev_dbg(hba->dev, 3330 "%s: failed with error %d, retries %d\n", 3331 __func__, ret, retries); 3332 else 3333 break; 3334 } 3335 3336 if (ret) 3337 dev_err(hba->dev, 3338 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3339 __func__, opcode, idn, ret, retries); 3340 return ret; 3341 } 3342 3343 /** 3344 * ufshcd_query_flag() - API function for sending flag query requests 3345 * @hba: per-adapter instance 3346 * @opcode: flag query to perform 3347 * @idn: flag idn to access 3348 * @index: flag index to access 3349 * @flag_res: the flag value after the query request completes 3350 * 3351 * Return: 0 for success, non-zero in case of failure. 3352 */ 3353 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3354 enum flag_idn idn, u8 index, bool *flag_res) 3355 { 3356 struct ufs_query_req *request = NULL; 3357 struct ufs_query_res *response = NULL; 3358 int err, selector = 0; 3359 int timeout = QUERY_REQ_TIMEOUT; 3360 3361 BUG_ON(!hba); 3362 3363 ufshcd_dev_man_lock(hba); 3364 3365 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3366 selector); 3367 3368 switch (opcode) { 3369 case UPIU_QUERY_OPCODE_SET_FLAG: 3370 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3371 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3372 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3373 break; 3374 case UPIU_QUERY_OPCODE_READ_FLAG: 3375 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3376 if (!flag_res) { 3377 /* No dummy reads */ 3378 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3379 __func__); 3380 err = -EINVAL; 3381 goto out_unlock; 3382 } 3383 break; 3384 default: 3385 dev_err(hba->dev, 3386 "%s: Expected query flag opcode but got = %d\n", 3387 __func__, opcode); 3388 err = -EINVAL; 3389 goto out_unlock; 3390 } 3391 3392 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3393 3394 if (err) { 3395 dev_err(hba->dev, 3396 "%s: Sending flag query for idn %d failed, err = %d\n", 3397 __func__, idn, err); 3398 goto out_unlock; 3399 } 3400 3401 if (flag_res) 3402 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3403 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3404 3405 out_unlock: 3406 ufshcd_dev_man_unlock(hba); 3407 return err; 3408 } 3409 3410 /** 3411 * ufshcd_query_attr - API function for sending attribute requests 3412 * @hba: per-adapter instance 3413 * @opcode: attribute opcode 3414 * @idn: attribute idn to access 3415 * @index: index field 3416 * @selector: selector field 3417 * @attr_val: the attribute value after the query request completes 3418 * 3419 * Return: 0 for success, non-zero in case of failure. 3420 */ 3421 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3422 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3423 { 3424 struct ufs_query_req *request = NULL; 3425 struct ufs_query_res *response = NULL; 3426 int err; 3427 3428 BUG_ON(!hba); 3429 3430 if (!attr_val) { 3431 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3432 __func__, opcode); 3433 return -EINVAL; 3434 } 3435 3436 ufshcd_dev_man_lock(hba); 3437 3438 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3439 selector); 3440 3441 switch (opcode) { 3442 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3443 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3444 request->upiu_req.value = cpu_to_be32(*attr_val); 3445 break; 3446 case UPIU_QUERY_OPCODE_READ_ATTR: 3447 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3448 break; 3449 default: 3450 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3451 __func__, opcode); 3452 err = -EINVAL; 3453 goto out_unlock; 3454 } 3455 3456 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3457 3458 if (err) { 3459 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3460 __func__, opcode, idn, index, err); 3461 goto out_unlock; 3462 } 3463 3464 *attr_val = be32_to_cpu(response->upiu_res.value); 3465 3466 out_unlock: 3467 ufshcd_dev_man_unlock(hba); 3468 return err; 3469 } 3470 3471 /** 3472 * ufshcd_query_attr_retry() - API function for sending query 3473 * attribute with retries 3474 * @hba: per-adapter instance 3475 * @opcode: attribute opcode 3476 * @idn: attribute idn to access 3477 * @index: index field 3478 * @selector: selector field 3479 * @attr_val: the attribute value after the query request 3480 * completes 3481 * 3482 * Return: 0 for success, non-zero in case of failure. 3483 */ 3484 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3485 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3486 u32 *attr_val) 3487 { 3488 int ret = 0; 3489 u32 retries; 3490 3491 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3492 ret = ufshcd_query_attr(hba, opcode, idn, index, 3493 selector, attr_val); 3494 if (ret) 3495 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3496 __func__, ret, retries); 3497 else 3498 break; 3499 } 3500 3501 if (ret) 3502 dev_err(hba->dev, 3503 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3504 __func__, idn, ret, QUERY_REQ_RETRIES); 3505 return ret; 3506 } 3507 3508 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3509 enum query_opcode opcode, enum desc_idn idn, u8 index, 3510 u8 selector, u8 *desc_buf, int *buf_len) 3511 { 3512 struct ufs_query_req *request = NULL; 3513 struct ufs_query_res *response = NULL; 3514 int err; 3515 3516 BUG_ON(!hba); 3517 3518 if (!desc_buf) { 3519 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3520 __func__, opcode); 3521 return -EINVAL; 3522 } 3523 3524 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3525 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3526 __func__, *buf_len); 3527 return -EINVAL; 3528 } 3529 3530 ufshcd_dev_man_lock(hba); 3531 3532 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3533 selector); 3534 hba->dev_cmd.query.descriptor = desc_buf; 3535 request->upiu_req.length = cpu_to_be16(*buf_len); 3536 3537 switch (opcode) { 3538 case UPIU_QUERY_OPCODE_WRITE_DESC: 3539 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3540 break; 3541 case UPIU_QUERY_OPCODE_READ_DESC: 3542 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3543 break; 3544 default: 3545 dev_err(hba->dev, 3546 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3547 __func__, opcode); 3548 err = -EINVAL; 3549 goto out_unlock; 3550 } 3551 3552 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3553 3554 if (err) { 3555 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3556 __func__, opcode, idn, index, err); 3557 goto out_unlock; 3558 } 3559 3560 *buf_len = be16_to_cpu(response->upiu_res.length); 3561 3562 out_unlock: 3563 hba->dev_cmd.query.descriptor = NULL; 3564 ufshcd_dev_man_unlock(hba); 3565 return err; 3566 } 3567 3568 /** 3569 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3570 * @hba: per-adapter instance 3571 * @opcode: attribute opcode 3572 * @idn: attribute idn to access 3573 * @index: index field 3574 * @selector: selector field 3575 * @desc_buf: the buffer that contains the descriptor 3576 * @buf_len: length parameter passed to the device 3577 * 3578 * The buf_len parameter will contain, on return, the length parameter 3579 * received on the response. 3580 * 3581 * Return: 0 for success, non-zero in case of failure. 3582 */ 3583 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3584 enum query_opcode opcode, 3585 enum desc_idn idn, u8 index, 3586 u8 selector, 3587 u8 *desc_buf, int *buf_len) 3588 { 3589 int err; 3590 int retries; 3591 3592 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3593 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3594 selector, desc_buf, buf_len); 3595 if (!err || err == -EINVAL) 3596 break; 3597 } 3598 3599 return err; 3600 } 3601 3602 /** 3603 * ufshcd_read_desc_param - read the specified descriptor parameter 3604 * @hba: Pointer to adapter instance 3605 * @desc_id: descriptor idn value 3606 * @desc_index: descriptor index 3607 * @param_offset: offset of the parameter to read 3608 * @param_read_buf: pointer to buffer where parameter would be read 3609 * @param_size: sizeof(param_read_buf) 3610 * 3611 * Return: 0 in case of success, non-zero otherwise. 3612 */ 3613 int ufshcd_read_desc_param(struct ufs_hba *hba, 3614 enum desc_idn desc_id, 3615 int desc_index, 3616 u8 param_offset, 3617 u8 *param_read_buf, 3618 u8 param_size) 3619 { 3620 int ret; 3621 u8 *desc_buf; 3622 int buff_len = QUERY_DESC_MAX_SIZE; 3623 bool is_kmalloc = true; 3624 3625 /* Safety check */ 3626 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3627 return -EINVAL; 3628 3629 /* Check whether we need temp memory */ 3630 if (param_offset != 0 || param_size < buff_len) { 3631 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3632 if (!desc_buf) 3633 return -ENOMEM; 3634 } else { 3635 desc_buf = param_read_buf; 3636 is_kmalloc = false; 3637 } 3638 3639 /* Request for full descriptor */ 3640 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3641 desc_id, desc_index, 0, 3642 desc_buf, &buff_len); 3643 if (ret) { 3644 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3645 __func__, desc_id, desc_index, param_offset, ret); 3646 goto out; 3647 } 3648 3649 /* Update descriptor length */ 3650 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3651 3652 if (param_offset >= buff_len) { 3653 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3654 __func__, param_offset, desc_id, buff_len); 3655 ret = -EINVAL; 3656 goto out; 3657 } 3658 3659 /* Sanity check */ 3660 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3661 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3662 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3663 ret = -EINVAL; 3664 goto out; 3665 } 3666 3667 if (is_kmalloc) { 3668 /* Make sure we don't copy more data than available */ 3669 if (param_offset >= buff_len) 3670 ret = -EINVAL; 3671 else 3672 memcpy(param_read_buf, &desc_buf[param_offset], 3673 min_t(u32, param_size, buff_len - param_offset)); 3674 } 3675 out: 3676 if (is_kmalloc) 3677 kfree(desc_buf); 3678 return ret; 3679 } 3680 3681 /** 3682 * struct uc_string_id - unicode string 3683 * 3684 * @len: size of this descriptor inclusive 3685 * @type: descriptor type 3686 * @uc: unicode string character 3687 */ 3688 struct uc_string_id { 3689 u8 len; 3690 u8 type; 3691 wchar_t uc[]; 3692 } __packed; 3693 3694 /* replace non-printable or non-ASCII characters with spaces */ 3695 static inline char ufshcd_remove_non_printable(u8 ch) 3696 { 3697 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3698 } 3699 3700 /** 3701 * ufshcd_read_string_desc - read string descriptor 3702 * @hba: pointer to adapter instance 3703 * @desc_index: descriptor index 3704 * @buf: pointer to buffer where descriptor would be read, 3705 * the caller should free the memory. 3706 * @ascii: if true convert from unicode to ascii characters 3707 * null terminated string. 3708 * 3709 * Return: 3710 * * string size on success. 3711 * * -ENOMEM: on allocation failure 3712 * * -EINVAL: on a wrong parameter 3713 */ 3714 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3715 u8 **buf, bool ascii) 3716 { 3717 struct uc_string_id *uc_str; 3718 u8 *str; 3719 int ret; 3720 3721 if (!buf) 3722 return -EINVAL; 3723 3724 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3725 if (!uc_str) 3726 return -ENOMEM; 3727 3728 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3729 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3730 if (ret < 0) { 3731 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3732 QUERY_REQ_RETRIES, ret); 3733 str = NULL; 3734 goto out; 3735 } 3736 3737 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3738 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3739 str = NULL; 3740 ret = 0; 3741 goto out; 3742 } 3743 3744 if (ascii) { 3745 ssize_t ascii_len; 3746 int i; 3747 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3748 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3749 str = kzalloc(ascii_len, GFP_KERNEL); 3750 if (!str) { 3751 ret = -ENOMEM; 3752 goto out; 3753 } 3754 3755 /* 3756 * the descriptor contains string in UTF16 format 3757 * we need to convert to utf-8 so it can be displayed 3758 */ 3759 ret = utf16s_to_utf8s(uc_str->uc, 3760 uc_str->len - QUERY_DESC_HDR_SIZE, 3761 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3762 3763 /* replace non-printable or non-ASCII characters with spaces */ 3764 for (i = 0; i < ret; i++) 3765 str[i] = ufshcd_remove_non_printable(str[i]); 3766 3767 str[ret++] = '\0'; 3768 3769 } else { 3770 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3771 if (!str) { 3772 ret = -ENOMEM; 3773 goto out; 3774 } 3775 ret = uc_str->len; 3776 } 3777 out: 3778 *buf = str; 3779 kfree(uc_str); 3780 return ret; 3781 } 3782 3783 /** 3784 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3785 * @hba: Pointer to adapter instance 3786 * @lun: lun id 3787 * @param_offset: offset of the parameter to read 3788 * @param_read_buf: pointer to buffer where parameter would be read 3789 * @param_size: sizeof(param_read_buf) 3790 * 3791 * Return: 0 in case of success, non-zero otherwise. 3792 */ 3793 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3794 int lun, 3795 enum unit_desc_param param_offset, 3796 u8 *param_read_buf, 3797 u32 param_size) 3798 { 3799 /* 3800 * Unit descriptors are only available for general purpose LUs (LUN id 3801 * from 0 to 7) and RPMB Well known LU. 3802 */ 3803 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3804 return -EOPNOTSUPP; 3805 3806 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3807 param_offset, param_read_buf, param_size); 3808 } 3809 3810 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3811 { 3812 int err = 0; 3813 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3814 3815 if (hba->dev_info.wspecversion >= 0x300) { 3816 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3817 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3818 &gating_wait); 3819 if (err) 3820 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3821 err, gating_wait); 3822 3823 if (gating_wait == 0) { 3824 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3825 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3826 gating_wait); 3827 } 3828 3829 hba->dev_info.clk_gating_wait_us = gating_wait; 3830 } 3831 3832 return err; 3833 } 3834 3835 /** 3836 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3837 * @hba: per adapter instance 3838 * 3839 * 1. Allocate DMA memory for Command Descriptor array 3840 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3841 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3842 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3843 * (UTMRDL) 3844 * 4. Allocate memory for local reference block(lrb). 3845 * 3846 * Return: 0 for success, non-zero in case of failure. 3847 */ 3848 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3849 { 3850 size_t utmrdl_size, utrdl_size, ucdl_size; 3851 3852 /* Allocate memory for UTP command descriptors */ 3853 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3854 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3855 ucdl_size, 3856 &hba->ucdl_dma_addr, 3857 GFP_KERNEL); 3858 3859 /* 3860 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3861 */ 3862 if (!hba->ucdl_base_addr || 3863 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3864 dev_err(hba->dev, 3865 "Command Descriptor Memory allocation failed\n"); 3866 goto out; 3867 } 3868 3869 /* 3870 * Allocate memory for UTP Transfer descriptors 3871 * UFSHCI requires 1KB alignment of UTRD 3872 */ 3873 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3874 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3875 utrdl_size, 3876 &hba->utrdl_dma_addr, 3877 GFP_KERNEL); 3878 if (!hba->utrdl_base_addr || 3879 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3880 dev_err(hba->dev, 3881 "Transfer Descriptor Memory allocation failed\n"); 3882 goto out; 3883 } 3884 3885 /* 3886 * Skip utmrdl allocation; it may have been 3887 * allocated during first pass and not released during 3888 * MCQ memory allocation. 3889 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3890 */ 3891 if (hba->utmrdl_base_addr) 3892 goto skip_utmrdl; 3893 /* 3894 * Allocate memory for UTP Task Management descriptors 3895 * UFSHCI requires 1KB alignment of UTMRD 3896 */ 3897 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3898 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3899 utmrdl_size, 3900 &hba->utmrdl_dma_addr, 3901 GFP_KERNEL); 3902 if (!hba->utmrdl_base_addr || 3903 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3904 dev_err(hba->dev, 3905 "Task Management Descriptor Memory allocation failed\n"); 3906 goto out; 3907 } 3908 3909 skip_utmrdl: 3910 /* Allocate memory for local reference block */ 3911 hba->lrb = devm_kcalloc(hba->dev, 3912 hba->nutrs, sizeof(struct ufshcd_lrb), 3913 GFP_KERNEL); 3914 if (!hba->lrb) { 3915 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3916 goto out; 3917 } 3918 return 0; 3919 out: 3920 return -ENOMEM; 3921 } 3922 3923 /** 3924 * ufshcd_host_memory_configure - configure local reference block with 3925 * memory offsets 3926 * @hba: per adapter instance 3927 * 3928 * Configure Host memory space 3929 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3930 * address. 3931 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3932 * and PRDT offset. 3933 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3934 * into local reference block. 3935 */ 3936 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3937 { 3938 struct utp_transfer_req_desc *utrdlp; 3939 dma_addr_t cmd_desc_dma_addr; 3940 dma_addr_t cmd_desc_element_addr; 3941 u16 response_offset; 3942 u16 prdt_offset; 3943 int cmd_desc_size; 3944 int i; 3945 3946 utrdlp = hba->utrdl_base_addr; 3947 3948 response_offset = 3949 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3950 prdt_offset = 3951 offsetof(struct utp_transfer_cmd_desc, prd_table); 3952 3953 cmd_desc_size = ufshcd_get_ucd_size(hba); 3954 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3955 3956 for (i = 0; i < hba->nutrs; i++) { 3957 /* Configure UTRD with command descriptor base address */ 3958 cmd_desc_element_addr = 3959 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3960 utrdlp[i].command_desc_base_addr = 3961 cpu_to_le64(cmd_desc_element_addr); 3962 3963 /* Response upiu and prdt offset should be in double words */ 3964 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3965 utrdlp[i].response_upiu_offset = 3966 cpu_to_le16(response_offset); 3967 utrdlp[i].prd_table_offset = 3968 cpu_to_le16(prdt_offset); 3969 utrdlp[i].response_upiu_length = 3970 cpu_to_le16(ALIGNED_UPIU_SIZE); 3971 } else { 3972 utrdlp[i].response_upiu_offset = 3973 cpu_to_le16(response_offset >> 2); 3974 utrdlp[i].prd_table_offset = 3975 cpu_to_le16(prdt_offset >> 2); 3976 utrdlp[i].response_upiu_length = 3977 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 3978 } 3979 3980 ufshcd_init_lrb(hba, &hba->lrb[i], i); 3981 } 3982 } 3983 3984 /** 3985 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 3986 * @hba: per adapter instance 3987 * 3988 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 3989 * in order to initialize the Unipro link startup procedure. 3990 * Once the Unipro links are up, the device connected to the controller 3991 * is detected. 3992 * 3993 * Return: 0 on success, non-zero value on failure. 3994 */ 3995 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 3996 { 3997 struct uic_command uic_cmd = { 3998 .command = UIC_CMD_DME_LINK_STARTUP, 3999 }; 4000 int ret; 4001 4002 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4003 if (ret) 4004 dev_dbg(hba->dev, 4005 "dme-link-startup: error code %d\n", ret); 4006 return ret; 4007 } 4008 /** 4009 * ufshcd_dme_reset - UIC command for DME_RESET 4010 * @hba: per adapter instance 4011 * 4012 * DME_RESET command is issued in order to reset UniPro stack. 4013 * This function now deals with cold reset. 4014 * 4015 * Return: 0 on success, non-zero value on failure. 4016 */ 4017 static int ufshcd_dme_reset(struct ufs_hba *hba) 4018 { 4019 struct uic_command uic_cmd = { 4020 .command = UIC_CMD_DME_RESET, 4021 }; 4022 int ret; 4023 4024 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4025 if (ret) 4026 dev_err(hba->dev, 4027 "dme-reset: error code %d\n", ret); 4028 4029 return ret; 4030 } 4031 4032 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 4033 int agreed_gear, 4034 int adapt_val) 4035 { 4036 int ret; 4037 4038 if (agreed_gear < UFS_HS_G4) 4039 adapt_val = PA_NO_ADAPT; 4040 4041 ret = ufshcd_dme_set(hba, 4042 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 4043 adapt_val); 4044 return ret; 4045 } 4046 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 4047 4048 /** 4049 * ufshcd_dme_enable - UIC command for DME_ENABLE 4050 * @hba: per adapter instance 4051 * 4052 * DME_ENABLE command is issued in order to enable UniPro stack. 4053 * 4054 * Return: 0 on success, non-zero value on failure. 4055 */ 4056 static int ufshcd_dme_enable(struct ufs_hba *hba) 4057 { 4058 struct uic_command uic_cmd = { 4059 .command = UIC_CMD_DME_ENABLE, 4060 }; 4061 int ret; 4062 4063 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4064 if (ret) 4065 dev_err(hba->dev, 4066 "dme-enable: error code %d\n", ret); 4067 4068 return ret; 4069 } 4070 4071 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 4072 { 4073 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 4074 unsigned long min_sleep_time_us; 4075 4076 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 4077 return; 4078 4079 /* 4080 * last_dme_cmd_tstamp will be 0 only for 1st call to 4081 * this function 4082 */ 4083 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 4084 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 4085 } else { 4086 unsigned long delta = 4087 (unsigned long) ktime_to_us( 4088 ktime_sub(ktime_get(), 4089 hba->last_dme_cmd_tstamp)); 4090 4091 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 4092 min_sleep_time_us = 4093 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 4094 else 4095 min_sleep_time_us = 0; /* no more delay required */ 4096 } 4097 4098 if (min_sleep_time_us > 0) { 4099 /* allow sleep for extra 50us if needed */ 4100 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 4101 } 4102 4103 /* update the last_dme_cmd_tstamp */ 4104 hba->last_dme_cmd_tstamp = ktime_get(); 4105 } 4106 4107 /** 4108 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 4109 * @hba: per adapter instance 4110 * @attr_sel: uic command argument1 4111 * @attr_set: attribute set type as uic command argument2 4112 * @mib_val: setting value as uic command argument3 4113 * @peer: indicate whether peer or local 4114 * 4115 * Return: 0 on success, non-zero value on failure. 4116 */ 4117 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 4118 u8 attr_set, u32 mib_val, u8 peer) 4119 { 4120 struct uic_command uic_cmd = { 4121 .command = peer ? UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET, 4122 .argument1 = attr_sel, 4123 .argument2 = UIC_ARG_ATTR_TYPE(attr_set), 4124 .argument3 = mib_val, 4125 }; 4126 static const char *const action[] = { 4127 "dme-set", 4128 "dme-peer-set" 4129 }; 4130 const char *set = action[!!peer]; 4131 int ret; 4132 int retries = UFS_UIC_COMMAND_RETRIES; 4133 4134 do { 4135 /* for peer attributes we retry upon failure */ 4136 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4137 if (ret) 4138 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4139 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4140 } while (ret && peer && --retries); 4141 4142 if (ret) 4143 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4144 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4145 UFS_UIC_COMMAND_RETRIES - retries); 4146 4147 return ret; 4148 } 4149 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4150 4151 /** 4152 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4153 * @hba: per adapter instance 4154 * @attr_sel: uic command argument1 4155 * @mib_val: the value of the attribute as returned by the UIC command 4156 * @peer: indicate whether peer or local 4157 * 4158 * Return: 0 on success, non-zero value on failure. 4159 */ 4160 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4161 u32 *mib_val, u8 peer) 4162 { 4163 struct uic_command uic_cmd = { 4164 .command = peer ? UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET, 4165 .argument1 = attr_sel, 4166 }; 4167 static const char *const action[] = { 4168 "dme-get", 4169 "dme-peer-get" 4170 }; 4171 const char *get = action[!!peer]; 4172 int ret; 4173 int retries = UFS_UIC_COMMAND_RETRIES; 4174 struct ufs_pa_layer_attr orig_pwr_info; 4175 struct ufs_pa_layer_attr temp_pwr_info; 4176 bool pwr_mode_change = false; 4177 4178 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4179 orig_pwr_info = hba->pwr_info; 4180 temp_pwr_info = orig_pwr_info; 4181 4182 if (orig_pwr_info.pwr_tx == FAST_MODE || 4183 orig_pwr_info.pwr_rx == FAST_MODE) { 4184 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4185 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4186 pwr_mode_change = true; 4187 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4188 orig_pwr_info.pwr_rx == SLOW_MODE) { 4189 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4190 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4191 pwr_mode_change = true; 4192 } 4193 if (pwr_mode_change) { 4194 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4195 if (ret) 4196 goto out; 4197 } 4198 } 4199 4200 do { 4201 /* for peer attributes we retry upon failure */ 4202 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4203 if (ret) 4204 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4205 get, UIC_GET_ATTR_ID(attr_sel), ret); 4206 } while (ret && peer && --retries); 4207 4208 if (ret) 4209 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4210 get, UIC_GET_ATTR_ID(attr_sel), 4211 UFS_UIC_COMMAND_RETRIES - retries); 4212 4213 if (mib_val && !ret) 4214 *mib_val = uic_cmd.argument3; 4215 4216 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4217 && pwr_mode_change) 4218 ufshcd_change_power_mode(hba, &orig_pwr_info); 4219 out: 4220 return ret; 4221 } 4222 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4223 4224 /** 4225 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4226 * state) and waits for it to take effect. 4227 * 4228 * @hba: per adapter instance 4229 * @cmd: UIC command to execute 4230 * 4231 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4232 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4233 * and device UniPro link and hence it's final completion would be indicated by 4234 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4235 * addition to normal UIC command completion Status (UCCS). This function only 4236 * returns after the relevant status bits indicate the completion. 4237 * 4238 * Return: 0 on success, non-zero value on failure. 4239 */ 4240 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4241 { 4242 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4243 unsigned long flags; 4244 u8 status; 4245 int ret; 4246 bool reenable_intr = false; 4247 4248 mutex_lock(&hba->uic_cmd_mutex); 4249 ufshcd_add_delay_before_dme_cmd(hba); 4250 4251 spin_lock_irqsave(hba->host->host_lock, flags); 4252 if (ufshcd_is_link_broken(hba)) { 4253 ret = -ENOLINK; 4254 goto out_unlock; 4255 } 4256 hba->uic_async_done = &uic_async_done; 4257 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4258 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4259 /* 4260 * Make sure UIC command completion interrupt is disabled before 4261 * issuing UIC command. 4262 */ 4263 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 4264 reenable_intr = true; 4265 } 4266 spin_unlock_irqrestore(hba->host->host_lock, flags); 4267 ret = __ufshcd_send_uic_cmd(hba, cmd); 4268 if (ret) { 4269 dev_err(hba->dev, 4270 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4271 cmd->command, cmd->argument3, ret); 4272 goto out; 4273 } 4274 4275 if (!wait_for_completion_timeout(hba->uic_async_done, 4276 msecs_to_jiffies(uic_cmd_timeout))) { 4277 dev_err(hba->dev, 4278 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4279 cmd->command, cmd->argument3); 4280 4281 if (!cmd->cmd_active) { 4282 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4283 __func__); 4284 goto check_upmcrs; 4285 } 4286 4287 ret = -ETIMEDOUT; 4288 goto out; 4289 } 4290 4291 check_upmcrs: 4292 status = ufshcd_get_upmcrs(hba); 4293 if (status != PWR_LOCAL) { 4294 dev_err(hba->dev, 4295 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4296 cmd->command, status); 4297 ret = (status != PWR_OK) ? status : -1; 4298 } 4299 out: 4300 if (ret) { 4301 ufshcd_print_host_state(hba); 4302 ufshcd_print_pwr_info(hba); 4303 ufshcd_print_evt_hist(hba); 4304 } 4305 4306 spin_lock_irqsave(hba->host->host_lock, flags); 4307 hba->active_uic_cmd = NULL; 4308 hba->uic_async_done = NULL; 4309 if (reenable_intr) 4310 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4311 if (ret) { 4312 ufshcd_set_link_broken(hba); 4313 ufshcd_schedule_eh_work(hba); 4314 } 4315 out_unlock: 4316 spin_unlock_irqrestore(hba->host->host_lock, flags); 4317 mutex_unlock(&hba->uic_cmd_mutex); 4318 4319 return ret; 4320 } 4321 4322 /** 4323 * ufshcd_send_bsg_uic_cmd - Send UIC commands requested via BSG layer and retrieve the result 4324 * @hba: per adapter instance 4325 * @uic_cmd: UIC command 4326 * 4327 * Return: 0 only if success. 4328 */ 4329 int ufshcd_send_bsg_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 4330 { 4331 int ret; 4332 4333 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 4334 return 0; 4335 4336 ufshcd_hold(hba); 4337 4338 if (uic_cmd->argument1 == UIC_ARG_MIB(PA_PWRMODE) && 4339 uic_cmd->command == UIC_CMD_DME_SET) { 4340 ret = ufshcd_uic_pwr_ctrl(hba, uic_cmd); 4341 goto out; 4342 } 4343 4344 mutex_lock(&hba->uic_cmd_mutex); 4345 ufshcd_add_delay_before_dme_cmd(hba); 4346 4347 ret = __ufshcd_send_uic_cmd(hba, uic_cmd); 4348 if (!ret) 4349 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 4350 4351 mutex_unlock(&hba->uic_cmd_mutex); 4352 4353 out: 4354 ufshcd_release(hba); 4355 return ret; 4356 } 4357 4358 /** 4359 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4360 * using DME_SET primitives. 4361 * @hba: per adapter instance 4362 * @mode: powr mode value 4363 * 4364 * Return: 0 on success, non-zero value on failure. 4365 */ 4366 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4367 { 4368 struct uic_command uic_cmd = { 4369 .command = UIC_CMD_DME_SET, 4370 .argument1 = UIC_ARG_MIB(PA_PWRMODE), 4371 .argument3 = mode, 4372 }; 4373 int ret; 4374 4375 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4376 ret = ufshcd_dme_set(hba, 4377 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4378 if (ret) { 4379 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4380 __func__, ret); 4381 goto out; 4382 } 4383 } 4384 4385 ufshcd_hold(hba); 4386 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4387 ufshcd_release(hba); 4388 4389 out: 4390 return ret; 4391 } 4392 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4393 4394 int ufshcd_link_recovery(struct ufs_hba *hba) 4395 { 4396 int ret; 4397 unsigned long flags; 4398 4399 spin_lock_irqsave(hba->host->host_lock, flags); 4400 hba->ufshcd_state = UFSHCD_STATE_RESET; 4401 ufshcd_set_eh_in_progress(hba); 4402 spin_unlock_irqrestore(hba->host->host_lock, flags); 4403 4404 /* Reset the attached device */ 4405 ufshcd_device_reset(hba); 4406 4407 ret = ufshcd_host_reset_and_restore(hba); 4408 4409 spin_lock_irqsave(hba->host->host_lock, flags); 4410 if (ret) 4411 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4412 ufshcd_clear_eh_in_progress(hba); 4413 spin_unlock_irqrestore(hba->host->host_lock, flags); 4414 4415 if (ret) 4416 dev_err(hba->dev, "%s: link recovery failed, err %d", 4417 __func__, ret); 4418 4419 return ret; 4420 } 4421 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4422 4423 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4424 { 4425 struct uic_command uic_cmd = { 4426 .command = UIC_CMD_DME_HIBER_ENTER, 4427 }; 4428 ktime_t start = ktime_get(); 4429 int ret; 4430 4431 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4432 4433 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4434 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4435 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4436 4437 if (ret) 4438 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4439 __func__, ret); 4440 else 4441 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4442 POST_CHANGE); 4443 4444 return ret; 4445 } 4446 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4447 4448 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4449 { 4450 struct uic_command uic_cmd = { 4451 .command = UIC_CMD_DME_HIBER_EXIT, 4452 }; 4453 int ret; 4454 ktime_t start = ktime_get(); 4455 4456 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4457 4458 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4459 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4460 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4461 4462 if (ret) { 4463 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4464 __func__, ret); 4465 } else { 4466 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4467 POST_CHANGE); 4468 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4469 hba->ufs_stats.hibern8_exit_cnt++; 4470 } 4471 4472 return ret; 4473 } 4474 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4475 4476 static void ufshcd_configure_auto_hibern8(struct ufs_hba *hba) 4477 { 4478 if (!ufshcd_is_auto_hibern8_supported(hba)) 4479 return; 4480 4481 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4482 } 4483 4484 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4485 { 4486 const u32 cur_ahit = READ_ONCE(hba->ahit); 4487 4488 if (!ufshcd_is_auto_hibern8_supported(hba) || cur_ahit == ahit) 4489 return; 4490 4491 WRITE_ONCE(hba->ahit, ahit); 4492 if (!pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4493 ufshcd_rpm_get_sync(hba); 4494 ufshcd_hold(hba); 4495 ufshcd_configure_auto_hibern8(hba); 4496 ufshcd_release(hba); 4497 ufshcd_rpm_put_sync(hba); 4498 } 4499 } 4500 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4501 4502 /** 4503 * ufshcd_init_pwr_info - setting the POR (power on reset) 4504 * values in hba power info 4505 * @hba: per-adapter instance 4506 */ 4507 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4508 { 4509 hba->pwr_info.gear_rx = UFS_PWM_G1; 4510 hba->pwr_info.gear_tx = UFS_PWM_G1; 4511 hba->pwr_info.lane_rx = UFS_LANE_1; 4512 hba->pwr_info.lane_tx = UFS_LANE_1; 4513 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4514 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4515 hba->pwr_info.hs_rate = 0; 4516 } 4517 4518 /** 4519 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4520 * @hba: per-adapter instance 4521 * 4522 * Return: 0 upon success; < 0 upon failure. 4523 */ 4524 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4525 { 4526 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4527 4528 if (hba->max_pwr_info.is_valid) 4529 return 0; 4530 4531 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4532 pwr_info->pwr_tx = FASTAUTO_MODE; 4533 pwr_info->pwr_rx = FASTAUTO_MODE; 4534 } else { 4535 pwr_info->pwr_tx = FAST_MODE; 4536 pwr_info->pwr_rx = FAST_MODE; 4537 } 4538 pwr_info->hs_rate = PA_HS_MODE_B; 4539 4540 /* Get the connected lane count */ 4541 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4542 &pwr_info->lane_rx); 4543 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4544 &pwr_info->lane_tx); 4545 4546 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4547 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4548 __func__, 4549 pwr_info->lane_rx, 4550 pwr_info->lane_tx); 4551 return -EINVAL; 4552 } 4553 4554 if (pwr_info->lane_rx != pwr_info->lane_tx) { 4555 dev_err(hba->dev, "%s: asymmetric connected lanes. rx=%d, tx=%d\n", 4556 __func__, 4557 pwr_info->lane_rx, 4558 pwr_info->lane_tx); 4559 return -EINVAL; 4560 } 4561 4562 /* 4563 * First, get the maximum gears of HS speed. 4564 * If a zero value, it means there is no HSGEAR capability. 4565 * Then, get the maximum gears of PWM speed. 4566 */ 4567 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4568 if (!pwr_info->gear_rx) { 4569 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4570 &pwr_info->gear_rx); 4571 if (!pwr_info->gear_rx) { 4572 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4573 __func__, pwr_info->gear_rx); 4574 return -EINVAL; 4575 } 4576 pwr_info->pwr_rx = SLOW_MODE; 4577 } 4578 4579 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4580 &pwr_info->gear_tx); 4581 if (!pwr_info->gear_tx) { 4582 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4583 &pwr_info->gear_tx); 4584 if (!pwr_info->gear_tx) { 4585 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4586 __func__, pwr_info->gear_tx); 4587 return -EINVAL; 4588 } 4589 pwr_info->pwr_tx = SLOW_MODE; 4590 } 4591 4592 hba->max_pwr_info.is_valid = true; 4593 return 0; 4594 } 4595 4596 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4597 struct ufs_pa_layer_attr *pwr_mode) 4598 { 4599 int ret; 4600 4601 /* if already configured to the requested pwr_mode */ 4602 if (!hba->force_pmc && 4603 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4604 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4605 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4606 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4607 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4608 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4609 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4610 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4611 return 0; 4612 } 4613 4614 /* 4615 * Configure attributes for power mode change with below. 4616 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4617 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4618 * - PA_HSSERIES 4619 */ 4620 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4621 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4622 pwr_mode->lane_rx); 4623 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4624 pwr_mode->pwr_rx == FAST_MODE) 4625 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4626 else 4627 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4628 4629 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4630 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4631 pwr_mode->lane_tx); 4632 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4633 pwr_mode->pwr_tx == FAST_MODE) 4634 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4635 else 4636 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4637 4638 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4639 pwr_mode->pwr_tx == FASTAUTO_MODE || 4640 pwr_mode->pwr_rx == FAST_MODE || 4641 pwr_mode->pwr_tx == FAST_MODE) 4642 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4643 pwr_mode->hs_rate); 4644 4645 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4646 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4647 DL_FC0ProtectionTimeOutVal_Default); 4648 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4649 DL_TC0ReplayTimeOutVal_Default); 4650 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4651 DL_AFC0ReqTimeOutVal_Default); 4652 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4653 DL_FC1ProtectionTimeOutVal_Default); 4654 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4655 DL_TC1ReplayTimeOutVal_Default); 4656 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4657 DL_AFC1ReqTimeOutVal_Default); 4658 4659 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4660 DL_FC0ProtectionTimeOutVal_Default); 4661 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4662 DL_TC0ReplayTimeOutVal_Default); 4663 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4664 DL_AFC0ReqTimeOutVal_Default); 4665 } 4666 4667 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4668 | pwr_mode->pwr_tx); 4669 4670 if (ret) { 4671 dev_err(hba->dev, 4672 "%s: power mode change failed %d\n", __func__, ret); 4673 } else { 4674 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4675 pwr_mode); 4676 4677 memcpy(&hba->pwr_info, pwr_mode, 4678 sizeof(struct ufs_pa_layer_attr)); 4679 } 4680 4681 return ret; 4682 } 4683 4684 /** 4685 * ufshcd_config_pwr_mode - configure a new power mode 4686 * @hba: per-adapter instance 4687 * @desired_pwr_mode: desired power configuration 4688 * 4689 * Return: 0 upon success; < 0 upon failure. 4690 */ 4691 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4692 struct ufs_pa_layer_attr *desired_pwr_mode) 4693 { 4694 struct ufs_pa_layer_attr final_params = { 0 }; 4695 int ret; 4696 4697 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4698 desired_pwr_mode, &final_params); 4699 4700 if (ret) 4701 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4702 4703 ret = ufshcd_change_power_mode(hba, &final_params); 4704 4705 return ret; 4706 } 4707 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4708 4709 /** 4710 * ufshcd_complete_dev_init() - checks device readiness 4711 * @hba: per-adapter instance 4712 * 4713 * Set fDeviceInit flag and poll until device toggles it. 4714 * 4715 * Return: 0 upon success; < 0 upon failure. 4716 */ 4717 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4718 { 4719 int err; 4720 bool flag_res = true; 4721 ktime_t timeout; 4722 4723 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4724 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4725 if (err) { 4726 dev_err(hba->dev, 4727 "%s: setting fDeviceInit flag failed with error %d\n", 4728 __func__, err); 4729 goto out; 4730 } 4731 4732 /* Poll fDeviceInit flag to be cleared */ 4733 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4734 do { 4735 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4736 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4737 if (!flag_res) 4738 break; 4739 usleep_range(500, 1000); 4740 } while (ktime_before(ktime_get(), timeout)); 4741 4742 if (err) { 4743 dev_err(hba->dev, 4744 "%s: reading fDeviceInit flag failed with error %d\n", 4745 __func__, err); 4746 } else if (flag_res) { 4747 dev_err(hba->dev, 4748 "%s: fDeviceInit was not cleared by the device\n", 4749 __func__); 4750 err = -EBUSY; 4751 } 4752 out: 4753 return err; 4754 } 4755 4756 /** 4757 * ufshcd_make_hba_operational - Make UFS controller operational 4758 * @hba: per adapter instance 4759 * 4760 * To bring UFS host controller to operational state, 4761 * 1. Enable required interrupts 4762 * 2. Configure interrupt aggregation 4763 * 3. Program UTRL and UTMRL base address 4764 * 4. Configure run-stop-registers 4765 * 4766 * Return: 0 on success, non-zero value on failure. 4767 */ 4768 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4769 { 4770 int err = 0; 4771 u32 reg; 4772 4773 /* Enable required interrupts */ 4774 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4775 4776 /* Configure interrupt aggregation */ 4777 if (ufshcd_is_intr_aggr_allowed(hba)) 4778 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4779 else 4780 ufshcd_disable_intr_aggr(hba); 4781 4782 /* Configure UTRL and UTMRL base address registers */ 4783 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4784 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4785 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4786 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4787 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4788 REG_UTP_TASK_REQ_LIST_BASE_L); 4789 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4790 REG_UTP_TASK_REQ_LIST_BASE_H); 4791 4792 /* 4793 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4794 */ 4795 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4796 if (!(ufshcd_get_lists_status(reg))) { 4797 ufshcd_enable_run_stop_reg(hba); 4798 } else { 4799 dev_err(hba->dev, 4800 "Host controller not ready to process requests"); 4801 err = -EIO; 4802 } 4803 4804 return err; 4805 } 4806 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4807 4808 /** 4809 * ufshcd_hba_stop - Send controller to reset state 4810 * @hba: per adapter instance 4811 */ 4812 void ufshcd_hba_stop(struct ufs_hba *hba) 4813 { 4814 unsigned long flags; 4815 int err; 4816 4817 /* 4818 * Obtain the host lock to prevent that the controller is disabled 4819 * while the UFS interrupt handler is active on another CPU. 4820 */ 4821 spin_lock_irqsave(hba->host->host_lock, flags); 4822 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4823 spin_unlock_irqrestore(hba->host->host_lock, flags); 4824 4825 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4826 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4827 10, 1); 4828 if (err) 4829 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4830 } 4831 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4832 4833 /** 4834 * ufshcd_hba_execute_hce - initialize the controller 4835 * @hba: per adapter instance 4836 * 4837 * The controller resets itself and controller firmware initialization 4838 * sequence kicks off. When controller is ready it will set 4839 * the Host Controller Enable bit to 1. 4840 * 4841 * Return: 0 on success, non-zero value on failure. 4842 */ 4843 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4844 { 4845 int retry; 4846 4847 for (retry = 3; retry > 0; retry--) { 4848 if (ufshcd_is_hba_active(hba)) 4849 /* change controller state to "reset state" */ 4850 ufshcd_hba_stop(hba); 4851 4852 /* UniPro link is disabled at this point */ 4853 ufshcd_set_link_off(hba); 4854 4855 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4856 4857 /* start controller initialization sequence */ 4858 ufshcd_hba_start(hba); 4859 4860 /* 4861 * To initialize a UFS host controller HCE bit must be set to 1. 4862 * During initialization the HCE bit value changes from 1->0->1. 4863 * When the host controller completes initialization sequence 4864 * it sets the value of HCE bit to 1. The same HCE bit is read back 4865 * to check if the controller has completed initialization sequence. 4866 * So without this delay the value HCE = 1, set in the previous 4867 * instruction might be read back. 4868 * This delay can be changed based on the controller. 4869 */ 4870 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4871 4872 /* wait for the host controller to complete initialization */ 4873 if (!ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, CONTROLLER_ENABLE, 4874 CONTROLLER_ENABLE, 1000, 50)) 4875 break; 4876 4877 dev_err(hba->dev, "Enabling the controller failed\n"); 4878 } 4879 4880 if (!retry) 4881 return -EIO; 4882 4883 /* enable UIC related interrupts */ 4884 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4885 4886 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4887 4888 return 0; 4889 } 4890 4891 int ufshcd_hba_enable(struct ufs_hba *hba) 4892 { 4893 int ret; 4894 4895 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4896 ufshcd_set_link_off(hba); 4897 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4898 4899 /* enable UIC related interrupts */ 4900 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4901 ret = ufshcd_dme_reset(hba); 4902 if (ret) { 4903 dev_err(hba->dev, "DME_RESET failed\n"); 4904 return ret; 4905 } 4906 4907 ret = ufshcd_dme_enable(hba); 4908 if (ret) { 4909 dev_err(hba->dev, "Enabling DME failed\n"); 4910 return ret; 4911 } 4912 4913 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4914 } else { 4915 ret = ufshcd_hba_execute_hce(hba); 4916 } 4917 4918 return ret; 4919 } 4920 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4921 4922 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4923 { 4924 int tx_lanes = 0, i, err = 0; 4925 4926 if (!peer) 4927 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4928 &tx_lanes); 4929 else 4930 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4931 &tx_lanes); 4932 for (i = 0; i < tx_lanes; i++) { 4933 if (!peer) 4934 err = ufshcd_dme_set(hba, 4935 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4936 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4937 0); 4938 else 4939 err = ufshcd_dme_peer_set(hba, 4940 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4941 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4942 0); 4943 if (err) { 4944 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4945 __func__, peer, i, err); 4946 break; 4947 } 4948 } 4949 4950 return err; 4951 } 4952 4953 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4954 { 4955 return ufshcd_disable_tx_lcc(hba, true); 4956 } 4957 4958 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4959 { 4960 struct ufs_event_hist *e; 4961 4962 if (id >= UFS_EVT_CNT) 4963 return; 4964 4965 e = &hba->ufs_stats.event[id]; 4966 e->val[e->pos] = val; 4967 e->tstamp[e->pos] = local_clock(); 4968 e->cnt += 1; 4969 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4970 4971 ufshcd_vops_event_notify(hba, id, &val); 4972 } 4973 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4974 4975 /** 4976 * ufshcd_link_startup - Initialize unipro link startup 4977 * @hba: per adapter instance 4978 * 4979 * Return: 0 for success, non-zero in case of failure. 4980 */ 4981 static int ufshcd_link_startup(struct ufs_hba *hba) 4982 { 4983 int ret; 4984 int retries = DME_LINKSTARTUP_RETRIES; 4985 bool link_startup_again = false; 4986 4987 /* 4988 * If UFS device isn't active then we will have to issue link startup 4989 * 2 times to make sure the device state move to active. 4990 */ 4991 if (!ufshcd_is_ufs_dev_active(hba)) 4992 link_startup_again = true; 4993 4994 link_startup: 4995 do { 4996 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4997 4998 ret = ufshcd_dme_link_startup(hba); 4999 5000 /* check if device is detected by inter-connect layer */ 5001 if (!ret && !ufshcd_is_device_present(hba)) { 5002 ufshcd_update_evt_hist(hba, 5003 UFS_EVT_LINK_STARTUP_FAIL, 5004 0); 5005 dev_err(hba->dev, "%s: Device not present\n", __func__); 5006 ret = -ENXIO; 5007 goto out; 5008 } 5009 5010 /* 5011 * DME link lost indication is only received when link is up, 5012 * but we can't be sure if the link is up until link startup 5013 * succeeds. So reset the local Uni-Pro and try again. 5014 */ 5015 if (ret && retries && ufshcd_hba_enable(hba)) { 5016 ufshcd_update_evt_hist(hba, 5017 UFS_EVT_LINK_STARTUP_FAIL, 5018 (u32)ret); 5019 goto out; 5020 } 5021 } while (ret && retries--); 5022 5023 if (ret) { 5024 /* failed to get the link up... retire */ 5025 ufshcd_update_evt_hist(hba, 5026 UFS_EVT_LINK_STARTUP_FAIL, 5027 (u32)ret); 5028 goto out; 5029 } 5030 5031 if (link_startup_again) { 5032 link_startup_again = false; 5033 retries = DME_LINKSTARTUP_RETRIES; 5034 goto link_startup; 5035 } 5036 5037 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 5038 ufshcd_init_pwr_info(hba); 5039 ufshcd_print_pwr_info(hba); 5040 5041 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 5042 ret = ufshcd_disable_device_tx_lcc(hba); 5043 if (ret) 5044 goto out; 5045 } 5046 5047 /* Include any host controller configuration via UIC commands */ 5048 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 5049 if (ret) 5050 goto out; 5051 5052 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 5053 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 5054 ret = ufshcd_make_hba_operational(hba); 5055 out: 5056 if (ret) { 5057 dev_err(hba->dev, "link startup failed %d\n", ret); 5058 ufshcd_print_host_state(hba); 5059 ufshcd_print_pwr_info(hba); 5060 ufshcd_print_evt_hist(hba); 5061 } 5062 return ret; 5063 } 5064 5065 /** 5066 * ufshcd_verify_dev_init() - Verify device initialization 5067 * @hba: per-adapter instance 5068 * 5069 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 5070 * device Transport Protocol (UTP) layer is ready after a reset. 5071 * If the UTP layer at the device side is not initialized, it may 5072 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 5073 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 5074 * 5075 * Return: 0 upon success; < 0 upon failure. 5076 */ 5077 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 5078 { 5079 int err = 0; 5080 int retries; 5081 5082 ufshcd_dev_man_lock(hba); 5083 5084 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 5085 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 5086 hba->nop_out_timeout); 5087 5088 if (!err || err == -ETIMEDOUT) 5089 break; 5090 5091 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 5092 } 5093 5094 ufshcd_dev_man_unlock(hba); 5095 5096 if (err) 5097 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 5098 return err; 5099 } 5100 5101 /** 5102 * ufshcd_setup_links - associate link b/w device wlun and other luns 5103 * @sdev: pointer to SCSI device 5104 * @hba: pointer to ufs hba 5105 */ 5106 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 5107 { 5108 struct device_link *link; 5109 5110 /* 5111 * Device wlun is the supplier & rest of the luns are consumers. 5112 * This ensures that device wlun suspends after all other luns. 5113 */ 5114 if (hba->ufs_device_wlun) { 5115 link = device_link_add(&sdev->sdev_gendev, 5116 &hba->ufs_device_wlun->sdev_gendev, 5117 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 5118 if (!link) { 5119 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 5120 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 5121 return; 5122 } 5123 hba->luns_avail--; 5124 /* Ignore REPORT_LUN wlun probing */ 5125 if (hba->luns_avail == 1) { 5126 ufshcd_rpm_put(hba); 5127 return; 5128 } 5129 } else { 5130 /* 5131 * Device wlun is probed. The assumption is that WLUNs are 5132 * scanned before other LUNs. 5133 */ 5134 hba->luns_avail--; 5135 } 5136 } 5137 5138 /** 5139 * ufshcd_lu_init - Initialize the relevant parameters of the LU 5140 * @hba: per-adapter instance 5141 * @sdev: pointer to SCSI device 5142 */ 5143 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 5144 { 5145 int len = QUERY_DESC_MAX_SIZE; 5146 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 5147 u8 lun_qdepth = hba->nutrs; 5148 u8 *desc_buf; 5149 int ret; 5150 5151 desc_buf = kzalloc(len, GFP_KERNEL); 5152 if (!desc_buf) 5153 goto set_qdepth; 5154 5155 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5156 if (ret < 0) { 5157 if (ret == -EOPNOTSUPP) 5158 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5159 lun_qdepth = 1; 5160 kfree(desc_buf); 5161 goto set_qdepth; 5162 } 5163 5164 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5165 /* 5166 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5167 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5168 */ 5169 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5170 } 5171 /* 5172 * According to UFS device specification, the write protection mode is only supported by 5173 * normal LU, not supported by WLUN. 5174 */ 5175 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5176 !hba->dev_info.is_lu_power_on_wp && 5177 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5178 hba->dev_info.is_lu_power_on_wp = true; 5179 5180 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5181 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5182 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5183 hba->dev_info.b_advanced_rpmb_en = true; 5184 5185 5186 kfree(desc_buf); 5187 set_qdepth: 5188 /* 5189 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5190 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5191 */ 5192 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5193 scsi_change_queue_depth(sdev, lun_qdepth); 5194 } 5195 5196 /** 5197 * ufshcd_slave_alloc - handle initial SCSI device configurations 5198 * @sdev: pointer to SCSI device 5199 * 5200 * Return: success. 5201 */ 5202 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5203 { 5204 struct ufs_hba *hba; 5205 5206 hba = shost_priv(sdev->host); 5207 5208 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5209 sdev->use_10_for_ms = 1; 5210 5211 /* DBD field should be set to 1 in mode sense(10) */ 5212 sdev->set_dbd_for_ms = 1; 5213 5214 /* allow SCSI layer to restart the device in case of errors */ 5215 sdev->allow_restart = 1; 5216 5217 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5218 sdev->no_report_opcodes = 1; 5219 5220 /* WRITE_SAME command is not supported */ 5221 sdev->no_write_same = 1; 5222 5223 ufshcd_lu_init(hba, sdev); 5224 5225 ufshcd_setup_links(hba, sdev); 5226 5227 return 0; 5228 } 5229 5230 /** 5231 * ufshcd_change_queue_depth - change queue depth 5232 * @sdev: pointer to SCSI device 5233 * @depth: required depth to set 5234 * 5235 * Change queue depth and make sure the max. limits are not crossed. 5236 * 5237 * Return: new queue depth. 5238 */ 5239 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5240 { 5241 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5242 } 5243 5244 /** 5245 * ufshcd_device_configure - adjust SCSI device configurations 5246 * @sdev: pointer to SCSI device 5247 * @lim: queue limits 5248 * 5249 * Return: 0 (success). 5250 */ 5251 static int ufshcd_device_configure(struct scsi_device *sdev, 5252 struct queue_limits *lim) 5253 { 5254 struct ufs_hba *hba = shost_priv(sdev->host); 5255 struct request_queue *q = sdev->request_queue; 5256 5257 lim->dma_pad_mask = PRDT_DATA_BYTE_COUNT_PAD - 1; 5258 5259 /* 5260 * Block runtime-pm until all consumers are added. 5261 * Refer ufshcd_setup_links(). 5262 */ 5263 if (is_device_wlun(sdev)) 5264 pm_runtime_get_noresume(&sdev->sdev_gendev); 5265 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5266 sdev->rpm_autosuspend = 1; 5267 /* 5268 * Do not print messages during runtime PM to avoid never-ending cycles 5269 * of messages written back to storage by user space causing runtime 5270 * resume, causing more messages and so on. 5271 */ 5272 sdev->silence_suspend = 1; 5273 5274 if (hba->vops && hba->vops->config_scsi_dev) 5275 hba->vops->config_scsi_dev(sdev); 5276 5277 ufshcd_crypto_register(hba, q); 5278 5279 return 0; 5280 } 5281 5282 /** 5283 * ufshcd_slave_destroy - remove SCSI device configurations 5284 * @sdev: pointer to SCSI device 5285 */ 5286 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5287 { 5288 struct ufs_hba *hba; 5289 unsigned long flags; 5290 5291 hba = shost_priv(sdev->host); 5292 5293 /* Drop the reference as it won't be needed anymore */ 5294 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5295 spin_lock_irqsave(hba->host->host_lock, flags); 5296 hba->ufs_device_wlun = NULL; 5297 spin_unlock_irqrestore(hba->host->host_lock, flags); 5298 } else if (hba->ufs_device_wlun) { 5299 struct device *supplier = NULL; 5300 5301 /* Ensure UFS Device WLUN exists and does not disappear */ 5302 spin_lock_irqsave(hba->host->host_lock, flags); 5303 if (hba->ufs_device_wlun) { 5304 supplier = &hba->ufs_device_wlun->sdev_gendev; 5305 get_device(supplier); 5306 } 5307 spin_unlock_irqrestore(hba->host->host_lock, flags); 5308 5309 if (supplier) { 5310 /* 5311 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5312 * device will not have been registered but can still 5313 * have a device link holding a reference to the device. 5314 */ 5315 device_link_remove(&sdev->sdev_gendev, supplier); 5316 put_device(supplier); 5317 } 5318 } 5319 } 5320 5321 /** 5322 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5323 * @lrbp: pointer to local reference block of completed command 5324 * @scsi_status: SCSI command status 5325 * 5326 * Return: value base on SCSI command status. 5327 */ 5328 static inline int 5329 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5330 { 5331 int result = 0; 5332 5333 switch (scsi_status) { 5334 case SAM_STAT_CHECK_CONDITION: 5335 ufshcd_copy_sense_data(lrbp); 5336 fallthrough; 5337 case SAM_STAT_GOOD: 5338 result |= DID_OK << 16 | scsi_status; 5339 break; 5340 case SAM_STAT_TASK_SET_FULL: 5341 case SAM_STAT_BUSY: 5342 case SAM_STAT_TASK_ABORTED: 5343 ufshcd_copy_sense_data(lrbp); 5344 result |= scsi_status; 5345 break; 5346 default: 5347 result |= DID_ERROR << 16; 5348 break; 5349 } /* end of switch */ 5350 5351 return result; 5352 } 5353 5354 /** 5355 * ufshcd_transfer_rsp_status - Get overall status of the response 5356 * @hba: per adapter instance 5357 * @lrbp: pointer to local reference block of completed command 5358 * @cqe: pointer to the completion queue entry 5359 * 5360 * Return: result of the command to notify SCSI midlayer. 5361 */ 5362 static inline int 5363 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5364 struct cq_entry *cqe) 5365 { 5366 int result = 0; 5367 int scsi_status; 5368 enum utp_ocs ocs; 5369 u8 upiu_flags; 5370 u32 resid; 5371 5372 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5373 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5374 /* 5375 * Test !overflow instead of underflow to support UFS devices that do 5376 * not set either flag. 5377 */ 5378 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5379 scsi_set_resid(lrbp->cmd, resid); 5380 5381 /* overall command status of utrd */ 5382 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5383 5384 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5385 if (lrbp->ucd_rsp_ptr->header.response || 5386 lrbp->ucd_rsp_ptr->header.status) 5387 ocs = OCS_SUCCESS; 5388 } 5389 5390 switch (ocs) { 5391 case OCS_SUCCESS: 5392 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5393 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5394 case UPIU_TRANSACTION_RESPONSE: 5395 /* 5396 * get the result based on SCSI status response 5397 * to notify the SCSI midlayer of the command status 5398 */ 5399 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5400 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5401 5402 /* 5403 * Currently we are only supporting BKOPs exception 5404 * events hence we can ignore BKOPs exception event 5405 * during power management callbacks. BKOPs exception 5406 * event is not expected to be raised in runtime suspend 5407 * callback as it allows the urgent bkops. 5408 * During system suspend, we are anyway forcefully 5409 * disabling the bkops and if urgent bkops is needed 5410 * it will be enabled on system resume. Long term 5411 * solution could be to abort the system suspend if 5412 * UFS device needs urgent BKOPs. 5413 */ 5414 if (!hba->pm_op_in_progress && 5415 !ufshcd_eh_in_progress(hba) && 5416 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5417 /* Flushed in suspend */ 5418 schedule_work(&hba->eeh_work); 5419 break; 5420 case UPIU_TRANSACTION_REJECT_UPIU: 5421 /* TODO: handle Reject UPIU Response */ 5422 result = DID_ERROR << 16; 5423 dev_err(hba->dev, 5424 "Reject UPIU not fully implemented\n"); 5425 break; 5426 default: 5427 dev_err(hba->dev, 5428 "Unexpected request response code = %x\n", 5429 result); 5430 result = DID_ERROR << 16; 5431 break; 5432 } 5433 break; 5434 case OCS_ABORTED: 5435 case OCS_INVALID_COMMAND_STATUS: 5436 result |= DID_REQUEUE << 16; 5437 dev_warn(hba->dev, 5438 "OCS %s from controller for tag %d\n", 5439 (ocs == OCS_ABORTED ? "aborted" : "invalid"), 5440 lrbp->task_tag); 5441 break; 5442 case OCS_INVALID_CMD_TABLE_ATTR: 5443 case OCS_INVALID_PRDT_ATTR: 5444 case OCS_MISMATCH_DATA_BUF_SIZE: 5445 case OCS_MISMATCH_RESP_UPIU_SIZE: 5446 case OCS_PEER_COMM_FAILURE: 5447 case OCS_FATAL_ERROR: 5448 case OCS_DEVICE_FATAL_ERROR: 5449 case OCS_INVALID_CRYPTO_CONFIG: 5450 case OCS_GENERAL_CRYPTO_ERROR: 5451 default: 5452 result |= DID_ERROR << 16; 5453 dev_err(hba->dev, 5454 "OCS error from controller = %x for tag %d\n", 5455 ocs, lrbp->task_tag); 5456 ufshcd_print_evt_hist(hba); 5457 ufshcd_print_host_state(hba); 5458 break; 5459 } /* end of switch */ 5460 5461 if ((host_byte(result) != DID_OK) && 5462 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5463 ufshcd_print_tr(hba, lrbp->task_tag, true); 5464 return result; 5465 } 5466 5467 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5468 u32 intr_mask) 5469 { 5470 if (!ufshcd_is_auto_hibern8_supported(hba) || 5471 !ufshcd_is_auto_hibern8_enabled(hba)) 5472 return false; 5473 5474 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5475 return false; 5476 5477 if (hba->active_uic_cmd && 5478 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5479 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5480 return false; 5481 5482 return true; 5483 } 5484 5485 /** 5486 * ufshcd_uic_cmd_compl - handle completion of uic command 5487 * @hba: per adapter instance 5488 * @intr_status: interrupt status generated by the controller 5489 * 5490 * Return: 5491 * IRQ_HANDLED - If interrupt is valid 5492 * IRQ_NONE - If invalid interrupt 5493 */ 5494 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5495 { 5496 irqreturn_t retval = IRQ_NONE; 5497 struct uic_command *cmd; 5498 5499 spin_lock(hba->host->host_lock); 5500 cmd = hba->active_uic_cmd; 5501 if (WARN_ON_ONCE(!cmd)) 5502 goto unlock; 5503 5504 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5505 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5506 5507 if (intr_status & UIC_COMMAND_COMPL) { 5508 cmd->argument2 |= ufshcd_get_uic_cmd_result(hba); 5509 cmd->argument3 = ufshcd_get_dme_attr_val(hba); 5510 if (!hba->uic_async_done) 5511 cmd->cmd_active = 0; 5512 complete(&cmd->done); 5513 retval = IRQ_HANDLED; 5514 } 5515 5516 if (intr_status & UFSHCD_UIC_PWR_MASK && hba->uic_async_done) { 5517 cmd->cmd_active = 0; 5518 complete(hba->uic_async_done); 5519 retval = IRQ_HANDLED; 5520 } 5521 5522 if (retval == IRQ_HANDLED) 5523 ufshcd_add_uic_command_trace(hba, cmd, UFS_CMD_COMP); 5524 5525 unlock: 5526 spin_unlock(hba->host->host_lock); 5527 5528 return retval; 5529 } 5530 5531 /* Release the resources allocated for processing a SCSI command. */ 5532 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5533 struct ufshcd_lrb *lrbp) 5534 { 5535 struct scsi_cmnd *cmd = lrbp->cmd; 5536 5537 scsi_dma_unmap(cmd); 5538 ufshcd_crypto_clear_prdt(hba, lrbp); 5539 ufshcd_release(hba); 5540 ufshcd_clk_scaling_update_busy(hba); 5541 } 5542 5543 /** 5544 * ufshcd_compl_one_cqe - handle a completion queue entry 5545 * @hba: per adapter instance 5546 * @task_tag: the task tag of the request to be completed 5547 * @cqe: pointer to the completion queue entry 5548 */ 5549 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5550 struct cq_entry *cqe) 5551 { 5552 struct ufshcd_lrb *lrbp; 5553 struct scsi_cmnd *cmd; 5554 enum utp_ocs ocs; 5555 5556 lrbp = &hba->lrb[task_tag]; 5557 lrbp->compl_time_stamp = ktime_get(); 5558 cmd = lrbp->cmd; 5559 if (cmd) { 5560 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5561 ufshcd_update_monitor(hba, lrbp); 5562 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5563 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5564 ufshcd_release_scsi_cmd(hba, lrbp); 5565 /* Do not touch lrbp after scsi done */ 5566 scsi_done(cmd); 5567 } else if (hba->dev_cmd.complete) { 5568 if (cqe) { 5569 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5570 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5571 } 5572 complete(hba->dev_cmd.complete); 5573 } 5574 } 5575 5576 /** 5577 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5578 * @hba: per adapter instance 5579 * @completed_reqs: bitmask that indicates which requests to complete 5580 */ 5581 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5582 unsigned long completed_reqs) 5583 { 5584 int tag; 5585 5586 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5587 ufshcd_compl_one_cqe(hba, tag, NULL); 5588 } 5589 5590 /* Any value that is not an existing queue number is fine for this constant. */ 5591 enum { 5592 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5593 }; 5594 5595 static void ufshcd_clear_polled(struct ufs_hba *hba, 5596 unsigned long *completed_reqs) 5597 { 5598 int tag; 5599 5600 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5601 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5602 5603 if (!cmd) 5604 continue; 5605 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5606 __clear_bit(tag, completed_reqs); 5607 } 5608 } 5609 5610 /* 5611 * Return: > 0 if one or more commands have been completed or 0 if no 5612 * requests have been completed. 5613 */ 5614 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5615 { 5616 struct ufs_hba *hba = shost_priv(shost); 5617 unsigned long completed_reqs, flags; 5618 u32 tr_doorbell; 5619 struct ufs_hw_queue *hwq; 5620 5621 if (hba->mcq_enabled) { 5622 hwq = &hba->uhq[queue_num]; 5623 5624 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5625 } 5626 5627 spin_lock_irqsave(&hba->outstanding_lock, flags); 5628 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5629 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5630 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5631 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5632 hba->outstanding_reqs); 5633 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5634 /* Do not complete polled requests from interrupt context. */ 5635 ufshcd_clear_polled(hba, &completed_reqs); 5636 } 5637 hba->outstanding_reqs &= ~completed_reqs; 5638 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5639 5640 if (completed_reqs) 5641 __ufshcd_transfer_req_compl(hba, completed_reqs); 5642 5643 return completed_reqs != 0; 5644 } 5645 5646 /** 5647 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5648 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5649 * to complete the pending transfers and free the resources associated with 5650 * the scsi command. 5651 * 5652 * @hba: per adapter instance 5653 * @force_compl: This flag is set to true when invoked 5654 * from ufshcd_host_reset_and_restore() in which case it requires special 5655 * handling because the host controller has been reset by ufshcd_hba_stop(). 5656 */ 5657 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5658 bool force_compl) 5659 { 5660 struct ufs_hw_queue *hwq; 5661 struct ufshcd_lrb *lrbp; 5662 struct scsi_cmnd *cmd; 5663 unsigned long flags; 5664 int tag; 5665 5666 for (tag = 0; tag < hba->nutrs; tag++) { 5667 lrbp = &hba->lrb[tag]; 5668 cmd = lrbp->cmd; 5669 if (!ufshcd_cmd_inflight(cmd) || 5670 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5671 continue; 5672 5673 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 5674 5675 if (force_compl) { 5676 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5677 /* 5678 * For those cmds of which the cqes are not present 5679 * in the cq, complete them explicitly. 5680 */ 5681 spin_lock_irqsave(&hwq->cq_lock, flags); 5682 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5683 set_host_byte(cmd, DID_REQUEUE); 5684 ufshcd_release_scsi_cmd(hba, lrbp); 5685 scsi_done(cmd); 5686 } 5687 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5688 } else { 5689 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5690 } 5691 } 5692 } 5693 5694 /** 5695 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5696 * @hba: per adapter instance 5697 * 5698 * Return: 5699 * IRQ_HANDLED - If interrupt is valid 5700 * IRQ_NONE - If invalid interrupt 5701 */ 5702 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5703 { 5704 /* Resetting interrupt aggregation counters first and reading the 5705 * DOOR_BELL afterward allows us to handle all the completed requests. 5706 * In order to prevent other interrupts starvation the DB is read once 5707 * after reset. The down side of this solution is the possibility of 5708 * false interrupt if device completes another request after resetting 5709 * aggregation and before reading the DB. 5710 */ 5711 if (ufshcd_is_intr_aggr_allowed(hba) && 5712 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5713 ufshcd_reset_intr_aggr(hba); 5714 5715 if (ufs_fail_completion(hba)) 5716 return IRQ_HANDLED; 5717 5718 /* 5719 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5720 * do not want polling to trigger spurious interrupt complaints. 5721 */ 5722 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5723 5724 return IRQ_HANDLED; 5725 } 5726 5727 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5728 { 5729 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5730 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5731 &ee_ctrl_mask); 5732 } 5733 5734 int ufshcd_write_ee_control(struct ufs_hba *hba) 5735 { 5736 int err; 5737 5738 mutex_lock(&hba->ee_ctrl_mutex); 5739 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5740 mutex_unlock(&hba->ee_ctrl_mutex); 5741 if (err) 5742 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5743 __func__, err); 5744 return err; 5745 } 5746 5747 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5748 const u16 *other_mask, u16 set, u16 clr) 5749 { 5750 u16 new_mask, ee_ctrl_mask; 5751 int err = 0; 5752 5753 mutex_lock(&hba->ee_ctrl_mutex); 5754 new_mask = (*mask & ~clr) | set; 5755 ee_ctrl_mask = new_mask | *other_mask; 5756 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5757 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5758 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5759 if (!err) { 5760 hba->ee_ctrl_mask = ee_ctrl_mask; 5761 *mask = new_mask; 5762 } 5763 mutex_unlock(&hba->ee_ctrl_mutex); 5764 return err; 5765 } 5766 5767 /** 5768 * ufshcd_disable_ee - disable exception event 5769 * @hba: per-adapter instance 5770 * @mask: exception event to disable 5771 * 5772 * Disables exception event in the device so that the EVENT_ALERT 5773 * bit is not set. 5774 * 5775 * Return: zero on success, non-zero error value on failure. 5776 */ 5777 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5778 { 5779 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5780 } 5781 5782 /** 5783 * ufshcd_enable_ee - enable exception event 5784 * @hba: per-adapter instance 5785 * @mask: exception event to enable 5786 * 5787 * Enable corresponding exception event in the device to allow 5788 * device to alert host in critical scenarios. 5789 * 5790 * Return: zero on success, non-zero error value on failure. 5791 */ 5792 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5793 { 5794 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5795 } 5796 5797 /** 5798 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5799 * @hba: per-adapter instance 5800 * 5801 * Allow device to manage background operations on its own. Enabling 5802 * this might lead to inconsistent latencies during normal data transfers 5803 * as the device is allowed to manage its own way of handling background 5804 * operations. 5805 * 5806 * Return: zero on success, non-zero on failure. 5807 */ 5808 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5809 { 5810 int err = 0; 5811 5812 if (hba->auto_bkops_enabled) 5813 goto out; 5814 5815 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5816 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5817 if (err) { 5818 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5819 __func__, err); 5820 goto out; 5821 } 5822 5823 hba->auto_bkops_enabled = true; 5824 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5825 5826 /* No need of URGENT_BKOPS exception from the device */ 5827 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5828 if (err) 5829 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5830 __func__, err); 5831 out: 5832 return err; 5833 } 5834 5835 /** 5836 * ufshcd_disable_auto_bkops - block device in doing background operations 5837 * @hba: per-adapter instance 5838 * 5839 * Disabling background operations improves command response latency but 5840 * has drawback of device moving into critical state where the device is 5841 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5842 * host is idle so that BKOPS are managed effectively without any negative 5843 * impacts. 5844 * 5845 * Return: zero on success, non-zero on failure. 5846 */ 5847 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5848 { 5849 int err = 0; 5850 5851 if (!hba->auto_bkops_enabled) 5852 goto out; 5853 5854 /* 5855 * If host assisted BKOPs is to be enabled, make sure 5856 * urgent bkops exception is allowed. 5857 */ 5858 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5859 if (err) { 5860 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5861 __func__, err); 5862 goto out; 5863 } 5864 5865 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5866 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5867 if (err) { 5868 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5869 __func__, err); 5870 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5871 goto out; 5872 } 5873 5874 hba->auto_bkops_enabled = false; 5875 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5876 hba->is_urgent_bkops_lvl_checked = false; 5877 out: 5878 return err; 5879 } 5880 5881 /** 5882 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5883 * @hba: per adapter instance 5884 * 5885 * After a device reset the device may toggle the BKOPS_EN flag 5886 * to default value. The s/w tracking variables should be updated 5887 * as well. This function would change the auto-bkops state based on 5888 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5889 */ 5890 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5891 { 5892 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5893 hba->auto_bkops_enabled = false; 5894 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5895 ufshcd_enable_auto_bkops(hba); 5896 } else { 5897 hba->auto_bkops_enabled = true; 5898 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5899 ufshcd_disable_auto_bkops(hba); 5900 } 5901 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5902 hba->is_urgent_bkops_lvl_checked = false; 5903 } 5904 5905 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5906 { 5907 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5908 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5909 } 5910 5911 /** 5912 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5913 * @hba: per-adapter instance 5914 * 5915 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5916 * flag in the device to permit background operations if the device 5917 * bkops_status is greater than or equal to the "hba->urgent_bkops_lvl", 5918 * disable otherwise. 5919 * 5920 * Return: 0 for success, non-zero in case of failure. 5921 * 5922 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5923 * to know whether auto bkops is enabled or disabled after this function 5924 * returns control to it. 5925 */ 5926 static int ufshcd_bkops_ctrl(struct ufs_hba *hba) 5927 { 5928 enum bkops_status status = hba->urgent_bkops_lvl; 5929 u32 curr_status = 0; 5930 int err; 5931 5932 err = ufshcd_get_bkops_status(hba, &curr_status); 5933 if (err) { 5934 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5935 __func__, err); 5936 goto out; 5937 } else if (curr_status > BKOPS_STATUS_MAX) { 5938 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5939 __func__, curr_status); 5940 err = -EINVAL; 5941 goto out; 5942 } 5943 5944 if (curr_status >= status) 5945 err = ufshcd_enable_auto_bkops(hba); 5946 else 5947 err = ufshcd_disable_auto_bkops(hba); 5948 out: 5949 return err; 5950 } 5951 5952 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5953 { 5954 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5955 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5956 } 5957 5958 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5959 { 5960 int err; 5961 u32 curr_status = 0; 5962 5963 if (hba->is_urgent_bkops_lvl_checked) 5964 goto enable_auto_bkops; 5965 5966 err = ufshcd_get_bkops_status(hba, &curr_status); 5967 if (err) { 5968 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5969 __func__, err); 5970 goto out; 5971 } 5972 5973 /* 5974 * We are seeing that some devices are raising the urgent bkops 5975 * exception events even when BKOPS status doesn't indicate performace 5976 * impacted or critical. Handle these device by determining their urgent 5977 * bkops status at runtime. 5978 */ 5979 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5980 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5981 __func__, curr_status); 5982 /* update the current status as the urgent bkops level */ 5983 hba->urgent_bkops_lvl = curr_status; 5984 hba->is_urgent_bkops_lvl_checked = true; 5985 } 5986 5987 enable_auto_bkops: 5988 err = ufshcd_enable_auto_bkops(hba); 5989 out: 5990 if (err < 0) 5991 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5992 __func__, err); 5993 } 5994 5995 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5996 { 5997 u32 value; 5998 5999 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6000 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 6001 return; 6002 6003 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 6004 6005 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 6006 6007 /* 6008 * A placeholder for the platform vendors to add whatever additional 6009 * steps required 6010 */ 6011 } 6012 6013 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 6014 { 6015 u8 index; 6016 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 6017 UPIU_QUERY_OPCODE_CLEAR_FLAG; 6018 6019 index = ufshcd_wb_get_query_index(hba); 6020 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 6021 } 6022 6023 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 6024 { 6025 int ret; 6026 6027 if (!ufshcd_is_wb_allowed(hba) || 6028 hba->dev_info.wb_enabled == enable) 6029 return 0; 6030 6031 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 6032 if (ret) { 6033 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 6034 __func__, enable ? "enabling" : "disabling", ret); 6035 return ret; 6036 } 6037 6038 hba->dev_info.wb_enabled = enable; 6039 dev_dbg(hba->dev, "%s: Write Booster %s\n", 6040 __func__, enable ? "enabled" : "disabled"); 6041 6042 return ret; 6043 } 6044 6045 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 6046 bool enable) 6047 { 6048 int ret; 6049 6050 ret = __ufshcd_wb_toggle(hba, enable, 6051 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 6052 if (ret) { 6053 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 6054 __func__, enable ? "enabling" : "disabling", ret); 6055 return; 6056 } 6057 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 6058 __func__, enable ? "enabled" : "disabled"); 6059 } 6060 6061 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 6062 { 6063 int ret; 6064 6065 if (!ufshcd_is_wb_allowed(hba) || 6066 hba->dev_info.wb_buf_flush_enabled == enable) 6067 return 0; 6068 6069 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 6070 if (ret) { 6071 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 6072 __func__, enable ? "enabling" : "disabling", ret); 6073 return ret; 6074 } 6075 6076 hba->dev_info.wb_buf_flush_enabled = enable; 6077 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 6078 __func__, enable ? "enabled" : "disabled"); 6079 6080 return ret; 6081 } 6082 6083 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 6084 u32 avail_buf) 6085 { 6086 u32 cur_buf; 6087 int ret; 6088 u8 index; 6089 6090 index = ufshcd_wb_get_query_index(hba); 6091 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6092 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 6093 index, 0, &cur_buf); 6094 if (ret) { 6095 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 6096 __func__, ret); 6097 return false; 6098 } 6099 6100 if (!cur_buf) { 6101 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 6102 cur_buf); 6103 return false; 6104 } 6105 /* Let it continue to flush when available buffer exceeds threshold */ 6106 return avail_buf < hba->vps->wb_flush_threshold; 6107 } 6108 6109 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 6110 { 6111 if (ufshcd_is_wb_buf_flush_allowed(hba)) 6112 ufshcd_wb_toggle_buf_flush(hba, false); 6113 6114 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 6115 ufshcd_wb_toggle(hba, false); 6116 hba->caps &= ~UFSHCD_CAP_WB_EN; 6117 6118 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 6119 } 6120 6121 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 6122 { 6123 u32 lifetime; 6124 int ret; 6125 u8 index; 6126 6127 index = ufshcd_wb_get_query_index(hba); 6128 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6129 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 6130 index, 0, &lifetime); 6131 if (ret) { 6132 dev_err(hba->dev, 6133 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 6134 __func__, ret); 6135 return false; 6136 } 6137 6138 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6139 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6140 __func__, lifetime); 6141 return false; 6142 } 6143 6144 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6145 __func__, lifetime); 6146 6147 return true; 6148 } 6149 6150 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6151 { 6152 int ret; 6153 u32 avail_buf; 6154 u8 index; 6155 6156 if (!ufshcd_is_wb_allowed(hba)) 6157 return false; 6158 6159 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6160 ufshcd_wb_force_disable(hba); 6161 return false; 6162 } 6163 6164 /* 6165 * The ufs device needs the vcc to be ON to flush. 6166 * With user-space reduction enabled, it's enough to enable flush 6167 * by checking only the available buffer. The threshold 6168 * defined here is > 90% full. 6169 * With user-space preserved enabled, the current-buffer 6170 * should be checked too because the wb buffer size can reduce 6171 * when disk tends to be full. This info is provided by current 6172 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6173 * keeping vcc on when current buffer is empty. 6174 */ 6175 index = ufshcd_wb_get_query_index(hba); 6176 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6177 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6178 index, 0, &avail_buf); 6179 if (ret) { 6180 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6181 __func__, ret); 6182 return false; 6183 } 6184 6185 if (!hba->dev_info.b_presrv_uspc_en) 6186 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6187 6188 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6189 } 6190 6191 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6192 { 6193 struct ufs_hba *hba = container_of(to_delayed_work(work), 6194 struct ufs_hba, 6195 rpm_dev_flush_recheck_work); 6196 /* 6197 * To prevent unnecessary VCC power drain after device finishes 6198 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6199 * after a certain delay to recheck the threshold by next runtime 6200 * suspend. 6201 */ 6202 ufshcd_rpm_get_sync(hba); 6203 ufshcd_rpm_put_sync(hba); 6204 } 6205 6206 /** 6207 * ufshcd_exception_event_handler - handle exceptions raised by device 6208 * @work: pointer to work data 6209 * 6210 * Read bExceptionEventStatus attribute from the device and handle the 6211 * exception event accordingly. 6212 */ 6213 static void ufshcd_exception_event_handler(struct work_struct *work) 6214 { 6215 struct ufs_hba *hba; 6216 int err; 6217 u32 status = 0; 6218 hba = container_of(work, struct ufs_hba, eeh_work); 6219 6220 err = ufshcd_get_ee_status(hba, &status); 6221 if (err) { 6222 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6223 __func__, err); 6224 return; 6225 } 6226 6227 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6228 6229 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6230 ufshcd_bkops_exception_event_handler(hba); 6231 6232 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6233 ufshcd_temp_exception_event_handler(hba, status); 6234 6235 ufs_debugfs_exception_event(hba, status); 6236 } 6237 6238 /* Complete requests that have door-bell cleared */ 6239 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6240 { 6241 if (hba->mcq_enabled) 6242 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6243 else 6244 ufshcd_transfer_req_compl(hba); 6245 6246 ufshcd_tmc_handler(hba); 6247 } 6248 6249 /** 6250 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6251 * to recover from the DL NAC errors or not. 6252 * @hba: per-adapter instance 6253 * 6254 * Return: true if error handling is required, false otherwise. 6255 */ 6256 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6257 { 6258 unsigned long flags; 6259 bool err_handling = true; 6260 6261 spin_lock_irqsave(hba->host->host_lock, flags); 6262 /* 6263 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6264 * device fatal error and/or DL NAC & REPLAY timeout errors. 6265 */ 6266 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6267 goto out; 6268 6269 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6270 ((hba->saved_err & UIC_ERROR) && 6271 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6272 goto out; 6273 6274 if ((hba->saved_err & UIC_ERROR) && 6275 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6276 int err; 6277 /* 6278 * wait for 50ms to see if we can get any other errors or not. 6279 */ 6280 spin_unlock_irqrestore(hba->host->host_lock, flags); 6281 msleep(50); 6282 spin_lock_irqsave(hba->host->host_lock, flags); 6283 6284 /* 6285 * now check if we have got any other severe errors other than 6286 * DL NAC error? 6287 */ 6288 if ((hba->saved_err & INT_FATAL_ERRORS) || 6289 ((hba->saved_err & UIC_ERROR) && 6290 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6291 goto out; 6292 6293 /* 6294 * As DL NAC is the only error received so far, send out NOP 6295 * command to confirm if link is still active or not. 6296 * - If we don't get any response then do error recovery. 6297 * - If we get response then clear the DL NAC error bit. 6298 */ 6299 6300 spin_unlock_irqrestore(hba->host->host_lock, flags); 6301 err = ufshcd_verify_dev_init(hba); 6302 spin_lock_irqsave(hba->host->host_lock, flags); 6303 6304 if (err) 6305 goto out; 6306 6307 /* Link seems to be alive hence ignore the DL NAC errors */ 6308 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6309 hba->saved_err &= ~UIC_ERROR; 6310 /* clear NAC error */ 6311 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6312 if (!hba->saved_uic_err) 6313 err_handling = false; 6314 } 6315 out: 6316 spin_unlock_irqrestore(hba->host->host_lock, flags); 6317 return err_handling; 6318 } 6319 6320 /* host lock must be held before calling this func */ 6321 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6322 { 6323 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6324 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6325 } 6326 6327 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6328 { 6329 lockdep_assert_held(hba->host->host_lock); 6330 6331 /* handle fatal errors only when link is not in error state */ 6332 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6333 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6334 ufshcd_is_saved_err_fatal(hba)) 6335 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6336 else 6337 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6338 queue_work(hba->eh_wq, &hba->eh_work); 6339 } 6340 } 6341 6342 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6343 { 6344 spin_lock_irq(hba->host->host_lock); 6345 hba->force_reset = true; 6346 ufshcd_schedule_eh_work(hba); 6347 spin_unlock_irq(hba->host->host_lock); 6348 } 6349 6350 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6351 { 6352 mutex_lock(&hba->wb_mutex); 6353 down_write(&hba->clk_scaling_lock); 6354 hba->clk_scaling.is_allowed = allow; 6355 up_write(&hba->clk_scaling_lock); 6356 mutex_unlock(&hba->wb_mutex); 6357 } 6358 6359 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6360 { 6361 if (suspend) { 6362 if (hba->clk_scaling.is_enabled) 6363 ufshcd_suspend_clkscaling(hba); 6364 ufshcd_clk_scaling_allow(hba, false); 6365 } else { 6366 ufshcd_clk_scaling_allow(hba, true); 6367 if (hba->clk_scaling.is_enabled) 6368 ufshcd_resume_clkscaling(hba); 6369 } 6370 } 6371 6372 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6373 { 6374 ufshcd_rpm_get_sync(hba); 6375 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6376 hba->is_sys_suspended) { 6377 enum ufs_pm_op pm_op; 6378 6379 /* 6380 * Don't assume anything of resume, if 6381 * resume fails, irq and clocks can be OFF, and powers 6382 * can be OFF or in LPM. 6383 */ 6384 ufshcd_setup_hba_vreg(hba, true); 6385 ufshcd_enable_irq(hba); 6386 ufshcd_setup_vreg(hba, true); 6387 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6388 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6389 ufshcd_hold(hba); 6390 if (!ufshcd_is_clkgating_allowed(hba)) 6391 ufshcd_setup_clocks(hba, true); 6392 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6393 ufshcd_vops_resume(hba, pm_op); 6394 } else { 6395 ufshcd_hold(hba); 6396 if (ufshcd_is_clkscaling_supported(hba) && 6397 hba->clk_scaling.is_enabled) 6398 ufshcd_suspend_clkscaling(hba); 6399 ufshcd_clk_scaling_allow(hba, false); 6400 } 6401 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6402 blk_mq_quiesce_tagset(&hba->host->tag_set); 6403 cancel_work_sync(&hba->eeh_work); 6404 } 6405 6406 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6407 { 6408 blk_mq_unquiesce_tagset(&hba->host->tag_set); 6409 ufshcd_release(hba); 6410 if (ufshcd_is_clkscaling_supported(hba)) 6411 ufshcd_clk_scaling_suspend(hba, false); 6412 ufshcd_rpm_put(hba); 6413 } 6414 6415 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6416 { 6417 return (!hba->is_powered || hba->shutting_down || 6418 !hba->ufs_device_wlun || 6419 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6420 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6421 ufshcd_is_link_broken(hba)))); 6422 } 6423 6424 #ifdef CONFIG_PM 6425 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6426 { 6427 struct Scsi_Host *shost = hba->host; 6428 struct scsi_device *sdev; 6429 struct request_queue *q; 6430 int ret; 6431 6432 hba->is_sys_suspended = false; 6433 /* 6434 * Set RPM status of wlun device to RPM_ACTIVE, 6435 * this also clears its runtime error. 6436 */ 6437 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6438 6439 /* hba device might have a runtime error otherwise */ 6440 if (ret) 6441 ret = pm_runtime_set_active(hba->dev); 6442 /* 6443 * If wlun device had runtime error, we also need to resume those 6444 * consumer scsi devices in case any of them has failed to be 6445 * resumed due to supplier runtime resume failure. This is to unblock 6446 * blk_queue_enter in case there are bios waiting inside it. 6447 */ 6448 if (!ret) { 6449 shost_for_each_device(sdev, shost) { 6450 q = sdev->request_queue; 6451 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6452 q->rpm_status == RPM_SUSPENDING)) 6453 pm_request_resume(q->dev); 6454 } 6455 } 6456 } 6457 #else 6458 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6459 { 6460 } 6461 #endif 6462 6463 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6464 { 6465 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6466 u32 mode; 6467 6468 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6469 6470 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6471 return true; 6472 6473 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6474 return true; 6475 6476 return false; 6477 } 6478 6479 static bool ufshcd_abort_one(struct request *rq, void *priv) 6480 { 6481 int *ret = priv; 6482 u32 tag = rq->tag; 6483 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6484 struct scsi_device *sdev = cmd->device; 6485 struct Scsi_Host *shost = sdev->host; 6486 struct ufs_hba *hba = shost_priv(shost); 6487 6488 *ret = ufshcd_try_to_abort_task(hba, tag); 6489 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6490 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6491 *ret ? "failed" : "succeeded"); 6492 6493 return *ret == 0; 6494 } 6495 6496 /** 6497 * ufshcd_abort_all - Abort all pending commands. 6498 * @hba: Host bus adapter pointer. 6499 * 6500 * Return: true if and only if the host controller needs to be reset. 6501 */ 6502 static bool ufshcd_abort_all(struct ufs_hba *hba) 6503 { 6504 int tag, ret = 0; 6505 6506 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6507 if (ret) 6508 goto out; 6509 6510 /* Clear pending task management requests */ 6511 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6512 ret = ufshcd_clear_tm_cmd(hba, tag); 6513 if (ret) 6514 goto out; 6515 } 6516 6517 out: 6518 /* Complete the requests that are cleared by s/w */ 6519 ufshcd_complete_requests(hba, false); 6520 6521 return ret != 0; 6522 } 6523 6524 /** 6525 * ufshcd_err_handler - handle UFS errors that require s/w attention 6526 * @work: pointer to work structure 6527 */ 6528 static void ufshcd_err_handler(struct work_struct *work) 6529 { 6530 int retries = MAX_ERR_HANDLER_RETRIES; 6531 struct ufs_hba *hba; 6532 unsigned long flags; 6533 bool needs_restore; 6534 bool needs_reset; 6535 int pmc_err; 6536 6537 hba = container_of(work, struct ufs_hba, eh_work); 6538 6539 dev_info(hba->dev, 6540 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6541 __func__, ufshcd_state_name[hba->ufshcd_state], 6542 hba->is_powered, hba->shutting_down, hba->saved_err, 6543 hba->saved_uic_err, hba->force_reset, 6544 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6545 6546 down(&hba->host_sem); 6547 spin_lock_irqsave(hba->host->host_lock, flags); 6548 if (ufshcd_err_handling_should_stop(hba)) { 6549 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6550 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6551 spin_unlock_irqrestore(hba->host->host_lock, flags); 6552 up(&hba->host_sem); 6553 return; 6554 } 6555 ufshcd_set_eh_in_progress(hba); 6556 spin_unlock_irqrestore(hba->host->host_lock, flags); 6557 ufshcd_err_handling_prepare(hba); 6558 /* Complete requests that have door-bell cleared by h/w */ 6559 ufshcd_complete_requests(hba, false); 6560 spin_lock_irqsave(hba->host->host_lock, flags); 6561 again: 6562 needs_restore = false; 6563 needs_reset = false; 6564 6565 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6566 hba->ufshcd_state = UFSHCD_STATE_RESET; 6567 /* 6568 * A full reset and restore might have happened after preparation 6569 * is finished, double check whether we should stop. 6570 */ 6571 if (ufshcd_err_handling_should_stop(hba)) 6572 goto skip_err_handling; 6573 6574 if ((hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) && 6575 !hba->force_reset) { 6576 bool ret; 6577 6578 spin_unlock_irqrestore(hba->host->host_lock, flags); 6579 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6580 ret = ufshcd_quirk_dl_nac_errors(hba); 6581 spin_lock_irqsave(hba->host->host_lock, flags); 6582 if (!ret && ufshcd_err_handling_should_stop(hba)) 6583 goto skip_err_handling; 6584 } 6585 6586 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6587 (hba->saved_uic_err && 6588 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6589 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6590 6591 spin_unlock_irqrestore(hba->host->host_lock, flags); 6592 ufshcd_print_host_state(hba); 6593 ufshcd_print_pwr_info(hba); 6594 ufshcd_print_evt_hist(hba); 6595 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6596 ufshcd_print_trs_all(hba, pr_prdt); 6597 spin_lock_irqsave(hba->host->host_lock, flags); 6598 } 6599 6600 /* 6601 * if host reset is required then skip clearing the pending 6602 * transfers forcefully because they will get cleared during 6603 * host reset and restore 6604 */ 6605 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6606 ufshcd_is_saved_err_fatal(hba) || 6607 ((hba->saved_err & UIC_ERROR) && 6608 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6609 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6610 needs_reset = true; 6611 goto do_reset; 6612 } 6613 6614 /* 6615 * If LINERESET was caught, UFS might have been put to PWM mode, 6616 * check if power mode restore is needed. 6617 */ 6618 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6619 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6620 if (!hba->saved_uic_err) 6621 hba->saved_err &= ~UIC_ERROR; 6622 spin_unlock_irqrestore(hba->host->host_lock, flags); 6623 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6624 needs_restore = true; 6625 spin_lock_irqsave(hba->host->host_lock, flags); 6626 if (!hba->saved_err && !needs_restore) 6627 goto skip_err_handling; 6628 } 6629 6630 hba->silence_err_logs = true; 6631 /* release lock as clear command might sleep */ 6632 spin_unlock_irqrestore(hba->host->host_lock, flags); 6633 6634 needs_reset = ufshcd_abort_all(hba); 6635 6636 spin_lock_irqsave(hba->host->host_lock, flags); 6637 hba->silence_err_logs = false; 6638 if (needs_reset) 6639 goto do_reset; 6640 6641 /* 6642 * After all reqs and tasks are cleared from doorbell, 6643 * now it is safe to retore power mode. 6644 */ 6645 if (needs_restore) { 6646 spin_unlock_irqrestore(hba->host->host_lock, flags); 6647 /* 6648 * Hold the scaling lock just in case dev cmds 6649 * are sent via bsg and/or sysfs. 6650 */ 6651 down_write(&hba->clk_scaling_lock); 6652 hba->force_pmc = true; 6653 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6654 if (pmc_err) { 6655 needs_reset = true; 6656 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6657 __func__, pmc_err); 6658 } 6659 hba->force_pmc = false; 6660 ufshcd_print_pwr_info(hba); 6661 up_write(&hba->clk_scaling_lock); 6662 spin_lock_irqsave(hba->host->host_lock, flags); 6663 } 6664 6665 do_reset: 6666 /* Fatal errors need reset */ 6667 if (needs_reset) { 6668 int err; 6669 6670 hba->force_reset = false; 6671 spin_unlock_irqrestore(hba->host->host_lock, flags); 6672 err = ufshcd_reset_and_restore(hba); 6673 if (err) 6674 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6675 __func__, err); 6676 else 6677 ufshcd_recover_pm_error(hba); 6678 spin_lock_irqsave(hba->host->host_lock, flags); 6679 } 6680 6681 skip_err_handling: 6682 if (!needs_reset) { 6683 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6684 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6685 if (hba->saved_err || hba->saved_uic_err) 6686 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6687 __func__, hba->saved_err, hba->saved_uic_err); 6688 } 6689 /* Exit in an operational state or dead */ 6690 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6691 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6692 if (--retries) 6693 goto again; 6694 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6695 } 6696 ufshcd_clear_eh_in_progress(hba); 6697 spin_unlock_irqrestore(hba->host->host_lock, flags); 6698 ufshcd_err_handling_unprepare(hba); 6699 up(&hba->host_sem); 6700 6701 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6702 ufshcd_state_name[hba->ufshcd_state]); 6703 } 6704 6705 /** 6706 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6707 * @hba: per-adapter instance 6708 * 6709 * Return: 6710 * IRQ_HANDLED - If interrupt is valid 6711 * IRQ_NONE - If invalid interrupt 6712 */ 6713 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6714 { 6715 u32 reg; 6716 irqreturn_t retval = IRQ_NONE; 6717 6718 /* PHY layer error */ 6719 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6720 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6721 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6722 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6723 /* 6724 * To know whether this error is fatal or not, DB timeout 6725 * must be checked but this error is handled separately. 6726 */ 6727 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6728 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6729 __func__); 6730 6731 /* Got a LINERESET indication. */ 6732 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6733 struct uic_command *cmd = NULL; 6734 6735 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6736 if (hba->uic_async_done && hba->active_uic_cmd) 6737 cmd = hba->active_uic_cmd; 6738 /* 6739 * Ignore the LINERESET during power mode change 6740 * operation via DME_SET command. 6741 */ 6742 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6743 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6744 } 6745 retval |= IRQ_HANDLED; 6746 } 6747 6748 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6749 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6750 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6751 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6752 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6753 6754 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6755 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6756 else if (hba->dev_quirks & 6757 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6758 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6759 hba->uic_error |= 6760 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6761 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6762 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6763 } 6764 retval |= IRQ_HANDLED; 6765 } 6766 6767 /* UIC NL/TL/DME errors needs software retry */ 6768 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6769 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6770 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6771 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6772 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6773 retval |= IRQ_HANDLED; 6774 } 6775 6776 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6777 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6778 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6779 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6780 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6781 retval |= IRQ_HANDLED; 6782 } 6783 6784 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6785 if ((reg & UIC_DME_ERROR) && 6786 (reg & UIC_DME_ERROR_CODE_MASK)) { 6787 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6788 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6789 retval |= IRQ_HANDLED; 6790 } 6791 6792 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6793 __func__, hba->uic_error); 6794 return retval; 6795 } 6796 6797 /** 6798 * ufshcd_check_errors - Check for errors that need s/w attention 6799 * @hba: per-adapter instance 6800 * @intr_status: interrupt status generated by the controller 6801 * 6802 * Return: 6803 * IRQ_HANDLED - If interrupt is valid 6804 * IRQ_NONE - If invalid interrupt 6805 */ 6806 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6807 { 6808 bool queue_eh_work = false; 6809 irqreturn_t retval = IRQ_NONE; 6810 6811 spin_lock(hba->host->host_lock); 6812 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6813 6814 if (hba->errors & INT_FATAL_ERRORS) { 6815 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6816 hba->errors); 6817 queue_eh_work = true; 6818 } 6819 6820 if (hba->errors & UIC_ERROR) { 6821 hba->uic_error = 0; 6822 retval = ufshcd_update_uic_error(hba); 6823 if (hba->uic_error) 6824 queue_eh_work = true; 6825 } 6826 6827 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6828 dev_err(hba->dev, 6829 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6830 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6831 "Enter" : "Exit", 6832 hba->errors, ufshcd_get_upmcrs(hba)); 6833 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6834 hba->errors); 6835 ufshcd_set_link_broken(hba); 6836 queue_eh_work = true; 6837 } 6838 6839 if (queue_eh_work) { 6840 /* 6841 * update the transfer error masks to sticky bits, let's do this 6842 * irrespective of current ufshcd_state. 6843 */ 6844 hba->saved_err |= hba->errors; 6845 hba->saved_uic_err |= hba->uic_error; 6846 6847 /* dump controller state before resetting */ 6848 if ((hba->saved_err & 6849 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6850 (hba->saved_uic_err && 6851 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6852 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6853 __func__, hba->saved_err, 6854 hba->saved_uic_err); 6855 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6856 "host_regs: "); 6857 ufshcd_print_pwr_info(hba); 6858 } 6859 ufshcd_schedule_eh_work(hba); 6860 retval |= IRQ_HANDLED; 6861 } 6862 /* 6863 * if (!queue_eh_work) - 6864 * Other errors are either non-fatal where host recovers 6865 * itself without s/w intervention or errors that will be 6866 * handled by the SCSI core layer. 6867 */ 6868 hba->errors = 0; 6869 hba->uic_error = 0; 6870 spin_unlock(hba->host->host_lock); 6871 return retval; 6872 } 6873 6874 /** 6875 * ufshcd_tmc_handler - handle task management function completion 6876 * @hba: per adapter instance 6877 * 6878 * Return: 6879 * IRQ_HANDLED - If interrupt is valid 6880 * IRQ_NONE - If invalid interrupt 6881 */ 6882 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6883 { 6884 unsigned long flags, pending, issued; 6885 irqreturn_t ret = IRQ_NONE; 6886 int tag; 6887 6888 spin_lock_irqsave(hba->host->host_lock, flags); 6889 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6890 issued = hba->outstanding_tasks & ~pending; 6891 for_each_set_bit(tag, &issued, hba->nutmrs) { 6892 struct request *req = hba->tmf_rqs[tag]; 6893 struct completion *c = req->end_io_data; 6894 6895 complete(c); 6896 ret = IRQ_HANDLED; 6897 } 6898 spin_unlock_irqrestore(hba->host->host_lock, flags); 6899 6900 return ret; 6901 } 6902 6903 /** 6904 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6905 * @hba: per adapter instance 6906 * 6907 * Return: IRQ_HANDLED if interrupt is handled. 6908 */ 6909 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6910 { 6911 struct ufs_hw_queue *hwq; 6912 unsigned long outstanding_cqs; 6913 unsigned int nr_queues; 6914 int i, ret; 6915 u32 events; 6916 6917 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6918 if (ret) 6919 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6920 6921 /* Exclude the poll queues */ 6922 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6923 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6924 hwq = &hba->uhq[i]; 6925 6926 events = ufshcd_mcq_read_cqis(hba, i); 6927 if (events) 6928 ufshcd_mcq_write_cqis(hba, events, i); 6929 6930 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6931 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6932 } 6933 6934 return IRQ_HANDLED; 6935 } 6936 6937 /** 6938 * ufshcd_sl_intr - Interrupt service routine 6939 * @hba: per adapter instance 6940 * @intr_status: contains interrupts generated by the controller 6941 * 6942 * Return: 6943 * IRQ_HANDLED - If interrupt is valid 6944 * IRQ_NONE - If invalid interrupt 6945 */ 6946 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6947 { 6948 irqreturn_t retval = IRQ_NONE; 6949 6950 if (intr_status & UFSHCD_UIC_MASK) 6951 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6952 6953 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6954 retval |= ufshcd_check_errors(hba, intr_status); 6955 6956 if (intr_status & UTP_TASK_REQ_COMPL) 6957 retval |= ufshcd_tmc_handler(hba); 6958 6959 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6960 retval |= ufshcd_transfer_req_compl(hba); 6961 6962 if (intr_status & MCQ_CQ_EVENT_STATUS) 6963 retval |= ufshcd_handle_mcq_cq_events(hba); 6964 6965 return retval; 6966 } 6967 6968 /** 6969 * ufshcd_intr - Main interrupt service routine 6970 * @irq: irq number 6971 * @__hba: pointer to adapter instance 6972 * 6973 * Return: 6974 * IRQ_HANDLED - If interrupt is valid 6975 * IRQ_NONE - If invalid interrupt 6976 */ 6977 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6978 { 6979 u32 intr_status, enabled_intr_status = 0; 6980 irqreturn_t retval = IRQ_NONE; 6981 struct ufs_hba *hba = __hba; 6982 int retries = hba->nutrs; 6983 6984 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6985 hba->ufs_stats.last_intr_status = intr_status; 6986 hba->ufs_stats.last_intr_ts = local_clock(); 6987 6988 /* 6989 * There could be max of hba->nutrs reqs in flight and in worst case 6990 * if the reqs get finished 1 by 1 after the interrupt status is 6991 * read, make sure we handle them by checking the interrupt status 6992 * again in a loop until we process all of the reqs before returning. 6993 */ 6994 while (intr_status && retries--) { 6995 enabled_intr_status = 6996 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6997 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6998 if (enabled_intr_status) 6999 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 7000 7001 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 7002 } 7003 7004 if (enabled_intr_status && retval == IRQ_NONE && 7005 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 7006 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 7007 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 7008 __func__, 7009 intr_status, 7010 hba->ufs_stats.last_intr_status, 7011 enabled_intr_status); 7012 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 7013 } 7014 7015 return retval; 7016 } 7017 7018 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 7019 { 7020 int err = 0; 7021 u32 mask = 1 << tag; 7022 7023 if (!test_bit(tag, &hba->outstanding_tasks)) 7024 goto out; 7025 7026 ufshcd_utmrl_clear(hba, tag); 7027 7028 /* poll for max. 1 sec to clear door bell register by h/w */ 7029 err = ufshcd_wait_for_register(hba, 7030 REG_UTP_TASK_REQ_DOOR_BELL, 7031 mask, 0, 1000, 1000); 7032 7033 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 7034 tag, err < 0 ? "failed" : "succeeded"); 7035 7036 out: 7037 return err; 7038 } 7039 7040 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 7041 struct utp_task_req_desc *treq, u8 tm_function) 7042 { 7043 struct request_queue *q = hba->tmf_queue; 7044 struct Scsi_Host *host = hba->host; 7045 DECLARE_COMPLETION_ONSTACK(wait); 7046 struct request *req; 7047 unsigned long flags; 7048 int task_tag, err; 7049 7050 /* 7051 * blk_mq_alloc_request() is used here only to get a free tag. 7052 */ 7053 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 7054 if (IS_ERR(req)) 7055 return PTR_ERR(req); 7056 7057 req->end_io_data = &wait; 7058 ufshcd_hold(hba); 7059 7060 spin_lock_irqsave(host->host_lock, flags); 7061 7062 task_tag = req->tag; 7063 hba->tmf_rqs[req->tag] = req; 7064 treq->upiu_req.req_header.task_tag = task_tag; 7065 7066 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 7067 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 7068 7069 __set_bit(task_tag, &hba->outstanding_tasks); 7070 7071 spin_unlock_irqrestore(host->host_lock, flags); 7072 7073 /* send command to the controller */ 7074 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 7075 7076 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 7077 7078 /* wait until the task management command is completed */ 7079 err = wait_for_completion_io_timeout(&wait, 7080 msecs_to_jiffies(TM_CMD_TIMEOUT)); 7081 if (!err) { 7082 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 7083 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 7084 __func__, tm_function); 7085 if (ufshcd_clear_tm_cmd(hba, task_tag)) 7086 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 7087 __func__, task_tag); 7088 err = -ETIMEDOUT; 7089 } else { 7090 err = 0; 7091 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 7092 7093 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 7094 } 7095 7096 spin_lock_irqsave(hba->host->host_lock, flags); 7097 hba->tmf_rqs[req->tag] = NULL; 7098 __clear_bit(task_tag, &hba->outstanding_tasks); 7099 spin_unlock_irqrestore(hba->host->host_lock, flags); 7100 7101 ufshcd_release(hba); 7102 blk_mq_free_request(req); 7103 7104 return err; 7105 } 7106 7107 /** 7108 * ufshcd_issue_tm_cmd - issues task management commands to controller 7109 * @hba: per adapter instance 7110 * @lun_id: LUN ID to which TM command is sent 7111 * @task_id: task ID to which the TM command is applicable 7112 * @tm_function: task management function opcode 7113 * @tm_response: task management service response return value 7114 * 7115 * Return: non-zero value on error, zero on success. 7116 */ 7117 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7118 u8 tm_function, u8 *tm_response) 7119 { 7120 struct utp_task_req_desc treq = { }; 7121 enum utp_ocs ocs_value; 7122 int err; 7123 7124 /* Configure task request descriptor */ 7125 treq.header.interrupt = 1; 7126 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7127 7128 /* Configure task request UPIU */ 7129 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7130 treq.upiu_req.req_header.lun = lun_id; 7131 treq.upiu_req.req_header.tm_function = tm_function; 7132 7133 /* 7134 * The host shall provide the same value for LUN field in the basic 7135 * header and for Input Parameter. 7136 */ 7137 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7138 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7139 7140 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7141 if (err == -ETIMEDOUT) 7142 return err; 7143 7144 ocs_value = treq.header.ocs & MASK_OCS; 7145 if (ocs_value != OCS_SUCCESS) 7146 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7147 __func__, ocs_value); 7148 else if (tm_response) 7149 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7150 MASK_TM_SERVICE_RESP; 7151 return err; 7152 } 7153 7154 /** 7155 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7156 * @hba: per-adapter instance 7157 * @req_upiu: upiu request 7158 * @rsp_upiu: upiu reply 7159 * @desc_buff: pointer to descriptor buffer, NULL if NA 7160 * @buff_len: descriptor size, 0 if NA 7161 * @cmd_type: specifies the type (NOP, Query...) 7162 * @desc_op: descriptor operation 7163 * 7164 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7165 * Therefore, it "rides" the device management infrastructure: uses its tag and 7166 * tasks work queues. 7167 * 7168 * Since there is only one available tag for device management commands, 7169 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7170 * 7171 * Return: 0 upon success; < 0 upon failure. 7172 */ 7173 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7174 struct utp_upiu_req *req_upiu, 7175 struct utp_upiu_req *rsp_upiu, 7176 u8 *desc_buff, int *buff_len, 7177 enum dev_cmd_type cmd_type, 7178 enum query_opcode desc_op) 7179 { 7180 const u32 tag = hba->reserved_slot; 7181 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7182 int err = 0; 7183 u8 upiu_flags; 7184 7185 /* Protects use of hba->reserved_slot. */ 7186 lockdep_assert_held(&hba->dev_cmd.lock); 7187 7188 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 7189 7190 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 7191 7192 /* update the task tag in the request upiu */ 7193 req_upiu->header.task_tag = tag; 7194 7195 /* just copy the upiu request as it is */ 7196 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7197 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7198 /* The Data Segment Area is optional depending upon the query 7199 * function value. for WRITE DESCRIPTOR, the data segment 7200 * follows right after the tsf. 7201 */ 7202 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7203 *buff_len = 0; 7204 } 7205 7206 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7207 7208 /* 7209 * ignore the returning value here - ufshcd_check_query_response is 7210 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7211 * read the response directly ignoring all errors. 7212 */ 7213 ufshcd_issue_dev_cmd(hba, lrbp, tag, QUERY_REQ_TIMEOUT); 7214 7215 /* just copy the upiu response as it is */ 7216 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7217 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7218 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7219 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7220 .data_segment_length); 7221 7222 if (*buff_len >= resp_len) { 7223 memcpy(desc_buff, descp, resp_len); 7224 *buff_len = resp_len; 7225 } else { 7226 dev_warn(hba->dev, 7227 "%s: rsp size %d is bigger than buffer size %d", 7228 __func__, resp_len, *buff_len); 7229 *buff_len = 0; 7230 err = -EINVAL; 7231 } 7232 } 7233 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7234 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7235 7236 return err; 7237 } 7238 7239 /** 7240 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7241 * @hba: per-adapter instance 7242 * @req_upiu: upiu request 7243 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7244 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7245 * @desc_buff: pointer to descriptor buffer, NULL if NA 7246 * @buff_len: descriptor size, 0 if NA 7247 * @desc_op: descriptor operation 7248 * 7249 * Supports UTP Transfer requests (nop and query), and UTP Task 7250 * Management requests. 7251 * It is up to the caller to fill the upiu conent properly, as it will 7252 * be copied without any further input validations. 7253 * 7254 * Return: 0 upon success; < 0 upon failure. 7255 */ 7256 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7257 struct utp_upiu_req *req_upiu, 7258 struct utp_upiu_req *rsp_upiu, 7259 enum upiu_request_transaction msgcode, 7260 u8 *desc_buff, int *buff_len, 7261 enum query_opcode desc_op) 7262 { 7263 int err; 7264 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7265 struct utp_task_req_desc treq = { }; 7266 enum utp_ocs ocs_value; 7267 u8 tm_f = req_upiu->header.tm_function; 7268 7269 switch (msgcode) { 7270 case UPIU_TRANSACTION_NOP_OUT: 7271 cmd_type = DEV_CMD_TYPE_NOP; 7272 fallthrough; 7273 case UPIU_TRANSACTION_QUERY_REQ: 7274 ufshcd_dev_man_lock(hba); 7275 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7276 desc_buff, buff_len, 7277 cmd_type, desc_op); 7278 ufshcd_dev_man_unlock(hba); 7279 7280 break; 7281 case UPIU_TRANSACTION_TASK_REQ: 7282 treq.header.interrupt = 1; 7283 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7284 7285 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7286 7287 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7288 if (err == -ETIMEDOUT) 7289 break; 7290 7291 ocs_value = treq.header.ocs & MASK_OCS; 7292 if (ocs_value != OCS_SUCCESS) { 7293 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7294 ocs_value); 7295 break; 7296 } 7297 7298 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7299 7300 break; 7301 default: 7302 err = -EINVAL; 7303 7304 break; 7305 } 7306 7307 return err; 7308 } 7309 7310 /** 7311 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7312 * @hba: per adapter instance 7313 * @req_upiu: upiu request 7314 * @rsp_upiu: upiu reply 7315 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7316 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7317 * @sg_cnt: The number of sg lists actually used 7318 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7319 * @dir: DMA direction 7320 * 7321 * Return: zero on success, non-zero on failure. 7322 */ 7323 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7324 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7325 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7326 enum dma_data_direction dir) 7327 { 7328 const u32 tag = hba->reserved_slot; 7329 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7330 int err = 0; 7331 int result; 7332 u8 upiu_flags; 7333 u8 *ehs_data; 7334 u16 ehs_len; 7335 int ehs = (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) ? 2 : 0; 7336 7337 /* Protects use of hba->reserved_slot. */ 7338 ufshcd_dev_man_lock(hba); 7339 7340 ufshcd_setup_dev_cmd(hba, lrbp, DEV_CMD_TYPE_RPMB, UFS_UPIU_RPMB_WLUN, tag); 7341 7342 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, ehs); 7343 7344 /* update the task tag */ 7345 req_upiu->header.task_tag = tag; 7346 7347 /* copy the UPIU(contains CDB) request as it is */ 7348 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7349 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7350 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7351 7352 if (dir != DMA_NONE && sg_list) 7353 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7354 7355 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7356 7357 err = ufshcd_issue_dev_cmd(hba, lrbp, tag, ADVANCED_RPMB_REQ_TIMEOUT); 7358 7359 if (!err) { 7360 /* Just copy the upiu response as it is */ 7361 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7362 /* Get the response UPIU result */ 7363 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7364 lrbp->ucd_rsp_ptr->header.status; 7365 7366 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7367 /* 7368 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7369 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7370 * Message is 02h 7371 */ 7372 if (ehs_len == 2 && rsp_ehs) { 7373 /* 7374 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7375 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7376 */ 7377 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7378 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7379 } 7380 } 7381 7382 ufshcd_dev_man_unlock(hba); 7383 7384 return err ? : result; 7385 } 7386 7387 /** 7388 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7389 * @cmd: SCSI command pointer 7390 * 7391 * Return: SUCCESS or FAILED. 7392 */ 7393 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7394 { 7395 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7396 struct Scsi_Host *host; 7397 struct ufs_hba *hba; 7398 struct ufs_hw_queue *hwq; 7399 struct ufshcd_lrb *lrbp; 7400 u32 pos, not_cleared_mask = 0; 7401 int err; 7402 u8 resp = 0xF, lun; 7403 7404 host = cmd->device->host; 7405 hba = shost_priv(host); 7406 7407 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7408 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7409 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7410 if (!err) 7411 err = resp; 7412 goto out; 7413 } 7414 7415 if (hba->mcq_enabled) { 7416 for (pos = 0; pos < hba->nutrs; pos++) { 7417 lrbp = &hba->lrb[pos]; 7418 if (ufshcd_cmd_inflight(lrbp->cmd) && 7419 lrbp->lun == lun) { 7420 ufshcd_clear_cmd(hba, pos); 7421 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7422 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7423 } 7424 } 7425 err = 0; 7426 goto out; 7427 } 7428 7429 /* clear the commands that were pending for corresponding LUN */ 7430 spin_lock_irqsave(&hba->outstanding_lock, flags); 7431 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7432 if (hba->lrb[pos].lun == lun) 7433 __set_bit(pos, &pending_reqs); 7434 hba->outstanding_reqs &= ~pending_reqs; 7435 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7436 7437 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7438 if (ufshcd_clear_cmd(hba, pos) < 0) { 7439 spin_lock_irqsave(&hba->outstanding_lock, flags); 7440 not_cleared = 1U << pos & 7441 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7442 hba->outstanding_reqs |= not_cleared; 7443 not_cleared_mask |= not_cleared; 7444 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7445 7446 dev_err(hba->dev, "%s: failed to clear request %d\n", 7447 __func__, pos); 7448 } 7449 } 7450 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7451 7452 out: 7453 hba->req_abort_count = 0; 7454 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7455 if (!err) { 7456 err = SUCCESS; 7457 } else { 7458 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7459 err = FAILED; 7460 } 7461 return err; 7462 } 7463 7464 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7465 { 7466 struct ufshcd_lrb *lrbp; 7467 int tag; 7468 7469 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7470 lrbp = &hba->lrb[tag]; 7471 lrbp->req_abort_skip = true; 7472 } 7473 } 7474 7475 /** 7476 * ufshcd_try_to_abort_task - abort a specific task 7477 * @hba: Pointer to adapter instance 7478 * @tag: Task tag/index to be aborted 7479 * 7480 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7481 * command, and in host controller by clearing the door-bell register. There can 7482 * be race between controller sending the command to the device while abort is 7483 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7484 * really issued and then try to abort it. 7485 * 7486 * Return: zero on success, non-zero on failure. 7487 */ 7488 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7489 { 7490 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7491 int err; 7492 int poll_cnt; 7493 u8 resp = 0xF; 7494 7495 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7496 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7497 UFS_QUERY_TASK, &resp); 7498 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7499 /* cmd pending in the device */ 7500 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7501 __func__, tag); 7502 break; 7503 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7504 /* 7505 * cmd not pending in the device, check if it is 7506 * in transition. 7507 */ 7508 dev_info( 7509 hba->dev, 7510 "%s: cmd with tag %d not pending in the device.\n", 7511 __func__, tag); 7512 if (!ufshcd_cmd_inflight(lrbp->cmd)) { 7513 dev_info(hba->dev, 7514 "%s: cmd with tag=%d completed.\n", 7515 __func__, tag); 7516 return 0; 7517 } 7518 usleep_range(100, 200); 7519 } else { 7520 dev_err(hba->dev, 7521 "%s: no response from device. tag = %d, err %d\n", 7522 __func__, tag, err); 7523 return err ? : resp; 7524 } 7525 } 7526 7527 if (!poll_cnt) 7528 return -EBUSY; 7529 7530 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7531 UFS_ABORT_TASK, &resp); 7532 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7533 if (!err) { 7534 err = resp; /* service response error */ 7535 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7536 __func__, tag, err); 7537 } 7538 return err; 7539 } 7540 7541 err = ufshcd_clear_cmd(hba, tag); 7542 if (err) 7543 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7544 __func__, tag, err); 7545 7546 return err; 7547 } 7548 7549 /** 7550 * ufshcd_abort - scsi host template eh_abort_handler callback 7551 * @cmd: SCSI command pointer 7552 * 7553 * Return: SUCCESS or FAILED. 7554 */ 7555 static int ufshcd_abort(struct scsi_cmnd *cmd) 7556 { 7557 struct Scsi_Host *host = cmd->device->host; 7558 struct ufs_hba *hba = shost_priv(host); 7559 int tag = scsi_cmd_to_rq(cmd)->tag; 7560 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7561 unsigned long flags; 7562 int err = FAILED; 7563 bool outstanding; 7564 u32 reg; 7565 7566 ufshcd_hold(hba); 7567 7568 if (!hba->mcq_enabled) { 7569 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7570 if (!test_bit(tag, &hba->outstanding_reqs)) { 7571 /* If command is already aborted/completed, return FAILED. */ 7572 dev_err(hba->dev, 7573 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7574 __func__, tag, hba->outstanding_reqs, reg); 7575 goto release; 7576 } 7577 } 7578 7579 /* Print Transfer Request of aborted task */ 7580 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7581 7582 /* 7583 * Print detailed info about aborted request. 7584 * As more than one request might get aborted at the same time, 7585 * print full information only for the first aborted request in order 7586 * to reduce repeated printouts. For other aborted requests only print 7587 * basic details. 7588 */ 7589 scsi_print_command(cmd); 7590 if (!hba->req_abort_count) { 7591 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7592 ufshcd_print_evt_hist(hba); 7593 ufshcd_print_host_state(hba); 7594 ufshcd_print_pwr_info(hba); 7595 ufshcd_print_tr(hba, tag, true); 7596 } else { 7597 ufshcd_print_tr(hba, tag, false); 7598 } 7599 hba->req_abort_count++; 7600 7601 if (!hba->mcq_enabled && !(reg & (1 << tag))) { 7602 /* only execute this code in single doorbell mode */ 7603 dev_err(hba->dev, 7604 "%s: cmd was completed, but without a notifying intr, tag = %d", 7605 __func__, tag); 7606 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7607 goto release; 7608 } 7609 7610 /* 7611 * Task abort to the device W-LUN is illegal. When this command 7612 * will fail, due to spec violation, scsi err handling next step 7613 * will be to send LU reset which, again, is a spec violation. 7614 * To avoid these unnecessary/illegal steps, first we clean up 7615 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7616 * then queue the eh_work and bail. 7617 */ 7618 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7619 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7620 7621 spin_lock_irqsave(host->host_lock, flags); 7622 hba->force_reset = true; 7623 ufshcd_schedule_eh_work(hba); 7624 spin_unlock_irqrestore(host->host_lock, flags); 7625 goto release; 7626 } 7627 7628 if (hba->mcq_enabled) { 7629 /* MCQ mode. Branch off to handle abort for mcq mode */ 7630 err = ufshcd_mcq_abort(cmd); 7631 goto release; 7632 } 7633 7634 /* Skip task abort in case previous aborts failed and report failure */ 7635 if (lrbp->req_abort_skip) { 7636 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7637 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7638 goto release; 7639 } 7640 7641 err = ufshcd_try_to_abort_task(hba, tag); 7642 if (err) { 7643 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7644 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7645 err = FAILED; 7646 goto release; 7647 } 7648 7649 /* 7650 * Clear the corresponding bit from outstanding_reqs since the command 7651 * has been aborted successfully. 7652 */ 7653 spin_lock_irqsave(&hba->outstanding_lock, flags); 7654 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7655 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7656 7657 if (outstanding) 7658 ufshcd_release_scsi_cmd(hba, lrbp); 7659 7660 err = SUCCESS; 7661 7662 release: 7663 /* Matches the ufshcd_hold() call at the start of this function. */ 7664 ufshcd_release(hba); 7665 return err; 7666 } 7667 7668 /** 7669 * ufshcd_process_probe_result - Process the ufshcd_probe_hba() result. 7670 * @hba: UFS host controller instance. 7671 * @probe_start: time when the ufshcd_probe_hba() call started. 7672 * @ret: ufshcd_probe_hba() return value. 7673 */ 7674 static void ufshcd_process_probe_result(struct ufs_hba *hba, 7675 ktime_t probe_start, int ret) 7676 { 7677 unsigned long flags; 7678 7679 spin_lock_irqsave(hba->host->host_lock, flags); 7680 if (ret) 7681 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7682 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 7683 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 7684 spin_unlock_irqrestore(hba->host->host_lock, flags); 7685 7686 trace_ufshcd_init(dev_name(hba->dev), ret, 7687 ktime_to_us(ktime_sub(ktime_get(), probe_start)), 7688 hba->curr_dev_pwr_mode, hba->uic_link_state); 7689 } 7690 7691 /** 7692 * ufshcd_host_reset_and_restore - reset and restore host controller 7693 * @hba: per-adapter instance 7694 * 7695 * Note that host controller reset may issue DME_RESET to 7696 * local and remote (device) Uni-Pro stack and the attributes 7697 * are reset to default state. 7698 * 7699 * Return: zero on success, non-zero on failure. 7700 */ 7701 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7702 { 7703 int err; 7704 7705 /* 7706 * Stop the host controller and complete the requests 7707 * cleared by h/w 7708 */ 7709 ufshcd_hba_stop(hba); 7710 hba->silence_err_logs = true; 7711 ufshcd_complete_requests(hba, true); 7712 hba->silence_err_logs = false; 7713 7714 /* scale up clocks to max frequency before full reinitialization */ 7715 ufshcd_scale_clks(hba, ULONG_MAX, true); 7716 7717 err = ufshcd_hba_enable(hba); 7718 7719 /* Establish the link again and restore the device */ 7720 if (!err) { 7721 ktime_t probe_start = ktime_get(); 7722 7723 err = ufshcd_device_init(hba, /*init_dev_params=*/false); 7724 if (!err) 7725 err = ufshcd_probe_hba(hba, false); 7726 ufshcd_process_probe_result(hba, probe_start, err); 7727 } 7728 7729 if (err) 7730 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7731 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7732 return err; 7733 } 7734 7735 /** 7736 * ufshcd_reset_and_restore - reset and re-initialize host/device 7737 * @hba: per-adapter instance 7738 * 7739 * Reset and recover device, host and re-establish link. This 7740 * is helpful to recover the communication in fatal error conditions. 7741 * 7742 * Return: zero on success, non-zero on failure. 7743 */ 7744 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7745 { 7746 u32 saved_err = 0; 7747 u32 saved_uic_err = 0; 7748 int err = 0; 7749 unsigned long flags; 7750 int retries = MAX_HOST_RESET_RETRIES; 7751 7752 spin_lock_irqsave(hba->host->host_lock, flags); 7753 do { 7754 /* 7755 * This is a fresh start, cache and clear saved error first, 7756 * in case new error generated during reset and restore. 7757 */ 7758 saved_err |= hba->saved_err; 7759 saved_uic_err |= hba->saved_uic_err; 7760 hba->saved_err = 0; 7761 hba->saved_uic_err = 0; 7762 hba->force_reset = false; 7763 hba->ufshcd_state = UFSHCD_STATE_RESET; 7764 spin_unlock_irqrestore(hba->host->host_lock, flags); 7765 7766 /* Reset the attached device */ 7767 ufshcd_device_reset(hba); 7768 7769 err = ufshcd_host_reset_and_restore(hba); 7770 7771 spin_lock_irqsave(hba->host->host_lock, flags); 7772 if (err) 7773 continue; 7774 /* Do not exit unless operational or dead */ 7775 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7776 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7777 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7778 err = -EAGAIN; 7779 } while (err && --retries); 7780 7781 /* 7782 * Inform scsi mid-layer that we did reset and allow to handle 7783 * Unit Attention properly. 7784 */ 7785 scsi_report_bus_reset(hba->host, 0); 7786 if (err) { 7787 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7788 hba->saved_err |= saved_err; 7789 hba->saved_uic_err |= saved_uic_err; 7790 } 7791 spin_unlock_irqrestore(hba->host->host_lock, flags); 7792 7793 return err; 7794 } 7795 7796 /** 7797 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7798 * @cmd: SCSI command pointer 7799 * 7800 * Return: SUCCESS or FAILED. 7801 */ 7802 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7803 { 7804 int err = SUCCESS; 7805 unsigned long flags; 7806 struct ufs_hba *hba; 7807 7808 hba = shost_priv(cmd->device->host); 7809 7810 /* 7811 * If runtime PM sent SSU and got a timeout, scsi_error_handler is 7812 * stuck in this function waiting for flush_work(&hba->eh_work). And 7813 * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do 7814 * ufshcd_link_recovery instead of eh_work to prevent deadlock. 7815 */ 7816 if (hba->pm_op_in_progress) { 7817 if (ufshcd_link_recovery(hba)) 7818 err = FAILED; 7819 7820 return err; 7821 } 7822 7823 spin_lock_irqsave(hba->host->host_lock, flags); 7824 hba->force_reset = true; 7825 ufshcd_schedule_eh_work(hba); 7826 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7827 spin_unlock_irqrestore(hba->host->host_lock, flags); 7828 7829 flush_work(&hba->eh_work); 7830 7831 spin_lock_irqsave(hba->host->host_lock, flags); 7832 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7833 err = FAILED; 7834 spin_unlock_irqrestore(hba->host->host_lock, flags); 7835 7836 return err; 7837 } 7838 7839 /** 7840 * ufshcd_get_max_icc_level - calculate the ICC level 7841 * @sup_curr_uA: max. current supported by the regulator 7842 * @start_scan: row at the desc table to start scan from 7843 * @buff: power descriptor buffer 7844 * 7845 * Return: calculated max ICC level for specific regulator. 7846 */ 7847 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7848 const char *buff) 7849 { 7850 int i; 7851 int curr_uA; 7852 u16 data; 7853 u16 unit; 7854 7855 for (i = start_scan; i >= 0; i--) { 7856 data = get_unaligned_be16(&buff[2 * i]); 7857 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7858 ATTR_ICC_LVL_UNIT_OFFSET; 7859 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7860 switch (unit) { 7861 case UFSHCD_NANO_AMP: 7862 curr_uA = curr_uA / 1000; 7863 break; 7864 case UFSHCD_MILI_AMP: 7865 curr_uA = curr_uA * 1000; 7866 break; 7867 case UFSHCD_AMP: 7868 curr_uA = curr_uA * 1000 * 1000; 7869 break; 7870 case UFSHCD_MICRO_AMP: 7871 default: 7872 break; 7873 } 7874 if (sup_curr_uA >= curr_uA) 7875 break; 7876 } 7877 if (i < 0) { 7878 i = 0; 7879 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7880 } 7881 7882 return (u32)i; 7883 } 7884 7885 /** 7886 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7887 * In case regulators are not initialized we'll return 0 7888 * @hba: per-adapter instance 7889 * @desc_buf: power descriptor buffer to extract ICC levels from. 7890 * 7891 * Return: calculated ICC level. 7892 */ 7893 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7894 const u8 *desc_buf) 7895 { 7896 u32 icc_level = 0; 7897 7898 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7899 !hba->vreg_info.vccq2) { 7900 /* 7901 * Using dev_dbg to avoid messages during runtime PM to avoid 7902 * never-ending cycles of messages written back to storage by 7903 * user space causing runtime resume, causing more messages and 7904 * so on. 7905 */ 7906 dev_dbg(hba->dev, 7907 "%s: Regulator capability was not set, actvIccLevel=%d", 7908 __func__, icc_level); 7909 goto out; 7910 } 7911 7912 if (hba->vreg_info.vcc->max_uA) 7913 icc_level = ufshcd_get_max_icc_level( 7914 hba->vreg_info.vcc->max_uA, 7915 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7916 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7917 7918 if (hba->vreg_info.vccq->max_uA) 7919 icc_level = ufshcd_get_max_icc_level( 7920 hba->vreg_info.vccq->max_uA, 7921 icc_level, 7922 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7923 7924 if (hba->vreg_info.vccq2->max_uA) 7925 icc_level = ufshcd_get_max_icc_level( 7926 hba->vreg_info.vccq2->max_uA, 7927 icc_level, 7928 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7929 out: 7930 return icc_level; 7931 } 7932 7933 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7934 { 7935 int ret; 7936 u8 *desc_buf; 7937 u32 icc_level; 7938 7939 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7940 if (!desc_buf) 7941 return; 7942 7943 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7944 desc_buf, QUERY_DESC_MAX_SIZE); 7945 if (ret) { 7946 dev_err(hba->dev, 7947 "%s: Failed reading power descriptor ret = %d", 7948 __func__, ret); 7949 goto out; 7950 } 7951 7952 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7953 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7954 7955 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7956 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7957 7958 if (ret) 7959 dev_err(hba->dev, 7960 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7961 __func__, icc_level, ret); 7962 7963 out: 7964 kfree(desc_buf); 7965 } 7966 7967 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7968 { 7969 struct Scsi_Host *shost = sdev->host; 7970 7971 scsi_autopm_get_device(sdev); 7972 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7973 if (sdev->rpm_autosuspend) 7974 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7975 shost->rpm_autosuspend_delay); 7976 scsi_autopm_put_device(sdev); 7977 } 7978 7979 /** 7980 * ufshcd_scsi_add_wlus - Adds required W-LUs 7981 * @hba: per-adapter instance 7982 * 7983 * UFS device specification requires the UFS devices to support 4 well known 7984 * logical units: 7985 * "REPORT_LUNS" (address: 01h) 7986 * "UFS Device" (address: 50h) 7987 * "RPMB" (address: 44h) 7988 * "BOOT" (address: 30h) 7989 * UFS device's power management needs to be controlled by "POWER CONDITION" 7990 * field of SSU (START STOP UNIT) command. But this "power condition" field 7991 * will take effect only when its sent to "UFS device" well known logical unit 7992 * hence we require the scsi_device instance to represent this logical unit in 7993 * order for the UFS host driver to send the SSU command for power management. 7994 * 7995 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 7996 * Block) LU so user space process can control this LU. User space may also 7997 * want to have access to BOOT LU. 7998 * 7999 * This function adds scsi device instances for each of all well known LUs 8000 * (except "REPORT LUNS" LU). 8001 * 8002 * Return: zero on success (all required W-LUs are added successfully), 8003 * non-zero error value on failure (if failed to add any of the required W-LU). 8004 */ 8005 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 8006 { 8007 int ret = 0; 8008 struct scsi_device *sdev_boot, *sdev_rpmb; 8009 8010 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 8011 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 8012 if (IS_ERR(hba->ufs_device_wlun)) { 8013 ret = PTR_ERR(hba->ufs_device_wlun); 8014 hba->ufs_device_wlun = NULL; 8015 goto out; 8016 } 8017 scsi_device_put(hba->ufs_device_wlun); 8018 8019 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 8020 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 8021 if (IS_ERR(sdev_rpmb)) { 8022 ret = PTR_ERR(sdev_rpmb); 8023 goto remove_ufs_device_wlun; 8024 } 8025 ufshcd_blk_pm_runtime_init(sdev_rpmb); 8026 scsi_device_put(sdev_rpmb); 8027 8028 sdev_boot = __scsi_add_device(hba->host, 0, 0, 8029 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 8030 if (IS_ERR(sdev_boot)) { 8031 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 8032 } else { 8033 ufshcd_blk_pm_runtime_init(sdev_boot); 8034 scsi_device_put(sdev_boot); 8035 } 8036 goto out; 8037 8038 remove_ufs_device_wlun: 8039 scsi_remove_device(hba->ufs_device_wlun); 8040 out: 8041 return ret; 8042 } 8043 8044 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 8045 { 8046 struct ufs_dev_info *dev_info = &hba->dev_info; 8047 u8 lun; 8048 u32 d_lu_wb_buf_alloc; 8049 u32 ext_ufs_feature; 8050 8051 if (!ufshcd_is_wb_allowed(hba)) 8052 return; 8053 8054 /* 8055 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 8056 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 8057 * enabled 8058 */ 8059 if (!(dev_info->wspecversion >= 0x310 || 8060 dev_info->wspecversion == 0x220 || 8061 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 8062 goto wb_disabled; 8063 8064 ext_ufs_feature = get_unaligned_be32(desc_buf + 8065 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8066 8067 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 8068 goto wb_disabled; 8069 8070 /* 8071 * WB may be supported but not configured while provisioning. The spec 8072 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 8073 * buffer configured. 8074 */ 8075 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 8076 8077 dev_info->b_presrv_uspc_en = 8078 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 8079 8080 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 8081 if (!get_unaligned_be32(desc_buf + 8082 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 8083 goto wb_disabled; 8084 } else { 8085 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 8086 d_lu_wb_buf_alloc = 0; 8087 ufshcd_read_unit_desc_param(hba, 8088 lun, 8089 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 8090 (u8 *)&d_lu_wb_buf_alloc, 8091 sizeof(d_lu_wb_buf_alloc)); 8092 if (d_lu_wb_buf_alloc) { 8093 dev_info->wb_dedicated_lu = lun; 8094 break; 8095 } 8096 } 8097 8098 if (!d_lu_wb_buf_alloc) 8099 goto wb_disabled; 8100 } 8101 8102 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8103 goto wb_disabled; 8104 8105 return; 8106 8107 wb_disabled: 8108 hba->caps &= ~UFSHCD_CAP_WB_EN; 8109 } 8110 8111 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8112 { 8113 struct ufs_dev_info *dev_info = &hba->dev_info; 8114 u32 ext_ufs_feature; 8115 u8 mask = 0; 8116 8117 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8118 return; 8119 8120 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8121 8122 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8123 mask |= MASK_EE_TOO_LOW_TEMP; 8124 8125 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8126 mask |= MASK_EE_TOO_HIGH_TEMP; 8127 8128 if (mask) { 8129 ufshcd_enable_ee(hba, mask); 8130 ufs_hwmon_probe(hba, mask); 8131 } 8132 } 8133 8134 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8135 { 8136 struct ufs_dev_info *dev_info = &hba->dev_info; 8137 u32 ext_ufs_feature; 8138 u32 ext_iid_en = 0; 8139 int err; 8140 8141 /* Only UFS-4.0 and above may support EXT_IID */ 8142 if (dev_info->wspecversion < 0x400) 8143 goto out; 8144 8145 ext_ufs_feature = get_unaligned_be32(desc_buf + 8146 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8147 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8148 goto out; 8149 8150 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8151 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8152 if (err) 8153 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8154 8155 out: 8156 dev_info->b_ext_iid_en = ext_iid_en; 8157 } 8158 8159 static void ufshcd_set_rtt(struct ufs_hba *hba) 8160 { 8161 struct ufs_dev_info *dev_info = &hba->dev_info; 8162 u32 rtt = 0; 8163 u32 dev_rtt = 0; 8164 int host_rtt_cap = hba->vops && hba->vops->max_num_rtt ? 8165 hba->vops->max_num_rtt : hba->nortt; 8166 8167 /* RTT override makes sense only for UFS-4.0 and above */ 8168 if (dev_info->wspecversion < 0x400) 8169 return; 8170 8171 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8172 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &dev_rtt)) { 8173 dev_err(hba->dev, "failed reading bMaxNumOfRTT\n"); 8174 return; 8175 } 8176 8177 /* do not override if it was already written */ 8178 if (dev_rtt != DEFAULT_MAX_NUM_RTT) 8179 return; 8180 8181 rtt = min_t(int, dev_info->rtt_cap, host_rtt_cap); 8182 8183 if (rtt == dev_rtt) 8184 return; 8185 8186 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8187 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &rtt)) 8188 dev_err(hba->dev, "failed writing bMaxNumOfRTT\n"); 8189 } 8190 8191 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8192 const struct ufs_dev_quirk *fixups) 8193 { 8194 const struct ufs_dev_quirk *f; 8195 struct ufs_dev_info *dev_info = &hba->dev_info; 8196 8197 if (!fixups) 8198 return; 8199 8200 for (f = fixups; f->quirk; f++) { 8201 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8202 f->wmanufacturerid == UFS_ANY_VENDOR) && 8203 ((dev_info->model && 8204 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8205 !strcmp(f->model, UFS_ANY_MODEL))) 8206 hba->dev_quirks |= f->quirk; 8207 } 8208 } 8209 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8210 8211 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8212 { 8213 /* fix by general quirk table */ 8214 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8215 8216 /* allow vendors to fix quirks */ 8217 ufshcd_vops_fixup_dev_quirks(hba); 8218 } 8219 8220 static void ufshcd_update_rtc(struct ufs_hba *hba) 8221 { 8222 struct timespec64 ts64; 8223 int err; 8224 u32 val; 8225 8226 ktime_get_real_ts64(&ts64); 8227 8228 if (ts64.tv_sec < hba->dev_info.rtc_time_baseline) { 8229 dev_warn_once(hba->dev, "%s: Current time precedes previous setting!\n", __func__); 8230 return; 8231 } 8232 8233 /* 8234 * The Absolute RTC mode has a 136-year limit, spanning from 2010 to 2146. If a time beyond 8235 * 2146 is required, it is recommended to choose the relative RTC mode. 8236 */ 8237 val = ts64.tv_sec - hba->dev_info.rtc_time_baseline; 8238 8239 /* Skip update RTC if RPM state is not RPM_ACTIVE */ 8240 if (ufshcd_rpm_get_if_active(hba) <= 0) 8241 return; 8242 8243 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_SECONDS_PASSED, 8244 0, 0, &val); 8245 ufshcd_rpm_put(hba); 8246 8247 if (err) 8248 dev_err(hba->dev, "%s: Failed to update rtc %d\n", __func__, err); 8249 else if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 8250 hba->dev_info.rtc_time_baseline = ts64.tv_sec; 8251 } 8252 8253 static void ufshcd_rtc_work(struct work_struct *work) 8254 { 8255 struct ufs_hba *hba; 8256 8257 hba = container_of(to_delayed_work(work), struct ufs_hba, ufs_rtc_update_work); 8258 8259 /* Update RTC only when there are no requests in progress and UFSHCI is operational */ 8260 if (!ufshcd_is_ufs_dev_busy(hba) && hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) 8261 ufshcd_update_rtc(hba); 8262 8263 if (ufshcd_is_ufs_dev_active(hba) && hba->dev_info.rtc_update_period) 8264 schedule_delayed_work(&hba->ufs_rtc_update_work, 8265 msecs_to_jiffies(hba->dev_info.rtc_update_period)); 8266 } 8267 8268 static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf) 8269 { 8270 u16 periodic_rtc_update = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_FRQ_RTC]); 8271 struct ufs_dev_info *dev_info = &hba->dev_info; 8272 8273 if (periodic_rtc_update & UFS_RTC_TIME_BASELINE) { 8274 dev_info->rtc_type = UFS_RTC_ABSOLUTE; 8275 8276 /* 8277 * The concept of measuring time in Linux as the number of seconds elapsed since 8278 * 00:00:00 UTC on January 1, 1970, and UFS ABS RTC is elapsed from January 1st 8279 * 2010 00:00, here we need to adjust ABS baseline. 8280 */ 8281 dev_info->rtc_time_baseline = mktime64(2010, 1, 1, 0, 0, 0) - 8282 mktime64(1970, 1, 1, 0, 0, 0); 8283 } else { 8284 dev_info->rtc_type = UFS_RTC_RELATIVE; 8285 dev_info->rtc_time_baseline = 0; 8286 } 8287 8288 /* 8289 * We ignore TIME_PERIOD defined in wPeriodicRTCUpdate because Spec does not clearly state 8290 * how to calculate the specific update period for each time unit. And we disable periodic 8291 * RTC update work, let user configure by sysfs node according to specific circumstance. 8292 */ 8293 dev_info->rtc_update_period = 0; 8294 } 8295 8296 static int ufs_get_device_desc(struct ufs_hba *hba) 8297 { 8298 int err; 8299 u8 model_index; 8300 u8 *desc_buf; 8301 struct ufs_dev_info *dev_info = &hba->dev_info; 8302 8303 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8304 if (!desc_buf) { 8305 err = -ENOMEM; 8306 goto out; 8307 } 8308 8309 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8310 QUERY_DESC_MAX_SIZE); 8311 if (err) { 8312 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8313 __func__, err); 8314 goto out; 8315 } 8316 8317 /* 8318 * getting vendor (manufacturerID) and Bank Index in big endian 8319 * format 8320 */ 8321 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8322 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8323 8324 /* getting Specification Version in big endian format */ 8325 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8326 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8327 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8328 8329 dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP]; 8330 8331 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8332 8333 err = ufshcd_read_string_desc(hba, model_index, 8334 &dev_info->model, SD_ASCII_STD); 8335 if (err < 0) { 8336 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8337 __func__, err); 8338 goto out; 8339 } 8340 8341 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8342 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8343 8344 ufs_fixup_device_setup(hba); 8345 8346 ufshcd_wb_probe(hba, desc_buf); 8347 8348 ufshcd_temp_notif_probe(hba, desc_buf); 8349 8350 ufs_init_rtc(hba, desc_buf); 8351 8352 if (hba->ext_iid_sup) 8353 ufshcd_ext_iid_probe(hba, desc_buf); 8354 8355 /* 8356 * ufshcd_read_string_desc returns size of the string 8357 * reset the error value 8358 */ 8359 err = 0; 8360 8361 out: 8362 kfree(desc_buf); 8363 return err; 8364 } 8365 8366 static void ufs_put_device_desc(struct ufs_hba *hba) 8367 { 8368 struct ufs_dev_info *dev_info = &hba->dev_info; 8369 8370 kfree(dev_info->model); 8371 dev_info->model = NULL; 8372 } 8373 8374 /** 8375 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8376 * less than device PA_TACTIVATE time. 8377 * @hba: per-adapter instance 8378 * 8379 * Some UFS devices require host PA_TACTIVATE to be lower than device 8380 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8381 * for such devices. 8382 * 8383 * Return: zero on success, non-zero error value on failure. 8384 */ 8385 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8386 { 8387 int ret = 0; 8388 u32 granularity, peer_granularity; 8389 u32 pa_tactivate, peer_pa_tactivate; 8390 u32 pa_tactivate_us, peer_pa_tactivate_us; 8391 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8392 8393 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8394 &granularity); 8395 if (ret) 8396 goto out; 8397 8398 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8399 &peer_granularity); 8400 if (ret) 8401 goto out; 8402 8403 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8404 (granularity > PA_GRANULARITY_MAX_VAL)) { 8405 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8406 __func__, granularity); 8407 return -EINVAL; 8408 } 8409 8410 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8411 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8412 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8413 __func__, peer_granularity); 8414 return -EINVAL; 8415 } 8416 8417 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8418 if (ret) 8419 goto out; 8420 8421 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8422 &peer_pa_tactivate); 8423 if (ret) 8424 goto out; 8425 8426 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8427 peer_pa_tactivate_us = peer_pa_tactivate * 8428 gran_to_us_table[peer_granularity - 1]; 8429 8430 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8431 u32 new_peer_pa_tactivate; 8432 8433 new_peer_pa_tactivate = pa_tactivate_us / 8434 gran_to_us_table[peer_granularity - 1]; 8435 new_peer_pa_tactivate++; 8436 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8437 new_peer_pa_tactivate); 8438 } 8439 8440 out: 8441 return ret; 8442 } 8443 8444 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8445 { 8446 ufshcd_vops_apply_dev_quirks(hba); 8447 8448 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8449 /* set 1ms timeout for PA_TACTIVATE */ 8450 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8451 8452 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8453 ufshcd_quirk_tune_host_pa_tactivate(hba); 8454 } 8455 8456 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8457 { 8458 hba->ufs_stats.hibern8_exit_cnt = 0; 8459 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8460 hba->req_abort_count = 0; 8461 } 8462 8463 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8464 { 8465 int err; 8466 u8 *desc_buf; 8467 8468 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8469 if (!desc_buf) { 8470 err = -ENOMEM; 8471 goto out; 8472 } 8473 8474 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8475 desc_buf, QUERY_DESC_MAX_SIZE); 8476 if (err) { 8477 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8478 __func__, err); 8479 goto out; 8480 } 8481 8482 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8483 hba->dev_info.max_lu_supported = 32; 8484 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8485 hba->dev_info.max_lu_supported = 8; 8486 8487 out: 8488 kfree(desc_buf); 8489 return err; 8490 } 8491 8492 struct ufs_ref_clk { 8493 unsigned long freq_hz; 8494 enum ufs_ref_clk_freq val; 8495 }; 8496 8497 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8498 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8499 {26000000, REF_CLK_FREQ_26_MHZ}, 8500 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8501 {52000000, REF_CLK_FREQ_52_MHZ}, 8502 {0, REF_CLK_FREQ_INVAL}, 8503 }; 8504 8505 static enum ufs_ref_clk_freq 8506 ufs_get_bref_clk_from_hz(unsigned long freq) 8507 { 8508 int i; 8509 8510 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8511 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8512 return ufs_ref_clk_freqs[i].val; 8513 8514 return REF_CLK_FREQ_INVAL; 8515 } 8516 8517 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8518 { 8519 unsigned long freq; 8520 8521 freq = clk_get_rate(refclk); 8522 8523 hba->dev_ref_clk_freq = 8524 ufs_get_bref_clk_from_hz(freq); 8525 8526 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8527 dev_err(hba->dev, 8528 "invalid ref_clk setting = %ld\n", freq); 8529 } 8530 8531 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8532 { 8533 int err; 8534 u32 ref_clk; 8535 u32 freq = hba->dev_ref_clk_freq; 8536 8537 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8538 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8539 8540 if (err) { 8541 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8542 err); 8543 goto out; 8544 } 8545 8546 if (ref_clk == freq) 8547 goto out; /* nothing to update */ 8548 8549 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8550 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8551 8552 if (err) { 8553 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8554 ufs_ref_clk_freqs[freq].freq_hz); 8555 goto out; 8556 } 8557 8558 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8559 ufs_ref_clk_freqs[freq].freq_hz); 8560 8561 out: 8562 return err; 8563 } 8564 8565 static int ufshcd_device_params_init(struct ufs_hba *hba) 8566 { 8567 bool flag; 8568 int ret; 8569 8570 /* Init UFS geometry descriptor related parameters */ 8571 ret = ufshcd_device_geo_params_init(hba); 8572 if (ret) 8573 goto out; 8574 8575 /* Check and apply UFS device quirks */ 8576 ret = ufs_get_device_desc(hba); 8577 if (ret) { 8578 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8579 __func__, ret); 8580 goto out; 8581 } 8582 8583 ufshcd_set_rtt(hba); 8584 8585 ufshcd_get_ref_clk_gating_wait(hba); 8586 8587 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8588 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8589 hba->dev_info.f_power_on_wp_en = flag; 8590 8591 /* Probe maximum power mode co-supported by both UFS host and device */ 8592 if (ufshcd_get_max_pwr_mode(hba)) 8593 dev_err(hba->dev, 8594 "%s: Failed getting max supported power mode\n", 8595 __func__); 8596 out: 8597 return ret; 8598 } 8599 8600 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8601 { 8602 int err; 8603 struct ufs_query_req *request = NULL; 8604 struct ufs_query_res *response = NULL; 8605 struct ufs_dev_info *dev_info = &hba->dev_info; 8606 struct utp_upiu_query_v4_0 *upiu_data; 8607 8608 if (dev_info->wspecversion < 0x400) 8609 return; 8610 8611 ufshcd_dev_man_lock(hba); 8612 8613 ufshcd_init_query(hba, &request, &response, 8614 UPIU_QUERY_OPCODE_WRITE_ATTR, 8615 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8616 8617 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8618 8619 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8620 8621 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8622 8623 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8624 8625 if (err) 8626 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8627 __func__, err); 8628 8629 ufshcd_dev_man_unlock(hba); 8630 } 8631 8632 /** 8633 * ufshcd_add_lus - probe and add UFS logical units 8634 * @hba: per-adapter instance 8635 * 8636 * Return: 0 upon success; < 0 upon failure. 8637 */ 8638 static int ufshcd_add_lus(struct ufs_hba *hba) 8639 { 8640 int ret; 8641 8642 /* Add required well known logical units to scsi mid layer */ 8643 ret = ufshcd_scsi_add_wlus(hba); 8644 if (ret) 8645 goto out; 8646 8647 /* Initialize devfreq after UFS device is detected */ 8648 if (ufshcd_is_clkscaling_supported(hba)) { 8649 memcpy(&hba->clk_scaling.saved_pwr_info, 8650 &hba->pwr_info, 8651 sizeof(struct ufs_pa_layer_attr)); 8652 hba->clk_scaling.is_allowed = true; 8653 8654 ret = ufshcd_devfreq_init(hba); 8655 if (ret) 8656 goto out; 8657 8658 hba->clk_scaling.is_enabled = true; 8659 ufshcd_init_clk_scaling_sysfs(hba); 8660 } 8661 8662 /* 8663 * The RTC update code accesses the hba->ufs_device_wlun->sdev_gendev 8664 * pointer and hence must only be started after the WLUN pointer has 8665 * been initialized by ufshcd_scsi_add_wlus(). 8666 */ 8667 schedule_delayed_work(&hba->ufs_rtc_update_work, 8668 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 8669 8670 ufs_bsg_probe(hba); 8671 scsi_scan_host(hba->host); 8672 8673 out: 8674 return ret; 8675 } 8676 8677 /* SDB - Single Doorbell */ 8678 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8679 { 8680 size_t ucdl_size, utrdl_size; 8681 8682 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8683 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8684 hba->ucdl_dma_addr); 8685 8686 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8687 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8688 hba->utrdl_dma_addr); 8689 8690 devm_kfree(hba->dev, hba->lrb); 8691 } 8692 8693 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8694 { 8695 int ret; 8696 int old_nutrs = hba->nutrs; 8697 8698 ret = ufshcd_mcq_decide_queue_depth(hba); 8699 if (ret < 0) 8700 return ret; 8701 8702 hba->nutrs = ret; 8703 ret = ufshcd_mcq_init(hba); 8704 if (ret) 8705 goto err; 8706 8707 /* 8708 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8709 * Number of supported tags in MCQ mode may be larger than SDB mode. 8710 */ 8711 if (hba->nutrs != old_nutrs) { 8712 ufshcd_release_sdb_queue(hba, old_nutrs); 8713 ret = ufshcd_memory_alloc(hba); 8714 if (ret) 8715 goto err; 8716 ufshcd_host_memory_configure(hba); 8717 } 8718 8719 ret = ufshcd_mcq_memory_alloc(hba); 8720 if (ret) 8721 goto err; 8722 8723 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8724 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8725 8726 return 0; 8727 err: 8728 hba->nutrs = old_nutrs; 8729 return ret; 8730 } 8731 8732 static void ufshcd_config_mcq(struct ufs_hba *hba) 8733 { 8734 int ret; 8735 u32 intrs; 8736 8737 ret = ufshcd_mcq_vops_config_esi(hba); 8738 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8739 8740 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8741 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8742 intrs &= ~MCQ_CQ_EVENT_STATUS; 8743 ufshcd_enable_intr(hba, intrs); 8744 ufshcd_mcq_make_queues_operational(hba); 8745 ufshcd_mcq_config_mac(hba, hba->nutrs); 8746 8747 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8748 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8749 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8750 hba->nutrs); 8751 } 8752 8753 static int ufshcd_post_device_init(struct ufs_hba *hba) 8754 { 8755 int ret; 8756 8757 ufshcd_tune_unipro_params(hba); 8758 8759 /* UFS device is also active now */ 8760 ufshcd_set_ufs_dev_active(hba); 8761 ufshcd_force_reset_auto_bkops(hba); 8762 8763 ufshcd_set_timestamp_attr(hba); 8764 8765 if (!hba->max_pwr_info.is_valid) 8766 return 0; 8767 8768 /* 8769 * Set the right value to bRefClkFreq before attempting to 8770 * switch to HS gears. 8771 */ 8772 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8773 ufshcd_set_dev_ref_clk(hba); 8774 /* Gear up to HS gear. */ 8775 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8776 if (ret) { 8777 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8778 __func__, ret); 8779 return ret; 8780 } 8781 8782 return 0; 8783 } 8784 8785 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8786 { 8787 int ret; 8788 8789 WARN_ON_ONCE(!hba->scsi_host_added); 8790 8791 hba->ufshcd_state = UFSHCD_STATE_RESET; 8792 8793 ret = ufshcd_link_startup(hba); 8794 if (ret) 8795 return ret; 8796 8797 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8798 return ret; 8799 8800 /* Debug counters initialization */ 8801 ufshcd_clear_dbg_ufs_stats(hba); 8802 8803 /* UniPro link is active now */ 8804 ufshcd_set_link_active(hba); 8805 8806 /* Reconfigure MCQ upon reset */ 8807 if (hba->mcq_enabled && !init_dev_params) { 8808 ufshcd_config_mcq(hba); 8809 ufshcd_mcq_enable(hba); 8810 } 8811 8812 /* Verify device initialization by sending NOP OUT UPIU */ 8813 ret = ufshcd_verify_dev_init(hba); 8814 if (ret) 8815 return ret; 8816 8817 /* Initiate UFS initialization, and waiting until completion */ 8818 ret = ufshcd_complete_dev_init(hba); 8819 if (ret) 8820 return ret; 8821 8822 /* 8823 * Initialize UFS device parameters used by driver, these 8824 * parameters are associated with UFS descriptors. 8825 */ 8826 if (init_dev_params) { 8827 ret = ufshcd_device_params_init(hba); 8828 if (ret) 8829 return ret; 8830 if (is_mcq_supported(hba) && 8831 hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) { 8832 ufshcd_config_mcq(hba); 8833 ufshcd_mcq_enable(hba); 8834 } 8835 } 8836 8837 return ufshcd_post_device_init(hba); 8838 } 8839 8840 /** 8841 * ufshcd_probe_hba - probe hba to detect device and initialize it 8842 * @hba: per-adapter instance 8843 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8844 * 8845 * Execute link-startup and verify device initialization 8846 * 8847 * Return: 0 upon success; < 0 upon failure. 8848 */ 8849 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8850 { 8851 int ret; 8852 8853 if (!hba->pm_op_in_progress && 8854 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8855 /* Reset the device and controller before doing reinit */ 8856 ufshcd_device_reset(hba); 8857 ufs_put_device_desc(hba); 8858 ufshcd_hba_stop(hba); 8859 ufshcd_vops_reinit_notify(hba); 8860 ret = ufshcd_hba_enable(hba); 8861 if (ret) { 8862 dev_err(hba->dev, "Host controller enable failed\n"); 8863 ufshcd_print_evt_hist(hba); 8864 ufshcd_print_host_state(hba); 8865 return ret; 8866 } 8867 8868 /* Reinit the device */ 8869 ret = ufshcd_device_init(hba, init_dev_params); 8870 if (ret) 8871 return ret; 8872 } 8873 8874 ufshcd_print_pwr_info(hba); 8875 8876 /* 8877 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8878 * and for removable UFS card as well, hence always set the parameter. 8879 * Note: Error handler may issue the device reset hence resetting 8880 * bActiveICCLevel as well so it is always safe to set this here. 8881 */ 8882 ufshcd_set_active_icc_lvl(hba); 8883 8884 /* Enable UFS Write Booster if supported */ 8885 ufshcd_configure_wb(hba); 8886 8887 if (hba->ee_usr_mask) 8888 ufshcd_write_ee_control(hba); 8889 ufshcd_configure_auto_hibern8(hba); 8890 8891 return 0; 8892 } 8893 8894 /** 8895 * ufshcd_async_scan - asynchronous execution for probing hba 8896 * @data: data pointer to pass to this function 8897 * @cookie: cookie data 8898 */ 8899 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8900 { 8901 struct ufs_hba *hba = (struct ufs_hba *)data; 8902 ktime_t probe_start; 8903 int ret; 8904 8905 down(&hba->host_sem); 8906 /* Initialize hba, detect and initialize UFS device */ 8907 probe_start = ktime_get(); 8908 ret = ufshcd_probe_hba(hba, true); 8909 ufshcd_process_probe_result(hba, probe_start, ret); 8910 up(&hba->host_sem); 8911 if (ret) 8912 goto out; 8913 8914 /* Probe and add UFS logical units */ 8915 ret = ufshcd_add_lus(hba); 8916 8917 out: 8918 pm_runtime_put_sync(hba->dev); 8919 8920 if (ret) 8921 dev_err(hba->dev, "%s failed: %d\n", __func__, ret); 8922 } 8923 8924 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8925 { 8926 struct ufs_hba *hba = shost_priv(scmd->device->host); 8927 8928 if (!hba->system_suspending) { 8929 /* Activate the error handler in the SCSI core. */ 8930 return SCSI_EH_NOT_HANDLED; 8931 } 8932 8933 /* 8934 * If we get here we know that no TMFs are outstanding and also that 8935 * the only pending command is a START STOP UNIT command. Handle the 8936 * timeout of that command directly to prevent a deadlock between 8937 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8938 */ 8939 ufshcd_link_recovery(hba); 8940 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8941 __func__, hba->outstanding_tasks); 8942 8943 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8944 } 8945 8946 static const struct attribute_group *ufshcd_driver_groups[] = { 8947 &ufs_sysfs_unit_descriptor_group, 8948 &ufs_sysfs_lun_attributes_group, 8949 NULL, 8950 }; 8951 8952 static struct ufs_hba_variant_params ufs_hba_vps = { 8953 .hba_enable_delay_us = 1000, 8954 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8955 .devfreq_profile.polling_ms = 100, 8956 .devfreq_profile.target = ufshcd_devfreq_target, 8957 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8958 .ondemand_data.upthreshold = 70, 8959 .ondemand_data.downdifferential = 5, 8960 }; 8961 8962 static const struct scsi_host_template ufshcd_driver_template = { 8963 .module = THIS_MODULE, 8964 .name = UFSHCD, 8965 .proc_name = UFSHCD, 8966 .map_queues = ufshcd_map_queues, 8967 .queuecommand = ufshcd_queuecommand, 8968 .mq_poll = ufshcd_poll, 8969 .slave_alloc = ufshcd_slave_alloc, 8970 .device_configure = ufshcd_device_configure, 8971 .slave_destroy = ufshcd_slave_destroy, 8972 .change_queue_depth = ufshcd_change_queue_depth, 8973 .eh_abort_handler = ufshcd_abort, 8974 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8975 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8976 .eh_timed_out = ufshcd_eh_timed_out, 8977 .this_id = -1, 8978 .sg_tablesize = SG_ALL, 8979 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8980 .max_sectors = SZ_1M / SECTOR_SIZE, 8981 .max_host_blocked = 1, 8982 .track_queue_depth = 1, 8983 .skip_settle_delay = 1, 8984 .sdev_groups = ufshcd_driver_groups, 8985 }; 8986 8987 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8988 int ua) 8989 { 8990 int ret; 8991 8992 if (!vreg) 8993 return 0; 8994 8995 /* 8996 * "set_load" operation shall be required on those regulators 8997 * which specifically configured current limitation. Otherwise 8998 * zero max_uA may cause unexpected behavior when regulator is 8999 * enabled or set as high power mode. 9000 */ 9001 if (!vreg->max_uA) 9002 return 0; 9003 9004 ret = regulator_set_load(vreg->reg, ua); 9005 if (ret < 0) { 9006 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 9007 __func__, vreg->name, ua, ret); 9008 } 9009 9010 return ret; 9011 } 9012 9013 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 9014 struct ufs_vreg *vreg) 9015 { 9016 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 9017 } 9018 9019 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 9020 struct ufs_vreg *vreg) 9021 { 9022 if (!vreg) 9023 return 0; 9024 9025 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 9026 } 9027 9028 static int ufshcd_config_vreg(struct device *dev, 9029 struct ufs_vreg *vreg, bool on) 9030 { 9031 if (regulator_count_voltages(vreg->reg) <= 0) 9032 return 0; 9033 9034 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 9035 } 9036 9037 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 9038 { 9039 int ret = 0; 9040 9041 if (!vreg || vreg->enabled) 9042 goto out; 9043 9044 ret = ufshcd_config_vreg(dev, vreg, true); 9045 if (!ret) 9046 ret = regulator_enable(vreg->reg); 9047 9048 if (!ret) 9049 vreg->enabled = true; 9050 else 9051 dev_err(dev, "%s: %s enable failed, err=%d\n", 9052 __func__, vreg->name, ret); 9053 out: 9054 return ret; 9055 } 9056 9057 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 9058 { 9059 int ret = 0; 9060 9061 if (!vreg || !vreg->enabled || vreg->always_on) 9062 goto out; 9063 9064 ret = regulator_disable(vreg->reg); 9065 9066 if (!ret) { 9067 /* ignore errors on applying disable config */ 9068 ufshcd_config_vreg(dev, vreg, false); 9069 vreg->enabled = false; 9070 } else { 9071 dev_err(dev, "%s: %s disable failed, err=%d\n", 9072 __func__, vreg->name, ret); 9073 } 9074 out: 9075 return ret; 9076 } 9077 9078 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 9079 { 9080 int ret = 0; 9081 struct device *dev = hba->dev; 9082 struct ufs_vreg_info *info = &hba->vreg_info; 9083 9084 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 9085 if (ret) 9086 goto out; 9087 9088 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 9089 if (ret) 9090 goto out; 9091 9092 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 9093 9094 out: 9095 if (ret) { 9096 ufshcd_toggle_vreg(dev, info->vccq2, false); 9097 ufshcd_toggle_vreg(dev, info->vccq, false); 9098 ufshcd_toggle_vreg(dev, info->vcc, false); 9099 } 9100 return ret; 9101 } 9102 9103 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9104 { 9105 struct ufs_vreg_info *info = &hba->vreg_info; 9106 9107 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9108 } 9109 9110 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9111 { 9112 int ret = 0; 9113 9114 if (!vreg) 9115 goto out; 9116 9117 vreg->reg = devm_regulator_get(dev, vreg->name); 9118 if (IS_ERR(vreg->reg)) { 9119 ret = PTR_ERR(vreg->reg); 9120 dev_err(dev, "%s: %s get failed, err=%d\n", 9121 __func__, vreg->name, ret); 9122 } 9123 out: 9124 return ret; 9125 } 9126 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9127 9128 static int ufshcd_init_vreg(struct ufs_hba *hba) 9129 { 9130 int ret = 0; 9131 struct device *dev = hba->dev; 9132 struct ufs_vreg_info *info = &hba->vreg_info; 9133 9134 ret = ufshcd_get_vreg(dev, info->vcc); 9135 if (ret) 9136 goto out; 9137 9138 ret = ufshcd_get_vreg(dev, info->vccq); 9139 if (!ret) 9140 ret = ufshcd_get_vreg(dev, info->vccq2); 9141 out: 9142 return ret; 9143 } 9144 9145 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9146 { 9147 struct ufs_vreg_info *info = &hba->vreg_info; 9148 9149 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9150 } 9151 9152 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9153 { 9154 int ret = 0; 9155 struct ufs_clk_info *clki; 9156 struct list_head *head = &hba->clk_list_head; 9157 unsigned long flags; 9158 ktime_t start = ktime_get(); 9159 bool clk_state_changed = false; 9160 9161 if (list_empty(head)) 9162 goto out; 9163 9164 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9165 if (ret) 9166 return ret; 9167 9168 list_for_each_entry(clki, head, list) { 9169 if (!IS_ERR_OR_NULL(clki->clk)) { 9170 /* 9171 * Don't disable clocks which are needed 9172 * to keep the link active. 9173 */ 9174 if (ufshcd_is_link_active(hba) && 9175 clki->keep_link_active) 9176 continue; 9177 9178 clk_state_changed = on ^ clki->enabled; 9179 if (on && !clki->enabled) { 9180 ret = clk_prepare_enable(clki->clk); 9181 if (ret) { 9182 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9183 __func__, clki->name, ret); 9184 goto out; 9185 } 9186 } else if (!on && clki->enabled) { 9187 clk_disable_unprepare(clki->clk); 9188 } 9189 clki->enabled = on; 9190 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9191 clki->name, on ? "en" : "dis"); 9192 } 9193 } 9194 9195 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9196 if (ret) 9197 return ret; 9198 9199 if (!ufshcd_is_clkscaling_supported(hba)) 9200 ufshcd_pm_qos_update(hba, on); 9201 out: 9202 if (ret) { 9203 list_for_each_entry(clki, head, list) { 9204 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9205 clk_disable_unprepare(clki->clk); 9206 } 9207 } else if (!ret && on) { 9208 spin_lock_irqsave(hba->host->host_lock, flags); 9209 hba->clk_gating.state = CLKS_ON; 9210 trace_ufshcd_clk_gating(dev_name(hba->dev), 9211 hba->clk_gating.state); 9212 spin_unlock_irqrestore(hba->host->host_lock, flags); 9213 } 9214 9215 if (clk_state_changed) 9216 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9217 (on ? "on" : "off"), 9218 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9219 return ret; 9220 } 9221 9222 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9223 { 9224 u32 freq; 9225 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9226 9227 if (ret) { 9228 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9229 return REF_CLK_FREQ_INVAL; 9230 } 9231 9232 return ufs_get_bref_clk_from_hz(freq); 9233 } 9234 9235 static int ufshcd_init_clocks(struct ufs_hba *hba) 9236 { 9237 int ret = 0; 9238 struct ufs_clk_info *clki; 9239 struct device *dev = hba->dev; 9240 struct list_head *head = &hba->clk_list_head; 9241 9242 if (list_empty(head)) 9243 goto out; 9244 9245 list_for_each_entry(clki, head, list) { 9246 if (!clki->name) 9247 continue; 9248 9249 clki->clk = devm_clk_get(dev, clki->name); 9250 if (IS_ERR(clki->clk)) { 9251 ret = PTR_ERR(clki->clk); 9252 dev_err(dev, "%s: %s clk get failed, %d\n", 9253 __func__, clki->name, ret); 9254 goto out; 9255 } 9256 9257 /* 9258 * Parse device ref clk freq as per device tree "ref_clk". 9259 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9260 * in ufshcd_alloc_host(). 9261 */ 9262 if (!strcmp(clki->name, "ref_clk")) 9263 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9264 9265 if (clki->max_freq) { 9266 ret = clk_set_rate(clki->clk, clki->max_freq); 9267 if (ret) { 9268 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9269 __func__, clki->name, 9270 clki->max_freq, ret); 9271 goto out; 9272 } 9273 clki->curr_freq = clki->max_freq; 9274 } 9275 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9276 clki->name, clk_get_rate(clki->clk)); 9277 } 9278 9279 /* Set Max. frequency for all clocks */ 9280 if (hba->use_pm_opp) { 9281 ret = ufshcd_opp_set_rate(hba, ULONG_MAX); 9282 if (ret) { 9283 dev_err(hba->dev, "%s: failed to set OPP: %d", __func__, 9284 ret); 9285 goto out; 9286 } 9287 } 9288 9289 out: 9290 return ret; 9291 } 9292 9293 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9294 { 9295 int err = 0; 9296 9297 if (!hba->vops) 9298 goto out; 9299 9300 err = ufshcd_vops_init(hba); 9301 if (err) 9302 dev_err_probe(hba->dev, err, 9303 "%s: variant %s init failed with err %d\n", 9304 __func__, ufshcd_get_var_name(hba), err); 9305 out: 9306 return err; 9307 } 9308 9309 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9310 { 9311 if (!hba->vops) 9312 return; 9313 9314 ufshcd_vops_exit(hba); 9315 } 9316 9317 static int ufshcd_hba_init(struct ufs_hba *hba) 9318 { 9319 int err; 9320 9321 /* 9322 * Handle host controller power separately from the UFS device power 9323 * rails as it will help controlling the UFS host controller power 9324 * collapse easily which is different than UFS device power collapse. 9325 * Also, enable the host controller power before we go ahead with rest 9326 * of the initialization here. 9327 */ 9328 err = ufshcd_init_hba_vreg(hba); 9329 if (err) 9330 goto out; 9331 9332 err = ufshcd_setup_hba_vreg(hba, true); 9333 if (err) 9334 goto out; 9335 9336 err = ufshcd_init_clocks(hba); 9337 if (err) 9338 goto out_disable_hba_vreg; 9339 9340 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9341 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9342 9343 err = ufshcd_setup_clocks(hba, true); 9344 if (err) 9345 goto out_disable_hba_vreg; 9346 9347 err = ufshcd_init_vreg(hba); 9348 if (err) 9349 goto out_disable_clks; 9350 9351 err = ufshcd_setup_vreg(hba, true); 9352 if (err) 9353 goto out_disable_clks; 9354 9355 err = ufshcd_variant_hba_init(hba); 9356 if (err) 9357 goto out_disable_vreg; 9358 9359 ufs_debugfs_hba_init(hba); 9360 ufs_fault_inject_hba_init(hba); 9361 9362 hba->is_powered = true; 9363 goto out; 9364 9365 out_disable_vreg: 9366 ufshcd_setup_vreg(hba, false); 9367 out_disable_clks: 9368 ufshcd_setup_clocks(hba, false); 9369 out_disable_hba_vreg: 9370 ufshcd_setup_hba_vreg(hba, false); 9371 out: 9372 return err; 9373 } 9374 9375 static void ufshcd_hba_exit(struct ufs_hba *hba) 9376 { 9377 if (hba->is_powered) { 9378 ufshcd_pm_qos_exit(hba); 9379 ufshcd_exit_clk_scaling(hba); 9380 ufshcd_exit_clk_gating(hba); 9381 if (hba->eh_wq) 9382 destroy_workqueue(hba->eh_wq); 9383 ufs_debugfs_hba_exit(hba); 9384 ufshcd_variant_hba_exit(hba); 9385 ufshcd_setup_vreg(hba, false); 9386 ufshcd_setup_clocks(hba, false); 9387 ufshcd_setup_hba_vreg(hba, false); 9388 hba->is_powered = false; 9389 ufs_put_device_desc(hba); 9390 } 9391 } 9392 9393 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9394 enum ufs_dev_pwr_mode pwr_mode, 9395 struct scsi_sense_hdr *sshdr) 9396 { 9397 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9398 struct scsi_failure failure_defs[] = { 9399 { 9400 .allowed = 2, 9401 .result = SCMD_FAILURE_RESULT_ANY, 9402 }, 9403 }; 9404 struct scsi_failures failures = { 9405 .failure_definitions = failure_defs, 9406 }; 9407 const struct scsi_exec_args args = { 9408 .failures = &failures, 9409 .sshdr = sshdr, 9410 .req_flags = BLK_MQ_REQ_PM, 9411 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9412 }; 9413 9414 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9415 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9416 &args); 9417 } 9418 9419 /** 9420 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9421 * power mode 9422 * @hba: per adapter instance 9423 * @pwr_mode: device power mode to set 9424 * 9425 * Return: 0 if requested power mode is set successfully; 9426 * < 0 if failed to set the requested power mode. 9427 */ 9428 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9429 enum ufs_dev_pwr_mode pwr_mode) 9430 { 9431 struct scsi_sense_hdr sshdr; 9432 struct scsi_device *sdp; 9433 unsigned long flags; 9434 int ret; 9435 9436 spin_lock_irqsave(hba->host->host_lock, flags); 9437 sdp = hba->ufs_device_wlun; 9438 if (sdp && scsi_device_online(sdp)) 9439 ret = scsi_device_get(sdp); 9440 else 9441 ret = -ENODEV; 9442 spin_unlock_irqrestore(hba->host->host_lock, flags); 9443 9444 if (ret) 9445 return ret; 9446 9447 /* 9448 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9449 * handling, which would wait for host to be resumed. Since we know 9450 * we are functional while we are here, skip host resume in error 9451 * handling context. 9452 */ 9453 hba->host->eh_noresume = 1; 9454 9455 /* 9456 * Current function would be generally called from the power management 9457 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9458 * already suspended childs. 9459 */ 9460 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9461 if (ret) { 9462 sdev_printk(KERN_WARNING, sdp, 9463 "START_STOP failed for power mode: %d, result %x\n", 9464 pwr_mode, ret); 9465 if (ret > 0) { 9466 if (scsi_sense_valid(&sshdr)) 9467 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9468 ret = -EIO; 9469 } 9470 } else { 9471 hba->curr_dev_pwr_mode = pwr_mode; 9472 } 9473 9474 scsi_device_put(sdp); 9475 hba->host->eh_noresume = 0; 9476 return ret; 9477 } 9478 9479 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9480 enum uic_link_state req_link_state, 9481 bool check_for_bkops) 9482 { 9483 int ret = 0; 9484 9485 if (req_link_state == hba->uic_link_state) 9486 return 0; 9487 9488 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9489 ret = ufshcd_uic_hibern8_enter(hba); 9490 if (!ret) { 9491 ufshcd_set_link_hibern8(hba); 9492 } else { 9493 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9494 __func__, ret); 9495 goto out; 9496 } 9497 } 9498 /* 9499 * If autobkops is enabled, link can't be turned off because 9500 * turning off the link would also turn off the device, except in the 9501 * case of DeepSleep where the device is expected to remain powered. 9502 */ 9503 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9504 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9505 /* 9506 * Let's make sure that link is in low power mode, we are doing 9507 * this currently by putting the link in Hibern8. Otherway to 9508 * put the link in low power mode is to send the DME end point 9509 * to device and then send the DME reset command to local 9510 * unipro. But putting the link in hibern8 is much faster. 9511 * 9512 * Note also that putting the link in Hibern8 is a requirement 9513 * for entering DeepSleep. 9514 */ 9515 ret = ufshcd_uic_hibern8_enter(hba); 9516 if (ret) { 9517 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9518 __func__, ret); 9519 goto out; 9520 } 9521 /* 9522 * Change controller state to "reset state" which 9523 * should also put the link in off/reset state 9524 */ 9525 ufshcd_hba_stop(hba); 9526 /* 9527 * TODO: Check if we need any delay to make sure that 9528 * controller is reset 9529 */ 9530 ufshcd_set_link_off(hba); 9531 } 9532 9533 out: 9534 return ret; 9535 } 9536 9537 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9538 { 9539 bool vcc_off = false; 9540 9541 /* 9542 * It seems some UFS devices may keep drawing more than sleep current 9543 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9544 * To avoid this situation, add 2ms delay before putting these UFS 9545 * rails in LPM mode. 9546 */ 9547 if (!ufshcd_is_link_active(hba) && 9548 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9549 usleep_range(2000, 2100); 9550 9551 /* 9552 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9553 * power. 9554 * 9555 * If UFS device and link is in OFF state, all power supplies (VCC, 9556 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9557 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9558 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9559 * 9560 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9561 * in low power state which would save some power. 9562 * 9563 * If Write Booster is enabled and the device needs to flush the WB 9564 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9565 */ 9566 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9567 !hba->dev_info.is_lu_power_on_wp) { 9568 ufshcd_setup_vreg(hba, false); 9569 vcc_off = true; 9570 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9571 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9572 vcc_off = true; 9573 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9574 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9575 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9576 } 9577 } 9578 9579 /* 9580 * Some UFS devices require delay after VCC power rail is turned-off. 9581 */ 9582 if (vcc_off && hba->vreg_info.vcc && 9583 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9584 usleep_range(5000, 5100); 9585 } 9586 9587 #ifdef CONFIG_PM 9588 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9589 { 9590 int ret = 0; 9591 9592 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9593 !hba->dev_info.is_lu_power_on_wp) { 9594 ret = ufshcd_setup_vreg(hba, true); 9595 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9596 if (!ufshcd_is_link_active(hba)) { 9597 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9598 if (ret) 9599 goto vcc_disable; 9600 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9601 if (ret) 9602 goto vccq_lpm; 9603 } 9604 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9605 } 9606 goto out; 9607 9608 vccq_lpm: 9609 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9610 vcc_disable: 9611 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9612 out: 9613 return ret; 9614 } 9615 #endif /* CONFIG_PM */ 9616 9617 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9618 { 9619 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9620 ufshcd_setup_hba_vreg(hba, false); 9621 } 9622 9623 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9624 { 9625 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9626 ufshcd_setup_hba_vreg(hba, true); 9627 } 9628 9629 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9630 { 9631 int ret = 0; 9632 bool check_for_bkops; 9633 enum ufs_pm_level pm_lvl; 9634 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9635 enum uic_link_state req_link_state; 9636 9637 hba->pm_op_in_progress = true; 9638 if (pm_op != UFS_SHUTDOWN_PM) { 9639 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9640 hba->rpm_lvl : hba->spm_lvl; 9641 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9642 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9643 } else { 9644 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9645 req_link_state = UIC_LINK_OFF_STATE; 9646 } 9647 9648 /* 9649 * If we can't transition into any of the low power modes 9650 * just gate the clocks. 9651 */ 9652 ufshcd_hold(hba); 9653 hba->clk_gating.is_suspended = true; 9654 9655 if (ufshcd_is_clkscaling_supported(hba)) 9656 ufshcd_clk_scaling_suspend(hba, true); 9657 9658 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9659 req_link_state == UIC_LINK_ACTIVE_STATE) { 9660 goto vops_suspend; 9661 } 9662 9663 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9664 (req_link_state == hba->uic_link_state)) 9665 goto enable_scaling; 9666 9667 /* UFS device & link must be active before we enter in this function */ 9668 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9669 /* Wait err handler finish or trigger err recovery */ 9670 if (!ufshcd_eh_in_progress(hba)) 9671 ufshcd_force_error_recovery(hba); 9672 ret = -EBUSY; 9673 goto enable_scaling; 9674 } 9675 9676 if (pm_op == UFS_RUNTIME_PM) { 9677 if (ufshcd_can_autobkops_during_suspend(hba)) { 9678 /* 9679 * The device is idle with no requests in the queue, 9680 * allow background operations if bkops status shows 9681 * that performance might be impacted. 9682 */ 9683 ret = ufshcd_bkops_ctrl(hba); 9684 if (ret) { 9685 /* 9686 * If return err in suspend flow, IO will hang. 9687 * Trigger error handler and break suspend for 9688 * error recovery. 9689 */ 9690 ufshcd_force_error_recovery(hba); 9691 ret = -EBUSY; 9692 goto enable_scaling; 9693 } 9694 } else { 9695 /* make sure that auto bkops is disabled */ 9696 ufshcd_disable_auto_bkops(hba); 9697 } 9698 /* 9699 * If device needs to do BKOP or WB buffer flush during 9700 * Hibern8, keep device power mode as "active power mode" 9701 * and VCC supply. 9702 */ 9703 hba->dev_info.b_rpm_dev_flush_capable = 9704 hba->auto_bkops_enabled || 9705 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9706 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9707 ufshcd_is_auto_hibern8_enabled(hba))) && 9708 ufshcd_wb_need_flush(hba)); 9709 } 9710 9711 flush_work(&hba->eeh_work); 9712 9713 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9714 if (ret) 9715 goto enable_scaling; 9716 9717 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9718 if (pm_op != UFS_RUNTIME_PM) 9719 /* ensure that bkops is disabled */ 9720 ufshcd_disable_auto_bkops(hba); 9721 9722 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9723 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9724 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9725 /* 9726 * If return err in suspend flow, IO will hang. 9727 * Trigger error handler and break suspend for 9728 * error recovery. 9729 */ 9730 ufshcd_force_error_recovery(hba); 9731 ret = -EBUSY; 9732 } 9733 if (ret) 9734 goto enable_scaling; 9735 } 9736 } 9737 9738 /* 9739 * In the case of DeepSleep, the device is expected to remain powered 9740 * with the link off, so do not check for bkops. 9741 */ 9742 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9743 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9744 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9745 /* 9746 * If return err in suspend flow, IO will hang. 9747 * Trigger error handler and break suspend for 9748 * error recovery. 9749 */ 9750 ufshcd_force_error_recovery(hba); 9751 ret = -EBUSY; 9752 } 9753 if (ret) 9754 goto set_dev_active; 9755 9756 vops_suspend: 9757 /* 9758 * Call vendor specific suspend callback. As these callbacks may access 9759 * vendor specific host controller register space call them before the 9760 * host clocks are ON. 9761 */ 9762 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9763 if (ret) 9764 goto set_link_active; 9765 9766 cancel_delayed_work_sync(&hba->ufs_rtc_update_work); 9767 goto out; 9768 9769 set_link_active: 9770 /* 9771 * Device hardware reset is required to exit DeepSleep. Also, for 9772 * DeepSleep, the link is off so host reset and restore will be done 9773 * further below. 9774 */ 9775 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9776 ufshcd_device_reset(hba); 9777 WARN_ON(!ufshcd_is_link_off(hba)); 9778 } 9779 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9780 ufshcd_set_link_active(hba); 9781 else if (ufshcd_is_link_off(hba)) 9782 ufshcd_host_reset_and_restore(hba); 9783 set_dev_active: 9784 /* Can also get here needing to exit DeepSleep */ 9785 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9786 ufshcd_device_reset(hba); 9787 ufshcd_host_reset_and_restore(hba); 9788 } 9789 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9790 ufshcd_disable_auto_bkops(hba); 9791 enable_scaling: 9792 if (ufshcd_is_clkscaling_supported(hba)) 9793 ufshcd_clk_scaling_suspend(hba, false); 9794 9795 hba->dev_info.b_rpm_dev_flush_capable = false; 9796 out: 9797 if (hba->dev_info.b_rpm_dev_flush_capable) { 9798 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9799 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9800 } 9801 9802 if (ret) { 9803 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9804 hba->clk_gating.is_suspended = false; 9805 ufshcd_release(hba); 9806 } 9807 hba->pm_op_in_progress = false; 9808 return ret; 9809 } 9810 9811 #ifdef CONFIG_PM 9812 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9813 { 9814 int ret; 9815 enum uic_link_state old_link_state = hba->uic_link_state; 9816 9817 hba->pm_op_in_progress = true; 9818 9819 /* 9820 * Call vendor specific resume callback. As these callbacks may access 9821 * vendor specific host controller register space call them when the 9822 * host clocks are ON. 9823 */ 9824 ret = ufshcd_vops_resume(hba, pm_op); 9825 if (ret) 9826 goto out; 9827 9828 /* For DeepSleep, the only supported option is to have the link off */ 9829 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9830 9831 if (ufshcd_is_link_hibern8(hba)) { 9832 ret = ufshcd_uic_hibern8_exit(hba); 9833 if (!ret) { 9834 ufshcd_set_link_active(hba); 9835 } else { 9836 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9837 __func__, ret); 9838 goto vendor_suspend; 9839 } 9840 } else if (ufshcd_is_link_off(hba)) { 9841 /* 9842 * A full initialization of the host and the device is 9843 * required since the link was put to off during suspend. 9844 * Note, in the case of DeepSleep, the device will exit 9845 * DeepSleep due to device reset. 9846 */ 9847 ret = ufshcd_reset_and_restore(hba); 9848 /* 9849 * ufshcd_reset_and_restore() should have already 9850 * set the link state as active 9851 */ 9852 if (ret || !ufshcd_is_link_active(hba)) 9853 goto vendor_suspend; 9854 } 9855 9856 if (!ufshcd_is_ufs_dev_active(hba)) { 9857 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9858 if (ret) 9859 goto set_old_link_state; 9860 ufshcd_set_timestamp_attr(hba); 9861 schedule_delayed_work(&hba->ufs_rtc_update_work, 9862 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 9863 } 9864 9865 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9866 ufshcd_enable_auto_bkops(hba); 9867 else 9868 /* 9869 * If BKOPs operations are urgently needed at this moment then 9870 * keep auto-bkops enabled or else disable it. 9871 */ 9872 ufshcd_bkops_ctrl(hba); 9873 9874 if (hba->ee_usr_mask) 9875 ufshcd_write_ee_control(hba); 9876 9877 if (ufshcd_is_clkscaling_supported(hba)) 9878 ufshcd_clk_scaling_suspend(hba, false); 9879 9880 if (hba->dev_info.b_rpm_dev_flush_capable) { 9881 hba->dev_info.b_rpm_dev_flush_capable = false; 9882 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9883 } 9884 9885 ufshcd_configure_auto_hibern8(hba); 9886 9887 goto out; 9888 9889 set_old_link_state: 9890 ufshcd_link_state_transition(hba, old_link_state, 0); 9891 vendor_suspend: 9892 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9893 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9894 out: 9895 if (ret) 9896 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9897 hba->clk_gating.is_suspended = false; 9898 ufshcd_release(hba); 9899 hba->pm_op_in_progress = false; 9900 return ret; 9901 } 9902 9903 static int ufshcd_wl_runtime_suspend(struct device *dev) 9904 { 9905 struct scsi_device *sdev = to_scsi_device(dev); 9906 struct ufs_hba *hba; 9907 int ret; 9908 ktime_t start = ktime_get(); 9909 9910 hba = shost_priv(sdev->host); 9911 9912 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9913 if (ret) 9914 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9915 9916 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9917 ktime_to_us(ktime_sub(ktime_get(), start)), 9918 hba->curr_dev_pwr_mode, hba->uic_link_state); 9919 9920 return ret; 9921 } 9922 9923 static int ufshcd_wl_runtime_resume(struct device *dev) 9924 { 9925 struct scsi_device *sdev = to_scsi_device(dev); 9926 struct ufs_hba *hba; 9927 int ret = 0; 9928 ktime_t start = ktime_get(); 9929 9930 hba = shost_priv(sdev->host); 9931 9932 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9933 if (ret) 9934 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9935 9936 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9937 ktime_to_us(ktime_sub(ktime_get(), start)), 9938 hba->curr_dev_pwr_mode, hba->uic_link_state); 9939 9940 return ret; 9941 } 9942 #endif 9943 9944 #ifdef CONFIG_PM_SLEEP 9945 static int ufshcd_wl_suspend(struct device *dev) 9946 { 9947 struct scsi_device *sdev = to_scsi_device(dev); 9948 struct ufs_hba *hba; 9949 int ret = 0; 9950 ktime_t start = ktime_get(); 9951 9952 hba = shost_priv(sdev->host); 9953 down(&hba->host_sem); 9954 hba->system_suspending = true; 9955 9956 if (pm_runtime_suspended(dev)) 9957 goto out; 9958 9959 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9960 if (ret) { 9961 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9962 up(&hba->host_sem); 9963 } 9964 9965 out: 9966 if (!ret) 9967 hba->is_sys_suspended = true; 9968 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9969 ktime_to_us(ktime_sub(ktime_get(), start)), 9970 hba->curr_dev_pwr_mode, hba->uic_link_state); 9971 9972 return ret; 9973 } 9974 9975 static int ufshcd_wl_resume(struct device *dev) 9976 { 9977 struct scsi_device *sdev = to_scsi_device(dev); 9978 struct ufs_hba *hba; 9979 int ret = 0; 9980 ktime_t start = ktime_get(); 9981 9982 hba = shost_priv(sdev->host); 9983 9984 if (pm_runtime_suspended(dev)) 9985 goto out; 9986 9987 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9988 if (ret) 9989 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9990 out: 9991 trace_ufshcd_wl_resume(dev_name(dev), ret, 9992 ktime_to_us(ktime_sub(ktime_get(), start)), 9993 hba->curr_dev_pwr_mode, hba->uic_link_state); 9994 if (!ret) 9995 hba->is_sys_suspended = false; 9996 hba->system_suspending = false; 9997 up(&hba->host_sem); 9998 return ret; 9999 } 10000 #endif 10001 10002 /** 10003 * ufshcd_suspend - helper function for suspend operations 10004 * @hba: per adapter instance 10005 * 10006 * This function will put disable irqs, turn off clocks 10007 * and set vreg and hba-vreg in lpm mode. 10008 * 10009 * Return: 0 upon success; < 0 upon failure. 10010 */ 10011 static int ufshcd_suspend(struct ufs_hba *hba) 10012 { 10013 int ret; 10014 10015 if (!hba->is_powered) 10016 return 0; 10017 /* 10018 * Disable the host irq as host controller as there won't be any 10019 * host controller transaction expected till resume. 10020 */ 10021 ufshcd_disable_irq(hba); 10022 ret = ufshcd_setup_clocks(hba, false); 10023 if (ret) { 10024 ufshcd_enable_irq(hba); 10025 return ret; 10026 } 10027 if (ufshcd_is_clkgating_allowed(hba)) { 10028 hba->clk_gating.state = CLKS_OFF; 10029 trace_ufshcd_clk_gating(dev_name(hba->dev), 10030 hba->clk_gating.state); 10031 } 10032 10033 ufshcd_vreg_set_lpm(hba); 10034 /* Put the host controller in low power mode if possible */ 10035 ufshcd_hba_vreg_set_lpm(hba); 10036 ufshcd_pm_qos_update(hba, false); 10037 return ret; 10038 } 10039 10040 #ifdef CONFIG_PM 10041 /** 10042 * ufshcd_resume - helper function for resume operations 10043 * @hba: per adapter instance 10044 * 10045 * This function basically turns on the regulators, clocks and 10046 * irqs of the hba. 10047 * 10048 * Return: 0 for success and non-zero for failure. 10049 */ 10050 static int ufshcd_resume(struct ufs_hba *hba) 10051 { 10052 int ret; 10053 10054 if (!hba->is_powered) 10055 return 0; 10056 10057 ufshcd_hba_vreg_set_hpm(hba); 10058 ret = ufshcd_vreg_set_hpm(hba); 10059 if (ret) 10060 goto out; 10061 10062 /* Make sure clocks are enabled before accessing controller */ 10063 ret = ufshcd_setup_clocks(hba, true); 10064 if (ret) 10065 goto disable_vreg; 10066 10067 /* enable the host irq as host controller would be active soon */ 10068 ufshcd_enable_irq(hba); 10069 10070 goto out; 10071 10072 disable_vreg: 10073 ufshcd_vreg_set_lpm(hba); 10074 out: 10075 if (ret) 10076 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 10077 return ret; 10078 } 10079 #endif /* CONFIG_PM */ 10080 10081 #ifdef CONFIG_PM_SLEEP 10082 /** 10083 * ufshcd_system_suspend - system suspend callback 10084 * @dev: Device associated with the UFS controller. 10085 * 10086 * Executed before putting the system into a sleep state in which the contents 10087 * of main memory are preserved. 10088 * 10089 * Return: 0 for success and non-zero for failure. 10090 */ 10091 int ufshcd_system_suspend(struct device *dev) 10092 { 10093 struct ufs_hba *hba = dev_get_drvdata(dev); 10094 int ret = 0; 10095 ktime_t start = ktime_get(); 10096 10097 if (pm_runtime_suspended(hba->dev)) 10098 goto out; 10099 10100 ret = ufshcd_suspend(hba); 10101 out: 10102 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 10103 ktime_to_us(ktime_sub(ktime_get(), start)), 10104 hba->curr_dev_pwr_mode, hba->uic_link_state); 10105 return ret; 10106 } 10107 EXPORT_SYMBOL(ufshcd_system_suspend); 10108 10109 /** 10110 * ufshcd_system_resume - system resume callback 10111 * @dev: Device associated with the UFS controller. 10112 * 10113 * Executed after waking the system up from a sleep state in which the contents 10114 * of main memory were preserved. 10115 * 10116 * Return: 0 for success and non-zero for failure. 10117 */ 10118 int ufshcd_system_resume(struct device *dev) 10119 { 10120 struct ufs_hba *hba = dev_get_drvdata(dev); 10121 ktime_t start = ktime_get(); 10122 int ret = 0; 10123 10124 if (pm_runtime_suspended(hba->dev)) 10125 goto out; 10126 10127 ret = ufshcd_resume(hba); 10128 10129 out: 10130 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10131 ktime_to_us(ktime_sub(ktime_get(), start)), 10132 hba->curr_dev_pwr_mode, hba->uic_link_state); 10133 10134 return ret; 10135 } 10136 EXPORT_SYMBOL(ufshcd_system_resume); 10137 #endif /* CONFIG_PM_SLEEP */ 10138 10139 #ifdef CONFIG_PM 10140 /** 10141 * ufshcd_runtime_suspend - runtime suspend callback 10142 * @dev: Device associated with the UFS controller. 10143 * 10144 * Check the description of ufshcd_suspend() function for more details. 10145 * 10146 * Return: 0 for success and non-zero for failure. 10147 */ 10148 int ufshcd_runtime_suspend(struct device *dev) 10149 { 10150 struct ufs_hba *hba = dev_get_drvdata(dev); 10151 int ret; 10152 ktime_t start = ktime_get(); 10153 10154 ret = ufshcd_suspend(hba); 10155 10156 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10157 ktime_to_us(ktime_sub(ktime_get(), start)), 10158 hba->curr_dev_pwr_mode, hba->uic_link_state); 10159 return ret; 10160 } 10161 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10162 10163 /** 10164 * ufshcd_runtime_resume - runtime resume routine 10165 * @dev: Device associated with the UFS controller. 10166 * 10167 * This function basically brings controller 10168 * to active state. Following operations are done in this function: 10169 * 10170 * 1. Turn on all the controller related clocks 10171 * 2. Turn ON VCC rail 10172 * 10173 * Return: 0 upon success; < 0 upon failure. 10174 */ 10175 int ufshcd_runtime_resume(struct device *dev) 10176 { 10177 struct ufs_hba *hba = dev_get_drvdata(dev); 10178 int ret; 10179 ktime_t start = ktime_get(); 10180 10181 ret = ufshcd_resume(hba); 10182 10183 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10184 ktime_to_us(ktime_sub(ktime_get(), start)), 10185 hba->curr_dev_pwr_mode, hba->uic_link_state); 10186 return ret; 10187 } 10188 EXPORT_SYMBOL(ufshcd_runtime_resume); 10189 #endif /* CONFIG_PM */ 10190 10191 static void ufshcd_wl_shutdown(struct device *dev) 10192 { 10193 struct scsi_device *sdev = to_scsi_device(dev); 10194 struct ufs_hba *hba = shost_priv(sdev->host); 10195 10196 down(&hba->host_sem); 10197 hba->shutting_down = true; 10198 up(&hba->host_sem); 10199 10200 /* Turn on everything while shutting down */ 10201 ufshcd_rpm_get_sync(hba); 10202 scsi_device_quiesce(sdev); 10203 shost_for_each_device(sdev, hba->host) { 10204 if (sdev == hba->ufs_device_wlun) 10205 continue; 10206 mutex_lock(&sdev->state_mutex); 10207 scsi_device_set_state(sdev, SDEV_OFFLINE); 10208 mutex_unlock(&sdev->state_mutex); 10209 } 10210 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10211 10212 /* 10213 * Next, turn off the UFS controller and the UFS regulators. Disable 10214 * clocks. 10215 */ 10216 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10217 ufshcd_suspend(hba); 10218 10219 hba->is_powered = false; 10220 } 10221 10222 /** 10223 * ufshcd_remove - de-allocate SCSI host and host memory space 10224 * data structure memory 10225 * @hba: per adapter instance 10226 */ 10227 void ufshcd_remove(struct ufs_hba *hba) 10228 { 10229 if (hba->ufs_device_wlun) 10230 ufshcd_rpm_get_sync(hba); 10231 ufs_hwmon_remove(hba); 10232 ufs_bsg_remove(hba); 10233 ufs_sysfs_remove_nodes(hba->dev); 10234 cancel_delayed_work_sync(&hba->ufs_rtc_update_work); 10235 blk_mq_destroy_queue(hba->tmf_queue); 10236 blk_put_queue(hba->tmf_queue); 10237 blk_mq_free_tag_set(&hba->tmf_tag_set); 10238 if (hba->scsi_host_added) 10239 scsi_remove_host(hba->host); 10240 /* disable interrupts */ 10241 ufshcd_disable_intr(hba, hba->intr_mask); 10242 ufshcd_hba_stop(hba); 10243 ufshcd_hba_exit(hba); 10244 } 10245 EXPORT_SYMBOL_GPL(ufshcd_remove); 10246 10247 #ifdef CONFIG_PM_SLEEP 10248 int ufshcd_system_freeze(struct device *dev) 10249 { 10250 10251 return ufshcd_system_suspend(dev); 10252 10253 } 10254 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10255 10256 int ufshcd_system_restore(struct device *dev) 10257 { 10258 10259 struct ufs_hba *hba = dev_get_drvdata(dev); 10260 int ret; 10261 10262 ret = ufshcd_system_resume(dev); 10263 if (ret) 10264 return ret; 10265 10266 /* Configure UTRL and UTMRL base address registers */ 10267 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10268 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10269 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10270 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10271 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10272 REG_UTP_TASK_REQ_LIST_BASE_L); 10273 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10274 REG_UTP_TASK_REQ_LIST_BASE_H); 10275 /* 10276 * Make sure that UTRL and UTMRL base address registers 10277 * are updated with the latest queue addresses. Only after 10278 * updating these addresses, we can queue the new commands. 10279 */ 10280 ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H); 10281 10282 return 0; 10283 10284 } 10285 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10286 10287 int ufshcd_system_thaw(struct device *dev) 10288 { 10289 return ufshcd_system_resume(dev); 10290 } 10291 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10292 #endif /* CONFIG_PM_SLEEP */ 10293 10294 /** 10295 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10296 * @hba: pointer to Host Bus Adapter (HBA) 10297 */ 10298 void ufshcd_dealloc_host(struct ufs_hba *hba) 10299 { 10300 scsi_host_put(hba->host); 10301 } 10302 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10303 10304 /** 10305 * ufshcd_set_dma_mask - Set dma mask based on the controller 10306 * addressing capability 10307 * @hba: per adapter instance 10308 * 10309 * Return: 0 for success, non-zero for failure. 10310 */ 10311 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10312 { 10313 if (hba->vops && hba->vops->set_dma_mask) 10314 return hba->vops->set_dma_mask(hba); 10315 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10316 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10317 return 0; 10318 } 10319 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10320 } 10321 10322 /** 10323 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10324 * @dev: pointer to device handle 10325 * @hba_handle: driver private handle 10326 * 10327 * Return: 0 on success, non-zero value on failure. 10328 */ 10329 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10330 { 10331 struct Scsi_Host *host; 10332 struct ufs_hba *hba; 10333 int err = 0; 10334 10335 if (!dev) { 10336 dev_err(dev, 10337 "Invalid memory reference for dev is NULL\n"); 10338 err = -ENODEV; 10339 goto out_error; 10340 } 10341 10342 host = scsi_host_alloc(&ufshcd_driver_template, 10343 sizeof(struct ufs_hba)); 10344 if (!host) { 10345 dev_err(dev, "scsi_host_alloc failed\n"); 10346 err = -ENOMEM; 10347 goto out_error; 10348 } 10349 host->nr_maps = HCTX_TYPE_POLL + 1; 10350 hba = shost_priv(host); 10351 hba->host = host; 10352 hba->dev = dev; 10353 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10354 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10355 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10356 INIT_LIST_HEAD(&hba->clk_list_head); 10357 spin_lock_init(&hba->outstanding_lock); 10358 10359 *hba_handle = hba; 10360 10361 out_error: 10362 return err; 10363 } 10364 EXPORT_SYMBOL(ufshcd_alloc_host); 10365 10366 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10367 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10368 const struct blk_mq_queue_data *qd) 10369 { 10370 WARN_ON_ONCE(true); 10371 return BLK_STS_NOTSUPP; 10372 } 10373 10374 static const struct blk_mq_ops ufshcd_tmf_ops = { 10375 .queue_rq = ufshcd_queue_tmf, 10376 }; 10377 10378 static int ufshcd_add_scsi_host(struct ufs_hba *hba) 10379 { 10380 int err; 10381 10382 if (is_mcq_supported(hba)) { 10383 ufshcd_mcq_enable(hba); 10384 err = ufshcd_alloc_mcq(hba); 10385 if (!err) { 10386 ufshcd_config_mcq(hba); 10387 } else { 10388 /* Continue with SDB mode */ 10389 ufshcd_mcq_disable(hba); 10390 use_mcq_mode = false; 10391 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 10392 err); 10393 } 10394 } 10395 if (!is_mcq_supported(hba) && !hba->lsdb_sup) { 10396 dev_err(hba->dev, 10397 "%s: failed to initialize (legacy doorbell mode not supported)\n", 10398 __func__); 10399 return -EINVAL; 10400 } 10401 10402 err = scsi_add_host(hba->host, hba->dev); 10403 if (err) { 10404 dev_err(hba->dev, "scsi_add_host failed\n"); 10405 return err; 10406 } 10407 hba->scsi_host_added = true; 10408 10409 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10410 .nr_hw_queues = 1, 10411 .queue_depth = hba->nutmrs, 10412 .ops = &ufshcd_tmf_ops, 10413 .flags = BLK_MQ_F_NO_SCHED, 10414 }; 10415 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10416 if (err < 0) 10417 goto remove_scsi_host; 10418 hba->tmf_queue = blk_mq_alloc_queue(&hba->tmf_tag_set, NULL, NULL); 10419 if (IS_ERR(hba->tmf_queue)) { 10420 err = PTR_ERR(hba->tmf_queue); 10421 goto free_tmf_tag_set; 10422 } 10423 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10424 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10425 if (!hba->tmf_rqs) { 10426 err = -ENOMEM; 10427 goto free_tmf_queue; 10428 } 10429 10430 return 0; 10431 10432 free_tmf_queue: 10433 blk_mq_destroy_queue(hba->tmf_queue); 10434 blk_put_queue(hba->tmf_queue); 10435 10436 free_tmf_tag_set: 10437 blk_mq_free_tag_set(&hba->tmf_tag_set); 10438 10439 remove_scsi_host: 10440 if (hba->scsi_host_added) 10441 scsi_remove_host(hba->host); 10442 10443 return err; 10444 } 10445 10446 /** 10447 * ufshcd_init - Driver initialization routine 10448 * @hba: per-adapter instance 10449 * @mmio_base: base register address 10450 * @irq: Interrupt line of device 10451 * 10452 * Return: 0 on success, non-zero value on failure. 10453 */ 10454 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10455 { 10456 int err; 10457 struct Scsi_Host *host = hba->host; 10458 struct device *dev = hba->dev; 10459 10460 /* 10461 * dev_set_drvdata() must be called before any callbacks are registered 10462 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10463 * sysfs). 10464 */ 10465 dev_set_drvdata(dev, hba); 10466 10467 if (!mmio_base) { 10468 dev_err(hba->dev, 10469 "Invalid memory reference for mmio_base is NULL\n"); 10470 err = -ENODEV; 10471 goto out_error; 10472 } 10473 10474 hba->mmio_base = mmio_base; 10475 hba->irq = irq; 10476 hba->vps = &ufs_hba_vps; 10477 10478 err = ufshcd_hba_init(hba); 10479 if (err) 10480 goto out_error; 10481 10482 /* Read capabilities registers */ 10483 err = ufshcd_hba_capabilities(hba); 10484 if (err) 10485 goto out_disable; 10486 10487 /* Get UFS version supported by the controller */ 10488 hba->ufs_version = ufshcd_get_ufs_version(hba); 10489 10490 /* Get Interrupt bit mask per version */ 10491 hba->intr_mask = ufshcd_get_intr_mask(hba); 10492 10493 err = ufshcd_set_dma_mask(hba); 10494 if (err) { 10495 dev_err(hba->dev, "set dma mask failed\n"); 10496 goto out_disable; 10497 } 10498 10499 /* Allocate memory for host memory space */ 10500 err = ufshcd_memory_alloc(hba); 10501 if (err) { 10502 dev_err(hba->dev, "Memory allocation failed\n"); 10503 goto out_disable; 10504 } 10505 10506 /* Configure LRB */ 10507 ufshcd_host_memory_configure(hba); 10508 10509 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10510 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10511 host->max_id = UFSHCD_MAX_ID; 10512 host->max_lun = UFS_MAX_LUNS; 10513 host->max_channel = UFSHCD_MAX_CHANNEL; 10514 host->unique_id = host->host_no; 10515 host->max_cmd_len = UFS_CDB_SIZE; 10516 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10517 10518 /* Use default RPM delay if host not set */ 10519 if (host->rpm_autosuspend_delay == 0) 10520 host->rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS; 10521 10522 hba->max_pwr_info.is_valid = false; 10523 10524 /* Initialize work queues */ 10525 hba->eh_wq = alloc_ordered_workqueue("ufs_eh_wq_%d", WQ_MEM_RECLAIM, 10526 hba->host->host_no); 10527 if (!hba->eh_wq) { 10528 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10529 __func__); 10530 err = -ENOMEM; 10531 goto out_disable; 10532 } 10533 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10534 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10535 10536 sema_init(&hba->host_sem, 1); 10537 10538 /* Initialize UIC command mutex */ 10539 mutex_init(&hba->uic_cmd_mutex); 10540 10541 /* Initialize mutex for device management commands */ 10542 mutex_init(&hba->dev_cmd.lock); 10543 10544 /* Initialize mutex for exception event control */ 10545 mutex_init(&hba->ee_ctrl_mutex); 10546 10547 mutex_init(&hba->wb_mutex); 10548 init_rwsem(&hba->clk_scaling_lock); 10549 10550 ufshcd_init_clk_gating(hba); 10551 10552 ufshcd_init_clk_scaling(hba); 10553 10554 /* 10555 * In order to avoid any spurious interrupt immediately after 10556 * registering UFS controller interrupt handler, clear any pending UFS 10557 * interrupt status and disable all the UFS interrupts. 10558 */ 10559 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10560 REG_INTERRUPT_STATUS); 10561 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10562 /* 10563 * Make sure that UFS interrupts are disabled and any pending interrupt 10564 * status is cleared before registering UFS interrupt handler. 10565 */ 10566 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 10567 10568 /* IRQ registration */ 10569 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10570 if (err) { 10571 dev_err(hba->dev, "request irq failed\n"); 10572 goto out_disable; 10573 } else { 10574 hba->is_irq_enabled = true; 10575 } 10576 10577 /* Reset the attached device */ 10578 ufshcd_device_reset(hba); 10579 10580 ufshcd_init_crypto(hba); 10581 10582 /* Host controller enable */ 10583 err = ufshcd_hba_enable(hba); 10584 if (err) { 10585 dev_err(hba->dev, "Host controller enable failed\n"); 10586 ufshcd_print_evt_hist(hba); 10587 ufshcd_print_host_state(hba); 10588 goto out_disable; 10589 } 10590 10591 /* 10592 * Set the default power management level for runtime and system PM. 10593 * Default power saving mode is to keep UFS link in Hibern8 state 10594 * and UFS device in sleep state. 10595 */ 10596 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10597 UFS_SLEEP_PWR_MODE, 10598 UIC_LINK_HIBERN8_STATE); 10599 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10600 UFS_SLEEP_PWR_MODE, 10601 UIC_LINK_HIBERN8_STATE); 10602 10603 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, ufshcd_rpm_dev_flush_recheck_work); 10604 INIT_DELAYED_WORK(&hba->ufs_rtc_update_work, ufshcd_rtc_work); 10605 10606 /* Set the default auto-hiberate idle timer value to 150 ms */ 10607 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10608 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10609 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10610 } 10611 10612 /* Hold auto suspend until async scan completes */ 10613 pm_runtime_get_sync(dev); 10614 10615 /* 10616 * We are assuming that device wasn't put in sleep/power-down 10617 * state exclusively during the boot stage before kernel. 10618 * This assumption helps avoid doing link startup twice during 10619 * ufshcd_probe_hba(). 10620 */ 10621 ufshcd_set_ufs_dev_active(hba); 10622 10623 /* Initialize hba, detect and initialize UFS device */ 10624 ktime_t probe_start = ktime_get(); 10625 10626 hba->ufshcd_state = UFSHCD_STATE_RESET; 10627 10628 err = ufshcd_link_startup(hba); 10629 if (err) 10630 goto out_disable; 10631 10632 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 10633 goto initialized; 10634 10635 /* Debug counters initialization */ 10636 ufshcd_clear_dbg_ufs_stats(hba); 10637 10638 /* UniPro link is active now */ 10639 ufshcd_set_link_active(hba); 10640 10641 /* Verify device initialization by sending NOP OUT UPIU */ 10642 err = ufshcd_verify_dev_init(hba); 10643 if (err) 10644 goto out_disable; 10645 10646 /* Initiate UFS initialization, and waiting until completion */ 10647 err = ufshcd_complete_dev_init(hba); 10648 if (err) 10649 goto out_disable; 10650 10651 err = ufshcd_device_params_init(hba); 10652 if (err) 10653 goto out_disable; 10654 10655 err = ufshcd_post_device_init(hba); 10656 10657 initialized: 10658 ufshcd_process_probe_result(hba, probe_start, err); 10659 if (err) 10660 goto out_disable; 10661 10662 err = ufshcd_add_scsi_host(hba); 10663 if (err) 10664 goto out_disable; 10665 10666 async_schedule(ufshcd_async_scan, hba); 10667 ufs_sysfs_add_nodes(hba->dev); 10668 10669 device_enable_async_suspend(dev); 10670 ufshcd_pm_qos_init(hba); 10671 return 0; 10672 10673 out_disable: 10674 hba->is_irq_enabled = false; 10675 ufshcd_hba_exit(hba); 10676 out_error: 10677 return err; 10678 } 10679 EXPORT_SYMBOL_GPL(ufshcd_init); 10680 10681 void ufshcd_resume_complete(struct device *dev) 10682 { 10683 struct ufs_hba *hba = dev_get_drvdata(dev); 10684 10685 if (hba->complete_put) { 10686 ufshcd_rpm_put(hba); 10687 hba->complete_put = false; 10688 } 10689 } 10690 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10691 10692 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10693 { 10694 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10695 enum ufs_dev_pwr_mode dev_pwr_mode; 10696 enum uic_link_state link_state; 10697 unsigned long flags; 10698 bool res; 10699 10700 spin_lock_irqsave(&dev->power.lock, flags); 10701 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10702 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10703 res = pm_runtime_suspended(dev) && 10704 hba->curr_dev_pwr_mode == dev_pwr_mode && 10705 hba->uic_link_state == link_state && 10706 !hba->dev_info.b_rpm_dev_flush_capable; 10707 spin_unlock_irqrestore(&dev->power.lock, flags); 10708 10709 return res; 10710 } 10711 10712 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10713 { 10714 struct ufs_hba *hba = dev_get_drvdata(dev); 10715 int ret; 10716 10717 /* 10718 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10719 * are same. And it doesn't wake up the device for system-suspend 10720 * if it's runtime suspended. But ufs doesn't follow that. 10721 * Refer ufshcd_resume_complete() 10722 */ 10723 if (hba->ufs_device_wlun) { 10724 /* Prevent runtime suspend */ 10725 ufshcd_rpm_get_noresume(hba); 10726 /* 10727 * Check if already runtime suspended in same state as system 10728 * suspend would be. 10729 */ 10730 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10731 /* RPM state is not ok for SPM, so runtime resume */ 10732 ret = ufshcd_rpm_resume(hba); 10733 if (ret < 0 && ret != -EACCES) { 10734 ufshcd_rpm_put(hba); 10735 return ret; 10736 } 10737 } 10738 hba->complete_put = true; 10739 } 10740 return 0; 10741 } 10742 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10743 10744 int ufshcd_suspend_prepare(struct device *dev) 10745 { 10746 return __ufshcd_suspend_prepare(dev, true); 10747 } 10748 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10749 10750 #ifdef CONFIG_PM_SLEEP 10751 static int ufshcd_wl_poweroff(struct device *dev) 10752 { 10753 struct scsi_device *sdev = to_scsi_device(dev); 10754 struct ufs_hba *hba = shost_priv(sdev->host); 10755 10756 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10757 return 0; 10758 } 10759 #endif 10760 10761 static int ufshcd_wl_probe(struct device *dev) 10762 { 10763 struct scsi_device *sdev = to_scsi_device(dev); 10764 10765 if (!is_device_wlun(sdev)) 10766 return -ENODEV; 10767 10768 blk_pm_runtime_init(sdev->request_queue, dev); 10769 pm_runtime_set_autosuspend_delay(dev, 0); 10770 pm_runtime_allow(dev); 10771 10772 return 0; 10773 } 10774 10775 static int ufshcd_wl_remove(struct device *dev) 10776 { 10777 pm_runtime_forbid(dev); 10778 return 0; 10779 } 10780 10781 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10782 #ifdef CONFIG_PM_SLEEP 10783 .suspend = ufshcd_wl_suspend, 10784 .resume = ufshcd_wl_resume, 10785 .freeze = ufshcd_wl_suspend, 10786 .thaw = ufshcd_wl_resume, 10787 .poweroff = ufshcd_wl_poweroff, 10788 .restore = ufshcd_wl_resume, 10789 #endif 10790 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10791 }; 10792 10793 static void ufshcd_check_header_layout(void) 10794 { 10795 /* 10796 * gcc compilers before version 10 cannot do constant-folding for 10797 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10798 * before. 10799 */ 10800 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10801 return; 10802 10803 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10804 .cci = 3})[0] != 3); 10805 10806 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10807 .ehs_length = 2})[1] != 2); 10808 10809 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10810 .enable_crypto = 1})[2] 10811 != 0x80); 10812 10813 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10814 .command_type = 5, 10815 .data_direction = 3, 10816 .interrupt = 1, 10817 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10818 10819 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10820 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10821 cpu_to_le32(0xdeadbeef)); 10822 10823 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10824 .ocs = 4})[8] != 4); 10825 10826 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10827 .cds = 5})[9] != 5); 10828 10829 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10830 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10831 cpu_to_le32(0xbadcafe)); 10832 10833 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10834 .iid = 0xf })[4] != 0xf0); 10835 10836 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10837 .command_set_type = 0xf })[4] != 0xf); 10838 } 10839 10840 /* 10841 * ufs_dev_wlun_template - describes ufs device wlun 10842 * ufs-device wlun - used to send pm commands 10843 * All luns are consumers of ufs-device wlun. 10844 * 10845 * Currently, no sd driver is present for wluns. 10846 * Hence the no specific pm operations are performed. 10847 * With ufs design, SSU should be sent to ufs-device wlun. 10848 * Hence register a scsi driver for ufs wluns only. 10849 */ 10850 static struct scsi_driver ufs_dev_wlun_template = { 10851 .gendrv = { 10852 .name = "ufs_device_wlun", 10853 .probe = ufshcd_wl_probe, 10854 .remove = ufshcd_wl_remove, 10855 .pm = &ufshcd_wl_pm_ops, 10856 .shutdown = ufshcd_wl_shutdown, 10857 }, 10858 }; 10859 10860 static int __init ufshcd_core_init(void) 10861 { 10862 int ret; 10863 10864 ufshcd_check_header_layout(); 10865 10866 ufs_debugfs_init(); 10867 10868 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10869 if (ret) 10870 ufs_debugfs_exit(); 10871 return ret; 10872 } 10873 10874 static void __exit ufshcd_core_exit(void) 10875 { 10876 ufs_debugfs_exit(); 10877 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10878 } 10879 10880 module_init(ufshcd_core_init); 10881 module_exit(ufshcd_core_exit); 10882 10883 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10884 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10885 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10886 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10887 MODULE_LICENSE("GPL"); 10888