1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/pm_opp.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/sched/clock.h> 26 #include <linux/iopoll.h> 27 #include <scsi/scsi_cmnd.h> 28 #include <scsi/scsi_dbg.h> 29 #include <scsi/scsi_driver.h> 30 #include <scsi/scsi_eh.h> 31 #include "ufshcd-priv.h" 32 #include <ufs/ufs_quirks.h> 33 #include <ufs/unipro.h> 34 #include "ufs-sysfs.h" 35 #include "ufs-debugfs.h" 36 #include "ufs-fault-injection.h" 37 #include "ufs_bsg.h" 38 #include "ufshcd-crypto.h" 39 #include <asm/unaligned.h> 40 41 #define CREATE_TRACE_POINTS 42 #include <trace/events/ufs.h> 43 44 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 45 UTP_TASK_REQ_COMPL |\ 46 UFSHCD_ERROR_MASK) 47 48 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 49 UFSHCD_ERROR_MASK |\ 50 MCQ_CQ_EVENT_STATUS) 51 52 53 /* UIC command timeout, unit: ms */ 54 #define UIC_CMD_TIMEOUT 500 55 56 /* NOP OUT retries waiting for NOP IN response */ 57 #define NOP_OUT_RETRIES 10 58 /* Timeout after 50 msecs if NOP OUT hangs without response */ 59 #define NOP_OUT_TIMEOUT 50 /* msecs */ 60 61 /* Query request retries */ 62 #define QUERY_REQ_RETRIES 3 63 /* Query request timeout */ 64 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 65 66 /* Advanced RPMB request timeout */ 67 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 68 69 /* Task management command timeout */ 70 #define TM_CMD_TIMEOUT 100 /* msecs */ 71 72 /* maximum number of retries for a general UIC command */ 73 #define UFS_UIC_COMMAND_RETRIES 3 74 75 /* maximum number of link-startup retries */ 76 #define DME_LINKSTARTUP_RETRIES 3 77 78 /* maximum number of reset retries before giving up */ 79 #define MAX_HOST_RESET_RETRIES 5 80 81 /* Maximum number of error handler retries before giving up */ 82 #define MAX_ERR_HANDLER_RETRIES 5 83 84 /* Expose the flag value from utp_upiu_query.value */ 85 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 86 87 /* Interrupt aggregation default timeout, unit: 40us */ 88 #define INT_AGGR_DEF_TO 0x02 89 90 /* default delay of autosuspend: 2000 ms */ 91 #define RPM_AUTOSUSPEND_DELAY_MS 2000 92 93 /* Default delay of RPM device flush delayed work */ 94 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 95 96 /* Default value of wait time before gating device ref clock */ 97 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 98 99 /* Polling time to wait for fDeviceInit */ 100 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 101 102 /* Default RTC update every 10 seconds */ 103 #define UFS_RTC_UPDATE_INTERVAL_MS (10 * MSEC_PER_SEC) 104 105 /* UFSHC 4.0 compliant HC support this mode. */ 106 static bool use_mcq_mode = true; 107 108 static bool is_mcq_supported(struct ufs_hba *hba) 109 { 110 return hba->mcq_sup && use_mcq_mode; 111 } 112 113 module_param(use_mcq_mode, bool, 0644); 114 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 115 116 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 117 ({ \ 118 int _ret; \ 119 if (_on) \ 120 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 121 else \ 122 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 123 _ret; \ 124 }) 125 126 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 127 size_t __len = (len); \ 128 print_hex_dump(KERN_ERR, prefix_str, \ 129 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 130 16, 4, buf, __len, false); \ 131 } while (0) 132 133 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 134 const char *prefix) 135 { 136 u32 *regs; 137 size_t pos; 138 139 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 140 return -EINVAL; 141 142 regs = kzalloc(len, GFP_ATOMIC); 143 if (!regs) 144 return -ENOMEM; 145 146 for (pos = 0; pos < len; pos += 4) { 147 if (offset == 0 && 148 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 149 pos <= REG_UIC_ERROR_CODE_DME) 150 continue; 151 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 152 } 153 154 ufshcd_hex_dump(prefix, regs, len); 155 kfree(regs); 156 157 return 0; 158 } 159 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 160 161 enum { 162 UFSHCD_MAX_CHANNEL = 0, 163 UFSHCD_MAX_ID = 1, 164 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED, 165 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED, 166 }; 167 168 static const char *const ufshcd_state_name[] = { 169 [UFSHCD_STATE_RESET] = "reset", 170 [UFSHCD_STATE_OPERATIONAL] = "operational", 171 [UFSHCD_STATE_ERROR] = "error", 172 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 173 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 174 }; 175 176 /* UFSHCD error handling flags */ 177 enum { 178 UFSHCD_EH_IN_PROGRESS = (1 << 0), 179 }; 180 181 /* UFSHCD UIC layer error flags */ 182 enum { 183 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 184 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 185 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 186 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 187 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 188 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 189 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 190 }; 191 192 #define ufshcd_set_eh_in_progress(h) \ 193 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 194 #define ufshcd_eh_in_progress(h) \ 195 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 196 #define ufshcd_clear_eh_in_progress(h) \ 197 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 198 199 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 200 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 201 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 202 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 203 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 204 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 205 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 206 /* 207 * For DeepSleep, the link is first put in hibern8 and then off. 208 * Leaving the link in hibern8 is not supported. 209 */ 210 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 211 }; 212 213 static inline enum ufs_dev_pwr_mode 214 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 215 { 216 return ufs_pm_lvl_states[lvl].dev_state; 217 } 218 219 static inline enum uic_link_state 220 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 221 { 222 return ufs_pm_lvl_states[lvl].link_state; 223 } 224 225 static inline enum ufs_pm_level 226 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 227 enum uic_link_state link_state) 228 { 229 enum ufs_pm_level lvl; 230 231 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 232 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 233 (ufs_pm_lvl_states[lvl].link_state == link_state)) 234 return lvl; 235 } 236 237 /* if no match found, return the level 0 */ 238 return UFS_PM_LVL_0; 239 } 240 241 static bool ufshcd_is_ufs_dev_busy(struct ufs_hba *hba) 242 { 243 return (hba->clk_gating.active_reqs || hba->outstanding_reqs || hba->outstanding_tasks || 244 hba->active_uic_cmd || hba->uic_async_done); 245 } 246 247 static const struct ufs_dev_quirk ufs_fixups[] = { 248 /* UFS cards deviations table */ 249 { .wmanufacturerid = UFS_VENDOR_MICRON, 250 .model = UFS_ANY_MODEL, 251 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 252 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 253 .model = UFS_ANY_MODEL, 254 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 255 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 256 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 257 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 258 .model = UFS_ANY_MODEL, 259 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 260 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 261 .model = "hB8aL1" /*H28U62301AMR*/, 262 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 263 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 264 .model = UFS_ANY_MODEL, 265 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 266 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 267 .model = "THGLF2G9C8KBADG", 268 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 269 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 270 .model = "THGLF2G9D8KBADG", 271 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 272 {} 273 }; 274 275 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 276 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 277 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 278 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 279 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 280 static void ufshcd_hba_exit(struct ufs_hba *hba); 281 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 282 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 283 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 284 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 285 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 286 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 287 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 288 bool scale_up); 289 static irqreturn_t ufshcd_intr(int irq, void *__hba); 290 static int ufshcd_change_power_mode(struct ufs_hba *hba, 291 struct ufs_pa_layer_attr *pwr_mode); 292 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 293 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 294 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 295 struct ufs_vreg *vreg); 296 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 297 bool enable); 298 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 299 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 300 301 void ufshcd_enable_irq(struct ufs_hba *hba) 302 { 303 if (!hba->is_irq_enabled) { 304 enable_irq(hba->irq); 305 hba->is_irq_enabled = true; 306 } 307 } 308 EXPORT_SYMBOL_GPL(ufshcd_enable_irq); 309 310 void ufshcd_disable_irq(struct ufs_hba *hba) 311 { 312 if (hba->is_irq_enabled) { 313 disable_irq(hba->irq); 314 hba->is_irq_enabled = false; 315 } 316 } 317 EXPORT_SYMBOL_GPL(ufshcd_disable_irq); 318 319 static void ufshcd_configure_wb(struct ufs_hba *hba) 320 { 321 if (!ufshcd_is_wb_allowed(hba)) 322 return; 323 324 ufshcd_wb_toggle(hba, true); 325 326 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 327 328 if (ufshcd_is_wb_buf_flush_allowed(hba)) 329 ufshcd_wb_toggle_buf_flush(hba, true); 330 } 331 332 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba) 333 { 334 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt)) 335 scsi_unblock_requests(hba->host); 336 } 337 338 static void ufshcd_scsi_block_requests(struct ufs_hba *hba) 339 { 340 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1) 341 scsi_block_requests(hba->host); 342 } 343 344 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 345 enum ufs_trace_str_t str_t) 346 { 347 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 348 struct utp_upiu_header *header; 349 350 if (!trace_ufshcd_upiu_enabled()) 351 return; 352 353 if (str_t == UFS_CMD_SEND) 354 header = &rq->header; 355 else 356 header = &hba->lrb[tag].ucd_rsp_ptr->header; 357 358 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 359 UFS_TSF_CDB); 360 } 361 362 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 363 enum ufs_trace_str_t str_t, 364 struct utp_upiu_req *rq_rsp) 365 { 366 if (!trace_ufshcd_upiu_enabled()) 367 return; 368 369 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 370 &rq_rsp->qr, UFS_TSF_OSF); 371 } 372 373 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 374 enum ufs_trace_str_t str_t) 375 { 376 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 377 378 if (!trace_ufshcd_upiu_enabled()) 379 return; 380 381 if (str_t == UFS_TM_SEND) 382 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 383 &descp->upiu_req.req_header, 384 &descp->upiu_req.input_param1, 385 UFS_TSF_TM_INPUT); 386 else 387 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 388 &descp->upiu_rsp.rsp_header, 389 &descp->upiu_rsp.output_param1, 390 UFS_TSF_TM_OUTPUT); 391 } 392 393 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 394 const struct uic_command *ucmd, 395 enum ufs_trace_str_t str_t) 396 { 397 u32 cmd; 398 399 if (!trace_ufshcd_uic_command_enabled()) 400 return; 401 402 if (str_t == UFS_CMD_SEND) 403 cmd = ucmd->command; 404 else 405 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 406 407 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 408 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 409 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 410 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 411 } 412 413 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 414 enum ufs_trace_str_t str_t) 415 { 416 u64 lba = 0; 417 u8 opcode = 0, group_id = 0; 418 u32 doorbell = 0; 419 u32 intr; 420 int hwq_id = -1; 421 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 422 struct scsi_cmnd *cmd = lrbp->cmd; 423 struct request *rq = scsi_cmd_to_rq(cmd); 424 int transfer_len = -1; 425 426 if (!cmd) 427 return; 428 429 /* trace UPIU also */ 430 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 431 if (!trace_ufshcd_command_enabled()) 432 return; 433 434 opcode = cmd->cmnd[0]; 435 436 if (opcode == READ_10 || opcode == WRITE_10) { 437 /* 438 * Currently we only fully trace read(10) and write(10) commands 439 */ 440 transfer_len = 441 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 442 lba = scsi_get_lba(cmd); 443 if (opcode == WRITE_10) 444 group_id = lrbp->cmd->cmnd[6]; 445 } else if (opcode == UNMAP) { 446 /* 447 * The number of Bytes to be unmapped beginning with the lba. 448 */ 449 transfer_len = blk_rq_bytes(rq); 450 lba = scsi_get_lba(cmd); 451 } 452 453 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 454 455 if (is_mcq_enabled(hba)) { 456 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 457 458 hwq_id = hwq->id; 459 } else { 460 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 461 } 462 trace_ufshcd_command(cmd->device, str_t, tag, doorbell, hwq_id, 463 transfer_len, intr, lba, opcode, group_id); 464 } 465 466 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 467 { 468 struct ufs_clk_info *clki; 469 struct list_head *head = &hba->clk_list_head; 470 471 if (list_empty(head)) 472 return; 473 474 list_for_each_entry(clki, head, list) { 475 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 476 clki->max_freq) 477 dev_err(hba->dev, "clk: %s, rate: %u\n", 478 clki->name, clki->curr_freq); 479 } 480 } 481 482 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 483 const char *err_name) 484 { 485 int i; 486 bool found = false; 487 const struct ufs_event_hist *e; 488 489 if (id >= UFS_EVT_CNT) 490 return; 491 492 e = &hba->ufs_stats.event[id]; 493 494 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 495 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 496 497 if (e->tstamp[p] == 0) 498 continue; 499 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 500 e->val[p], div_u64(e->tstamp[p], 1000)); 501 found = true; 502 } 503 504 if (!found) 505 dev_err(hba->dev, "No record of %s\n", err_name); 506 else 507 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 508 } 509 510 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 511 { 512 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 513 514 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 515 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 516 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 517 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 518 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 519 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 520 "auto_hibern8_err"); 521 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 522 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 523 "link_startup_fail"); 524 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 525 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 526 "suspend_fail"); 527 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 528 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 529 "wlun suspend_fail"); 530 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 531 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 532 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 533 534 ufshcd_vops_dbg_register_dump(hba); 535 } 536 537 static 538 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 539 { 540 const struct ufshcd_lrb *lrbp; 541 int prdt_length; 542 543 lrbp = &hba->lrb[tag]; 544 545 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 546 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 547 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 548 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 549 dev_err(hba->dev, 550 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 551 tag, (u64)lrbp->utrd_dma_addr); 552 553 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 554 sizeof(struct utp_transfer_req_desc)); 555 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 556 (u64)lrbp->ucd_req_dma_addr); 557 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 558 sizeof(struct utp_upiu_req)); 559 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 560 (u64)lrbp->ucd_rsp_dma_addr); 561 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 562 sizeof(struct utp_upiu_rsp)); 563 564 prdt_length = le16_to_cpu( 565 lrbp->utr_descriptor_ptr->prd_table_length); 566 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 567 prdt_length /= ufshcd_sg_entry_size(hba); 568 569 dev_err(hba->dev, 570 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 571 tag, prdt_length, 572 (u64)lrbp->ucd_prdt_dma_addr); 573 574 if (pr_prdt) 575 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 576 ufshcd_sg_entry_size(hba) * prdt_length); 577 } 578 579 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 580 { 581 struct scsi_device *sdev = req->q->queuedata; 582 struct Scsi_Host *shost = sdev->host; 583 struct ufs_hba *hba = shost_priv(shost); 584 585 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 586 587 return true; 588 } 589 590 /** 591 * ufshcd_print_trs_all - print trs for all started requests. 592 * @hba: per-adapter instance. 593 * @pr_prdt: need to print prdt or not. 594 */ 595 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 596 { 597 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 598 } 599 600 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 601 { 602 int tag; 603 604 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 605 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 606 607 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 608 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 609 } 610 } 611 612 static void ufshcd_print_host_state(struct ufs_hba *hba) 613 { 614 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 615 616 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 617 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 618 hba->outstanding_reqs, hba->outstanding_tasks); 619 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 620 hba->saved_err, hba->saved_uic_err); 621 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 622 hba->curr_dev_pwr_mode, hba->uic_link_state); 623 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 624 hba->pm_op_in_progress, hba->is_sys_suspended); 625 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 626 hba->auto_bkops_enabled, hba->host->host_self_blocked); 627 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 628 dev_err(hba->dev, 629 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 630 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 631 hba->ufs_stats.hibern8_exit_cnt); 632 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 633 div_u64(hba->ufs_stats.last_intr_ts, 1000), 634 hba->ufs_stats.last_intr_status); 635 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 636 hba->eh_flags, hba->req_abort_count); 637 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 638 hba->ufs_version, hba->capabilities, hba->caps); 639 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 640 hba->dev_quirks); 641 if (sdev_ufs) 642 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 643 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 644 645 ufshcd_print_clk_freqs(hba); 646 } 647 648 /** 649 * ufshcd_print_pwr_info - print power params as saved in hba 650 * power info 651 * @hba: per-adapter instance 652 */ 653 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 654 { 655 static const char * const names[] = { 656 "INVALID MODE", 657 "FAST MODE", 658 "SLOW_MODE", 659 "INVALID MODE", 660 "FASTAUTO_MODE", 661 "SLOWAUTO_MODE", 662 "INVALID MODE", 663 }; 664 665 /* 666 * Using dev_dbg to avoid messages during runtime PM to avoid 667 * never-ending cycles of messages written back to storage by user space 668 * causing runtime resume, causing more messages and so on. 669 */ 670 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 671 __func__, 672 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 673 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 674 names[hba->pwr_info.pwr_rx], 675 names[hba->pwr_info.pwr_tx], 676 hba->pwr_info.hs_rate); 677 } 678 679 static void ufshcd_device_reset(struct ufs_hba *hba) 680 { 681 int err; 682 683 err = ufshcd_vops_device_reset(hba); 684 685 if (!err) { 686 ufshcd_set_ufs_dev_active(hba); 687 if (ufshcd_is_wb_allowed(hba)) { 688 hba->dev_info.wb_enabled = false; 689 hba->dev_info.wb_buf_flush_enabled = false; 690 } 691 if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 692 hba->dev_info.rtc_time_baseline = 0; 693 } 694 if (err != -EOPNOTSUPP) 695 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 696 } 697 698 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 699 { 700 if (!us) 701 return; 702 703 if (us < 10) 704 udelay(us); 705 else 706 usleep_range(us, us + tolerance); 707 } 708 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 709 710 /** 711 * ufshcd_wait_for_register - wait for register value to change 712 * @hba: per-adapter interface 713 * @reg: mmio register offset 714 * @mask: mask to apply to the read register value 715 * @val: value to wait for 716 * @interval_us: polling interval in microseconds 717 * @timeout_ms: timeout in milliseconds 718 * 719 * Return: -ETIMEDOUT on error, zero on success. 720 */ 721 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 722 u32 val, unsigned long interval_us, 723 unsigned long timeout_ms) 724 { 725 int err = 0; 726 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 727 728 /* ignore bits that we don't intend to wait on */ 729 val = val & mask; 730 731 while ((ufshcd_readl(hba, reg) & mask) != val) { 732 usleep_range(interval_us, interval_us + 50); 733 if (time_after(jiffies, timeout)) { 734 if ((ufshcd_readl(hba, reg) & mask) != val) 735 err = -ETIMEDOUT; 736 break; 737 } 738 } 739 740 return err; 741 } 742 743 /** 744 * ufshcd_get_intr_mask - Get the interrupt bit mask 745 * @hba: Pointer to adapter instance 746 * 747 * Return: interrupt bit mask per version 748 */ 749 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 750 { 751 if (hba->ufs_version <= ufshci_version(2, 0)) 752 return INTERRUPT_MASK_ALL_VER_11; 753 754 return INTERRUPT_MASK_ALL_VER_21; 755 } 756 757 /** 758 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 759 * @hba: Pointer to adapter instance 760 * 761 * Return: UFSHCI version supported by the controller 762 */ 763 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 764 { 765 u32 ufshci_ver; 766 767 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 768 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 769 else 770 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 771 772 /* 773 * UFSHCI v1.x uses a different version scheme, in order 774 * to allow the use of comparisons with the ufshci_version 775 * function, we convert it to the same scheme as ufs 2.0+. 776 */ 777 if (ufshci_ver & 0x00010000) 778 return ufshci_version(1, ufshci_ver & 0x00000100); 779 780 return ufshci_ver; 781 } 782 783 /** 784 * ufshcd_is_device_present - Check if any device connected to 785 * the host controller 786 * @hba: pointer to adapter instance 787 * 788 * Return: true if device present, false if no device detected 789 */ 790 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 791 { 792 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 793 } 794 795 /** 796 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 797 * @lrbp: pointer to local command reference block 798 * @cqe: pointer to the completion queue entry 799 * 800 * This function is used to get the OCS field from UTRD 801 * 802 * Return: the OCS field in the UTRD. 803 */ 804 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 805 struct cq_entry *cqe) 806 { 807 if (cqe) 808 return le32_to_cpu(cqe->status) & MASK_OCS; 809 810 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 811 } 812 813 /** 814 * ufshcd_utrl_clear() - Clear requests from the controller request list. 815 * @hba: per adapter instance 816 * @mask: mask with one bit set for each request to be cleared 817 */ 818 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 819 { 820 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 821 mask = ~mask; 822 /* 823 * From the UFSHCI specification: "UTP Transfer Request List CLear 824 * Register (UTRLCLR): This field is bit significant. Each bit 825 * corresponds to a slot in the UTP Transfer Request List, where bit 0 826 * corresponds to request slot 0. A bit in this field is set to ‘0’ 827 * by host software to indicate to the host controller that a transfer 828 * request slot is cleared. The host controller 829 * shall free up any resources associated to the request slot 830 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 831 * host software indicates no change to request slots by setting the 832 * associated bits in this field to ‘1’. Bits in this field shall only 833 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 834 */ 835 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 836 } 837 838 /** 839 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 840 * @hba: per adapter instance 841 * @pos: position of the bit to be cleared 842 */ 843 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 844 { 845 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 846 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 847 else 848 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 849 } 850 851 /** 852 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 853 * @reg: Register value of host controller status 854 * 855 * Return: 0 on success; a positive value if failed. 856 */ 857 static inline int ufshcd_get_lists_status(u32 reg) 858 { 859 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 860 } 861 862 /** 863 * ufshcd_get_uic_cmd_result - Get the UIC command result 864 * @hba: Pointer to adapter instance 865 * 866 * This function gets the result of UIC command completion 867 * 868 * Return: 0 on success; non-zero value on error. 869 */ 870 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 871 { 872 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 873 MASK_UIC_COMMAND_RESULT; 874 } 875 876 /** 877 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 878 * @hba: Pointer to adapter instance 879 * 880 * This function gets UIC command argument3 881 * 882 * Return: 0 on success; non-zero value on error. 883 */ 884 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 885 { 886 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 887 } 888 889 /** 890 * ufshcd_get_req_rsp - returns the TR response transaction type 891 * @ucd_rsp_ptr: pointer to response UPIU 892 * 893 * Return: UPIU type. 894 */ 895 static inline enum upiu_response_transaction 896 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 897 { 898 return ucd_rsp_ptr->header.transaction_code; 899 } 900 901 /** 902 * ufshcd_is_exception_event - Check if the device raised an exception event 903 * @ucd_rsp_ptr: pointer to response UPIU 904 * 905 * The function checks if the device raised an exception event indicated in 906 * the Device Information field of response UPIU. 907 * 908 * Return: true if exception is raised, false otherwise. 909 */ 910 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 911 { 912 return ucd_rsp_ptr->header.device_information & 1; 913 } 914 915 /** 916 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 917 * @hba: per adapter instance 918 */ 919 static inline void 920 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 921 { 922 ufshcd_writel(hba, INT_AGGR_ENABLE | 923 INT_AGGR_COUNTER_AND_TIMER_RESET, 924 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 925 } 926 927 /** 928 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 929 * @hba: per adapter instance 930 * @cnt: Interrupt aggregation counter threshold 931 * @tmout: Interrupt aggregation timeout value 932 */ 933 static inline void 934 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 935 { 936 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 937 INT_AGGR_COUNTER_THLD_VAL(cnt) | 938 INT_AGGR_TIMEOUT_VAL(tmout), 939 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 940 } 941 942 /** 943 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 944 * @hba: per adapter instance 945 */ 946 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 947 { 948 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 949 } 950 951 /** 952 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 953 * When run-stop registers are set to 1, it indicates the 954 * host controller that it can process the requests 955 * @hba: per adapter instance 956 */ 957 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 958 { 959 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 960 REG_UTP_TASK_REQ_LIST_RUN_STOP); 961 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 962 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 963 } 964 965 /** 966 * ufshcd_hba_start - Start controller initialization sequence 967 * @hba: per adapter instance 968 */ 969 static inline void ufshcd_hba_start(struct ufs_hba *hba) 970 { 971 u32 val = CONTROLLER_ENABLE; 972 973 if (ufshcd_crypto_enable(hba)) 974 val |= CRYPTO_GENERAL_ENABLE; 975 976 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 977 } 978 979 /** 980 * ufshcd_is_hba_active - Get controller state 981 * @hba: per adapter instance 982 * 983 * Return: true if and only if the controller is active. 984 */ 985 bool ufshcd_is_hba_active(struct ufs_hba *hba) 986 { 987 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 988 } 989 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 990 991 /** 992 * ufshcd_pm_qos_init - initialize PM QoS request 993 * @hba: per adapter instance 994 */ 995 void ufshcd_pm_qos_init(struct ufs_hba *hba) 996 { 997 998 if (hba->pm_qos_enabled) 999 return; 1000 1001 cpu_latency_qos_add_request(&hba->pm_qos_req, PM_QOS_DEFAULT_VALUE); 1002 1003 if (cpu_latency_qos_request_active(&hba->pm_qos_req)) 1004 hba->pm_qos_enabled = true; 1005 } 1006 1007 /** 1008 * ufshcd_pm_qos_exit - remove request from PM QoS 1009 * @hba: per adapter instance 1010 */ 1011 void ufshcd_pm_qos_exit(struct ufs_hba *hba) 1012 { 1013 if (!hba->pm_qos_enabled) 1014 return; 1015 1016 cpu_latency_qos_remove_request(&hba->pm_qos_req); 1017 hba->pm_qos_enabled = false; 1018 } 1019 1020 /** 1021 * ufshcd_pm_qos_update - update PM QoS request 1022 * @hba: per adapter instance 1023 * @on: If True, vote for perf PM QoS mode otherwise power save mode 1024 */ 1025 static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) 1026 { 1027 if (!hba->pm_qos_enabled) 1028 return; 1029 1030 cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE); 1031 } 1032 1033 /** 1034 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1035 * @hba: per adapter instance 1036 * @scale_up: If True, set max possible frequency othewise set low frequency 1037 * 1038 * Return: 0 if successful; < 0 upon failure. 1039 */ 1040 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1041 { 1042 int ret = 0; 1043 struct ufs_clk_info *clki; 1044 struct list_head *head = &hba->clk_list_head; 1045 1046 if (list_empty(head)) 1047 goto out; 1048 1049 list_for_each_entry(clki, head, list) { 1050 if (!IS_ERR_OR_NULL(clki->clk)) { 1051 if (scale_up && clki->max_freq) { 1052 if (clki->curr_freq == clki->max_freq) 1053 continue; 1054 1055 ret = clk_set_rate(clki->clk, clki->max_freq); 1056 if (ret) { 1057 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1058 __func__, clki->name, 1059 clki->max_freq, ret); 1060 break; 1061 } 1062 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1063 "scaled up", clki->name, 1064 clki->curr_freq, 1065 clki->max_freq); 1066 1067 clki->curr_freq = clki->max_freq; 1068 1069 } else if (!scale_up && clki->min_freq) { 1070 if (clki->curr_freq == clki->min_freq) 1071 continue; 1072 1073 ret = clk_set_rate(clki->clk, clki->min_freq); 1074 if (ret) { 1075 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1076 __func__, clki->name, 1077 clki->min_freq, ret); 1078 break; 1079 } 1080 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1081 "scaled down", clki->name, 1082 clki->curr_freq, 1083 clki->min_freq); 1084 clki->curr_freq = clki->min_freq; 1085 } 1086 } 1087 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1088 clki->name, clk_get_rate(clki->clk)); 1089 } 1090 1091 out: 1092 return ret; 1093 } 1094 1095 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1096 struct dev_pm_opp *opp, void *data, 1097 bool scaling_down) 1098 { 1099 struct ufs_hba *hba = dev_get_drvdata(dev); 1100 struct list_head *head = &hba->clk_list_head; 1101 struct ufs_clk_info *clki; 1102 unsigned long freq; 1103 u8 idx = 0; 1104 int ret; 1105 1106 list_for_each_entry(clki, head, list) { 1107 if (!IS_ERR_OR_NULL(clki->clk)) { 1108 freq = dev_pm_opp_get_freq_indexed(opp, idx++); 1109 1110 /* Do not set rate for clocks having frequency as 0 */ 1111 if (!freq) 1112 continue; 1113 1114 ret = clk_set_rate(clki->clk, freq); 1115 if (ret) { 1116 dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n", 1117 __func__, clki->name, freq, ret); 1118 return ret; 1119 } 1120 1121 trace_ufshcd_clk_scaling(dev_name(dev), 1122 (scaling_down ? "scaled down" : "scaled up"), 1123 clki->name, hba->clk_scaling.target_freq, freq); 1124 } 1125 } 1126 1127 return 0; 1128 } 1129 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks); 1130 1131 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) 1132 { 1133 struct dev_pm_opp *opp; 1134 int ret; 1135 1136 opp = dev_pm_opp_find_freq_floor_indexed(hba->dev, 1137 &freq, 0); 1138 if (IS_ERR(opp)) 1139 return PTR_ERR(opp); 1140 1141 ret = dev_pm_opp_set_opp(hba->dev, opp); 1142 dev_pm_opp_put(opp); 1143 1144 return ret; 1145 } 1146 1147 /** 1148 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1149 * @hba: per adapter instance 1150 * @freq: frequency to scale 1151 * @scale_up: True if scaling up and false if scaling down 1152 * 1153 * Return: 0 if successful; < 0 upon failure. 1154 */ 1155 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 1156 bool scale_up) 1157 { 1158 int ret = 0; 1159 ktime_t start = ktime_get(); 1160 1161 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1162 if (ret) 1163 goto out; 1164 1165 if (hba->use_pm_opp) 1166 ret = ufshcd_opp_set_rate(hba, freq); 1167 else 1168 ret = ufshcd_set_clk_freq(hba, scale_up); 1169 if (ret) 1170 goto out; 1171 1172 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1173 if (ret) { 1174 if (hba->use_pm_opp) 1175 ufshcd_opp_set_rate(hba, 1176 hba->devfreq->previous_freq); 1177 else 1178 ufshcd_set_clk_freq(hba, !scale_up); 1179 goto out; 1180 } 1181 1182 ufshcd_pm_qos_update(hba, scale_up); 1183 1184 out: 1185 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1186 (scale_up ? "up" : "down"), 1187 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1188 return ret; 1189 } 1190 1191 /** 1192 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1193 * @hba: per adapter instance 1194 * @freq: frequency to scale 1195 * @scale_up: True if scaling up and false if scaling down 1196 * 1197 * Return: true if scaling is required, false otherwise. 1198 */ 1199 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1200 unsigned long freq, bool scale_up) 1201 { 1202 struct ufs_clk_info *clki; 1203 struct list_head *head = &hba->clk_list_head; 1204 1205 if (list_empty(head)) 1206 return false; 1207 1208 if (hba->use_pm_opp) 1209 return freq != hba->clk_scaling.target_freq; 1210 1211 list_for_each_entry(clki, head, list) { 1212 if (!IS_ERR_OR_NULL(clki->clk)) { 1213 if (scale_up && clki->max_freq) { 1214 if (clki->curr_freq == clki->max_freq) 1215 continue; 1216 return true; 1217 } else if (!scale_up && clki->min_freq) { 1218 if (clki->curr_freq == clki->min_freq) 1219 continue; 1220 return true; 1221 } 1222 } 1223 } 1224 1225 return false; 1226 } 1227 1228 /* 1229 * Determine the number of pending commands by counting the bits in the SCSI 1230 * device budget maps. This approach has been selected because a bit is set in 1231 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1232 * flag. The host_self_blocked flag can be modified by calling 1233 * scsi_block_requests() or scsi_unblock_requests(). 1234 */ 1235 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1236 { 1237 const struct scsi_device *sdev; 1238 u32 pending = 0; 1239 1240 lockdep_assert_held(hba->host->host_lock); 1241 __shost_for_each_device(sdev, hba->host) 1242 pending += sbitmap_weight(&sdev->budget_map); 1243 1244 return pending; 1245 } 1246 1247 /* 1248 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1249 * has expired. 1250 * 1251 * Return: 0 upon success; -EBUSY upon timeout. 1252 */ 1253 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1254 u64 wait_timeout_us) 1255 { 1256 unsigned long flags; 1257 int ret = 0; 1258 u32 tm_doorbell; 1259 u32 tr_pending; 1260 bool timeout = false, do_last_check = false; 1261 ktime_t start; 1262 1263 ufshcd_hold(hba); 1264 spin_lock_irqsave(hba->host->host_lock, flags); 1265 /* 1266 * Wait for all the outstanding tasks/transfer requests. 1267 * Verify by checking the doorbell registers are clear. 1268 */ 1269 start = ktime_get(); 1270 do { 1271 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1272 ret = -EBUSY; 1273 goto out; 1274 } 1275 1276 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1277 tr_pending = ufshcd_pending_cmds(hba); 1278 if (!tm_doorbell && !tr_pending) { 1279 timeout = false; 1280 break; 1281 } else if (do_last_check) { 1282 break; 1283 } 1284 1285 spin_unlock_irqrestore(hba->host->host_lock, flags); 1286 io_schedule_timeout(msecs_to_jiffies(20)); 1287 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1288 wait_timeout_us) { 1289 timeout = true; 1290 /* 1291 * We might have scheduled out for long time so make 1292 * sure to check if doorbells are cleared by this time 1293 * or not. 1294 */ 1295 do_last_check = true; 1296 } 1297 spin_lock_irqsave(hba->host->host_lock, flags); 1298 } while (tm_doorbell || tr_pending); 1299 1300 if (timeout) { 1301 dev_err(hba->dev, 1302 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1303 __func__, tm_doorbell, tr_pending); 1304 ret = -EBUSY; 1305 } 1306 out: 1307 spin_unlock_irqrestore(hba->host->host_lock, flags); 1308 ufshcd_release(hba); 1309 return ret; 1310 } 1311 1312 /** 1313 * ufshcd_scale_gear - scale up/down UFS gear 1314 * @hba: per adapter instance 1315 * @scale_up: True for scaling up gear and false for scaling down 1316 * 1317 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1318 * non-zero for any other errors. 1319 */ 1320 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1321 { 1322 int ret = 0; 1323 struct ufs_pa_layer_attr new_pwr_info; 1324 1325 if (scale_up) { 1326 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1327 sizeof(struct ufs_pa_layer_attr)); 1328 } else { 1329 memcpy(&new_pwr_info, &hba->pwr_info, 1330 sizeof(struct ufs_pa_layer_attr)); 1331 1332 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1333 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1334 /* save the current power mode */ 1335 memcpy(&hba->clk_scaling.saved_pwr_info, 1336 &hba->pwr_info, 1337 sizeof(struct ufs_pa_layer_attr)); 1338 1339 /* scale down gear */ 1340 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1341 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1342 } 1343 } 1344 1345 /* check if the power mode needs to be changed or not? */ 1346 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1347 if (ret) 1348 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1349 __func__, ret, 1350 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1351 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1352 1353 return ret; 1354 } 1355 1356 /* 1357 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1358 * has expired. 1359 * 1360 * Return: 0 upon success; -EBUSY upon timeout. 1361 */ 1362 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1363 { 1364 int ret = 0; 1365 /* 1366 * make sure that there are no outstanding requests when 1367 * clock scaling is in progress 1368 */ 1369 ufshcd_scsi_block_requests(hba); 1370 mutex_lock(&hba->wb_mutex); 1371 down_write(&hba->clk_scaling_lock); 1372 1373 if (!hba->clk_scaling.is_allowed || 1374 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1375 ret = -EBUSY; 1376 up_write(&hba->clk_scaling_lock); 1377 mutex_unlock(&hba->wb_mutex); 1378 ufshcd_scsi_unblock_requests(hba); 1379 goto out; 1380 } 1381 1382 /* let's not get into low power until clock scaling is completed */ 1383 ufshcd_hold(hba); 1384 1385 out: 1386 return ret; 1387 } 1388 1389 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1390 { 1391 up_write(&hba->clk_scaling_lock); 1392 1393 /* Enable Write Booster if we have scaled up else disable it */ 1394 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1395 ufshcd_wb_toggle(hba, scale_up); 1396 1397 mutex_unlock(&hba->wb_mutex); 1398 1399 ufshcd_scsi_unblock_requests(hba); 1400 ufshcd_release(hba); 1401 } 1402 1403 /** 1404 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1405 * @hba: per adapter instance 1406 * @freq: frequency to scale 1407 * @scale_up: True for scaling up and false for scalin down 1408 * 1409 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1410 * for any other errors. 1411 */ 1412 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, 1413 bool scale_up) 1414 { 1415 int ret = 0; 1416 1417 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1418 if (ret) 1419 return ret; 1420 1421 /* scale down the gear before scaling down clocks */ 1422 if (!scale_up) { 1423 ret = ufshcd_scale_gear(hba, false); 1424 if (ret) 1425 goto out_unprepare; 1426 } 1427 1428 ret = ufshcd_scale_clks(hba, freq, scale_up); 1429 if (ret) { 1430 if (!scale_up) 1431 ufshcd_scale_gear(hba, true); 1432 goto out_unprepare; 1433 } 1434 1435 /* scale up the gear after scaling up clocks */ 1436 if (scale_up) { 1437 ret = ufshcd_scale_gear(hba, true); 1438 if (ret) { 1439 ufshcd_scale_clks(hba, hba->devfreq->previous_freq, 1440 false); 1441 goto out_unprepare; 1442 } 1443 } 1444 1445 out_unprepare: 1446 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1447 return ret; 1448 } 1449 1450 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1451 { 1452 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1453 clk_scaling.suspend_work); 1454 unsigned long irq_flags; 1455 1456 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1457 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1458 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1459 return; 1460 } 1461 hba->clk_scaling.is_suspended = true; 1462 hba->clk_scaling.window_start_t = 0; 1463 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1464 1465 devfreq_suspend_device(hba->devfreq); 1466 } 1467 1468 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1469 { 1470 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1471 clk_scaling.resume_work); 1472 unsigned long irq_flags; 1473 1474 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1475 if (!hba->clk_scaling.is_suspended) { 1476 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1477 return; 1478 } 1479 hba->clk_scaling.is_suspended = false; 1480 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1481 1482 devfreq_resume_device(hba->devfreq); 1483 } 1484 1485 static int ufshcd_devfreq_target(struct device *dev, 1486 unsigned long *freq, u32 flags) 1487 { 1488 int ret = 0; 1489 struct ufs_hba *hba = dev_get_drvdata(dev); 1490 ktime_t start; 1491 bool scale_up = false, sched_clk_scaling_suspend_work = false; 1492 struct list_head *clk_list = &hba->clk_list_head; 1493 struct ufs_clk_info *clki; 1494 unsigned long irq_flags; 1495 1496 if (!ufshcd_is_clkscaling_supported(hba)) 1497 return -EINVAL; 1498 1499 if (hba->use_pm_opp) { 1500 struct dev_pm_opp *opp; 1501 1502 /* Get the recommended frequency from OPP framework */ 1503 opp = devfreq_recommended_opp(dev, freq, flags); 1504 if (IS_ERR(opp)) 1505 return PTR_ERR(opp); 1506 1507 dev_pm_opp_put(opp); 1508 } else { 1509 /* Override with the closest supported frequency */ 1510 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, 1511 list); 1512 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1513 } 1514 1515 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1516 if (ufshcd_eh_in_progress(hba)) { 1517 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1518 return 0; 1519 } 1520 1521 /* Skip scaling clock when clock scaling is suspended */ 1522 if (hba->clk_scaling.is_suspended) { 1523 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1524 dev_warn(hba->dev, "clock scaling is suspended, skip"); 1525 return 0; 1526 } 1527 1528 if (!hba->clk_scaling.active_reqs) 1529 sched_clk_scaling_suspend_work = true; 1530 1531 if (list_empty(clk_list)) { 1532 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1533 goto out; 1534 } 1535 1536 /* Decide based on the target or rounded-off frequency and update */ 1537 if (hba->use_pm_opp) 1538 scale_up = *freq > hba->clk_scaling.target_freq; 1539 else 1540 scale_up = *freq == clki->max_freq; 1541 1542 if (!hba->use_pm_opp && !scale_up) 1543 *freq = clki->min_freq; 1544 1545 /* Update the frequency */ 1546 if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) { 1547 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1548 ret = 0; 1549 goto out; /* no state change required */ 1550 } 1551 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1552 1553 start = ktime_get(); 1554 ret = ufshcd_devfreq_scale(hba, *freq, scale_up); 1555 if (!ret) 1556 hba->clk_scaling.target_freq = *freq; 1557 1558 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1559 (scale_up ? "up" : "down"), 1560 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1561 1562 out: 1563 if (sched_clk_scaling_suspend_work && !scale_up) 1564 queue_work(hba->clk_scaling.workq, 1565 &hba->clk_scaling.suspend_work); 1566 1567 return ret; 1568 } 1569 1570 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1571 struct devfreq_dev_status *stat) 1572 { 1573 struct ufs_hba *hba = dev_get_drvdata(dev); 1574 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1575 unsigned long flags; 1576 ktime_t curr_t; 1577 1578 if (!ufshcd_is_clkscaling_supported(hba)) 1579 return -EINVAL; 1580 1581 memset(stat, 0, sizeof(*stat)); 1582 1583 spin_lock_irqsave(hba->host->host_lock, flags); 1584 curr_t = ktime_get(); 1585 if (!scaling->window_start_t) 1586 goto start_window; 1587 1588 /* 1589 * If current frequency is 0, then the ondemand governor considers 1590 * there's no initial frequency set. And it always requests to set 1591 * to max. frequency. 1592 */ 1593 if (hba->use_pm_opp) { 1594 stat->current_frequency = hba->clk_scaling.target_freq; 1595 } else { 1596 struct list_head *clk_list = &hba->clk_list_head; 1597 struct ufs_clk_info *clki; 1598 1599 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1600 stat->current_frequency = clki->curr_freq; 1601 } 1602 1603 if (scaling->is_busy_started) 1604 scaling->tot_busy_t += ktime_us_delta(curr_t, 1605 scaling->busy_start_t); 1606 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1607 stat->busy_time = scaling->tot_busy_t; 1608 start_window: 1609 scaling->window_start_t = curr_t; 1610 scaling->tot_busy_t = 0; 1611 1612 if (scaling->active_reqs) { 1613 scaling->busy_start_t = curr_t; 1614 scaling->is_busy_started = true; 1615 } else { 1616 scaling->busy_start_t = 0; 1617 scaling->is_busy_started = false; 1618 } 1619 spin_unlock_irqrestore(hba->host->host_lock, flags); 1620 return 0; 1621 } 1622 1623 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1624 { 1625 struct list_head *clk_list = &hba->clk_list_head; 1626 struct ufs_clk_info *clki; 1627 struct devfreq *devfreq; 1628 int ret; 1629 1630 /* Skip devfreq if we don't have any clocks in the list */ 1631 if (list_empty(clk_list)) 1632 return 0; 1633 1634 if (!hba->use_pm_opp) { 1635 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1636 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1637 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1638 } 1639 1640 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1641 &hba->vps->ondemand_data); 1642 devfreq = devfreq_add_device(hba->dev, 1643 &hba->vps->devfreq_profile, 1644 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1645 &hba->vps->ondemand_data); 1646 if (IS_ERR(devfreq)) { 1647 ret = PTR_ERR(devfreq); 1648 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1649 1650 if (!hba->use_pm_opp) { 1651 dev_pm_opp_remove(hba->dev, clki->min_freq); 1652 dev_pm_opp_remove(hba->dev, clki->max_freq); 1653 } 1654 return ret; 1655 } 1656 1657 hba->devfreq = devfreq; 1658 1659 return 0; 1660 } 1661 1662 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1663 { 1664 struct list_head *clk_list = &hba->clk_list_head; 1665 1666 if (!hba->devfreq) 1667 return; 1668 1669 devfreq_remove_device(hba->devfreq); 1670 hba->devfreq = NULL; 1671 1672 if (!hba->use_pm_opp) { 1673 struct ufs_clk_info *clki; 1674 1675 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1676 dev_pm_opp_remove(hba->dev, clki->min_freq); 1677 dev_pm_opp_remove(hba->dev, clki->max_freq); 1678 } 1679 } 1680 1681 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1682 { 1683 unsigned long flags; 1684 bool suspend = false; 1685 1686 cancel_work_sync(&hba->clk_scaling.suspend_work); 1687 cancel_work_sync(&hba->clk_scaling.resume_work); 1688 1689 spin_lock_irqsave(hba->host->host_lock, flags); 1690 if (!hba->clk_scaling.is_suspended) { 1691 suspend = true; 1692 hba->clk_scaling.is_suspended = true; 1693 hba->clk_scaling.window_start_t = 0; 1694 } 1695 spin_unlock_irqrestore(hba->host->host_lock, flags); 1696 1697 if (suspend) 1698 devfreq_suspend_device(hba->devfreq); 1699 } 1700 1701 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1702 { 1703 unsigned long flags; 1704 bool resume = false; 1705 1706 spin_lock_irqsave(hba->host->host_lock, flags); 1707 if (hba->clk_scaling.is_suspended) { 1708 resume = true; 1709 hba->clk_scaling.is_suspended = false; 1710 } 1711 spin_unlock_irqrestore(hba->host->host_lock, flags); 1712 1713 if (resume) 1714 devfreq_resume_device(hba->devfreq); 1715 } 1716 1717 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1718 struct device_attribute *attr, char *buf) 1719 { 1720 struct ufs_hba *hba = dev_get_drvdata(dev); 1721 1722 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1723 } 1724 1725 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1726 struct device_attribute *attr, const char *buf, size_t count) 1727 { 1728 struct ufs_hba *hba = dev_get_drvdata(dev); 1729 u32 value; 1730 int err = 0; 1731 1732 if (kstrtou32(buf, 0, &value)) 1733 return -EINVAL; 1734 1735 down(&hba->host_sem); 1736 if (!ufshcd_is_user_access_allowed(hba)) { 1737 err = -EBUSY; 1738 goto out; 1739 } 1740 1741 value = !!value; 1742 if (value == hba->clk_scaling.is_enabled) 1743 goto out; 1744 1745 ufshcd_rpm_get_sync(hba); 1746 ufshcd_hold(hba); 1747 1748 hba->clk_scaling.is_enabled = value; 1749 1750 if (value) { 1751 ufshcd_resume_clkscaling(hba); 1752 } else { 1753 ufshcd_suspend_clkscaling(hba); 1754 err = ufshcd_devfreq_scale(hba, ULONG_MAX, true); 1755 if (err) 1756 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1757 __func__, err); 1758 } 1759 1760 ufshcd_release(hba); 1761 ufshcd_rpm_put_sync(hba); 1762 out: 1763 up(&hba->host_sem); 1764 return err ? err : count; 1765 } 1766 1767 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1768 { 1769 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1770 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1771 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1772 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1773 hba->clk_scaling.enable_attr.attr.mode = 0644; 1774 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1775 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1776 } 1777 1778 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1779 { 1780 if (hba->clk_scaling.enable_attr.attr.name) 1781 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1782 } 1783 1784 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1785 { 1786 char wq_name[sizeof("ufs_clkscaling_00")]; 1787 1788 if (!ufshcd_is_clkscaling_supported(hba)) 1789 return; 1790 1791 if (!hba->clk_scaling.min_gear) 1792 hba->clk_scaling.min_gear = UFS_HS_G1; 1793 1794 INIT_WORK(&hba->clk_scaling.suspend_work, 1795 ufshcd_clk_scaling_suspend_work); 1796 INIT_WORK(&hba->clk_scaling.resume_work, 1797 ufshcd_clk_scaling_resume_work); 1798 1799 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d", 1800 hba->host->host_no); 1801 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name); 1802 1803 hba->clk_scaling.is_initialized = true; 1804 } 1805 1806 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1807 { 1808 if (!hba->clk_scaling.is_initialized) 1809 return; 1810 1811 ufshcd_remove_clk_scaling_sysfs(hba); 1812 destroy_workqueue(hba->clk_scaling.workq); 1813 ufshcd_devfreq_remove(hba); 1814 hba->clk_scaling.is_initialized = false; 1815 } 1816 1817 static void ufshcd_ungate_work(struct work_struct *work) 1818 { 1819 int ret; 1820 unsigned long flags; 1821 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1822 clk_gating.ungate_work); 1823 1824 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1825 1826 spin_lock_irqsave(hba->host->host_lock, flags); 1827 if (hba->clk_gating.state == CLKS_ON) { 1828 spin_unlock_irqrestore(hba->host->host_lock, flags); 1829 return; 1830 } 1831 1832 spin_unlock_irqrestore(hba->host->host_lock, flags); 1833 ufshcd_hba_vreg_set_hpm(hba); 1834 ufshcd_setup_clocks(hba, true); 1835 1836 ufshcd_enable_irq(hba); 1837 1838 /* Exit from hibern8 */ 1839 if (ufshcd_can_hibern8_during_gating(hba)) { 1840 /* Prevent gating in this path */ 1841 hba->clk_gating.is_suspended = true; 1842 if (ufshcd_is_link_hibern8(hba)) { 1843 ret = ufshcd_uic_hibern8_exit(hba); 1844 if (ret) 1845 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1846 __func__, ret); 1847 else 1848 ufshcd_set_link_active(hba); 1849 } 1850 hba->clk_gating.is_suspended = false; 1851 } 1852 } 1853 1854 /** 1855 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1856 * Also, exit from hibern8 mode and set the link as active. 1857 * @hba: per adapter instance 1858 */ 1859 void ufshcd_hold(struct ufs_hba *hba) 1860 { 1861 bool flush_result; 1862 unsigned long flags; 1863 1864 if (!ufshcd_is_clkgating_allowed(hba) || 1865 !hba->clk_gating.is_initialized) 1866 return; 1867 spin_lock_irqsave(hba->host->host_lock, flags); 1868 hba->clk_gating.active_reqs++; 1869 1870 start: 1871 switch (hba->clk_gating.state) { 1872 case CLKS_ON: 1873 /* 1874 * Wait for the ungate work to complete if in progress. 1875 * Though the clocks may be in ON state, the link could 1876 * still be in hibner8 state if hibern8 is allowed 1877 * during clock gating. 1878 * Make sure we exit hibern8 state also in addition to 1879 * clocks being ON. 1880 */ 1881 if (ufshcd_can_hibern8_during_gating(hba) && 1882 ufshcd_is_link_hibern8(hba)) { 1883 spin_unlock_irqrestore(hba->host->host_lock, flags); 1884 flush_result = flush_work(&hba->clk_gating.ungate_work); 1885 if (hba->clk_gating.is_suspended && !flush_result) 1886 return; 1887 spin_lock_irqsave(hba->host->host_lock, flags); 1888 goto start; 1889 } 1890 break; 1891 case REQ_CLKS_OFF: 1892 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1893 hba->clk_gating.state = CLKS_ON; 1894 trace_ufshcd_clk_gating(dev_name(hba->dev), 1895 hba->clk_gating.state); 1896 break; 1897 } 1898 /* 1899 * If we are here, it means gating work is either done or 1900 * currently running. Hence, fall through to cancel gating 1901 * work and to enable clocks. 1902 */ 1903 fallthrough; 1904 case CLKS_OFF: 1905 hba->clk_gating.state = REQ_CLKS_ON; 1906 trace_ufshcd_clk_gating(dev_name(hba->dev), 1907 hba->clk_gating.state); 1908 queue_work(hba->clk_gating.clk_gating_workq, 1909 &hba->clk_gating.ungate_work); 1910 /* 1911 * fall through to check if we should wait for this 1912 * work to be done or not. 1913 */ 1914 fallthrough; 1915 case REQ_CLKS_ON: 1916 spin_unlock_irqrestore(hba->host->host_lock, flags); 1917 flush_work(&hba->clk_gating.ungate_work); 1918 /* Make sure state is CLKS_ON before returning */ 1919 spin_lock_irqsave(hba->host->host_lock, flags); 1920 goto start; 1921 default: 1922 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1923 __func__, hba->clk_gating.state); 1924 break; 1925 } 1926 spin_unlock_irqrestore(hba->host->host_lock, flags); 1927 } 1928 EXPORT_SYMBOL_GPL(ufshcd_hold); 1929 1930 static void ufshcd_gate_work(struct work_struct *work) 1931 { 1932 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1933 clk_gating.gate_work.work); 1934 unsigned long flags; 1935 int ret; 1936 1937 spin_lock_irqsave(hba->host->host_lock, flags); 1938 /* 1939 * In case you are here to cancel this work the gating state 1940 * would be marked as REQ_CLKS_ON. In this case save time by 1941 * skipping the gating work and exit after changing the clock 1942 * state to CLKS_ON. 1943 */ 1944 if (hba->clk_gating.is_suspended || 1945 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1946 hba->clk_gating.state = CLKS_ON; 1947 trace_ufshcd_clk_gating(dev_name(hba->dev), 1948 hba->clk_gating.state); 1949 goto rel_lock; 1950 } 1951 1952 if (ufshcd_is_ufs_dev_busy(hba) || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) 1953 goto rel_lock; 1954 1955 spin_unlock_irqrestore(hba->host->host_lock, flags); 1956 1957 /* put the link into hibern8 mode before turning off clocks */ 1958 if (ufshcd_can_hibern8_during_gating(hba)) { 1959 ret = ufshcd_uic_hibern8_enter(hba); 1960 if (ret) { 1961 hba->clk_gating.state = CLKS_ON; 1962 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1963 __func__, ret); 1964 trace_ufshcd_clk_gating(dev_name(hba->dev), 1965 hba->clk_gating.state); 1966 goto out; 1967 } 1968 ufshcd_set_link_hibern8(hba); 1969 } 1970 1971 ufshcd_disable_irq(hba); 1972 1973 ufshcd_setup_clocks(hba, false); 1974 1975 /* Put the host controller in low power mode if possible */ 1976 ufshcd_hba_vreg_set_lpm(hba); 1977 /* 1978 * In case you are here to cancel this work the gating state 1979 * would be marked as REQ_CLKS_ON. In this case keep the state 1980 * as REQ_CLKS_ON which would anyway imply that clocks are off 1981 * and a request to turn them on is pending. By doing this way, 1982 * we keep the state machine in tact and this would ultimately 1983 * prevent from doing cancel work multiple times when there are 1984 * new requests arriving before the current cancel work is done. 1985 */ 1986 spin_lock_irqsave(hba->host->host_lock, flags); 1987 if (hba->clk_gating.state == REQ_CLKS_OFF) { 1988 hba->clk_gating.state = CLKS_OFF; 1989 trace_ufshcd_clk_gating(dev_name(hba->dev), 1990 hba->clk_gating.state); 1991 } 1992 rel_lock: 1993 spin_unlock_irqrestore(hba->host->host_lock, flags); 1994 out: 1995 return; 1996 } 1997 1998 /* host lock must be held before calling this variant */ 1999 static void __ufshcd_release(struct ufs_hba *hba) 2000 { 2001 if (!ufshcd_is_clkgating_allowed(hba)) 2002 return; 2003 2004 hba->clk_gating.active_reqs--; 2005 2006 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 2007 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 2008 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 2009 hba->active_uic_cmd || hba->uic_async_done || 2010 hba->clk_gating.state == CLKS_OFF) 2011 return; 2012 2013 hba->clk_gating.state = REQ_CLKS_OFF; 2014 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 2015 queue_delayed_work(hba->clk_gating.clk_gating_workq, 2016 &hba->clk_gating.gate_work, 2017 msecs_to_jiffies(hba->clk_gating.delay_ms)); 2018 } 2019 2020 void ufshcd_release(struct ufs_hba *hba) 2021 { 2022 unsigned long flags; 2023 2024 spin_lock_irqsave(hba->host->host_lock, flags); 2025 __ufshcd_release(hba); 2026 spin_unlock_irqrestore(hba->host->host_lock, flags); 2027 } 2028 EXPORT_SYMBOL_GPL(ufshcd_release); 2029 2030 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 2031 struct device_attribute *attr, char *buf) 2032 { 2033 struct ufs_hba *hba = dev_get_drvdata(dev); 2034 2035 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 2036 } 2037 2038 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 2039 { 2040 struct ufs_hba *hba = dev_get_drvdata(dev); 2041 unsigned long flags; 2042 2043 spin_lock_irqsave(hba->host->host_lock, flags); 2044 hba->clk_gating.delay_ms = value; 2045 spin_unlock_irqrestore(hba->host->host_lock, flags); 2046 } 2047 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 2048 2049 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 2050 struct device_attribute *attr, const char *buf, size_t count) 2051 { 2052 unsigned long value; 2053 2054 if (kstrtoul(buf, 0, &value)) 2055 return -EINVAL; 2056 2057 ufshcd_clkgate_delay_set(dev, value); 2058 return count; 2059 } 2060 2061 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 2062 struct device_attribute *attr, char *buf) 2063 { 2064 struct ufs_hba *hba = dev_get_drvdata(dev); 2065 2066 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 2067 } 2068 2069 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 2070 struct device_attribute *attr, const char *buf, size_t count) 2071 { 2072 struct ufs_hba *hba = dev_get_drvdata(dev); 2073 unsigned long flags; 2074 u32 value; 2075 2076 if (kstrtou32(buf, 0, &value)) 2077 return -EINVAL; 2078 2079 value = !!value; 2080 2081 spin_lock_irqsave(hba->host->host_lock, flags); 2082 if (value == hba->clk_gating.is_enabled) 2083 goto out; 2084 2085 if (value) 2086 __ufshcd_release(hba); 2087 else 2088 hba->clk_gating.active_reqs++; 2089 2090 hba->clk_gating.is_enabled = value; 2091 out: 2092 spin_unlock_irqrestore(hba->host->host_lock, flags); 2093 return count; 2094 } 2095 2096 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 2097 { 2098 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 2099 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 2100 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 2101 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 2102 hba->clk_gating.delay_attr.attr.mode = 0644; 2103 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 2104 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 2105 2106 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 2107 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 2108 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 2109 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 2110 hba->clk_gating.enable_attr.attr.mode = 0644; 2111 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 2112 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 2113 } 2114 2115 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 2116 { 2117 if (hba->clk_gating.delay_attr.attr.name) 2118 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 2119 if (hba->clk_gating.enable_attr.attr.name) 2120 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 2121 } 2122 2123 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 2124 { 2125 char wq_name[sizeof("ufs_clk_gating_00")]; 2126 2127 if (!ufshcd_is_clkgating_allowed(hba)) 2128 return; 2129 2130 hba->clk_gating.state = CLKS_ON; 2131 2132 hba->clk_gating.delay_ms = 150; 2133 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2134 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2135 2136 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d", 2137 hba->host->host_no); 2138 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name, 2139 WQ_MEM_RECLAIM | WQ_HIGHPRI); 2140 2141 ufshcd_init_clk_gating_sysfs(hba); 2142 2143 hba->clk_gating.is_enabled = true; 2144 hba->clk_gating.is_initialized = true; 2145 } 2146 2147 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2148 { 2149 if (!hba->clk_gating.is_initialized) 2150 return; 2151 2152 ufshcd_remove_clk_gating_sysfs(hba); 2153 2154 /* Ungate the clock if necessary. */ 2155 ufshcd_hold(hba); 2156 hba->clk_gating.is_initialized = false; 2157 ufshcd_release(hba); 2158 2159 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2160 } 2161 2162 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2163 { 2164 bool queue_resume_work = false; 2165 ktime_t curr_t = ktime_get(); 2166 unsigned long flags; 2167 2168 if (!ufshcd_is_clkscaling_supported(hba)) 2169 return; 2170 2171 spin_lock_irqsave(hba->host->host_lock, flags); 2172 if (!hba->clk_scaling.active_reqs++) 2173 queue_resume_work = true; 2174 2175 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2176 spin_unlock_irqrestore(hba->host->host_lock, flags); 2177 return; 2178 } 2179 2180 if (queue_resume_work) 2181 queue_work(hba->clk_scaling.workq, 2182 &hba->clk_scaling.resume_work); 2183 2184 if (!hba->clk_scaling.window_start_t) { 2185 hba->clk_scaling.window_start_t = curr_t; 2186 hba->clk_scaling.tot_busy_t = 0; 2187 hba->clk_scaling.is_busy_started = false; 2188 } 2189 2190 if (!hba->clk_scaling.is_busy_started) { 2191 hba->clk_scaling.busy_start_t = curr_t; 2192 hba->clk_scaling.is_busy_started = true; 2193 } 2194 spin_unlock_irqrestore(hba->host->host_lock, flags); 2195 } 2196 2197 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2198 { 2199 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2200 unsigned long flags; 2201 2202 if (!ufshcd_is_clkscaling_supported(hba)) 2203 return; 2204 2205 spin_lock_irqsave(hba->host->host_lock, flags); 2206 hba->clk_scaling.active_reqs--; 2207 if (!scaling->active_reqs && scaling->is_busy_started) { 2208 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2209 scaling->busy_start_t)); 2210 scaling->busy_start_t = 0; 2211 scaling->is_busy_started = false; 2212 } 2213 spin_unlock_irqrestore(hba->host->host_lock, flags); 2214 } 2215 2216 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2217 { 2218 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2219 return READ; 2220 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2221 return WRITE; 2222 else 2223 return -EINVAL; 2224 } 2225 2226 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2227 struct ufshcd_lrb *lrbp) 2228 { 2229 const struct ufs_hba_monitor *m = &hba->monitor; 2230 2231 return (m->enabled && lrbp && lrbp->cmd && 2232 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2233 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2234 } 2235 2236 static void ufshcd_start_monitor(struct ufs_hba *hba, 2237 const struct ufshcd_lrb *lrbp) 2238 { 2239 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2240 unsigned long flags; 2241 2242 spin_lock_irqsave(hba->host->host_lock, flags); 2243 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2244 hba->monitor.busy_start_ts[dir] = ktime_get(); 2245 spin_unlock_irqrestore(hba->host->host_lock, flags); 2246 } 2247 2248 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2249 { 2250 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2251 unsigned long flags; 2252 2253 spin_lock_irqsave(hba->host->host_lock, flags); 2254 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2255 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2256 struct ufs_hba_monitor *m = &hba->monitor; 2257 ktime_t now, inc, lat; 2258 2259 now = lrbp->compl_time_stamp; 2260 inc = ktime_sub(now, m->busy_start_ts[dir]); 2261 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2262 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2263 2264 /* Update latencies */ 2265 m->nr_req[dir]++; 2266 lat = ktime_sub(now, lrbp->issue_time_stamp); 2267 m->lat_sum[dir] += lat; 2268 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2269 m->lat_max[dir] = lat; 2270 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2271 m->lat_min[dir] = lat; 2272 2273 m->nr_queued[dir]--; 2274 /* Push forward the busy start of monitor */ 2275 m->busy_start_ts[dir] = now; 2276 } 2277 spin_unlock_irqrestore(hba->host->host_lock, flags); 2278 } 2279 2280 /** 2281 * ufshcd_send_command - Send SCSI or device management commands 2282 * @hba: per adapter instance 2283 * @task_tag: Task tag of the command 2284 * @hwq: pointer to hardware queue instance 2285 */ 2286 static inline 2287 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2288 struct ufs_hw_queue *hwq) 2289 { 2290 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2291 unsigned long flags; 2292 2293 lrbp->issue_time_stamp = ktime_get(); 2294 lrbp->issue_time_stamp_local_clock = local_clock(); 2295 lrbp->compl_time_stamp = ktime_set(0, 0); 2296 lrbp->compl_time_stamp_local_clock = 0; 2297 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2298 if (lrbp->cmd) 2299 ufshcd_clk_scaling_start_busy(hba); 2300 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2301 ufshcd_start_monitor(hba, lrbp); 2302 2303 if (is_mcq_enabled(hba)) { 2304 int utrd_size = sizeof(struct utp_transfer_req_desc); 2305 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2306 struct utp_transfer_req_desc *dest; 2307 2308 spin_lock(&hwq->sq_lock); 2309 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2310 memcpy(dest, src, utrd_size); 2311 ufshcd_inc_sq_tail(hwq); 2312 spin_unlock(&hwq->sq_lock); 2313 } else { 2314 spin_lock_irqsave(&hba->outstanding_lock, flags); 2315 if (hba->vops && hba->vops->setup_xfer_req) 2316 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2317 !!lrbp->cmd); 2318 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2319 ufshcd_writel(hba, 1 << lrbp->task_tag, 2320 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2321 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2322 } 2323 } 2324 2325 /** 2326 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2327 * @lrbp: pointer to local reference block 2328 */ 2329 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2330 { 2331 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2332 u16 resp_len; 2333 int len; 2334 2335 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2336 if (sense_buffer && resp_len) { 2337 int len_to_copy; 2338 2339 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2340 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2341 2342 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2343 len_to_copy); 2344 } 2345 } 2346 2347 /** 2348 * ufshcd_copy_query_response() - Copy the Query Response and the data 2349 * descriptor 2350 * @hba: per adapter instance 2351 * @lrbp: pointer to local reference block 2352 * 2353 * Return: 0 upon success; < 0 upon failure. 2354 */ 2355 static 2356 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2357 { 2358 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2359 2360 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2361 2362 /* Get the descriptor */ 2363 if (hba->dev_cmd.query.descriptor && 2364 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2365 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2366 GENERAL_UPIU_REQUEST_SIZE; 2367 u16 resp_len; 2368 u16 buf_len; 2369 2370 /* data segment length */ 2371 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2372 .data_segment_length); 2373 buf_len = be16_to_cpu( 2374 hba->dev_cmd.query.request.upiu_req.length); 2375 if (likely(buf_len >= resp_len)) { 2376 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2377 } else { 2378 dev_warn(hba->dev, 2379 "%s: rsp size %d is bigger than buffer size %d", 2380 __func__, resp_len, buf_len); 2381 return -EINVAL; 2382 } 2383 } 2384 2385 return 0; 2386 } 2387 2388 /** 2389 * ufshcd_hba_capabilities - Read controller capabilities 2390 * @hba: per adapter instance 2391 * 2392 * Return: 0 on success, negative on error. 2393 */ 2394 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2395 { 2396 int err; 2397 2398 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2399 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) 2400 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT; 2401 2402 /* nutrs and nutmrs are 0 based values */ 2403 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1; 2404 hba->nutmrs = 2405 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2406 hba->reserved_slot = hba->nutrs - 1; 2407 2408 /* Read crypto capabilities */ 2409 err = ufshcd_hba_init_crypto_capabilities(hba); 2410 if (err) { 2411 dev_err(hba->dev, "crypto setup failed\n"); 2412 return err; 2413 } 2414 2415 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2416 if (!hba->mcq_sup) 2417 return 0; 2418 2419 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2420 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2421 hba->mcq_capabilities); 2422 2423 return 0; 2424 } 2425 2426 /** 2427 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2428 * to accept UIC commands 2429 * @hba: per adapter instance 2430 * 2431 * Return: true on success, else false. 2432 */ 2433 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2434 { 2435 u32 val; 2436 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2437 500, UIC_CMD_TIMEOUT * 1000, false, hba, 2438 REG_CONTROLLER_STATUS); 2439 return ret == 0; 2440 } 2441 2442 /** 2443 * ufshcd_get_upmcrs - Get the power mode change request status 2444 * @hba: Pointer to adapter instance 2445 * 2446 * This function gets the UPMCRS field of HCS register 2447 * 2448 * Return: value of UPMCRS field. 2449 */ 2450 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2451 { 2452 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2453 } 2454 2455 /** 2456 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2457 * @hba: per adapter instance 2458 * @uic_cmd: UIC command 2459 */ 2460 static inline void 2461 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2462 { 2463 lockdep_assert_held(&hba->uic_cmd_mutex); 2464 2465 WARN_ON(hba->active_uic_cmd); 2466 2467 hba->active_uic_cmd = uic_cmd; 2468 2469 /* Write Args */ 2470 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2471 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2472 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2473 2474 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2475 2476 /* Write UIC Cmd */ 2477 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2478 REG_UIC_COMMAND); 2479 } 2480 2481 /** 2482 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2483 * @hba: per adapter instance 2484 * @uic_cmd: UIC command 2485 * 2486 * Return: 0 only if success. 2487 */ 2488 static int 2489 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2490 { 2491 int ret; 2492 unsigned long flags; 2493 2494 lockdep_assert_held(&hba->uic_cmd_mutex); 2495 2496 if (wait_for_completion_timeout(&uic_cmd->done, 2497 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 2498 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2499 } else { 2500 ret = -ETIMEDOUT; 2501 dev_err(hba->dev, 2502 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2503 uic_cmd->command, uic_cmd->argument3); 2504 2505 if (!uic_cmd->cmd_active) { 2506 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2507 __func__); 2508 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2509 } 2510 } 2511 2512 spin_lock_irqsave(hba->host->host_lock, flags); 2513 hba->active_uic_cmd = NULL; 2514 spin_unlock_irqrestore(hba->host->host_lock, flags); 2515 2516 return ret; 2517 } 2518 2519 /** 2520 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2521 * @hba: per adapter instance 2522 * @uic_cmd: UIC command 2523 * @completion: initialize the completion only if this is set to true 2524 * 2525 * Return: 0 only if success. 2526 */ 2527 static int 2528 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd, 2529 bool completion) 2530 { 2531 lockdep_assert_held(&hba->uic_cmd_mutex); 2532 2533 if (!ufshcd_ready_for_uic_cmd(hba)) { 2534 dev_err(hba->dev, 2535 "Controller not ready to accept UIC commands\n"); 2536 return -EIO; 2537 } 2538 2539 if (completion) 2540 init_completion(&uic_cmd->done); 2541 2542 uic_cmd->cmd_active = 1; 2543 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2544 2545 return 0; 2546 } 2547 2548 /** 2549 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2550 * @hba: per adapter instance 2551 * @uic_cmd: UIC command 2552 * 2553 * Return: 0 only if success. 2554 */ 2555 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2556 { 2557 int ret; 2558 2559 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2560 return 0; 2561 2562 ufshcd_hold(hba); 2563 mutex_lock(&hba->uic_cmd_mutex); 2564 ufshcd_add_delay_before_dme_cmd(hba); 2565 2566 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true); 2567 if (!ret) 2568 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2569 2570 mutex_unlock(&hba->uic_cmd_mutex); 2571 2572 ufshcd_release(hba); 2573 return ret; 2574 } 2575 2576 /** 2577 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2578 * @hba: per-adapter instance 2579 * @lrbp: pointer to local reference block 2580 * @sg_entries: The number of sg lists actually used 2581 * @sg_list: Pointer to SG list 2582 */ 2583 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2584 struct scatterlist *sg_list) 2585 { 2586 struct ufshcd_sg_entry *prd; 2587 struct scatterlist *sg; 2588 int i; 2589 2590 if (sg_entries) { 2591 2592 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2593 lrbp->utr_descriptor_ptr->prd_table_length = 2594 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2595 else 2596 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2597 2598 prd = lrbp->ucd_prdt_ptr; 2599 2600 for_each_sg(sg_list, sg, sg_entries, i) { 2601 const unsigned int len = sg_dma_len(sg); 2602 2603 /* 2604 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2605 * based value that indicates the length, in bytes, of 2606 * the data block. A maximum of length of 256KB may 2607 * exist for any entry. Bits 1:0 of this field shall be 2608 * 11b to indicate Dword granularity. A value of '3' 2609 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2610 */ 2611 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2612 prd->size = cpu_to_le32(len - 1); 2613 prd->addr = cpu_to_le64(sg->dma_address); 2614 prd->reserved = 0; 2615 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2616 } 2617 } else { 2618 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2619 } 2620 } 2621 2622 /** 2623 * ufshcd_map_sg - Map scatter-gather list to prdt 2624 * @hba: per adapter instance 2625 * @lrbp: pointer to local reference block 2626 * 2627 * Return: 0 in case of success, non-zero value in case of failure. 2628 */ 2629 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2630 { 2631 struct scsi_cmnd *cmd = lrbp->cmd; 2632 int sg_segments = scsi_dma_map(cmd); 2633 2634 if (sg_segments < 0) 2635 return sg_segments; 2636 2637 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2638 2639 return 0; 2640 } 2641 2642 /** 2643 * ufshcd_enable_intr - enable interrupts 2644 * @hba: per adapter instance 2645 * @intrs: interrupt bits 2646 */ 2647 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2648 { 2649 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2650 2651 set |= intrs; 2652 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2653 } 2654 2655 /** 2656 * ufshcd_disable_intr - disable interrupts 2657 * @hba: per adapter instance 2658 * @intrs: interrupt bits 2659 */ 2660 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2661 { 2662 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2663 2664 set &= ~intrs; 2665 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2666 } 2667 2668 /** 2669 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2670 * descriptor according to request 2671 * @hba: per adapter instance 2672 * @lrbp: pointer to local reference block 2673 * @upiu_flags: flags required in the header 2674 * @cmd_dir: requests data direction 2675 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2676 */ 2677 static void 2678 ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 2679 u8 *upiu_flags, enum dma_data_direction cmd_dir, 2680 int ehs_length) 2681 { 2682 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2683 struct request_desc_header *h = &req_desc->header; 2684 enum utp_data_direction data_direction; 2685 2686 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2687 2688 *h = (typeof(*h)){ }; 2689 2690 if (cmd_dir == DMA_FROM_DEVICE) { 2691 data_direction = UTP_DEVICE_TO_HOST; 2692 *upiu_flags = UPIU_CMD_FLAGS_READ; 2693 } else if (cmd_dir == DMA_TO_DEVICE) { 2694 data_direction = UTP_HOST_TO_DEVICE; 2695 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2696 } else { 2697 data_direction = UTP_NO_DATA_TRANSFER; 2698 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2699 } 2700 2701 h->command_type = lrbp->command_type; 2702 h->data_direction = data_direction; 2703 h->ehs_length = ehs_length; 2704 2705 if (lrbp->intr_cmd) 2706 h->interrupt = 1; 2707 2708 /* Prepare crypto related dwords */ 2709 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2710 2711 /* 2712 * assigning invalid value for command status. Controller 2713 * updates OCS on command completion, with the command 2714 * status 2715 */ 2716 h->ocs = OCS_INVALID_COMMAND_STATUS; 2717 2718 req_desc->prd_table_length = 0; 2719 } 2720 2721 /** 2722 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2723 * for scsi commands 2724 * @lrbp: local reference block pointer 2725 * @upiu_flags: flags 2726 */ 2727 static 2728 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2729 { 2730 struct scsi_cmnd *cmd = lrbp->cmd; 2731 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2732 unsigned short cdb_len; 2733 2734 ucd_req_ptr->header = (struct utp_upiu_header){ 2735 .transaction_code = UPIU_TRANSACTION_COMMAND, 2736 .flags = upiu_flags, 2737 .lun = lrbp->lun, 2738 .task_tag = lrbp->task_tag, 2739 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2740 }; 2741 2742 WARN_ON_ONCE(ucd_req_ptr->header.task_tag != lrbp->task_tag); 2743 2744 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2745 2746 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2747 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 2748 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2749 2750 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2751 } 2752 2753 /** 2754 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2755 * @hba: UFS hba 2756 * @lrbp: local reference block pointer 2757 * @upiu_flags: flags 2758 */ 2759 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2760 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2761 { 2762 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2763 struct ufs_query *query = &hba->dev_cmd.query; 2764 u16 len = be16_to_cpu(query->request.upiu_req.length); 2765 2766 /* Query request header */ 2767 ucd_req_ptr->header = (struct utp_upiu_header){ 2768 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2769 .flags = upiu_flags, 2770 .lun = lrbp->lun, 2771 .task_tag = lrbp->task_tag, 2772 .query_function = query->request.query_func, 2773 /* Data segment length only need for WRITE_DESC */ 2774 .data_segment_length = 2775 query->request.upiu_req.opcode == 2776 UPIU_QUERY_OPCODE_WRITE_DESC ? 2777 cpu_to_be16(len) : 2778 0, 2779 }; 2780 2781 /* Copy the Query Request buffer as is */ 2782 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2783 QUERY_OSF_SIZE); 2784 2785 /* Copy the Descriptor */ 2786 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2787 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2788 2789 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2790 } 2791 2792 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2793 { 2794 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2795 2796 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2797 2798 ucd_req_ptr->header = (struct utp_upiu_header){ 2799 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2800 .task_tag = lrbp->task_tag, 2801 }; 2802 2803 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2804 } 2805 2806 /** 2807 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2808 * for Device Management Purposes 2809 * @hba: per adapter instance 2810 * @lrbp: pointer to local reference block 2811 * 2812 * Return: 0 upon success; < 0 upon failure. 2813 */ 2814 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2815 struct ufshcd_lrb *lrbp) 2816 { 2817 u8 upiu_flags; 2818 int ret = 0; 2819 2820 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 2821 2822 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2823 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2824 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2825 ufshcd_prepare_utp_nop_upiu(lrbp); 2826 else 2827 ret = -EINVAL; 2828 2829 return ret; 2830 } 2831 2832 /** 2833 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2834 * for SCSI Purposes 2835 * @hba: per adapter instance 2836 * @lrbp: pointer to local reference block 2837 */ 2838 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2839 { 2840 struct request *rq = scsi_cmd_to_rq(lrbp->cmd); 2841 unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq)); 2842 u8 upiu_flags; 2843 2844 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0); 2845 if (ioprio_class == IOPRIO_CLASS_RT) 2846 upiu_flags |= UPIU_CMD_FLAGS_CP; 2847 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2848 } 2849 2850 /** 2851 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2852 * @upiu_wlun_id: UPIU W-LUN id 2853 * 2854 * Return: SCSI W-LUN id. 2855 */ 2856 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2857 { 2858 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2859 } 2860 2861 static inline bool is_device_wlun(struct scsi_device *sdev) 2862 { 2863 return sdev->lun == 2864 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2865 } 2866 2867 /* 2868 * Associate the UFS controller queue with the default and poll HCTX types. 2869 * Initialize the mq_map[] arrays. 2870 */ 2871 static void ufshcd_map_queues(struct Scsi_Host *shost) 2872 { 2873 struct ufs_hba *hba = shost_priv(shost); 2874 int i, queue_offset = 0; 2875 2876 if (!is_mcq_supported(hba)) { 2877 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2878 hba->nr_queues[HCTX_TYPE_READ] = 0; 2879 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2880 hba->nr_hw_queues = 1; 2881 } 2882 2883 for (i = 0; i < shost->nr_maps; i++) { 2884 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2885 2886 map->nr_queues = hba->nr_queues[i]; 2887 if (!map->nr_queues) 2888 continue; 2889 map->queue_offset = queue_offset; 2890 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2891 map->queue_offset = 0; 2892 2893 blk_mq_map_queues(map); 2894 queue_offset += map->nr_queues; 2895 } 2896 } 2897 2898 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2899 { 2900 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2901 i * ufshcd_get_ucd_size(hba); 2902 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2903 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2904 i * ufshcd_get_ucd_size(hba); 2905 u16 response_offset = offsetof(struct utp_transfer_cmd_desc, 2906 response_upiu); 2907 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 2908 2909 lrb->utr_descriptor_ptr = utrdlp + i; 2910 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2911 i * sizeof(struct utp_transfer_req_desc); 2912 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2913 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2914 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2915 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2916 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2917 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2918 } 2919 2920 /** 2921 * ufshcd_queuecommand - main entry point for SCSI requests 2922 * @host: SCSI host pointer 2923 * @cmd: command from SCSI Midlayer 2924 * 2925 * Return: 0 for success, non-zero in case of failure. 2926 */ 2927 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2928 { 2929 struct ufs_hba *hba = shost_priv(host); 2930 int tag = scsi_cmd_to_rq(cmd)->tag; 2931 struct ufshcd_lrb *lrbp; 2932 int err = 0; 2933 struct ufs_hw_queue *hwq = NULL; 2934 2935 switch (hba->ufshcd_state) { 2936 case UFSHCD_STATE_OPERATIONAL: 2937 break; 2938 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2939 /* 2940 * SCSI error handler can call ->queuecommand() while UFS error 2941 * handler is in progress. Error interrupts could change the 2942 * state from UFSHCD_STATE_RESET to 2943 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2944 * being issued in that case. 2945 */ 2946 if (ufshcd_eh_in_progress(hba)) { 2947 err = SCSI_MLQUEUE_HOST_BUSY; 2948 goto out; 2949 } 2950 break; 2951 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2952 /* 2953 * pm_runtime_get_sync() is used at error handling preparation 2954 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2955 * PM ops, it can never be finished if we let SCSI layer keep 2956 * retrying it, which gets err handler stuck forever. Neither 2957 * can we let the scsi cmd pass through, because UFS is in bad 2958 * state, the scsi cmd may eventually time out, which will get 2959 * err handler blocked for too long. So, just fail the scsi cmd 2960 * sent from PM ops, err handler can recover PM error anyways. 2961 */ 2962 if (hba->pm_op_in_progress) { 2963 hba->force_reset = true; 2964 set_host_byte(cmd, DID_BAD_TARGET); 2965 scsi_done(cmd); 2966 goto out; 2967 } 2968 fallthrough; 2969 case UFSHCD_STATE_RESET: 2970 err = SCSI_MLQUEUE_HOST_BUSY; 2971 goto out; 2972 case UFSHCD_STATE_ERROR: 2973 set_host_byte(cmd, DID_ERROR); 2974 scsi_done(cmd); 2975 goto out; 2976 } 2977 2978 hba->req_abort_count = 0; 2979 2980 ufshcd_hold(hba); 2981 2982 lrbp = &hba->lrb[tag]; 2983 lrbp->cmd = cmd; 2984 lrbp->task_tag = tag; 2985 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 2986 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 2987 2988 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp); 2989 2990 lrbp->req_abort_skip = false; 2991 2992 ufshcd_comp_scsi_upiu(hba, lrbp); 2993 2994 err = ufshcd_map_sg(hba, lrbp); 2995 if (err) { 2996 ufshcd_release(hba); 2997 goto out; 2998 } 2999 3000 if (is_mcq_enabled(hba)) 3001 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 3002 3003 ufshcd_send_command(hba, tag, hwq); 3004 3005 out: 3006 if (ufs_trigger_eh(hba)) { 3007 unsigned long flags; 3008 3009 spin_lock_irqsave(hba->host->host_lock, flags); 3010 ufshcd_schedule_eh_work(hba); 3011 spin_unlock_irqrestore(hba->host->host_lock, flags); 3012 } 3013 3014 return err; 3015 } 3016 3017 static void ufshcd_setup_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3018 enum dev_cmd_type cmd_type, u8 lun, int tag) 3019 { 3020 lrbp->cmd = NULL; 3021 lrbp->task_tag = tag; 3022 lrbp->lun = lun; 3023 lrbp->intr_cmd = true; /* No interrupt aggregation */ 3024 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 3025 hba->dev_cmd.type = cmd_type; 3026 } 3027 3028 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 3029 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 3030 { 3031 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 3032 3033 return ufshcd_compose_devman_upiu(hba, lrbp); 3034 } 3035 3036 /* 3037 * Check with the block layer if the command is inflight 3038 * @cmd: command to check. 3039 * 3040 * Return: true if command is inflight; false if not. 3041 */ 3042 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 3043 { 3044 return cmd && blk_mq_rq_state(scsi_cmd_to_rq(cmd)) == MQ_RQ_IN_FLIGHT; 3045 } 3046 3047 /* 3048 * Clear the pending command in the controller and wait until 3049 * the controller confirms that the command has been cleared. 3050 * @hba: per adapter instance 3051 * @task_tag: The tag number of the command to be cleared. 3052 */ 3053 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 3054 { 3055 u32 mask; 3056 unsigned long flags; 3057 int err; 3058 3059 if (is_mcq_enabled(hba)) { 3060 /* 3061 * MCQ mode. Clean up the MCQ resources similar to 3062 * what the ufshcd_utrl_clear() does for SDB mode. 3063 */ 3064 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 3065 if (err) { 3066 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 3067 __func__, task_tag, err); 3068 return err; 3069 } 3070 return 0; 3071 } 3072 3073 mask = 1U << task_tag; 3074 3075 /* clear outstanding transaction before retry */ 3076 spin_lock_irqsave(hba->host->host_lock, flags); 3077 ufshcd_utrl_clear(hba, mask); 3078 spin_unlock_irqrestore(hba->host->host_lock, flags); 3079 3080 /* 3081 * wait for h/w to clear corresponding bit in door-bell. 3082 * max. wait is 1 sec. 3083 */ 3084 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 3085 mask, ~mask, 1000, 1000); 3086 } 3087 3088 /** 3089 * ufshcd_dev_cmd_completion() - handles device management command responses 3090 * @hba: per adapter instance 3091 * @lrbp: pointer to local reference block 3092 * 3093 * Return: 0 upon success; < 0 upon failure. 3094 */ 3095 static int 3096 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 3097 { 3098 enum upiu_response_transaction resp; 3099 int err = 0; 3100 3101 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 3102 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3103 3104 switch (resp) { 3105 case UPIU_TRANSACTION_NOP_IN: 3106 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3107 err = -EINVAL; 3108 dev_err(hba->dev, "%s: unexpected response %x\n", 3109 __func__, resp); 3110 } 3111 break; 3112 case UPIU_TRANSACTION_QUERY_RSP: { 3113 u8 response = lrbp->ucd_rsp_ptr->header.response; 3114 3115 if (response == 0) 3116 err = ufshcd_copy_query_response(hba, lrbp); 3117 break; 3118 } 3119 case UPIU_TRANSACTION_REJECT_UPIU: 3120 /* TODO: handle Reject UPIU Response */ 3121 err = -EPERM; 3122 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3123 __func__); 3124 break; 3125 case UPIU_TRANSACTION_RESPONSE: 3126 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3127 err = -EINVAL; 3128 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3129 } 3130 break; 3131 default: 3132 err = -EINVAL; 3133 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3134 __func__, resp); 3135 break; 3136 } 3137 3138 return err; 3139 } 3140 3141 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3142 struct ufshcd_lrb *lrbp, int max_timeout) 3143 { 3144 unsigned long time_left = msecs_to_jiffies(max_timeout); 3145 unsigned long flags; 3146 bool pending; 3147 int err; 3148 3149 retry: 3150 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3151 time_left); 3152 3153 if (likely(time_left)) { 3154 /* 3155 * The completion handler called complete() and the caller of 3156 * this function still owns the @lrbp tag so the code below does 3157 * not trigger any race conditions. 3158 */ 3159 hba->dev_cmd.complete = NULL; 3160 err = ufshcd_get_tr_ocs(lrbp, NULL); 3161 if (!err) 3162 err = ufshcd_dev_cmd_completion(hba, lrbp); 3163 } else { 3164 err = -ETIMEDOUT; 3165 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3166 __func__, lrbp->task_tag); 3167 3168 /* MCQ mode */ 3169 if (is_mcq_enabled(hba)) { 3170 err = ufshcd_clear_cmd(hba, lrbp->task_tag); 3171 hba->dev_cmd.complete = NULL; 3172 return err; 3173 } 3174 3175 /* SDB mode */ 3176 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3177 /* successfully cleared the command, retry if needed */ 3178 err = -EAGAIN; 3179 /* 3180 * Since clearing the command succeeded we also need to 3181 * clear the task tag bit from the outstanding_reqs 3182 * variable. 3183 */ 3184 spin_lock_irqsave(&hba->outstanding_lock, flags); 3185 pending = test_bit(lrbp->task_tag, 3186 &hba->outstanding_reqs); 3187 if (pending) { 3188 hba->dev_cmd.complete = NULL; 3189 __clear_bit(lrbp->task_tag, 3190 &hba->outstanding_reqs); 3191 } 3192 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3193 3194 if (!pending) { 3195 /* 3196 * The completion handler ran while we tried to 3197 * clear the command. 3198 */ 3199 time_left = 1; 3200 goto retry; 3201 } 3202 } else { 3203 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3204 __func__, lrbp->task_tag); 3205 3206 spin_lock_irqsave(&hba->outstanding_lock, flags); 3207 pending = test_bit(lrbp->task_tag, 3208 &hba->outstanding_reqs); 3209 if (pending) 3210 hba->dev_cmd.complete = NULL; 3211 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3212 3213 if (!pending) { 3214 /* 3215 * The completion handler ran while we tried to 3216 * clear the command. 3217 */ 3218 time_left = 1; 3219 goto retry; 3220 } 3221 } 3222 } 3223 3224 return err; 3225 } 3226 3227 static void ufshcd_dev_man_lock(struct ufs_hba *hba) 3228 { 3229 ufshcd_hold(hba); 3230 mutex_lock(&hba->dev_cmd.lock); 3231 down_read(&hba->clk_scaling_lock); 3232 } 3233 3234 static void ufshcd_dev_man_unlock(struct ufs_hba *hba) 3235 { 3236 up_read(&hba->clk_scaling_lock); 3237 mutex_unlock(&hba->dev_cmd.lock); 3238 ufshcd_release(hba); 3239 } 3240 3241 static int ufshcd_issue_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3242 const u32 tag, int timeout) 3243 { 3244 DECLARE_COMPLETION_ONSTACK(wait); 3245 int err; 3246 3247 hba->dev_cmd.complete = &wait; 3248 3249 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3250 3251 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3252 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3253 3254 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3255 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3256 3257 return err; 3258 } 3259 3260 /** 3261 * ufshcd_exec_dev_cmd - API for sending device management requests 3262 * @hba: UFS hba 3263 * @cmd_type: specifies the type (NOP, Query...) 3264 * @timeout: timeout in milliseconds 3265 * 3266 * Return: 0 upon success; < 0 upon failure. 3267 * 3268 * NOTE: Since there is only one available tag for device management commands, 3269 * it is expected you hold the hba->dev_cmd.lock mutex. 3270 */ 3271 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3272 enum dev_cmd_type cmd_type, int timeout) 3273 { 3274 const u32 tag = hba->reserved_slot; 3275 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 3276 int err; 3277 3278 /* Protects use of hba->reserved_slot. */ 3279 lockdep_assert_held(&hba->dev_cmd.lock); 3280 3281 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3282 if (unlikely(err)) 3283 return err; 3284 3285 return ufshcd_issue_dev_cmd(hba, lrbp, tag, timeout); 3286 } 3287 3288 /** 3289 * ufshcd_init_query() - init the query response and request parameters 3290 * @hba: per-adapter instance 3291 * @request: address of the request pointer to be initialized 3292 * @response: address of the response pointer to be initialized 3293 * @opcode: operation to perform 3294 * @idn: flag idn to access 3295 * @index: LU number to access 3296 * @selector: query/flag/descriptor further identification 3297 */ 3298 static inline void ufshcd_init_query(struct ufs_hba *hba, 3299 struct ufs_query_req **request, struct ufs_query_res **response, 3300 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3301 { 3302 *request = &hba->dev_cmd.query.request; 3303 *response = &hba->dev_cmd.query.response; 3304 memset(*request, 0, sizeof(struct ufs_query_req)); 3305 memset(*response, 0, sizeof(struct ufs_query_res)); 3306 (*request)->upiu_req.opcode = opcode; 3307 (*request)->upiu_req.idn = idn; 3308 (*request)->upiu_req.index = index; 3309 (*request)->upiu_req.selector = selector; 3310 } 3311 3312 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3313 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3314 { 3315 int ret; 3316 int retries; 3317 3318 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3319 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3320 if (ret) 3321 dev_dbg(hba->dev, 3322 "%s: failed with error %d, retries %d\n", 3323 __func__, ret, retries); 3324 else 3325 break; 3326 } 3327 3328 if (ret) 3329 dev_err(hba->dev, 3330 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3331 __func__, opcode, idn, ret, retries); 3332 return ret; 3333 } 3334 3335 /** 3336 * ufshcd_query_flag() - API function for sending flag query requests 3337 * @hba: per-adapter instance 3338 * @opcode: flag query to perform 3339 * @idn: flag idn to access 3340 * @index: flag index to access 3341 * @flag_res: the flag value after the query request completes 3342 * 3343 * Return: 0 for success, non-zero in case of failure. 3344 */ 3345 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3346 enum flag_idn idn, u8 index, bool *flag_res) 3347 { 3348 struct ufs_query_req *request = NULL; 3349 struct ufs_query_res *response = NULL; 3350 int err, selector = 0; 3351 int timeout = QUERY_REQ_TIMEOUT; 3352 3353 BUG_ON(!hba); 3354 3355 ufshcd_dev_man_lock(hba); 3356 3357 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3358 selector); 3359 3360 switch (opcode) { 3361 case UPIU_QUERY_OPCODE_SET_FLAG: 3362 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3363 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3364 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3365 break; 3366 case UPIU_QUERY_OPCODE_READ_FLAG: 3367 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3368 if (!flag_res) { 3369 /* No dummy reads */ 3370 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3371 __func__); 3372 err = -EINVAL; 3373 goto out_unlock; 3374 } 3375 break; 3376 default: 3377 dev_err(hba->dev, 3378 "%s: Expected query flag opcode but got = %d\n", 3379 __func__, opcode); 3380 err = -EINVAL; 3381 goto out_unlock; 3382 } 3383 3384 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3385 3386 if (err) { 3387 dev_err(hba->dev, 3388 "%s: Sending flag query for idn %d failed, err = %d\n", 3389 __func__, idn, err); 3390 goto out_unlock; 3391 } 3392 3393 if (flag_res) 3394 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3395 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3396 3397 out_unlock: 3398 ufshcd_dev_man_unlock(hba); 3399 return err; 3400 } 3401 3402 /** 3403 * ufshcd_query_attr - API function for sending attribute requests 3404 * @hba: per-adapter instance 3405 * @opcode: attribute opcode 3406 * @idn: attribute idn to access 3407 * @index: index field 3408 * @selector: selector field 3409 * @attr_val: the attribute value after the query request completes 3410 * 3411 * Return: 0 for success, non-zero in case of failure. 3412 */ 3413 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3414 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3415 { 3416 struct ufs_query_req *request = NULL; 3417 struct ufs_query_res *response = NULL; 3418 int err; 3419 3420 BUG_ON(!hba); 3421 3422 if (!attr_val) { 3423 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3424 __func__, opcode); 3425 return -EINVAL; 3426 } 3427 3428 ufshcd_dev_man_lock(hba); 3429 3430 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3431 selector); 3432 3433 switch (opcode) { 3434 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3435 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3436 request->upiu_req.value = cpu_to_be32(*attr_val); 3437 break; 3438 case UPIU_QUERY_OPCODE_READ_ATTR: 3439 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3440 break; 3441 default: 3442 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3443 __func__, opcode); 3444 err = -EINVAL; 3445 goto out_unlock; 3446 } 3447 3448 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3449 3450 if (err) { 3451 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3452 __func__, opcode, idn, index, err); 3453 goto out_unlock; 3454 } 3455 3456 *attr_val = be32_to_cpu(response->upiu_res.value); 3457 3458 out_unlock: 3459 ufshcd_dev_man_unlock(hba); 3460 return err; 3461 } 3462 3463 /** 3464 * ufshcd_query_attr_retry() - API function for sending query 3465 * attribute with retries 3466 * @hba: per-adapter instance 3467 * @opcode: attribute opcode 3468 * @idn: attribute idn to access 3469 * @index: index field 3470 * @selector: selector field 3471 * @attr_val: the attribute value after the query request 3472 * completes 3473 * 3474 * Return: 0 for success, non-zero in case of failure. 3475 */ 3476 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3477 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3478 u32 *attr_val) 3479 { 3480 int ret = 0; 3481 u32 retries; 3482 3483 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3484 ret = ufshcd_query_attr(hba, opcode, idn, index, 3485 selector, attr_val); 3486 if (ret) 3487 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3488 __func__, ret, retries); 3489 else 3490 break; 3491 } 3492 3493 if (ret) 3494 dev_err(hba->dev, 3495 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3496 __func__, idn, ret, QUERY_REQ_RETRIES); 3497 return ret; 3498 } 3499 3500 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3501 enum query_opcode opcode, enum desc_idn idn, u8 index, 3502 u8 selector, u8 *desc_buf, int *buf_len) 3503 { 3504 struct ufs_query_req *request = NULL; 3505 struct ufs_query_res *response = NULL; 3506 int err; 3507 3508 BUG_ON(!hba); 3509 3510 if (!desc_buf) { 3511 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3512 __func__, opcode); 3513 return -EINVAL; 3514 } 3515 3516 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3517 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3518 __func__, *buf_len); 3519 return -EINVAL; 3520 } 3521 3522 ufshcd_dev_man_lock(hba); 3523 3524 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3525 selector); 3526 hba->dev_cmd.query.descriptor = desc_buf; 3527 request->upiu_req.length = cpu_to_be16(*buf_len); 3528 3529 switch (opcode) { 3530 case UPIU_QUERY_OPCODE_WRITE_DESC: 3531 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3532 break; 3533 case UPIU_QUERY_OPCODE_READ_DESC: 3534 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3535 break; 3536 default: 3537 dev_err(hba->dev, 3538 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3539 __func__, opcode); 3540 err = -EINVAL; 3541 goto out_unlock; 3542 } 3543 3544 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3545 3546 if (err) { 3547 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3548 __func__, opcode, idn, index, err); 3549 goto out_unlock; 3550 } 3551 3552 *buf_len = be16_to_cpu(response->upiu_res.length); 3553 3554 out_unlock: 3555 hba->dev_cmd.query.descriptor = NULL; 3556 ufshcd_dev_man_unlock(hba); 3557 return err; 3558 } 3559 3560 /** 3561 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3562 * @hba: per-adapter instance 3563 * @opcode: attribute opcode 3564 * @idn: attribute idn to access 3565 * @index: index field 3566 * @selector: selector field 3567 * @desc_buf: the buffer that contains the descriptor 3568 * @buf_len: length parameter passed to the device 3569 * 3570 * The buf_len parameter will contain, on return, the length parameter 3571 * received on the response. 3572 * 3573 * Return: 0 for success, non-zero in case of failure. 3574 */ 3575 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3576 enum query_opcode opcode, 3577 enum desc_idn idn, u8 index, 3578 u8 selector, 3579 u8 *desc_buf, int *buf_len) 3580 { 3581 int err; 3582 int retries; 3583 3584 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3585 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3586 selector, desc_buf, buf_len); 3587 if (!err || err == -EINVAL) 3588 break; 3589 } 3590 3591 return err; 3592 } 3593 3594 /** 3595 * ufshcd_read_desc_param - read the specified descriptor parameter 3596 * @hba: Pointer to adapter instance 3597 * @desc_id: descriptor idn value 3598 * @desc_index: descriptor index 3599 * @param_offset: offset of the parameter to read 3600 * @param_read_buf: pointer to buffer where parameter would be read 3601 * @param_size: sizeof(param_read_buf) 3602 * 3603 * Return: 0 in case of success, non-zero otherwise. 3604 */ 3605 int ufshcd_read_desc_param(struct ufs_hba *hba, 3606 enum desc_idn desc_id, 3607 int desc_index, 3608 u8 param_offset, 3609 u8 *param_read_buf, 3610 u8 param_size) 3611 { 3612 int ret; 3613 u8 *desc_buf; 3614 int buff_len = QUERY_DESC_MAX_SIZE; 3615 bool is_kmalloc = true; 3616 3617 /* Safety check */ 3618 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3619 return -EINVAL; 3620 3621 /* Check whether we need temp memory */ 3622 if (param_offset != 0 || param_size < buff_len) { 3623 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3624 if (!desc_buf) 3625 return -ENOMEM; 3626 } else { 3627 desc_buf = param_read_buf; 3628 is_kmalloc = false; 3629 } 3630 3631 /* Request for full descriptor */ 3632 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3633 desc_id, desc_index, 0, 3634 desc_buf, &buff_len); 3635 if (ret) { 3636 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3637 __func__, desc_id, desc_index, param_offset, ret); 3638 goto out; 3639 } 3640 3641 /* Update descriptor length */ 3642 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3643 3644 if (param_offset >= buff_len) { 3645 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3646 __func__, param_offset, desc_id, buff_len); 3647 ret = -EINVAL; 3648 goto out; 3649 } 3650 3651 /* Sanity check */ 3652 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3653 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3654 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3655 ret = -EINVAL; 3656 goto out; 3657 } 3658 3659 if (is_kmalloc) { 3660 /* Make sure we don't copy more data than available */ 3661 if (param_offset >= buff_len) 3662 ret = -EINVAL; 3663 else 3664 memcpy(param_read_buf, &desc_buf[param_offset], 3665 min_t(u32, param_size, buff_len - param_offset)); 3666 } 3667 out: 3668 if (is_kmalloc) 3669 kfree(desc_buf); 3670 return ret; 3671 } 3672 3673 /** 3674 * struct uc_string_id - unicode string 3675 * 3676 * @len: size of this descriptor inclusive 3677 * @type: descriptor type 3678 * @uc: unicode string character 3679 */ 3680 struct uc_string_id { 3681 u8 len; 3682 u8 type; 3683 wchar_t uc[]; 3684 } __packed; 3685 3686 /* replace non-printable or non-ASCII characters with spaces */ 3687 static inline char ufshcd_remove_non_printable(u8 ch) 3688 { 3689 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3690 } 3691 3692 /** 3693 * ufshcd_read_string_desc - read string descriptor 3694 * @hba: pointer to adapter instance 3695 * @desc_index: descriptor index 3696 * @buf: pointer to buffer where descriptor would be read, 3697 * the caller should free the memory. 3698 * @ascii: if true convert from unicode to ascii characters 3699 * null terminated string. 3700 * 3701 * Return: 3702 * * string size on success. 3703 * * -ENOMEM: on allocation failure 3704 * * -EINVAL: on a wrong parameter 3705 */ 3706 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3707 u8 **buf, bool ascii) 3708 { 3709 struct uc_string_id *uc_str; 3710 u8 *str; 3711 int ret; 3712 3713 if (!buf) 3714 return -EINVAL; 3715 3716 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3717 if (!uc_str) 3718 return -ENOMEM; 3719 3720 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3721 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3722 if (ret < 0) { 3723 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3724 QUERY_REQ_RETRIES, ret); 3725 str = NULL; 3726 goto out; 3727 } 3728 3729 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3730 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3731 str = NULL; 3732 ret = 0; 3733 goto out; 3734 } 3735 3736 if (ascii) { 3737 ssize_t ascii_len; 3738 int i; 3739 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3740 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3741 str = kzalloc(ascii_len, GFP_KERNEL); 3742 if (!str) { 3743 ret = -ENOMEM; 3744 goto out; 3745 } 3746 3747 /* 3748 * the descriptor contains string in UTF16 format 3749 * we need to convert to utf-8 so it can be displayed 3750 */ 3751 ret = utf16s_to_utf8s(uc_str->uc, 3752 uc_str->len - QUERY_DESC_HDR_SIZE, 3753 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3754 3755 /* replace non-printable or non-ASCII characters with spaces */ 3756 for (i = 0; i < ret; i++) 3757 str[i] = ufshcd_remove_non_printable(str[i]); 3758 3759 str[ret++] = '\0'; 3760 3761 } else { 3762 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3763 if (!str) { 3764 ret = -ENOMEM; 3765 goto out; 3766 } 3767 ret = uc_str->len; 3768 } 3769 out: 3770 *buf = str; 3771 kfree(uc_str); 3772 return ret; 3773 } 3774 3775 /** 3776 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3777 * @hba: Pointer to adapter instance 3778 * @lun: lun id 3779 * @param_offset: offset of the parameter to read 3780 * @param_read_buf: pointer to buffer where parameter would be read 3781 * @param_size: sizeof(param_read_buf) 3782 * 3783 * Return: 0 in case of success, non-zero otherwise. 3784 */ 3785 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3786 int lun, 3787 enum unit_desc_param param_offset, 3788 u8 *param_read_buf, 3789 u32 param_size) 3790 { 3791 /* 3792 * Unit descriptors are only available for general purpose LUs (LUN id 3793 * from 0 to 7) and RPMB Well known LU. 3794 */ 3795 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3796 return -EOPNOTSUPP; 3797 3798 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3799 param_offset, param_read_buf, param_size); 3800 } 3801 3802 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3803 { 3804 int err = 0; 3805 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3806 3807 if (hba->dev_info.wspecversion >= 0x300) { 3808 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3809 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3810 &gating_wait); 3811 if (err) 3812 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3813 err, gating_wait); 3814 3815 if (gating_wait == 0) { 3816 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3817 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3818 gating_wait); 3819 } 3820 3821 hba->dev_info.clk_gating_wait_us = gating_wait; 3822 } 3823 3824 return err; 3825 } 3826 3827 /** 3828 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3829 * @hba: per adapter instance 3830 * 3831 * 1. Allocate DMA memory for Command Descriptor array 3832 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3833 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3834 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3835 * (UTMRDL) 3836 * 4. Allocate memory for local reference block(lrb). 3837 * 3838 * Return: 0 for success, non-zero in case of failure. 3839 */ 3840 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3841 { 3842 size_t utmrdl_size, utrdl_size, ucdl_size; 3843 3844 /* Allocate memory for UTP command descriptors */ 3845 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3846 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3847 ucdl_size, 3848 &hba->ucdl_dma_addr, 3849 GFP_KERNEL); 3850 3851 /* 3852 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3853 */ 3854 if (!hba->ucdl_base_addr || 3855 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3856 dev_err(hba->dev, 3857 "Command Descriptor Memory allocation failed\n"); 3858 goto out; 3859 } 3860 3861 /* 3862 * Allocate memory for UTP Transfer descriptors 3863 * UFSHCI requires 1KB alignment of UTRD 3864 */ 3865 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3866 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3867 utrdl_size, 3868 &hba->utrdl_dma_addr, 3869 GFP_KERNEL); 3870 if (!hba->utrdl_base_addr || 3871 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3872 dev_err(hba->dev, 3873 "Transfer Descriptor Memory allocation failed\n"); 3874 goto out; 3875 } 3876 3877 /* 3878 * Skip utmrdl allocation; it may have been 3879 * allocated during first pass and not released during 3880 * MCQ memory allocation. 3881 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3882 */ 3883 if (hba->utmrdl_base_addr) 3884 goto skip_utmrdl; 3885 /* 3886 * Allocate memory for UTP Task Management descriptors 3887 * UFSHCI requires 1KB alignment of UTMRD 3888 */ 3889 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3890 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3891 utmrdl_size, 3892 &hba->utmrdl_dma_addr, 3893 GFP_KERNEL); 3894 if (!hba->utmrdl_base_addr || 3895 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3896 dev_err(hba->dev, 3897 "Task Management Descriptor Memory allocation failed\n"); 3898 goto out; 3899 } 3900 3901 skip_utmrdl: 3902 /* Allocate memory for local reference block */ 3903 hba->lrb = devm_kcalloc(hba->dev, 3904 hba->nutrs, sizeof(struct ufshcd_lrb), 3905 GFP_KERNEL); 3906 if (!hba->lrb) { 3907 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3908 goto out; 3909 } 3910 return 0; 3911 out: 3912 return -ENOMEM; 3913 } 3914 3915 /** 3916 * ufshcd_host_memory_configure - configure local reference block with 3917 * memory offsets 3918 * @hba: per adapter instance 3919 * 3920 * Configure Host memory space 3921 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3922 * address. 3923 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3924 * and PRDT offset. 3925 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3926 * into local reference block. 3927 */ 3928 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3929 { 3930 struct utp_transfer_req_desc *utrdlp; 3931 dma_addr_t cmd_desc_dma_addr; 3932 dma_addr_t cmd_desc_element_addr; 3933 u16 response_offset; 3934 u16 prdt_offset; 3935 int cmd_desc_size; 3936 int i; 3937 3938 utrdlp = hba->utrdl_base_addr; 3939 3940 response_offset = 3941 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3942 prdt_offset = 3943 offsetof(struct utp_transfer_cmd_desc, prd_table); 3944 3945 cmd_desc_size = ufshcd_get_ucd_size(hba); 3946 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3947 3948 for (i = 0; i < hba->nutrs; i++) { 3949 /* Configure UTRD with command descriptor base address */ 3950 cmd_desc_element_addr = 3951 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3952 utrdlp[i].command_desc_base_addr = 3953 cpu_to_le64(cmd_desc_element_addr); 3954 3955 /* Response upiu and prdt offset should be in double words */ 3956 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3957 utrdlp[i].response_upiu_offset = 3958 cpu_to_le16(response_offset); 3959 utrdlp[i].prd_table_offset = 3960 cpu_to_le16(prdt_offset); 3961 utrdlp[i].response_upiu_length = 3962 cpu_to_le16(ALIGNED_UPIU_SIZE); 3963 } else { 3964 utrdlp[i].response_upiu_offset = 3965 cpu_to_le16(response_offset >> 2); 3966 utrdlp[i].prd_table_offset = 3967 cpu_to_le16(prdt_offset >> 2); 3968 utrdlp[i].response_upiu_length = 3969 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 3970 } 3971 3972 ufshcd_init_lrb(hba, &hba->lrb[i], i); 3973 } 3974 } 3975 3976 /** 3977 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 3978 * @hba: per adapter instance 3979 * 3980 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 3981 * in order to initialize the Unipro link startup procedure. 3982 * Once the Unipro links are up, the device connected to the controller 3983 * is detected. 3984 * 3985 * Return: 0 on success, non-zero value on failure. 3986 */ 3987 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 3988 { 3989 struct uic_command uic_cmd = {0}; 3990 int ret; 3991 3992 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 3993 3994 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3995 if (ret) 3996 dev_dbg(hba->dev, 3997 "dme-link-startup: error code %d\n", ret); 3998 return ret; 3999 } 4000 /** 4001 * ufshcd_dme_reset - UIC command for DME_RESET 4002 * @hba: per adapter instance 4003 * 4004 * DME_RESET command is issued in order to reset UniPro stack. 4005 * This function now deals with cold reset. 4006 * 4007 * Return: 0 on success, non-zero value on failure. 4008 */ 4009 static int ufshcd_dme_reset(struct ufs_hba *hba) 4010 { 4011 struct uic_command uic_cmd = {0}; 4012 int ret; 4013 4014 uic_cmd.command = UIC_CMD_DME_RESET; 4015 4016 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4017 if (ret) 4018 dev_err(hba->dev, 4019 "dme-reset: error code %d\n", ret); 4020 4021 return ret; 4022 } 4023 4024 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 4025 int agreed_gear, 4026 int adapt_val) 4027 { 4028 int ret; 4029 4030 if (agreed_gear < UFS_HS_G4) 4031 adapt_val = PA_NO_ADAPT; 4032 4033 ret = ufshcd_dme_set(hba, 4034 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 4035 adapt_val); 4036 return ret; 4037 } 4038 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 4039 4040 /** 4041 * ufshcd_dme_enable - UIC command for DME_ENABLE 4042 * @hba: per adapter instance 4043 * 4044 * DME_ENABLE command is issued in order to enable UniPro stack. 4045 * 4046 * Return: 0 on success, non-zero value on failure. 4047 */ 4048 static int ufshcd_dme_enable(struct ufs_hba *hba) 4049 { 4050 struct uic_command uic_cmd = {0}; 4051 int ret; 4052 4053 uic_cmd.command = UIC_CMD_DME_ENABLE; 4054 4055 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4056 if (ret) 4057 dev_err(hba->dev, 4058 "dme-enable: error code %d\n", ret); 4059 4060 return ret; 4061 } 4062 4063 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 4064 { 4065 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 4066 unsigned long min_sleep_time_us; 4067 4068 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 4069 return; 4070 4071 /* 4072 * last_dme_cmd_tstamp will be 0 only for 1st call to 4073 * this function 4074 */ 4075 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 4076 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 4077 } else { 4078 unsigned long delta = 4079 (unsigned long) ktime_to_us( 4080 ktime_sub(ktime_get(), 4081 hba->last_dme_cmd_tstamp)); 4082 4083 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 4084 min_sleep_time_us = 4085 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 4086 else 4087 return; /* no more delay required */ 4088 } 4089 4090 /* allow sleep for extra 50us if needed */ 4091 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 4092 } 4093 4094 /** 4095 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 4096 * @hba: per adapter instance 4097 * @attr_sel: uic command argument1 4098 * @attr_set: attribute set type as uic command argument2 4099 * @mib_val: setting value as uic command argument3 4100 * @peer: indicate whether peer or local 4101 * 4102 * Return: 0 on success, non-zero value on failure. 4103 */ 4104 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 4105 u8 attr_set, u32 mib_val, u8 peer) 4106 { 4107 struct uic_command uic_cmd = {0}; 4108 static const char *const action[] = { 4109 "dme-set", 4110 "dme-peer-set" 4111 }; 4112 const char *set = action[!!peer]; 4113 int ret; 4114 int retries = UFS_UIC_COMMAND_RETRIES; 4115 4116 uic_cmd.command = peer ? 4117 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 4118 uic_cmd.argument1 = attr_sel; 4119 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 4120 uic_cmd.argument3 = mib_val; 4121 4122 do { 4123 /* for peer attributes we retry upon failure */ 4124 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4125 if (ret) 4126 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4127 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4128 } while (ret && peer && --retries); 4129 4130 if (ret) 4131 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4132 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4133 UFS_UIC_COMMAND_RETRIES - retries); 4134 4135 return ret; 4136 } 4137 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4138 4139 /** 4140 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4141 * @hba: per adapter instance 4142 * @attr_sel: uic command argument1 4143 * @mib_val: the value of the attribute as returned by the UIC command 4144 * @peer: indicate whether peer or local 4145 * 4146 * Return: 0 on success, non-zero value on failure. 4147 */ 4148 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4149 u32 *mib_val, u8 peer) 4150 { 4151 struct uic_command uic_cmd = {0}; 4152 static const char *const action[] = { 4153 "dme-get", 4154 "dme-peer-get" 4155 }; 4156 const char *get = action[!!peer]; 4157 int ret; 4158 int retries = UFS_UIC_COMMAND_RETRIES; 4159 struct ufs_pa_layer_attr orig_pwr_info; 4160 struct ufs_pa_layer_attr temp_pwr_info; 4161 bool pwr_mode_change = false; 4162 4163 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4164 orig_pwr_info = hba->pwr_info; 4165 temp_pwr_info = orig_pwr_info; 4166 4167 if (orig_pwr_info.pwr_tx == FAST_MODE || 4168 orig_pwr_info.pwr_rx == FAST_MODE) { 4169 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4170 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4171 pwr_mode_change = true; 4172 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4173 orig_pwr_info.pwr_rx == SLOW_MODE) { 4174 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4175 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4176 pwr_mode_change = true; 4177 } 4178 if (pwr_mode_change) { 4179 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4180 if (ret) 4181 goto out; 4182 } 4183 } 4184 4185 uic_cmd.command = peer ? 4186 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 4187 uic_cmd.argument1 = attr_sel; 4188 4189 do { 4190 /* for peer attributes we retry upon failure */ 4191 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4192 if (ret) 4193 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4194 get, UIC_GET_ATTR_ID(attr_sel), ret); 4195 } while (ret && peer && --retries); 4196 4197 if (ret) 4198 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4199 get, UIC_GET_ATTR_ID(attr_sel), 4200 UFS_UIC_COMMAND_RETRIES - retries); 4201 4202 if (mib_val && !ret) 4203 *mib_val = uic_cmd.argument3; 4204 4205 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4206 && pwr_mode_change) 4207 ufshcd_change_power_mode(hba, &orig_pwr_info); 4208 out: 4209 return ret; 4210 } 4211 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4212 4213 /** 4214 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4215 * state) and waits for it to take effect. 4216 * 4217 * @hba: per adapter instance 4218 * @cmd: UIC command to execute 4219 * 4220 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4221 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4222 * and device UniPro link and hence it's final completion would be indicated by 4223 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4224 * addition to normal UIC command completion Status (UCCS). This function only 4225 * returns after the relevant status bits indicate the completion. 4226 * 4227 * Return: 0 on success, non-zero value on failure. 4228 */ 4229 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4230 { 4231 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4232 unsigned long flags; 4233 u8 status; 4234 int ret; 4235 bool reenable_intr = false; 4236 4237 mutex_lock(&hba->uic_cmd_mutex); 4238 ufshcd_add_delay_before_dme_cmd(hba); 4239 4240 spin_lock_irqsave(hba->host->host_lock, flags); 4241 if (ufshcd_is_link_broken(hba)) { 4242 ret = -ENOLINK; 4243 goto out_unlock; 4244 } 4245 hba->uic_async_done = &uic_async_done; 4246 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4247 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4248 /* 4249 * Make sure UIC command completion interrupt is disabled before 4250 * issuing UIC command. 4251 */ 4252 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 4253 reenable_intr = true; 4254 } 4255 spin_unlock_irqrestore(hba->host->host_lock, flags); 4256 ret = __ufshcd_send_uic_cmd(hba, cmd, false); 4257 if (ret) { 4258 dev_err(hba->dev, 4259 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4260 cmd->command, cmd->argument3, ret); 4261 goto out; 4262 } 4263 4264 if (!wait_for_completion_timeout(hba->uic_async_done, 4265 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 4266 dev_err(hba->dev, 4267 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4268 cmd->command, cmd->argument3); 4269 4270 if (!cmd->cmd_active) { 4271 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4272 __func__); 4273 goto check_upmcrs; 4274 } 4275 4276 ret = -ETIMEDOUT; 4277 goto out; 4278 } 4279 4280 check_upmcrs: 4281 status = ufshcd_get_upmcrs(hba); 4282 if (status != PWR_LOCAL) { 4283 dev_err(hba->dev, 4284 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4285 cmd->command, status); 4286 ret = (status != PWR_OK) ? status : -1; 4287 } 4288 out: 4289 if (ret) { 4290 ufshcd_print_host_state(hba); 4291 ufshcd_print_pwr_info(hba); 4292 ufshcd_print_evt_hist(hba); 4293 } 4294 4295 spin_lock_irqsave(hba->host->host_lock, flags); 4296 hba->active_uic_cmd = NULL; 4297 hba->uic_async_done = NULL; 4298 if (reenable_intr) 4299 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4300 if (ret) { 4301 ufshcd_set_link_broken(hba); 4302 ufshcd_schedule_eh_work(hba); 4303 } 4304 out_unlock: 4305 spin_unlock_irqrestore(hba->host->host_lock, flags); 4306 mutex_unlock(&hba->uic_cmd_mutex); 4307 4308 return ret; 4309 } 4310 4311 /** 4312 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4313 * using DME_SET primitives. 4314 * @hba: per adapter instance 4315 * @mode: powr mode value 4316 * 4317 * Return: 0 on success, non-zero value on failure. 4318 */ 4319 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4320 { 4321 struct uic_command uic_cmd = {0}; 4322 int ret; 4323 4324 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4325 ret = ufshcd_dme_set(hba, 4326 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4327 if (ret) { 4328 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4329 __func__, ret); 4330 goto out; 4331 } 4332 } 4333 4334 uic_cmd.command = UIC_CMD_DME_SET; 4335 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 4336 uic_cmd.argument3 = mode; 4337 ufshcd_hold(hba); 4338 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4339 ufshcd_release(hba); 4340 4341 out: 4342 return ret; 4343 } 4344 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4345 4346 int ufshcd_link_recovery(struct ufs_hba *hba) 4347 { 4348 int ret; 4349 unsigned long flags; 4350 4351 spin_lock_irqsave(hba->host->host_lock, flags); 4352 hba->ufshcd_state = UFSHCD_STATE_RESET; 4353 ufshcd_set_eh_in_progress(hba); 4354 spin_unlock_irqrestore(hba->host->host_lock, flags); 4355 4356 /* Reset the attached device */ 4357 ufshcd_device_reset(hba); 4358 4359 ret = ufshcd_host_reset_and_restore(hba); 4360 4361 spin_lock_irqsave(hba->host->host_lock, flags); 4362 if (ret) 4363 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4364 ufshcd_clear_eh_in_progress(hba); 4365 spin_unlock_irqrestore(hba->host->host_lock, flags); 4366 4367 if (ret) 4368 dev_err(hba->dev, "%s: link recovery failed, err %d", 4369 __func__, ret); 4370 4371 return ret; 4372 } 4373 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4374 4375 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4376 { 4377 int ret; 4378 struct uic_command uic_cmd = {0}; 4379 ktime_t start = ktime_get(); 4380 4381 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4382 4383 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER; 4384 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4385 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4386 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4387 4388 if (ret) 4389 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4390 __func__, ret); 4391 else 4392 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4393 POST_CHANGE); 4394 4395 return ret; 4396 } 4397 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4398 4399 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4400 { 4401 struct uic_command uic_cmd = {0}; 4402 int ret; 4403 ktime_t start = ktime_get(); 4404 4405 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4406 4407 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT; 4408 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4409 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4410 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4411 4412 if (ret) { 4413 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4414 __func__, ret); 4415 } else { 4416 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4417 POST_CHANGE); 4418 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4419 hba->ufs_stats.hibern8_exit_cnt++; 4420 } 4421 4422 return ret; 4423 } 4424 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4425 4426 static void ufshcd_configure_auto_hibern8(struct ufs_hba *hba) 4427 { 4428 if (!ufshcd_is_auto_hibern8_supported(hba)) 4429 return; 4430 4431 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4432 } 4433 4434 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4435 { 4436 const u32 cur_ahit = READ_ONCE(hba->ahit); 4437 4438 if (!ufshcd_is_auto_hibern8_supported(hba) || cur_ahit == ahit) 4439 return; 4440 4441 WRITE_ONCE(hba->ahit, ahit); 4442 if (!pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4443 ufshcd_rpm_get_sync(hba); 4444 ufshcd_hold(hba); 4445 ufshcd_configure_auto_hibern8(hba); 4446 ufshcd_release(hba); 4447 ufshcd_rpm_put_sync(hba); 4448 } 4449 } 4450 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4451 4452 /** 4453 * ufshcd_init_pwr_info - setting the POR (power on reset) 4454 * values in hba power info 4455 * @hba: per-adapter instance 4456 */ 4457 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4458 { 4459 hba->pwr_info.gear_rx = UFS_PWM_G1; 4460 hba->pwr_info.gear_tx = UFS_PWM_G1; 4461 hba->pwr_info.lane_rx = UFS_LANE_1; 4462 hba->pwr_info.lane_tx = UFS_LANE_1; 4463 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4464 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4465 hba->pwr_info.hs_rate = 0; 4466 } 4467 4468 /** 4469 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4470 * @hba: per-adapter instance 4471 * 4472 * Return: 0 upon success; < 0 upon failure. 4473 */ 4474 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4475 { 4476 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4477 4478 if (hba->max_pwr_info.is_valid) 4479 return 0; 4480 4481 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4482 pwr_info->pwr_tx = FASTAUTO_MODE; 4483 pwr_info->pwr_rx = FASTAUTO_MODE; 4484 } else { 4485 pwr_info->pwr_tx = FAST_MODE; 4486 pwr_info->pwr_rx = FAST_MODE; 4487 } 4488 pwr_info->hs_rate = PA_HS_MODE_B; 4489 4490 /* Get the connected lane count */ 4491 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4492 &pwr_info->lane_rx); 4493 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4494 &pwr_info->lane_tx); 4495 4496 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4497 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4498 __func__, 4499 pwr_info->lane_rx, 4500 pwr_info->lane_tx); 4501 return -EINVAL; 4502 } 4503 4504 /* 4505 * First, get the maximum gears of HS speed. 4506 * If a zero value, it means there is no HSGEAR capability. 4507 * Then, get the maximum gears of PWM speed. 4508 */ 4509 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4510 if (!pwr_info->gear_rx) { 4511 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4512 &pwr_info->gear_rx); 4513 if (!pwr_info->gear_rx) { 4514 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4515 __func__, pwr_info->gear_rx); 4516 return -EINVAL; 4517 } 4518 pwr_info->pwr_rx = SLOW_MODE; 4519 } 4520 4521 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4522 &pwr_info->gear_tx); 4523 if (!pwr_info->gear_tx) { 4524 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4525 &pwr_info->gear_tx); 4526 if (!pwr_info->gear_tx) { 4527 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4528 __func__, pwr_info->gear_tx); 4529 return -EINVAL; 4530 } 4531 pwr_info->pwr_tx = SLOW_MODE; 4532 } 4533 4534 hba->max_pwr_info.is_valid = true; 4535 return 0; 4536 } 4537 4538 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4539 struct ufs_pa_layer_attr *pwr_mode) 4540 { 4541 int ret; 4542 4543 /* if already configured to the requested pwr_mode */ 4544 if (!hba->force_pmc && 4545 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4546 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4547 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4548 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4549 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4550 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4551 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4552 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4553 return 0; 4554 } 4555 4556 /* 4557 * Configure attributes for power mode change with below. 4558 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4559 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4560 * - PA_HSSERIES 4561 */ 4562 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4563 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4564 pwr_mode->lane_rx); 4565 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4566 pwr_mode->pwr_rx == FAST_MODE) 4567 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4568 else 4569 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4570 4571 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4572 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4573 pwr_mode->lane_tx); 4574 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4575 pwr_mode->pwr_tx == FAST_MODE) 4576 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4577 else 4578 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4579 4580 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4581 pwr_mode->pwr_tx == FASTAUTO_MODE || 4582 pwr_mode->pwr_rx == FAST_MODE || 4583 pwr_mode->pwr_tx == FAST_MODE) 4584 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4585 pwr_mode->hs_rate); 4586 4587 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4588 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4589 DL_FC0ProtectionTimeOutVal_Default); 4590 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4591 DL_TC0ReplayTimeOutVal_Default); 4592 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4593 DL_AFC0ReqTimeOutVal_Default); 4594 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4595 DL_FC1ProtectionTimeOutVal_Default); 4596 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4597 DL_TC1ReplayTimeOutVal_Default); 4598 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4599 DL_AFC1ReqTimeOutVal_Default); 4600 4601 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4602 DL_FC0ProtectionTimeOutVal_Default); 4603 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4604 DL_TC0ReplayTimeOutVal_Default); 4605 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4606 DL_AFC0ReqTimeOutVal_Default); 4607 } 4608 4609 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4610 | pwr_mode->pwr_tx); 4611 4612 if (ret) { 4613 dev_err(hba->dev, 4614 "%s: power mode change failed %d\n", __func__, ret); 4615 } else { 4616 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4617 pwr_mode); 4618 4619 memcpy(&hba->pwr_info, pwr_mode, 4620 sizeof(struct ufs_pa_layer_attr)); 4621 } 4622 4623 return ret; 4624 } 4625 4626 /** 4627 * ufshcd_config_pwr_mode - configure a new power mode 4628 * @hba: per-adapter instance 4629 * @desired_pwr_mode: desired power configuration 4630 * 4631 * Return: 0 upon success; < 0 upon failure. 4632 */ 4633 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4634 struct ufs_pa_layer_attr *desired_pwr_mode) 4635 { 4636 struct ufs_pa_layer_attr final_params = { 0 }; 4637 int ret; 4638 4639 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4640 desired_pwr_mode, &final_params); 4641 4642 if (ret) 4643 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4644 4645 ret = ufshcd_change_power_mode(hba, &final_params); 4646 4647 return ret; 4648 } 4649 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4650 4651 /** 4652 * ufshcd_complete_dev_init() - checks device readiness 4653 * @hba: per-adapter instance 4654 * 4655 * Set fDeviceInit flag and poll until device toggles it. 4656 * 4657 * Return: 0 upon success; < 0 upon failure. 4658 */ 4659 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4660 { 4661 int err; 4662 bool flag_res = true; 4663 ktime_t timeout; 4664 4665 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4666 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4667 if (err) { 4668 dev_err(hba->dev, 4669 "%s: setting fDeviceInit flag failed with error %d\n", 4670 __func__, err); 4671 goto out; 4672 } 4673 4674 /* Poll fDeviceInit flag to be cleared */ 4675 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4676 do { 4677 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4678 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4679 if (!flag_res) 4680 break; 4681 usleep_range(500, 1000); 4682 } while (ktime_before(ktime_get(), timeout)); 4683 4684 if (err) { 4685 dev_err(hba->dev, 4686 "%s: reading fDeviceInit flag failed with error %d\n", 4687 __func__, err); 4688 } else if (flag_res) { 4689 dev_err(hba->dev, 4690 "%s: fDeviceInit was not cleared by the device\n", 4691 __func__); 4692 err = -EBUSY; 4693 } 4694 out: 4695 return err; 4696 } 4697 4698 /** 4699 * ufshcd_make_hba_operational - Make UFS controller operational 4700 * @hba: per adapter instance 4701 * 4702 * To bring UFS host controller to operational state, 4703 * 1. Enable required interrupts 4704 * 2. Configure interrupt aggregation 4705 * 3. Program UTRL and UTMRL base address 4706 * 4. Configure run-stop-registers 4707 * 4708 * Return: 0 on success, non-zero value on failure. 4709 */ 4710 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4711 { 4712 int err = 0; 4713 u32 reg; 4714 4715 /* Enable required interrupts */ 4716 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4717 4718 /* Configure interrupt aggregation */ 4719 if (ufshcd_is_intr_aggr_allowed(hba)) 4720 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4721 else 4722 ufshcd_disable_intr_aggr(hba); 4723 4724 /* Configure UTRL and UTMRL base address registers */ 4725 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4726 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4727 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4728 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4729 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4730 REG_UTP_TASK_REQ_LIST_BASE_L); 4731 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4732 REG_UTP_TASK_REQ_LIST_BASE_H); 4733 4734 /* 4735 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4736 */ 4737 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4738 if (!(ufshcd_get_lists_status(reg))) { 4739 ufshcd_enable_run_stop_reg(hba); 4740 } else { 4741 dev_err(hba->dev, 4742 "Host controller not ready to process requests"); 4743 err = -EIO; 4744 } 4745 4746 return err; 4747 } 4748 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4749 4750 /** 4751 * ufshcd_hba_stop - Send controller to reset state 4752 * @hba: per adapter instance 4753 */ 4754 void ufshcd_hba_stop(struct ufs_hba *hba) 4755 { 4756 unsigned long flags; 4757 int err; 4758 4759 /* 4760 * Obtain the host lock to prevent that the controller is disabled 4761 * while the UFS interrupt handler is active on another CPU. 4762 */ 4763 spin_lock_irqsave(hba->host->host_lock, flags); 4764 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4765 spin_unlock_irqrestore(hba->host->host_lock, flags); 4766 4767 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4768 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4769 10, 1); 4770 if (err) 4771 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4772 } 4773 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4774 4775 /** 4776 * ufshcd_hba_execute_hce - initialize the controller 4777 * @hba: per adapter instance 4778 * 4779 * The controller resets itself and controller firmware initialization 4780 * sequence kicks off. When controller is ready it will set 4781 * the Host Controller Enable bit to 1. 4782 * 4783 * Return: 0 on success, non-zero value on failure. 4784 */ 4785 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4786 { 4787 int retry_outer = 3; 4788 int retry_inner; 4789 4790 start: 4791 if (ufshcd_is_hba_active(hba)) 4792 /* change controller state to "reset state" */ 4793 ufshcd_hba_stop(hba); 4794 4795 /* UniPro link is disabled at this point */ 4796 ufshcd_set_link_off(hba); 4797 4798 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4799 4800 /* start controller initialization sequence */ 4801 ufshcd_hba_start(hba); 4802 4803 /* 4804 * To initialize a UFS host controller HCE bit must be set to 1. 4805 * During initialization the HCE bit value changes from 1->0->1. 4806 * When the host controller completes initialization sequence 4807 * it sets the value of HCE bit to 1. The same HCE bit is read back 4808 * to check if the controller has completed initialization sequence. 4809 * So without this delay the value HCE = 1, set in the previous 4810 * instruction might be read back. 4811 * This delay can be changed based on the controller. 4812 */ 4813 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4814 4815 /* wait for the host controller to complete initialization */ 4816 retry_inner = 50; 4817 while (!ufshcd_is_hba_active(hba)) { 4818 if (retry_inner) { 4819 retry_inner--; 4820 } else { 4821 dev_err(hba->dev, 4822 "Controller enable failed\n"); 4823 if (retry_outer) { 4824 retry_outer--; 4825 goto start; 4826 } 4827 return -EIO; 4828 } 4829 usleep_range(1000, 1100); 4830 } 4831 4832 /* enable UIC related interrupts */ 4833 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4834 4835 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4836 4837 return 0; 4838 } 4839 4840 int ufshcd_hba_enable(struct ufs_hba *hba) 4841 { 4842 int ret; 4843 4844 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4845 ufshcd_set_link_off(hba); 4846 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4847 4848 /* enable UIC related interrupts */ 4849 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4850 ret = ufshcd_dme_reset(hba); 4851 if (ret) { 4852 dev_err(hba->dev, "DME_RESET failed\n"); 4853 return ret; 4854 } 4855 4856 ret = ufshcd_dme_enable(hba); 4857 if (ret) { 4858 dev_err(hba->dev, "Enabling DME failed\n"); 4859 return ret; 4860 } 4861 4862 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4863 } else { 4864 ret = ufshcd_hba_execute_hce(hba); 4865 } 4866 4867 return ret; 4868 } 4869 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4870 4871 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4872 { 4873 int tx_lanes = 0, i, err = 0; 4874 4875 if (!peer) 4876 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4877 &tx_lanes); 4878 else 4879 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4880 &tx_lanes); 4881 for (i = 0; i < tx_lanes; i++) { 4882 if (!peer) 4883 err = ufshcd_dme_set(hba, 4884 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4885 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4886 0); 4887 else 4888 err = ufshcd_dme_peer_set(hba, 4889 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4890 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4891 0); 4892 if (err) { 4893 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4894 __func__, peer, i, err); 4895 break; 4896 } 4897 } 4898 4899 return err; 4900 } 4901 4902 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4903 { 4904 return ufshcd_disable_tx_lcc(hba, true); 4905 } 4906 4907 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4908 { 4909 struct ufs_event_hist *e; 4910 4911 if (id >= UFS_EVT_CNT) 4912 return; 4913 4914 e = &hba->ufs_stats.event[id]; 4915 e->val[e->pos] = val; 4916 e->tstamp[e->pos] = local_clock(); 4917 e->cnt += 1; 4918 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4919 4920 ufshcd_vops_event_notify(hba, id, &val); 4921 } 4922 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4923 4924 /** 4925 * ufshcd_link_startup - Initialize unipro link startup 4926 * @hba: per adapter instance 4927 * 4928 * Return: 0 for success, non-zero in case of failure. 4929 */ 4930 static int ufshcd_link_startup(struct ufs_hba *hba) 4931 { 4932 int ret; 4933 int retries = DME_LINKSTARTUP_RETRIES; 4934 bool link_startup_again = false; 4935 4936 /* 4937 * If UFS device isn't active then we will have to issue link startup 4938 * 2 times to make sure the device state move to active. 4939 */ 4940 if (!ufshcd_is_ufs_dev_active(hba)) 4941 link_startup_again = true; 4942 4943 link_startup: 4944 do { 4945 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4946 4947 ret = ufshcd_dme_link_startup(hba); 4948 4949 /* check if device is detected by inter-connect layer */ 4950 if (!ret && !ufshcd_is_device_present(hba)) { 4951 ufshcd_update_evt_hist(hba, 4952 UFS_EVT_LINK_STARTUP_FAIL, 4953 0); 4954 dev_err(hba->dev, "%s: Device not present\n", __func__); 4955 ret = -ENXIO; 4956 goto out; 4957 } 4958 4959 /* 4960 * DME link lost indication is only received when link is up, 4961 * but we can't be sure if the link is up until link startup 4962 * succeeds. So reset the local Uni-Pro and try again. 4963 */ 4964 if (ret && retries && ufshcd_hba_enable(hba)) { 4965 ufshcd_update_evt_hist(hba, 4966 UFS_EVT_LINK_STARTUP_FAIL, 4967 (u32)ret); 4968 goto out; 4969 } 4970 } while (ret && retries--); 4971 4972 if (ret) { 4973 /* failed to get the link up... retire */ 4974 ufshcd_update_evt_hist(hba, 4975 UFS_EVT_LINK_STARTUP_FAIL, 4976 (u32)ret); 4977 goto out; 4978 } 4979 4980 if (link_startup_again) { 4981 link_startup_again = false; 4982 retries = DME_LINKSTARTUP_RETRIES; 4983 goto link_startup; 4984 } 4985 4986 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 4987 ufshcd_init_pwr_info(hba); 4988 ufshcd_print_pwr_info(hba); 4989 4990 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 4991 ret = ufshcd_disable_device_tx_lcc(hba); 4992 if (ret) 4993 goto out; 4994 } 4995 4996 /* Include any host controller configuration via UIC commands */ 4997 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 4998 if (ret) 4999 goto out; 5000 5001 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 5002 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 5003 ret = ufshcd_make_hba_operational(hba); 5004 out: 5005 if (ret) { 5006 dev_err(hba->dev, "link startup failed %d\n", ret); 5007 ufshcd_print_host_state(hba); 5008 ufshcd_print_pwr_info(hba); 5009 ufshcd_print_evt_hist(hba); 5010 } 5011 return ret; 5012 } 5013 5014 /** 5015 * ufshcd_verify_dev_init() - Verify device initialization 5016 * @hba: per-adapter instance 5017 * 5018 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 5019 * device Transport Protocol (UTP) layer is ready after a reset. 5020 * If the UTP layer at the device side is not initialized, it may 5021 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 5022 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 5023 * 5024 * Return: 0 upon success; < 0 upon failure. 5025 */ 5026 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 5027 { 5028 int err = 0; 5029 int retries; 5030 5031 ufshcd_dev_man_lock(hba); 5032 5033 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 5034 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 5035 hba->nop_out_timeout); 5036 5037 if (!err || err == -ETIMEDOUT) 5038 break; 5039 5040 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 5041 } 5042 5043 ufshcd_dev_man_unlock(hba); 5044 5045 if (err) 5046 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 5047 return err; 5048 } 5049 5050 /** 5051 * ufshcd_setup_links - associate link b/w device wlun and other luns 5052 * @sdev: pointer to SCSI device 5053 * @hba: pointer to ufs hba 5054 */ 5055 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 5056 { 5057 struct device_link *link; 5058 5059 /* 5060 * Device wlun is the supplier & rest of the luns are consumers. 5061 * This ensures that device wlun suspends after all other luns. 5062 */ 5063 if (hba->ufs_device_wlun) { 5064 link = device_link_add(&sdev->sdev_gendev, 5065 &hba->ufs_device_wlun->sdev_gendev, 5066 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 5067 if (!link) { 5068 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 5069 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 5070 return; 5071 } 5072 hba->luns_avail--; 5073 /* Ignore REPORT_LUN wlun probing */ 5074 if (hba->luns_avail == 1) { 5075 ufshcd_rpm_put(hba); 5076 return; 5077 } 5078 } else { 5079 /* 5080 * Device wlun is probed. The assumption is that WLUNs are 5081 * scanned before other LUNs. 5082 */ 5083 hba->luns_avail--; 5084 } 5085 } 5086 5087 /** 5088 * ufshcd_lu_init - Initialize the relevant parameters of the LU 5089 * @hba: per-adapter instance 5090 * @sdev: pointer to SCSI device 5091 */ 5092 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 5093 { 5094 int len = QUERY_DESC_MAX_SIZE; 5095 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 5096 u8 lun_qdepth = hba->nutrs; 5097 u8 *desc_buf; 5098 int ret; 5099 5100 desc_buf = kzalloc(len, GFP_KERNEL); 5101 if (!desc_buf) 5102 goto set_qdepth; 5103 5104 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5105 if (ret < 0) { 5106 if (ret == -EOPNOTSUPP) 5107 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5108 lun_qdepth = 1; 5109 kfree(desc_buf); 5110 goto set_qdepth; 5111 } 5112 5113 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5114 /* 5115 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5116 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5117 */ 5118 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5119 } 5120 /* 5121 * According to UFS device specification, the write protection mode is only supported by 5122 * normal LU, not supported by WLUN. 5123 */ 5124 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5125 !hba->dev_info.is_lu_power_on_wp && 5126 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5127 hba->dev_info.is_lu_power_on_wp = true; 5128 5129 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5130 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5131 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5132 hba->dev_info.b_advanced_rpmb_en = true; 5133 5134 5135 kfree(desc_buf); 5136 set_qdepth: 5137 /* 5138 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5139 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5140 */ 5141 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5142 scsi_change_queue_depth(sdev, lun_qdepth); 5143 } 5144 5145 /** 5146 * ufshcd_slave_alloc - handle initial SCSI device configurations 5147 * @sdev: pointer to SCSI device 5148 * 5149 * Return: success. 5150 */ 5151 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5152 { 5153 struct ufs_hba *hba; 5154 5155 hba = shost_priv(sdev->host); 5156 5157 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5158 sdev->use_10_for_ms = 1; 5159 5160 /* DBD field should be set to 1 in mode sense(10) */ 5161 sdev->set_dbd_for_ms = 1; 5162 5163 /* allow SCSI layer to restart the device in case of errors */ 5164 sdev->allow_restart = 1; 5165 5166 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5167 sdev->no_report_opcodes = 1; 5168 5169 /* WRITE_SAME command is not supported */ 5170 sdev->no_write_same = 1; 5171 5172 ufshcd_lu_init(hba, sdev); 5173 5174 ufshcd_setup_links(hba, sdev); 5175 5176 return 0; 5177 } 5178 5179 /** 5180 * ufshcd_change_queue_depth - change queue depth 5181 * @sdev: pointer to SCSI device 5182 * @depth: required depth to set 5183 * 5184 * Change queue depth and make sure the max. limits are not crossed. 5185 * 5186 * Return: new queue depth. 5187 */ 5188 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5189 { 5190 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5191 } 5192 5193 /** 5194 * ufshcd_slave_configure - adjust SCSI device configurations 5195 * @sdev: pointer to SCSI device 5196 * 5197 * Return: 0 (success). 5198 */ 5199 static int ufshcd_slave_configure(struct scsi_device *sdev) 5200 { 5201 struct ufs_hba *hba = shost_priv(sdev->host); 5202 struct request_queue *q = sdev->request_queue; 5203 5204 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1); 5205 5206 /* 5207 * Block runtime-pm until all consumers are added. 5208 * Refer ufshcd_setup_links(). 5209 */ 5210 if (is_device_wlun(sdev)) 5211 pm_runtime_get_noresume(&sdev->sdev_gendev); 5212 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5213 sdev->rpm_autosuspend = 1; 5214 /* 5215 * Do not print messages during runtime PM to avoid never-ending cycles 5216 * of messages written back to storage by user space causing runtime 5217 * resume, causing more messages and so on. 5218 */ 5219 sdev->silence_suspend = 1; 5220 5221 ufshcd_crypto_register(hba, q); 5222 5223 return 0; 5224 } 5225 5226 /** 5227 * ufshcd_slave_destroy - remove SCSI device configurations 5228 * @sdev: pointer to SCSI device 5229 */ 5230 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5231 { 5232 struct ufs_hba *hba; 5233 unsigned long flags; 5234 5235 hba = shost_priv(sdev->host); 5236 5237 /* Drop the reference as it won't be needed anymore */ 5238 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5239 spin_lock_irqsave(hba->host->host_lock, flags); 5240 hba->ufs_device_wlun = NULL; 5241 spin_unlock_irqrestore(hba->host->host_lock, flags); 5242 } else if (hba->ufs_device_wlun) { 5243 struct device *supplier = NULL; 5244 5245 /* Ensure UFS Device WLUN exists and does not disappear */ 5246 spin_lock_irqsave(hba->host->host_lock, flags); 5247 if (hba->ufs_device_wlun) { 5248 supplier = &hba->ufs_device_wlun->sdev_gendev; 5249 get_device(supplier); 5250 } 5251 spin_unlock_irqrestore(hba->host->host_lock, flags); 5252 5253 if (supplier) { 5254 /* 5255 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5256 * device will not have been registered but can still 5257 * have a device link holding a reference to the device. 5258 */ 5259 device_link_remove(&sdev->sdev_gendev, supplier); 5260 put_device(supplier); 5261 } 5262 } 5263 } 5264 5265 /** 5266 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5267 * @lrbp: pointer to local reference block of completed command 5268 * @scsi_status: SCSI command status 5269 * 5270 * Return: value base on SCSI command status. 5271 */ 5272 static inline int 5273 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5274 { 5275 int result = 0; 5276 5277 switch (scsi_status) { 5278 case SAM_STAT_CHECK_CONDITION: 5279 ufshcd_copy_sense_data(lrbp); 5280 fallthrough; 5281 case SAM_STAT_GOOD: 5282 result |= DID_OK << 16 | scsi_status; 5283 break; 5284 case SAM_STAT_TASK_SET_FULL: 5285 case SAM_STAT_BUSY: 5286 case SAM_STAT_TASK_ABORTED: 5287 ufshcd_copy_sense_data(lrbp); 5288 result |= scsi_status; 5289 break; 5290 default: 5291 result |= DID_ERROR << 16; 5292 break; 5293 } /* end of switch */ 5294 5295 return result; 5296 } 5297 5298 /** 5299 * ufshcd_transfer_rsp_status - Get overall status of the response 5300 * @hba: per adapter instance 5301 * @lrbp: pointer to local reference block of completed command 5302 * @cqe: pointer to the completion queue entry 5303 * 5304 * Return: result of the command to notify SCSI midlayer. 5305 */ 5306 static inline int 5307 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5308 struct cq_entry *cqe) 5309 { 5310 int result = 0; 5311 int scsi_status; 5312 enum utp_ocs ocs; 5313 u8 upiu_flags; 5314 u32 resid; 5315 5316 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5317 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5318 /* 5319 * Test !overflow instead of underflow to support UFS devices that do 5320 * not set either flag. 5321 */ 5322 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5323 scsi_set_resid(lrbp->cmd, resid); 5324 5325 /* overall command status of utrd */ 5326 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5327 5328 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5329 if (lrbp->ucd_rsp_ptr->header.response || 5330 lrbp->ucd_rsp_ptr->header.status) 5331 ocs = OCS_SUCCESS; 5332 } 5333 5334 switch (ocs) { 5335 case OCS_SUCCESS: 5336 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5337 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5338 case UPIU_TRANSACTION_RESPONSE: 5339 /* 5340 * get the result based on SCSI status response 5341 * to notify the SCSI midlayer of the command status 5342 */ 5343 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5344 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5345 5346 /* 5347 * Currently we are only supporting BKOPs exception 5348 * events hence we can ignore BKOPs exception event 5349 * during power management callbacks. BKOPs exception 5350 * event is not expected to be raised in runtime suspend 5351 * callback as it allows the urgent bkops. 5352 * During system suspend, we are anyway forcefully 5353 * disabling the bkops and if urgent bkops is needed 5354 * it will be enabled on system resume. Long term 5355 * solution could be to abort the system suspend if 5356 * UFS device needs urgent BKOPs. 5357 */ 5358 if (!hba->pm_op_in_progress && 5359 !ufshcd_eh_in_progress(hba) && 5360 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5361 /* Flushed in suspend */ 5362 schedule_work(&hba->eeh_work); 5363 break; 5364 case UPIU_TRANSACTION_REJECT_UPIU: 5365 /* TODO: handle Reject UPIU Response */ 5366 result = DID_ERROR << 16; 5367 dev_err(hba->dev, 5368 "Reject UPIU not fully implemented\n"); 5369 break; 5370 default: 5371 dev_err(hba->dev, 5372 "Unexpected request response code = %x\n", 5373 result); 5374 result = DID_ERROR << 16; 5375 break; 5376 } 5377 break; 5378 case OCS_ABORTED: 5379 result |= DID_ABORT << 16; 5380 break; 5381 case OCS_INVALID_COMMAND_STATUS: 5382 result |= DID_REQUEUE << 16; 5383 break; 5384 case OCS_INVALID_CMD_TABLE_ATTR: 5385 case OCS_INVALID_PRDT_ATTR: 5386 case OCS_MISMATCH_DATA_BUF_SIZE: 5387 case OCS_MISMATCH_RESP_UPIU_SIZE: 5388 case OCS_PEER_COMM_FAILURE: 5389 case OCS_FATAL_ERROR: 5390 case OCS_DEVICE_FATAL_ERROR: 5391 case OCS_INVALID_CRYPTO_CONFIG: 5392 case OCS_GENERAL_CRYPTO_ERROR: 5393 default: 5394 result |= DID_ERROR << 16; 5395 dev_err(hba->dev, 5396 "OCS error from controller = %x for tag %d\n", 5397 ocs, lrbp->task_tag); 5398 ufshcd_print_evt_hist(hba); 5399 ufshcd_print_host_state(hba); 5400 break; 5401 } /* end of switch */ 5402 5403 if ((host_byte(result) != DID_OK) && 5404 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5405 ufshcd_print_tr(hba, lrbp->task_tag, true); 5406 return result; 5407 } 5408 5409 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5410 u32 intr_mask) 5411 { 5412 if (!ufshcd_is_auto_hibern8_supported(hba) || 5413 !ufshcd_is_auto_hibern8_enabled(hba)) 5414 return false; 5415 5416 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5417 return false; 5418 5419 if (hba->active_uic_cmd && 5420 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5421 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5422 return false; 5423 5424 return true; 5425 } 5426 5427 /** 5428 * ufshcd_uic_cmd_compl - handle completion of uic command 5429 * @hba: per adapter instance 5430 * @intr_status: interrupt status generated by the controller 5431 * 5432 * Return: 5433 * IRQ_HANDLED - If interrupt is valid 5434 * IRQ_NONE - If invalid interrupt 5435 */ 5436 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5437 { 5438 irqreturn_t retval = IRQ_NONE; 5439 5440 spin_lock(hba->host->host_lock); 5441 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5442 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5443 5444 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { 5445 hba->active_uic_cmd->argument2 |= 5446 ufshcd_get_uic_cmd_result(hba); 5447 hba->active_uic_cmd->argument3 = 5448 ufshcd_get_dme_attr_val(hba); 5449 if (!hba->uic_async_done) 5450 hba->active_uic_cmd->cmd_active = 0; 5451 complete(&hba->active_uic_cmd->done); 5452 retval = IRQ_HANDLED; 5453 } 5454 5455 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { 5456 hba->active_uic_cmd->cmd_active = 0; 5457 complete(hba->uic_async_done); 5458 retval = IRQ_HANDLED; 5459 } 5460 5461 if (retval == IRQ_HANDLED) 5462 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd, 5463 UFS_CMD_COMP); 5464 spin_unlock(hba->host->host_lock); 5465 return retval; 5466 } 5467 5468 /* Release the resources allocated for processing a SCSI command. */ 5469 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5470 struct ufshcd_lrb *lrbp) 5471 { 5472 struct scsi_cmnd *cmd = lrbp->cmd; 5473 5474 scsi_dma_unmap(cmd); 5475 ufshcd_release(hba); 5476 ufshcd_clk_scaling_update_busy(hba); 5477 } 5478 5479 /** 5480 * ufshcd_compl_one_cqe - handle a completion queue entry 5481 * @hba: per adapter instance 5482 * @task_tag: the task tag of the request to be completed 5483 * @cqe: pointer to the completion queue entry 5484 */ 5485 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5486 struct cq_entry *cqe) 5487 { 5488 struct ufshcd_lrb *lrbp; 5489 struct scsi_cmnd *cmd; 5490 enum utp_ocs ocs; 5491 5492 lrbp = &hba->lrb[task_tag]; 5493 lrbp->compl_time_stamp = ktime_get(); 5494 cmd = lrbp->cmd; 5495 if (cmd) { 5496 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5497 ufshcd_update_monitor(hba, lrbp); 5498 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5499 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5500 ufshcd_release_scsi_cmd(hba, lrbp); 5501 /* Do not touch lrbp after scsi done */ 5502 scsi_done(cmd); 5503 } else if (hba->dev_cmd.complete) { 5504 if (cqe) { 5505 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5506 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5507 } 5508 complete(hba->dev_cmd.complete); 5509 } 5510 } 5511 5512 /** 5513 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5514 * @hba: per adapter instance 5515 * @completed_reqs: bitmask that indicates which requests to complete 5516 */ 5517 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5518 unsigned long completed_reqs) 5519 { 5520 int tag; 5521 5522 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5523 ufshcd_compl_one_cqe(hba, tag, NULL); 5524 } 5525 5526 /* Any value that is not an existing queue number is fine for this constant. */ 5527 enum { 5528 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5529 }; 5530 5531 static void ufshcd_clear_polled(struct ufs_hba *hba, 5532 unsigned long *completed_reqs) 5533 { 5534 int tag; 5535 5536 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5537 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5538 5539 if (!cmd) 5540 continue; 5541 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5542 __clear_bit(tag, completed_reqs); 5543 } 5544 } 5545 5546 /* 5547 * Return: > 0 if one or more commands have been completed or 0 if no 5548 * requests have been completed. 5549 */ 5550 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5551 { 5552 struct ufs_hba *hba = shost_priv(shost); 5553 unsigned long completed_reqs, flags; 5554 u32 tr_doorbell; 5555 struct ufs_hw_queue *hwq; 5556 5557 if (is_mcq_enabled(hba)) { 5558 hwq = &hba->uhq[queue_num]; 5559 5560 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5561 } 5562 5563 spin_lock_irqsave(&hba->outstanding_lock, flags); 5564 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5565 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5566 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5567 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5568 hba->outstanding_reqs); 5569 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5570 /* Do not complete polled requests from interrupt context. */ 5571 ufshcd_clear_polled(hba, &completed_reqs); 5572 } 5573 hba->outstanding_reqs &= ~completed_reqs; 5574 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5575 5576 if (completed_reqs) 5577 __ufshcd_transfer_req_compl(hba, completed_reqs); 5578 5579 return completed_reqs != 0; 5580 } 5581 5582 /** 5583 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5584 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5585 * to complete the pending transfers and free the resources associated with 5586 * the scsi command. 5587 * 5588 * @hba: per adapter instance 5589 * @force_compl: This flag is set to true when invoked 5590 * from ufshcd_host_reset_and_restore() in which case it requires special 5591 * handling because the host controller has been reset by ufshcd_hba_stop(). 5592 */ 5593 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5594 bool force_compl) 5595 { 5596 struct ufs_hw_queue *hwq; 5597 struct ufshcd_lrb *lrbp; 5598 struct scsi_cmnd *cmd; 5599 unsigned long flags; 5600 int tag; 5601 5602 for (tag = 0; tag < hba->nutrs; tag++) { 5603 lrbp = &hba->lrb[tag]; 5604 cmd = lrbp->cmd; 5605 if (!ufshcd_cmd_inflight(cmd) || 5606 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5607 continue; 5608 5609 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 5610 5611 if (force_compl) { 5612 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5613 /* 5614 * For those cmds of which the cqes are not present 5615 * in the cq, complete them explicitly. 5616 */ 5617 spin_lock_irqsave(&hwq->cq_lock, flags); 5618 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5619 set_host_byte(cmd, DID_REQUEUE); 5620 ufshcd_release_scsi_cmd(hba, lrbp); 5621 scsi_done(cmd); 5622 } 5623 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5624 } else { 5625 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5626 } 5627 } 5628 } 5629 5630 /** 5631 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5632 * @hba: per adapter instance 5633 * 5634 * Return: 5635 * IRQ_HANDLED - If interrupt is valid 5636 * IRQ_NONE - If invalid interrupt 5637 */ 5638 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5639 { 5640 /* Resetting interrupt aggregation counters first and reading the 5641 * DOOR_BELL afterward allows us to handle all the completed requests. 5642 * In order to prevent other interrupts starvation the DB is read once 5643 * after reset. The down side of this solution is the possibility of 5644 * false interrupt if device completes another request after resetting 5645 * aggregation and before reading the DB. 5646 */ 5647 if (ufshcd_is_intr_aggr_allowed(hba) && 5648 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5649 ufshcd_reset_intr_aggr(hba); 5650 5651 if (ufs_fail_completion(hba)) 5652 return IRQ_HANDLED; 5653 5654 /* 5655 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5656 * do not want polling to trigger spurious interrupt complaints. 5657 */ 5658 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5659 5660 return IRQ_HANDLED; 5661 } 5662 5663 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5664 { 5665 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5666 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5667 &ee_ctrl_mask); 5668 } 5669 5670 int ufshcd_write_ee_control(struct ufs_hba *hba) 5671 { 5672 int err; 5673 5674 mutex_lock(&hba->ee_ctrl_mutex); 5675 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5676 mutex_unlock(&hba->ee_ctrl_mutex); 5677 if (err) 5678 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5679 __func__, err); 5680 return err; 5681 } 5682 5683 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5684 const u16 *other_mask, u16 set, u16 clr) 5685 { 5686 u16 new_mask, ee_ctrl_mask; 5687 int err = 0; 5688 5689 mutex_lock(&hba->ee_ctrl_mutex); 5690 new_mask = (*mask & ~clr) | set; 5691 ee_ctrl_mask = new_mask | *other_mask; 5692 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5693 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5694 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5695 if (!err) { 5696 hba->ee_ctrl_mask = ee_ctrl_mask; 5697 *mask = new_mask; 5698 } 5699 mutex_unlock(&hba->ee_ctrl_mutex); 5700 return err; 5701 } 5702 5703 /** 5704 * ufshcd_disable_ee - disable exception event 5705 * @hba: per-adapter instance 5706 * @mask: exception event to disable 5707 * 5708 * Disables exception event in the device so that the EVENT_ALERT 5709 * bit is not set. 5710 * 5711 * Return: zero on success, non-zero error value on failure. 5712 */ 5713 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5714 { 5715 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5716 } 5717 5718 /** 5719 * ufshcd_enable_ee - enable exception event 5720 * @hba: per-adapter instance 5721 * @mask: exception event to enable 5722 * 5723 * Enable corresponding exception event in the device to allow 5724 * device to alert host in critical scenarios. 5725 * 5726 * Return: zero on success, non-zero error value on failure. 5727 */ 5728 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5729 { 5730 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5731 } 5732 5733 /** 5734 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5735 * @hba: per-adapter instance 5736 * 5737 * Allow device to manage background operations on its own. Enabling 5738 * this might lead to inconsistent latencies during normal data transfers 5739 * as the device is allowed to manage its own way of handling background 5740 * operations. 5741 * 5742 * Return: zero on success, non-zero on failure. 5743 */ 5744 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5745 { 5746 int err = 0; 5747 5748 if (hba->auto_bkops_enabled) 5749 goto out; 5750 5751 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5752 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5753 if (err) { 5754 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5755 __func__, err); 5756 goto out; 5757 } 5758 5759 hba->auto_bkops_enabled = true; 5760 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5761 5762 /* No need of URGENT_BKOPS exception from the device */ 5763 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5764 if (err) 5765 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5766 __func__, err); 5767 out: 5768 return err; 5769 } 5770 5771 /** 5772 * ufshcd_disable_auto_bkops - block device in doing background operations 5773 * @hba: per-adapter instance 5774 * 5775 * Disabling background operations improves command response latency but 5776 * has drawback of device moving into critical state where the device is 5777 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5778 * host is idle so that BKOPS are managed effectively without any negative 5779 * impacts. 5780 * 5781 * Return: zero on success, non-zero on failure. 5782 */ 5783 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5784 { 5785 int err = 0; 5786 5787 if (!hba->auto_bkops_enabled) 5788 goto out; 5789 5790 /* 5791 * If host assisted BKOPs is to be enabled, make sure 5792 * urgent bkops exception is allowed. 5793 */ 5794 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5795 if (err) { 5796 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5797 __func__, err); 5798 goto out; 5799 } 5800 5801 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5802 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5803 if (err) { 5804 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5805 __func__, err); 5806 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5807 goto out; 5808 } 5809 5810 hba->auto_bkops_enabled = false; 5811 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5812 hba->is_urgent_bkops_lvl_checked = false; 5813 out: 5814 return err; 5815 } 5816 5817 /** 5818 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5819 * @hba: per adapter instance 5820 * 5821 * After a device reset the device may toggle the BKOPS_EN flag 5822 * to default value. The s/w tracking variables should be updated 5823 * as well. This function would change the auto-bkops state based on 5824 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5825 */ 5826 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5827 { 5828 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5829 hba->auto_bkops_enabled = false; 5830 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5831 ufshcd_enable_auto_bkops(hba); 5832 } else { 5833 hba->auto_bkops_enabled = true; 5834 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5835 ufshcd_disable_auto_bkops(hba); 5836 } 5837 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5838 hba->is_urgent_bkops_lvl_checked = false; 5839 } 5840 5841 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5842 { 5843 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5844 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5845 } 5846 5847 /** 5848 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5849 * @hba: per-adapter instance 5850 * @status: bkops_status value 5851 * 5852 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5853 * flag in the device to permit background operations if the device 5854 * bkops_status is greater than or equal to "status" argument passed to 5855 * this function, disable otherwise. 5856 * 5857 * Return: 0 for success, non-zero in case of failure. 5858 * 5859 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5860 * to know whether auto bkops is enabled or disabled after this function 5861 * returns control to it. 5862 */ 5863 static int ufshcd_bkops_ctrl(struct ufs_hba *hba, 5864 enum bkops_status status) 5865 { 5866 int err; 5867 u32 curr_status = 0; 5868 5869 err = ufshcd_get_bkops_status(hba, &curr_status); 5870 if (err) { 5871 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5872 __func__, err); 5873 goto out; 5874 } else if (curr_status > BKOPS_STATUS_MAX) { 5875 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5876 __func__, curr_status); 5877 err = -EINVAL; 5878 goto out; 5879 } 5880 5881 if (curr_status >= status) 5882 err = ufshcd_enable_auto_bkops(hba); 5883 else 5884 err = ufshcd_disable_auto_bkops(hba); 5885 out: 5886 return err; 5887 } 5888 5889 /** 5890 * ufshcd_urgent_bkops - handle urgent bkops exception event 5891 * @hba: per-adapter instance 5892 * 5893 * Enable fBackgroundOpsEn flag in the device to permit background 5894 * operations. 5895 * 5896 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled 5897 * and negative error value for any other failure. 5898 * 5899 * Return: 0 upon success; < 0 upon failure. 5900 */ 5901 static int ufshcd_urgent_bkops(struct ufs_hba *hba) 5902 { 5903 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl); 5904 } 5905 5906 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5907 { 5908 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5909 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5910 } 5911 5912 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5913 { 5914 int err; 5915 u32 curr_status = 0; 5916 5917 if (hba->is_urgent_bkops_lvl_checked) 5918 goto enable_auto_bkops; 5919 5920 err = ufshcd_get_bkops_status(hba, &curr_status); 5921 if (err) { 5922 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5923 __func__, err); 5924 goto out; 5925 } 5926 5927 /* 5928 * We are seeing that some devices are raising the urgent bkops 5929 * exception events even when BKOPS status doesn't indicate performace 5930 * impacted or critical. Handle these device by determining their urgent 5931 * bkops status at runtime. 5932 */ 5933 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5934 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5935 __func__, curr_status); 5936 /* update the current status as the urgent bkops level */ 5937 hba->urgent_bkops_lvl = curr_status; 5938 hba->is_urgent_bkops_lvl_checked = true; 5939 } 5940 5941 enable_auto_bkops: 5942 err = ufshcd_enable_auto_bkops(hba); 5943 out: 5944 if (err < 0) 5945 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5946 __func__, err); 5947 } 5948 5949 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5950 { 5951 u32 value; 5952 5953 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5954 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 5955 return; 5956 5957 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 5958 5959 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 5960 5961 /* 5962 * A placeholder for the platform vendors to add whatever additional 5963 * steps required 5964 */ 5965 } 5966 5967 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 5968 { 5969 u8 index; 5970 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 5971 UPIU_QUERY_OPCODE_CLEAR_FLAG; 5972 5973 index = ufshcd_wb_get_query_index(hba); 5974 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 5975 } 5976 5977 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 5978 { 5979 int ret; 5980 5981 if (!ufshcd_is_wb_allowed(hba) || 5982 hba->dev_info.wb_enabled == enable) 5983 return 0; 5984 5985 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 5986 if (ret) { 5987 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 5988 __func__, enable ? "enabling" : "disabling", ret); 5989 return ret; 5990 } 5991 5992 hba->dev_info.wb_enabled = enable; 5993 dev_dbg(hba->dev, "%s: Write Booster %s\n", 5994 __func__, enable ? "enabled" : "disabled"); 5995 5996 return ret; 5997 } 5998 5999 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 6000 bool enable) 6001 { 6002 int ret; 6003 6004 ret = __ufshcd_wb_toggle(hba, enable, 6005 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 6006 if (ret) { 6007 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 6008 __func__, enable ? "enabling" : "disabling", ret); 6009 return; 6010 } 6011 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 6012 __func__, enable ? "enabled" : "disabled"); 6013 } 6014 6015 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 6016 { 6017 int ret; 6018 6019 if (!ufshcd_is_wb_allowed(hba) || 6020 hba->dev_info.wb_buf_flush_enabled == enable) 6021 return 0; 6022 6023 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 6024 if (ret) { 6025 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 6026 __func__, enable ? "enabling" : "disabling", ret); 6027 return ret; 6028 } 6029 6030 hba->dev_info.wb_buf_flush_enabled = enable; 6031 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 6032 __func__, enable ? "enabled" : "disabled"); 6033 6034 return ret; 6035 } 6036 6037 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 6038 u32 avail_buf) 6039 { 6040 u32 cur_buf; 6041 int ret; 6042 u8 index; 6043 6044 index = ufshcd_wb_get_query_index(hba); 6045 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6046 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 6047 index, 0, &cur_buf); 6048 if (ret) { 6049 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 6050 __func__, ret); 6051 return false; 6052 } 6053 6054 if (!cur_buf) { 6055 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 6056 cur_buf); 6057 return false; 6058 } 6059 /* Let it continue to flush when available buffer exceeds threshold */ 6060 return avail_buf < hba->vps->wb_flush_threshold; 6061 } 6062 6063 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 6064 { 6065 if (ufshcd_is_wb_buf_flush_allowed(hba)) 6066 ufshcd_wb_toggle_buf_flush(hba, false); 6067 6068 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 6069 ufshcd_wb_toggle(hba, false); 6070 hba->caps &= ~UFSHCD_CAP_WB_EN; 6071 6072 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 6073 } 6074 6075 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 6076 { 6077 u32 lifetime; 6078 int ret; 6079 u8 index; 6080 6081 index = ufshcd_wb_get_query_index(hba); 6082 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6083 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 6084 index, 0, &lifetime); 6085 if (ret) { 6086 dev_err(hba->dev, 6087 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 6088 __func__, ret); 6089 return false; 6090 } 6091 6092 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6093 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6094 __func__, lifetime); 6095 return false; 6096 } 6097 6098 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6099 __func__, lifetime); 6100 6101 return true; 6102 } 6103 6104 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6105 { 6106 int ret; 6107 u32 avail_buf; 6108 u8 index; 6109 6110 if (!ufshcd_is_wb_allowed(hba)) 6111 return false; 6112 6113 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6114 ufshcd_wb_force_disable(hba); 6115 return false; 6116 } 6117 6118 /* 6119 * The ufs device needs the vcc to be ON to flush. 6120 * With user-space reduction enabled, it's enough to enable flush 6121 * by checking only the available buffer. The threshold 6122 * defined here is > 90% full. 6123 * With user-space preserved enabled, the current-buffer 6124 * should be checked too because the wb buffer size can reduce 6125 * when disk tends to be full. This info is provided by current 6126 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6127 * keeping vcc on when current buffer is empty. 6128 */ 6129 index = ufshcd_wb_get_query_index(hba); 6130 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6131 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6132 index, 0, &avail_buf); 6133 if (ret) { 6134 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6135 __func__, ret); 6136 return false; 6137 } 6138 6139 if (!hba->dev_info.b_presrv_uspc_en) 6140 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6141 6142 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6143 } 6144 6145 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6146 { 6147 struct ufs_hba *hba = container_of(to_delayed_work(work), 6148 struct ufs_hba, 6149 rpm_dev_flush_recheck_work); 6150 /* 6151 * To prevent unnecessary VCC power drain after device finishes 6152 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6153 * after a certain delay to recheck the threshold by next runtime 6154 * suspend. 6155 */ 6156 ufshcd_rpm_get_sync(hba); 6157 ufshcd_rpm_put_sync(hba); 6158 } 6159 6160 /** 6161 * ufshcd_exception_event_handler - handle exceptions raised by device 6162 * @work: pointer to work data 6163 * 6164 * Read bExceptionEventStatus attribute from the device and handle the 6165 * exception event accordingly. 6166 */ 6167 static void ufshcd_exception_event_handler(struct work_struct *work) 6168 { 6169 struct ufs_hba *hba; 6170 int err; 6171 u32 status = 0; 6172 hba = container_of(work, struct ufs_hba, eeh_work); 6173 6174 ufshcd_scsi_block_requests(hba); 6175 err = ufshcd_get_ee_status(hba, &status); 6176 if (err) { 6177 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6178 __func__, err); 6179 goto out; 6180 } 6181 6182 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6183 6184 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6185 ufshcd_bkops_exception_event_handler(hba); 6186 6187 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6188 ufshcd_temp_exception_event_handler(hba, status); 6189 6190 ufs_debugfs_exception_event(hba, status); 6191 out: 6192 ufshcd_scsi_unblock_requests(hba); 6193 } 6194 6195 /* Complete requests that have door-bell cleared */ 6196 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6197 { 6198 if (is_mcq_enabled(hba)) 6199 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6200 else 6201 ufshcd_transfer_req_compl(hba); 6202 6203 ufshcd_tmc_handler(hba); 6204 } 6205 6206 /** 6207 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6208 * to recover from the DL NAC errors or not. 6209 * @hba: per-adapter instance 6210 * 6211 * Return: true if error handling is required, false otherwise. 6212 */ 6213 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6214 { 6215 unsigned long flags; 6216 bool err_handling = true; 6217 6218 spin_lock_irqsave(hba->host->host_lock, flags); 6219 /* 6220 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6221 * device fatal error and/or DL NAC & REPLAY timeout errors. 6222 */ 6223 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6224 goto out; 6225 6226 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6227 ((hba->saved_err & UIC_ERROR) && 6228 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6229 goto out; 6230 6231 if ((hba->saved_err & UIC_ERROR) && 6232 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6233 int err; 6234 /* 6235 * wait for 50ms to see if we can get any other errors or not. 6236 */ 6237 spin_unlock_irqrestore(hba->host->host_lock, flags); 6238 msleep(50); 6239 spin_lock_irqsave(hba->host->host_lock, flags); 6240 6241 /* 6242 * now check if we have got any other severe errors other than 6243 * DL NAC error? 6244 */ 6245 if ((hba->saved_err & INT_FATAL_ERRORS) || 6246 ((hba->saved_err & UIC_ERROR) && 6247 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6248 goto out; 6249 6250 /* 6251 * As DL NAC is the only error received so far, send out NOP 6252 * command to confirm if link is still active or not. 6253 * - If we don't get any response then do error recovery. 6254 * - If we get response then clear the DL NAC error bit. 6255 */ 6256 6257 spin_unlock_irqrestore(hba->host->host_lock, flags); 6258 err = ufshcd_verify_dev_init(hba); 6259 spin_lock_irqsave(hba->host->host_lock, flags); 6260 6261 if (err) 6262 goto out; 6263 6264 /* Link seems to be alive hence ignore the DL NAC errors */ 6265 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6266 hba->saved_err &= ~UIC_ERROR; 6267 /* clear NAC error */ 6268 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6269 if (!hba->saved_uic_err) 6270 err_handling = false; 6271 } 6272 out: 6273 spin_unlock_irqrestore(hba->host->host_lock, flags); 6274 return err_handling; 6275 } 6276 6277 /* host lock must be held before calling this func */ 6278 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6279 { 6280 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6281 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6282 } 6283 6284 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6285 { 6286 lockdep_assert_held(hba->host->host_lock); 6287 6288 /* handle fatal errors only when link is not in error state */ 6289 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6290 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6291 ufshcd_is_saved_err_fatal(hba)) 6292 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6293 else 6294 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6295 queue_work(hba->eh_wq, &hba->eh_work); 6296 } 6297 } 6298 6299 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6300 { 6301 spin_lock_irq(hba->host->host_lock); 6302 hba->force_reset = true; 6303 ufshcd_schedule_eh_work(hba); 6304 spin_unlock_irq(hba->host->host_lock); 6305 } 6306 6307 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6308 { 6309 mutex_lock(&hba->wb_mutex); 6310 down_write(&hba->clk_scaling_lock); 6311 hba->clk_scaling.is_allowed = allow; 6312 up_write(&hba->clk_scaling_lock); 6313 mutex_unlock(&hba->wb_mutex); 6314 } 6315 6316 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6317 { 6318 if (suspend) { 6319 if (hba->clk_scaling.is_enabled) 6320 ufshcd_suspend_clkscaling(hba); 6321 ufshcd_clk_scaling_allow(hba, false); 6322 } else { 6323 ufshcd_clk_scaling_allow(hba, true); 6324 if (hba->clk_scaling.is_enabled) 6325 ufshcd_resume_clkscaling(hba); 6326 } 6327 } 6328 6329 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6330 { 6331 ufshcd_rpm_get_sync(hba); 6332 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6333 hba->is_sys_suspended) { 6334 enum ufs_pm_op pm_op; 6335 6336 /* 6337 * Don't assume anything of resume, if 6338 * resume fails, irq and clocks can be OFF, and powers 6339 * can be OFF or in LPM. 6340 */ 6341 ufshcd_setup_hba_vreg(hba, true); 6342 ufshcd_enable_irq(hba); 6343 ufshcd_setup_vreg(hba, true); 6344 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6345 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6346 ufshcd_hold(hba); 6347 if (!ufshcd_is_clkgating_allowed(hba)) 6348 ufshcd_setup_clocks(hba, true); 6349 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6350 ufshcd_vops_resume(hba, pm_op); 6351 } else { 6352 ufshcd_hold(hba); 6353 if (ufshcd_is_clkscaling_supported(hba) && 6354 hba->clk_scaling.is_enabled) 6355 ufshcd_suspend_clkscaling(hba); 6356 ufshcd_clk_scaling_allow(hba, false); 6357 } 6358 ufshcd_scsi_block_requests(hba); 6359 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6360 blk_mq_wait_quiesce_done(&hba->host->tag_set); 6361 cancel_work_sync(&hba->eeh_work); 6362 } 6363 6364 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6365 { 6366 ufshcd_scsi_unblock_requests(hba); 6367 ufshcd_release(hba); 6368 if (ufshcd_is_clkscaling_supported(hba)) 6369 ufshcd_clk_scaling_suspend(hba, false); 6370 ufshcd_rpm_put(hba); 6371 } 6372 6373 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6374 { 6375 return (!hba->is_powered || hba->shutting_down || 6376 !hba->ufs_device_wlun || 6377 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6378 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6379 ufshcd_is_link_broken(hba)))); 6380 } 6381 6382 #ifdef CONFIG_PM 6383 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6384 { 6385 struct Scsi_Host *shost = hba->host; 6386 struct scsi_device *sdev; 6387 struct request_queue *q; 6388 int ret; 6389 6390 hba->is_sys_suspended = false; 6391 /* 6392 * Set RPM status of wlun device to RPM_ACTIVE, 6393 * this also clears its runtime error. 6394 */ 6395 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6396 6397 /* hba device might have a runtime error otherwise */ 6398 if (ret) 6399 ret = pm_runtime_set_active(hba->dev); 6400 /* 6401 * If wlun device had runtime error, we also need to resume those 6402 * consumer scsi devices in case any of them has failed to be 6403 * resumed due to supplier runtime resume failure. This is to unblock 6404 * blk_queue_enter in case there are bios waiting inside it. 6405 */ 6406 if (!ret) { 6407 shost_for_each_device(sdev, shost) { 6408 q = sdev->request_queue; 6409 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6410 q->rpm_status == RPM_SUSPENDING)) 6411 pm_request_resume(q->dev); 6412 } 6413 } 6414 } 6415 #else 6416 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6417 { 6418 } 6419 #endif 6420 6421 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6422 { 6423 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6424 u32 mode; 6425 6426 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6427 6428 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6429 return true; 6430 6431 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6432 return true; 6433 6434 return false; 6435 } 6436 6437 static bool ufshcd_abort_one(struct request *rq, void *priv) 6438 { 6439 int *ret = priv; 6440 u32 tag = rq->tag; 6441 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6442 struct scsi_device *sdev = cmd->device; 6443 struct Scsi_Host *shost = sdev->host; 6444 struct ufs_hba *hba = shost_priv(shost); 6445 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 6446 struct ufs_hw_queue *hwq; 6447 unsigned long flags; 6448 6449 *ret = ufshcd_try_to_abort_task(hba, tag); 6450 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6451 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6452 *ret ? "failed" : "succeeded"); 6453 6454 /* Release cmd in MCQ mode if abort succeeds */ 6455 if (is_mcq_enabled(hba) && (*ret == 0)) { 6456 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 6457 spin_lock_irqsave(&hwq->cq_lock, flags); 6458 if (ufshcd_cmd_inflight(lrbp->cmd)) 6459 ufshcd_release_scsi_cmd(hba, lrbp); 6460 spin_unlock_irqrestore(&hwq->cq_lock, flags); 6461 } 6462 6463 return *ret == 0; 6464 } 6465 6466 /** 6467 * ufshcd_abort_all - Abort all pending commands. 6468 * @hba: Host bus adapter pointer. 6469 * 6470 * Return: true if and only if the host controller needs to be reset. 6471 */ 6472 static bool ufshcd_abort_all(struct ufs_hba *hba) 6473 { 6474 int tag, ret = 0; 6475 6476 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6477 if (ret) 6478 goto out; 6479 6480 /* Clear pending task management requests */ 6481 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6482 ret = ufshcd_clear_tm_cmd(hba, tag); 6483 if (ret) 6484 goto out; 6485 } 6486 6487 out: 6488 /* Complete the requests that are cleared by s/w */ 6489 ufshcd_complete_requests(hba, false); 6490 6491 return ret != 0; 6492 } 6493 6494 /** 6495 * ufshcd_err_handler - handle UFS errors that require s/w attention 6496 * @work: pointer to work structure 6497 */ 6498 static void ufshcd_err_handler(struct work_struct *work) 6499 { 6500 int retries = MAX_ERR_HANDLER_RETRIES; 6501 struct ufs_hba *hba; 6502 unsigned long flags; 6503 bool needs_restore; 6504 bool needs_reset; 6505 int pmc_err; 6506 6507 hba = container_of(work, struct ufs_hba, eh_work); 6508 6509 dev_info(hba->dev, 6510 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6511 __func__, ufshcd_state_name[hba->ufshcd_state], 6512 hba->is_powered, hba->shutting_down, hba->saved_err, 6513 hba->saved_uic_err, hba->force_reset, 6514 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6515 6516 down(&hba->host_sem); 6517 spin_lock_irqsave(hba->host->host_lock, flags); 6518 if (ufshcd_err_handling_should_stop(hba)) { 6519 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6520 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6521 spin_unlock_irqrestore(hba->host->host_lock, flags); 6522 up(&hba->host_sem); 6523 return; 6524 } 6525 ufshcd_set_eh_in_progress(hba); 6526 spin_unlock_irqrestore(hba->host->host_lock, flags); 6527 ufshcd_err_handling_prepare(hba); 6528 /* Complete requests that have door-bell cleared by h/w */ 6529 ufshcd_complete_requests(hba, false); 6530 spin_lock_irqsave(hba->host->host_lock, flags); 6531 again: 6532 needs_restore = false; 6533 needs_reset = false; 6534 6535 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6536 hba->ufshcd_state = UFSHCD_STATE_RESET; 6537 /* 6538 * A full reset and restore might have happened after preparation 6539 * is finished, double check whether we should stop. 6540 */ 6541 if (ufshcd_err_handling_should_stop(hba)) 6542 goto skip_err_handling; 6543 6544 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6545 bool ret; 6546 6547 spin_unlock_irqrestore(hba->host->host_lock, flags); 6548 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6549 ret = ufshcd_quirk_dl_nac_errors(hba); 6550 spin_lock_irqsave(hba->host->host_lock, flags); 6551 if (!ret && ufshcd_err_handling_should_stop(hba)) 6552 goto skip_err_handling; 6553 } 6554 6555 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6556 (hba->saved_uic_err && 6557 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6558 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6559 6560 spin_unlock_irqrestore(hba->host->host_lock, flags); 6561 ufshcd_print_host_state(hba); 6562 ufshcd_print_pwr_info(hba); 6563 ufshcd_print_evt_hist(hba); 6564 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6565 ufshcd_print_trs_all(hba, pr_prdt); 6566 spin_lock_irqsave(hba->host->host_lock, flags); 6567 } 6568 6569 /* 6570 * if host reset is required then skip clearing the pending 6571 * transfers forcefully because they will get cleared during 6572 * host reset and restore 6573 */ 6574 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6575 ufshcd_is_saved_err_fatal(hba) || 6576 ((hba->saved_err & UIC_ERROR) && 6577 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6578 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6579 needs_reset = true; 6580 goto do_reset; 6581 } 6582 6583 /* 6584 * If LINERESET was caught, UFS might have been put to PWM mode, 6585 * check if power mode restore is needed. 6586 */ 6587 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6588 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6589 if (!hba->saved_uic_err) 6590 hba->saved_err &= ~UIC_ERROR; 6591 spin_unlock_irqrestore(hba->host->host_lock, flags); 6592 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6593 needs_restore = true; 6594 spin_lock_irqsave(hba->host->host_lock, flags); 6595 if (!hba->saved_err && !needs_restore) 6596 goto skip_err_handling; 6597 } 6598 6599 hba->silence_err_logs = true; 6600 /* release lock as clear command might sleep */ 6601 spin_unlock_irqrestore(hba->host->host_lock, flags); 6602 6603 needs_reset = ufshcd_abort_all(hba); 6604 6605 spin_lock_irqsave(hba->host->host_lock, flags); 6606 hba->silence_err_logs = false; 6607 if (needs_reset) 6608 goto do_reset; 6609 6610 /* 6611 * After all reqs and tasks are cleared from doorbell, 6612 * now it is safe to retore power mode. 6613 */ 6614 if (needs_restore) { 6615 spin_unlock_irqrestore(hba->host->host_lock, flags); 6616 /* 6617 * Hold the scaling lock just in case dev cmds 6618 * are sent via bsg and/or sysfs. 6619 */ 6620 down_write(&hba->clk_scaling_lock); 6621 hba->force_pmc = true; 6622 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6623 if (pmc_err) { 6624 needs_reset = true; 6625 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6626 __func__, pmc_err); 6627 } 6628 hba->force_pmc = false; 6629 ufshcd_print_pwr_info(hba); 6630 up_write(&hba->clk_scaling_lock); 6631 spin_lock_irqsave(hba->host->host_lock, flags); 6632 } 6633 6634 do_reset: 6635 /* Fatal errors need reset */ 6636 if (needs_reset) { 6637 int err; 6638 6639 hba->force_reset = false; 6640 spin_unlock_irqrestore(hba->host->host_lock, flags); 6641 err = ufshcd_reset_and_restore(hba); 6642 if (err) 6643 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6644 __func__, err); 6645 else 6646 ufshcd_recover_pm_error(hba); 6647 spin_lock_irqsave(hba->host->host_lock, flags); 6648 } 6649 6650 skip_err_handling: 6651 if (!needs_reset) { 6652 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6653 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6654 if (hba->saved_err || hba->saved_uic_err) 6655 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6656 __func__, hba->saved_err, hba->saved_uic_err); 6657 } 6658 /* Exit in an operational state or dead */ 6659 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6660 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6661 if (--retries) 6662 goto again; 6663 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6664 } 6665 ufshcd_clear_eh_in_progress(hba); 6666 spin_unlock_irqrestore(hba->host->host_lock, flags); 6667 ufshcd_err_handling_unprepare(hba); 6668 up(&hba->host_sem); 6669 6670 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6671 ufshcd_state_name[hba->ufshcd_state]); 6672 } 6673 6674 /** 6675 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6676 * @hba: per-adapter instance 6677 * 6678 * Return: 6679 * IRQ_HANDLED - If interrupt is valid 6680 * IRQ_NONE - If invalid interrupt 6681 */ 6682 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6683 { 6684 u32 reg; 6685 irqreturn_t retval = IRQ_NONE; 6686 6687 /* PHY layer error */ 6688 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6689 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6690 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6691 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6692 /* 6693 * To know whether this error is fatal or not, DB timeout 6694 * must be checked but this error is handled separately. 6695 */ 6696 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6697 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6698 __func__); 6699 6700 /* Got a LINERESET indication. */ 6701 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6702 struct uic_command *cmd = NULL; 6703 6704 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6705 if (hba->uic_async_done && hba->active_uic_cmd) 6706 cmd = hba->active_uic_cmd; 6707 /* 6708 * Ignore the LINERESET during power mode change 6709 * operation via DME_SET command. 6710 */ 6711 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6712 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6713 } 6714 retval |= IRQ_HANDLED; 6715 } 6716 6717 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6718 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6719 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6720 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6721 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6722 6723 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6724 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6725 else if (hba->dev_quirks & 6726 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6727 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6728 hba->uic_error |= 6729 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6730 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6731 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6732 } 6733 retval |= IRQ_HANDLED; 6734 } 6735 6736 /* UIC NL/TL/DME errors needs software retry */ 6737 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6738 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6739 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6740 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6741 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6742 retval |= IRQ_HANDLED; 6743 } 6744 6745 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6746 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6747 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6748 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6749 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6750 retval |= IRQ_HANDLED; 6751 } 6752 6753 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6754 if ((reg & UIC_DME_ERROR) && 6755 (reg & UIC_DME_ERROR_CODE_MASK)) { 6756 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6757 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6758 retval |= IRQ_HANDLED; 6759 } 6760 6761 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6762 __func__, hba->uic_error); 6763 return retval; 6764 } 6765 6766 /** 6767 * ufshcd_check_errors - Check for errors that need s/w attention 6768 * @hba: per-adapter instance 6769 * @intr_status: interrupt status generated by the controller 6770 * 6771 * Return: 6772 * IRQ_HANDLED - If interrupt is valid 6773 * IRQ_NONE - If invalid interrupt 6774 */ 6775 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6776 { 6777 bool queue_eh_work = false; 6778 irqreturn_t retval = IRQ_NONE; 6779 6780 spin_lock(hba->host->host_lock); 6781 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6782 6783 if (hba->errors & INT_FATAL_ERRORS) { 6784 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6785 hba->errors); 6786 queue_eh_work = true; 6787 } 6788 6789 if (hba->errors & UIC_ERROR) { 6790 hba->uic_error = 0; 6791 retval = ufshcd_update_uic_error(hba); 6792 if (hba->uic_error) 6793 queue_eh_work = true; 6794 } 6795 6796 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6797 dev_err(hba->dev, 6798 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6799 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6800 "Enter" : "Exit", 6801 hba->errors, ufshcd_get_upmcrs(hba)); 6802 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6803 hba->errors); 6804 ufshcd_set_link_broken(hba); 6805 queue_eh_work = true; 6806 } 6807 6808 if (queue_eh_work) { 6809 /* 6810 * update the transfer error masks to sticky bits, let's do this 6811 * irrespective of current ufshcd_state. 6812 */ 6813 hba->saved_err |= hba->errors; 6814 hba->saved_uic_err |= hba->uic_error; 6815 6816 /* dump controller state before resetting */ 6817 if ((hba->saved_err & 6818 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6819 (hba->saved_uic_err && 6820 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6821 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6822 __func__, hba->saved_err, 6823 hba->saved_uic_err); 6824 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6825 "host_regs: "); 6826 ufshcd_print_pwr_info(hba); 6827 } 6828 ufshcd_schedule_eh_work(hba); 6829 retval |= IRQ_HANDLED; 6830 } 6831 /* 6832 * if (!queue_eh_work) - 6833 * Other errors are either non-fatal where host recovers 6834 * itself without s/w intervention or errors that will be 6835 * handled by the SCSI core layer. 6836 */ 6837 hba->errors = 0; 6838 hba->uic_error = 0; 6839 spin_unlock(hba->host->host_lock); 6840 return retval; 6841 } 6842 6843 /** 6844 * ufshcd_tmc_handler - handle task management function completion 6845 * @hba: per adapter instance 6846 * 6847 * Return: 6848 * IRQ_HANDLED - If interrupt is valid 6849 * IRQ_NONE - If invalid interrupt 6850 */ 6851 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6852 { 6853 unsigned long flags, pending, issued; 6854 irqreturn_t ret = IRQ_NONE; 6855 int tag; 6856 6857 spin_lock_irqsave(hba->host->host_lock, flags); 6858 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6859 issued = hba->outstanding_tasks & ~pending; 6860 for_each_set_bit(tag, &issued, hba->nutmrs) { 6861 struct request *req = hba->tmf_rqs[tag]; 6862 struct completion *c = req->end_io_data; 6863 6864 complete(c); 6865 ret = IRQ_HANDLED; 6866 } 6867 spin_unlock_irqrestore(hba->host->host_lock, flags); 6868 6869 return ret; 6870 } 6871 6872 /** 6873 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6874 * @hba: per adapter instance 6875 * 6876 * Return: IRQ_HANDLED if interrupt is handled. 6877 */ 6878 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6879 { 6880 struct ufs_hw_queue *hwq; 6881 unsigned long outstanding_cqs; 6882 unsigned int nr_queues; 6883 int i, ret; 6884 u32 events; 6885 6886 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6887 if (ret) 6888 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6889 6890 /* Exclude the poll queues */ 6891 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6892 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6893 hwq = &hba->uhq[i]; 6894 6895 events = ufshcd_mcq_read_cqis(hba, i); 6896 if (events) 6897 ufshcd_mcq_write_cqis(hba, events, i); 6898 6899 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6900 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6901 } 6902 6903 return IRQ_HANDLED; 6904 } 6905 6906 /** 6907 * ufshcd_sl_intr - Interrupt service routine 6908 * @hba: per adapter instance 6909 * @intr_status: contains interrupts generated by the controller 6910 * 6911 * Return: 6912 * IRQ_HANDLED - If interrupt is valid 6913 * IRQ_NONE - If invalid interrupt 6914 */ 6915 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6916 { 6917 irqreturn_t retval = IRQ_NONE; 6918 6919 if (intr_status & UFSHCD_UIC_MASK) 6920 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6921 6922 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6923 retval |= ufshcd_check_errors(hba, intr_status); 6924 6925 if (intr_status & UTP_TASK_REQ_COMPL) 6926 retval |= ufshcd_tmc_handler(hba); 6927 6928 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6929 retval |= ufshcd_transfer_req_compl(hba); 6930 6931 if (intr_status & MCQ_CQ_EVENT_STATUS) 6932 retval |= ufshcd_handle_mcq_cq_events(hba); 6933 6934 return retval; 6935 } 6936 6937 /** 6938 * ufshcd_intr - Main interrupt service routine 6939 * @irq: irq number 6940 * @__hba: pointer to adapter instance 6941 * 6942 * Return: 6943 * IRQ_HANDLED - If interrupt is valid 6944 * IRQ_NONE - If invalid interrupt 6945 */ 6946 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6947 { 6948 u32 intr_status, enabled_intr_status = 0; 6949 irqreturn_t retval = IRQ_NONE; 6950 struct ufs_hba *hba = __hba; 6951 int retries = hba->nutrs; 6952 6953 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6954 hba->ufs_stats.last_intr_status = intr_status; 6955 hba->ufs_stats.last_intr_ts = local_clock(); 6956 6957 /* 6958 * There could be max of hba->nutrs reqs in flight and in worst case 6959 * if the reqs get finished 1 by 1 after the interrupt status is 6960 * read, make sure we handle them by checking the interrupt status 6961 * again in a loop until we process all of the reqs before returning. 6962 */ 6963 while (intr_status && retries--) { 6964 enabled_intr_status = 6965 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6966 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6967 if (enabled_intr_status) 6968 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 6969 6970 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6971 } 6972 6973 if (enabled_intr_status && retval == IRQ_NONE && 6974 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 6975 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 6976 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 6977 __func__, 6978 intr_status, 6979 hba->ufs_stats.last_intr_status, 6980 enabled_intr_status); 6981 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 6982 } 6983 6984 return retval; 6985 } 6986 6987 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 6988 { 6989 int err = 0; 6990 u32 mask = 1 << tag; 6991 unsigned long flags; 6992 6993 if (!test_bit(tag, &hba->outstanding_tasks)) 6994 goto out; 6995 6996 spin_lock_irqsave(hba->host->host_lock, flags); 6997 ufshcd_utmrl_clear(hba, tag); 6998 spin_unlock_irqrestore(hba->host->host_lock, flags); 6999 7000 /* poll for max. 1 sec to clear door bell register by h/w */ 7001 err = ufshcd_wait_for_register(hba, 7002 REG_UTP_TASK_REQ_DOOR_BELL, 7003 mask, 0, 1000, 1000); 7004 7005 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 7006 tag, err < 0 ? "failed" : "succeeded"); 7007 7008 out: 7009 return err; 7010 } 7011 7012 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 7013 struct utp_task_req_desc *treq, u8 tm_function) 7014 { 7015 struct request_queue *q = hba->tmf_queue; 7016 struct Scsi_Host *host = hba->host; 7017 DECLARE_COMPLETION_ONSTACK(wait); 7018 struct request *req; 7019 unsigned long flags; 7020 int task_tag, err; 7021 7022 /* 7023 * blk_mq_alloc_request() is used here only to get a free tag. 7024 */ 7025 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 7026 if (IS_ERR(req)) 7027 return PTR_ERR(req); 7028 7029 req->end_io_data = &wait; 7030 ufshcd_hold(hba); 7031 7032 spin_lock_irqsave(host->host_lock, flags); 7033 7034 task_tag = req->tag; 7035 hba->tmf_rqs[req->tag] = req; 7036 treq->upiu_req.req_header.task_tag = task_tag; 7037 7038 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 7039 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 7040 7041 /* send command to the controller */ 7042 __set_bit(task_tag, &hba->outstanding_tasks); 7043 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 7044 7045 spin_unlock_irqrestore(host->host_lock, flags); 7046 7047 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 7048 7049 /* wait until the task management command is completed */ 7050 err = wait_for_completion_io_timeout(&wait, 7051 msecs_to_jiffies(TM_CMD_TIMEOUT)); 7052 if (!err) { 7053 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 7054 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 7055 __func__, tm_function); 7056 if (ufshcd_clear_tm_cmd(hba, task_tag)) 7057 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 7058 __func__, task_tag); 7059 err = -ETIMEDOUT; 7060 } else { 7061 err = 0; 7062 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 7063 7064 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 7065 } 7066 7067 spin_lock_irqsave(hba->host->host_lock, flags); 7068 hba->tmf_rqs[req->tag] = NULL; 7069 __clear_bit(task_tag, &hba->outstanding_tasks); 7070 spin_unlock_irqrestore(hba->host->host_lock, flags); 7071 7072 ufshcd_release(hba); 7073 blk_mq_free_request(req); 7074 7075 return err; 7076 } 7077 7078 /** 7079 * ufshcd_issue_tm_cmd - issues task management commands to controller 7080 * @hba: per adapter instance 7081 * @lun_id: LUN ID to which TM command is sent 7082 * @task_id: task ID to which the TM command is applicable 7083 * @tm_function: task management function opcode 7084 * @tm_response: task management service response return value 7085 * 7086 * Return: non-zero value on error, zero on success. 7087 */ 7088 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7089 u8 tm_function, u8 *tm_response) 7090 { 7091 struct utp_task_req_desc treq = { }; 7092 enum utp_ocs ocs_value; 7093 int err; 7094 7095 /* Configure task request descriptor */ 7096 treq.header.interrupt = 1; 7097 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7098 7099 /* Configure task request UPIU */ 7100 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7101 treq.upiu_req.req_header.lun = lun_id; 7102 treq.upiu_req.req_header.tm_function = tm_function; 7103 7104 /* 7105 * The host shall provide the same value for LUN field in the basic 7106 * header and for Input Parameter. 7107 */ 7108 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7109 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7110 7111 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7112 if (err == -ETIMEDOUT) 7113 return err; 7114 7115 ocs_value = treq.header.ocs & MASK_OCS; 7116 if (ocs_value != OCS_SUCCESS) 7117 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7118 __func__, ocs_value); 7119 else if (tm_response) 7120 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7121 MASK_TM_SERVICE_RESP; 7122 return err; 7123 } 7124 7125 /** 7126 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7127 * @hba: per-adapter instance 7128 * @req_upiu: upiu request 7129 * @rsp_upiu: upiu reply 7130 * @desc_buff: pointer to descriptor buffer, NULL if NA 7131 * @buff_len: descriptor size, 0 if NA 7132 * @cmd_type: specifies the type (NOP, Query...) 7133 * @desc_op: descriptor operation 7134 * 7135 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7136 * Therefore, it "rides" the device management infrastructure: uses its tag and 7137 * tasks work queues. 7138 * 7139 * Since there is only one available tag for device management commands, 7140 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7141 * 7142 * Return: 0 upon success; < 0 upon failure. 7143 */ 7144 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7145 struct utp_upiu_req *req_upiu, 7146 struct utp_upiu_req *rsp_upiu, 7147 u8 *desc_buff, int *buff_len, 7148 enum dev_cmd_type cmd_type, 7149 enum query_opcode desc_op) 7150 { 7151 const u32 tag = hba->reserved_slot; 7152 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7153 int err = 0; 7154 u8 upiu_flags; 7155 7156 /* Protects use of hba->reserved_slot. */ 7157 lockdep_assert_held(&hba->dev_cmd.lock); 7158 7159 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 7160 7161 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 7162 7163 /* update the task tag in the request upiu */ 7164 req_upiu->header.task_tag = tag; 7165 7166 /* just copy the upiu request as it is */ 7167 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7168 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7169 /* The Data Segment Area is optional depending upon the query 7170 * function value. for WRITE DESCRIPTOR, the data segment 7171 * follows right after the tsf. 7172 */ 7173 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7174 *buff_len = 0; 7175 } 7176 7177 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7178 7179 /* 7180 * ignore the returning value here - ufshcd_check_query_response is 7181 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7182 * read the response directly ignoring all errors. 7183 */ 7184 ufshcd_issue_dev_cmd(hba, lrbp, tag, QUERY_REQ_TIMEOUT); 7185 7186 /* just copy the upiu response as it is */ 7187 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7188 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7189 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7190 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7191 .data_segment_length); 7192 7193 if (*buff_len >= resp_len) { 7194 memcpy(desc_buff, descp, resp_len); 7195 *buff_len = resp_len; 7196 } else { 7197 dev_warn(hba->dev, 7198 "%s: rsp size %d is bigger than buffer size %d", 7199 __func__, resp_len, *buff_len); 7200 *buff_len = 0; 7201 err = -EINVAL; 7202 } 7203 } 7204 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7205 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7206 7207 return err; 7208 } 7209 7210 /** 7211 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7212 * @hba: per-adapter instance 7213 * @req_upiu: upiu request 7214 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7215 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7216 * @desc_buff: pointer to descriptor buffer, NULL if NA 7217 * @buff_len: descriptor size, 0 if NA 7218 * @desc_op: descriptor operation 7219 * 7220 * Supports UTP Transfer requests (nop and query), and UTP Task 7221 * Management requests. 7222 * It is up to the caller to fill the upiu conent properly, as it will 7223 * be copied without any further input validations. 7224 * 7225 * Return: 0 upon success; < 0 upon failure. 7226 */ 7227 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7228 struct utp_upiu_req *req_upiu, 7229 struct utp_upiu_req *rsp_upiu, 7230 enum upiu_request_transaction msgcode, 7231 u8 *desc_buff, int *buff_len, 7232 enum query_opcode desc_op) 7233 { 7234 int err; 7235 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7236 struct utp_task_req_desc treq = { }; 7237 enum utp_ocs ocs_value; 7238 u8 tm_f = req_upiu->header.tm_function; 7239 7240 switch (msgcode) { 7241 case UPIU_TRANSACTION_NOP_OUT: 7242 cmd_type = DEV_CMD_TYPE_NOP; 7243 fallthrough; 7244 case UPIU_TRANSACTION_QUERY_REQ: 7245 ufshcd_dev_man_lock(hba); 7246 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7247 desc_buff, buff_len, 7248 cmd_type, desc_op); 7249 ufshcd_dev_man_unlock(hba); 7250 7251 break; 7252 case UPIU_TRANSACTION_TASK_REQ: 7253 treq.header.interrupt = 1; 7254 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7255 7256 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7257 7258 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7259 if (err == -ETIMEDOUT) 7260 break; 7261 7262 ocs_value = treq.header.ocs & MASK_OCS; 7263 if (ocs_value != OCS_SUCCESS) { 7264 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7265 ocs_value); 7266 break; 7267 } 7268 7269 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7270 7271 break; 7272 default: 7273 err = -EINVAL; 7274 7275 break; 7276 } 7277 7278 return err; 7279 } 7280 7281 /** 7282 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7283 * @hba: per adapter instance 7284 * @req_upiu: upiu request 7285 * @rsp_upiu: upiu reply 7286 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7287 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7288 * @sg_cnt: The number of sg lists actually used 7289 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7290 * @dir: DMA direction 7291 * 7292 * Return: zero on success, non-zero on failure. 7293 */ 7294 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7295 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7296 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7297 enum dma_data_direction dir) 7298 { 7299 const u32 tag = hba->reserved_slot; 7300 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7301 int err = 0; 7302 int result; 7303 u8 upiu_flags; 7304 u8 *ehs_data; 7305 u16 ehs_len; 7306 int ehs = (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) ? 2 : 0; 7307 7308 /* Protects use of hba->reserved_slot. */ 7309 ufshcd_dev_man_lock(hba); 7310 7311 ufshcd_setup_dev_cmd(hba, lrbp, DEV_CMD_TYPE_RPMB, UFS_UPIU_RPMB_WLUN, tag); 7312 7313 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, ehs); 7314 7315 /* update the task tag */ 7316 req_upiu->header.task_tag = tag; 7317 7318 /* copy the UPIU(contains CDB) request as it is */ 7319 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7320 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7321 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7322 7323 if (dir != DMA_NONE && sg_list) 7324 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7325 7326 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7327 7328 err = ufshcd_issue_dev_cmd(hba, lrbp, tag, ADVANCED_RPMB_REQ_TIMEOUT); 7329 7330 if (!err) { 7331 /* Just copy the upiu response as it is */ 7332 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7333 /* Get the response UPIU result */ 7334 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7335 lrbp->ucd_rsp_ptr->header.status; 7336 7337 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7338 /* 7339 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7340 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7341 * Message is 02h 7342 */ 7343 if (ehs_len == 2 && rsp_ehs) { 7344 /* 7345 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7346 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7347 */ 7348 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7349 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7350 } 7351 } 7352 7353 ufshcd_dev_man_unlock(hba); 7354 7355 return err ? : result; 7356 } 7357 7358 /** 7359 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7360 * @cmd: SCSI command pointer 7361 * 7362 * Return: SUCCESS or FAILED. 7363 */ 7364 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7365 { 7366 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7367 struct Scsi_Host *host; 7368 struct ufs_hba *hba; 7369 struct ufs_hw_queue *hwq; 7370 struct ufshcd_lrb *lrbp; 7371 u32 pos, not_cleared_mask = 0; 7372 int err; 7373 u8 resp = 0xF, lun; 7374 7375 host = cmd->device->host; 7376 hba = shost_priv(host); 7377 7378 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7379 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7380 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7381 if (!err) 7382 err = resp; 7383 goto out; 7384 } 7385 7386 if (is_mcq_enabled(hba)) { 7387 for (pos = 0; pos < hba->nutrs; pos++) { 7388 lrbp = &hba->lrb[pos]; 7389 if (ufshcd_cmd_inflight(lrbp->cmd) && 7390 lrbp->lun == lun) { 7391 ufshcd_clear_cmd(hba, pos); 7392 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7393 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7394 } 7395 } 7396 err = 0; 7397 goto out; 7398 } 7399 7400 /* clear the commands that were pending for corresponding LUN */ 7401 spin_lock_irqsave(&hba->outstanding_lock, flags); 7402 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7403 if (hba->lrb[pos].lun == lun) 7404 __set_bit(pos, &pending_reqs); 7405 hba->outstanding_reqs &= ~pending_reqs; 7406 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7407 7408 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7409 if (ufshcd_clear_cmd(hba, pos) < 0) { 7410 spin_lock_irqsave(&hba->outstanding_lock, flags); 7411 not_cleared = 1U << pos & 7412 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7413 hba->outstanding_reqs |= not_cleared; 7414 not_cleared_mask |= not_cleared; 7415 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7416 7417 dev_err(hba->dev, "%s: failed to clear request %d\n", 7418 __func__, pos); 7419 } 7420 } 7421 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7422 7423 out: 7424 hba->req_abort_count = 0; 7425 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7426 if (!err) { 7427 err = SUCCESS; 7428 } else { 7429 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7430 err = FAILED; 7431 } 7432 return err; 7433 } 7434 7435 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7436 { 7437 struct ufshcd_lrb *lrbp; 7438 int tag; 7439 7440 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7441 lrbp = &hba->lrb[tag]; 7442 lrbp->req_abort_skip = true; 7443 } 7444 } 7445 7446 /** 7447 * ufshcd_try_to_abort_task - abort a specific task 7448 * @hba: Pointer to adapter instance 7449 * @tag: Task tag/index to be aborted 7450 * 7451 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7452 * command, and in host controller by clearing the door-bell register. There can 7453 * be race between controller sending the command to the device while abort is 7454 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7455 * really issued and then try to abort it. 7456 * 7457 * Return: zero on success, non-zero on failure. 7458 */ 7459 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7460 { 7461 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7462 int err = 0; 7463 int poll_cnt; 7464 u8 resp = 0xF; 7465 u32 reg; 7466 7467 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7468 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7469 UFS_QUERY_TASK, &resp); 7470 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7471 /* cmd pending in the device */ 7472 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7473 __func__, tag); 7474 break; 7475 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7476 /* 7477 * cmd not pending in the device, check if it is 7478 * in transition. 7479 */ 7480 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n", 7481 __func__, tag); 7482 if (is_mcq_enabled(hba)) { 7483 /* MCQ mode */ 7484 if (ufshcd_cmd_inflight(lrbp->cmd)) { 7485 /* sleep for max. 200us same delay as in SDB mode */ 7486 usleep_range(100, 200); 7487 continue; 7488 } 7489 /* command completed already */ 7490 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n", 7491 __func__, tag); 7492 goto out; 7493 } 7494 7495 /* Single Doorbell Mode */ 7496 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7497 if (reg & (1 << tag)) { 7498 /* sleep for max. 200us to stabilize */ 7499 usleep_range(100, 200); 7500 continue; 7501 } 7502 /* command completed already */ 7503 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n", 7504 __func__, tag); 7505 goto out; 7506 } else { 7507 dev_err(hba->dev, 7508 "%s: no response from device. tag = %d, err %d\n", 7509 __func__, tag, err); 7510 if (!err) 7511 err = resp; /* service response error */ 7512 goto out; 7513 } 7514 } 7515 7516 if (!poll_cnt) { 7517 err = -EBUSY; 7518 goto out; 7519 } 7520 7521 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7522 UFS_ABORT_TASK, &resp); 7523 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7524 if (!err) { 7525 err = resp; /* service response error */ 7526 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7527 __func__, tag, err); 7528 } 7529 goto out; 7530 } 7531 7532 err = ufshcd_clear_cmd(hba, tag); 7533 if (err) 7534 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7535 __func__, tag, err); 7536 7537 out: 7538 return err; 7539 } 7540 7541 /** 7542 * ufshcd_abort - scsi host template eh_abort_handler callback 7543 * @cmd: SCSI command pointer 7544 * 7545 * Return: SUCCESS or FAILED. 7546 */ 7547 static int ufshcd_abort(struct scsi_cmnd *cmd) 7548 { 7549 struct Scsi_Host *host = cmd->device->host; 7550 struct ufs_hba *hba = shost_priv(host); 7551 int tag = scsi_cmd_to_rq(cmd)->tag; 7552 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7553 unsigned long flags; 7554 int err = FAILED; 7555 bool outstanding; 7556 u32 reg; 7557 7558 ufshcd_hold(hba); 7559 7560 if (!is_mcq_enabled(hba)) { 7561 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7562 if (!test_bit(tag, &hba->outstanding_reqs)) { 7563 /* If command is already aborted/completed, return FAILED. */ 7564 dev_err(hba->dev, 7565 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7566 __func__, tag, hba->outstanding_reqs, reg); 7567 goto release; 7568 } 7569 } 7570 7571 /* Print Transfer Request of aborted task */ 7572 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7573 7574 /* 7575 * Print detailed info about aborted request. 7576 * As more than one request might get aborted at the same time, 7577 * print full information only for the first aborted request in order 7578 * to reduce repeated printouts. For other aborted requests only print 7579 * basic details. 7580 */ 7581 scsi_print_command(cmd); 7582 if (!hba->req_abort_count) { 7583 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7584 ufshcd_print_evt_hist(hba); 7585 ufshcd_print_host_state(hba); 7586 ufshcd_print_pwr_info(hba); 7587 ufshcd_print_tr(hba, tag, true); 7588 } else { 7589 ufshcd_print_tr(hba, tag, false); 7590 } 7591 hba->req_abort_count++; 7592 7593 if (!is_mcq_enabled(hba) && !(reg & (1 << tag))) { 7594 /* only execute this code in single doorbell mode */ 7595 dev_err(hba->dev, 7596 "%s: cmd was completed, but without a notifying intr, tag = %d", 7597 __func__, tag); 7598 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7599 goto release; 7600 } 7601 7602 /* 7603 * Task abort to the device W-LUN is illegal. When this command 7604 * will fail, due to spec violation, scsi err handling next step 7605 * will be to send LU reset which, again, is a spec violation. 7606 * To avoid these unnecessary/illegal steps, first we clean up 7607 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7608 * then queue the eh_work and bail. 7609 */ 7610 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7611 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7612 7613 spin_lock_irqsave(host->host_lock, flags); 7614 hba->force_reset = true; 7615 ufshcd_schedule_eh_work(hba); 7616 spin_unlock_irqrestore(host->host_lock, flags); 7617 goto release; 7618 } 7619 7620 if (is_mcq_enabled(hba)) { 7621 /* MCQ mode. Branch off to handle abort for mcq mode */ 7622 err = ufshcd_mcq_abort(cmd); 7623 goto release; 7624 } 7625 7626 /* Skip task abort in case previous aborts failed and report failure */ 7627 if (lrbp->req_abort_skip) { 7628 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7629 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7630 goto release; 7631 } 7632 7633 err = ufshcd_try_to_abort_task(hba, tag); 7634 if (err) { 7635 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7636 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7637 err = FAILED; 7638 goto release; 7639 } 7640 7641 /* 7642 * Clear the corresponding bit from outstanding_reqs since the command 7643 * has been aborted successfully. 7644 */ 7645 spin_lock_irqsave(&hba->outstanding_lock, flags); 7646 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7647 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7648 7649 if (outstanding) 7650 ufshcd_release_scsi_cmd(hba, lrbp); 7651 7652 err = SUCCESS; 7653 7654 release: 7655 /* Matches the ufshcd_hold() call at the start of this function. */ 7656 ufshcd_release(hba); 7657 return err; 7658 } 7659 7660 /** 7661 * ufshcd_host_reset_and_restore - reset and restore host controller 7662 * @hba: per-adapter instance 7663 * 7664 * Note that host controller reset may issue DME_RESET to 7665 * local and remote (device) Uni-Pro stack and the attributes 7666 * are reset to default state. 7667 * 7668 * Return: zero on success, non-zero on failure. 7669 */ 7670 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7671 { 7672 int err; 7673 7674 /* 7675 * Stop the host controller and complete the requests 7676 * cleared by h/w 7677 */ 7678 ufshcd_hba_stop(hba); 7679 hba->silence_err_logs = true; 7680 ufshcd_complete_requests(hba, true); 7681 hba->silence_err_logs = false; 7682 7683 /* scale up clocks to max frequency before full reinitialization */ 7684 ufshcd_scale_clks(hba, ULONG_MAX, true); 7685 7686 err = ufshcd_hba_enable(hba); 7687 7688 /* Establish the link again and restore the device */ 7689 if (!err) 7690 err = ufshcd_probe_hba(hba, false); 7691 7692 if (err) 7693 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7694 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7695 return err; 7696 } 7697 7698 /** 7699 * ufshcd_reset_and_restore - reset and re-initialize host/device 7700 * @hba: per-adapter instance 7701 * 7702 * Reset and recover device, host and re-establish link. This 7703 * is helpful to recover the communication in fatal error conditions. 7704 * 7705 * Return: zero on success, non-zero on failure. 7706 */ 7707 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7708 { 7709 u32 saved_err = 0; 7710 u32 saved_uic_err = 0; 7711 int err = 0; 7712 unsigned long flags; 7713 int retries = MAX_HOST_RESET_RETRIES; 7714 7715 spin_lock_irqsave(hba->host->host_lock, flags); 7716 do { 7717 /* 7718 * This is a fresh start, cache and clear saved error first, 7719 * in case new error generated during reset and restore. 7720 */ 7721 saved_err |= hba->saved_err; 7722 saved_uic_err |= hba->saved_uic_err; 7723 hba->saved_err = 0; 7724 hba->saved_uic_err = 0; 7725 hba->force_reset = false; 7726 hba->ufshcd_state = UFSHCD_STATE_RESET; 7727 spin_unlock_irqrestore(hba->host->host_lock, flags); 7728 7729 /* Reset the attached device */ 7730 ufshcd_device_reset(hba); 7731 7732 err = ufshcd_host_reset_and_restore(hba); 7733 7734 spin_lock_irqsave(hba->host->host_lock, flags); 7735 if (err) 7736 continue; 7737 /* Do not exit unless operational or dead */ 7738 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7739 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7740 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7741 err = -EAGAIN; 7742 } while (err && --retries); 7743 7744 /* 7745 * Inform scsi mid-layer that we did reset and allow to handle 7746 * Unit Attention properly. 7747 */ 7748 scsi_report_bus_reset(hba->host, 0); 7749 if (err) { 7750 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7751 hba->saved_err |= saved_err; 7752 hba->saved_uic_err |= saved_uic_err; 7753 } 7754 spin_unlock_irqrestore(hba->host->host_lock, flags); 7755 7756 return err; 7757 } 7758 7759 /** 7760 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7761 * @cmd: SCSI command pointer 7762 * 7763 * Return: SUCCESS or FAILED. 7764 */ 7765 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7766 { 7767 int err = SUCCESS; 7768 unsigned long flags; 7769 struct ufs_hba *hba; 7770 7771 hba = shost_priv(cmd->device->host); 7772 7773 /* 7774 * If runtime PM sent SSU and got a timeout, scsi_error_handler is 7775 * stuck in this function waiting for flush_work(&hba->eh_work). And 7776 * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do 7777 * ufshcd_link_recovery instead of eh_work to prevent deadlock. 7778 */ 7779 if (hba->pm_op_in_progress) { 7780 if (ufshcd_link_recovery(hba)) 7781 err = FAILED; 7782 7783 return err; 7784 } 7785 7786 spin_lock_irqsave(hba->host->host_lock, flags); 7787 hba->force_reset = true; 7788 ufshcd_schedule_eh_work(hba); 7789 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7790 spin_unlock_irqrestore(hba->host->host_lock, flags); 7791 7792 flush_work(&hba->eh_work); 7793 7794 spin_lock_irqsave(hba->host->host_lock, flags); 7795 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7796 err = FAILED; 7797 spin_unlock_irqrestore(hba->host->host_lock, flags); 7798 7799 return err; 7800 } 7801 7802 /** 7803 * ufshcd_get_max_icc_level - calculate the ICC level 7804 * @sup_curr_uA: max. current supported by the regulator 7805 * @start_scan: row at the desc table to start scan from 7806 * @buff: power descriptor buffer 7807 * 7808 * Return: calculated max ICC level for specific regulator. 7809 */ 7810 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7811 const char *buff) 7812 { 7813 int i; 7814 int curr_uA; 7815 u16 data; 7816 u16 unit; 7817 7818 for (i = start_scan; i >= 0; i--) { 7819 data = get_unaligned_be16(&buff[2 * i]); 7820 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7821 ATTR_ICC_LVL_UNIT_OFFSET; 7822 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7823 switch (unit) { 7824 case UFSHCD_NANO_AMP: 7825 curr_uA = curr_uA / 1000; 7826 break; 7827 case UFSHCD_MILI_AMP: 7828 curr_uA = curr_uA * 1000; 7829 break; 7830 case UFSHCD_AMP: 7831 curr_uA = curr_uA * 1000 * 1000; 7832 break; 7833 case UFSHCD_MICRO_AMP: 7834 default: 7835 break; 7836 } 7837 if (sup_curr_uA >= curr_uA) 7838 break; 7839 } 7840 if (i < 0) { 7841 i = 0; 7842 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7843 } 7844 7845 return (u32)i; 7846 } 7847 7848 /** 7849 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7850 * In case regulators are not initialized we'll return 0 7851 * @hba: per-adapter instance 7852 * @desc_buf: power descriptor buffer to extract ICC levels from. 7853 * 7854 * Return: calculated ICC level. 7855 */ 7856 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7857 const u8 *desc_buf) 7858 { 7859 u32 icc_level = 0; 7860 7861 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7862 !hba->vreg_info.vccq2) { 7863 /* 7864 * Using dev_dbg to avoid messages during runtime PM to avoid 7865 * never-ending cycles of messages written back to storage by 7866 * user space causing runtime resume, causing more messages and 7867 * so on. 7868 */ 7869 dev_dbg(hba->dev, 7870 "%s: Regulator capability was not set, actvIccLevel=%d", 7871 __func__, icc_level); 7872 goto out; 7873 } 7874 7875 if (hba->vreg_info.vcc->max_uA) 7876 icc_level = ufshcd_get_max_icc_level( 7877 hba->vreg_info.vcc->max_uA, 7878 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7879 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7880 7881 if (hba->vreg_info.vccq->max_uA) 7882 icc_level = ufshcd_get_max_icc_level( 7883 hba->vreg_info.vccq->max_uA, 7884 icc_level, 7885 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7886 7887 if (hba->vreg_info.vccq2->max_uA) 7888 icc_level = ufshcd_get_max_icc_level( 7889 hba->vreg_info.vccq2->max_uA, 7890 icc_level, 7891 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7892 out: 7893 return icc_level; 7894 } 7895 7896 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7897 { 7898 int ret; 7899 u8 *desc_buf; 7900 u32 icc_level; 7901 7902 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7903 if (!desc_buf) 7904 return; 7905 7906 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7907 desc_buf, QUERY_DESC_MAX_SIZE); 7908 if (ret) { 7909 dev_err(hba->dev, 7910 "%s: Failed reading power descriptor ret = %d", 7911 __func__, ret); 7912 goto out; 7913 } 7914 7915 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7916 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7917 7918 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7919 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7920 7921 if (ret) 7922 dev_err(hba->dev, 7923 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7924 __func__, icc_level, ret); 7925 7926 out: 7927 kfree(desc_buf); 7928 } 7929 7930 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7931 { 7932 struct Scsi_Host *shost = sdev->host; 7933 7934 scsi_autopm_get_device(sdev); 7935 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7936 if (sdev->rpm_autosuspend) 7937 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7938 shost->rpm_autosuspend_delay); 7939 scsi_autopm_put_device(sdev); 7940 } 7941 7942 /** 7943 * ufshcd_scsi_add_wlus - Adds required W-LUs 7944 * @hba: per-adapter instance 7945 * 7946 * UFS device specification requires the UFS devices to support 4 well known 7947 * logical units: 7948 * "REPORT_LUNS" (address: 01h) 7949 * "UFS Device" (address: 50h) 7950 * "RPMB" (address: 44h) 7951 * "BOOT" (address: 30h) 7952 * UFS device's power management needs to be controlled by "POWER CONDITION" 7953 * field of SSU (START STOP UNIT) command. But this "power condition" field 7954 * will take effect only when its sent to "UFS device" well known logical unit 7955 * hence we require the scsi_device instance to represent this logical unit in 7956 * order for the UFS host driver to send the SSU command for power management. 7957 * 7958 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 7959 * Block) LU so user space process can control this LU. User space may also 7960 * want to have access to BOOT LU. 7961 * 7962 * This function adds scsi device instances for each of all well known LUs 7963 * (except "REPORT LUNS" LU). 7964 * 7965 * Return: zero on success (all required W-LUs are added successfully), 7966 * non-zero error value on failure (if failed to add any of the required W-LU). 7967 */ 7968 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 7969 { 7970 int ret = 0; 7971 struct scsi_device *sdev_boot, *sdev_rpmb; 7972 7973 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 7974 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 7975 if (IS_ERR(hba->ufs_device_wlun)) { 7976 ret = PTR_ERR(hba->ufs_device_wlun); 7977 hba->ufs_device_wlun = NULL; 7978 goto out; 7979 } 7980 scsi_device_put(hba->ufs_device_wlun); 7981 7982 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 7983 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 7984 if (IS_ERR(sdev_rpmb)) { 7985 ret = PTR_ERR(sdev_rpmb); 7986 goto remove_ufs_device_wlun; 7987 } 7988 ufshcd_blk_pm_runtime_init(sdev_rpmb); 7989 scsi_device_put(sdev_rpmb); 7990 7991 sdev_boot = __scsi_add_device(hba->host, 0, 0, 7992 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 7993 if (IS_ERR(sdev_boot)) { 7994 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 7995 } else { 7996 ufshcd_blk_pm_runtime_init(sdev_boot); 7997 scsi_device_put(sdev_boot); 7998 } 7999 goto out; 8000 8001 remove_ufs_device_wlun: 8002 scsi_remove_device(hba->ufs_device_wlun); 8003 out: 8004 return ret; 8005 } 8006 8007 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 8008 { 8009 struct ufs_dev_info *dev_info = &hba->dev_info; 8010 u8 lun; 8011 u32 d_lu_wb_buf_alloc; 8012 u32 ext_ufs_feature; 8013 8014 if (!ufshcd_is_wb_allowed(hba)) 8015 return; 8016 8017 /* 8018 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 8019 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 8020 * enabled 8021 */ 8022 if (!(dev_info->wspecversion >= 0x310 || 8023 dev_info->wspecversion == 0x220 || 8024 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 8025 goto wb_disabled; 8026 8027 ext_ufs_feature = get_unaligned_be32(desc_buf + 8028 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8029 8030 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 8031 goto wb_disabled; 8032 8033 /* 8034 * WB may be supported but not configured while provisioning. The spec 8035 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 8036 * buffer configured. 8037 */ 8038 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 8039 8040 dev_info->b_presrv_uspc_en = 8041 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 8042 8043 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 8044 if (!get_unaligned_be32(desc_buf + 8045 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 8046 goto wb_disabled; 8047 } else { 8048 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 8049 d_lu_wb_buf_alloc = 0; 8050 ufshcd_read_unit_desc_param(hba, 8051 lun, 8052 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 8053 (u8 *)&d_lu_wb_buf_alloc, 8054 sizeof(d_lu_wb_buf_alloc)); 8055 if (d_lu_wb_buf_alloc) { 8056 dev_info->wb_dedicated_lu = lun; 8057 break; 8058 } 8059 } 8060 8061 if (!d_lu_wb_buf_alloc) 8062 goto wb_disabled; 8063 } 8064 8065 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8066 goto wb_disabled; 8067 8068 return; 8069 8070 wb_disabled: 8071 hba->caps &= ~UFSHCD_CAP_WB_EN; 8072 } 8073 8074 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8075 { 8076 struct ufs_dev_info *dev_info = &hba->dev_info; 8077 u32 ext_ufs_feature; 8078 u8 mask = 0; 8079 8080 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8081 return; 8082 8083 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8084 8085 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8086 mask |= MASK_EE_TOO_LOW_TEMP; 8087 8088 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8089 mask |= MASK_EE_TOO_HIGH_TEMP; 8090 8091 if (mask) { 8092 ufshcd_enable_ee(hba, mask); 8093 ufs_hwmon_probe(hba, mask); 8094 } 8095 } 8096 8097 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8098 { 8099 struct ufs_dev_info *dev_info = &hba->dev_info; 8100 u32 ext_ufs_feature; 8101 u32 ext_iid_en = 0; 8102 int err; 8103 8104 /* Only UFS-4.0 and above may support EXT_IID */ 8105 if (dev_info->wspecversion < 0x400) 8106 goto out; 8107 8108 ext_ufs_feature = get_unaligned_be32(desc_buf + 8109 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8110 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8111 goto out; 8112 8113 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8114 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8115 if (err) 8116 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8117 8118 out: 8119 dev_info->b_ext_iid_en = ext_iid_en; 8120 } 8121 8122 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8123 const struct ufs_dev_quirk *fixups) 8124 { 8125 const struct ufs_dev_quirk *f; 8126 struct ufs_dev_info *dev_info = &hba->dev_info; 8127 8128 if (!fixups) 8129 return; 8130 8131 for (f = fixups; f->quirk; f++) { 8132 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8133 f->wmanufacturerid == UFS_ANY_VENDOR) && 8134 ((dev_info->model && 8135 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8136 !strcmp(f->model, UFS_ANY_MODEL))) 8137 hba->dev_quirks |= f->quirk; 8138 } 8139 } 8140 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8141 8142 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8143 { 8144 /* fix by general quirk table */ 8145 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8146 8147 /* allow vendors to fix quirks */ 8148 ufshcd_vops_fixup_dev_quirks(hba); 8149 } 8150 8151 static void ufshcd_update_rtc(struct ufs_hba *hba) 8152 { 8153 struct timespec64 ts64; 8154 int err; 8155 u32 val; 8156 8157 ktime_get_real_ts64(&ts64); 8158 8159 if (ts64.tv_sec < hba->dev_info.rtc_time_baseline) { 8160 dev_warn_once(hba->dev, "%s: Current time precedes previous setting!\n", __func__); 8161 return; 8162 } 8163 8164 /* 8165 * The Absolute RTC mode has a 136-year limit, spanning from 2010 to 2146. If a time beyond 8166 * 2146 is required, it is recommended to choose the relative RTC mode. 8167 */ 8168 val = ts64.tv_sec - hba->dev_info.rtc_time_baseline; 8169 8170 ufshcd_rpm_get_sync(hba); 8171 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_SECONDS_PASSED, 8172 0, 0, &val); 8173 ufshcd_rpm_put_sync(hba); 8174 8175 if (err) 8176 dev_err(hba->dev, "%s: Failed to update rtc %d\n", __func__, err); 8177 else if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 8178 hba->dev_info.rtc_time_baseline = ts64.tv_sec; 8179 } 8180 8181 static void ufshcd_rtc_work(struct work_struct *work) 8182 { 8183 struct ufs_hba *hba; 8184 8185 hba = container_of(to_delayed_work(work), struct ufs_hba, ufs_rtc_update_work); 8186 8187 /* Update RTC only when there are no requests in progress and UFSHCI is operational */ 8188 if (!ufshcd_is_ufs_dev_busy(hba) && hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) 8189 ufshcd_update_rtc(hba); 8190 8191 if (ufshcd_is_ufs_dev_active(hba) && hba->dev_info.rtc_update_period) 8192 schedule_delayed_work(&hba->ufs_rtc_update_work, 8193 msecs_to_jiffies(hba->dev_info.rtc_update_period)); 8194 } 8195 8196 static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf) 8197 { 8198 u16 periodic_rtc_update = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_FRQ_RTC]); 8199 struct ufs_dev_info *dev_info = &hba->dev_info; 8200 8201 if (periodic_rtc_update & UFS_RTC_TIME_BASELINE) { 8202 dev_info->rtc_type = UFS_RTC_ABSOLUTE; 8203 8204 /* 8205 * The concept of measuring time in Linux as the number of seconds elapsed since 8206 * 00:00:00 UTC on January 1, 1970, and UFS ABS RTC is elapsed from January 1st 8207 * 2010 00:00, here we need to adjust ABS baseline. 8208 */ 8209 dev_info->rtc_time_baseline = mktime64(2010, 1, 1, 0, 0, 0) - 8210 mktime64(1970, 1, 1, 0, 0, 0); 8211 } else { 8212 dev_info->rtc_type = UFS_RTC_RELATIVE; 8213 dev_info->rtc_time_baseline = 0; 8214 } 8215 8216 /* 8217 * We ignore TIME_PERIOD defined in wPeriodicRTCUpdate because Spec does not clearly state 8218 * how to calculate the specific update period for each time unit. And we disable periodic 8219 * RTC update work, let user configure by sysfs node according to specific circumstance. 8220 */ 8221 dev_info->rtc_update_period = 0; 8222 } 8223 8224 static int ufs_get_device_desc(struct ufs_hba *hba) 8225 { 8226 int err; 8227 u8 model_index; 8228 u8 *desc_buf; 8229 struct ufs_dev_info *dev_info = &hba->dev_info; 8230 8231 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8232 if (!desc_buf) { 8233 err = -ENOMEM; 8234 goto out; 8235 } 8236 8237 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8238 QUERY_DESC_MAX_SIZE); 8239 if (err) { 8240 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8241 __func__, err); 8242 goto out; 8243 } 8244 8245 /* 8246 * getting vendor (manufacturerID) and Bank Index in big endian 8247 * format 8248 */ 8249 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8250 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8251 8252 /* getting Specification Version in big endian format */ 8253 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8254 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8255 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8256 8257 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8258 8259 err = ufshcd_read_string_desc(hba, model_index, 8260 &dev_info->model, SD_ASCII_STD); 8261 if (err < 0) { 8262 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8263 __func__, err); 8264 goto out; 8265 } 8266 8267 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8268 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8269 8270 ufs_fixup_device_setup(hba); 8271 8272 ufshcd_wb_probe(hba, desc_buf); 8273 8274 ufshcd_temp_notif_probe(hba, desc_buf); 8275 8276 ufs_init_rtc(hba, desc_buf); 8277 8278 if (hba->ext_iid_sup) 8279 ufshcd_ext_iid_probe(hba, desc_buf); 8280 8281 /* 8282 * ufshcd_read_string_desc returns size of the string 8283 * reset the error value 8284 */ 8285 err = 0; 8286 8287 out: 8288 kfree(desc_buf); 8289 return err; 8290 } 8291 8292 static void ufs_put_device_desc(struct ufs_hba *hba) 8293 { 8294 struct ufs_dev_info *dev_info = &hba->dev_info; 8295 8296 kfree(dev_info->model); 8297 dev_info->model = NULL; 8298 } 8299 8300 /** 8301 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8302 * less than device PA_TACTIVATE time. 8303 * @hba: per-adapter instance 8304 * 8305 * Some UFS devices require host PA_TACTIVATE to be lower than device 8306 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8307 * for such devices. 8308 * 8309 * Return: zero on success, non-zero error value on failure. 8310 */ 8311 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8312 { 8313 int ret = 0; 8314 u32 granularity, peer_granularity; 8315 u32 pa_tactivate, peer_pa_tactivate; 8316 u32 pa_tactivate_us, peer_pa_tactivate_us; 8317 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8318 8319 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8320 &granularity); 8321 if (ret) 8322 goto out; 8323 8324 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8325 &peer_granularity); 8326 if (ret) 8327 goto out; 8328 8329 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8330 (granularity > PA_GRANULARITY_MAX_VAL)) { 8331 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8332 __func__, granularity); 8333 return -EINVAL; 8334 } 8335 8336 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8337 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8338 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8339 __func__, peer_granularity); 8340 return -EINVAL; 8341 } 8342 8343 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8344 if (ret) 8345 goto out; 8346 8347 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8348 &peer_pa_tactivate); 8349 if (ret) 8350 goto out; 8351 8352 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8353 peer_pa_tactivate_us = peer_pa_tactivate * 8354 gran_to_us_table[peer_granularity - 1]; 8355 8356 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8357 u32 new_peer_pa_tactivate; 8358 8359 new_peer_pa_tactivate = pa_tactivate_us / 8360 gran_to_us_table[peer_granularity - 1]; 8361 new_peer_pa_tactivate++; 8362 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8363 new_peer_pa_tactivate); 8364 } 8365 8366 out: 8367 return ret; 8368 } 8369 8370 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8371 { 8372 ufshcd_vops_apply_dev_quirks(hba); 8373 8374 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8375 /* set 1ms timeout for PA_TACTIVATE */ 8376 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8377 8378 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8379 ufshcd_quirk_tune_host_pa_tactivate(hba); 8380 } 8381 8382 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8383 { 8384 hba->ufs_stats.hibern8_exit_cnt = 0; 8385 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8386 hba->req_abort_count = 0; 8387 } 8388 8389 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8390 { 8391 int err; 8392 u8 *desc_buf; 8393 8394 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8395 if (!desc_buf) { 8396 err = -ENOMEM; 8397 goto out; 8398 } 8399 8400 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8401 desc_buf, QUERY_DESC_MAX_SIZE); 8402 if (err) { 8403 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8404 __func__, err); 8405 goto out; 8406 } 8407 8408 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8409 hba->dev_info.max_lu_supported = 32; 8410 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8411 hba->dev_info.max_lu_supported = 8; 8412 8413 out: 8414 kfree(desc_buf); 8415 return err; 8416 } 8417 8418 struct ufs_ref_clk { 8419 unsigned long freq_hz; 8420 enum ufs_ref_clk_freq val; 8421 }; 8422 8423 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8424 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8425 {26000000, REF_CLK_FREQ_26_MHZ}, 8426 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8427 {52000000, REF_CLK_FREQ_52_MHZ}, 8428 {0, REF_CLK_FREQ_INVAL}, 8429 }; 8430 8431 static enum ufs_ref_clk_freq 8432 ufs_get_bref_clk_from_hz(unsigned long freq) 8433 { 8434 int i; 8435 8436 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8437 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8438 return ufs_ref_clk_freqs[i].val; 8439 8440 return REF_CLK_FREQ_INVAL; 8441 } 8442 8443 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8444 { 8445 unsigned long freq; 8446 8447 freq = clk_get_rate(refclk); 8448 8449 hba->dev_ref_clk_freq = 8450 ufs_get_bref_clk_from_hz(freq); 8451 8452 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8453 dev_err(hba->dev, 8454 "invalid ref_clk setting = %ld\n", freq); 8455 } 8456 8457 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8458 { 8459 int err; 8460 u32 ref_clk; 8461 u32 freq = hba->dev_ref_clk_freq; 8462 8463 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8464 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8465 8466 if (err) { 8467 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8468 err); 8469 goto out; 8470 } 8471 8472 if (ref_clk == freq) 8473 goto out; /* nothing to update */ 8474 8475 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8476 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8477 8478 if (err) { 8479 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8480 ufs_ref_clk_freqs[freq].freq_hz); 8481 goto out; 8482 } 8483 8484 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8485 ufs_ref_clk_freqs[freq].freq_hz); 8486 8487 out: 8488 return err; 8489 } 8490 8491 static int ufshcd_device_params_init(struct ufs_hba *hba) 8492 { 8493 bool flag; 8494 int ret; 8495 8496 /* Init UFS geometry descriptor related parameters */ 8497 ret = ufshcd_device_geo_params_init(hba); 8498 if (ret) 8499 goto out; 8500 8501 /* Check and apply UFS device quirks */ 8502 ret = ufs_get_device_desc(hba); 8503 if (ret) { 8504 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8505 __func__, ret); 8506 goto out; 8507 } 8508 8509 ufshcd_get_ref_clk_gating_wait(hba); 8510 8511 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8512 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8513 hba->dev_info.f_power_on_wp_en = flag; 8514 8515 /* Probe maximum power mode co-supported by both UFS host and device */ 8516 if (ufshcd_get_max_pwr_mode(hba)) 8517 dev_err(hba->dev, 8518 "%s: Failed getting max supported power mode\n", 8519 __func__); 8520 out: 8521 return ret; 8522 } 8523 8524 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8525 { 8526 int err; 8527 struct ufs_query_req *request = NULL; 8528 struct ufs_query_res *response = NULL; 8529 struct ufs_dev_info *dev_info = &hba->dev_info; 8530 struct utp_upiu_query_v4_0 *upiu_data; 8531 8532 if (dev_info->wspecversion < 0x400) 8533 return; 8534 8535 ufshcd_dev_man_lock(hba); 8536 8537 ufshcd_init_query(hba, &request, &response, 8538 UPIU_QUERY_OPCODE_WRITE_ATTR, 8539 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8540 8541 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8542 8543 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8544 8545 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8546 8547 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8548 8549 if (err) 8550 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8551 __func__, err); 8552 8553 ufshcd_dev_man_unlock(hba); 8554 } 8555 8556 /** 8557 * ufshcd_add_lus - probe and add UFS logical units 8558 * @hba: per-adapter instance 8559 * 8560 * Return: 0 upon success; < 0 upon failure. 8561 */ 8562 static int ufshcd_add_lus(struct ufs_hba *hba) 8563 { 8564 int ret; 8565 8566 /* Add required well known logical units to scsi mid layer */ 8567 ret = ufshcd_scsi_add_wlus(hba); 8568 if (ret) 8569 goto out; 8570 8571 /* Initialize devfreq after UFS device is detected */ 8572 if (ufshcd_is_clkscaling_supported(hba)) { 8573 memcpy(&hba->clk_scaling.saved_pwr_info, 8574 &hba->pwr_info, 8575 sizeof(struct ufs_pa_layer_attr)); 8576 hba->clk_scaling.is_allowed = true; 8577 8578 ret = ufshcd_devfreq_init(hba); 8579 if (ret) 8580 goto out; 8581 8582 hba->clk_scaling.is_enabled = true; 8583 ufshcd_init_clk_scaling_sysfs(hba); 8584 } 8585 8586 ufs_bsg_probe(hba); 8587 scsi_scan_host(hba->host); 8588 8589 out: 8590 return ret; 8591 } 8592 8593 /* SDB - Single Doorbell */ 8594 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8595 { 8596 size_t ucdl_size, utrdl_size; 8597 8598 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8599 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8600 hba->ucdl_dma_addr); 8601 8602 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8603 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8604 hba->utrdl_dma_addr); 8605 8606 devm_kfree(hba->dev, hba->lrb); 8607 } 8608 8609 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8610 { 8611 int ret; 8612 int old_nutrs = hba->nutrs; 8613 8614 ret = ufshcd_mcq_decide_queue_depth(hba); 8615 if (ret < 0) 8616 return ret; 8617 8618 hba->nutrs = ret; 8619 ret = ufshcd_mcq_init(hba); 8620 if (ret) 8621 goto err; 8622 8623 /* 8624 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8625 * Number of supported tags in MCQ mode may be larger than SDB mode. 8626 */ 8627 if (hba->nutrs != old_nutrs) { 8628 ufshcd_release_sdb_queue(hba, old_nutrs); 8629 ret = ufshcd_memory_alloc(hba); 8630 if (ret) 8631 goto err; 8632 ufshcd_host_memory_configure(hba); 8633 } 8634 8635 ret = ufshcd_mcq_memory_alloc(hba); 8636 if (ret) 8637 goto err; 8638 8639 return 0; 8640 err: 8641 hba->nutrs = old_nutrs; 8642 return ret; 8643 } 8644 8645 static void ufshcd_config_mcq(struct ufs_hba *hba) 8646 { 8647 int ret; 8648 u32 intrs; 8649 8650 ret = ufshcd_mcq_vops_config_esi(hba); 8651 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8652 8653 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8654 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8655 intrs &= ~MCQ_CQ_EVENT_STATUS; 8656 ufshcd_enable_intr(hba, intrs); 8657 ufshcd_mcq_make_queues_operational(hba); 8658 ufshcd_mcq_config_mac(hba, hba->nutrs); 8659 8660 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8661 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8662 8663 ufshcd_mcq_enable(hba); 8664 hba->mcq_enabled = true; 8665 8666 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8667 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8668 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8669 hba->nutrs); 8670 } 8671 8672 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8673 { 8674 int ret; 8675 struct Scsi_Host *host = hba->host; 8676 8677 hba->ufshcd_state = UFSHCD_STATE_RESET; 8678 8679 ret = ufshcd_link_startup(hba); 8680 if (ret) 8681 return ret; 8682 8683 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8684 return ret; 8685 8686 /* Debug counters initialization */ 8687 ufshcd_clear_dbg_ufs_stats(hba); 8688 8689 /* UniPro link is active now */ 8690 ufshcd_set_link_active(hba); 8691 8692 /* Reconfigure MCQ upon reset */ 8693 if (is_mcq_enabled(hba) && !init_dev_params) 8694 ufshcd_config_mcq(hba); 8695 8696 /* Verify device initialization by sending NOP OUT UPIU */ 8697 ret = ufshcd_verify_dev_init(hba); 8698 if (ret) 8699 return ret; 8700 8701 /* Initiate UFS initialization, and waiting until completion */ 8702 ret = ufshcd_complete_dev_init(hba); 8703 if (ret) 8704 return ret; 8705 8706 /* 8707 * Initialize UFS device parameters used by driver, these 8708 * parameters are associated with UFS descriptors. 8709 */ 8710 if (init_dev_params) { 8711 ret = ufshcd_device_params_init(hba); 8712 if (ret) 8713 return ret; 8714 if (is_mcq_supported(hba) && !hba->scsi_host_added) { 8715 ret = ufshcd_alloc_mcq(hba); 8716 if (!ret) { 8717 ufshcd_config_mcq(hba); 8718 } else { 8719 /* Continue with SDB mode */ 8720 use_mcq_mode = false; 8721 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 8722 ret); 8723 } 8724 ret = scsi_add_host(host, hba->dev); 8725 if (ret) { 8726 dev_err(hba->dev, "scsi_add_host failed\n"); 8727 return ret; 8728 } 8729 hba->scsi_host_added = true; 8730 } else if (is_mcq_supported(hba)) { 8731 /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */ 8732 ufshcd_config_mcq(hba); 8733 } 8734 } 8735 8736 ufshcd_tune_unipro_params(hba); 8737 8738 /* UFS device is also active now */ 8739 ufshcd_set_ufs_dev_active(hba); 8740 ufshcd_force_reset_auto_bkops(hba); 8741 8742 ufshcd_set_timestamp_attr(hba); 8743 schedule_delayed_work(&hba->ufs_rtc_update_work, 8744 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 8745 8746 /* Gear up to HS gear if supported */ 8747 if (hba->max_pwr_info.is_valid) { 8748 /* 8749 * Set the right value to bRefClkFreq before attempting to 8750 * switch to HS gears. 8751 */ 8752 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8753 ufshcd_set_dev_ref_clk(hba); 8754 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8755 if (ret) { 8756 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8757 __func__, ret); 8758 return ret; 8759 } 8760 } 8761 8762 return 0; 8763 } 8764 8765 /** 8766 * ufshcd_probe_hba - probe hba to detect device and initialize it 8767 * @hba: per-adapter instance 8768 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8769 * 8770 * Execute link-startup and verify device initialization 8771 * 8772 * Return: 0 upon success; < 0 upon failure. 8773 */ 8774 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8775 { 8776 ktime_t start = ktime_get(); 8777 unsigned long flags; 8778 int ret; 8779 8780 ret = ufshcd_device_init(hba, init_dev_params); 8781 if (ret) 8782 goto out; 8783 8784 if (!hba->pm_op_in_progress && 8785 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8786 /* Reset the device and controller before doing reinit */ 8787 ufshcd_device_reset(hba); 8788 ufshcd_hba_stop(hba); 8789 ufshcd_vops_reinit_notify(hba); 8790 ret = ufshcd_hba_enable(hba); 8791 if (ret) { 8792 dev_err(hba->dev, "Host controller enable failed\n"); 8793 ufshcd_print_evt_hist(hba); 8794 ufshcd_print_host_state(hba); 8795 goto out; 8796 } 8797 8798 /* Reinit the device */ 8799 ret = ufshcd_device_init(hba, init_dev_params); 8800 if (ret) 8801 goto out; 8802 } 8803 8804 ufshcd_print_pwr_info(hba); 8805 8806 /* 8807 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8808 * and for removable UFS card as well, hence always set the parameter. 8809 * Note: Error handler may issue the device reset hence resetting 8810 * bActiveICCLevel as well so it is always safe to set this here. 8811 */ 8812 ufshcd_set_active_icc_lvl(hba); 8813 8814 /* Enable UFS Write Booster if supported */ 8815 ufshcd_configure_wb(hba); 8816 8817 if (hba->ee_usr_mask) 8818 ufshcd_write_ee_control(hba); 8819 ufshcd_configure_auto_hibern8(hba); 8820 8821 out: 8822 spin_lock_irqsave(hba->host->host_lock, flags); 8823 if (ret) 8824 hba->ufshcd_state = UFSHCD_STATE_ERROR; 8825 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 8826 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 8827 spin_unlock_irqrestore(hba->host->host_lock, flags); 8828 8829 trace_ufshcd_init(dev_name(hba->dev), ret, 8830 ktime_to_us(ktime_sub(ktime_get(), start)), 8831 hba->curr_dev_pwr_mode, hba->uic_link_state); 8832 return ret; 8833 } 8834 8835 /** 8836 * ufshcd_async_scan - asynchronous execution for probing hba 8837 * @data: data pointer to pass to this function 8838 * @cookie: cookie data 8839 */ 8840 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8841 { 8842 struct ufs_hba *hba = (struct ufs_hba *)data; 8843 int ret; 8844 8845 down(&hba->host_sem); 8846 /* Initialize hba, detect and initialize UFS device */ 8847 ret = ufshcd_probe_hba(hba, true); 8848 up(&hba->host_sem); 8849 if (ret) 8850 goto out; 8851 8852 /* Probe and add UFS logical units */ 8853 ret = ufshcd_add_lus(hba); 8854 8855 out: 8856 pm_runtime_put_sync(hba->dev); 8857 8858 if (ret) 8859 dev_err(hba->dev, "%s failed: %d\n", __func__, ret); 8860 } 8861 8862 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8863 { 8864 struct ufs_hba *hba = shost_priv(scmd->device->host); 8865 8866 if (!hba->system_suspending) { 8867 /* Activate the error handler in the SCSI core. */ 8868 return SCSI_EH_NOT_HANDLED; 8869 } 8870 8871 /* 8872 * If we get here we know that no TMFs are outstanding and also that 8873 * the only pending command is a START STOP UNIT command. Handle the 8874 * timeout of that command directly to prevent a deadlock between 8875 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8876 */ 8877 ufshcd_link_recovery(hba); 8878 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8879 __func__, hba->outstanding_tasks); 8880 8881 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8882 } 8883 8884 static const struct attribute_group *ufshcd_driver_groups[] = { 8885 &ufs_sysfs_unit_descriptor_group, 8886 &ufs_sysfs_lun_attributes_group, 8887 NULL, 8888 }; 8889 8890 static struct ufs_hba_variant_params ufs_hba_vps = { 8891 .hba_enable_delay_us = 1000, 8892 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8893 .devfreq_profile.polling_ms = 100, 8894 .devfreq_profile.target = ufshcd_devfreq_target, 8895 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8896 .ondemand_data.upthreshold = 70, 8897 .ondemand_data.downdifferential = 5, 8898 }; 8899 8900 static const struct scsi_host_template ufshcd_driver_template = { 8901 .module = THIS_MODULE, 8902 .name = UFSHCD, 8903 .proc_name = UFSHCD, 8904 .map_queues = ufshcd_map_queues, 8905 .queuecommand = ufshcd_queuecommand, 8906 .mq_poll = ufshcd_poll, 8907 .slave_alloc = ufshcd_slave_alloc, 8908 .slave_configure = ufshcd_slave_configure, 8909 .slave_destroy = ufshcd_slave_destroy, 8910 .change_queue_depth = ufshcd_change_queue_depth, 8911 .eh_abort_handler = ufshcd_abort, 8912 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8913 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8914 .eh_timed_out = ufshcd_eh_timed_out, 8915 .this_id = -1, 8916 .sg_tablesize = SG_ALL, 8917 .cmd_per_lun = UFSHCD_CMD_PER_LUN, 8918 .can_queue = UFSHCD_CAN_QUEUE, 8919 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8920 .max_sectors = SZ_1M / SECTOR_SIZE, 8921 .max_host_blocked = 1, 8922 .track_queue_depth = 1, 8923 .skip_settle_delay = 1, 8924 .sdev_groups = ufshcd_driver_groups, 8925 }; 8926 8927 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8928 int ua) 8929 { 8930 int ret; 8931 8932 if (!vreg) 8933 return 0; 8934 8935 /* 8936 * "set_load" operation shall be required on those regulators 8937 * which specifically configured current limitation. Otherwise 8938 * zero max_uA may cause unexpected behavior when regulator is 8939 * enabled or set as high power mode. 8940 */ 8941 if (!vreg->max_uA) 8942 return 0; 8943 8944 ret = regulator_set_load(vreg->reg, ua); 8945 if (ret < 0) { 8946 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 8947 __func__, vreg->name, ua, ret); 8948 } 8949 8950 return ret; 8951 } 8952 8953 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 8954 struct ufs_vreg *vreg) 8955 { 8956 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 8957 } 8958 8959 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 8960 struct ufs_vreg *vreg) 8961 { 8962 if (!vreg) 8963 return 0; 8964 8965 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 8966 } 8967 8968 static int ufshcd_config_vreg(struct device *dev, 8969 struct ufs_vreg *vreg, bool on) 8970 { 8971 if (regulator_count_voltages(vreg->reg) <= 0) 8972 return 0; 8973 8974 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 8975 } 8976 8977 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 8978 { 8979 int ret = 0; 8980 8981 if (!vreg || vreg->enabled) 8982 goto out; 8983 8984 ret = ufshcd_config_vreg(dev, vreg, true); 8985 if (!ret) 8986 ret = regulator_enable(vreg->reg); 8987 8988 if (!ret) 8989 vreg->enabled = true; 8990 else 8991 dev_err(dev, "%s: %s enable failed, err=%d\n", 8992 __func__, vreg->name, ret); 8993 out: 8994 return ret; 8995 } 8996 8997 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 8998 { 8999 int ret = 0; 9000 9001 if (!vreg || !vreg->enabled || vreg->always_on) 9002 goto out; 9003 9004 ret = regulator_disable(vreg->reg); 9005 9006 if (!ret) { 9007 /* ignore errors on applying disable config */ 9008 ufshcd_config_vreg(dev, vreg, false); 9009 vreg->enabled = false; 9010 } else { 9011 dev_err(dev, "%s: %s disable failed, err=%d\n", 9012 __func__, vreg->name, ret); 9013 } 9014 out: 9015 return ret; 9016 } 9017 9018 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 9019 { 9020 int ret = 0; 9021 struct device *dev = hba->dev; 9022 struct ufs_vreg_info *info = &hba->vreg_info; 9023 9024 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 9025 if (ret) 9026 goto out; 9027 9028 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 9029 if (ret) 9030 goto out; 9031 9032 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 9033 9034 out: 9035 if (ret) { 9036 ufshcd_toggle_vreg(dev, info->vccq2, false); 9037 ufshcd_toggle_vreg(dev, info->vccq, false); 9038 ufshcd_toggle_vreg(dev, info->vcc, false); 9039 } 9040 return ret; 9041 } 9042 9043 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9044 { 9045 struct ufs_vreg_info *info = &hba->vreg_info; 9046 9047 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9048 } 9049 9050 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9051 { 9052 int ret = 0; 9053 9054 if (!vreg) 9055 goto out; 9056 9057 vreg->reg = devm_regulator_get(dev, vreg->name); 9058 if (IS_ERR(vreg->reg)) { 9059 ret = PTR_ERR(vreg->reg); 9060 dev_err(dev, "%s: %s get failed, err=%d\n", 9061 __func__, vreg->name, ret); 9062 } 9063 out: 9064 return ret; 9065 } 9066 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9067 9068 static int ufshcd_init_vreg(struct ufs_hba *hba) 9069 { 9070 int ret = 0; 9071 struct device *dev = hba->dev; 9072 struct ufs_vreg_info *info = &hba->vreg_info; 9073 9074 ret = ufshcd_get_vreg(dev, info->vcc); 9075 if (ret) 9076 goto out; 9077 9078 ret = ufshcd_get_vreg(dev, info->vccq); 9079 if (!ret) 9080 ret = ufshcd_get_vreg(dev, info->vccq2); 9081 out: 9082 return ret; 9083 } 9084 9085 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9086 { 9087 struct ufs_vreg_info *info = &hba->vreg_info; 9088 9089 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9090 } 9091 9092 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9093 { 9094 int ret = 0; 9095 struct ufs_clk_info *clki; 9096 struct list_head *head = &hba->clk_list_head; 9097 unsigned long flags; 9098 ktime_t start = ktime_get(); 9099 bool clk_state_changed = false; 9100 9101 if (list_empty(head)) 9102 goto out; 9103 9104 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9105 if (ret) 9106 return ret; 9107 9108 list_for_each_entry(clki, head, list) { 9109 if (!IS_ERR_OR_NULL(clki->clk)) { 9110 /* 9111 * Don't disable clocks which are needed 9112 * to keep the link active. 9113 */ 9114 if (ufshcd_is_link_active(hba) && 9115 clki->keep_link_active) 9116 continue; 9117 9118 clk_state_changed = on ^ clki->enabled; 9119 if (on && !clki->enabled) { 9120 ret = clk_prepare_enable(clki->clk); 9121 if (ret) { 9122 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9123 __func__, clki->name, ret); 9124 goto out; 9125 } 9126 } else if (!on && clki->enabled) { 9127 clk_disable_unprepare(clki->clk); 9128 } 9129 clki->enabled = on; 9130 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9131 clki->name, on ? "en" : "dis"); 9132 } 9133 } 9134 9135 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9136 if (ret) 9137 return ret; 9138 9139 if (!ufshcd_is_clkscaling_supported(hba)) 9140 ufshcd_pm_qos_update(hba, on); 9141 out: 9142 if (ret) { 9143 list_for_each_entry(clki, head, list) { 9144 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9145 clk_disable_unprepare(clki->clk); 9146 } 9147 } else if (!ret && on) { 9148 spin_lock_irqsave(hba->host->host_lock, flags); 9149 hba->clk_gating.state = CLKS_ON; 9150 trace_ufshcd_clk_gating(dev_name(hba->dev), 9151 hba->clk_gating.state); 9152 spin_unlock_irqrestore(hba->host->host_lock, flags); 9153 } 9154 9155 if (clk_state_changed) 9156 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9157 (on ? "on" : "off"), 9158 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9159 return ret; 9160 } 9161 9162 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9163 { 9164 u32 freq; 9165 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9166 9167 if (ret) { 9168 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9169 return REF_CLK_FREQ_INVAL; 9170 } 9171 9172 return ufs_get_bref_clk_from_hz(freq); 9173 } 9174 9175 static int ufshcd_init_clocks(struct ufs_hba *hba) 9176 { 9177 int ret = 0; 9178 struct ufs_clk_info *clki; 9179 struct device *dev = hba->dev; 9180 struct list_head *head = &hba->clk_list_head; 9181 9182 if (list_empty(head)) 9183 goto out; 9184 9185 list_for_each_entry(clki, head, list) { 9186 if (!clki->name) 9187 continue; 9188 9189 clki->clk = devm_clk_get(dev, clki->name); 9190 if (IS_ERR(clki->clk)) { 9191 ret = PTR_ERR(clki->clk); 9192 dev_err(dev, "%s: %s clk get failed, %d\n", 9193 __func__, clki->name, ret); 9194 goto out; 9195 } 9196 9197 /* 9198 * Parse device ref clk freq as per device tree "ref_clk". 9199 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9200 * in ufshcd_alloc_host(). 9201 */ 9202 if (!strcmp(clki->name, "ref_clk")) 9203 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9204 9205 if (clki->max_freq) { 9206 ret = clk_set_rate(clki->clk, clki->max_freq); 9207 if (ret) { 9208 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9209 __func__, clki->name, 9210 clki->max_freq, ret); 9211 goto out; 9212 } 9213 clki->curr_freq = clki->max_freq; 9214 } 9215 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9216 clki->name, clk_get_rate(clki->clk)); 9217 } 9218 9219 /* Set Max. frequency for all clocks */ 9220 if (hba->use_pm_opp) { 9221 ret = ufshcd_opp_set_rate(hba, ULONG_MAX); 9222 if (ret) { 9223 dev_err(hba->dev, "%s: failed to set OPP: %d", __func__, 9224 ret); 9225 goto out; 9226 } 9227 } 9228 9229 out: 9230 return ret; 9231 } 9232 9233 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9234 { 9235 int err = 0; 9236 9237 if (!hba->vops) 9238 goto out; 9239 9240 err = ufshcd_vops_init(hba); 9241 if (err) 9242 dev_err_probe(hba->dev, err, 9243 "%s: variant %s init failed with err %d\n", 9244 __func__, ufshcd_get_var_name(hba), err); 9245 out: 9246 return err; 9247 } 9248 9249 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9250 { 9251 if (!hba->vops) 9252 return; 9253 9254 ufshcd_vops_exit(hba); 9255 } 9256 9257 static int ufshcd_hba_init(struct ufs_hba *hba) 9258 { 9259 int err; 9260 9261 /* 9262 * Handle host controller power separately from the UFS device power 9263 * rails as it will help controlling the UFS host controller power 9264 * collapse easily which is different than UFS device power collapse. 9265 * Also, enable the host controller power before we go ahead with rest 9266 * of the initialization here. 9267 */ 9268 err = ufshcd_init_hba_vreg(hba); 9269 if (err) 9270 goto out; 9271 9272 err = ufshcd_setup_hba_vreg(hba, true); 9273 if (err) 9274 goto out; 9275 9276 err = ufshcd_init_clocks(hba); 9277 if (err) 9278 goto out_disable_hba_vreg; 9279 9280 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9281 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9282 9283 err = ufshcd_setup_clocks(hba, true); 9284 if (err) 9285 goto out_disable_hba_vreg; 9286 9287 err = ufshcd_init_vreg(hba); 9288 if (err) 9289 goto out_disable_clks; 9290 9291 err = ufshcd_setup_vreg(hba, true); 9292 if (err) 9293 goto out_disable_clks; 9294 9295 err = ufshcd_variant_hba_init(hba); 9296 if (err) 9297 goto out_disable_vreg; 9298 9299 ufs_debugfs_hba_init(hba); 9300 ufs_fault_inject_hba_init(hba); 9301 9302 hba->is_powered = true; 9303 goto out; 9304 9305 out_disable_vreg: 9306 ufshcd_setup_vreg(hba, false); 9307 out_disable_clks: 9308 ufshcd_setup_clocks(hba, false); 9309 out_disable_hba_vreg: 9310 ufshcd_setup_hba_vreg(hba, false); 9311 out: 9312 return err; 9313 } 9314 9315 static void ufshcd_hba_exit(struct ufs_hba *hba) 9316 { 9317 if (hba->is_powered) { 9318 ufshcd_pm_qos_exit(hba); 9319 ufshcd_exit_clk_scaling(hba); 9320 ufshcd_exit_clk_gating(hba); 9321 if (hba->eh_wq) 9322 destroy_workqueue(hba->eh_wq); 9323 ufs_debugfs_hba_exit(hba); 9324 ufshcd_variant_hba_exit(hba); 9325 ufshcd_setup_vreg(hba, false); 9326 ufshcd_setup_clocks(hba, false); 9327 ufshcd_setup_hba_vreg(hba, false); 9328 hba->is_powered = false; 9329 ufs_put_device_desc(hba); 9330 } 9331 } 9332 9333 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9334 enum ufs_dev_pwr_mode pwr_mode, 9335 struct scsi_sense_hdr *sshdr) 9336 { 9337 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9338 struct scsi_failure failure_defs[] = { 9339 { 9340 .allowed = 2, 9341 .result = SCMD_FAILURE_RESULT_ANY, 9342 }, 9343 }; 9344 struct scsi_failures failures = { 9345 .failure_definitions = failure_defs, 9346 }; 9347 const struct scsi_exec_args args = { 9348 .failures = &failures, 9349 .sshdr = sshdr, 9350 .req_flags = BLK_MQ_REQ_PM, 9351 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9352 }; 9353 9354 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9355 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9356 &args); 9357 } 9358 9359 /** 9360 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9361 * power mode 9362 * @hba: per adapter instance 9363 * @pwr_mode: device power mode to set 9364 * 9365 * Return: 0 if requested power mode is set successfully; 9366 * < 0 if failed to set the requested power mode. 9367 */ 9368 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9369 enum ufs_dev_pwr_mode pwr_mode) 9370 { 9371 struct scsi_sense_hdr sshdr; 9372 struct scsi_device *sdp; 9373 unsigned long flags; 9374 int ret; 9375 9376 spin_lock_irqsave(hba->host->host_lock, flags); 9377 sdp = hba->ufs_device_wlun; 9378 if (sdp && scsi_device_online(sdp)) 9379 ret = scsi_device_get(sdp); 9380 else 9381 ret = -ENODEV; 9382 spin_unlock_irqrestore(hba->host->host_lock, flags); 9383 9384 if (ret) 9385 return ret; 9386 9387 /* 9388 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9389 * handling, which would wait for host to be resumed. Since we know 9390 * we are functional while we are here, skip host resume in error 9391 * handling context. 9392 */ 9393 hba->host->eh_noresume = 1; 9394 9395 /* 9396 * Current function would be generally called from the power management 9397 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9398 * already suspended childs. 9399 */ 9400 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9401 if (ret) { 9402 sdev_printk(KERN_WARNING, sdp, 9403 "START_STOP failed for power mode: %d, result %x\n", 9404 pwr_mode, ret); 9405 if (ret > 0) { 9406 if (scsi_sense_valid(&sshdr)) 9407 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9408 ret = -EIO; 9409 } 9410 } else { 9411 hba->curr_dev_pwr_mode = pwr_mode; 9412 } 9413 9414 scsi_device_put(sdp); 9415 hba->host->eh_noresume = 0; 9416 return ret; 9417 } 9418 9419 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9420 enum uic_link_state req_link_state, 9421 bool check_for_bkops) 9422 { 9423 int ret = 0; 9424 9425 if (req_link_state == hba->uic_link_state) 9426 return 0; 9427 9428 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9429 ret = ufshcd_uic_hibern8_enter(hba); 9430 if (!ret) { 9431 ufshcd_set_link_hibern8(hba); 9432 } else { 9433 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9434 __func__, ret); 9435 goto out; 9436 } 9437 } 9438 /* 9439 * If autobkops is enabled, link can't be turned off because 9440 * turning off the link would also turn off the device, except in the 9441 * case of DeepSleep where the device is expected to remain powered. 9442 */ 9443 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9444 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9445 /* 9446 * Let's make sure that link is in low power mode, we are doing 9447 * this currently by putting the link in Hibern8. Otherway to 9448 * put the link in low power mode is to send the DME end point 9449 * to device and then send the DME reset command to local 9450 * unipro. But putting the link in hibern8 is much faster. 9451 * 9452 * Note also that putting the link in Hibern8 is a requirement 9453 * for entering DeepSleep. 9454 */ 9455 ret = ufshcd_uic_hibern8_enter(hba); 9456 if (ret) { 9457 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9458 __func__, ret); 9459 goto out; 9460 } 9461 /* 9462 * Change controller state to "reset state" which 9463 * should also put the link in off/reset state 9464 */ 9465 ufshcd_hba_stop(hba); 9466 /* 9467 * TODO: Check if we need any delay to make sure that 9468 * controller is reset 9469 */ 9470 ufshcd_set_link_off(hba); 9471 } 9472 9473 out: 9474 return ret; 9475 } 9476 9477 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9478 { 9479 bool vcc_off = false; 9480 9481 /* 9482 * It seems some UFS devices may keep drawing more than sleep current 9483 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9484 * To avoid this situation, add 2ms delay before putting these UFS 9485 * rails in LPM mode. 9486 */ 9487 if (!ufshcd_is_link_active(hba) && 9488 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9489 usleep_range(2000, 2100); 9490 9491 /* 9492 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9493 * power. 9494 * 9495 * If UFS device and link is in OFF state, all power supplies (VCC, 9496 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9497 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9498 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9499 * 9500 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9501 * in low power state which would save some power. 9502 * 9503 * If Write Booster is enabled and the device needs to flush the WB 9504 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9505 */ 9506 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9507 !hba->dev_info.is_lu_power_on_wp) { 9508 ufshcd_setup_vreg(hba, false); 9509 vcc_off = true; 9510 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9511 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9512 vcc_off = true; 9513 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9514 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9515 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9516 } 9517 } 9518 9519 /* 9520 * Some UFS devices require delay after VCC power rail is turned-off. 9521 */ 9522 if (vcc_off && hba->vreg_info.vcc && 9523 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9524 usleep_range(5000, 5100); 9525 } 9526 9527 #ifdef CONFIG_PM 9528 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9529 { 9530 int ret = 0; 9531 9532 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9533 !hba->dev_info.is_lu_power_on_wp) { 9534 ret = ufshcd_setup_vreg(hba, true); 9535 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9536 if (!ufshcd_is_link_active(hba)) { 9537 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9538 if (ret) 9539 goto vcc_disable; 9540 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9541 if (ret) 9542 goto vccq_lpm; 9543 } 9544 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9545 } 9546 goto out; 9547 9548 vccq_lpm: 9549 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9550 vcc_disable: 9551 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9552 out: 9553 return ret; 9554 } 9555 #endif /* CONFIG_PM */ 9556 9557 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9558 { 9559 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9560 ufshcd_setup_hba_vreg(hba, false); 9561 } 9562 9563 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9564 { 9565 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9566 ufshcd_setup_hba_vreg(hba, true); 9567 } 9568 9569 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9570 { 9571 int ret = 0; 9572 bool check_for_bkops; 9573 enum ufs_pm_level pm_lvl; 9574 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9575 enum uic_link_state req_link_state; 9576 9577 hba->pm_op_in_progress = true; 9578 if (pm_op != UFS_SHUTDOWN_PM) { 9579 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9580 hba->rpm_lvl : hba->spm_lvl; 9581 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9582 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9583 } else { 9584 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9585 req_link_state = UIC_LINK_OFF_STATE; 9586 } 9587 9588 /* 9589 * If we can't transition into any of the low power modes 9590 * just gate the clocks. 9591 */ 9592 ufshcd_hold(hba); 9593 hba->clk_gating.is_suspended = true; 9594 9595 if (ufshcd_is_clkscaling_supported(hba)) 9596 ufshcd_clk_scaling_suspend(hba, true); 9597 9598 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9599 req_link_state == UIC_LINK_ACTIVE_STATE) { 9600 goto vops_suspend; 9601 } 9602 9603 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9604 (req_link_state == hba->uic_link_state)) 9605 goto enable_scaling; 9606 9607 /* UFS device & link must be active before we enter in this function */ 9608 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9609 ret = -EINVAL; 9610 goto enable_scaling; 9611 } 9612 9613 if (pm_op == UFS_RUNTIME_PM) { 9614 if (ufshcd_can_autobkops_during_suspend(hba)) { 9615 /* 9616 * The device is idle with no requests in the queue, 9617 * allow background operations if bkops status shows 9618 * that performance might be impacted. 9619 */ 9620 ret = ufshcd_urgent_bkops(hba); 9621 if (ret) { 9622 /* 9623 * If return err in suspend flow, IO will hang. 9624 * Trigger error handler and break suspend for 9625 * error recovery. 9626 */ 9627 ufshcd_force_error_recovery(hba); 9628 ret = -EBUSY; 9629 goto enable_scaling; 9630 } 9631 } else { 9632 /* make sure that auto bkops is disabled */ 9633 ufshcd_disable_auto_bkops(hba); 9634 } 9635 /* 9636 * If device needs to do BKOP or WB buffer flush during 9637 * Hibern8, keep device power mode as "active power mode" 9638 * and VCC supply. 9639 */ 9640 hba->dev_info.b_rpm_dev_flush_capable = 9641 hba->auto_bkops_enabled || 9642 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9643 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9644 ufshcd_is_auto_hibern8_enabled(hba))) && 9645 ufshcd_wb_need_flush(hba)); 9646 } 9647 9648 flush_work(&hba->eeh_work); 9649 9650 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9651 if (ret) 9652 goto enable_scaling; 9653 9654 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9655 if (pm_op != UFS_RUNTIME_PM) 9656 /* ensure that bkops is disabled */ 9657 ufshcd_disable_auto_bkops(hba); 9658 9659 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9660 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9661 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9662 /* 9663 * If return err in suspend flow, IO will hang. 9664 * Trigger error handler and break suspend for 9665 * error recovery. 9666 */ 9667 ufshcd_force_error_recovery(hba); 9668 ret = -EBUSY; 9669 } 9670 if (ret) 9671 goto enable_scaling; 9672 } 9673 } 9674 9675 /* 9676 * In the case of DeepSleep, the device is expected to remain powered 9677 * with the link off, so do not check for bkops. 9678 */ 9679 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9680 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9681 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9682 /* 9683 * If return err in suspend flow, IO will hang. 9684 * Trigger error handler and break suspend for 9685 * error recovery. 9686 */ 9687 ufshcd_force_error_recovery(hba); 9688 ret = -EBUSY; 9689 } 9690 if (ret) 9691 goto set_dev_active; 9692 9693 vops_suspend: 9694 /* 9695 * Call vendor specific suspend callback. As these callbacks may access 9696 * vendor specific host controller register space call them before the 9697 * host clocks are ON. 9698 */ 9699 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9700 if (ret) 9701 goto set_link_active; 9702 9703 cancel_delayed_work_sync(&hba->ufs_rtc_update_work); 9704 goto out; 9705 9706 set_link_active: 9707 /* 9708 * Device hardware reset is required to exit DeepSleep. Also, for 9709 * DeepSleep, the link is off so host reset and restore will be done 9710 * further below. 9711 */ 9712 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9713 ufshcd_device_reset(hba); 9714 WARN_ON(!ufshcd_is_link_off(hba)); 9715 } 9716 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9717 ufshcd_set_link_active(hba); 9718 else if (ufshcd_is_link_off(hba)) 9719 ufshcd_host_reset_and_restore(hba); 9720 set_dev_active: 9721 /* Can also get here needing to exit DeepSleep */ 9722 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9723 ufshcd_device_reset(hba); 9724 ufshcd_host_reset_and_restore(hba); 9725 } 9726 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9727 ufshcd_disable_auto_bkops(hba); 9728 enable_scaling: 9729 if (ufshcd_is_clkscaling_supported(hba)) 9730 ufshcd_clk_scaling_suspend(hba, false); 9731 9732 hba->dev_info.b_rpm_dev_flush_capable = false; 9733 out: 9734 if (hba->dev_info.b_rpm_dev_flush_capable) { 9735 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9736 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9737 } 9738 9739 if (ret) { 9740 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9741 hba->clk_gating.is_suspended = false; 9742 ufshcd_release(hba); 9743 } 9744 hba->pm_op_in_progress = false; 9745 return ret; 9746 } 9747 9748 #ifdef CONFIG_PM 9749 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9750 { 9751 int ret; 9752 enum uic_link_state old_link_state = hba->uic_link_state; 9753 9754 hba->pm_op_in_progress = true; 9755 9756 /* 9757 * Call vendor specific resume callback. As these callbacks may access 9758 * vendor specific host controller register space call them when the 9759 * host clocks are ON. 9760 */ 9761 ret = ufshcd_vops_resume(hba, pm_op); 9762 if (ret) 9763 goto out; 9764 9765 /* For DeepSleep, the only supported option is to have the link off */ 9766 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9767 9768 if (ufshcd_is_link_hibern8(hba)) { 9769 ret = ufshcd_uic_hibern8_exit(hba); 9770 if (!ret) { 9771 ufshcd_set_link_active(hba); 9772 } else { 9773 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9774 __func__, ret); 9775 goto vendor_suspend; 9776 } 9777 } else if (ufshcd_is_link_off(hba)) { 9778 /* 9779 * A full initialization of the host and the device is 9780 * required since the link was put to off during suspend. 9781 * Note, in the case of DeepSleep, the device will exit 9782 * DeepSleep due to device reset. 9783 */ 9784 ret = ufshcd_reset_and_restore(hba); 9785 /* 9786 * ufshcd_reset_and_restore() should have already 9787 * set the link state as active 9788 */ 9789 if (ret || !ufshcd_is_link_active(hba)) 9790 goto vendor_suspend; 9791 } 9792 9793 if (!ufshcd_is_ufs_dev_active(hba)) { 9794 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9795 if (ret) 9796 goto set_old_link_state; 9797 ufshcd_set_timestamp_attr(hba); 9798 schedule_delayed_work(&hba->ufs_rtc_update_work, 9799 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 9800 } 9801 9802 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9803 ufshcd_enable_auto_bkops(hba); 9804 else 9805 /* 9806 * If BKOPs operations are urgently needed at this moment then 9807 * keep auto-bkops enabled or else disable it. 9808 */ 9809 ufshcd_urgent_bkops(hba); 9810 9811 if (hba->ee_usr_mask) 9812 ufshcd_write_ee_control(hba); 9813 9814 if (ufshcd_is_clkscaling_supported(hba)) 9815 ufshcd_clk_scaling_suspend(hba, false); 9816 9817 if (hba->dev_info.b_rpm_dev_flush_capable) { 9818 hba->dev_info.b_rpm_dev_flush_capable = false; 9819 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9820 } 9821 9822 ufshcd_configure_auto_hibern8(hba); 9823 9824 goto out; 9825 9826 set_old_link_state: 9827 ufshcd_link_state_transition(hba, old_link_state, 0); 9828 vendor_suspend: 9829 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9830 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9831 out: 9832 if (ret) 9833 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9834 hba->clk_gating.is_suspended = false; 9835 ufshcd_release(hba); 9836 hba->pm_op_in_progress = false; 9837 return ret; 9838 } 9839 9840 static int ufshcd_wl_runtime_suspend(struct device *dev) 9841 { 9842 struct scsi_device *sdev = to_scsi_device(dev); 9843 struct ufs_hba *hba; 9844 int ret; 9845 ktime_t start = ktime_get(); 9846 9847 hba = shost_priv(sdev->host); 9848 9849 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9850 if (ret) 9851 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9852 9853 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9854 ktime_to_us(ktime_sub(ktime_get(), start)), 9855 hba->curr_dev_pwr_mode, hba->uic_link_state); 9856 9857 return ret; 9858 } 9859 9860 static int ufshcd_wl_runtime_resume(struct device *dev) 9861 { 9862 struct scsi_device *sdev = to_scsi_device(dev); 9863 struct ufs_hba *hba; 9864 int ret = 0; 9865 ktime_t start = ktime_get(); 9866 9867 hba = shost_priv(sdev->host); 9868 9869 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9870 if (ret) 9871 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9872 9873 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9874 ktime_to_us(ktime_sub(ktime_get(), start)), 9875 hba->curr_dev_pwr_mode, hba->uic_link_state); 9876 9877 return ret; 9878 } 9879 #endif 9880 9881 #ifdef CONFIG_PM_SLEEP 9882 static int ufshcd_wl_suspend(struct device *dev) 9883 { 9884 struct scsi_device *sdev = to_scsi_device(dev); 9885 struct ufs_hba *hba; 9886 int ret = 0; 9887 ktime_t start = ktime_get(); 9888 9889 hba = shost_priv(sdev->host); 9890 down(&hba->host_sem); 9891 hba->system_suspending = true; 9892 9893 if (pm_runtime_suspended(dev)) 9894 goto out; 9895 9896 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9897 if (ret) { 9898 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9899 up(&hba->host_sem); 9900 } 9901 9902 out: 9903 if (!ret) 9904 hba->is_sys_suspended = true; 9905 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9906 ktime_to_us(ktime_sub(ktime_get(), start)), 9907 hba->curr_dev_pwr_mode, hba->uic_link_state); 9908 9909 return ret; 9910 } 9911 9912 static int ufshcd_wl_resume(struct device *dev) 9913 { 9914 struct scsi_device *sdev = to_scsi_device(dev); 9915 struct ufs_hba *hba; 9916 int ret = 0; 9917 ktime_t start = ktime_get(); 9918 9919 hba = shost_priv(sdev->host); 9920 9921 if (pm_runtime_suspended(dev)) 9922 goto out; 9923 9924 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9925 if (ret) 9926 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9927 out: 9928 trace_ufshcd_wl_resume(dev_name(dev), ret, 9929 ktime_to_us(ktime_sub(ktime_get(), start)), 9930 hba->curr_dev_pwr_mode, hba->uic_link_state); 9931 if (!ret) 9932 hba->is_sys_suspended = false; 9933 hba->system_suspending = false; 9934 up(&hba->host_sem); 9935 return ret; 9936 } 9937 #endif 9938 9939 /** 9940 * ufshcd_suspend - helper function for suspend operations 9941 * @hba: per adapter instance 9942 * 9943 * This function will put disable irqs, turn off clocks 9944 * and set vreg and hba-vreg in lpm mode. 9945 * 9946 * Return: 0 upon success; < 0 upon failure. 9947 */ 9948 static int ufshcd_suspend(struct ufs_hba *hba) 9949 { 9950 int ret; 9951 9952 if (!hba->is_powered) 9953 return 0; 9954 /* 9955 * Disable the host irq as host controller as there won't be any 9956 * host controller transaction expected till resume. 9957 */ 9958 ufshcd_disable_irq(hba); 9959 ret = ufshcd_setup_clocks(hba, false); 9960 if (ret) { 9961 ufshcd_enable_irq(hba); 9962 return ret; 9963 } 9964 if (ufshcd_is_clkgating_allowed(hba)) { 9965 hba->clk_gating.state = CLKS_OFF; 9966 trace_ufshcd_clk_gating(dev_name(hba->dev), 9967 hba->clk_gating.state); 9968 } 9969 9970 ufshcd_vreg_set_lpm(hba); 9971 /* Put the host controller in low power mode if possible */ 9972 ufshcd_hba_vreg_set_lpm(hba); 9973 ufshcd_pm_qos_update(hba, false); 9974 return ret; 9975 } 9976 9977 #ifdef CONFIG_PM 9978 /** 9979 * ufshcd_resume - helper function for resume operations 9980 * @hba: per adapter instance 9981 * 9982 * This function basically turns on the regulators, clocks and 9983 * irqs of the hba. 9984 * 9985 * Return: 0 for success and non-zero for failure. 9986 */ 9987 static int ufshcd_resume(struct ufs_hba *hba) 9988 { 9989 int ret; 9990 9991 if (!hba->is_powered) 9992 return 0; 9993 9994 ufshcd_hba_vreg_set_hpm(hba); 9995 ret = ufshcd_vreg_set_hpm(hba); 9996 if (ret) 9997 goto out; 9998 9999 /* Make sure clocks are enabled before accessing controller */ 10000 ret = ufshcd_setup_clocks(hba, true); 10001 if (ret) 10002 goto disable_vreg; 10003 10004 /* enable the host irq as host controller would be active soon */ 10005 ufshcd_enable_irq(hba); 10006 10007 goto out; 10008 10009 disable_vreg: 10010 ufshcd_vreg_set_lpm(hba); 10011 out: 10012 if (ret) 10013 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 10014 return ret; 10015 } 10016 #endif /* CONFIG_PM */ 10017 10018 #ifdef CONFIG_PM_SLEEP 10019 /** 10020 * ufshcd_system_suspend - system suspend callback 10021 * @dev: Device associated with the UFS controller. 10022 * 10023 * Executed before putting the system into a sleep state in which the contents 10024 * of main memory are preserved. 10025 * 10026 * Return: 0 for success and non-zero for failure. 10027 */ 10028 int ufshcd_system_suspend(struct device *dev) 10029 { 10030 struct ufs_hba *hba = dev_get_drvdata(dev); 10031 int ret = 0; 10032 ktime_t start = ktime_get(); 10033 10034 if (pm_runtime_suspended(hba->dev)) 10035 goto out; 10036 10037 ret = ufshcd_suspend(hba); 10038 out: 10039 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 10040 ktime_to_us(ktime_sub(ktime_get(), start)), 10041 hba->curr_dev_pwr_mode, hba->uic_link_state); 10042 return ret; 10043 } 10044 EXPORT_SYMBOL(ufshcd_system_suspend); 10045 10046 /** 10047 * ufshcd_system_resume - system resume callback 10048 * @dev: Device associated with the UFS controller. 10049 * 10050 * Executed after waking the system up from a sleep state in which the contents 10051 * of main memory were preserved. 10052 * 10053 * Return: 0 for success and non-zero for failure. 10054 */ 10055 int ufshcd_system_resume(struct device *dev) 10056 { 10057 struct ufs_hba *hba = dev_get_drvdata(dev); 10058 ktime_t start = ktime_get(); 10059 int ret = 0; 10060 10061 if (pm_runtime_suspended(hba->dev)) 10062 goto out; 10063 10064 ret = ufshcd_resume(hba); 10065 10066 out: 10067 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10068 ktime_to_us(ktime_sub(ktime_get(), start)), 10069 hba->curr_dev_pwr_mode, hba->uic_link_state); 10070 10071 return ret; 10072 } 10073 EXPORT_SYMBOL(ufshcd_system_resume); 10074 #endif /* CONFIG_PM_SLEEP */ 10075 10076 #ifdef CONFIG_PM 10077 /** 10078 * ufshcd_runtime_suspend - runtime suspend callback 10079 * @dev: Device associated with the UFS controller. 10080 * 10081 * Check the description of ufshcd_suspend() function for more details. 10082 * 10083 * Return: 0 for success and non-zero for failure. 10084 */ 10085 int ufshcd_runtime_suspend(struct device *dev) 10086 { 10087 struct ufs_hba *hba = dev_get_drvdata(dev); 10088 int ret; 10089 ktime_t start = ktime_get(); 10090 10091 ret = ufshcd_suspend(hba); 10092 10093 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10094 ktime_to_us(ktime_sub(ktime_get(), start)), 10095 hba->curr_dev_pwr_mode, hba->uic_link_state); 10096 return ret; 10097 } 10098 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10099 10100 /** 10101 * ufshcd_runtime_resume - runtime resume routine 10102 * @dev: Device associated with the UFS controller. 10103 * 10104 * This function basically brings controller 10105 * to active state. Following operations are done in this function: 10106 * 10107 * 1. Turn on all the controller related clocks 10108 * 2. Turn ON VCC rail 10109 * 10110 * Return: 0 upon success; < 0 upon failure. 10111 */ 10112 int ufshcd_runtime_resume(struct device *dev) 10113 { 10114 struct ufs_hba *hba = dev_get_drvdata(dev); 10115 int ret; 10116 ktime_t start = ktime_get(); 10117 10118 ret = ufshcd_resume(hba); 10119 10120 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10121 ktime_to_us(ktime_sub(ktime_get(), start)), 10122 hba->curr_dev_pwr_mode, hba->uic_link_state); 10123 return ret; 10124 } 10125 EXPORT_SYMBOL(ufshcd_runtime_resume); 10126 #endif /* CONFIG_PM */ 10127 10128 static void ufshcd_wl_shutdown(struct device *dev) 10129 { 10130 struct scsi_device *sdev = to_scsi_device(dev); 10131 struct ufs_hba *hba = shost_priv(sdev->host); 10132 10133 down(&hba->host_sem); 10134 hba->shutting_down = true; 10135 up(&hba->host_sem); 10136 10137 /* Turn on everything while shutting down */ 10138 ufshcd_rpm_get_sync(hba); 10139 scsi_device_quiesce(sdev); 10140 shost_for_each_device(sdev, hba->host) { 10141 if (sdev == hba->ufs_device_wlun) 10142 continue; 10143 scsi_device_quiesce(sdev); 10144 } 10145 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10146 10147 /* 10148 * Next, turn off the UFS controller and the UFS regulators. Disable 10149 * clocks. 10150 */ 10151 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10152 ufshcd_suspend(hba); 10153 10154 hba->is_powered = false; 10155 } 10156 10157 /** 10158 * ufshcd_remove - de-allocate SCSI host and host memory space 10159 * data structure memory 10160 * @hba: per adapter instance 10161 */ 10162 void ufshcd_remove(struct ufs_hba *hba) 10163 { 10164 if (hba->ufs_device_wlun) 10165 ufshcd_rpm_get_sync(hba); 10166 ufs_hwmon_remove(hba); 10167 ufs_bsg_remove(hba); 10168 ufs_sysfs_remove_nodes(hba->dev); 10169 blk_mq_destroy_queue(hba->tmf_queue); 10170 blk_put_queue(hba->tmf_queue); 10171 blk_mq_free_tag_set(&hba->tmf_tag_set); 10172 scsi_remove_host(hba->host); 10173 /* disable interrupts */ 10174 ufshcd_disable_intr(hba, hba->intr_mask); 10175 ufshcd_hba_stop(hba); 10176 ufshcd_hba_exit(hba); 10177 } 10178 EXPORT_SYMBOL_GPL(ufshcd_remove); 10179 10180 #ifdef CONFIG_PM_SLEEP 10181 int ufshcd_system_freeze(struct device *dev) 10182 { 10183 10184 return ufshcd_system_suspend(dev); 10185 10186 } 10187 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10188 10189 int ufshcd_system_restore(struct device *dev) 10190 { 10191 10192 struct ufs_hba *hba = dev_get_drvdata(dev); 10193 int ret; 10194 10195 ret = ufshcd_system_resume(dev); 10196 if (ret) 10197 return ret; 10198 10199 /* Configure UTRL and UTMRL base address registers */ 10200 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10201 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10202 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10203 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10204 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10205 REG_UTP_TASK_REQ_LIST_BASE_L); 10206 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10207 REG_UTP_TASK_REQ_LIST_BASE_H); 10208 /* 10209 * Make sure that UTRL and UTMRL base address registers 10210 * are updated with the latest queue addresses. Only after 10211 * updating these addresses, we can queue the new commands. 10212 */ 10213 ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H); 10214 10215 /* Resuming from hibernate, assume that link was OFF */ 10216 ufshcd_set_link_off(hba); 10217 10218 return 0; 10219 10220 } 10221 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10222 10223 int ufshcd_system_thaw(struct device *dev) 10224 { 10225 return ufshcd_system_resume(dev); 10226 } 10227 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10228 #endif /* CONFIG_PM_SLEEP */ 10229 10230 /** 10231 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10232 * @hba: pointer to Host Bus Adapter (HBA) 10233 */ 10234 void ufshcd_dealloc_host(struct ufs_hba *hba) 10235 { 10236 scsi_host_put(hba->host); 10237 } 10238 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10239 10240 /** 10241 * ufshcd_set_dma_mask - Set dma mask based on the controller 10242 * addressing capability 10243 * @hba: per adapter instance 10244 * 10245 * Return: 0 for success, non-zero for failure. 10246 */ 10247 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10248 { 10249 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10250 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10251 return 0; 10252 } 10253 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10254 } 10255 10256 /** 10257 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10258 * @dev: pointer to device handle 10259 * @hba_handle: driver private handle 10260 * 10261 * Return: 0 on success, non-zero value on failure. 10262 */ 10263 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10264 { 10265 struct Scsi_Host *host; 10266 struct ufs_hba *hba; 10267 int err = 0; 10268 10269 if (!dev) { 10270 dev_err(dev, 10271 "Invalid memory reference for dev is NULL\n"); 10272 err = -ENODEV; 10273 goto out_error; 10274 } 10275 10276 host = scsi_host_alloc(&ufshcd_driver_template, 10277 sizeof(struct ufs_hba)); 10278 if (!host) { 10279 dev_err(dev, "scsi_host_alloc failed\n"); 10280 err = -ENOMEM; 10281 goto out_error; 10282 } 10283 host->nr_maps = HCTX_TYPE_POLL + 1; 10284 hba = shost_priv(host); 10285 hba->host = host; 10286 hba->dev = dev; 10287 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10288 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10289 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10290 INIT_LIST_HEAD(&hba->clk_list_head); 10291 spin_lock_init(&hba->outstanding_lock); 10292 10293 *hba_handle = hba; 10294 10295 out_error: 10296 return err; 10297 } 10298 EXPORT_SYMBOL(ufshcd_alloc_host); 10299 10300 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10301 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10302 const struct blk_mq_queue_data *qd) 10303 { 10304 WARN_ON_ONCE(true); 10305 return BLK_STS_NOTSUPP; 10306 } 10307 10308 static const struct blk_mq_ops ufshcd_tmf_ops = { 10309 .queue_rq = ufshcd_queue_tmf, 10310 }; 10311 10312 /** 10313 * ufshcd_init - Driver initialization routine 10314 * @hba: per-adapter instance 10315 * @mmio_base: base register address 10316 * @irq: Interrupt line of device 10317 * 10318 * Return: 0 on success, non-zero value on failure. 10319 */ 10320 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10321 { 10322 int err; 10323 struct Scsi_Host *host = hba->host; 10324 struct device *dev = hba->dev; 10325 char eh_wq_name[sizeof("ufs_eh_wq_00")]; 10326 10327 /* 10328 * dev_set_drvdata() must be called before any callbacks are registered 10329 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10330 * sysfs). 10331 */ 10332 dev_set_drvdata(dev, hba); 10333 10334 if (!mmio_base) { 10335 dev_err(hba->dev, 10336 "Invalid memory reference for mmio_base is NULL\n"); 10337 err = -ENODEV; 10338 goto out_error; 10339 } 10340 10341 hba->mmio_base = mmio_base; 10342 hba->irq = irq; 10343 hba->vps = &ufs_hba_vps; 10344 10345 err = ufshcd_hba_init(hba); 10346 if (err) 10347 goto out_error; 10348 10349 /* Read capabilities registers */ 10350 err = ufshcd_hba_capabilities(hba); 10351 if (err) 10352 goto out_disable; 10353 10354 /* Get UFS version supported by the controller */ 10355 hba->ufs_version = ufshcd_get_ufs_version(hba); 10356 10357 /* Get Interrupt bit mask per version */ 10358 hba->intr_mask = ufshcd_get_intr_mask(hba); 10359 10360 err = ufshcd_set_dma_mask(hba); 10361 if (err) { 10362 dev_err(hba->dev, "set dma mask failed\n"); 10363 goto out_disable; 10364 } 10365 10366 /* Allocate memory for host memory space */ 10367 err = ufshcd_memory_alloc(hba); 10368 if (err) { 10369 dev_err(hba->dev, "Memory allocation failed\n"); 10370 goto out_disable; 10371 } 10372 10373 /* Configure LRB */ 10374 ufshcd_host_memory_configure(hba); 10375 10376 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10377 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10378 host->max_id = UFSHCD_MAX_ID; 10379 host->max_lun = UFS_MAX_LUNS; 10380 host->max_channel = UFSHCD_MAX_CHANNEL; 10381 host->unique_id = host->host_no; 10382 host->max_cmd_len = UFS_CDB_SIZE; 10383 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10384 10385 /* Use default RPM delay if host not set */ 10386 if (host->rpm_autosuspend_delay == 0) 10387 host->rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS; 10388 10389 hba->max_pwr_info.is_valid = false; 10390 10391 /* Initialize work queues */ 10392 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d", 10393 hba->host->host_no); 10394 hba->eh_wq = create_singlethread_workqueue(eh_wq_name); 10395 if (!hba->eh_wq) { 10396 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10397 __func__); 10398 err = -ENOMEM; 10399 goto out_disable; 10400 } 10401 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10402 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10403 10404 sema_init(&hba->host_sem, 1); 10405 10406 /* Initialize UIC command mutex */ 10407 mutex_init(&hba->uic_cmd_mutex); 10408 10409 /* Initialize mutex for device management commands */ 10410 mutex_init(&hba->dev_cmd.lock); 10411 10412 /* Initialize mutex for exception event control */ 10413 mutex_init(&hba->ee_ctrl_mutex); 10414 10415 mutex_init(&hba->wb_mutex); 10416 init_rwsem(&hba->clk_scaling_lock); 10417 10418 ufshcd_init_clk_gating(hba); 10419 10420 ufshcd_init_clk_scaling(hba); 10421 10422 /* 10423 * In order to avoid any spurious interrupt immediately after 10424 * registering UFS controller interrupt handler, clear any pending UFS 10425 * interrupt status and disable all the UFS interrupts. 10426 */ 10427 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10428 REG_INTERRUPT_STATUS); 10429 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10430 /* 10431 * Make sure that UFS interrupts are disabled and any pending interrupt 10432 * status is cleared before registering UFS interrupt handler. 10433 */ 10434 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 10435 10436 /* IRQ registration */ 10437 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10438 if (err) { 10439 dev_err(hba->dev, "request irq failed\n"); 10440 goto out_disable; 10441 } else { 10442 hba->is_irq_enabled = true; 10443 } 10444 10445 if (!is_mcq_supported(hba)) { 10446 err = scsi_add_host(host, hba->dev); 10447 if (err) { 10448 dev_err(hba->dev, "scsi_add_host failed\n"); 10449 goto out_disable; 10450 } 10451 } 10452 10453 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10454 .nr_hw_queues = 1, 10455 .queue_depth = hba->nutmrs, 10456 .ops = &ufshcd_tmf_ops, 10457 .flags = BLK_MQ_F_NO_SCHED, 10458 }; 10459 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10460 if (err < 0) 10461 goto out_remove_scsi_host; 10462 hba->tmf_queue = blk_mq_alloc_queue(&hba->tmf_tag_set, NULL, NULL); 10463 if (IS_ERR(hba->tmf_queue)) { 10464 err = PTR_ERR(hba->tmf_queue); 10465 goto free_tmf_tag_set; 10466 } 10467 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10468 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10469 if (!hba->tmf_rqs) { 10470 err = -ENOMEM; 10471 goto free_tmf_queue; 10472 } 10473 10474 /* Reset the attached device */ 10475 ufshcd_device_reset(hba); 10476 10477 ufshcd_init_crypto(hba); 10478 10479 /* Host controller enable */ 10480 err = ufshcd_hba_enable(hba); 10481 if (err) { 10482 dev_err(hba->dev, "Host controller enable failed\n"); 10483 ufshcd_print_evt_hist(hba); 10484 ufshcd_print_host_state(hba); 10485 goto free_tmf_queue; 10486 } 10487 10488 /* 10489 * Set the default power management level for runtime and system PM. 10490 * Default power saving mode is to keep UFS link in Hibern8 state 10491 * and UFS device in sleep state. 10492 */ 10493 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10494 UFS_SLEEP_PWR_MODE, 10495 UIC_LINK_HIBERN8_STATE); 10496 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10497 UFS_SLEEP_PWR_MODE, 10498 UIC_LINK_HIBERN8_STATE); 10499 10500 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, ufshcd_rpm_dev_flush_recheck_work); 10501 INIT_DELAYED_WORK(&hba->ufs_rtc_update_work, ufshcd_rtc_work); 10502 10503 /* Set the default auto-hiberate idle timer value to 150 ms */ 10504 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10505 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10506 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10507 } 10508 10509 /* Hold auto suspend until async scan completes */ 10510 pm_runtime_get_sync(dev); 10511 atomic_set(&hba->scsi_block_reqs_cnt, 0); 10512 /* 10513 * We are assuming that device wasn't put in sleep/power-down 10514 * state exclusively during the boot stage before kernel. 10515 * This assumption helps avoid doing link startup twice during 10516 * ufshcd_probe_hba(). 10517 */ 10518 ufshcd_set_ufs_dev_active(hba); 10519 10520 async_schedule(ufshcd_async_scan, hba); 10521 ufs_sysfs_add_nodes(hba->dev); 10522 10523 device_enable_async_suspend(dev); 10524 ufshcd_pm_qos_init(hba); 10525 return 0; 10526 10527 free_tmf_queue: 10528 blk_mq_destroy_queue(hba->tmf_queue); 10529 blk_put_queue(hba->tmf_queue); 10530 free_tmf_tag_set: 10531 blk_mq_free_tag_set(&hba->tmf_tag_set); 10532 out_remove_scsi_host: 10533 scsi_remove_host(hba->host); 10534 out_disable: 10535 hba->is_irq_enabled = false; 10536 ufshcd_hba_exit(hba); 10537 out_error: 10538 return err; 10539 } 10540 EXPORT_SYMBOL_GPL(ufshcd_init); 10541 10542 void ufshcd_resume_complete(struct device *dev) 10543 { 10544 struct ufs_hba *hba = dev_get_drvdata(dev); 10545 10546 if (hba->complete_put) { 10547 ufshcd_rpm_put(hba); 10548 hba->complete_put = false; 10549 } 10550 } 10551 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10552 10553 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10554 { 10555 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10556 enum ufs_dev_pwr_mode dev_pwr_mode; 10557 enum uic_link_state link_state; 10558 unsigned long flags; 10559 bool res; 10560 10561 spin_lock_irqsave(&dev->power.lock, flags); 10562 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10563 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10564 res = pm_runtime_suspended(dev) && 10565 hba->curr_dev_pwr_mode == dev_pwr_mode && 10566 hba->uic_link_state == link_state && 10567 !hba->dev_info.b_rpm_dev_flush_capable; 10568 spin_unlock_irqrestore(&dev->power.lock, flags); 10569 10570 return res; 10571 } 10572 10573 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10574 { 10575 struct ufs_hba *hba = dev_get_drvdata(dev); 10576 int ret; 10577 10578 /* 10579 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10580 * are same. And it doesn't wake up the device for system-suspend 10581 * if it's runtime suspended. But ufs doesn't follow that. 10582 * Refer ufshcd_resume_complete() 10583 */ 10584 if (hba->ufs_device_wlun) { 10585 /* Prevent runtime suspend */ 10586 ufshcd_rpm_get_noresume(hba); 10587 /* 10588 * Check if already runtime suspended in same state as system 10589 * suspend would be. 10590 */ 10591 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10592 /* RPM state is not ok for SPM, so runtime resume */ 10593 ret = ufshcd_rpm_resume(hba); 10594 if (ret < 0 && ret != -EACCES) { 10595 ufshcd_rpm_put(hba); 10596 return ret; 10597 } 10598 } 10599 hba->complete_put = true; 10600 } 10601 return 0; 10602 } 10603 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10604 10605 int ufshcd_suspend_prepare(struct device *dev) 10606 { 10607 return __ufshcd_suspend_prepare(dev, true); 10608 } 10609 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10610 10611 #ifdef CONFIG_PM_SLEEP 10612 static int ufshcd_wl_poweroff(struct device *dev) 10613 { 10614 struct scsi_device *sdev = to_scsi_device(dev); 10615 struct ufs_hba *hba = shost_priv(sdev->host); 10616 10617 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10618 return 0; 10619 } 10620 #endif 10621 10622 static int ufshcd_wl_probe(struct device *dev) 10623 { 10624 struct scsi_device *sdev = to_scsi_device(dev); 10625 10626 if (!is_device_wlun(sdev)) 10627 return -ENODEV; 10628 10629 blk_pm_runtime_init(sdev->request_queue, dev); 10630 pm_runtime_set_autosuspend_delay(dev, 0); 10631 pm_runtime_allow(dev); 10632 10633 return 0; 10634 } 10635 10636 static int ufshcd_wl_remove(struct device *dev) 10637 { 10638 pm_runtime_forbid(dev); 10639 return 0; 10640 } 10641 10642 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10643 #ifdef CONFIG_PM_SLEEP 10644 .suspend = ufshcd_wl_suspend, 10645 .resume = ufshcd_wl_resume, 10646 .freeze = ufshcd_wl_suspend, 10647 .thaw = ufshcd_wl_resume, 10648 .poweroff = ufshcd_wl_poweroff, 10649 .restore = ufshcd_wl_resume, 10650 #endif 10651 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10652 }; 10653 10654 static void ufshcd_check_header_layout(void) 10655 { 10656 /* 10657 * gcc compilers before version 10 cannot do constant-folding for 10658 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10659 * before. 10660 */ 10661 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10662 return; 10663 10664 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10665 .cci = 3})[0] != 3); 10666 10667 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10668 .ehs_length = 2})[1] != 2); 10669 10670 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10671 .enable_crypto = 1})[2] 10672 != 0x80); 10673 10674 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10675 .command_type = 5, 10676 .data_direction = 3, 10677 .interrupt = 1, 10678 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10679 10680 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10681 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10682 cpu_to_le32(0xdeadbeef)); 10683 10684 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10685 .ocs = 4})[8] != 4); 10686 10687 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10688 .cds = 5})[9] != 5); 10689 10690 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10691 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10692 cpu_to_le32(0xbadcafe)); 10693 10694 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10695 .iid = 0xf })[4] != 0xf0); 10696 10697 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10698 .command_set_type = 0xf })[4] != 0xf); 10699 } 10700 10701 /* 10702 * ufs_dev_wlun_template - describes ufs device wlun 10703 * ufs-device wlun - used to send pm commands 10704 * All luns are consumers of ufs-device wlun. 10705 * 10706 * Currently, no sd driver is present for wluns. 10707 * Hence the no specific pm operations are performed. 10708 * With ufs design, SSU should be sent to ufs-device wlun. 10709 * Hence register a scsi driver for ufs wluns only. 10710 */ 10711 static struct scsi_driver ufs_dev_wlun_template = { 10712 .gendrv = { 10713 .name = "ufs_device_wlun", 10714 .probe = ufshcd_wl_probe, 10715 .remove = ufshcd_wl_remove, 10716 .pm = &ufshcd_wl_pm_ops, 10717 .shutdown = ufshcd_wl_shutdown, 10718 }, 10719 }; 10720 10721 static int __init ufshcd_core_init(void) 10722 { 10723 int ret; 10724 10725 ufshcd_check_header_layout(); 10726 10727 ufs_debugfs_init(); 10728 10729 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10730 if (ret) 10731 ufs_debugfs_exit(); 10732 return ret; 10733 } 10734 10735 static void __exit ufshcd_core_exit(void) 10736 { 10737 ufs_debugfs_exit(); 10738 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10739 } 10740 10741 module_init(ufshcd_core_init); 10742 module_exit(ufshcd_core_exit); 10743 10744 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10745 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10746 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10747 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10748 MODULE_LICENSE("GPL"); 10749