1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/pm_opp.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/sched/clock.h> 26 #include <linux/iopoll.h> 27 #include <scsi/scsi_cmnd.h> 28 #include <scsi/scsi_dbg.h> 29 #include <scsi/scsi_driver.h> 30 #include <scsi/scsi_eh.h> 31 #include "ufshcd-priv.h" 32 #include <ufs/ufs_quirks.h> 33 #include <ufs/unipro.h> 34 #include "ufs-sysfs.h" 35 #include "ufs-debugfs.h" 36 #include "ufs-fault-injection.h" 37 #include "ufs_bsg.h" 38 #include "ufshcd-crypto.h" 39 #include <asm/unaligned.h> 40 41 #define CREATE_TRACE_POINTS 42 #include <trace/events/ufs.h> 43 44 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 45 UTP_TASK_REQ_COMPL |\ 46 UFSHCD_ERROR_MASK) 47 48 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 49 UFSHCD_ERROR_MASK |\ 50 MCQ_CQ_EVENT_STATUS) 51 52 53 /* UIC command timeout, unit: ms */ 54 #define UIC_CMD_TIMEOUT 500 55 56 /* NOP OUT retries waiting for NOP IN response */ 57 #define NOP_OUT_RETRIES 10 58 /* Timeout after 50 msecs if NOP OUT hangs without response */ 59 #define NOP_OUT_TIMEOUT 50 /* msecs */ 60 61 /* Query request retries */ 62 #define QUERY_REQ_RETRIES 3 63 /* Query request timeout */ 64 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 65 66 /* Advanced RPMB request timeout */ 67 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 68 69 /* Task management command timeout */ 70 #define TM_CMD_TIMEOUT 100 /* msecs */ 71 72 /* maximum number of retries for a general UIC command */ 73 #define UFS_UIC_COMMAND_RETRIES 3 74 75 /* maximum number of link-startup retries */ 76 #define DME_LINKSTARTUP_RETRIES 3 77 78 /* maximum number of reset retries before giving up */ 79 #define MAX_HOST_RESET_RETRIES 5 80 81 /* Maximum number of error handler retries before giving up */ 82 #define MAX_ERR_HANDLER_RETRIES 5 83 84 /* Expose the flag value from utp_upiu_query.value */ 85 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 86 87 /* Interrupt aggregation default timeout, unit: 40us */ 88 #define INT_AGGR_DEF_TO 0x02 89 90 /* default delay of autosuspend: 2000 ms */ 91 #define RPM_AUTOSUSPEND_DELAY_MS 2000 92 93 /* Default delay of RPM device flush delayed work */ 94 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 95 96 /* Default value of wait time before gating device ref clock */ 97 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 98 99 /* Polling time to wait for fDeviceInit */ 100 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 101 102 /* Default RTC update every 10 seconds */ 103 #define UFS_RTC_UPDATE_INTERVAL_MS (10 * MSEC_PER_SEC) 104 105 /* bMaxNumOfRTT is equal to two after device manufacturing */ 106 #define DEFAULT_MAX_NUM_RTT 2 107 108 /* UFSHC 4.0 compliant HC support this mode. */ 109 static bool use_mcq_mode = true; 110 111 static bool is_mcq_supported(struct ufs_hba *hba) 112 { 113 return hba->mcq_sup && use_mcq_mode; 114 } 115 116 module_param(use_mcq_mode, bool, 0644); 117 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 118 119 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 120 ({ \ 121 int _ret; \ 122 if (_on) \ 123 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 124 else \ 125 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 126 _ret; \ 127 }) 128 129 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 130 size_t __len = (len); \ 131 print_hex_dump(KERN_ERR, prefix_str, \ 132 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 133 16, 4, buf, __len, false); \ 134 } while (0) 135 136 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 137 const char *prefix) 138 { 139 u32 *regs; 140 size_t pos; 141 142 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 143 return -EINVAL; 144 145 regs = kzalloc(len, GFP_ATOMIC); 146 if (!regs) 147 return -ENOMEM; 148 149 for (pos = 0; pos < len; pos += 4) { 150 if (offset == 0 && 151 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 152 pos <= REG_UIC_ERROR_CODE_DME) 153 continue; 154 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 155 } 156 157 ufshcd_hex_dump(prefix, regs, len); 158 kfree(regs); 159 160 return 0; 161 } 162 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 163 164 enum { 165 UFSHCD_MAX_CHANNEL = 0, 166 UFSHCD_MAX_ID = 1, 167 }; 168 169 static const char *const ufshcd_state_name[] = { 170 [UFSHCD_STATE_RESET] = "reset", 171 [UFSHCD_STATE_OPERATIONAL] = "operational", 172 [UFSHCD_STATE_ERROR] = "error", 173 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 174 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 175 }; 176 177 /* UFSHCD error handling flags */ 178 enum { 179 UFSHCD_EH_IN_PROGRESS = (1 << 0), 180 }; 181 182 /* UFSHCD UIC layer error flags */ 183 enum { 184 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 185 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 186 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 187 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 188 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 189 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 190 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 191 }; 192 193 #define ufshcd_set_eh_in_progress(h) \ 194 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 195 #define ufshcd_eh_in_progress(h) \ 196 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 197 #define ufshcd_clear_eh_in_progress(h) \ 198 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 199 200 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 201 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 202 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 203 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 204 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 205 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 206 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 207 /* 208 * For DeepSleep, the link is first put in hibern8 and then off. 209 * Leaving the link in hibern8 is not supported. 210 */ 211 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 212 }; 213 214 static inline enum ufs_dev_pwr_mode 215 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 216 { 217 return ufs_pm_lvl_states[lvl].dev_state; 218 } 219 220 static inline enum uic_link_state 221 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 222 { 223 return ufs_pm_lvl_states[lvl].link_state; 224 } 225 226 static inline enum ufs_pm_level 227 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 228 enum uic_link_state link_state) 229 { 230 enum ufs_pm_level lvl; 231 232 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 233 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 234 (ufs_pm_lvl_states[lvl].link_state == link_state)) 235 return lvl; 236 } 237 238 /* if no match found, return the level 0 */ 239 return UFS_PM_LVL_0; 240 } 241 242 static bool ufshcd_is_ufs_dev_busy(struct ufs_hba *hba) 243 { 244 return (hba->clk_gating.active_reqs || hba->outstanding_reqs || hba->outstanding_tasks || 245 hba->active_uic_cmd || hba->uic_async_done); 246 } 247 248 static const struct ufs_dev_quirk ufs_fixups[] = { 249 /* UFS cards deviations table */ 250 { .wmanufacturerid = UFS_VENDOR_MICRON, 251 .model = UFS_ANY_MODEL, 252 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 253 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 254 .model = UFS_ANY_MODEL, 255 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 256 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 257 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 258 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 259 .model = UFS_ANY_MODEL, 260 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 261 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 262 .model = "hB8aL1" /*H28U62301AMR*/, 263 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 264 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 265 .model = UFS_ANY_MODEL, 266 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 267 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 268 .model = "THGLF2G9C8KBADG", 269 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 270 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 271 .model = "THGLF2G9D8KBADG", 272 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 273 {} 274 }; 275 276 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 277 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 278 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 279 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 280 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 281 static void ufshcd_hba_exit(struct ufs_hba *hba); 282 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 283 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 284 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 285 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 286 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 287 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 288 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 289 bool scale_up); 290 static irqreturn_t ufshcd_intr(int irq, void *__hba); 291 static int ufshcd_change_power_mode(struct ufs_hba *hba, 292 struct ufs_pa_layer_attr *pwr_mode); 293 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 294 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 295 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 296 struct ufs_vreg *vreg); 297 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 298 bool enable); 299 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 300 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 301 302 void ufshcd_enable_irq(struct ufs_hba *hba) 303 { 304 if (!hba->is_irq_enabled) { 305 enable_irq(hba->irq); 306 hba->is_irq_enabled = true; 307 } 308 } 309 EXPORT_SYMBOL_GPL(ufshcd_enable_irq); 310 311 void ufshcd_disable_irq(struct ufs_hba *hba) 312 { 313 if (hba->is_irq_enabled) { 314 disable_irq(hba->irq); 315 hba->is_irq_enabled = false; 316 } 317 } 318 EXPORT_SYMBOL_GPL(ufshcd_disable_irq); 319 320 static void ufshcd_configure_wb(struct ufs_hba *hba) 321 { 322 if (!ufshcd_is_wb_allowed(hba)) 323 return; 324 325 ufshcd_wb_toggle(hba, true); 326 327 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 328 329 if (ufshcd_is_wb_buf_flush_allowed(hba)) 330 ufshcd_wb_toggle_buf_flush(hba, true); 331 } 332 333 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba) 334 { 335 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt)) 336 scsi_unblock_requests(hba->host); 337 } 338 339 static void ufshcd_scsi_block_requests(struct ufs_hba *hba) 340 { 341 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1) 342 scsi_block_requests(hba->host); 343 } 344 345 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 346 enum ufs_trace_str_t str_t) 347 { 348 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 349 struct utp_upiu_header *header; 350 351 if (!trace_ufshcd_upiu_enabled()) 352 return; 353 354 if (str_t == UFS_CMD_SEND) 355 header = &rq->header; 356 else 357 header = &hba->lrb[tag].ucd_rsp_ptr->header; 358 359 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 360 UFS_TSF_CDB); 361 } 362 363 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 364 enum ufs_trace_str_t str_t, 365 struct utp_upiu_req *rq_rsp) 366 { 367 if (!trace_ufshcd_upiu_enabled()) 368 return; 369 370 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 371 &rq_rsp->qr, UFS_TSF_OSF); 372 } 373 374 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 375 enum ufs_trace_str_t str_t) 376 { 377 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 378 379 if (!trace_ufshcd_upiu_enabled()) 380 return; 381 382 if (str_t == UFS_TM_SEND) 383 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 384 &descp->upiu_req.req_header, 385 &descp->upiu_req.input_param1, 386 UFS_TSF_TM_INPUT); 387 else 388 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 389 &descp->upiu_rsp.rsp_header, 390 &descp->upiu_rsp.output_param1, 391 UFS_TSF_TM_OUTPUT); 392 } 393 394 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 395 const struct uic_command *ucmd, 396 enum ufs_trace_str_t str_t) 397 { 398 u32 cmd; 399 400 if (!trace_ufshcd_uic_command_enabled()) 401 return; 402 403 if (str_t == UFS_CMD_SEND) 404 cmd = ucmd->command; 405 else 406 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 407 408 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 409 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 410 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 411 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 412 } 413 414 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 415 enum ufs_trace_str_t str_t) 416 { 417 u64 lba = 0; 418 u8 opcode = 0, group_id = 0; 419 u32 doorbell = 0; 420 u32 intr; 421 int hwq_id = -1; 422 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 423 struct scsi_cmnd *cmd = lrbp->cmd; 424 struct request *rq = scsi_cmd_to_rq(cmd); 425 int transfer_len = -1; 426 427 if (!cmd) 428 return; 429 430 /* trace UPIU also */ 431 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 432 if (!trace_ufshcd_command_enabled()) 433 return; 434 435 opcode = cmd->cmnd[0]; 436 437 if (opcode == READ_10 || opcode == WRITE_10) { 438 /* 439 * Currently we only fully trace read(10) and write(10) commands 440 */ 441 transfer_len = 442 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 443 lba = scsi_get_lba(cmd); 444 if (opcode == WRITE_10) 445 group_id = lrbp->cmd->cmnd[6]; 446 } else if (opcode == UNMAP) { 447 /* 448 * The number of Bytes to be unmapped beginning with the lba. 449 */ 450 transfer_len = blk_rq_bytes(rq); 451 lba = scsi_get_lba(cmd); 452 } 453 454 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 455 456 if (hba->mcq_enabled) { 457 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 458 459 hwq_id = hwq->id; 460 } else { 461 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 462 } 463 trace_ufshcd_command(cmd->device, str_t, tag, doorbell, hwq_id, 464 transfer_len, intr, lba, opcode, group_id); 465 } 466 467 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 468 { 469 struct ufs_clk_info *clki; 470 struct list_head *head = &hba->clk_list_head; 471 472 if (list_empty(head)) 473 return; 474 475 list_for_each_entry(clki, head, list) { 476 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 477 clki->max_freq) 478 dev_err(hba->dev, "clk: %s, rate: %u\n", 479 clki->name, clki->curr_freq); 480 } 481 } 482 483 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 484 const char *err_name) 485 { 486 int i; 487 bool found = false; 488 const struct ufs_event_hist *e; 489 490 if (id >= UFS_EVT_CNT) 491 return; 492 493 e = &hba->ufs_stats.event[id]; 494 495 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 496 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 497 498 if (e->tstamp[p] == 0) 499 continue; 500 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 501 e->val[p], div_u64(e->tstamp[p], 1000)); 502 found = true; 503 } 504 505 if (!found) 506 dev_err(hba->dev, "No record of %s\n", err_name); 507 else 508 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 509 } 510 511 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 512 { 513 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 514 515 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 516 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 517 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 518 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 519 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 520 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 521 "auto_hibern8_err"); 522 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 523 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 524 "link_startup_fail"); 525 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 526 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 527 "suspend_fail"); 528 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 529 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 530 "wlun suspend_fail"); 531 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 532 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 533 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 534 535 ufshcd_vops_dbg_register_dump(hba); 536 } 537 538 static 539 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 540 { 541 const struct ufshcd_lrb *lrbp; 542 int prdt_length; 543 544 lrbp = &hba->lrb[tag]; 545 546 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 547 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 548 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 549 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 550 dev_err(hba->dev, 551 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 552 tag, (u64)lrbp->utrd_dma_addr); 553 554 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 555 sizeof(struct utp_transfer_req_desc)); 556 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 557 (u64)lrbp->ucd_req_dma_addr); 558 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 559 sizeof(struct utp_upiu_req)); 560 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 561 (u64)lrbp->ucd_rsp_dma_addr); 562 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 563 sizeof(struct utp_upiu_rsp)); 564 565 prdt_length = le16_to_cpu( 566 lrbp->utr_descriptor_ptr->prd_table_length); 567 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 568 prdt_length /= ufshcd_sg_entry_size(hba); 569 570 dev_err(hba->dev, 571 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 572 tag, prdt_length, 573 (u64)lrbp->ucd_prdt_dma_addr); 574 575 if (pr_prdt) 576 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 577 ufshcd_sg_entry_size(hba) * prdt_length); 578 } 579 580 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 581 { 582 struct scsi_device *sdev = req->q->queuedata; 583 struct Scsi_Host *shost = sdev->host; 584 struct ufs_hba *hba = shost_priv(shost); 585 586 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 587 588 return true; 589 } 590 591 /** 592 * ufshcd_print_trs_all - print trs for all started requests. 593 * @hba: per-adapter instance. 594 * @pr_prdt: need to print prdt or not. 595 */ 596 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 597 { 598 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 599 } 600 601 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 602 { 603 int tag; 604 605 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 606 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 607 608 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 609 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 610 } 611 } 612 613 static void ufshcd_print_host_state(struct ufs_hba *hba) 614 { 615 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 616 617 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 618 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 619 hba->outstanding_reqs, hba->outstanding_tasks); 620 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 621 hba->saved_err, hba->saved_uic_err); 622 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 623 hba->curr_dev_pwr_mode, hba->uic_link_state); 624 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 625 hba->pm_op_in_progress, hba->is_sys_suspended); 626 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 627 hba->auto_bkops_enabled, hba->host->host_self_blocked); 628 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 629 dev_err(hba->dev, 630 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 631 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 632 hba->ufs_stats.hibern8_exit_cnt); 633 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 634 div_u64(hba->ufs_stats.last_intr_ts, 1000), 635 hba->ufs_stats.last_intr_status); 636 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 637 hba->eh_flags, hba->req_abort_count); 638 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 639 hba->ufs_version, hba->capabilities, hba->caps); 640 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 641 hba->dev_quirks); 642 if (sdev_ufs) 643 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 644 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 645 646 ufshcd_print_clk_freqs(hba); 647 } 648 649 /** 650 * ufshcd_print_pwr_info - print power params as saved in hba 651 * power info 652 * @hba: per-adapter instance 653 */ 654 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 655 { 656 static const char * const names[] = { 657 "INVALID MODE", 658 "FAST MODE", 659 "SLOW_MODE", 660 "INVALID MODE", 661 "FASTAUTO_MODE", 662 "SLOWAUTO_MODE", 663 "INVALID MODE", 664 }; 665 666 /* 667 * Using dev_dbg to avoid messages during runtime PM to avoid 668 * never-ending cycles of messages written back to storage by user space 669 * causing runtime resume, causing more messages and so on. 670 */ 671 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 672 __func__, 673 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 674 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 675 names[hba->pwr_info.pwr_rx], 676 names[hba->pwr_info.pwr_tx], 677 hba->pwr_info.hs_rate); 678 } 679 680 static void ufshcd_device_reset(struct ufs_hba *hba) 681 { 682 int err; 683 684 err = ufshcd_vops_device_reset(hba); 685 686 if (!err) { 687 ufshcd_set_ufs_dev_active(hba); 688 if (ufshcd_is_wb_allowed(hba)) { 689 hba->dev_info.wb_enabled = false; 690 hba->dev_info.wb_buf_flush_enabled = false; 691 } 692 if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 693 hba->dev_info.rtc_time_baseline = 0; 694 } 695 if (err != -EOPNOTSUPP) 696 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 697 } 698 699 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 700 { 701 if (!us) 702 return; 703 704 if (us < 10) 705 udelay(us); 706 else 707 usleep_range(us, us + tolerance); 708 } 709 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 710 711 /** 712 * ufshcd_wait_for_register - wait for register value to change 713 * @hba: per-adapter interface 714 * @reg: mmio register offset 715 * @mask: mask to apply to the read register value 716 * @val: value to wait for 717 * @interval_us: polling interval in microseconds 718 * @timeout_ms: timeout in milliseconds 719 * 720 * Return: -ETIMEDOUT on error, zero on success. 721 */ 722 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 723 u32 val, unsigned long interval_us, 724 unsigned long timeout_ms) 725 { 726 int err = 0; 727 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 728 729 /* ignore bits that we don't intend to wait on */ 730 val = val & mask; 731 732 while ((ufshcd_readl(hba, reg) & mask) != val) { 733 usleep_range(interval_us, interval_us + 50); 734 if (time_after(jiffies, timeout)) { 735 if ((ufshcd_readl(hba, reg) & mask) != val) 736 err = -ETIMEDOUT; 737 break; 738 } 739 } 740 741 return err; 742 } 743 744 /** 745 * ufshcd_get_intr_mask - Get the interrupt bit mask 746 * @hba: Pointer to adapter instance 747 * 748 * Return: interrupt bit mask per version 749 */ 750 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 751 { 752 if (hba->ufs_version <= ufshci_version(2, 0)) 753 return INTERRUPT_MASK_ALL_VER_11; 754 755 return INTERRUPT_MASK_ALL_VER_21; 756 } 757 758 /** 759 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 760 * @hba: Pointer to adapter instance 761 * 762 * Return: UFSHCI version supported by the controller 763 */ 764 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 765 { 766 u32 ufshci_ver; 767 768 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 769 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 770 else 771 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 772 773 /* 774 * UFSHCI v1.x uses a different version scheme, in order 775 * to allow the use of comparisons with the ufshci_version 776 * function, we convert it to the same scheme as ufs 2.0+. 777 */ 778 if (ufshci_ver & 0x00010000) 779 return ufshci_version(1, ufshci_ver & 0x00000100); 780 781 return ufshci_ver; 782 } 783 784 /** 785 * ufshcd_is_device_present - Check if any device connected to 786 * the host controller 787 * @hba: pointer to adapter instance 788 * 789 * Return: true if device present, false if no device detected 790 */ 791 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 792 { 793 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 794 } 795 796 /** 797 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 798 * @lrbp: pointer to local command reference block 799 * @cqe: pointer to the completion queue entry 800 * 801 * This function is used to get the OCS field from UTRD 802 * 803 * Return: the OCS field in the UTRD. 804 */ 805 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 806 struct cq_entry *cqe) 807 { 808 if (cqe) 809 return le32_to_cpu(cqe->status) & MASK_OCS; 810 811 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 812 } 813 814 /** 815 * ufshcd_utrl_clear() - Clear requests from the controller request list. 816 * @hba: per adapter instance 817 * @mask: mask with one bit set for each request to be cleared 818 */ 819 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 820 { 821 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 822 mask = ~mask; 823 /* 824 * From the UFSHCI specification: "UTP Transfer Request List CLear 825 * Register (UTRLCLR): This field is bit significant. Each bit 826 * corresponds to a slot in the UTP Transfer Request List, where bit 0 827 * corresponds to request slot 0. A bit in this field is set to ‘0’ 828 * by host software to indicate to the host controller that a transfer 829 * request slot is cleared. The host controller 830 * shall free up any resources associated to the request slot 831 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 832 * host software indicates no change to request slots by setting the 833 * associated bits in this field to ‘1’. Bits in this field shall only 834 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 835 */ 836 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 837 } 838 839 /** 840 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 841 * @hba: per adapter instance 842 * @pos: position of the bit to be cleared 843 */ 844 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 845 { 846 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 847 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 848 else 849 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 850 } 851 852 /** 853 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 854 * @reg: Register value of host controller status 855 * 856 * Return: 0 on success; a positive value if failed. 857 */ 858 static inline int ufshcd_get_lists_status(u32 reg) 859 { 860 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 861 } 862 863 /** 864 * ufshcd_get_uic_cmd_result - Get the UIC command result 865 * @hba: Pointer to adapter instance 866 * 867 * This function gets the result of UIC command completion 868 * 869 * Return: 0 on success; non-zero value on error. 870 */ 871 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 872 { 873 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 874 MASK_UIC_COMMAND_RESULT; 875 } 876 877 /** 878 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 879 * @hba: Pointer to adapter instance 880 * 881 * This function gets UIC command argument3 882 * 883 * Return: 0 on success; non-zero value on error. 884 */ 885 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 886 { 887 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 888 } 889 890 /** 891 * ufshcd_get_req_rsp - returns the TR response transaction type 892 * @ucd_rsp_ptr: pointer to response UPIU 893 * 894 * Return: UPIU type. 895 */ 896 static inline enum upiu_response_transaction 897 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 898 { 899 return ucd_rsp_ptr->header.transaction_code; 900 } 901 902 /** 903 * ufshcd_is_exception_event - Check if the device raised an exception event 904 * @ucd_rsp_ptr: pointer to response UPIU 905 * 906 * The function checks if the device raised an exception event indicated in 907 * the Device Information field of response UPIU. 908 * 909 * Return: true if exception is raised, false otherwise. 910 */ 911 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 912 { 913 return ucd_rsp_ptr->header.device_information & 1; 914 } 915 916 /** 917 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 918 * @hba: per adapter instance 919 */ 920 static inline void 921 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 922 { 923 ufshcd_writel(hba, INT_AGGR_ENABLE | 924 INT_AGGR_COUNTER_AND_TIMER_RESET, 925 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 926 } 927 928 /** 929 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 930 * @hba: per adapter instance 931 * @cnt: Interrupt aggregation counter threshold 932 * @tmout: Interrupt aggregation timeout value 933 */ 934 static inline void 935 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 936 { 937 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 938 INT_AGGR_COUNTER_THLD_VAL(cnt) | 939 INT_AGGR_TIMEOUT_VAL(tmout), 940 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 941 } 942 943 /** 944 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 945 * @hba: per adapter instance 946 */ 947 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 948 { 949 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 950 } 951 952 /** 953 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 954 * When run-stop registers are set to 1, it indicates the 955 * host controller that it can process the requests 956 * @hba: per adapter instance 957 */ 958 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 959 { 960 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 961 REG_UTP_TASK_REQ_LIST_RUN_STOP); 962 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 963 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 964 } 965 966 /** 967 * ufshcd_hba_start - Start controller initialization sequence 968 * @hba: per adapter instance 969 */ 970 static inline void ufshcd_hba_start(struct ufs_hba *hba) 971 { 972 u32 val = CONTROLLER_ENABLE; 973 974 if (ufshcd_crypto_enable(hba)) 975 val |= CRYPTO_GENERAL_ENABLE; 976 977 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 978 } 979 980 /** 981 * ufshcd_is_hba_active - Get controller state 982 * @hba: per adapter instance 983 * 984 * Return: true if and only if the controller is active. 985 */ 986 bool ufshcd_is_hba_active(struct ufs_hba *hba) 987 { 988 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 989 } 990 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 991 992 /** 993 * ufshcd_pm_qos_init - initialize PM QoS request 994 * @hba: per adapter instance 995 */ 996 void ufshcd_pm_qos_init(struct ufs_hba *hba) 997 { 998 999 if (hba->pm_qos_enabled) 1000 return; 1001 1002 cpu_latency_qos_add_request(&hba->pm_qos_req, PM_QOS_DEFAULT_VALUE); 1003 1004 if (cpu_latency_qos_request_active(&hba->pm_qos_req)) 1005 hba->pm_qos_enabled = true; 1006 } 1007 1008 /** 1009 * ufshcd_pm_qos_exit - remove request from PM QoS 1010 * @hba: per adapter instance 1011 */ 1012 void ufshcd_pm_qos_exit(struct ufs_hba *hba) 1013 { 1014 if (!hba->pm_qos_enabled) 1015 return; 1016 1017 cpu_latency_qos_remove_request(&hba->pm_qos_req); 1018 hba->pm_qos_enabled = false; 1019 } 1020 1021 /** 1022 * ufshcd_pm_qos_update - update PM QoS request 1023 * @hba: per adapter instance 1024 * @on: If True, vote for perf PM QoS mode otherwise power save mode 1025 */ 1026 static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) 1027 { 1028 if (!hba->pm_qos_enabled) 1029 return; 1030 1031 cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE); 1032 } 1033 1034 /** 1035 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1036 * @hba: per adapter instance 1037 * @scale_up: If True, set max possible frequency othewise set low frequency 1038 * 1039 * Return: 0 if successful; < 0 upon failure. 1040 */ 1041 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1042 { 1043 int ret = 0; 1044 struct ufs_clk_info *clki; 1045 struct list_head *head = &hba->clk_list_head; 1046 1047 if (list_empty(head)) 1048 goto out; 1049 1050 list_for_each_entry(clki, head, list) { 1051 if (!IS_ERR_OR_NULL(clki->clk)) { 1052 if (scale_up && clki->max_freq) { 1053 if (clki->curr_freq == clki->max_freq) 1054 continue; 1055 1056 ret = clk_set_rate(clki->clk, clki->max_freq); 1057 if (ret) { 1058 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1059 __func__, clki->name, 1060 clki->max_freq, ret); 1061 break; 1062 } 1063 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1064 "scaled up", clki->name, 1065 clki->curr_freq, 1066 clki->max_freq); 1067 1068 clki->curr_freq = clki->max_freq; 1069 1070 } else if (!scale_up && clki->min_freq) { 1071 if (clki->curr_freq == clki->min_freq) 1072 continue; 1073 1074 ret = clk_set_rate(clki->clk, clki->min_freq); 1075 if (ret) { 1076 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1077 __func__, clki->name, 1078 clki->min_freq, ret); 1079 break; 1080 } 1081 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1082 "scaled down", clki->name, 1083 clki->curr_freq, 1084 clki->min_freq); 1085 clki->curr_freq = clki->min_freq; 1086 } 1087 } 1088 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1089 clki->name, clk_get_rate(clki->clk)); 1090 } 1091 1092 out: 1093 return ret; 1094 } 1095 1096 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1097 struct dev_pm_opp *opp, void *data, 1098 bool scaling_down) 1099 { 1100 struct ufs_hba *hba = dev_get_drvdata(dev); 1101 struct list_head *head = &hba->clk_list_head; 1102 struct ufs_clk_info *clki; 1103 unsigned long freq; 1104 u8 idx = 0; 1105 int ret; 1106 1107 list_for_each_entry(clki, head, list) { 1108 if (!IS_ERR_OR_NULL(clki->clk)) { 1109 freq = dev_pm_opp_get_freq_indexed(opp, idx++); 1110 1111 /* Do not set rate for clocks having frequency as 0 */ 1112 if (!freq) 1113 continue; 1114 1115 ret = clk_set_rate(clki->clk, freq); 1116 if (ret) { 1117 dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n", 1118 __func__, clki->name, freq, ret); 1119 return ret; 1120 } 1121 1122 trace_ufshcd_clk_scaling(dev_name(dev), 1123 (scaling_down ? "scaled down" : "scaled up"), 1124 clki->name, hba->clk_scaling.target_freq, freq); 1125 } 1126 } 1127 1128 return 0; 1129 } 1130 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks); 1131 1132 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) 1133 { 1134 struct dev_pm_opp *opp; 1135 int ret; 1136 1137 opp = dev_pm_opp_find_freq_floor_indexed(hba->dev, 1138 &freq, 0); 1139 if (IS_ERR(opp)) 1140 return PTR_ERR(opp); 1141 1142 ret = dev_pm_opp_set_opp(hba->dev, opp); 1143 dev_pm_opp_put(opp); 1144 1145 return ret; 1146 } 1147 1148 /** 1149 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1150 * @hba: per adapter instance 1151 * @freq: frequency to scale 1152 * @scale_up: True if scaling up and false if scaling down 1153 * 1154 * Return: 0 if successful; < 0 upon failure. 1155 */ 1156 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 1157 bool scale_up) 1158 { 1159 int ret = 0; 1160 ktime_t start = ktime_get(); 1161 1162 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1163 if (ret) 1164 goto out; 1165 1166 if (hba->use_pm_opp) 1167 ret = ufshcd_opp_set_rate(hba, freq); 1168 else 1169 ret = ufshcd_set_clk_freq(hba, scale_up); 1170 if (ret) 1171 goto out; 1172 1173 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1174 if (ret) { 1175 if (hba->use_pm_opp) 1176 ufshcd_opp_set_rate(hba, 1177 hba->devfreq->previous_freq); 1178 else 1179 ufshcd_set_clk_freq(hba, !scale_up); 1180 goto out; 1181 } 1182 1183 ufshcd_pm_qos_update(hba, scale_up); 1184 1185 out: 1186 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1187 (scale_up ? "up" : "down"), 1188 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1189 return ret; 1190 } 1191 1192 /** 1193 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1194 * @hba: per adapter instance 1195 * @freq: frequency to scale 1196 * @scale_up: True if scaling up and false if scaling down 1197 * 1198 * Return: true if scaling is required, false otherwise. 1199 */ 1200 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1201 unsigned long freq, bool scale_up) 1202 { 1203 struct ufs_clk_info *clki; 1204 struct list_head *head = &hba->clk_list_head; 1205 1206 if (list_empty(head)) 1207 return false; 1208 1209 if (hba->use_pm_opp) 1210 return freq != hba->clk_scaling.target_freq; 1211 1212 list_for_each_entry(clki, head, list) { 1213 if (!IS_ERR_OR_NULL(clki->clk)) { 1214 if (scale_up && clki->max_freq) { 1215 if (clki->curr_freq == clki->max_freq) 1216 continue; 1217 return true; 1218 } else if (!scale_up && clki->min_freq) { 1219 if (clki->curr_freq == clki->min_freq) 1220 continue; 1221 return true; 1222 } 1223 } 1224 } 1225 1226 return false; 1227 } 1228 1229 /* 1230 * Determine the number of pending commands by counting the bits in the SCSI 1231 * device budget maps. This approach has been selected because a bit is set in 1232 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1233 * flag. The host_self_blocked flag can be modified by calling 1234 * scsi_block_requests() or scsi_unblock_requests(). 1235 */ 1236 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1237 { 1238 const struct scsi_device *sdev; 1239 u32 pending = 0; 1240 1241 lockdep_assert_held(hba->host->host_lock); 1242 __shost_for_each_device(sdev, hba->host) 1243 pending += sbitmap_weight(&sdev->budget_map); 1244 1245 return pending; 1246 } 1247 1248 /* 1249 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1250 * has expired. 1251 * 1252 * Return: 0 upon success; -EBUSY upon timeout. 1253 */ 1254 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1255 u64 wait_timeout_us) 1256 { 1257 unsigned long flags; 1258 int ret = 0; 1259 u32 tm_doorbell; 1260 u32 tr_pending; 1261 bool timeout = false, do_last_check = false; 1262 ktime_t start; 1263 1264 ufshcd_hold(hba); 1265 spin_lock_irqsave(hba->host->host_lock, flags); 1266 /* 1267 * Wait for all the outstanding tasks/transfer requests. 1268 * Verify by checking the doorbell registers are clear. 1269 */ 1270 start = ktime_get(); 1271 do { 1272 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1273 ret = -EBUSY; 1274 goto out; 1275 } 1276 1277 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1278 tr_pending = ufshcd_pending_cmds(hba); 1279 if (!tm_doorbell && !tr_pending) { 1280 timeout = false; 1281 break; 1282 } else if (do_last_check) { 1283 break; 1284 } 1285 1286 spin_unlock_irqrestore(hba->host->host_lock, flags); 1287 io_schedule_timeout(msecs_to_jiffies(20)); 1288 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1289 wait_timeout_us) { 1290 timeout = true; 1291 /* 1292 * We might have scheduled out for long time so make 1293 * sure to check if doorbells are cleared by this time 1294 * or not. 1295 */ 1296 do_last_check = true; 1297 } 1298 spin_lock_irqsave(hba->host->host_lock, flags); 1299 } while (tm_doorbell || tr_pending); 1300 1301 if (timeout) { 1302 dev_err(hba->dev, 1303 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1304 __func__, tm_doorbell, tr_pending); 1305 ret = -EBUSY; 1306 } 1307 out: 1308 spin_unlock_irqrestore(hba->host->host_lock, flags); 1309 ufshcd_release(hba); 1310 return ret; 1311 } 1312 1313 /** 1314 * ufshcd_scale_gear - scale up/down UFS gear 1315 * @hba: per adapter instance 1316 * @scale_up: True for scaling up gear and false for scaling down 1317 * 1318 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1319 * non-zero for any other errors. 1320 */ 1321 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1322 { 1323 int ret = 0; 1324 struct ufs_pa_layer_attr new_pwr_info; 1325 1326 if (scale_up) { 1327 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1328 sizeof(struct ufs_pa_layer_attr)); 1329 } else { 1330 memcpy(&new_pwr_info, &hba->pwr_info, 1331 sizeof(struct ufs_pa_layer_attr)); 1332 1333 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1334 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1335 /* save the current power mode */ 1336 memcpy(&hba->clk_scaling.saved_pwr_info, 1337 &hba->pwr_info, 1338 sizeof(struct ufs_pa_layer_attr)); 1339 1340 /* scale down gear */ 1341 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1342 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1343 } 1344 } 1345 1346 /* check if the power mode needs to be changed or not? */ 1347 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1348 if (ret) 1349 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1350 __func__, ret, 1351 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1352 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1353 1354 return ret; 1355 } 1356 1357 /* 1358 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1359 * has expired. 1360 * 1361 * Return: 0 upon success; -EBUSY upon timeout. 1362 */ 1363 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1364 { 1365 int ret = 0; 1366 /* 1367 * make sure that there are no outstanding requests when 1368 * clock scaling is in progress 1369 */ 1370 blk_mq_quiesce_tagset(&hba->host->tag_set); 1371 mutex_lock(&hba->wb_mutex); 1372 down_write(&hba->clk_scaling_lock); 1373 1374 if (!hba->clk_scaling.is_allowed || 1375 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1376 ret = -EBUSY; 1377 up_write(&hba->clk_scaling_lock); 1378 mutex_unlock(&hba->wb_mutex); 1379 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1380 goto out; 1381 } 1382 1383 /* let's not get into low power until clock scaling is completed */ 1384 ufshcd_hold(hba); 1385 1386 out: 1387 return ret; 1388 } 1389 1390 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1391 { 1392 up_write(&hba->clk_scaling_lock); 1393 1394 /* Enable Write Booster if we have scaled up else disable it */ 1395 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1396 ufshcd_wb_toggle(hba, scale_up); 1397 1398 mutex_unlock(&hba->wb_mutex); 1399 1400 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1401 ufshcd_release(hba); 1402 } 1403 1404 /** 1405 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1406 * @hba: per adapter instance 1407 * @freq: frequency to scale 1408 * @scale_up: True for scaling up and false for scalin down 1409 * 1410 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1411 * for any other errors. 1412 */ 1413 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, 1414 bool scale_up) 1415 { 1416 int ret = 0; 1417 1418 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1419 if (ret) 1420 return ret; 1421 1422 /* scale down the gear before scaling down clocks */ 1423 if (!scale_up) { 1424 ret = ufshcd_scale_gear(hba, false); 1425 if (ret) 1426 goto out_unprepare; 1427 } 1428 1429 ret = ufshcd_scale_clks(hba, freq, scale_up); 1430 if (ret) { 1431 if (!scale_up) 1432 ufshcd_scale_gear(hba, true); 1433 goto out_unprepare; 1434 } 1435 1436 /* scale up the gear after scaling up clocks */ 1437 if (scale_up) { 1438 ret = ufshcd_scale_gear(hba, true); 1439 if (ret) { 1440 ufshcd_scale_clks(hba, hba->devfreq->previous_freq, 1441 false); 1442 goto out_unprepare; 1443 } 1444 } 1445 1446 out_unprepare: 1447 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1448 return ret; 1449 } 1450 1451 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1452 { 1453 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1454 clk_scaling.suspend_work); 1455 unsigned long irq_flags; 1456 1457 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1458 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1459 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1460 return; 1461 } 1462 hba->clk_scaling.is_suspended = true; 1463 hba->clk_scaling.window_start_t = 0; 1464 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1465 1466 devfreq_suspend_device(hba->devfreq); 1467 } 1468 1469 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1470 { 1471 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1472 clk_scaling.resume_work); 1473 unsigned long irq_flags; 1474 1475 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1476 if (!hba->clk_scaling.is_suspended) { 1477 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1478 return; 1479 } 1480 hba->clk_scaling.is_suspended = false; 1481 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1482 1483 devfreq_resume_device(hba->devfreq); 1484 } 1485 1486 static int ufshcd_devfreq_target(struct device *dev, 1487 unsigned long *freq, u32 flags) 1488 { 1489 int ret = 0; 1490 struct ufs_hba *hba = dev_get_drvdata(dev); 1491 ktime_t start; 1492 bool scale_up = false, sched_clk_scaling_suspend_work = false; 1493 struct list_head *clk_list = &hba->clk_list_head; 1494 struct ufs_clk_info *clki; 1495 unsigned long irq_flags; 1496 1497 if (!ufshcd_is_clkscaling_supported(hba)) 1498 return -EINVAL; 1499 1500 if (hba->use_pm_opp) { 1501 struct dev_pm_opp *opp; 1502 1503 /* Get the recommended frequency from OPP framework */ 1504 opp = devfreq_recommended_opp(dev, freq, flags); 1505 if (IS_ERR(opp)) 1506 return PTR_ERR(opp); 1507 1508 dev_pm_opp_put(opp); 1509 } else { 1510 /* Override with the closest supported frequency */ 1511 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, 1512 list); 1513 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1514 } 1515 1516 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1517 if (ufshcd_eh_in_progress(hba)) { 1518 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1519 return 0; 1520 } 1521 1522 /* Skip scaling clock when clock scaling is suspended */ 1523 if (hba->clk_scaling.is_suspended) { 1524 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1525 dev_warn(hba->dev, "clock scaling is suspended, skip"); 1526 return 0; 1527 } 1528 1529 if (!hba->clk_scaling.active_reqs) 1530 sched_clk_scaling_suspend_work = true; 1531 1532 if (list_empty(clk_list)) { 1533 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1534 goto out; 1535 } 1536 1537 /* Decide based on the target or rounded-off frequency and update */ 1538 if (hba->use_pm_opp) 1539 scale_up = *freq > hba->clk_scaling.target_freq; 1540 else 1541 scale_up = *freq == clki->max_freq; 1542 1543 if (!hba->use_pm_opp && !scale_up) 1544 *freq = clki->min_freq; 1545 1546 /* Update the frequency */ 1547 if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) { 1548 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1549 ret = 0; 1550 goto out; /* no state change required */ 1551 } 1552 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1553 1554 start = ktime_get(); 1555 ret = ufshcd_devfreq_scale(hba, *freq, scale_up); 1556 if (!ret) 1557 hba->clk_scaling.target_freq = *freq; 1558 1559 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1560 (scale_up ? "up" : "down"), 1561 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1562 1563 out: 1564 if (sched_clk_scaling_suspend_work && 1565 (!scale_up || hba->clk_scaling.suspend_on_no_request)) 1566 queue_work(hba->clk_scaling.workq, 1567 &hba->clk_scaling.suspend_work); 1568 1569 return ret; 1570 } 1571 1572 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1573 struct devfreq_dev_status *stat) 1574 { 1575 struct ufs_hba *hba = dev_get_drvdata(dev); 1576 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1577 unsigned long flags; 1578 ktime_t curr_t; 1579 1580 if (!ufshcd_is_clkscaling_supported(hba)) 1581 return -EINVAL; 1582 1583 memset(stat, 0, sizeof(*stat)); 1584 1585 spin_lock_irqsave(hba->host->host_lock, flags); 1586 curr_t = ktime_get(); 1587 if (!scaling->window_start_t) 1588 goto start_window; 1589 1590 /* 1591 * If current frequency is 0, then the ondemand governor considers 1592 * there's no initial frequency set. And it always requests to set 1593 * to max. frequency. 1594 */ 1595 if (hba->use_pm_opp) { 1596 stat->current_frequency = hba->clk_scaling.target_freq; 1597 } else { 1598 struct list_head *clk_list = &hba->clk_list_head; 1599 struct ufs_clk_info *clki; 1600 1601 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1602 stat->current_frequency = clki->curr_freq; 1603 } 1604 1605 if (scaling->is_busy_started) 1606 scaling->tot_busy_t += ktime_us_delta(curr_t, 1607 scaling->busy_start_t); 1608 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1609 stat->busy_time = scaling->tot_busy_t; 1610 start_window: 1611 scaling->window_start_t = curr_t; 1612 scaling->tot_busy_t = 0; 1613 1614 if (scaling->active_reqs) { 1615 scaling->busy_start_t = curr_t; 1616 scaling->is_busy_started = true; 1617 } else { 1618 scaling->busy_start_t = 0; 1619 scaling->is_busy_started = false; 1620 } 1621 spin_unlock_irqrestore(hba->host->host_lock, flags); 1622 return 0; 1623 } 1624 1625 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1626 { 1627 struct list_head *clk_list = &hba->clk_list_head; 1628 struct ufs_clk_info *clki; 1629 struct devfreq *devfreq; 1630 int ret; 1631 1632 /* Skip devfreq if we don't have any clocks in the list */ 1633 if (list_empty(clk_list)) 1634 return 0; 1635 1636 if (!hba->use_pm_opp) { 1637 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1638 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1639 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1640 } 1641 1642 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1643 &hba->vps->ondemand_data); 1644 devfreq = devfreq_add_device(hba->dev, 1645 &hba->vps->devfreq_profile, 1646 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1647 &hba->vps->ondemand_data); 1648 if (IS_ERR(devfreq)) { 1649 ret = PTR_ERR(devfreq); 1650 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1651 1652 if (!hba->use_pm_opp) { 1653 dev_pm_opp_remove(hba->dev, clki->min_freq); 1654 dev_pm_opp_remove(hba->dev, clki->max_freq); 1655 } 1656 return ret; 1657 } 1658 1659 hba->devfreq = devfreq; 1660 1661 return 0; 1662 } 1663 1664 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1665 { 1666 struct list_head *clk_list = &hba->clk_list_head; 1667 1668 if (!hba->devfreq) 1669 return; 1670 1671 devfreq_remove_device(hba->devfreq); 1672 hba->devfreq = NULL; 1673 1674 if (!hba->use_pm_opp) { 1675 struct ufs_clk_info *clki; 1676 1677 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1678 dev_pm_opp_remove(hba->dev, clki->min_freq); 1679 dev_pm_opp_remove(hba->dev, clki->max_freq); 1680 } 1681 } 1682 1683 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1684 { 1685 unsigned long flags; 1686 bool suspend = false; 1687 1688 cancel_work_sync(&hba->clk_scaling.suspend_work); 1689 cancel_work_sync(&hba->clk_scaling.resume_work); 1690 1691 spin_lock_irqsave(hba->host->host_lock, flags); 1692 if (!hba->clk_scaling.is_suspended) { 1693 suspend = true; 1694 hba->clk_scaling.is_suspended = true; 1695 hba->clk_scaling.window_start_t = 0; 1696 } 1697 spin_unlock_irqrestore(hba->host->host_lock, flags); 1698 1699 if (suspend) 1700 devfreq_suspend_device(hba->devfreq); 1701 } 1702 1703 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1704 { 1705 unsigned long flags; 1706 bool resume = false; 1707 1708 spin_lock_irqsave(hba->host->host_lock, flags); 1709 if (hba->clk_scaling.is_suspended) { 1710 resume = true; 1711 hba->clk_scaling.is_suspended = false; 1712 } 1713 spin_unlock_irqrestore(hba->host->host_lock, flags); 1714 1715 if (resume) 1716 devfreq_resume_device(hba->devfreq); 1717 } 1718 1719 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1720 struct device_attribute *attr, char *buf) 1721 { 1722 struct ufs_hba *hba = dev_get_drvdata(dev); 1723 1724 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1725 } 1726 1727 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1728 struct device_attribute *attr, const char *buf, size_t count) 1729 { 1730 struct ufs_hba *hba = dev_get_drvdata(dev); 1731 u32 value; 1732 int err = 0; 1733 1734 if (kstrtou32(buf, 0, &value)) 1735 return -EINVAL; 1736 1737 down(&hba->host_sem); 1738 if (!ufshcd_is_user_access_allowed(hba)) { 1739 err = -EBUSY; 1740 goto out; 1741 } 1742 1743 value = !!value; 1744 if (value == hba->clk_scaling.is_enabled) 1745 goto out; 1746 1747 ufshcd_rpm_get_sync(hba); 1748 ufshcd_hold(hba); 1749 1750 hba->clk_scaling.is_enabled = value; 1751 1752 if (value) { 1753 ufshcd_resume_clkscaling(hba); 1754 } else { 1755 ufshcd_suspend_clkscaling(hba); 1756 err = ufshcd_devfreq_scale(hba, ULONG_MAX, true); 1757 if (err) 1758 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1759 __func__, err); 1760 } 1761 1762 ufshcd_release(hba); 1763 ufshcd_rpm_put_sync(hba); 1764 out: 1765 up(&hba->host_sem); 1766 return err ? err : count; 1767 } 1768 1769 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1770 { 1771 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1772 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1773 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1774 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1775 hba->clk_scaling.enable_attr.attr.mode = 0644; 1776 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1777 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1778 } 1779 1780 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1781 { 1782 if (hba->clk_scaling.enable_attr.attr.name) 1783 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1784 } 1785 1786 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1787 { 1788 char wq_name[sizeof("ufs_clkscaling_00")]; 1789 1790 if (!ufshcd_is_clkscaling_supported(hba)) 1791 return; 1792 1793 if (!hba->clk_scaling.min_gear) 1794 hba->clk_scaling.min_gear = UFS_HS_G1; 1795 1796 INIT_WORK(&hba->clk_scaling.suspend_work, 1797 ufshcd_clk_scaling_suspend_work); 1798 INIT_WORK(&hba->clk_scaling.resume_work, 1799 ufshcd_clk_scaling_resume_work); 1800 1801 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d", 1802 hba->host->host_no); 1803 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name); 1804 1805 hba->clk_scaling.is_initialized = true; 1806 } 1807 1808 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1809 { 1810 if (!hba->clk_scaling.is_initialized) 1811 return; 1812 1813 ufshcd_remove_clk_scaling_sysfs(hba); 1814 destroy_workqueue(hba->clk_scaling.workq); 1815 ufshcd_devfreq_remove(hba); 1816 hba->clk_scaling.is_initialized = false; 1817 } 1818 1819 static void ufshcd_ungate_work(struct work_struct *work) 1820 { 1821 int ret; 1822 unsigned long flags; 1823 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1824 clk_gating.ungate_work); 1825 1826 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1827 1828 spin_lock_irqsave(hba->host->host_lock, flags); 1829 if (hba->clk_gating.state == CLKS_ON) { 1830 spin_unlock_irqrestore(hba->host->host_lock, flags); 1831 return; 1832 } 1833 1834 spin_unlock_irqrestore(hba->host->host_lock, flags); 1835 ufshcd_hba_vreg_set_hpm(hba); 1836 ufshcd_setup_clocks(hba, true); 1837 1838 ufshcd_enable_irq(hba); 1839 1840 /* Exit from hibern8 */ 1841 if (ufshcd_can_hibern8_during_gating(hba)) { 1842 /* Prevent gating in this path */ 1843 hba->clk_gating.is_suspended = true; 1844 if (ufshcd_is_link_hibern8(hba)) { 1845 ret = ufshcd_uic_hibern8_exit(hba); 1846 if (ret) 1847 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1848 __func__, ret); 1849 else 1850 ufshcd_set_link_active(hba); 1851 } 1852 hba->clk_gating.is_suspended = false; 1853 } 1854 } 1855 1856 /** 1857 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1858 * Also, exit from hibern8 mode and set the link as active. 1859 * @hba: per adapter instance 1860 */ 1861 void ufshcd_hold(struct ufs_hba *hba) 1862 { 1863 bool flush_result; 1864 unsigned long flags; 1865 1866 if (!ufshcd_is_clkgating_allowed(hba) || 1867 !hba->clk_gating.is_initialized) 1868 return; 1869 spin_lock_irqsave(hba->host->host_lock, flags); 1870 hba->clk_gating.active_reqs++; 1871 1872 start: 1873 switch (hba->clk_gating.state) { 1874 case CLKS_ON: 1875 /* 1876 * Wait for the ungate work to complete if in progress. 1877 * Though the clocks may be in ON state, the link could 1878 * still be in hibner8 state if hibern8 is allowed 1879 * during clock gating. 1880 * Make sure we exit hibern8 state also in addition to 1881 * clocks being ON. 1882 */ 1883 if (ufshcd_can_hibern8_during_gating(hba) && 1884 ufshcd_is_link_hibern8(hba)) { 1885 spin_unlock_irqrestore(hba->host->host_lock, flags); 1886 flush_result = flush_work(&hba->clk_gating.ungate_work); 1887 if (hba->clk_gating.is_suspended && !flush_result) 1888 return; 1889 spin_lock_irqsave(hba->host->host_lock, flags); 1890 goto start; 1891 } 1892 break; 1893 case REQ_CLKS_OFF: 1894 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1895 hba->clk_gating.state = CLKS_ON; 1896 trace_ufshcd_clk_gating(dev_name(hba->dev), 1897 hba->clk_gating.state); 1898 break; 1899 } 1900 /* 1901 * If we are here, it means gating work is either done or 1902 * currently running. Hence, fall through to cancel gating 1903 * work and to enable clocks. 1904 */ 1905 fallthrough; 1906 case CLKS_OFF: 1907 hba->clk_gating.state = REQ_CLKS_ON; 1908 trace_ufshcd_clk_gating(dev_name(hba->dev), 1909 hba->clk_gating.state); 1910 queue_work(hba->clk_gating.clk_gating_workq, 1911 &hba->clk_gating.ungate_work); 1912 /* 1913 * fall through to check if we should wait for this 1914 * work to be done or not. 1915 */ 1916 fallthrough; 1917 case REQ_CLKS_ON: 1918 spin_unlock_irqrestore(hba->host->host_lock, flags); 1919 flush_work(&hba->clk_gating.ungate_work); 1920 /* Make sure state is CLKS_ON before returning */ 1921 spin_lock_irqsave(hba->host->host_lock, flags); 1922 goto start; 1923 default: 1924 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1925 __func__, hba->clk_gating.state); 1926 break; 1927 } 1928 spin_unlock_irqrestore(hba->host->host_lock, flags); 1929 } 1930 EXPORT_SYMBOL_GPL(ufshcd_hold); 1931 1932 static void ufshcd_gate_work(struct work_struct *work) 1933 { 1934 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1935 clk_gating.gate_work.work); 1936 unsigned long flags; 1937 int ret; 1938 1939 spin_lock_irqsave(hba->host->host_lock, flags); 1940 /* 1941 * In case you are here to cancel this work the gating state 1942 * would be marked as REQ_CLKS_ON. In this case save time by 1943 * skipping the gating work and exit after changing the clock 1944 * state to CLKS_ON. 1945 */ 1946 if (hba->clk_gating.is_suspended || 1947 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1948 hba->clk_gating.state = CLKS_ON; 1949 trace_ufshcd_clk_gating(dev_name(hba->dev), 1950 hba->clk_gating.state); 1951 goto rel_lock; 1952 } 1953 1954 if (ufshcd_is_ufs_dev_busy(hba) || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) 1955 goto rel_lock; 1956 1957 spin_unlock_irqrestore(hba->host->host_lock, flags); 1958 1959 /* put the link into hibern8 mode before turning off clocks */ 1960 if (ufshcd_can_hibern8_during_gating(hba)) { 1961 ret = ufshcd_uic_hibern8_enter(hba); 1962 if (ret) { 1963 hba->clk_gating.state = CLKS_ON; 1964 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1965 __func__, ret); 1966 trace_ufshcd_clk_gating(dev_name(hba->dev), 1967 hba->clk_gating.state); 1968 goto out; 1969 } 1970 ufshcd_set_link_hibern8(hba); 1971 } 1972 1973 ufshcd_disable_irq(hba); 1974 1975 ufshcd_setup_clocks(hba, false); 1976 1977 /* Put the host controller in low power mode if possible */ 1978 ufshcd_hba_vreg_set_lpm(hba); 1979 /* 1980 * In case you are here to cancel this work the gating state 1981 * would be marked as REQ_CLKS_ON. In this case keep the state 1982 * as REQ_CLKS_ON which would anyway imply that clocks are off 1983 * and a request to turn them on is pending. By doing this way, 1984 * we keep the state machine in tact and this would ultimately 1985 * prevent from doing cancel work multiple times when there are 1986 * new requests arriving before the current cancel work is done. 1987 */ 1988 spin_lock_irqsave(hba->host->host_lock, flags); 1989 if (hba->clk_gating.state == REQ_CLKS_OFF) { 1990 hba->clk_gating.state = CLKS_OFF; 1991 trace_ufshcd_clk_gating(dev_name(hba->dev), 1992 hba->clk_gating.state); 1993 } 1994 rel_lock: 1995 spin_unlock_irqrestore(hba->host->host_lock, flags); 1996 out: 1997 return; 1998 } 1999 2000 /* host lock must be held before calling this variant */ 2001 static void __ufshcd_release(struct ufs_hba *hba) 2002 { 2003 if (!ufshcd_is_clkgating_allowed(hba)) 2004 return; 2005 2006 hba->clk_gating.active_reqs--; 2007 2008 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 2009 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 2010 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 2011 hba->active_uic_cmd || hba->uic_async_done || 2012 hba->clk_gating.state == CLKS_OFF) 2013 return; 2014 2015 hba->clk_gating.state = REQ_CLKS_OFF; 2016 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 2017 queue_delayed_work(hba->clk_gating.clk_gating_workq, 2018 &hba->clk_gating.gate_work, 2019 msecs_to_jiffies(hba->clk_gating.delay_ms)); 2020 } 2021 2022 void ufshcd_release(struct ufs_hba *hba) 2023 { 2024 unsigned long flags; 2025 2026 spin_lock_irqsave(hba->host->host_lock, flags); 2027 __ufshcd_release(hba); 2028 spin_unlock_irqrestore(hba->host->host_lock, flags); 2029 } 2030 EXPORT_SYMBOL_GPL(ufshcd_release); 2031 2032 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 2033 struct device_attribute *attr, char *buf) 2034 { 2035 struct ufs_hba *hba = dev_get_drvdata(dev); 2036 2037 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 2038 } 2039 2040 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 2041 { 2042 struct ufs_hba *hba = dev_get_drvdata(dev); 2043 unsigned long flags; 2044 2045 spin_lock_irqsave(hba->host->host_lock, flags); 2046 hba->clk_gating.delay_ms = value; 2047 spin_unlock_irqrestore(hba->host->host_lock, flags); 2048 } 2049 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 2050 2051 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 2052 struct device_attribute *attr, const char *buf, size_t count) 2053 { 2054 unsigned long value; 2055 2056 if (kstrtoul(buf, 0, &value)) 2057 return -EINVAL; 2058 2059 ufshcd_clkgate_delay_set(dev, value); 2060 return count; 2061 } 2062 2063 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 2064 struct device_attribute *attr, char *buf) 2065 { 2066 struct ufs_hba *hba = dev_get_drvdata(dev); 2067 2068 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 2069 } 2070 2071 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 2072 struct device_attribute *attr, const char *buf, size_t count) 2073 { 2074 struct ufs_hba *hba = dev_get_drvdata(dev); 2075 unsigned long flags; 2076 u32 value; 2077 2078 if (kstrtou32(buf, 0, &value)) 2079 return -EINVAL; 2080 2081 value = !!value; 2082 2083 spin_lock_irqsave(hba->host->host_lock, flags); 2084 if (value == hba->clk_gating.is_enabled) 2085 goto out; 2086 2087 if (value) 2088 __ufshcd_release(hba); 2089 else 2090 hba->clk_gating.active_reqs++; 2091 2092 hba->clk_gating.is_enabled = value; 2093 out: 2094 spin_unlock_irqrestore(hba->host->host_lock, flags); 2095 return count; 2096 } 2097 2098 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 2099 { 2100 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 2101 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 2102 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 2103 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 2104 hba->clk_gating.delay_attr.attr.mode = 0644; 2105 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 2106 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 2107 2108 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 2109 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 2110 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 2111 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 2112 hba->clk_gating.enable_attr.attr.mode = 0644; 2113 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 2114 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 2115 } 2116 2117 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 2118 { 2119 if (hba->clk_gating.delay_attr.attr.name) 2120 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 2121 if (hba->clk_gating.enable_attr.attr.name) 2122 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 2123 } 2124 2125 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 2126 { 2127 char wq_name[sizeof("ufs_clk_gating_00")]; 2128 2129 if (!ufshcd_is_clkgating_allowed(hba)) 2130 return; 2131 2132 hba->clk_gating.state = CLKS_ON; 2133 2134 hba->clk_gating.delay_ms = 150; 2135 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2136 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2137 2138 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d", 2139 hba->host->host_no); 2140 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name, 2141 WQ_MEM_RECLAIM | WQ_HIGHPRI); 2142 2143 ufshcd_init_clk_gating_sysfs(hba); 2144 2145 hba->clk_gating.is_enabled = true; 2146 hba->clk_gating.is_initialized = true; 2147 } 2148 2149 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2150 { 2151 if (!hba->clk_gating.is_initialized) 2152 return; 2153 2154 ufshcd_remove_clk_gating_sysfs(hba); 2155 2156 /* Ungate the clock if necessary. */ 2157 ufshcd_hold(hba); 2158 hba->clk_gating.is_initialized = false; 2159 ufshcd_release(hba); 2160 2161 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2162 } 2163 2164 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2165 { 2166 bool queue_resume_work = false; 2167 ktime_t curr_t = ktime_get(); 2168 unsigned long flags; 2169 2170 if (!ufshcd_is_clkscaling_supported(hba)) 2171 return; 2172 2173 spin_lock_irqsave(hba->host->host_lock, flags); 2174 if (!hba->clk_scaling.active_reqs++) 2175 queue_resume_work = true; 2176 2177 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2178 spin_unlock_irqrestore(hba->host->host_lock, flags); 2179 return; 2180 } 2181 2182 if (queue_resume_work) 2183 queue_work(hba->clk_scaling.workq, 2184 &hba->clk_scaling.resume_work); 2185 2186 if (!hba->clk_scaling.window_start_t) { 2187 hba->clk_scaling.window_start_t = curr_t; 2188 hba->clk_scaling.tot_busy_t = 0; 2189 hba->clk_scaling.is_busy_started = false; 2190 } 2191 2192 if (!hba->clk_scaling.is_busy_started) { 2193 hba->clk_scaling.busy_start_t = curr_t; 2194 hba->clk_scaling.is_busy_started = true; 2195 } 2196 spin_unlock_irqrestore(hba->host->host_lock, flags); 2197 } 2198 2199 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2200 { 2201 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2202 unsigned long flags; 2203 2204 if (!ufshcd_is_clkscaling_supported(hba)) 2205 return; 2206 2207 spin_lock_irqsave(hba->host->host_lock, flags); 2208 hba->clk_scaling.active_reqs--; 2209 if (!scaling->active_reqs && scaling->is_busy_started) { 2210 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2211 scaling->busy_start_t)); 2212 scaling->busy_start_t = 0; 2213 scaling->is_busy_started = false; 2214 } 2215 spin_unlock_irqrestore(hba->host->host_lock, flags); 2216 } 2217 2218 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2219 { 2220 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2221 return READ; 2222 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2223 return WRITE; 2224 else 2225 return -EINVAL; 2226 } 2227 2228 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2229 struct ufshcd_lrb *lrbp) 2230 { 2231 const struct ufs_hba_monitor *m = &hba->monitor; 2232 2233 return (m->enabled && lrbp && lrbp->cmd && 2234 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2235 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2236 } 2237 2238 static void ufshcd_start_monitor(struct ufs_hba *hba, 2239 const struct ufshcd_lrb *lrbp) 2240 { 2241 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2242 unsigned long flags; 2243 2244 spin_lock_irqsave(hba->host->host_lock, flags); 2245 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2246 hba->monitor.busy_start_ts[dir] = ktime_get(); 2247 spin_unlock_irqrestore(hba->host->host_lock, flags); 2248 } 2249 2250 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2251 { 2252 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2253 unsigned long flags; 2254 2255 spin_lock_irqsave(hba->host->host_lock, flags); 2256 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2257 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2258 struct ufs_hba_monitor *m = &hba->monitor; 2259 ktime_t now, inc, lat; 2260 2261 now = lrbp->compl_time_stamp; 2262 inc = ktime_sub(now, m->busy_start_ts[dir]); 2263 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2264 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2265 2266 /* Update latencies */ 2267 m->nr_req[dir]++; 2268 lat = ktime_sub(now, lrbp->issue_time_stamp); 2269 m->lat_sum[dir] += lat; 2270 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2271 m->lat_max[dir] = lat; 2272 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2273 m->lat_min[dir] = lat; 2274 2275 m->nr_queued[dir]--; 2276 /* Push forward the busy start of monitor */ 2277 m->busy_start_ts[dir] = now; 2278 } 2279 spin_unlock_irqrestore(hba->host->host_lock, flags); 2280 } 2281 2282 /** 2283 * ufshcd_send_command - Send SCSI or device management commands 2284 * @hba: per adapter instance 2285 * @task_tag: Task tag of the command 2286 * @hwq: pointer to hardware queue instance 2287 */ 2288 static inline 2289 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2290 struct ufs_hw_queue *hwq) 2291 { 2292 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2293 unsigned long flags; 2294 2295 lrbp->issue_time_stamp = ktime_get(); 2296 lrbp->issue_time_stamp_local_clock = local_clock(); 2297 lrbp->compl_time_stamp = ktime_set(0, 0); 2298 lrbp->compl_time_stamp_local_clock = 0; 2299 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2300 if (lrbp->cmd) 2301 ufshcd_clk_scaling_start_busy(hba); 2302 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2303 ufshcd_start_monitor(hba, lrbp); 2304 2305 if (hba->mcq_enabled) { 2306 int utrd_size = sizeof(struct utp_transfer_req_desc); 2307 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2308 struct utp_transfer_req_desc *dest; 2309 2310 spin_lock(&hwq->sq_lock); 2311 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2312 memcpy(dest, src, utrd_size); 2313 ufshcd_inc_sq_tail(hwq); 2314 spin_unlock(&hwq->sq_lock); 2315 } else { 2316 spin_lock_irqsave(&hba->outstanding_lock, flags); 2317 if (hba->vops && hba->vops->setup_xfer_req) 2318 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2319 !!lrbp->cmd); 2320 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2321 ufshcd_writel(hba, 1 << lrbp->task_tag, 2322 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2323 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2324 } 2325 } 2326 2327 /** 2328 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2329 * @lrbp: pointer to local reference block 2330 */ 2331 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2332 { 2333 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2334 u16 resp_len; 2335 int len; 2336 2337 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2338 if (sense_buffer && resp_len) { 2339 int len_to_copy; 2340 2341 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2342 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2343 2344 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2345 len_to_copy); 2346 } 2347 } 2348 2349 /** 2350 * ufshcd_copy_query_response() - Copy the Query Response and the data 2351 * descriptor 2352 * @hba: per adapter instance 2353 * @lrbp: pointer to local reference block 2354 * 2355 * Return: 0 upon success; < 0 upon failure. 2356 */ 2357 static 2358 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2359 { 2360 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2361 2362 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2363 2364 /* Get the descriptor */ 2365 if (hba->dev_cmd.query.descriptor && 2366 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2367 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2368 GENERAL_UPIU_REQUEST_SIZE; 2369 u16 resp_len; 2370 u16 buf_len; 2371 2372 /* data segment length */ 2373 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2374 .data_segment_length); 2375 buf_len = be16_to_cpu( 2376 hba->dev_cmd.query.request.upiu_req.length); 2377 if (likely(buf_len >= resp_len)) { 2378 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2379 } else { 2380 dev_warn(hba->dev, 2381 "%s: rsp size %d is bigger than buffer size %d", 2382 __func__, resp_len, buf_len); 2383 return -EINVAL; 2384 } 2385 } 2386 2387 return 0; 2388 } 2389 2390 /** 2391 * ufshcd_hba_capabilities - Read controller capabilities 2392 * @hba: per adapter instance 2393 * 2394 * Return: 0 on success, negative on error. 2395 */ 2396 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2397 { 2398 int err; 2399 2400 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2401 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) 2402 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT; 2403 2404 /* nutrs and nutmrs are 0 based values */ 2405 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS_SDB) + 1; 2406 hba->nutmrs = 2407 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2408 hba->reserved_slot = hba->nutrs - 1; 2409 2410 hba->nortt = FIELD_GET(MASK_NUMBER_OUTSTANDING_RTT, hba->capabilities) + 1; 2411 2412 /* Read crypto capabilities */ 2413 err = ufshcd_hba_init_crypto_capabilities(hba); 2414 if (err) { 2415 dev_err(hba->dev, "crypto setup failed\n"); 2416 return err; 2417 } 2418 2419 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2420 if (!hba->mcq_sup) 2421 return 0; 2422 2423 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2424 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2425 hba->mcq_capabilities); 2426 2427 return 0; 2428 } 2429 2430 /** 2431 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2432 * to accept UIC commands 2433 * @hba: per adapter instance 2434 * 2435 * Return: true on success, else false. 2436 */ 2437 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2438 { 2439 u32 val; 2440 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2441 500, UIC_CMD_TIMEOUT * 1000, false, hba, 2442 REG_CONTROLLER_STATUS); 2443 return ret == 0; 2444 } 2445 2446 /** 2447 * ufshcd_get_upmcrs - Get the power mode change request status 2448 * @hba: Pointer to adapter instance 2449 * 2450 * This function gets the UPMCRS field of HCS register 2451 * 2452 * Return: value of UPMCRS field. 2453 */ 2454 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2455 { 2456 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2457 } 2458 2459 /** 2460 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2461 * @hba: per adapter instance 2462 * @uic_cmd: UIC command 2463 */ 2464 static inline void 2465 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2466 { 2467 lockdep_assert_held(&hba->uic_cmd_mutex); 2468 2469 WARN_ON(hba->active_uic_cmd); 2470 2471 hba->active_uic_cmd = uic_cmd; 2472 2473 /* Write Args */ 2474 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2475 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2476 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2477 2478 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2479 2480 /* Write UIC Cmd */ 2481 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2482 REG_UIC_COMMAND); 2483 } 2484 2485 /** 2486 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2487 * @hba: per adapter instance 2488 * @uic_cmd: UIC command 2489 * 2490 * Return: 0 only if success. 2491 */ 2492 static int 2493 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2494 { 2495 int ret; 2496 unsigned long flags; 2497 2498 lockdep_assert_held(&hba->uic_cmd_mutex); 2499 2500 if (wait_for_completion_timeout(&uic_cmd->done, 2501 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 2502 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2503 } else { 2504 ret = -ETIMEDOUT; 2505 dev_err(hba->dev, 2506 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2507 uic_cmd->command, uic_cmd->argument3); 2508 2509 if (!uic_cmd->cmd_active) { 2510 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2511 __func__); 2512 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2513 } 2514 } 2515 2516 spin_lock_irqsave(hba->host->host_lock, flags); 2517 hba->active_uic_cmd = NULL; 2518 spin_unlock_irqrestore(hba->host->host_lock, flags); 2519 2520 return ret; 2521 } 2522 2523 /** 2524 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2525 * @hba: per adapter instance 2526 * @uic_cmd: UIC command 2527 * @completion: initialize the completion only if this is set to true 2528 * 2529 * Return: 0 only if success. 2530 */ 2531 static int 2532 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd, 2533 bool completion) 2534 { 2535 lockdep_assert_held(&hba->uic_cmd_mutex); 2536 2537 if (!ufshcd_ready_for_uic_cmd(hba)) { 2538 dev_err(hba->dev, 2539 "Controller not ready to accept UIC commands\n"); 2540 return -EIO; 2541 } 2542 2543 if (completion) 2544 init_completion(&uic_cmd->done); 2545 2546 uic_cmd->cmd_active = 1; 2547 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2548 2549 return 0; 2550 } 2551 2552 /** 2553 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2554 * @hba: per adapter instance 2555 * @uic_cmd: UIC command 2556 * 2557 * Return: 0 only if success. 2558 */ 2559 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2560 { 2561 int ret; 2562 2563 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2564 return 0; 2565 2566 ufshcd_hold(hba); 2567 mutex_lock(&hba->uic_cmd_mutex); 2568 ufshcd_add_delay_before_dme_cmd(hba); 2569 2570 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true); 2571 if (!ret) 2572 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2573 2574 mutex_unlock(&hba->uic_cmd_mutex); 2575 2576 ufshcd_release(hba); 2577 return ret; 2578 } 2579 2580 /** 2581 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2582 * @hba: per-adapter instance 2583 * @lrbp: pointer to local reference block 2584 * @sg_entries: The number of sg lists actually used 2585 * @sg_list: Pointer to SG list 2586 */ 2587 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2588 struct scatterlist *sg_list) 2589 { 2590 struct ufshcd_sg_entry *prd; 2591 struct scatterlist *sg; 2592 int i; 2593 2594 if (sg_entries) { 2595 2596 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2597 lrbp->utr_descriptor_ptr->prd_table_length = 2598 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2599 else 2600 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2601 2602 prd = lrbp->ucd_prdt_ptr; 2603 2604 for_each_sg(sg_list, sg, sg_entries, i) { 2605 const unsigned int len = sg_dma_len(sg); 2606 2607 /* 2608 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2609 * based value that indicates the length, in bytes, of 2610 * the data block. A maximum of length of 256KB may 2611 * exist for any entry. Bits 1:0 of this field shall be 2612 * 11b to indicate Dword granularity. A value of '3' 2613 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2614 */ 2615 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2616 prd->size = cpu_to_le32(len - 1); 2617 prd->addr = cpu_to_le64(sg->dma_address); 2618 prd->reserved = 0; 2619 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2620 } 2621 } else { 2622 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2623 } 2624 } 2625 2626 /** 2627 * ufshcd_map_sg - Map scatter-gather list to prdt 2628 * @hba: per adapter instance 2629 * @lrbp: pointer to local reference block 2630 * 2631 * Return: 0 in case of success, non-zero value in case of failure. 2632 */ 2633 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2634 { 2635 struct scsi_cmnd *cmd = lrbp->cmd; 2636 int sg_segments = scsi_dma_map(cmd); 2637 2638 if (sg_segments < 0) 2639 return sg_segments; 2640 2641 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2642 2643 return ufshcd_crypto_fill_prdt(hba, lrbp); 2644 } 2645 2646 /** 2647 * ufshcd_enable_intr - enable interrupts 2648 * @hba: per adapter instance 2649 * @intrs: interrupt bits 2650 */ 2651 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2652 { 2653 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2654 2655 set |= intrs; 2656 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2657 } 2658 2659 /** 2660 * ufshcd_disable_intr - disable interrupts 2661 * @hba: per adapter instance 2662 * @intrs: interrupt bits 2663 */ 2664 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2665 { 2666 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2667 2668 set &= ~intrs; 2669 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2670 } 2671 2672 /** 2673 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2674 * descriptor according to request 2675 * @hba: per adapter instance 2676 * @lrbp: pointer to local reference block 2677 * @upiu_flags: flags required in the header 2678 * @cmd_dir: requests data direction 2679 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2680 */ 2681 static void 2682 ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 2683 u8 *upiu_flags, enum dma_data_direction cmd_dir, 2684 int ehs_length) 2685 { 2686 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2687 struct request_desc_header *h = &req_desc->header; 2688 enum utp_data_direction data_direction; 2689 2690 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2691 2692 *h = (typeof(*h)){ }; 2693 2694 if (cmd_dir == DMA_FROM_DEVICE) { 2695 data_direction = UTP_DEVICE_TO_HOST; 2696 *upiu_flags = UPIU_CMD_FLAGS_READ; 2697 } else if (cmd_dir == DMA_TO_DEVICE) { 2698 data_direction = UTP_HOST_TO_DEVICE; 2699 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2700 } else { 2701 data_direction = UTP_NO_DATA_TRANSFER; 2702 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2703 } 2704 2705 h->command_type = lrbp->command_type; 2706 h->data_direction = data_direction; 2707 h->ehs_length = ehs_length; 2708 2709 if (lrbp->intr_cmd) 2710 h->interrupt = 1; 2711 2712 /* Prepare crypto related dwords */ 2713 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2714 2715 /* 2716 * assigning invalid value for command status. Controller 2717 * updates OCS on command completion, with the command 2718 * status 2719 */ 2720 h->ocs = OCS_INVALID_COMMAND_STATUS; 2721 2722 req_desc->prd_table_length = 0; 2723 } 2724 2725 /** 2726 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2727 * for scsi commands 2728 * @lrbp: local reference block pointer 2729 * @upiu_flags: flags 2730 */ 2731 static 2732 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2733 { 2734 struct scsi_cmnd *cmd = lrbp->cmd; 2735 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2736 unsigned short cdb_len; 2737 2738 ucd_req_ptr->header = (struct utp_upiu_header){ 2739 .transaction_code = UPIU_TRANSACTION_COMMAND, 2740 .flags = upiu_flags, 2741 .lun = lrbp->lun, 2742 .task_tag = lrbp->task_tag, 2743 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2744 }; 2745 2746 WARN_ON_ONCE(ucd_req_ptr->header.task_tag != lrbp->task_tag); 2747 2748 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2749 2750 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2751 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 2752 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2753 2754 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2755 } 2756 2757 /** 2758 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2759 * @hba: UFS hba 2760 * @lrbp: local reference block pointer 2761 * @upiu_flags: flags 2762 */ 2763 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2764 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2765 { 2766 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2767 struct ufs_query *query = &hba->dev_cmd.query; 2768 u16 len = be16_to_cpu(query->request.upiu_req.length); 2769 2770 /* Query request header */ 2771 ucd_req_ptr->header = (struct utp_upiu_header){ 2772 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2773 .flags = upiu_flags, 2774 .lun = lrbp->lun, 2775 .task_tag = lrbp->task_tag, 2776 .query_function = query->request.query_func, 2777 /* Data segment length only need for WRITE_DESC */ 2778 .data_segment_length = 2779 query->request.upiu_req.opcode == 2780 UPIU_QUERY_OPCODE_WRITE_DESC ? 2781 cpu_to_be16(len) : 2782 0, 2783 }; 2784 2785 /* Copy the Query Request buffer as is */ 2786 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2787 QUERY_OSF_SIZE); 2788 2789 /* Copy the Descriptor */ 2790 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2791 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2792 2793 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2794 } 2795 2796 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2797 { 2798 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2799 2800 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2801 2802 ucd_req_ptr->header = (struct utp_upiu_header){ 2803 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2804 .task_tag = lrbp->task_tag, 2805 }; 2806 2807 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2808 } 2809 2810 /** 2811 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2812 * for Device Management Purposes 2813 * @hba: per adapter instance 2814 * @lrbp: pointer to local reference block 2815 * 2816 * Return: 0 upon success; < 0 upon failure. 2817 */ 2818 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2819 struct ufshcd_lrb *lrbp) 2820 { 2821 u8 upiu_flags; 2822 int ret = 0; 2823 2824 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 2825 2826 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2827 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2828 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2829 ufshcd_prepare_utp_nop_upiu(lrbp); 2830 else 2831 ret = -EINVAL; 2832 2833 return ret; 2834 } 2835 2836 /** 2837 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2838 * for SCSI Purposes 2839 * @hba: per adapter instance 2840 * @lrbp: pointer to local reference block 2841 */ 2842 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2843 { 2844 struct request *rq = scsi_cmd_to_rq(lrbp->cmd); 2845 unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq)); 2846 u8 upiu_flags; 2847 2848 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0); 2849 if (ioprio_class == IOPRIO_CLASS_RT) 2850 upiu_flags |= UPIU_CMD_FLAGS_CP; 2851 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2852 } 2853 2854 /** 2855 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2856 * @upiu_wlun_id: UPIU W-LUN id 2857 * 2858 * Return: SCSI W-LUN id. 2859 */ 2860 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2861 { 2862 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2863 } 2864 2865 static inline bool is_device_wlun(struct scsi_device *sdev) 2866 { 2867 return sdev->lun == 2868 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2869 } 2870 2871 /* 2872 * Associate the UFS controller queue with the default and poll HCTX types. 2873 * Initialize the mq_map[] arrays. 2874 */ 2875 static void ufshcd_map_queues(struct Scsi_Host *shost) 2876 { 2877 struct ufs_hba *hba = shost_priv(shost); 2878 int i, queue_offset = 0; 2879 2880 if (!is_mcq_supported(hba)) { 2881 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2882 hba->nr_queues[HCTX_TYPE_READ] = 0; 2883 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2884 hba->nr_hw_queues = 1; 2885 } 2886 2887 for (i = 0; i < shost->nr_maps; i++) { 2888 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2889 2890 map->nr_queues = hba->nr_queues[i]; 2891 if (!map->nr_queues) 2892 continue; 2893 map->queue_offset = queue_offset; 2894 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2895 map->queue_offset = 0; 2896 2897 blk_mq_map_queues(map); 2898 queue_offset += map->nr_queues; 2899 } 2900 } 2901 2902 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2903 { 2904 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2905 i * ufshcd_get_ucd_size(hba); 2906 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2907 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2908 i * ufshcd_get_ucd_size(hba); 2909 u16 response_offset = offsetof(struct utp_transfer_cmd_desc, 2910 response_upiu); 2911 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 2912 2913 lrb->utr_descriptor_ptr = utrdlp + i; 2914 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2915 i * sizeof(struct utp_transfer_req_desc); 2916 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2917 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2918 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2919 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2920 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2921 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2922 } 2923 2924 /** 2925 * ufshcd_queuecommand - main entry point for SCSI requests 2926 * @host: SCSI host pointer 2927 * @cmd: command from SCSI Midlayer 2928 * 2929 * Return: 0 for success, non-zero in case of failure. 2930 */ 2931 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2932 { 2933 struct ufs_hba *hba = shost_priv(host); 2934 int tag = scsi_cmd_to_rq(cmd)->tag; 2935 struct ufshcd_lrb *lrbp; 2936 int err = 0; 2937 struct ufs_hw_queue *hwq = NULL; 2938 2939 switch (hba->ufshcd_state) { 2940 case UFSHCD_STATE_OPERATIONAL: 2941 break; 2942 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2943 /* 2944 * SCSI error handler can call ->queuecommand() while UFS error 2945 * handler is in progress. Error interrupts could change the 2946 * state from UFSHCD_STATE_RESET to 2947 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2948 * being issued in that case. 2949 */ 2950 if (ufshcd_eh_in_progress(hba)) { 2951 err = SCSI_MLQUEUE_HOST_BUSY; 2952 goto out; 2953 } 2954 break; 2955 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2956 /* 2957 * pm_runtime_get_sync() is used at error handling preparation 2958 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2959 * PM ops, it can never be finished if we let SCSI layer keep 2960 * retrying it, which gets err handler stuck forever. Neither 2961 * can we let the scsi cmd pass through, because UFS is in bad 2962 * state, the scsi cmd may eventually time out, which will get 2963 * err handler blocked for too long. So, just fail the scsi cmd 2964 * sent from PM ops, err handler can recover PM error anyways. 2965 */ 2966 if (hba->pm_op_in_progress) { 2967 hba->force_reset = true; 2968 set_host_byte(cmd, DID_BAD_TARGET); 2969 scsi_done(cmd); 2970 goto out; 2971 } 2972 fallthrough; 2973 case UFSHCD_STATE_RESET: 2974 err = SCSI_MLQUEUE_HOST_BUSY; 2975 goto out; 2976 case UFSHCD_STATE_ERROR: 2977 set_host_byte(cmd, DID_ERROR); 2978 scsi_done(cmd); 2979 goto out; 2980 } 2981 2982 hba->req_abort_count = 0; 2983 2984 ufshcd_hold(hba); 2985 2986 lrbp = &hba->lrb[tag]; 2987 lrbp->cmd = cmd; 2988 lrbp->task_tag = tag; 2989 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 2990 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 2991 2992 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp); 2993 2994 lrbp->req_abort_skip = false; 2995 2996 ufshcd_comp_scsi_upiu(hba, lrbp); 2997 2998 err = ufshcd_map_sg(hba, lrbp); 2999 if (err) { 3000 ufshcd_release(hba); 3001 goto out; 3002 } 3003 3004 if (hba->mcq_enabled) 3005 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 3006 3007 ufshcd_send_command(hba, tag, hwq); 3008 3009 out: 3010 if (ufs_trigger_eh(hba)) { 3011 unsigned long flags; 3012 3013 spin_lock_irqsave(hba->host->host_lock, flags); 3014 ufshcd_schedule_eh_work(hba); 3015 spin_unlock_irqrestore(hba->host->host_lock, flags); 3016 } 3017 3018 return err; 3019 } 3020 3021 static void ufshcd_setup_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3022 enum dev_cmd_type cmd_type, u8 lun, int tag) 3023 { 3024 lrbp->cmd = NULL; 3025 lrbp->task_tag = tag; 3026 lrbp->lun = lun; 3027 lrbp->intr_cmd = true; /* No interrupt aggregation */ 3028 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 3029 hba->dev_cmd.type = cmd_type; 3030 } 3031 3032 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 3033 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 3034 { 3035 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 3036 3037 return ufshcd_compose_devman_upiu(hba, lrbp); 3038 } 3039 3040 /* 3041 * Check with the block layer if the command is inflight 3042 * @cmd: command to check. 3043 * 3044 * Return: true if command is inflight; false if not. 3045 */ 3046 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 3047 { 3048 return cmd && blk_mq_rq_state(scsi_cmd_to_rq(cmd)) == MQ_RQ_IN_FLIGHT; 3049 } 3050 3051 /* 3052 * Clear the pending command in the controller and wait until 3053 * the controller confirms that the command has been cleared. 3054 * @hba: per adapter instance 3055 * @task_tag: The tag number of the command to be cleared. 3056 */ 3057 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 3058 { 3059 u32 mask; 3060 unsigned long flags; 3061 int err; 3062 3063 if (hba->mcq_enabled) { 3064 /* 3065 * MCQ mode. Clean up the MCQ resources similar to 3066 * what the ufshcd_utrl_clear() does for SDB mode. 3067 */ 3068 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 3069 if (err) { 3070 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 3071 __func__, task_tag, err); 3072 return err; 3073 } 3074 return 0; 3075 } 3076 3077 mask = 1U << task_tag; 3078 3079 /* clear outstanding transaction before retry */ 3080 spin_lock_irqsave(hba->host->host_lock, flags); 3081 ufshcd_utrl_clear(hba, mask); 3082 spin_unlock_irqrestore(hba->host->host_lock, flags); 3083 3084 /* 3085 * wait for h/w to clear corresponding bit in door-bell. 3086 * max. wait is 1 sec. 3087 */ 3088 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 3089 mask, ~mask, 1000, 1000); 3090 } 3091 3092 /** 3093 * ufshcd_dev_cmd_completion() - handles device management command responses 3094 * @hba: per adapter instance 3095 * @lrbp: pointer to local reference block 3096 * 3097 * Return: 0 upon success; < 0 upon failure. 3098 */ 3099 static int 3100 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 3101 { 3102 enum upiu_response_transaction resp; 3103 int err = 0; 3104 3105 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 3106 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3107 3108 switch (resp) { 3109 case UPIU_TRANSACTION_NOP_IN: 3110 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3111 err = -EINVAL; 3112 dev_err(hba->dev, "%s: unexpected response %x\n", 3113 __func__, resp); 3114 } 3115 break; 3116 case UPIU_TRANSACTION_QUERY_RSP: { 3117 u8 response = lrbp->ucd_rsp_ptr->header.response; 3118 3119 if (response == 0) 3120 err = ufshcd_copy_query_response(hba, lrbp); 3121 break; 3122 } 3123 case UPIU_TRANSACTION_REJECT_UPIU: 3124 /* TODO: handle Reject UPIU Response */ 3125 err = -EPERM; 3126 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3127 __func__); 3128 break; 3129 case UPIU_TRANSACTION_RESPONSE: 3130 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3131 err = -EINVAL; 3132 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3133 } 3134 break; 3135 default: 3136 err = -EINVAL; 3137 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3138 __func__, resp); 3139 break; 3140 } 3141 3142 return err; 3143 } 3144 3145 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3146 struct ufshcd_lrb *lrbp, int max_timeout) 3147 { 3148 unsigned long time_left = msecs_to_jiffies(max_timeout); 3149 unsigned long flags; 3150 bool pending; 3151 int err; 3152 3153 retry: 3154 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3155 time_left); 3156 3157 if (likely(time_left)) { 3158 /* 3159 * The completion handler called complete() and the caller of 3160 * this function still owns the @lrbp tag so the code below does 3161 * not trigger any race conditions. 3162 */ 3163 hba->dev_cmd.complete = NULL; 3164 err = ufshcd_get_tr_ocs(lrbp, NULL); 3165 if (!err) 3166 err = ufshcd_dev_cmd_completion(hba, lrbp); 3167 } else { 3168 err = -ETIMEDOUT; 3169 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3170 __func__, lrbp->task_tag); 3171 3172 /* MCQ mode */ 3173 if (hba->mcq_enabled) { 3174 /* successfully cleared the command, retry if needed */ 3175 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) 3176 err = -EAGAIN; 3177 hba->dev_cmd.complete = NULL; 3178 return err; 3179 } 3180 3181 /* SDB mode */ 3182 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3183 /* successfully cleared the command, retry if needed */ 3184 err = -EAGAIN; 3185 /* 3186 * Since clearing the command succeeded we also need to 3187 * clear the task tag bit from the outstanding_reqs 3188 * variable. 3189 */ 3190 spin_lock_irqsave(&hba->outstanding_lock, flags); 3191 pending = test_bit(lrbp->task_tag, 3192 &hba->outstanding_reqs); 3193 if (pending) { 3194 hba->dev_cmd.complete = NULL; 3195 __clear_bit(lrbp->task_tag, 3196 &hba->outstanding_reqs); 3197 } 3198 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3199 3200 if (!pending) { 3201 /* 3202 * The completion handler ran while we tried to 3203 * clear the command. 3204 */ 3205 time_left = 1; 3206 goto retry; 3207 } 3208 } else { 3209 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3210 __func__, lrbp->task_tag); 3211 3212 spin_lock_irqsave(&hba->outstanding_lock, flags); 3213 pending = test_bit(lrbp->task_tag, 3214 &hba->outstanding_reqs); 3215 if (pending) 3216 hba->dev_cmd.complete = NULL; 3217 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3218 3219 if (!pending) { 3220 /* 3221 * The completion handler ran while we tried to 3222 * clear the command. 3223 */ 3224 time_left = 1; 3225 goto retry; 3226 } 3227 } 3228 } 3229 3230 return err; 3231 } 3232 3233 static void ufshcd_dev_man_lock(struct ufs_hba *hba) 3234 { 3235 ufshcd_hold(hba); 3236 mutex_lock(&hba->dev_cmd.lock); 3237 down_read(&hba->clk_scaling_lock); 3238 } 3239 3240 static void ufshcd_dev_man_unlock(struct ufs_hba *hba) 3241 { 3242 up_read(&hba->clk_scaling_lock); 3243 mutex_unlock(&hba->dev_cmd.lock); 3244 ufshcd_release(hba); 3245 } 3246 3247 static int ufshcd_issue_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3248 const u32 tag, int timeout) 3249 { 3250 DECLARE_COMPLETION_ONSTACK(wait); 3251 int err; 3252 3253 hba->dev_cmd.complete = &wait; 3254 3255 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3256 3257 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3258 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3259 3260 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3261 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3262 3263 return err; 3264 } 3265 3266 /** 3267 * ufshcd_exec_dev_cmd - API for sending device management requests 3268 * @hba: UFS hba 3269 * @cmd_type: specifies the type (NOP, Query...) 3270 * @timeout: timeout in milliseconds 3271 * 3272 * Return: 0 upon success; < 0 upon failure. 3273 * 3274 * NOTE: Since there is only one available tag for device management commands, 3275 * it is expected you hold the hba->dev_cmd.lock mutex. 3276 */ 3277 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3278 enum dev_cmd_type cmd_type, int timeout) 3279 { 3280 const u32 tag = hba->reserved_slot; 3281 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 3282 int err; 3283 3284 /* Protects use of hba->reserved_slot. */ 3285 lockdep_assert_held(&hba->dev_cmd.lock); 3286 3287 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3288 if (unlikely(err)) 3289 return err; 3290 3291 return ufshcd_issue_dev_cmd(hba, lrbp, tag, timeout); 3292 } 3293 3294 /** 3295 * ufshcd_init_query() - init the query response and request parameters 3296 * @hba: per-adapter instance 3297 * @request: address of the request pointer to be initialized 3298 * @response: address of the response pointer to be initialized 3299 * @opcode: operation to perform 3300 * @idn: flag idn to access 3301 * @index: LU number to access 3302 * @selector: query/flag/descriptor further identification 3303 */ 3304 static inline void ufshcd_init_query(struct ufs_hba *hba, 3305 struct ufs_query_req **request, struct ufs_query_res **response, 3306 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3307 { 3308 *request = &hba->dev_cmd.query.request; 3309 *response = &hba->dev_cmd.query.response; 3310 memset(*request, 0, sizeof(struct ufs_query_req)); 3311 memset(*response, 0, sizeof(struct ufs_query_res)); 3312 (*request)->upiu_req.opcode = opcode; 3313 (*request)->upiu_req.idn = idn; 3314 (*request)->upiu_req.index = index; 3315 (*request)->upiu_req.selector = selector; 3316 } 3317 3318 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3319 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3320 { 3321 int ret; 3322 int retries; 3323 3324 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3325 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3326 if (ret) 3327 dev_dbg(hba->dev, 3328 "%s: failed with error %d, retries %d\n", 3329 __func__, ret, retries); 3330 else 3331 break; 3332 } 3333 3334 if (ret) 3335 dev_err(hba->dev, 3336 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3337 __func__, opcode, idn, ret, retries); 3338 return ret; 3339 } 3340 3341 /** 3342 * ufshcd_query_flag() - API function for sending flag query requests 3343 * @hba: per-adapter instance 3344 * @opcode: flag query to perform 3345 * @idn: flag idn to access 3346 * @index: flag index to access 3347 * @flag_res: the flag value after the query request completes 3348 * 3349 * Return: 0 for success, non-zero in case of failure. 3350 */ 3351 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3352 enum flag_idn idn, u8 index, bool *flag_res) 3353 { 3354 struct ufs_query_req *request = NULL; 3355 struct ufs_query_res *response = NULL; 3356 int err, selector = 0; 3357 int timeout = QUERY_REQ_TIMEOUT; 3358 3359 BUG_ON(!hba); 3360 3361 ufshcd_dev_man_lock(hba); 3362 3363 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3364 selector); 3365 3366 switch (opcode) { 3367 case UPIU_QUERY_OPCODE_SET_FLAG: 3368 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3369 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3370 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3371 break; 3372 case UPIU_QUERY_OPCODE_READ_FLAG: 3373 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3374 if (!flag_res) { 3375 /* No dummy reads */ 3376 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3377 __func__); 3378 err = -EINVAL; 3379 goto out_unlock; 3380 } 3381 break; 3382 default: 3383 dev_err(hba->dev, 3384 "%s: Expected query flag opcode but got = %d\n", 3385 __func__, opcode); 3386 err = -EINVAL; 3387 goto out_unlock; 3388 } 3389 3390 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3391 3392 if (err) { 3393 dev_err(hba->dev, 3394 "%s: Sending flag query for idn %d failed, err = %d\n", 3395 __func__, idn, err); 3396 goto out_unlock; 3397 } 3398 3399 if (flag_res) 3400 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3401 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3402 3403 out_unlock: 3404 ufshcd_dev_man_unlock(hba); 3405 return err; 3406 } 3407 3408 /** 3409 * ufshcd_query_attr - API function for sending attribute requests 3410 * @hba: per-adapter instance 3411 * @opcode: attribute opcode 3412 * @idn: attribute idn to access 3413 * @index: index field 3414 * @selector: selector field 3415 * @attr_val: the attribute value after the query request completes 3416 * 3417 * Return: 0 for success, non-zero in case of failure. 3418 */ 3419 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3420 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3421 { 3422 struct ufs_query_req *request = NULL; 3423 struct ufs_query_res *response = NULL; 3424 int err; 3425 3426 BUG_ON(!hba); 3427 3428 if (!attr_val) { 3429 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3430 __func__, opcode); 3431 return -EINVAL; 3432 } 3433 3434 ufshcd_dev_man_lock(hba); 3435 3436 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3437 selector); 3438 3439 switch (opcode) { 3440 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3441 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3442 request->upiu_req.value = cpu_to_be32(*attr_val); 3443 break; 3444 case UPIU_QUERY_OPCODE_READ_ATTR: 3445 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3446 break; 3447 default: 3448 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3449 __func__, opcode); 3450 err = -EINVAL; 3451 goto out_unlock; 3452 } 3453 3454 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3455 3456 if (err) { 3457 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3458 __func__, opcode, idn, index, err); 3459 goto out_unlock; 3460 } 3461 3462 *attr_val = be32_to_cpu(response->upiu_res.value); 3463 3464 out_unlock: 3465 ufshcd_dev_man_unlock(hba); 3466 return err; 3467 } 3468 3469 /** 3470 * ufshcd_query_attr_retry() - API function for sending query 3471 * attribute with retries 3472 * @hba: per-adapter instance 3473 * @opcode: attribute opcode 3474 * @idn: attribute idn to access 3475 * @index: index field 3476 * @selector: selector field 3477 * @attr_val: the attribute value after the query request 3478 * completes 3479 * 3480 * Return: 0 for success, non-zero in case of failure. 3481 */ 3482 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3483 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3484 u32 *attr_val) 3485 { 3486 int ret = 0; 3487 u32 retries; 3488 3489 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3490 ret = ufshcd_query_attr(hba, opcode, idn, index, 3491 selector, attr_val); 3492 if (ret) 3493 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3494 __func__, ret, retries); 3495 else 3496 break; 3497 } 3498 3499 if (ret) 3500 dev_err(hba->dev, 3501 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3502 __func__, idn, ret, QUERY_REQ_RETRIES); 3503 return ret; 3504 } 3505 3506 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3507 enum query_opcode opcode, enum desc_idn idn, u8 index, 3508 u8 selector, u8 *desc_buf, int *buf_len) 3509 { 3510 struct ufs_query_req *request = NULL; 3511 struct ufs_query_res *response = NULL; 3512 int err; 3513 3514 BUG_ON(!hba); 3515 3516 if (!desc_buf) { 3517 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3518 __func__, opcode); 3519 return -EINVAL; 3520 } 3521 3522 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3523 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3524 __func__, *buf_len); 3525 return -EINVAL; 3526 } 3527 3528 ufshcd_dev_man_lock(hba); 3529 3530 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3531 selector); 3532 hba->dev_cmd.query.descriptor = desc_buf; 3533 request->upiu_req.length = cpu_to_be16(*buf_len); 3534 3535 switch (opcode) { 3536 case UPIU_QUERY_OPCODE_WRITE_DESC: 3537 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3538 break; 3539 case UPIU_QUERY_OPCODE_READ_DESC: 3540 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3541 break; 3542 default: 3543 dev_err(hba->dev, 3544 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3545 __func__, opcode); 3546 err = -EINVAL; 3547 goto out_unlock; 3548 } 3549 3550 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3551 3552 if (err) { 3553 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3554 __func__, opcode, idn, index, err); 3555 goto out_unlock; 3556 } 3557 3558 *buf_len = be16_to_cpu(response->upiu_res.length); 3559 3560 out_unlock: 3561 hba->dev_cmd.query.descriptor = NULL; 3562 ufshcd_dev_man_unlock(hba); 3563 return err; 3564 } 3565 3566 /** 3567 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3568 * @hba: per-adapter instance 3569 * @opcode: attribute opcode 3570 * @idn: attribute idn to access 3571 * @index: index field 3572 * @selector: selector field 3573 * @desc_buf: the buffer that contains the descriptor 3574 * @buf_len: length parameter passed to the device 3575 * 3576 * The buf_len parameter will contain, on return, the length parameter 3577 * received on the response. 3578 * 3579 * Return: 0 for success, non-zero in case of failure. 3580 */ 3581 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3582 enum query_opcode opcode, 3583 enum desc_idn idn, u8 index, 3584 u8 selector, 3585 u8 *desc_buf, int *buf_len) 3586 { 3587 int err; 3588 int retries; 3589 3590 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3591 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3592 selector, desc_buf, buf_len); 3593 if (!err || err == -EINVAL) 3594 break; 3595 } 3596 3597 return err; 3598 } 3599 3600 /** 3601 * ufshcd_read_desc_param - read the specified descriptor parameter 3602 * @hba: Pointer to adapter instance 3603 * @desc_id: descriptor idn value 3604 * @desc_index: descriptor index 3605 * @param_offset: offset of the parameter to read 3606 * @param_read_buf: pointer to buffer where parameter would be read 3607 * @param_size: sizeof(param_read_buf) 3608 * 3609 * Return: 0 in case of success, non-zero otherwise. 3610 */ 3611 int ufshcd_read_desc_param(struct ufs_hba *hba, 3612 enum desc_idn desc_id, 3613 int desc_index, 3614 u8 param_offset, 3615 u8 *param_read_buf, 3616 u8 param_size) 3617 { 3618 int ret; 3619 u8 *desc_buf; 3620 int buff_len = QUERY_DESC_MAX_SIZE; 3621 bool is_kmalloc = true; 3622 3623 /* Safety check */ 3624 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3625 return -EINVAL; 3626 3627 /* Check whether we need temp memory */ 3628 if (param_offset != 0 || param_size < buff_len) { 3629 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3630 if (!desc_buf) 3631 return -ENOMEM; 3632 } else { 3633 desc_buf = param_read_buf; 3634 is_kmalloc = false; 3635 } 3636 3637 /* Request for full descriptor */ 3638 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3639 desc_id, desc_index, 0, 3640 desc_buf, &buff_len); 3641 if (ret) { 3642 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3643 __func__, desc_id, desc_index, param_offset, ret); 3644 goto out; 3645 } 3646 3647 /* Update descriptor length */ 3648 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3649 3650 if (param_offset >= buff_len) { 3651 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3652 __func__, param_offset, desc_id, buff_len); 3653 ret = -EINVAL; 3654 goto out; 3655 } 3656 3657 /* Sanity check */ 3658 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3659 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3660 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3661 ret = -EINVAL; 3662 goto out; 3663 } 3664 3665 if (is_kmalloc) { 3666 /* Make sure we don't copy more data than available */ 3667 if (param_offset >= buff_len) 3668 ret = -EINVAL; 3669 else 3670 memcpy(param_read_buf, &desc_buf[param_offset], 3671 min_t(u32, param_size, buff_len - param_offset)); 3672 } 3673 out: 3674 if (is_kmalloc) 3675 kfree(desc_buf); 3676 return ret; 3677 } 3678 3679 /** 3680 * struct uc_string_id - unicode string 3681 * 3682 * @len: size of this descriptor inclusive 3683 * @type: descriptor type 3684 * @uc: unicode string character 3685 */ 3686 struct uc_string_id { 3687 u8 len; 3688 u8 type; 3689 wchar_t uc[]; 3690 } __packed; 3691 3692 /* replace non-printable or non-ASCII characters with spaces */ 3693 static inline char ufshcd_remove_non_printable(u8 ch) 3694 { 3695 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3696 } 3697 3698 /** 3699 * ufshcd_read_string_desc - read string descriptor 3700 * @hba: pointer to adapter instance 3701 * @desc_index: descriptor index 3702 * @buf: pointer to buffer where descriptor would be read, 3703 * the caller should free the memory. 3704 * @ascii: if true convert from unicode to ascii characters 3705 * null terminated string. 3706 * 3707 * Return: 3708 * * string size on success. 3709 * * -ENOMEM: on allocation failure 3710 * * -EINVAL: on a wrong parameter 3711 */ 3712 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3713 u8 **buf, bool ascii) 3714 { 3715 struct uc_string_id *uc_str; 3716 u8 *str; 3717 int ret; 3718 3719 if (!buf) 3720 return -EINVAL; 3721 3722 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3723 if (!uc_str) 3724 return -ENOMEM; 3725 3726 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3727 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3728 if (ret < 0) { 3729 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3730 QUERY_REQ_RETRIES, ret); 3731 str = NULL; 3732 goto out; 3733 } 3734 3735 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3736 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3737 str = NULL; 3738 ret = 0; 3739 goto out; 3740 } 3741 3742 if (ascii) { 3743 ssize_t ascii_len; 3744 int i; 3745 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3746 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3747 str = kzalloc(ascii_len, GFP_KERNEL); 3748 if (!str) { 3749 ret = -ENOMEM; 3750 goto out; 3751 } 3752 3753 /* 3754 * the descriptor contains string in UTF16 format 3755 * we need to convert to utf-8 so it can be displayed 3756 */ 3757 ret = utf16s_to_utf8s(uc_str->uc, 3758 uc_str->len - QUERY_DESC_HDR_SIZE, 3759 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3760 3761 /* replace non-printable or non-ASCII characters with spaces */ 3762 for (i = 0; i < ret; i++) 3763 str[i] = ufshcd_remove_non_printable(str[i]); 3764 3765 str[ret++] = '\0'; 3766 3767 } else { 3768 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3769 if (!str) { 3770 ret = -ENOMEM; 3771 goto out; 3772 } 3773 ret = uc_str->len; 3774 } 3775 out: 3776 *buf = str; 3777 kfree(uc_str); 3778 return ret; 3779 } 3780 3781 /** 3782 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3783 * @hba: Pointer to adapter instance 3784 * @lun: lun id 3785 * @param_offset: offset of the parameter to read 3786 * @param_read_buf: pointer to buffer where parameter would be read 3787 * @param_size: sizeof(param_read_buf) 3788 * 3789 * Return: 0 in case of success, non-zero otherwise. 3790 */ 3791 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3792 int lun, 3793 enum unit_desc_param param_offset, 3794 u8 *param_read_buf, 3795 u32 param_size) 3796 { 3797 /* 3798 * Unit descriptors are only available for general purpose LUs (LUN id 3799 * from 0 to 7) and RPMB Well known LU. 3800 */ 3801 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3802 return -EOPNOTSUPP; 3803 3804 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3805 param_offset, param_read_buf, param_size); 3806 } 3807 3808 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3809 { 3810 int err = 0; 3811 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3812 3813 if (hba->dev_info.wspecversion >= 0x300) { 3814 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3815 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3816 &gating_wait); 3817 if (err) 3818 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3819 err, gating_wait); 3820 3821 if (gating_wait == 0) { 3822 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3823 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3824 gating_wait); 3825 } 3826 3827 hba->dev_info.clk_gating_wait_us = gating_wait; 3828 } 3829 3830 return err; 3831 } 3832 3833 /** 3834 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3835 * @hba: per adapter instance 3836 * 3837 * 1. Allocate DMA memory for Command Descriptor array 3838 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3839 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3840 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3841 * (UTMRDL) 3842 * 4. Allocate memory for local reference block(lrb). 3843 * 3844 * Return: 0 for success, non-zero in case of failure. 3845 */ 3846 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3847 { 3848 size_t utmrdl_size, utrdl_size, ucdl_size; 3849 3850 /* Allocate memory for UTP command descriptors */ 3851 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3852 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3853 ucdl_size, 3854 &hba->ucdl_dma_addr, 3855 GFP_KERNEL); 3856 3857 /* 3858 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3859 */ 3860 if (!hba->ucdl_base_addr || 3861 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3862 dev_err(hba->dev, 3863 "Command Descriptor Memory allocation failed\n"); 3864 goto out; 3865 } 3866 3867 /* 3868 * Allocate memory for UTP Transfer descriptors 3869 * UFSHCI requires 1KB alignment of UTRD 3870 */ 3871 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3872 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3873 utrdl_size, 3874 &hba->utrdl_dma_addr, 3875 GFP_KERNEL); 3876 if (!hba->utrdl_base_addr || 3877 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3878 dev_err(hba->dev, 3879 "Transfer Descriptor Memory allocation failed\n"); 3880 goto out; 3881 } 3882 3883 /* 3884 * Skip utmrdl allocation; it may have been 3885 * allocated during first pass and not released during 3886 * MCQ memory allocation. 3887 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3888 */ 3889 if (hba->utmrdl_base_addr) 3890 goto skip_utmrdl; 3891 /* 3892 * Allocate memory for UTP Task Management descriptors 3893 * UFSHCI requires 1KB alignment of UTMRD 3894 */ 3895 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3896 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3897 utmrdl_size, 3898 &hba->utmrdl_dma_addr, 3899 GFP_KERNEL); 3900 if (!hba->utmrdl_base_addr || 3901 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3902 dev_err(hba->dev, 3903 "Task Management Descriptor Memory allocation failed\n"); 3904 goto out; 3905 } 3906 3907 skip_utmrdl: 3908 /* Allocate memory for local reference block */ 3909 hba->lrb = devm_kcalloc(hba->dev, 3910 hba->nutrs, sizeof(struct ufshcd_lrb), 3911 GFP_KERNEL); 3912 if (!hba->lrb) { 3913 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3914 goto out; 3915 } 3916 return 0; 3917 out: 3918 return -ENOMEM; 3919 } 3920 3921 /** 3922 * ufshcd_host_memory_configure - configure local reference block with 3923 * memory offsets 3924 * @hba: per adapter instance 3925 * 3926 * Configure Host memory space 3927 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3928 * address. 3929 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3930 * and PRDT offset. 3931 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3932 * into local reference block. 3933 */ 3934 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3935 { 3936 struct utp_transfer_req_desc *utrdlp; 3937 dma_addr_t cmd_desc_dma_addr; 3938 dma_addr_t cmd_desc_element_addr; 3939 u16 response_offset; 3940 u16 prdt_offset; 3941 int cmd_desc_size; 3942 int i; 3943 3944 utrdlp = hba->utrdl_base_addr; 3945 3946 response_offset = 3947 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3948 prdt_offset = 3949 offsetof(struct utp_transfer_cmd_desc, prd_table); 3950 3951 cmd_desc_size = ufshcd_get_ucd_size(hba); 3952 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3953 3954 for (i = 0; i < hba->nutrs; i++) { 3955 /* Configure UTRD with command descriptor base address */ 3956 cmd_desc_element_addr = 3957 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3958 utrdlp[i].command_desc_base_addr = 3959 cpu_to_le64(cmd_desc_element_addr); 3960 3961 /* Response upiu and prdt offset should be in double words */ 3962 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3963 utrdlp[i].response_upiu_offset = 3964 cpu_to_le16(response_offset); 3965 utrdlp[i].prd_table_offset = 3966 cpu_to_le16(prdt_offset); 3967 utrdlp[i].response_upiu_length = 3968 cpu_to_le16(ALIGNED_UPIU_SIZE); 3969 } else { 3970 utrdlp[i].response_upiu_offset = 3971 cpu_to_le16(response_offset >> 2); 3972 utrdlp[i].prd_table_offset = 3973 cpu_to_le16(prdt_offset >> 2); 3974 utrdlp[i].response_upiu_length = 3975 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 3976 } 3977 3978 ufshcd_init_lrb(hba, &hba->lrb[i], i); 3979 } 3980 } 3981 3982 /** 3983 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 3984 * @hba: per adapter instance 3985 * 3986 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 3987 * in order to initialize the Unipro link startup procedure. 3988 * Once the Unipro links are up, the device connected to the controller 3989 * is detected. 3990 * 3991 * Return: 0 on success, non-zero value on failure. 3992 */ 3993 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 3994 { 3995 struct uic_command uic_cmd = { 3996 .command = UIC_CMD_DME_LINK_STARTUP, 3997 }; 3998 int ret; 3999 4000 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4001 if (ret) 4002 dev_dbg(hba->dev, 4003 "dme-link-startup: error code %d\n", ret); 4004 return ret; 4005 } 4006 /** 4007 * ufshcd_dme_reset - UIC command for DME_RESET 4008 * @hba: per adapter instance 4009 * 4010 * DME_RESET command is issued in order to reset UniPro stack. 4011 * This function now deals with cold reset. 4012 * 4013 * Return: 0 on success, non-zero value on failure. 4014 */ 4015 static int ufshcd_dme_reset(struct ufs_hba *hba) 4016 { 4017 struct uic_command uic_cmd = { 4018 .command = UIC_CMD_DME_RESET, 4019 }; 4020 int ret; 4021 4022 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4023 if (ret) 4024 dev_err(hba->dev, 4025 "dme-reset: error code %d\n", ret); 4026 4027 return ret; 4028 } 4029 4030 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 4031 int agreed_gear, 4032 int adapt_val) 4033 { 4034 int ret; 4035 4036 if (agreed_gear < UFS_HS_G4) 4037 adapt_val = PA_NO_ADAPT; 4038 4039 ret = ufshcd_dme_set(hba, 4040 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 4041 adapt_val); 4042 return ret; 4043 } 4044 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 4045 4046 /** 4047 * ufshcd_dme_enable - UIC command for DME_ENABLE 4048 * @hba: per adapter instance 4049 * 4050 * DME_ENABLE command is issued in order to enable UniPro stack. 4051 * 4052 * Return: 0 on success, non-zero value on failure. 4053 */ 4054 static int ufshcd_dme_enable(struct ufs_hba *hba) 4055 { 4056 struct uic_command uic_cmd = { 4057 .command = UIC_CMD_DME_ENABLE, 4058 }; 4059 int ret; 4060 4061 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4062 if (ret) 4063 dev_err(hba->dev, 4064 "dme-enable: error code %d\n", ret); 4065 4066 return ret; 4067 } 4068 4069 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 4070 { 4071 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 4072 unsigned long min_sleep_time_us; 4073 4074 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 4075 return; 4076 4077 /* 4078 * last_dme_cmd_tstamp will be 0 only for 1st call to 4079 * this function 4080 */ 4081 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 4082 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 4083 } else { 4084 unsigned long delta = 4085 (unsigned long) ktime_to_us( 4086 ktime_sub(ktime_get(), 4087 hba->last_dme_cmd_tstamp)); 4088 4089 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 4090 min_sleep_time_us = 4091 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 4092 else 4093 return; /* no more delay required */ 4094 } 4095 4096 /* allow sleep for extra 50us if needed */ 4097 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 4098 } 4099 4100 /** 4101 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 4102 * @hba: per adapter instance 4103 * @attr_sel: uic command argument1 4104 * @attr_set: attribute set type as uic command argument2 4105 * @mib_val: setting value as uic command argument3 4106 * @peer: indicate whether peer or local 4107 * 4108 * Return: 0 on success, non-zero value on failure. 4109 */ 4110 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 4111 u8 attr_set, u32 mib_val, u8 peer) 4112 { 4113 struct uic_command uic_cmd = { 4114 .command = peer ? UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET, 4115 .argument1 = attr_sel, 4116 .argument2 = UIC_ARG_ATTR_TYPE(attr_set), 4117 .argument3 = mib_val, 4118 }; 4119 static const char *const action[] = { 4120 "dme-set", 4121 "dme-peer-set" 4122 }; 4123 const char *set = action[!!peer]; 4124 int ret; 4125 int retries = UFS_UIC_COMMAND_RETRIES; 4126 4127 do { 4128 /* for peer attributes we retry upon failure */ 4129 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4130 if (ret) 4131 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4132 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4133 } while (ret && peer && --retries); 4134 4135 if (ret) 4136 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4137 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4138 UFS_UIC_COMMAND_RETRIES - retries); 4139 4140 return ret; 4141 } 4142 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4143 4144 /** 4145 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4146 * @hba: per adapter instance 4147 * @attr_sel: uic command argument1 4148 * @mib_val: the value of the attribute as returned by the UIC command 4149 * @peer: indicate whether peer or local 4150 * 4151 * Return: 0 on success, non-zero value on failure. 4152 */ 4153 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4154 u32 *mib_val, u8 peer) 4155 { 4156 struct uic_command uic_cmd = { 4157 .command = peer ? UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET, 4158 .argument1 = attr_sel, 4159 }; 4160 static const char *const action[] = { 4161 "dme-get", 4162 "dme-peer-get" 4163 }; 4164 const char *get = action[!!peer]; 4165 int ret; 4166 int retries = UFS_UIC_COMMAND_RETRIES; 4167 struct ufs_pa_layer_attr orig_pwr_info; 4168 struct ufs_pa_layer_attr temp_pwr_info; 4169 bool pwr_mode_change = false; 4170 4171 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4172 orig_pwr_info = hba->pwr_info; 4173 temp_pwr_info = orig_pwr_info; 4174 4175 if (orig_pwr_info.pwr_tx == FAST_MODE || 4176 orig_pwr_info.pwr_rx == FAST_MODE) { 4177 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4178 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4179 pwr_mode_change = true; 4180 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4181 orig_pwr_info.pwr_rx == SLOW_MODE) { 4182 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4183 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4184 pwr_mode_change = true; 4185 } 4186 if (pwr_mode_change) { 4187 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4188 if (ret) 4189 goto out; 4190 } 4191 } 4192 4193 do { 4194 /* for peer attributes we retry upon failure */ 4195 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4196 if (ret) 4197 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4198 get, UIC_GET_ATTR_ID(attr_sel), ret); 4199 } while (ret && peer && --retries); 4200 4201 if (ret) 4202 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4203 get, UIC_GET_ATTR_ID(attr_sel), 4204 UFS_UIC_COMMAND_RETRIES - retries); 4205 4206 if (mib_val && !ret) 4207 *mib_val = uic_cmd.argument3; 4208 4209 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4210 && pwr_mode_change) 4211 ufshcd_change_power_mode(hba, &orig_pwr_info); 4212 out: 4213 return ret; 4214 } 4215 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4216 4217 /** 4218 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4219 * state) and waits for it to take effect. 4220 * 4221 * @hba: per adapter instance 4222 * @cmd: UIC command to execute 4223 * 4224 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4225 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4226 * and device UniPro link and hence it's final completion would be indicated by 4227 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4228 * addition to normal UIC command completion Status (UCCS). This function only 4229 * returns after the relevant status bits indicate the completion. 4230 * 4231 * Return: 0 on success, non-zero value on failure. 4232 */ 4233 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4234 { 4235 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4236 unsigned long flags; 4237 u8 status; 4238 int ret; 4239 bool reenable_intr = false; 4240 4241 mutex_lock(&hba->uic_cmd_mutex); 4242 ufshcd_add_delay_before_dme_cmd(hba); 4243 4244 spin_lock_irqsave(hba->host->host_lock, flags); 4245 if (ufshcd_is_link_broken(hba)) { 4246 ret = -ENOLINK; 4247 goto out_unlock; 4248 } 4249 hba->uic_async_done = &uic_async_done; 4250 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4251 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4252 /* 4253 * Make sure UIC command completion interrupt is disabled before 4254 * issuing UIC command. 4255 */ 4256 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 4257 reenable_intr = true; 4258 } 4259 spin_unlock_irqrestore(hba->host->host_lock, flags); 4260 ret = __ufshcd_send_uic_cmd(hba, cmd, false); 4261 if (ret) { 4262 dev_err(hba->dev, 4263 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4264 cmd->command, cmd->argument3, ret); 4265 goto out; 4266 } 4267 4268 if (!wait_for_completion_timeout(hba->uic_async_done, 4269 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 4270 dev_err(hba->dev, 4271 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4272 cmd->command, cmd->argument3); 4273 4274 if (!cmd->cmd_active) { 4275 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4276 __func__); 4277 goto check_upmcrs; 4278 } 4279 4280 ret = -ETIMEDOUT; 4281 goto out; 4282 } 4283 4284 check_upmcrs: 4285 status = ufshcd_get_upmcrs(hba); 4286 if (status != PWR_LOCAL) { 4287 dev_err(hba->dev, 4288 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4289 cmd->command, status); 4290 ret = (status != PWR_OK) ? status : -1; 4291 } 4292 out: 4293 if (ret) { 4294 ufshcd_print_host_state(hba); 4295 ufshcd_print_pwr_info(hba); 4296 ufshcd_print_evt_hist(hba); 4297 } 4298 4299 spin_lock_irqsave(hba->host->host_lock, flags); 4300 hba->active_uic_cmd = NULL; 4301 hba->uic_async_done = NULL; 4302 if (reenable_intr) 4303 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4304 if (ret) { 4305 ufshcd_set_link_broken(hba); 4306 ufshcd_schedule_eh_work(hba); 4307 } 4308 out_unlock: 4309 spin_unlock_irqrestore(hba->host->host_lock, flags); 4310 mutex_unlock(&hba->uic_cmd_mutex); 4311 4312 return ret; 4313 } 4314 4315 /** 4316 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4317 * using DME_SET primitives. 4318 * @hba: per adapter instance 4319 * @mode: powr mode value 4320 * 4321 * Return: 0 on success, non-zero value on failure. 4322 */ 4323 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4324 { 4325 struct uic_command uic_cmd = { 4326 .command = UIC_CMD_DME_SET, 4327 .argument1 = UIC_ARG_MIB(PA_PWRMODE), 4328 .argument3 = mode, 4329 }; 4330 int ret; 4331 4332 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4333 ret = ufshcd_dme_set(hba, 4334 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4335 if (ret) { 4336 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4337 __func__, ret); 4338 goto out; 4339 } 4340 } 4341 4342 ufshcd_hold(hba); 4343 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4344 ufshcd_release(hba); 4345 4346 out: 4347 return ret; 4348 } 4349 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4350 4351 int ufshcd_link_recovery(struct ufs_hba *hba) 4352 { 4353 int ret; 4354 unsigned long flags; 4355 4356 spin_lock_irqsave(hba->host->host_lock, flags); 4357 hba->ufshcd_state = UFSHCD_STATE_RESET; 4358 ufshcd_set_eh_in_progress(hba); 4359 spin_unlock_irqrestore(hba->host->host_lock, flags); 4360 4361 /* Reset the attached device */ 4362 ufshcd_device_reset(hba); 4363 4364 ret = ufshcd_host_reset_and_restore(hba); 4365 4366 spin_lock_irqsave(hba->host->host_lock, flags); 4367 if (ret) 4368 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4369 ufshcd_clear_eh_in_progress(hba); 4370 spin_unlock_irqrestore(hba->host->host_lock, flags); 4371 4372 if (ret) 4373 dev_err(hba->dev, "%s: link recovery failed, err %d", 4374 __func__, ret); 4375 4376 return ret; 4377 } 4378 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4379 4380 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4381 { 4382 struct uic_command uic_cmd = { 4383 .command = UIC_CMD_DME_HIBER_ENTER, 4384 }; 4385 ktime_t start = ktime_get(); 4386 int ret; 4387 4388 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4389 4390 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4391 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4392 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4393 4394 if (ret) 4395 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4396 __func__, ret); 4397 else 4398 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4399 POST_CHANGE); 4400 4401 return ret; 4402 } 4403 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4404 4405 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4406 { 4407 struct uic_command uic_cmd = { 4408 .command = UIC_CMD_DME_HIBER_EXIT, 4409 }; 4410 int ret; 4411 ktime_t start = ktime_get(); 4412 4413 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4414 4415 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4416 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4417 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4418 4419 if (ret) { 4420 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4421 __func__, ret); 4422 } else { 4423 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4424 POST_CHANGE); 4425 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4426 hba->ufs_stats.hibern8_exit_cnt++; 4427 } 4428 4429 return ret; 4430 } 4431 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4432 4433 static void ufshcd_configure_auto_hibern8(struct ufs_hba *hba) 4434 { 4435 if (!ufshcd_is_auto_hibern8_supported(hba)) 4436 return; 4437 4438 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4439 } 4440 4441 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4442 { 4443 const u32 cur_ahit = READ_ONCE(hba->ahit); 4444 4445 if (!ufshcd_is_auto_hibern8_supported(hba) || cur_ahit == ahit) 4446 return; 4447 4448 WRITE_ONCE(hba->ahit, ahit); 4449 if (!pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4450 ufshcd_rpm_get_sync(hba); 4451 ufshcd_hold(hba); 4452 ufshcd_configure_auto_hibern8(hba); 4453 ufshcd_release(hba); 4454 ufshcd_rpm_put_sync(hba); 4455 } 4456 } 4457 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4458 4459 /** 4460 * ufshcd_init_pwr_info - setting the POR (power on reset) 4461 * values in hba power info 4462 * @hba: per-adapter instance 4463 */ 4464 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4465 { 4466 hba->pwr_info.gear_rx = UFS_PWM_G1; 4467 hba->pwr_info.gear_tx = UFS_PWM_G1; 4468 hba->pwr_info.lane_rx = UFS_LANE_1; 4469 hba->pwr_info.lane_tx = UFS_LANE_1; 4470 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4471 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4472 hba->pwr_info.hs_rate = 0; 4473 } 4474 4475 /** 4476 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4477 * @hba: per-adapter instance 4478 * 4479 * Return: 0 upon success; < 0 upon failure. 4480 */ 4481 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4482 { 4483 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4484 4485 if (hba->max_pwr_info.is_valid) 4486 return 0; 4487 4488 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4489 pwr_info->pwr_tx = FASTAUTO_MODE; 4490 pwr_info->pwr_rx = FASTAUTO_MODE; 4491 } else { 4492 pwr_info->pwr_tx = FAST_MODE; 4493 pwr_info->pwr_rx = FAST_MODE; 4494 } 4495 pwr_info->hs_rate = PA_HS_MODE_B; 4496 4497 /* Get the connected lane count */ 4498 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4499 &pwr_info->lane_rx); 4500 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4501 &pwr_info->lane_tx); 4502 4503 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4504 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4505 __func__, 4506 pwr_info->lane_rx, 4507 pwr_info->lane_tx); 4508 return -EINVAL; 4509 } 4510 4511 /* 4512 * First, get the maximum gears of HS speed. 4513 * If a zero value, it means there is no HSGEAR capability. 4514 * Then, get the maximum gears of PWM speed. 4515 */ 4516 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4517 if (!pwr_info->gear_rx) { 4518 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4519 &pwr_info->gear_rx); 4520 if (!pwr_info->gear_rx) { 4521 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4522 __func__, pwr_info->gear_rx); 4523 return -EINVAL; 4524 } 4525 pwr_info->pwr_rx = SLOW_MODE; 4526 } 4527 4528 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4529 &pwr_info->gear_tx); 4530 if (!pwr_info->gear_tx) { 4531 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4532 &pwr_info->gear_tx); 4533 if (!pwr_info->gear_tx) { 4534 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4535 __func__, pwr_info->gear_tx); 4536 return -EINVAL; 4537 } 4538 pwr_info->pwr_tx = SLOW_MODE; 4539 } 4540 4541 hba->max_pwr_info.is_valid = true; 4542 return 0; 4543 } 4544 4545 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4546 struct ufs_pa_layer_attr *pwr_mode) 4547 { 4548 int ret; 4549 4550 /* if already configured to the requested pwr_mode */ 4551 if (!hba->force_pmc && 4552 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4553 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4554 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4555 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4556 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4557 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4558 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4559 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4560 return 0; 4561 } 4562 4563 /* 4564 * Configure attributes for power mode change with below. 4565 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4566 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4567 * - PA_HSSERIES 4568 */ 4569 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4570 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4571 pwr_mode->lane_rx); 4572 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4573 pwr_mode->pwr_rx == FAST_MODE) 4574 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4575 else 4576 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4577 4578 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4579 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4580 pwr_mode->lane_tx); 4581 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4582 pwr_mode->pwr_tx == FAST_MODE) 4583 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4584 else 4585 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4586 4587 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4588 pwr_mode->pwr_tx == FASTAUTO_MODE || 4589 pwr_mode->pwr_rx == FAST_MODE || 4590 pwr_mode->pwr_tx == FAST_MODE) 4591 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4592 pwr_mode->hs_rate); 4593 4594 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4595 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4596 DL_FC0ProtectionTimeOutVal_Default); 4597 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4598 DL_TC0ReplayTimeOutVal_Default); 4599 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4600 DL_AFC0ReqTimeOutVal_Default); 4601 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4602 DL_FC1ProtectionTimeOutVal_Default); 4603 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4604 DL_TC1ReplayTimeOutVal_Default); 4605 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4606 DL_AFC1ReqTimeOutVal_Default); 4607 4608 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4609 DL_FC0ProtectionTimeOutVal_Default); 4610 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4611 DL_TC0ReplayTimeOutVal_Default); 4612 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4613 DL_AFC0ReqTimeOutVal_Default); 4614 } 4615 4616 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4617 | pwr_mode->pwr_tx); 4618 4619 if (ret) { 4620 dev_err(hba->dev, 4621 "%s: power mode change failed %d\n", __func__, ret); 4622 } else { 4623 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4624 pwr_mode); 4625 4626 memcpy(&hba->pwr_info, pwr_mode, 4627 sizeof(struct ufs_pa_layer_attr)); 4628 } 4629 4630 return ret; 4631 } 4632 4633 /** 4634 * ufshcd_config_pwr_mode - configure a new power mode 4635 * @hba: per-adapter instance 4636 * @desired_pwr_mode: desired power configuration 4637 * 4638 * Return: 0 upon success; < 0 upon failure. 4639 */ 4640 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4641 struct ufs_pa_layer_attr *desired_pwr_mode) 4642 { 4643 struct ufs_pa_layer_attr final_params = { 0 }; 4644 int ret; 4645 4646 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4647 desired_pwr_mode, &final_params); 4648 4649 if (ret) 4650 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4651 4652 ret = ufshcd_change_power_mode(hba, &final_params); 4653 4654 return ret; 4655 } 4656 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4657 4658 /** 4659 * ufshcd_complete_dev_init() - checks device readiness 4660 * @hba: per-adapter instance 4661 * 4662 * Set fDeviceInit flag and poll until device toggles it. 4663 * 4664 * Return: 0 upon success; < 0 upon failure. 4665 */ 4666 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4667 { 4668 int err; 4669 bool flag_res = true; 4670 ktime_t timeout; 4671 4672 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4673 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4674 if (err) { 4675 dev_err(hba->dev, 4676 "%s: setting fDeviceInit flag failed with error %d\n", 4677 __func__, err); 4678 goto out; 4679 } 4680 4681 /* Poll fDeviceInit flag to be cleared */ 4682 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4683 do { 4684 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4685 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4686 if (!flag_res) 4687 break; 4688 usleep_range(500, 1000); 4689 } while (ktime_before(ktime_get(), timeout)); 4690 4691 if (err) { 4692 dev_err(hba->dev, 4693 "%s: reading fDeviceInit flag failed with error %d\n", 4694 __func__, err); 4695 } else if (flag_res) { 4696 dev_err(hba->dev, 4697 "%s: fDeviceInit was not cleared by the device\n", 4698 __func__); 4699 err = -EBUSY; 4700 } 4701 out: 4702 return err; 4703 } 4704 4705 /** 4706 * ufshcd_make_hba_operational - Make UFS controller operational 4707 * @hba: per adapter instance 4708 * 4709 * To bring UFS host controller to operational state, 4710 * 1. Enable required interrupts 4711 * 2. Configure interrupt aggregation 4712 * 3. Program UTRL and UTMRL base address 4713 * 4. Configure run-stop-registers 4714 * 4715 * Return: 0 on success, non-zero value on failure. 4716 */ 4717 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4718 { 4719 int err = 0; 4720 u32 reg; 4721 4722 /* Enable required interrupts */ 4723 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4724 4725 /* Configure interrupt aggregation */ 4726 if (ufshcd_is_intr_aggr_allowed(hba)) 4727 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4728 else 4729 ufshcd_disable_intr_aggr(hba); 4730 4731 /* Configure UTRL and UTMRL base address registers */ 4732 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4733 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4734 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4735 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4736 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4737 REG_UTP_TASK_REQ_LIST_BASE_L); 4738 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4739 REG_UTP_TASK_REQ_LIST_BASE_H); 4740 4741 /* 4742 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4743 */ 4744 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4745 if (!(ufshcd_get_lists_status(reg))) { 4746 ufshcd_enable_run_stop_reg(hba); 4747 } else { 4748 dev_err(hba->dev, 4749 "Host controller not ready to process requests"); 4750 err = -EIO; 4751 } 4752 4753 return err; 4754 } 4755 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4756 4757 /** 4758 * ufshcd_hba_stop - Send controller to reset state 4759 * @hba: per adapter instance 4760 */ 4761 void ufshcd_hba_stop(struct ufs_hba *hba) 4762 { 4763 unsigned long flags; 4764 int err; 4765 4766 /* 4767 * Obtain the host lock to prevent that the controller is disabled 4768 * while the UFS interrupt handler is active on another CPU. 4769 */ 4770 spin_lock_irqsave(hba->host->host_lock, flags); 4771 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4772 spin_unlock_irqrestore(hba->host->host_lock, flags); 4773 4774 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4775 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4776 10, 1); 4777 if (err) 4778 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4779 } 4780 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4781 4782 /** 4783 * ufshcd_hba_execute_hce - initialize the controller 4784 * @hba: per adapter instance 4785 * 4786 * The controller resets itself and controller firmware initialization 4787 * sequence kicks off. When controller is ready it will set 4788 * the Host Controller Enable bit to 1. 4789 * 4790 * Return: 0 on success, non-zero value on failure. 4791 */ 4792 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4793 { 4794 int retry_outer = 3; 4795 int retry_inner; 4796 4797 start: 4798 if (ufshcd_is_hba_active(hba)) 4799 /* change controller state to "reset state" */ 4800 ufshcd_hba_stop(hba); 4801 4802 /* UniPro link is disabled at this point */ 4803 ufshcd_set_link_off(hba); 4804 4805 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4806 4807 /* start controller initialization sequence */ 4808 ufshcd_hba_start(hba); 4809 4810 /* 4811 * To initialize a UFS host controller HCE bit must be set to 1. 4812 * During initialization the HCE bit value changes from 1->0->1. 4813 * When the host controller completes initialization sequence 4814 * it sets the value of HCE bit to 1. The same HCE bit is read back 4815 * to check if the controller has completed initialization sequence. 4816 * So without this delay the value HCE = 1, set in the previous 4817 * instruction might be read back. 4818 * This delay can be changed based on the controller. 4819 */ 4820 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4821 4822 /* wait for the host controller to complete initialization */ 4823 retry_inner = 50; 4824 while (!ufshcd_is_hba_active(hba)) { 4825 if (retry_inner) { 4826 retry_inner--; 4827 } else { 4828 dev_err(hba->dev, 4829 "Controller enable failed\n"); 4830 if (retry_outer) { 4831 retry_outer--; 4832 goto start; 4833 } 4834 return -EIO; 4835 } 4836 usleep_range(1000, 1100); 4837 } 4838 4839 /* enable UIC related interrupts */ 4840 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4841 4842 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4843 4844 return 0; 4845 } 4846 4847 int ufshcd_hba_enable(struct ufs_hba *hba) 4848 { 4849 int ret; 4850 4851 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4852 ufshcd_set_link_off(hba); 4853 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4854 4855 /* enable UIC related interrupts */ 4856 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4857 ret = ufshcd_dme_reset(hba); 4858 if (ret) { 4859 dev_err(hba->dev, "DME_RESET failed\n"); 4860 return ret; 4861 } 4862 4863 ret = ufshcd_dme_enable(hba); 4864 if (ret) { 4865 dev_err(hba->dev, "Enabling DME failed\n"); 4866 return ret; 4867 } 4868 4869 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4870 } else { 4871 ret = ufshcd_hba_execute_hce(hba); 4872 } 4873 4874 return ret; 4875 } 4876 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4877 4878 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4879 { 4880 int tx_lanes = 0, i, err = 0; 4881 4882 if (!peer) 4883 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4884 &tx_lanes); 4885 else 4886 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4887 &tx_lanes); 4888 for (i = 0; i < tx_lanes; i++) { 4889 if (!peer) 4890 err = ufshcd_dme_set(hba, 4891 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4892 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4893 0); 4894 else 4895 err = ufshcd_dme_peer_set(hba, 4896 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4897 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4898 0); 4899 if (err) { 4900 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4901 __func__, peer, i, err); 4902 break; 4903 } 4904 } 4905 4906 return err; 4907 } 4908 4909 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4910 { 4911 return ufshcd_disable_tx_lcc(hba, true); 4912 } 4913 4914 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4915 { 4916 struct ufs_event_hist *e; 4917 4918 if (id >= UFS_EVT_CNT) 4919 return; 4920 4921 e = &hba->ufs_stats.event[id]; 4922 e->val[e->pos] = val; 4923 e->tstamp[e->pos] = local_clock(); 4924 e->cnt += 1; 4925 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4926 4927 ufshcd_vops_event_notify(hba, id, &val); 4928 } 4929 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4930 4931 /** 4932 * ufshcd_link_startup - Initialize unipro link startup 4933 * @hba: per adapter instance 4934 * 4935 * Return: 0 for success, non-zero in case of failure. 4936 */ 4937 static int ufshcd_link_startup(struct ufs_hba *hba) 4938 { 4939 int ret; 4940 int retries = DME_LINKSTARTUP_RETRIES; 4941 bool link_startup_again = false; 4942 4943 /* 4944 * If UFS device isn't active then we will have to issue link startup 4945 * 2 times to make sure the device state move to active. 4946 */ 4947 if (!ufshcd_is_ufs_dev_active(hba)) 4948 link_startup_again = true; 4949 4950 link_startup: 4951 do { 4952 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4953 4954 ret = ufshcd_dme_link_startup(hba); 4955 4956 /* check if device is detected by inter-connect layer */ 4957 if (!ret && !ufshcd_is_device_present(hba)) { 4958 ufshcd_update_evt_hist(hba, 4959 UFS_EVT_LINK_STARTUP_FAIL, 4960 0); 4961 dev_err(hba->dev, "%s: Device not present\n", __func__); 4962 ret = -ENXIO; 4963 goto out; 4964 } 4965 4966 /* 4967 * DME link lost indication is only received when link is up, 4968 * but we can't be sure if the link is up until link startup 4969 * succeeds. So reset the local Uni-Pro and try again. 4970 */ 4971 if (ret && retries && ufshcd_hba_enable(hba)) { 4972 ufshcd_update_evt_hist(hba, 4973 UFS_EVT_LINK_STARTUP_FAIL, 4974 (u32)ret); 4975 goto out; 4976 } 4977 } while (ret && retries--); 4978 4979 if (ret) { 4980 /* failed to get the link up... retire */ 4981 ufshcd_update_evt_hist(hba, 4982 UFS_EVT_LINK_STARTUP_FAIL, 4983 (u32)ret); 4984 goto out; 4985 } 4986 4987 if (link_startup_again) { 4988 link_startup_again = false; 4989 retries = DME_LINKSTARTUP_RETRIES; 4990 goto link_startup; 4991 } 4992 4993 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 4994 ufshcd_init_pwr_info(hba); 4995 ufshcd_print_pwr_info(hba); 4996 4997 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 4998 ret = ufshcd_disable_device_tx_lcc(hba); 4999 if (ret) 5000 goto out; 5001 } 5002 5003 /* Include any host controller configuration via UIC commands */ 5004 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 5005 if (ret) 5006 goto out; 5007 5008 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 5009 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 5010 ret = ufshcd_make_hba_operational(hba); 5011 out: 5012 if (ret) { 5013 dev_err(hba->dev, "link startup failed %d\n", ret); 5014 ufshcd_print_host_state(hba); 5015 ufshcd_print_pwr_info(hba); 5016 ufshcd_print_evt_hist(hba); 5017 } 5018 return ret; 5019 } 5020 5021 /** 5022 * ufshcd_verify_dev_init() - Verify device initialization 5023 * @hba: per-adapter instance 5024 * 5025 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 5026 * device Transport Protocol (UTP) layer is ready after a reset. 5027 * If the UTP layer at the device side is not initialized, it may 5028 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 5029 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 5030 * 5031 * Return: 0 upon success; < 0 upon failure. 5032 */ 5033 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 5034 { 5035 int err = 0; 5036 int retries; 5037 5038 ufshcd_dev_man_lock(hba); 5039 5040 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 5041 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 5042 hba->nop_out_timeout); 5043 5044 if (!err || err == -ETIMEDOUT) 5045 break; 5046 5047 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 5048 } 5049 5050 ufshcd_dev_man_unlock(hba); 5051 5052 if (err) 5053 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 5054 return err; 5055 } 5056 5057 /** 5058 * ufshcd_setup_links - associate link b/w device wlun and other luns 5059 * @sdev: pointer to SCSI device 5060 * @hba: pointer to ufs hba 5061 */ 5062 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 5063 { 5064 struct device_link *link; 5065 5066 /* 5067 * Device wlun is the supplier & rest of the luns are consumers. 5068 * This ensures that device wlun suspends after all other luns. 5069 */ 5070 if (hba->ufs_device_wlun) { 5071 link = device_link_add(&sdev->sdev_gendev, 5072 &hba->ufs_device_wlun->sdev_gendev, 5073 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 5074 if (!link) { 5075 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 5076 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 5077 return; 5078 } 5079 hba->luns_avail--; 5080 /* Ignore REPORT_LUN wlun probing */ 5081 if (hba->luns_avail == 1) { 5082 ufshcd_rpm_put(hba); 5083 return; 5084 } 5085 } else { 5086 /* 5087 * Device wlun is probed. The assumption is that WLUNs are 5088 * scanned before other LUNs. 5089 */ 5090 hba->luns_avail--; 5091 } 5092 } 5093 5094 /** 5095 * ufshcd_lu_init - Initialize the relevant parameters of the LU 5096 * @hba: per-adapter instance 5097 * @sdev: pointer to SCSI device 5098 */ 5099 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 5100 { 5101 int len = QUERY_DESC_MAX_SIZE; 5102 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 5103 u8 lun_qdepth = hba->nutrs; 5104 u8 *desc_buf; 5105 int ret; 5106 5107 desc_buf = kzalloc(len, GFP_KERNEL); 5108 if (!desc_buf) 5109 goto set_qdepth; 5110 5111 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5112 if (ret < 0) { 5113 if (ret == -EOPNOTSUPP) 5114 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5115 lun_qdepth = 1; 5116 kfree(desc_buf); 5117 goto set_qdepth; 5118 } 5119 5120 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5121 /* 5122 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5123 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5124 */ 5125 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5126 } 5127 /* 5128 * According to UFS device specification, the write protection mode is only supported by 5129 * normal LU, not supported by WLUN. 5130 */ 5131 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5132 !hba->dev_info.is_lu_power_on_wp && 5133 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5134 hba->dev_info.is_lu_power_on_wp = true; 5135 5136 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5137 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5138 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5139 hba->dev_info.b_advanced_rpmb_en = true; 5140 5141 5142 kfree(desc_buf); 5143 set_qdepth: 5144 /* 5145 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5146 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5147 */ 5148 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5149 scsi_change_queue_depth(sdev, lun_qdepth); 5150 } 5151 5152 /** 5153 * ufshcd_slave_alloc - handle initial SCSI device configurations 5154 * @sdev: pointer to SCSI device 5155 * 5156 * Return: success. 5157 */ 5158 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5159 { 5160 struct ufs_hba *hba; 5161 5162 hba = shost_priv(sdev->host); 5163 5164 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5165 sdev->use_10_for_ms = 1; 5166 5167 /* DBD field should be set to 1 in mode sense(10) */ 5168 sdev->set_dbd_for_ms = 1; 5169 5170 /* allow SCSI layer to restart the device in case of errors */ 5171 sdev->allow_restart = 1; 5172 5173 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5174 sdev->no_report_opcodes = 1; 5175 5176 /* WRITE_SAME command is not supported */ 5177 sdev->no_write_same = 1; 5178 5179 ufshcd_lu_init(hba, sdev); 5180 5181 ufshcd_setup_links(hba, sdev); 5182 5183 return 0; 5184 } 5185 5186 /** 5187 * ufshcd_change_queue_depth - change queue depth 5188 * @sdev: pointer to SCSI device 5189 * @depth: required depth to set 5190 * 5191 * Change queue depth and make sure the max. limits are not crossed. 5192 * 5193 * Return: new queue depth. 5194 */ 5195 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5196 { 5197 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5198 } 5199 5200 /** 5201 * ufshcd_device_configure - adjust SCSI device configurations 5202 * @sdev: pointer to SCSI device 5203 * @lim: queue limits 5204 * 5205 * Return: 0 (success). 5206 */ 5207 static int ufshcd_device_configure(struct scsi_device *sdev, 5208 struct queue_limits *lim) 5209 { 5210 struct ufs_hba *hba = shost_priv(sdev->host); 5211 struct request_queue *q = sdev->request_queue; 5212 5213 lim->dma_pad_mask = PRDT_DATA_BYTE_COUNT_PAD - 1; 5214 5215 /* 5216 * Block runtime-pm until all consumers are added. 5217 * Refer ufshcd_setup_links(). 5218 */ 5219 if (is_device_wlun(sdev)) 5220 pm_runtime_get_noresume(&sdev->sdev_gendev); 5221 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5222 sdev->rpm_autosuspend = 1; 5223 /* 5224 * Do not print messages during runtime PM to avoid never-ending cycles 5225 * of messages written back to storage by user space causing runtime 5226 * resume, causing more messages and so on. 5227 */ 5228 sdev->silence_suspend = 1; 5229 5230 ufshcd_crypto_register(hba, q); 5231 5232 return 0; 5233 } 5234 5235 /** 5236 * ufshcd_slave_destroy - remove SCSI device configurations 5237 * @sdev: pointer to SCSI device 5238 */ 5239 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5240 { 5241 struct ufs_hba *hba; 5242 unsigned long flags; 5243 5244 hba = shost_priv(sdev->host); 5245 5246 /* Drop the reference as it won't be needed anymore */ 5247 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5248 spin_lock_irqsave(hba->host->host_lock, flags); 5249 hba->ufs_device_wlun = NULL; 5250 spin_unlock_irqrestore(hba->host->host_lock, flags); 5251 } else if (hba->ufs_device_wlun) { 5252 struct device *supplier = NULL; 5253 5254 /* Ensure UFS Device WLUN exists and does not disappear */ 5255 spin_lock_irqsave(hba->host->host_lock, flags); 5256 if (hba->ufs_device_wlun) { 5257 supplier = &hba->ufs_device_wlun->sdev_gendev; 5258 get_device(supplier); 5259 } 5260 spin_unlock_irqrestore(hba->host->host_lock, flags); 5261 5262 if (supplier) { 5263 /* 5264 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5265 * device will not have been registered but can still 5266 * have a device link holding a reference to the device. 5267 */ 5268 device_link_remove(&sdev->sdev_gendev, supplier); 5269 put_device(supplier); 5270 } 5271 } 5272 } 5273 5274 /** 5275 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5276 * @lrbp: pointer to local reference block of completed command 5277 * @scsi_status: SCSI command status 5278 * 5279 * Return: value base on SCSI command status. 5280 */ 5281 static inline int 5282 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5283 { 5284 int result = 0; 5285 5286 switch (scsi_status) { 5287 case SAM_STAT_CHECK_CONDITION: 5288 ufshcd_copy_sense_data(lrbp); 5289 fallthrough; 5290 case SAM_STAT_GOOD: 5291 result |= DID_OK << 16 | scsi_status; 5292 break; 5293 case SAM_STAT_TASK_SET_FULL: 5294 case SAM_STAT_BUSY: 5295 case SAM_STAT_TASK_ABORTED: 5296 ufshcd_copy_sense_data(lrbp); 5297 result |= scsi_status; 5298 break; 5299 default: 5300 result |= DID_ERROR << 16; 5301 break; 5302 } /* end of switch */ 5303 5304 return result; 5305 } 5306 5307 /** 5308 * ufshcd_transfer_rsp_status - Get overall status of the response 5309 * @hba: per adapter instance 5310 * @lrbp: pointer to local reference block of completed command 5311 * @cqe: pointer to the completion queue entry 5312 * 5313 * Return: result of the command to notify SCSI midlayer. 5314 */ 5315 static inline int 5316 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5317 struct cq_entry *cqe) 5318 { 5319 int result = 0; 5320 int scsi_status; 5321 enum utp_ocs ocs; 5322 u8 upiu_flags; 5323 u32 resid; 5324 5325 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5326 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5327 /* 5328 * Test !overflow instead of underflow to support UFS devices that do 5329 * not set either flag. 5330 */ 5331 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5332 scsi_set_resid(lrbp->cmd, resid); 5333 5334 /* overall command status of utrd */ 5335 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5336 5337 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5338 if (lrbp->ucd_rsp_ptr->header.response || 5339 lrbp->ucd_rsp_ptr->header.status) 5340 ocs = OCS_SUCCESS; 5341 } 5342 5343 switch (ocs) { 5344 case OCS_SUCCESS: 5345 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5346 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5347 case UPIU_TRANSACTION_RESPONSE: 5348 /* 5349 * get the result based on SCSI status response 5350 * to notify the SCSI midlayer of the command status 5351 */ 5352 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5353 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5354 5355 /* 5356 * Currently we are only supporting BKOPs exception 5357 * events hence we can ignore BKOPs exception event 5358 * during power management callbacks. BKOPs exception 5359 * event is not expected to be raised in runtime suspend 5360 * callback as it allows the urgent bkops. 5361 * During system suspend, we are anyway forcefully 5362 * disabling the bkops and if urgent bkops is needed 5363 * it will be enabled on system resume. Long term 5364 * solution could be to abort the system suspend if 5365 * UFS device needs urgent BKOPs. 5366 */ 5367 if (!hba->pm_op_in_progress && 5368 !ufshcd_eh_in_progress(hba) && 5369 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5370 /* Flushed in suspend */ 5371 schedule_work(&hba->eeh_work); 5372 break; 5373 case UPIU_TRANSACTION_REJECT_UPIU: 5374 /* TODO: handle Reject UPIU Response */ 5375 result = DID_ERROR << 16; 5376 dev_err(hba->dev, 5377 "Reject UPIU not fully implemented\n"); 5378 break; 5379 default: 5380 dev_err(hba->dev, 5381 "Unexpected request response code = %x\n", 5382 result); 5383 result = DID_ERROR << 16; 5384 break; 5385 } 5386 break; 5387 case OCS_ABORTED: 5388 result |= DID_ABORT << 16; 5389 break; 5390 case OCS_INVALID_COMMAND_STATUS: 5391 result |= DID_REQUEUE << 16; 5392 break; 5393 case OCS_INVALID_CMD_TABLE_ATTR: 5394 case OCS_INVALID_PRDT_ATTR: 5395 case OCS_MISMATCH_DATA_BUF_SIZE: 5396 case OCS_MISMATCH_RESP_UPIU_SIZE: 5397 case OCS_PEER_COMM_FAILURE: 5398 case OCS_FATAL_ERROR: 5399 case OCS_DEVICE_FATAL_ERROR: 5400 case OCS_INVALID_CRYPTO_CONFIG: 5401 case OCS_GENERAL_CRYPTO_ERROR: 5402 default: 5403 result |= DID_ERROR << 16; 5404 dev_err(hba->dev, 5405 "OCS error from controller = %x for tag %d\n", 5406 ocs, lrbp->task_tag); 5407 ufshcd_print_evt_hist(hba); 5408 ufshcd_print_host_state(hba); 5409 break; 5410 } /* end of switch */ 5411 5412 if ((host_byte(result) != DID_OK) && 5413 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5414 ufshcd_print_tr(hba, lrbp->task_tag, true); 5415 return result; 5416 } 5417 5418 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5419 u32 intr_mask) 5420 { 5421 if (!ufshcd_is_auto_hibern8_supported(hba) || 5422 !ufshcd_is_auto_hibern8_enabled(hba)) 5423 return false; 5424 5425 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5426 return false; 5427 5428 if (hba->active_uic_cmd && 5429 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5430 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5431 return false; 5432 5433 return true; 5434 } 5435 5436 /** 5437 * ufshcd_uic_cmd_compl - handle completion of uic command 5438 * @hba: per adapter instance 5439 * @intr_status: interrupt status generated by the controller 5440 * 5441 * Return: 5442 * IRQ_HANDLED - If interrupt is valid 5443 * IRQ_NONE - If invalid interrupt 5444 */ 5445 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5446 { 5447 irqreturn_t retval = IRQ_NONE; 5448 5449 spin_lock(hba->host->host_lock); 5450 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5451 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5452 5453 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { 5454 hba->active_uic_cmd->argument2 |= 5455 ufshcd_get_uic_cmd_result(hba); 5456 hba->active_uic_cmd->argument3 = 5457 ufshcd_get_dme_attr_val(hba); 5458 if (!hba->uic_async_done) 5459 hba->active_uic_cmd->cmd_active = 0; 5460 complete(&hba->active_uic_cmd->done); 5461 retval = IRQ_HANDLED; 5462 } 5463 5464 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { 5465 hba->active_uic_cmd->cmd_active = 0; 5466 complete(hba->uic_async_done); 5467 retval = IRQ_HANDLED; 5468 } 5469 5470 if (retval == IRQ_HANDLED) 5471 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd, 5472 UFS_CMD_COMP); 5473 spin_unlock(hba->host->host_lock); 5474 return retval; 5475 } 5476 5477 /* Release the resources allocated for processing a SCSI command. */ 5478 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5479 struct ufshcd_lrb *lrbp) 5480 { 5481 struct scsi_cmnd *cmd = lrbp->cmd; 5482 5483 scsi_dma_unmap(cmd); 5484 ufshcd_crypto_clear_prdt(hba, lrbp); 5485 ufshcd_release(hba); 5486 ufshcd_clk_scaling_update_busy(hba); 5487 } 5488 5489 /** 5490 * ufshcd_compl_one_cqe - handle a completion queue entry 5491 * @hba: per adapter instance 5492 * @task_tag: the task tag of the request to be completed 5493 * @cqe: pointer to the completion queue entry 5494 */ 5495 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5496 struct cq_entry *cqe) 5497 { 5498 struct ufshcd_lrb *lrbp; 5499 struct scsi_cmnd *cmd; 5500 enum utp_ocs ocs; 5501 5502 lrbp = &hba->lrb[task_tag]; 5503 lrbp->compl_time_stamp = ktime_get(); 5504 cmd = lrbp->cmd; 5505 if (cmd) { 5506 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5507 ufshcd_update_monitor(hba, lrbp); 5508 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5509 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5510 ufshcd_release_scsi_cmd(hba, lrbp); 5511 /* Do not touch lrbp after scsi done */ 5512 scsi_done(cmd); 5513 } else if (hba->dev_cmd.complete) { 5514 if (cqe) { 5515 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5516 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5517 } 5518 complete(hba->dev_cmd.complete); 5519 } 5520 } 5521 5522 /** 5523 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5524 * @hba: per adapter instance 5525 * @completed_reqs: bitmask that indicates which requests to complete 5526 */ 5527 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5528 unsigned long completed_reqs) 5529 { 5530 int tag; 5531 5532 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5533 ufshcd_compl_one_cqe(hba, tag, NULL); 5534 } 5535 5536 /* Any value that is not an existing queue number is fine for this constant. */ 5537 enum { 5538 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5539 }; 5540 5541 static void ufshcd_clear_polled(struct ufs_hba *hba, 5542 unsigned long *completed_reqs) 5543 { 5544 int tag; 5545 5546 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5547 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5548 5549 if (!cmd) 5550 continue; 5551 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5552 __clear_bit(tag, completed_reqs); 5553 } 5554 } 5555 5556 /* 5557 * Return: > 0 if one or more commands have been completed or 0 if no 5558 * requests have been completed. 5559 */ 5560 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5561 { 5562 struct ufs_hba *hba = shost_priv(shost); 5563 unsigned long completed_reqs, flags; 5564 u32 tr_doorbell; 5565 struct ufs_hw_queue *hwq; 5566 5567 if (hba->mcq_enabled) { 5568 hwq = &hba->uhq[queue_num]; 5569 5570 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5571 } 5572 5573 spin_lock_irqsave(&hba->outstanding_lock, flags); 5574 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5575 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5576 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5577 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5578 hba->outstanding_reqs); 5579 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5580 /* Do not complete polled requests from interrupt context. */ 5581 ufshcd_clear_polled(hba, &completed_reqs); 5582 } 5583 hba->outstanding_reqs &= ~completed_reqs; 5584 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5585 5586 if (completed_reqs) 5587 __ufshcd_transfer_req_compl(hba, completed_reqs); 5588 5589 return completed_reqs != 0; 5590 } 5591 5592 /** 5593 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5594 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5595 * to complete the pending transfers and free the resources associated with 5596 * the scsi command. 5597 * 5598 * @hba: per adapter instance 5599 * @force_compl: This flag is set to true when invoked 5600 * from ufshcd_host_reset_and_restore() in which case it requires special 5601 * handling because the host controller has been reset by ufshcd_hba_stop(). 5602 */ 5603 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5604 bool force_compl) 5605 { 5606 struct ufs_hw_queue *hwq; 5607 struct ufshcd_lrb *lrbp; 5608 struct scsi_cmnd *cmd; 5609 unsigned long flags; 5610 int tag; 5611 5612 for (tag = 0; tag < hba->nutrs; tag++) { 5613 lrbp = &hba->lrb[tag]; 5614 cmd = lrbp->cmd; 5615 if (!ufshcd_cmd_inflight(cmd) || 5616 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5617 continue; 5618 5619 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 5620 5621 if (force_compl) { 5622 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5623 /* 5624 * For those cmds of which the cqes are not present 5625 * in the cq, complete them explicitly. 5626 */ 5627 spin_lock_irqsave(&hwq->cq_lock, flags); 5628 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5629 set_host_byte(cmd, DID_REQUEUE); 5630 ufshcd_release_scsi_cmd(hba, lrbp); 5631 scsi_done(cmd); 5632 } 5633 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5634 } else { 5635 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5636 } 5637 } 5638 } 5639 5640 /** 5641 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5642 * @hba: per adapter instance 5643 * 5644 * Return: 5645 * IRQ_HANDLED - If interrupt is valid 5646 * IRQ_NONE - If invalid interrupt 5647 */ 5648 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5649 { 5650 /* Resetting interrupt aggregation counters first and reading the 5651 * DOOR_BELL afterward allows us to handle all the completed requests. 5652 * In order to prevent other interrupts starvation the DB is read once 5653 * after reset. The down side of this solution is the possibility of 5654 * false interrupt if device completes another request after resetting 5655 * aggregation and before reading the DB. 5656 */ 5657 if (ufshcd_is_intr_aggr_allowed(hba) && 5658 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5659 ufshcd_reset_intr_aggr(hba); 5660 5661 if (ufs_fail_completion(hba)) 5662 return IRQ_HANDLED; 5663 5664 /* 5665 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5666 * do not want polling to trigger spurious interrupt complaints. 5667 */ 5668 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5669 5670 return IRQ_HANDLED; 5671 } 5672 5673 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5674 { 5675 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5676 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5677 &ee_ctrl_mask); 5678 } 5679 5680 int ufshcd_write_ee_control(struct ufs_hba *hba) 5681 { 5682 int err; 5683 5684 mutex_lock(&hba->ee_ctrl_mutex); 5685 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5686 mutex_unlock(&hba->ee_ctrl_mutex); 5687 if (err) 5688 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5689 __func__, err); 5690 return err; 5691 } 5692 5693 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5694 const u16 *other_mask, u16 set, u16 clr) 5695 { 5696 u16 new_mask, ee_ctrl_mask; 5697 int err = 0; 5698 5699 mutex_lock(&hba->ee_ctrl_mutex); 5700 new_mask = (*mask & ~clr) | set; 5701 ee_ctrl_mask = new_mask | *other_mask; 5702 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5703 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5704 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5705 if (!err) { 5706 hba->ee_ctrl_mask = ee_ctrl_mask; 5707 *mask = new_mask; 5708 } 5709 mutex_unlock(&hba->ee_ctrl_mutex); 5710 return err; 5711 } 5712 5713 /** 5714 * ufshcd_disable_ee - disable exception event 5715 * @hba: per-adapter instance 5716 * @mask: exception event to disable 5717 * 5718 * Disables exception event in the device so that the EVENT_ALERT 5719 * bit is not set. 5720 * 5721 * Return: zero on success, non-zero error value on failure. 5722 */ 5723 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5724 { 5725 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5726 } 5727 5728 /** 5729 * ufshcd_enable_ee - enable exception event 5730 * @hba: per-adapter instance 5731 * @mask: exception event to enable 5732 * 5733 * Enable corresponding exception event in the device to allow 5734 * device to alert host in critical scenarios. 5735 * 5736 * Return: zero on success, non-zero error value on failure. 5737 */ 5738 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5739 { 5740 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5741 } 5742 5743 /** 5744 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5745 * @hba: per-adapter instance 5746 * 5747 * Allow device to manage background operations on its own. Enabling 5748 * this might lead to inconsistent latencies during normal data transfers 5749 * as the device is allowed to manage its own way of handling background 5750 * operations. 5751 * 5752 * Return: zero on success, non-zero on failure. 5753 */ 5754 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5755 { 5756 int err = 0; 5757 5758 if (hba->auto_bkops_enabled) 5759 goto out; 5760 5761 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5762 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5763 if (err) { 5764 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5765 __func__, err); 5766 goto out; 5767 } 5768 5769 hba->auto_bkops_enabled = true; 5770 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5771 5772 /* No need of URGENT_BKOPS exception from the device */ 5773 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5774 if (err) 5775 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5776 __func__, err); 5777 out: 5778 return err; 5779 } 5780 5781 /** 5782 * ufshcd_disable_auto_bkops - block device in doing background operations 5783 * @hba: per-adapter instance 5784 * 5785 * Disabling background operations improves command response latency but 5786 * has drawback of device moving into critical state where the device is 5787 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5788 * host is idle so that BKOPS are managed effectively without any negative 5789 * impacts. 5790 * 5791 * Return: zero on success, non-zero on failure. 5792 */ 5793 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5794 { 5795 int err = 0; 5796 5797 if (!hba->auto_bkops_enabled) 5798 goto out; 5799 5800 /* 5801 * If host assisted BKOPs is to be enabled, make sure 5802 * urgent bkops exception is allowed. 5803 */ 5804 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5805 if (err) { 5806 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5807 __func__, err); 5808 goto out; 5809 } 5810 5811 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5812 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5813 if (err) { 5814 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5815 __func__, err); 5816 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5817 goto out; 5818 } 5819 5820 hba->auto_bkops_enabled = false; 5821 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5822 hba->is_urgent_bkops_lvl_checked = false; 5823 out: 5824 return err; 5825 } 5826 5827 /** 5828 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5829 * @hba: per adapter instance 5830 * 5831 * After a device reset the device may toggle the BKOPS_EN flag 5832 * to default value. The s/w tracking variables should be updated 5833 * as well. This function would change the auto-bkops state based on 5834 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5835 */ 5836 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5837 { 5838 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5839 hba->auto_bkops_enabled = false; 5840 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5841 ufshcd_enable_auto_bkops(hba); 5842 } else { 5843 hba->auto_bkops_enabled = true; 5844 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5845 ufshcd_disable_auto_bkops(hba); 5846 } 5847 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5848 hba->is_urgent_bkops_lvl_checked = false; 5849 } 5850 5851 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5852 { 5853 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5854 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5855 } 5856 5857 /** 5858 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5859 * @hba: per-adapter instance 5860 * @status: bkops_status value 5861 * 5862 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5863 * flag in the device to permit background operations if the device 5864 * bkops_status is greater than or equal to "status" argument passed to 5865 * this function, disable otherwise. 5866 * 5867 * Return: 0 for success, non-zero in case of failure. 5868 * 5869 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5870 * to know whether auto bkops is enabled or disabled after this function 5871 * returns control to it. 5872 */ 5873 static int ufshcd_bkops_ctrl(struct ufs_hba *hba, 5874 enum bkops_status status) 5875 { 5876 int err; 5877 u32 curr_status = 0; 5878 5879 err = ufshcd_get_bkops_status(hba, &curr_status); 5880 if (err) { 5881 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5882 __func__, err); 5883 goto out; 5884 } else if (curr_status > BKOPS_STATUS_MAX) { 5885 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5886 __func__, curr_status); 5887 err = -EINVAL; 5888 goto out; 5889 } 5890 5891 if (curr_status >= status) 5892 err = ufshcd_enable_auto_bkops(hba); 5893 else 5894 err = ufshcd_disable_auto_bkops(hba); 5895 out: 5896 return err; 5897 } 5898 5899 /** 5900 * ufshcd_urgent_bkops - handle urgent bkops exception event 5901 * @hba: per-adapter instance 5902 * 5903 * Enable fBackgroundOpsEn flag in the device to permit background 5904 * operations. 5905 * 5906 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled 5907 * and negative error value for any other failure. 5908 * 5909 * Return: 0 upon success; < 0 upon failure. 5910 */ 5911 static int ufshcd_urgent_bkops(struct ufs_hba *hba) 5912 { 5913 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl); 5914 } 5915 5916 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5917 { 5918 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5919 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5920 } 5921 5922 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5923 { 5924 int err; 5925 u32 curr_status = 0; 5926 5927 if (hba->is_urgent_bkops_lvl_checked) 5928 goto enable_auto_bkops; 5929 5930 err = ufshcd_get_bkops_status(hba, &curr_status); 5931 if (err) { 5932 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5933 __func__, err); 5934 goto out; 5935 } 5936 5937 /* 5938 * We are seeing that some devices are raising the urgent bkops 5939 * exception events even when BKOPS status doesn't indicate performace 5940 * impacted or critical. Handle these device by determining their urgent 5941 * bkops status at runtime. 5942 */ 5943 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5944 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5945 __func__, curr_status); 5946 /* update the current status as the urgent bkops level */ 5947 hba->urgent_bkops_lvl = curr_status; 5948 hba->is_urgent_bkops_lvl_checked = true; 5949 } 5950 5951 enable_auto_bkops: 5952 err = ufshcd_enable_auto_bkops(hba); 5953 out: 5954 if (err < 0) 5955 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5956 __func__, err); 5957 } 5958 5959 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5960 { 5961 u32 value; 5962 5963 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5964 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 5965 return; 5966 5967 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 5968 5969 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 5970 5971 /* 5972 * A placeholder for the platform vendors to add whatever additional 5973 * steps required 5974 */ 5975 } 5976 5977 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 5978 { 5979 u8 index; 5980 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 5981 UPIU_QUERY_OPCODE_CLEAR_FLAG; 5982 5983 index = ufshcd_wb_get_query_index(hba); 5984 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 5985 } 5986 5987 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 5988 { 5989 int ret; 5990 5991 if (!ufshcd_is_wb_allowed(hba) || 5992 hba->dev_info.wb_enabled == enable) 5993 return 0; 5994 5995 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 5996 if (ret) { 5997 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 5998 __func__, enable ? "enabling" : "disabling", ret); 5999 return ret; 6000 } 6001 6002 hba->dev_info.wb_enabled = enable; 6003 dev_dbg(hba->dev, "%s: Write Booster %s\n", 6004 __func__, enable ? "enabled" : "disabled"); 6005 6006 return ret; 6007 } 6008 6009 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 6010 bool enable) 6011 { 6012 int ret; 6013 6014 ret = __ufshcd_wb_toggle(hba, enable, 6015 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 6016 if (ret) { 6017 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 6018 __func__, enable ? "enabling" : "disabling", ret); 6019 return; 6020 } 6021 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 6022 __func__, enable ? "enabled" : "disabled"); 6023 } 6024 6025 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 6026 { 6027 int ret; 6028 6029 if (!ufshcd_is_wb_allowed(hba) || 6030 hba->dev_info.wb_buf_flush_enabled == enable) 6031 return 0; 6032 6033 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 6034 if (ret) { 6035 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 6036 __func__, enable ? "enabling" : "disabling", ret); 6037 return ret; 6038 } 6039 6040 hba->dev_info.wb_buf_flush_enabled = enable; 6041 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 6042 __func__, enable ? "enabled" : "disabled"); 6043 6044 return ret; 6045 } 6046 6047 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 6048 u32 avail_buf) 6049 { 6050 u32 cur_buf; 6051 int ret; 6052 u8 index; 6053 6054 index = ufshcd_wb_get_query_index(hba); 6055 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6056 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 6057 index, 0, &cur_buf); 6058 if (ret) { 6059 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 6060 __func__, ret); 6061 return false; 6062 } 6063 6064 if (!cur_buf) { 6065 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 6066 cur_buf); 6067 return false; 6068 } 6069 /* Let it continue to flush when available buffer exceeds threshold */ 6070 return avail_buf < hba->vps->wb_flush_threshold; 6071 } 6072 6073 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 6074 { 6075 if (ufshcd_is_wb_buf_flush_allowed(hba)) 6076 ufshcd_wb_toggle_buf_flush(hba, false); 6077 6078 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 6079 ufshcd_wb_toggle(hba, false); 6080 hba->caps &= ~UFSHCD_CAP_WB_EN; 6081 6082 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 6083 } 6084 6085 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 6086 { 6087 u32 lifetime; 6088 int ret; 6089 u8 index; 6090 6091 index = ufshcd_wb_get_query_index(hba); 6092 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6093 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 6094 index, 0, &lifetime); 6095 if (ret) { 6096 dev_err(hba->dev, 6097 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 6098 __func__, ret); 6099 return false; 6100 } 6101 6102 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6103 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6104 __func__, lifetime); 6105 return false; 6106 } 6107 6108 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6109 __func__, lifetime); 6110 6111 return true; 6112 } 6113 6114 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6115 { 6116 int ret; 6117 u32 avail_buf; 6118 u8 index; 6119 6120 if (!ufshcd_is_wb_allowed(hba)) 6121 return false; 6122 6123 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6124 ufshcd_wb_force_disable(hba); 6125 return false; 6126 } 6127 6128 /* 6129 * The ufs device needs the vcc to be ON to flush. 6130 * With user-space reduction enabled, it's enough to enable flush 6131 * by checking only the available buffer. The threshold 6132 * defined here is > 90% full. 6133 * With user-space preserved enabled, the current-buffer 6134 * should be checked too because the wb buffer size can reduce 6135 * when disk tends to be full. This info is provided by current 6136 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6137 * keeping vcc on when current buffer is empty. 6138 */ 6139 index = ufshcd_wb_get_query_index(hba); 6140 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6141 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6142 index, 0, &avail_buf); 6143 if (ret) { 6144 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6145 __func__, ret); 6146 return false; 6147 } 6148 6149 if (!hba->dev_info.b_presrv_uspc_en) 6150 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6151 6152 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6153 } 6154 6155 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6156 { 6157 struct ufs_hba *hba = container_of(to_delayed_work(work), 6158 struct ufs_hba, 6159 rpm_dev_flush_recheck_work); 6160 /* 6161 * To prevent unnecessary VCC power drain after device finishes 6162 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6163 * after a certain delay to recheck the threshold by next runtime 6164 * suspend. 6165 */ 6166 ufshcd_rpm_get_sync(hba); 6167 ufshcd_rpm_put_sync(hba); 6168 } 6169 6170 /** 6171 * ufshcd_exception_event_handler - handle exceptions raised by device 6172 * @work: pointer to work data 6173 * 6174 * Read bExceptionEventStatus attribute from the device and handle the 6175 * exception event accordingly. 6176 */ 6177 static void ufshcd_exception_event_handler(struct work_struct *work) 6178 { 6179 struct ufs_hba *hba; 6180 int err; 6181 u32 status = 0; 6182 hba = container_of(work, struct ufs_hba, eeh_work); 6183 6184 ufshcd_scsi_block_requests(hba); 6185 err = ufshcd_get_ee_status(hba, &status); 6186 if (err) { 6187 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6188 __func__, err); 6189 goto out; 6190 } 6191 6192 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6193 6194 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6195 ufshcd_bkops_exception_event_handler(hba); 6196 6197 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6198 ufshcd_temp_exception_event_handler(hba, status); 6199 6200 ufs_debugfs_exception_event(hba, status); 6201 out: 6202 ufshcd_scsi_unblock_requests(hba); 6203 } 6204 6205 /* Complete requests that have door-bell cleared */ 6206 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6207 { 6208 if (hba->mcq_enabled) 6209 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6210 else 6211 ufshcd_transfer_req_compl(hba); 6212 6213 ufshcd_tmc_handler(hba); 6214 } 6215 6216 /** 6217 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6218 * to recover from the DL NAC errors or not. 6219 * @hba: per-adapter instance 6220 * 6221 * Return: true if error handling is required, false otherwise. 6222 */ 6223 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6224 { 6225 unsigned long flags; 6226 bool err_handling = true; 6227 6228 spin_lock_irqsave(hba->host->host_lock, flags); 6229 /* 6230 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6231 * device fatal error and/or DL NAC & REPLAY timeout errors. 6232 */ 6233 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6234 goto out; 6235 6236 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6237 ((hba->saved_err & UIC_ERROR) && 6238 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6239 goto out; 6240 6241 if ((hba->saved_err & UIC_ERROR) && 6242 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6243 int err; 6244 /* 6245 * wait for 50ms to see if we can get any other errors or not. 6246 */ 6247 spin_unlock_irqrestore(hba->host->host_lock, flags); 6248 msleep(50); 6249 spin_lock_irqsave(hba->host->host_lock, flags); 6250 6251 /* 6252 * now check if we have got any other severe errors other than 6253 * DL NAC error? 6254 */ 6255 if ((hba->saved_err & INT_FATAL_ERRORS) || 6256 ((hba->saved_err & UIC_ERROR) && 6257 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6258 goto out; 6259 6260 /* 6261 * As DL NAC is the only error received so far, send out NOP 6262 * command to confirm if link is still active or not. 6263 * - If we don't get any response then do error recovery. 6264 * - If we get response then clear the DL NAC error bit. 6265 */ 6266 6267 spin_unlock_irqrestore(hba->host->host_lock, flags); 6268 err = ufshcd_verify_dev_init(hba); 6269 spin_lock_irqsave(hba->host->host_lock, flags); 6270 6271 if (err) 6272 goto out; 6273 6274 /* Link seems to be alive hence ignore the DL NAC errors */ 6275 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6276 hba->saved_err &= ~UIC_ERROR; 6277 /* clear NAC error */ 6278 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6279 if (!hba->saved_uic_err) 6280 err_handling = false; 6281 } 6282 out: 6283 spin_unlock_irqrestore(hba->host->host_lock, flags); 6284 return err_handling; 6285 } 6286 6287 /* host lock must be held before calling this func */ 6288 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6289 { 6290 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6291 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6292 } 6293 6294 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6295 { 6296 lockdep_assert_held(hba->host->host_lock); 6297 6298 /* handle fatal errors only when link is not in error state */ 6299 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6300 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6301 ufshcd_is_saved_err_fatal(hba)) 6302 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6303 else 6304 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6305 queue_work(hba->eh_wq, &hba->eh_work); 6306 } 6307 } 6308 6309 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6310 { 6311 spin_lock_irq(hba->host->host_lock); 6312 hba->force_reset = true; 6313 ufshcd_schedule_eh_work(hba); 6314 spin_unlock_irq(hba->host->host_lock); 6315 } 6316 6317 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6318 { 6319 mutex_lock(&hba->wb_mutex); 6320 down_write(&hba->clk_scaling_lock); 6321 hba->clk_scaling.is_allowed = allow; 6322 up_write(&hba->clk_scaling_lock); 6323 mutex_unlock(&hba->wb_mutex); 6324 } 6325 6326 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6327 { 6328 if (suspend) { 6329 if (hba->clk_scaling.is_enabled) 6330 ufshcd_suspend_clkscaling(hba); 6331 ufshcd_clk_scaling_allow(hba, false); 6332 } else { 6333 ufshcd_clk_scaling_allow(hba, true); 6334 if (hba->clk_scaling.is_enabled) 6335 ufshcd_resume_clkscaling(hba); 6336 } 6337 } 6338 6339 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6340 { 6341 ufshcd_rpm_get_sync(hba); 6342 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6343 hba->is_sys_suspended) { 6344 enum ufs_pm_op pm_op; 6345 6346 /* 6347 * Don't assume anything of resume, if 6348 * resume fails, irq and clocks can be OFF, and powers 6349 * can be OFF or in LPM. 6350 */ 6351 ufshcd_setup_hba_vreg(hba, true); 6352 ufshcd_enable_irq(hba); 6353 ufshcd_setup_vreg(hba, true); 6354 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6355 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6356 ufshcd_hold(hba); 6357 if (!ufshcd_is_clkgating_allowed(hba)) 6358 ufshcd_setup_clocks(hba, true); 6359 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6360 ufshcd_vops_resume(hba, pm_op); 6361 } else { 6362 ufshcd_hold(hba); 6363 if (ufshcd_is_clkscaling_supported(hba) && 6364 hba->clk_scaling.is_enabled) 6365 ufshcd_suspend_clkscaling(hba); 6366 ufshcd_clk_scaling_allow(hba, false); 6367 } 6368 ufshcd_scsi_block_requests(hba); 6369 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6370 blk_mq_wait_quiesce_done(&hba->host->tag_set); 6371 cancel_work_sync(&hba->eeh_work); 6372 } 6373 6374 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6375 { 6376 ufshcd_scsi_unblock_requests(hba); 6377 ufshcd_release(hba); 6378 if (ufshcd_is_clkscaling_supported(hba)) 6379 ufshcd_clk_scaling_suspend(hba, false); 6380 ufshcd_rpm_put(hba); 6381 } 6382 6383 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6384 { 6385 return (!hba->is_powered || hba->shutting_down || 6386 !hba->ufs_device_wlun || 6387 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6388 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6389 ufshcd_is_link_broken(hba)))); 6390 } 6391 6392 #ifdef CONFIG_PM 6393 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6394 { 6395 struct Scsi_Host *shost = hba->host; 6396 struct scsi_device *sdev; 6397 struct request_queue *q; 6398 int ret; 6399 6400 hba->is_sys_suspended = false; 6401 /* 6402 * Set RPM status of wlun device to RPM_ACTIVE, 6403 * this also clears its runtime error. 6404 */ 6405 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6406 6407 /* hba device might have a runtime error otherwise */ 6408 if (ret) 6409 ret = pm_runtime_set_active(hba->dev); 6410 /* 6411 * If wlun device had runtime error, we also need to resume those 6412 * consumer scsi devices in case any of them has failed to be 6413 * resumed due to supplier runtime resume failure. This is to unblock 6414 * blk_queue_enter in case there are bios waiting inside it. 6415 */ 6416 if (!ret) { 6417 shost_for_each_device(sdev, shost) { 6418 q = sdev->request_queue; 6419 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6420 q->rpm_status == RPM_SUSPENDING)) 6421 pm_request_resume(q->dev); 6422 } 6423 } 6424 } 6425 #else 6426 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6427 { 6428 } 6429 #endif 6430 6431 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6432 { 6433 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6434 u32 mode; 6435 6436 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6437 6438 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6439 return true; 6440 6441 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6442 return true; 6443 6444 return false; 6445 } 6446 6447 static bool ufshcd_abort_one(struct request *rq, void *priv) 6448 { 6449 int *ret = priv; 6450 u32 tag = rq->tag; 6451 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6452 struct scsi_device *sdev = cmd->device; 6453 struct Scsi_Host *shost = sdev->host; 6454 struct ufs_hba *hba = shost_priv(shost); 6455 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 6456 struct ufs_hw_queue *hwq; 6457 unsigned long flags; 6458 6459 *ret = ufshcd_try_to_abort_task(hba, tag); 6460 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6461 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6462 *ret ? "failed" : "succeeded"); 6463 6464 /* Release cmd in MCQ mode if abort succeeds */ 6465 if (hba->mcq_enabled && (*ret == 0)) { 6466 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 6467 if (!hwq) 6468 return 0; 6469 spin_lock_irqsave(&hwq->cq_lock, flags); 6470 if (ufshcd_cmd_inflight(lrbp->cmd)) 6471 ufshcd_release_scsi_cmd(hba, lrbp); 6472 spin_unlock_irqrestore(&hwq->cq_lock, flags); 6473 } 6474 6475 return *ret == 0; 6476 } 6477 6478 /** 6479 * ufshcd_abort_all - Abort all pending commands. 6480 * @hba: Host bus adapter pointer. 6481 * 6482 * Return: true if and only if the host controller needs to be reset. 6483 */ 6484 static bool ufshcd_abort_all(struct ufs_hba *hba) 6485 { 6486 int tag, ret = 0; 6487 6488 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6489 if (ret) 6490 goto out; 6491 6492 /* Clear pending task management requests */ 6493 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6494 ret = ufshcd_clear_tm_cmd(hba, tag); 6495 if (ret) 6496 goto out; 6497 } 6498 6499 out: 6500 /* Complete the requests that are cleared by s/w */ 6501 ufshcd_complete_requests(hba, false); 6502 6503 return ret != 0; 6504 } 6505 6506 /** 6507 * ufshcd_err_handler - handle UFS errors that require s/w attention 6508 * @work: pointer to work structure 6509 */ 6510 static void ufshcd_err_handler(struct work_struct *work) 6511 { 6512 int retries = MAX_ERR_HANDLER_RETRIES; 6513 struct ufs_hba *hba; 6514 unsigned long flags; 6515 bool needs_restore; 6516 bool needs_reset; 6517 int pmc_err; 6518 6519 hba = container_of(work, struct ufs_hba, eh_work); 6520 6521 dev_info(hba->dev, 6522 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6523 __func__, ufshcd_state_name[hba->ufshcd_state], 6524 hba->is_powered, hba->shutting_down, hba->saved_err, 6525 hba->saved_uic_err, hba->force_reset, 6526 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6527 6528 down(&hba->host_sem); 6529 spin_lock_irqsave(hba->host->host_lock, flags); 6530 if (ufshcd_err_handling_should_stop(hba)) { 6531 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6532 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6533 spin_unlock_irqrestore(hba->host->host_lock, flags); 6534 up(&hba->host_sem); 6535 return; 6536 } 6537 ufshcd_set_eh_in_progress(hba); 6538 spin_unlock_irqrestore(hba->host->host_lock, flags); 6539 ufshcd_err_handling_prepare(hba); 6540 /* Complete requests that have door-bell cleared by h/w */ 6541 ufshcd_complete_requests(hba, false); 6542 spin_lock_irqsave(hba->host->host_lock, flags); 6543 again: 6544 needs_restore = false; 6545 needs_reset = false; 6546 6547 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6548 hba->ufshcd_state = UFSHCD_STATE_RESET; 6549 /* 6550 * A full reset and restore might have happened after preparation 6551 * is finished, double check whether we should stop. 6552 */ 6553 if (ufshcd_err_handling_should_stop(hba)) 6554 goto skip_err_handling; 6555 6556 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6557 bool ret; 6558 6559 spin_unlock_irqrestore(hba->host->host_lock, flags); 6560 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6561 ret = ufshcd_quirk_dl_nac_errors(hba); 6562 spin_lock_irqsave(hba->host->host_lock, flags); 6563 if (!ret && ufshcd_err_handling_should_stop(hba)) 6564 goto skip_err_handling; 6565 } 6566 6567 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6568 (hba->saved_uic_err && 6569 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6570 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6571 6572 spin_unlock_irqrestore(hba->host->host_lock, flags); 6573 ufshcd_print_host_state(hba); 6574 ufshcd_print_pwr_info(hba); 6575 ufshcd_print_evt_hist(hba); 6576 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6577 ufshcd_print_trs_all(hba, pr_prdt); 6578 spin_lock_irqsave(hba->host->host_lock, flags); 6579 } 6580 6581 /* 6582 * if host reset is required then skip clearing the pending 6583 * transfers forcefully because they will get cleared during 6584 * host reset and restore 6585 */ 6586 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6587 ufshcd_is_saved_err_fatal(hba) || 6588 ((hba->saved_err & UIC_ERROR) && 6589 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6590 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6591 needs_reset = true; 6592 goto do_reset; 6593 } 6594 6595 /* 6596 * If LINERESET was caught, UFS might have been put to PWM mode, 6597 * check if power mode restore is needed. 6598 */ 6599 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6600 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6601 if (!hba->saved_uic_err) 6602 hba->saved_err &= ~UIC_ERROR; 6603 spin_unlock_irqrestore(hba->host->host_lock, flags); 6604 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6605 needs_restore = true; 6606 spin_lock_irqsave(hba->host->host_lock, flags); 6607 if (!hba->saved_err && !needs_restore) 6608 goto skip_err_handling; 6609 } 6610 6611 hba->silence_err_logs = true; 6612 /* release lock as clear command might sleep */ 6613 spin_unlock_irqrestore(hba->host->host_lock, flags); 6614 6615 needs_reset = ufshcd_abort_all(hba); 6616 6617 spin_lock_irqsave(hba->host->host_lock, flags); 6618 hba->silence_err_logs = false; 6619 if (needs_reset) 6620 goto do_reset; 6621 6622 /* 6623 * After all reqs and tasks are cleared from doorbell, 6624 * now it is safe to retore power mode. 6625 */ 6626 if (needs_restore) { 6627 spin_unlock_irqrestore(hba->host->host_lock, flags); 6628 /* 6629 * Hold the scaling lock just in case dev cmds 6630 * are sent via bsg and/or sysfs. 6631 */ 6632 down_write(&hba->clk_scaling_lock); 6633 hba->force_pmc = true; 6634 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6635 if (pmc_err) { 6636 needs_reset = true; 6637 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6638 __func__, pmc_err); 6639 } 6640 hba->force_pmc = false; 6641 ufshcd_print_pwr_info(hba); 6642 up_write(&hba->clk_scaling_lock); 6643 spin_lock_irqsave(hba->host->host_lock, flags); 6644 } 6645 6646 do_reset: 6647 /* Fatal errors need reset */ 6648 if (needs_reset) { 6649 int err; 6650 6651 hba->force_reset = false; 6652 spin_unlock_irqrestore(hba->host->host_lock, flags); 6653 err = ufshcd_reset_and_restore(hba); 6654 if (err) 6655 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6656 __func__, err); 6657 else 6658 ufshcd_recover_pm_error(hba); 6659 spin_lock_irqsave(hba->host->host_lock, flags); 6660 } 6661 6662 skip_err_handling: 6663 if (!needs_reset) { 6664 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6665 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6666 if (hba->saved_err || hba->saved_uic_err) 6667 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6668 __func__, hba->saved_err, hba->saved_uic_err); 6669 } 6670 /* Exit in an operational state or dead */ 6671 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6672 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6673 if (--retries) 6674 goto again; 6675 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6676 } 6677 ufshcd_clear_eh_in_progress(hba); 6678 spin_unlock_irqrestore(hba->host->host_lock, flags); 6679 ufshcd_err_handling_unprepare(hba); 6680 up(&hba->host_sem); 6681 6682 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6683 ufshcd_state_name[hba->ufshcd_state]); 6684 } 6685 6686 /** 6687 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6688 * @hba: per-adapter instance 6689 * 6690 * Return: 6691 * IRQ_HANDLED - If interrupt is valid 6692 * IRQ_NONE - If invalid interrupt 6693 */ 6694 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6695 { 6696 u32 reg; 6697 irqreturn_t retval = IRQ_NONE; 6698 6699 /* PHY layer error */ 6700 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6701 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6702 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6703 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6704 /* 6705 * To know whether this error is fatal or not, DB timeout 6706 * must be checked but this error is handled separately. 6707 */ 6708 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6709 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6710 __func__); 6711 6712 /* Got a LINERESET indication. */ 6713 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6714 struct uic_command *cmd = NULL; 6715 6716 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6717 if (hba->uic_async_done && hba->active_uic_cmd) 6718 cmd = hba->active_uic_cmd; 6719 /* 6720 * Ignore the LINERESET during power mode change 6721 * operation via DME_SET command. 6722 */ 6723 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6724 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6725 } 6726 retval |= IRQ_HANDLED; 6727 } 6728 6729 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6730 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6731 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6732 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6733 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6734 6735 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6736 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6737 else if (hba->dev_quirks & 6738 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6739 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6740 hba->uic_error |= 6741 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6742 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6743 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6744 } 6745 retval |= IRQ_HANDLED; 6746 } 6747 6748 /* UIC NL/TL/DME errors needs software retry */ 6749 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6750 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6751 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6752 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6753 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6754 retval |= IRQ_HANDLED; 6755 } 6756 6757 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6758 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6759 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6760 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6761 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6762 retval |= IRQ_HANDLED; 6763 } 6764 6765 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6766 if ((reg & UIC_DME_ERROR) && 6767 (reg & UIC_DME_ERROR_CODE_MASK)) { 6768 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6769 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6770 retval |= IRQ_HANDLED; 6771 } 6772 6773 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6774 __func__, hba->uic_error); 6775 return retval; 6776 } 6777 6778 /** 6779 * ufshcd_check_errors - Check for errors that need s/w attention 6780 * @hba: per-adapter instance 6781 * @intr_status: interrupt status generated by the controller 6782 * 6783 * Return: 6784 * IRQ_HANDLED - If interrupt is valid 6785 * IRQ_NONE - If invalid interrupt 6786 */ 6787 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6788 { 6789 bool queue_eh_work = false; 6790 irqreturn_t retval = IRQ_NONE; 6791 6792 spin_lock(hba->host->host_lock); 6793 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6794 6795 if (hba->errors & INT_FATAL_ERRORS) { 6796 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6797 hba->errors); 6798 queue_eh_work = true; 6799 } 6800 6801 if (hba->errors & UIC_ERROR) { 6802 hba->uic_error = 0; 6803 retval = ufshcd_update_uic_error(hba); 6804 if (hba->uic_error) 6805 queue_eh_work = true; 6806 } 6807 6808 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6809 dev_err(hba->dev, 6810 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6811 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6812 "Enter" : "Exit", 6813 hba->errors, ufshcd_get_upmcrs(hba)); 6814 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6815 hba->errors); 6816 ufshcd_set_link_broken(hba); 6817 queue_eh_work = true; 6818 } 6819 6820 if (queue_eh_work) { 6821 /* 6822 * update the transfer error masks to sticky bits, let's do this 6823 * irrespective of current ufshcd_state. 6824 */ 6825 hba->saved_err |= hba->errors; 6826 hba->saved_uic_err |= hba->uic_error; 6827 6828 /* dump controller state before resetting */ 6829 if ((hba->saved_err & 6830 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6831 (hba->saved_uic_err && 6832 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6833 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6834 __func__, hba->saved_err, 6835 hba->saved_uic_err); 6836 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6837 "host_regs: "); 6838 ufshcd_print_pwr_info(hba); 6839 } 6840 ufshcd_schedule_eh_work(hba); 6841 retval |= IRQ_HANDLED; 6842 } 6843 /* 6844 * if (!queue_eh_work) - 6845 * Other errors are either non-fatal where host recovers 6846 * itself without s/w intervention or errors that will be 6847 * handled by the SCSI core layer. 6848 */ 6849 hba->errors = 0; 6850 hba->uic_error = 0; 6851 spin_unlock(hba->host->host_lock); 6852 return retval; 6853 } 6854 6855 /** 6856 * ufshcd_tmc_handler - handle task management function completion 6857 * @hba: per adapter instance 6858 * 6859 * Return: 6860 * IRQ_HANDLED - If interrupt is valid 6861 * IRQ_NONE - If invalid interrupt 6862 */ 6863 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6864 { 6865 unsigned long flags, pending, issued; 6866 irqreturn_t ret = IRQ_NONE; 6867 int tag; 6868 6869 spin_lock_irqsave(hba->host->host_lock, flags); 6870 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6871 issued = hba->outstanding_tasks & ~pending; 6872 for_each_set_bit(tag, &issued, hba->nutmrs) { 6873 struct request *req = hba->tmf_rqs[tag]; 6874 struct completion *c = req->end_io_data; 6875 6876 complete(c); 6877 ret = IRQ_HANDLED; 6878 } 6879 spin_unlock_irqrestore(hba->host->host_lock, flags); 6880 6881 return ret; 6882 } 6883 6884 /** 6885 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6886 * @hba: per adapter instance 6887 * 6888 * Return: IRQ_HANDLED if interrupt is handled. 6889 */ 6890 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6891 { 6892 struct ufs_hw_queue *hwq; 6893 unsigned long outstanding_cqs; 6894 unsigned int nr_queues; 6895 int i, ret; 6896 u32 events; 6897 6898 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6899 if (ret) 6900 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6901 6902 /* Exclude the poll queues */ 6903 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6904 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6905 hwq = &hba->uhq[i]; 6906 6907 events = ufshcd_mcq_read_cqis(hba, i); 6908 if (events) 6909 ufshcd_mcq_write_cqis(hba, events, i); 6910 6911 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6912 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6913 } 6914 6915 return IRQ_HANDLED; 6916 } 6917 6918 /** 6919 * ufshcd_sl_intr - Interrupt service routine 6920 * @hba: per adapter instance 6921 * @intr_status: contains interrupts generated by the controller 6922 * 6923 * Return: 6924 * IRQ_HANDLED - If interrupt is valid 6925 * IRQ_NONE - If invalid interrupt 6926 */ 6927 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6928 { 6929 irqreturn_t retval = IRQ_NONE; 6930 6931 if (intr_status & UFSHCD_UIC_MASK) 6932 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6933 6934 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6935 retval |= ufshcd_check_errors(hba, intr_status); 6936 6937 if (intr_status & UTP_TASK_REQ_COMPL) 6938 retval |= ufshcd_tmc_handler(hba); 6939 6940 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6941 retval |= ufshcd_transfer_req_compl(hba); 6942 6943 if (intr_status & MCQ_CQ_EVENT_STATUS) 6944 retval |= ufshcd_handle_mcq_cq_events(hba); 6945 6946 return retval; 6947 } 6948 6949 /** 6950 * ufshcd_intr - Main interrupt service routine 6951 * @irq: irq number 6952 * @__hba: pointer to adapter instance 6953 * 6954 * Return: 6955 * IRQ_HANDLED - If interrupt is valid 6956 * IRQ_NONE - If invalid interrupt 6957 */ 6958 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6959 { 6960 u32 intr_status, enabled_intr_status = 0; 6961 irqreturn_t retval = IRQ_NONE; 6962 struct ufs_hba *hba = __hba; 6963 int retries = hba->nutrs; 6964 6965 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6966 hba->ufs_stats.last_intr_status = intr_status; 6967 hba->ufs_stats.last_intr_ts = local_clock(); 6968 6969 /* 6970 * There could be max of hba->nutrs reqs in flight and in worst case 6971 * if the reqs get finished 1 by 1 after the interrupt status is 6972 * read, make sure we handle them by checking the interrupt status 6973 * again in a loop until we process all of the reqs before returning. 6974 */ 6975 while (intr_status && retries--) { 6976 enabled_intr_status = 6977 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6978 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6979 if (enabled_intr_status) 6980 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 6981 6982 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6983 } 6984 6985 if (enabled_intr_status && retval == IRQ_NONE && 6986 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 6987 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 6988 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 6989 __func__, 6990 intr_status, 6991 hba->ufs_stats.last_intr_status, 6992 enabled_intr_status); 6993 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 6994 } 6995 6996 return retval; 6997 } 6998 6999 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 7000 { 7001 int err = 0; 7002 u32 mask = 1 << tag; 7003 unsigned long flags; 7004 7005 if (!test_bit(tag, &hba->outstanding_tasks)) 7006 goto out; 7007 7008 spin_lock_irqsave(hba->host->host_lock, flags); 7009 ufshcd_utmrl_clear(hba, tag); 7010 spin_unlock_irqrestore(hba->host->host_lock, flags); 7011 7012 /* poll for max. 1 sec to clear door bell register by h/w */ 7013 err = ufshcd_wait_for_register(hba, 7014 REG_UTP_TASK_REQ_DOOR_BELL, 7015 mask, 0, 1000, 1000); 7016 7017 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 7018 tag, err < 0 ? "failed" : "succeeded"); 7019 7020 out: 7021 return err; 7022 } 7023 7024 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 7025 struct utp_task_req_desc *treq, u8 tm_function) 7026 { 7027 struct request_queue *q = hba->tmf_queue; 7028 struct Scsi_Host *host = hba->host; 7029 DECLARE_COMPLETION_ONSTACK(wait); 7030 struct request *req; 7031 unsigned long flags; 7032 int task_tag, err; 7033 7034 /* 7035 * blk_mq_alloc_request() is used here only to get a free tag. 7036 */ 7037 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 7038 if (IS_ERR(req)) 7039 return PTR_ERR(req); 7040 7041 req->end_io_data = &wait; 7042 ufshcd_hold(hba); 7043 7044 spin_lock_irqsave(host->host_lock, flags); 7045 7046 task_tag = req->tag; 7047 hba->tmf_rqs[req->tag] = req; 7048 treq->upiu_req.req_header.task_tag = task_tag; 7049 7050 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 7051 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 7052 7053 /* send command to the controller */ 7054 __set_bit(task_tag, &hba->outstanding_tasks); 7055 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 7056 7057 spin_unlock_irqrestore(host->host_lock, flags); 7058 7059 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 7060 7061 /* wait until the task management command is completed */ 7062 err = wait_for_completion_io_timeout(&wait, 7063 msecs_to_jiffies(TM_CMD_TIMEOUT)); 7064 if (!err) { 7065 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 7066 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 7067 __func__, tm_function); 7068 if (ufshcd_clear_tm_cmd(hba, task_tag)) 7069 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 7070 __func__, task_tag); 7071 err = -ETIMEDOUT; 7072 } else { 7073 err = 0; 7074 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 7075 7076 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 7077 } 7078 7079 spin_lock_irqsave(hba->host->host_lock, flags); 7080 hba->tmf_rqs[req->tag] = NULL; 7081 __clear_bit(task_tag, &hba->outstanding_tasks); 7082 spin_unlock_irqrestore(hba->host->host_lock, flags); 7083 7084 ufshcd_release(hba); 7085 blk_mq_free_request(req); 7086 7087 return err; 7088 } 7089 7090 /** 7091 * ufshcd_issue_tm_cmd - issues task management commands to controller 7092 * @hba: per adapter instance 7093 * @lun_id: LUN ID to which TM command is sent 7094 * @task_id: task ID to which the TM command is applicable 7095 * @tm_function: task management function opcode 7096 * @tm_response: task management service response return value 7097 * 7098 * Return: non-zero value on error, zero on success. 7099 */ 7100 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7101 u8 tm_function, u8 *tm_response) 7102 { 7103 struct utp_task_req_desc treq = { }; 7104 enum utp_ocs ocs_value; 7105 int err; 7106 7107 /* Configure task request descriptor */ 7108 treq.header.interrupt = 1; 7109 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7110 7111 /* Configure task request UPIU */ 7112 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7113 treq.upiu_req.req_header.lun = lun_id; 7114 treq.upiu_req.req_header.tm_function = tm_function; 7115 7116 /* 7117 * The host shall provide the same value for LUN field in the basic 7118 * header and for Input Parameter. 7119 */ 7120 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7121 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7122 7123 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7124 if (err == -ETIMEDOUT) 7125 return err; 7126 7127 ocs_value = treq.header.ocs & MASK_OCS; 7128 if (ocs_value != OCS_SUCCESS) 7129 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7130 __func__, ocs_value); 7131 else if (tm_response) 7132 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7133 MASK_TM_SERVICE_RESP; 7134 return err; 7135 } 7136 7137 /** 7138 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7139 * @hba: per-adapter instance 7140 * @req_upiu: upiu request 7141 * @rsp_upiu: upiu reply 7142 * @desc_buff: pointer to descriptor buffer, NULL if NA 7143 * @buff_len: descriptor size, 0 if NA 7144 * @cmd_type: specifies the type (NOP, Query...) 7145 * @desc_op: descriptor operation 7146 * 7147 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7148 * Therefore, it "rides" the device management infrastructure: uses its tag and 7149 * tasks work queues. 7150 * 7151 * Since there is only one available tag for device management commands, 7152 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7153 * 7154 * Return: 0 upon success; < 0 upon failure. 7155 */ 7156 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7157 struct utp_upiu_req *req_upiu, 7158 struct utp_upiu_req *rsp_upiu, 7159 u8 *desc_buff, int *buff_len, 7160 enum dev_cmd_type cmd_type, 7161 enum query_opcode desc_op) 7162 { 7163 const u32 tag = hba->reserved_slot; 7164 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7165 int err = 0; 7166 u8 upiu_flags; 7167 7168 /* Protects use of hba->reserved_slot. */ 7169 lockdep_assert_held(&hba->dev_cmd.lock); 7170 7171 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 7172 7173 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 7174 7175 /* update the task tag in the request upiu */ 7176 req_upiu->header.task_tag = tag; 7177 7178 /* just copy the upiu request as it is */ 7179 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7180 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7181 /* The Data Segment Area is optional depending upon the query 7182 * function value. for WRITE DESCRIPTOR, the data segment 7183 * follows right after the tsf. 7184 */ 7185 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7186 *buff_len = 0; 7187 } 7188 7189 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7190 7191 /* 7192 * ignore the returning value here - ufshcd_check_query_response is 7193 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7194 * read the response directly ignoring all errors. 7195 */ 7196 ufshcd_issue_dev_cmd(hba, lrbp, tag, QUERY_REQ_TIMEOUT); 7197 7198 /* just copy the upiu response as it is */ 7199 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7200 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7201 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7202 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7203 .data_segment_length); 7204 7205 if (*buff_len >= resp_len) { 7206 memcpy(desc_buff, descp, resp_len); 7207 *buff_len = resp_len; 7208 } else { 7209 dev_warn(hba->dev, 7210 "%s: rsp size %d is bigger than buffer size %d", 7211 __func__, resp_len, *buff_len); 7212 *buff_len = 0; 7213 err = -EINVAL; 7214 } 7215 } 7216 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7217 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7218 7219 return err; 7220 } 7221 7222 /** 7223 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7224 * @hba: per-adapter instance 7225 * @req_upiu: upiu request 7226 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7227 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7228 * @desc_buff: pointer to descriptor buffer, NULL if NA 7229 * @buff_len: descriptor size, 0 if NA 7230 * @desc_op: descriptor operation 7231 * 7232 * Supports UTP Transfer requests (nop and query), and UTP Task 7233 * Management requests. 7234 * It is up to the caller to fill the upiu conent properly, as it will 7235 * be copied without any further input validations. 7236 * 7237 * Return: 0 upon success; < 0 upon failure. 7238 */ 7239 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7240 struct utp_upiu_req *req_upiu, 7241 struct utp_upiu_req *rsp_upiu, 7242 enum upiu_request_transaction msgcode, 7243 u8 *desc_buff, int *buff_len, 7244 enum query_opcode desc_op) 7245 { 7246 int err; 7247 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7248 struct utp_task_req_desc treq = { }; 7249 enum utp_ocs ocs_value; 7250 u8 tm_f = req_upiu->header.tm_function; 7251 7252 switch (msgcode) { 7253 case UPIU_TRANSACTION_NOP_OUT: 7254 cmd_type = DEV_CMD_TYPE_NOP; 7255 fallthrough; 7256 case UPIU_TRANSACTION_QUERY_REQ: 7257 ufshcd_dev_man_lock(hba); 7258 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7259 desc_buff, buff_len, 7260 cmd_type, desc_op); 7261 ufshcd_dev_man_unlock(hba); 7262 7263 break; 7264 case UPIU_TRANSACTION_TASK_REQ: 7265 treq.header.interrupt = 1; 7266 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7267 7268 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7269 7270 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7271 if (err == -ETIMEDOUT) 7272 break; 7273 7274 ocs_value = treq.header.ocs & MASK_OCS; 7275 if (ocs_value != OCS_SUCCESS) { 7276 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7277 ocs_value); 7278 break; 7279 } 7280 7281 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7282 7283 break; 7284 default: 7285 err = -EINVAL; 7286 7287 break; 7288 } 7289 7290 return err; 7291 } 7292 7293 /** 7294 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7295 * @hba: per adapter instance 7296 * @req_upiu: upiu request 7297 * @rsp_upiu: upiu reply 7298 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7299 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7300 * @sg_cnt: The number of sg lists actually used 7301 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7302 * @dir: DMA direction 7303 * 7304 * Return: zero on success, non-zero on failure. 7305 */ 7306 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7307 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7308 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7309 enum dma_data_direction dir) 7310 { 7311 const u32 tag = hba->reserved_slot; 7312 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7313 int err = 0; 7314 int result; 7315 u8 upiu_flags; 7316 u8 *ehs_data; 7317 u16 ehs_len; 7318 int ehs = (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) ? 2 : 0; 7319 7320 /* Protects use of hba->reserved_slot. */ 7321 ufshcd_dev_man_lock(hba); 7322 7323 ufshcd_setup_dev_cmd(hba, lrbp, DEV_CMD_TYPE_RPMB, UFS_UPIU_RPMB_WLUN, tag); 7324 7325 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, ehs); 7326 7327 /* update the task tag */ 7328 req_upiu->header.task_tag = tag; 7329 7330 /* copy the UPIU(contains CDB) request as it is */ 7331 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7332 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7333 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7334 7335 if (dir != DMA_NONE && sg_list) 7336 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7337 7338 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7339 7340 err = ufshcd_issue_dev_cmd(hba, lrbp, tag, ADVANCED_RPMB_REQ_TIMEOUT); 7341 7342 if (!err) { 7343 /* Just copy the upiu response as it is */ 7344 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7345 /* Get the response UPIU result */ 7346 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7347 lrbp->ucd_rsp_ptr->header.status; 7348 7349 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7350 /* 7351 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7352 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7353 * Message is 02h 7354 */ 7355 if (ehs_len == 2 && rsp_ehs) { 7356 /* 7357 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7358 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7359 */ 7360 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7361 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7362 } 7363 } 7364 7365 ufshcd_dev_man_unlock(hba); 7366 7367 return err ? : result; 7368 } 7369 7370 /** 7371 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7372 * @cmd: SCSI command pointer 7373 * 7374 * Return: SUCCESS or FAILED. 7375 */ 7376 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7377 { 7378 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7379 struct Scsi_Host *host; 7380 struct ufs_hba *hba; 7381 struct ufs_hw_queue *hwq; 7382 struct ufshcd_lrb *lrbp; 7383 u32 pos, not_cleared_mask = 0; 7384 int err; 7385 u8 resp = 0xF, lun; 7386 7387 host = cmd->device->host; 7388 hba = shost_priv(host); 7389 7390 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7391 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7392 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7393 if (!err) 7394 err = resp; 7395 goto out; 7396 } 7397 7398 if (hba->mcq_enabled) { 7399 for (pos = 0; pos < hba->nutrs; pos++) { 7400 lrbp = &hba->lrb[pos]; 7401 if (ufshcd_cmd_inflight(lrbp->cmd) && 7402 lrbp->lun == lun) { 7403 ufshcd_clear_cmd(hba, pos); 7404 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7405 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7406 } 7407 } 7408 err = 0; 7409 goto out; 7410 } 7411 7412 /* clear the commands that were pending for corresponding LUN */ 7413 spin_lock_irqsave(&hba->outstanding_lock, flags); 7414 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7415 if (hba->lrb[pos].lun == lun) 7416 __set_bit(pos, &pending_reqs); 7417 hba->outstanding_reqs &= ~pending_reqs; 7418 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7419 7420 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7421 if (ufshcd_clear_cmd(hba, pos) < 0) { 7422 spin_lock_irqsave(&hba->outstanding_lock, flags); 7423 not_cleared = 1U << pos & 7424 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7425 hba->outstanding_reqs |= not_cleared; 7426 not_cleared_mask |= not_cleared; 7427 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7428 7429 dev_err(hba->dev, "%s: failed to clear request %d\n", 7430 __func__, pos); 7431 } 7432 } 7433 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7434 7435 out: 7436 hba->req_abort_count = 0; 7437 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7438 if (!err) { 7439 err = SUCCESS; 7440 } else { 7441 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7442 err = FAILED; 7443 } 7444 return err; 7445 } 7446 7447 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7448 { 7449 struct ufshcd_lrb *lrbp; 7450 int tag; 7451 7452 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7453 lrbp = &hba->lrb[tag]; 7454 lrbp->req_abort_skip = true; 7455 } 7456 } 7457 7458 /** 7459 * ufshcd_try_to_abort_task - abort a specific task 7460 * @hba: Pointer to adapter instance 7461 * @tag: Task tag/index to be aborted 7462 * 7463 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7464 * command, and in host controller by clearing the door-bell register. There can 7465 * be race between controller sending the command to the device while abort is 7466 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7467 * really issued and then try to abort it. 7468 * 7469 * Return: zero on success, non-zero on failure. 7470 */ 7471 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7472 { 7473 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7474 int err = 0; 7475 int poll_cnt; 7476 u8 resp = 0xF; 7477 u32 reg; 7478 7479 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7480 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7481 UFS_QUERY_TASK, &resp); 7482 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7483 /* cmd pending in the device */ 7484 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7485 __func__, tag); 7486 break; 7487 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7488 /* 7489 * cmd not pending in the device, check if it is 7490 * in transition. 7491 */ 7492 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n", 7493 __func__, tag); 7494 if (hba->mcq_enabled) { 7495 /* MCQ mode */ 7496 if (ufshcd_cmd_inflight(lrbp->cmd)) { 7497 /* sleep for max. 200us same delay as in SDB mode */ 7498 usleep_range(100, 200); 7499 continue; 7500 } 7501 /* command completed already */ 7502 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n", 7503 __func__, tag); 7504 goto out; 7505 } 7506 7507 /* Single Doorbell Mode */ 7508 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7509 if (reg & (1 << tag)) { 7510 /* sleep for max. 200us to stabilize */ 7511 usleep_range(100, 200); 7512 continue; 7513 } 7514 /* command completed already */ 7515 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n", 7516 __func__, tag); 7517 goto out; 7518 } else { 7519 dev_err(hba->dev, 7520 "%s: no response from device. tag = %d, err %d\n", 7521 __func__, tag, err); 7522 if (!err) 7523 err = resp; /* service response error */ 7524 goto out; 7525 } 7526 } 7527 7528 if (!poll_cnt) { 7529 err = -EBUSY; 7530 goto out; 7531 } 7532 7533 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7534 UFS_ABORT_TASK, &resp); 7535 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7536 if (!err) { 7537 err = resp; /* service response error */ 7538 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7539 __func__, tag, err); 7540 } 7541 goto out; 7542 } 7543 7544 err = ufshcd_clear_cmd(hba, tag); 7545 if (err) 7546 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7547 __func__, tag, err); 7548 7549 out: 7550 return err; 7551 } 7552 7553 /** 7554 * ufshcd_abort - scsi host template eh_abort_handler callback 7555 * @cmd: SCSI command pointer 7556 * 7557 * Return: SUCCESS or FAILED. 7558 */ 7559 static int ufshcd_abort(struct scsi_cmnd *cmd) 7560 { 7561 struct Scsi_Host *host = cmd->device->host; 7562 struct ufs_hba *hba = shost_priv(host); 7563 int tag = scsi_cmd_to_rq(cmd)->tag; 7564 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7565 unsigned long flags; 7566 int err = FAILED; 7567 bool outstanding; 7568 u32 reg; 7569 7570 ufshcd_hold(hba); 7571 7572 if (!hba->mcq_enabled) { 7573 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7574 if (!test_bit(tag, &hba->outstanding_reqs)) { 7575 /* If command is already aborted/completed, return FAILED. */ 7576 dev_err(hba->dev, 7577 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7578 __func__, tag, hba->outstanding_reqs, reg); 7579 goto release; 7580 } 7581 } 7582 7583 /* Print Transfer Request of aborted task */ 7584 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7585 7586 /* 7587 * Print detailed info about aborted request. 7588 * As more than one request might get aborted at the same time, 7589 * print full information only for the first aborted request in order 7590 * to reduce repeated printouts. For other aborted requests only print 7591 * basic details. 7592 */ 7593 scsi_print_command(cmd); 7594 if (!hba->req_abort_count) { 7595 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7596 ufshcd_print_evt_hist(hba); 7597 ufshcd_print_host_state(hba); 7598 ufshcd_print_pwr_info(hba); 7599 ufshcd_print_tr(hba, tag, true); 7600 } else { 7601 ufshcd_print_tr(hba, tag, false); 7602 } 7603 hba->req_abort_count++; 7604 7605 if (!hba->mcq_enabled && !(reg & (1 << tag))) { 7606 /* only execute this code in single doorbell mode */ 7607 dev_err(hba->dev, 7608 "%s: cmd was completed, but without a notifying intr, tag = %d", 7609 __func__, tag); 7610 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7611 goto release; 7612 } 7613 7614 /* 7615 * Task abort to the device W-LUN is illegal. When this command 7616 * will fail, due to spec violation, scsi err handling next step 7617 * will be to send LU reset which, again, is a spec violation. 7618 * To avoid these unnecessary/illegal steps, first we clean up 7619 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7620 * then queue the eh_work and bail. 7621 */ 7622 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7623 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7624 7625 spin_lock_irqsave(host->host_lock, flags); 7626 hba->force_reset = true; 7627 ufshcd_schedule_eh_work(hba); 7628 spin_unlock_irqrestore(host->host_lock, flags); 7629 goto release; 7630 } 7631 7632 if (hba->mcq_enabled) { 7633 /* MCQ mode. Branch off to handle abort for mcq mode */ 7634 err = ufshcd_mcq_abort(cmd); 7635 goto release; 7636 } 7637 7638 /* Skip task abort in case previous aborts failed and report failure */ 7639 if (lrbp->req_abort_skip) { 7640 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7641 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7642 goto release; 7643 } 7644 7645 err = ufshcd_try_to_abort_task(hba, tag); 7646 if (err) { 7647 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7648 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7649 err = FAILED; 7650 goto release; 7651 } 7652 7653 /* 7654 * Clear the corresponding bit from outstanding_reqs since the command 7655 * has been aborted successfully. 7656 */ 7657 spin_lock_irqsave(&hba->outstanding_lock, flags); 7658 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7659 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7660 7661 if (outstanding) 7662 ufshcd_release_scsi_cmd(hba, lrbp); 7663 7664 err = SUCCESS; 7665 7666 release: 7667 /* Matches the ufshcd_hold() call at the start of this function. */ 7668 ufshcd_release(hba); 7669 return err; 7670 } 7671 7672 /** 7673 * ufshcd_host_reset_and_restore - reset and restore host controller 7674 * @hba: per-adapter instance 7675 * 7676 * Note that host controller reset may issue DME_RESET to 7677 * local and remote (device) Uni-Pro stack and the attributes 7678 * are reset to default state. 7679 * 7680 * Return: zero on success, non-zero on failure. 7681 */ 7682 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7683 { 7684 int err; 7685 7686 /* 7687 * Stop the host controller and complete the requests 7688 * cleared by h/w 7689 */ 7690 ufshcd_hba_stop(hba); 7691 hba->silence_err_logs = true; 7692 ufshcd_complete_requests(hba, true); 7693 hba->silence_err_logs = false; 7694 7695 /* scale up clocks to max frequency before full reinitialization */ 7696 ufshcd_scale_clks(hba, ULONG_MAX, true); 7697 7698 err = ufshcd_hba_enable(hba); 7699 7700 /* Establish the link again and restore the device */ 7701 if (!err) 7702 err = ufshcd_probe_hba(hba, false); 7703 7704 if (err) 7705 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7706 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7707 return err; 7708 } 7709 7710 /** 7711 * ufshcd_reset_and_restore - reset and re-initialize host/device 7712 * @hba: per-adapter instance 7713 * 7714 * Reset and recover device, host and re-establish link. This 7715 * is helpful to recover the communication in fatal error conditions. 7716 * 7717 * Return: zero on success, non-zero on failure. 7718 */ 7719 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7720 { 7721 u32 saved_err = 0; 7722 u32 saved_uic_err = 0; 7723 int err = 0; 7724 unsigned long flags; 7725 int retries = MAX_HOST_RESET_RETRIES; 7726 7727 spin_lock_irqsave(hba->host->host_lock, flags); 7728 do { 7729 /* 7730 * This is a fresh start, cache and clear saved error first, 7731 * in case new error generated during reset and restore. 7732 */ 7733 saved_err |= hba->saved_err; 7734 saved_uic_err |= hba->saved_uic_err; 7735 hba->saved_err = 0; 7736 hba->saved_uic_err = 0; 7737 hba->force_reset = false; 7738 hba->ufshcd_state = UFSHCD_STATE_RESET; 7739 spin_unlock_irqrestore(hba->host->host_lock, flags); 7740 7741 /* Reset the attached device */ 7742 ufshcd_device_reset(hba); 7743 7744 err = ufshcd_host_reset_and_restore(hba); 7745 7746 spin_lock_irqsave(hba->host->host_lock, flags); 7747 if (err) 7748 continue; 7749 /* Do not exit unless operational or dead */ 7750 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7751 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7752 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7753 err = -EAGAIN; 7754 } while (err && --retries); 7755 7756 /* 7757 * Inform scsi mid-layer that we did reset and allow to handle 7758 * Unit Attention properly. 7759 */ 7760 scsi_report_bus_reset(hba->host, 0); 7761 if (err) { 7762 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7763 hba->saved_err |= saved_err; 7764 hba->saved_uic_err |= saved_uic_err; 7765 } 7766 spin_unlock_irqrestore(hba->host->host_lock, flags); 7767 7768 return err; 7769 } 7770 7771 /** 7772 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7773 * @cmd: SCSI command pointer 7774 * 7775 * Return: SUCCESS or FAILED. 7776 */ 7777 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7778 { 7779 int err = SUCCESS; 7780 unsigned long flags; 7781 struct ufs_hba *hba; 7782 7783 hba = shost_priv(cmd->device->host); 7784 7785 /* 7786 * If runtime PM sent SSU and got a timeout, scsi_error_handler is 7787 * stuck in this function waiting for flush_work(&hba->eh_work). And 7788 * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do 7789 * ufshcd_link_recovery instead of eh_work to prevent deadlock. 7790 */ 7791 if (hba->pm_op_in_progress) { 7792 if (ufshcd_link_recovery(hba)) 7793 err = FAILED; 7794 7795 return err; 7796 } 7797 7798 spin_lock_irqsave(hba->host->host_lock, flags); 7799 hba->force_reset = true; 7800 ufshcd_schedule_eh_work(hba); 7801 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7802 spin_unlock_irqrestore(hba->host->host_lock, flags); 7803 7804 flush_work(&hba->eh_work); 7805 7806 spin_lock_irqsave(hba->host->host_lock, flags); 7807 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7808 err = FAILED; 7809 spin_unlock_irqrestore(hba->host->host_lock, flags); 7810 7811 return err; 7812 } 7813 7814 /** 7815 * ufshcd_get_max_icc_level - calculate the ICC level 7816 * @sup_curr_uA: max. current supported by the regulator 7817 * @start_scan: row at the desc table to start scan from 7818 * @buff: power descriptor buffer 7819 * 7820 * Return: calculated max ICC level for specific regulator. 7821 */ 7822 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7823 const char *buff) 7824 { 7825 int i; 7826 int curr_uA; 7827 u16 data; 7828 u16 unit; 7829 7830 for (i = start_scan; i >= 0; i--) { 7831 data = get_unaligned_be16(&buff[2 * i]); 7832 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7833 ATTR_ICC_LVL_UNIT_OFFSET; 7834 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7835 switch (unit) { 7836 case UFSHCD_NANO_AMP: 7837 curr_uA = curr_uA / 1000; 7838 break; 7839 case UFSHCD_MILI_AMP: 7840 curr_uA = curr_uA * 1000; 7841 break; 7842 case UFSHCD_AMP: 7843 curr_uA = curr_uA * 1000 * 1000; 7844 break; 7845 case UFSHCD_MICRO_AMP: 7846 default: 7847 break; 7848 } 7849 if (sup_curr_uA >= curr_uA) 7850 break; 7851 } 7852 if (i < 0) { 7853 i = 0; 7854 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7855 } 7856 7857 return (u32)i; 7858 } 7859 7860 /** 7861 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7862 * In case regulators are not initialized we'll return 0 7863 * @hba: per-adapter instance 7864 * @desc_buf: power descriptor buffer to extract ICC levels from. 7865 * 7866 * Return: calculated ICC level. 7867 */ 7868 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7869 const u8 *desc_buf) 7870 { 7871 u32 icc_level = 0; 7872 7873 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7874 !hba->vreg_info.vccq2) { 7875 /* 7876 * Using dev_dbg to avoid messages during runtime PM to avoid 7877 * never-ending cycles of messages written back to storage by 7878 * user space causing runtime resume, causing more messages and 7879 * so on. 7880 */ 7881 dev_dbg(hba->dev, 7882 "%s: Regulator capability was not set, actvIccLevel=%d", 7883 __func__, icc_level); 7884 goto out; 7885 } 7886 7887 if (hba->vreg_info.vcc->max_uA) 7888 icc_level = ufshcd_get_max_icc_level( 7889 hba->vreg_info.vcc->max_uA, 7890 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7891 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7892 7893 if (hba->vreg_info.vccq->max_uA) 7894 icc_level = ufshcd_get_max_icc_level( 7895 hba->vreg_info.vccq->max_uA, 7896 icc_level, 7897 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7898 7899 if (hba->vreg_info.vccq2->max_uA) 7900 icc_level = ufshcd_get_max_icc_level( 7901 hba->vreg_info.vccq2->max_uA, 7902 icc_level, 7903 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7904 out: 7905 return icc_level; 7906 } 7907 7908 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7909 { 7910 int ret; 7911 u8 *desc_buf; 7912 u32 icc_level; 7913 7914 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7915 if (!desc_buf) 7916 return; 7917 7918 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7919 desc_buf, QUERY_DESC_MAX_SIZE); 7920 if (ret) { 7921 dev_err(hba->dev, 7922 "%s: Failed reading power descriptor ret = %d", 7923 __func__, ret); 7924 goto out; 7925 } 7926 7927 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7928 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7929 7930 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7931 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7932 7933 if (ret) 7934 dev_err(hba->dev, 7935 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7936 __func__, icc_level, ret); 7937 7938 out: 7939 kfree(desc_buf); 7940 } 7941 7942 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7943 { 7944 struct Scsi_Host *shost = sdev->host; 7945 7946 scsi_autopm_get_device(sdev); 7947 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7948 if (sdev->rpm_autosuspend) 7949 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7950 shost->rpm_autosuspend_delay); 7951 scsi_autopm_put_device(sdev); 7952 } 7953 7954 /** 7955 * ufshcd_scsi_add_wlus - Adds required W-LUs 7956 * @hba: per-adapter instance 7957 * 7958 * UFS device specification requires the UFS devices to support 4 well known 7959 * logical units: 7960 * "REPORT_LUNS" (address: 01h) 7961 * "UFS Device" (address: 50h) 7962 * "RPMB" (address: 44h) 7963 * "BOOT" (address: 30h) 7964 * UFS device's power management needs to be controlled by "POWER CONDITION" 7965 * field of SSU (START STOP UNIT) command. But this "power condition" field 7966 * will take effect only when its sent to "UFS device" well known logical unit 7967 * hence we require the scsi_device instance to represent this logical unit in 7968 * order for the UFS host driver to send the SSU command for power management. 7969 * 7970 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 7971 * Block) LU so user space process can control this LU. User space may also 7972 * want to have access to BOOT LU. 7973 * 7974 * This function adds scsi device instances for each of all well known LUs 7975 * (except "REPORT LUNS" LU). 7976 * 7977 * Return: zero on success (all required W-LUs are added successfully), 7978 * non-zero error value on failure (if failed to add any of the required W-LU). 7979 */ 7980 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 7981 { 7982 int ret = 0; 7983 struct scsi_device *sdev_boot, *sdev_rpmb; 7984 7985 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 7986 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 7987 if (IS_ERR(hba->ufs_device_wlun)) { 7988 ret = PTR_ERR(hba->ufs_device_wlun); 7989 hba->ufs_device_wlun = NULL; 7990 goto out; 7991 } 7992 scsi_device_put(hba->ufs_device_wlun); 7993 7994 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 7995 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 7996 if (IS_ERR(sdev_rpmb)) { 7997 ret = PTR_ERR(sdev_rpmb); 7998 goto remove_ufs_device_wlun; 7999 } 8000 ufshcd_blk_pm_runtime_init(sdev_rpmb); 8001 scsi_device_put(sdev_rpmb); 8002 8003 sdev_boot = __scsi_add_device(hba->host, 0, 0, 8004 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 8005 if (IS_ERR(sdev_boot)) { 8006 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 8007 } else { 8008 ufshcd_blk_pm_runtime_init(sdev_boot); 8009 scsi_device_put(sdev_boot); 8010 } 8011 goto out; 8012 8013 remove_ufs_device_wlun: 8014 scsi_remove_device(hba->ufs_device_wlun); 8015 out: 8016 return ret; 8017 } 8018 8019 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 8020 { 8021 struct ufs_dev_info *dev_info = &hba->dev_info; 8022 u8 lun; 8023 u32 d_lu_wb_buf_alloc; 8024 u32 ext_ufs_feature; 8025 8026 if (!ufshcd_is_wb_allowed(hba)) 8027 return; 8028 8029 /* 8030 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 8031 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 8032 * enabled 8033 */ 8034 if (!(dev_info->wspecversion >= 0x310 || 8035 dev_info->wspecversion == 0x220 || 8036 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 8037 goto wb_disabled; 8038 8039 ext_ufs_feature = get_unaligned_be32(desc_buf + 8040 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8041 8042 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 8043 goto wb_disabled; 8044 8045 /* 8046 * WB may be supported but not configured while provisioning. The spec 8047 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 8048 * buffer configured. 8049 */ 8050 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 8051 8052 dev_info->b_presrv_uspc_en = 8053 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 8054 8055 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 8056 if (!get_unaligned_be32(desc_buf + 8057 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 8058 goto wb_disabled; 8059 } else { 8060 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 8061 d_lu_wb_buf_alloc = 0; 8062 ufshcd_read_unit_desc_param(hba, 8063 lun, 8064 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 8065 (u8 *)&d_lu_wb_buf_alloc, 8066 sizeof(d_lu_wb_buf_alloc)); 8067 if (d_lu_wb_buf_alloc) { 8068 dev_info->wb_dedicated_lu = lun; 8069 break; 8070 } 8071 } 8072 8073 if (!d_lu_wb_buf_alloc) 8074 goto wb_disabled; 8075 } 8076 8077 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8078 goto wb_disabled; 8079 8080 return; 8081 8082 wb_disabled: 8083 hba->caps &= ~UFSHCD_CAP_WB_EN; 8084 } 8085 8086 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8087 { 8088 struct ufs_dev_info *dev_info = &hba->dev_info; 8089 u32 ext_ufs_feature; 8090 u8 mask = 0; 8091 8092 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8093 return; 8094 8095 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8096 8097 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8098 mask |= MASK_EE_TOO_LOW_TEMP; 8099 8100 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8101 mask |= MASK_EE_TOO_HIGH_TEMP; 8102 8103 if (mask) { 8104 ufshcd_enable_ee(hba, mask); 8105 ufs_hwmon_probe(hba, mask); 8106 } 8107 } 8108 8109 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8110 { 8111 struct ufs_dev_info *dev_info = &hba->dev_info; 8112 u32 ext_ufs_feature; 8113 u32 ext_iid_en = 0; 8114 int err; 8115 8116 /* Only UFS-4.0 and above may support EXT_IID */ 8117 if (dev_info->wspecversion < 0x400) 8118 goto out; 8119 8120 ext_ufs_feature = get_unaligned_be32(desc_buf + 8121 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8122 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8123 goto out; 8124 8125 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8126 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8127 if (err) 8128 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8129 8130 out: 8131 dev_info->b_ext_iid_en = ext_iid_en; 8132 } 8133 8134 static void ufshcd_set_rtt(struct ufs_hba *hba) 8135 { 8136 struct ufs_dev_info *dev_info = &hba->dev_info; 8137 u32 rtt = 0; 8138 u32 dev_rtt = 0; 8139 int host_rtt_cap = hba->vops && hba->vops->max_num_rtt ? 8140 hba->vops->max_num_rtt : hba->nortt; 8141 8142 /* RTT override makes sense only for UFS-4.0 and above */ 8143 if (dev_info->wspecversion < 0x400) 8144 return; 8145 8146 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8147 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &dev_rtt)) { 8148 dev_err(hba->dev, "failed reading bMaxNumOfRTT\n"); 8149 return; 8150 } 8151 8152 /* do not override if it was already written */ 8153 if (dev_rtt != DEFAULT_MAX_NUM_RTT) 8154 return; 8155 8156 rtt = min_t(int, dev_info->rtt_cap, host_rtt_cap); 8157 8158 if (rtt == dev_rtt) 8159 return; 8160 8161 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8162 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &rtt)) 8163 dev_err(hba->dev, "failed writing bMaxNumOfRTT\n"); 8164 } 8165 8166 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8167 const struct ufs_dev_quirk *fixups) 8168 { 8169 const struct ufs_dev_quirk *f; 8170 struct ufs_dev_info *dev_info = &hba->dev_info; 8171 8172 if (!fixups) 8173 return; 8174 8175 for (f = fixups; f->quirk; f++) { 8176 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8177 f->wmanufacturerid == UFS_ANY_VENDOR) && 8178 ((dev_info->model && 8179 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8180 !strcmp(f->model, UFS_ANY_MODEL))) 8181 hba->dev_quirks |= f->quirk; 8182 } 8183 } 8184 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8185 8186 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8187 { 8188 /* fix by general quirk table */ 8189 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8190 8191 /* allow vendors to fix quirks */ 8192 ufshcd_vops_fixup_dev_quirks(hba); 8193 } 8194 8195 static void ufshcd_update_rtc(struct ufs_hba *hba) 8196 { 8197 struct timespec64 ts64; 8198 int err; 8199 u32 val; 8200 8201 ktime_get_real_ts64(&ts64); 8202 8203 if (ts64.tv_sec < hba->dev_info.rtc_time_baseline) { 8204 dev_warn_once(hba->dev, "%s: Current time precedes previous setting!\n", __func__); 8205 return; 8206 } 8207 8208 /* 8209 * The Absolute RTC mode has a 136-year limit, spanning from 2010 to 2146. If a time beyond 8210 * 2146 is required, it is recommended to choose the relative RTC mode. 8211 */ 8212 val = ts64.tv_sec - hba->dev_info.rtc_time_baseline; 8213 8214 ufshcd_rpm_get_sync(hba); 8215 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_SECONDS_PASSED, 8216 0, 0, &val); 8217 ufshcd_rpm_put_sync(hba); 8218 8219 if (err) 8220 dev_err(hba->dev, "%s: Failed to update rtc %d\n", __func__, err); 8221 else if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 8222 hba->dev_info.rtc_time_baseline = ts64.tv_sec; 8223 } 8224 8225 static void ufshcd_rtc_work(struct work_struct *work) 8226 { 8227 struct ufs_hba *hba; 8228 8229 hba = container_of(to_delayed_work(work), struct ufs_hba, ufs_rtc_update_work); 8230 8231 /* Update RTC only when there are no requests in progress and UFSHCI is operational */ 8232 if (!ufshcd_is_ufs_dev_busy(hba) && hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) 8233 ufshcd_update_rtc(hba); 8234 8235 if (ufshcd_is_ufs_dev_active(hba) && hba->dev_info.rtc_update_period) 8236 schedule_delayed_work(&hba->ufs_rtc_update_work, 8237 msecs_to_jiffies(hba->dev_info.rtc_update_period)); 8238 } 8239 8240 static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf) 8241 { 8242 u16 periodic_rtc_update = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_FRQ_RTC]); 8243 struct ufs_dev_info *dev_info = &hba->dev_info; 8244 8245 if (periodic_rtc_update & UFS_RTC_TIME_BASELINE) { 8246 dev_info->rtc_type = UFS_RTC_ABSOLUTE; 8247 8248 /* 8249 * The concept of measuring time in Linux as the number of seconds elapsed since 8250 * 00:00:00 UTC on January 1, 1970, and UFS ABS RTC is elapsed from January 1st 8251 * 2010 00:00, here we need to adjust ABS baseline. 8252 */ 8253 dev_info->rtc_time_baseline = mktime64(2010, 1, 1, 0, 0, 0) - 8254 mktime64(1970, 1, 1, 0, 0, 0); 8255 } else { 8256 dev_info->rtc_type = UFS_RTC_RELATIVE; 8257 dev_info->rtc_time_baseline = 0; 8258 } 8259 8260 /* 8261 * We ignore TIME_PERIOD defined in wPeriodicRTCUpdate because Spec does not clearly state 8262 * how to calculate the specific update period for each time unit. And we disable periodic 8263 * RTC update work, let user configure by sysfs node according to specific circumstance. 8264 */ 8265 dev_info->rtc_update_period = 0; 8266 } 8267 8268 static int ufs_get_device_desc(struct ufs_hba *hba) 8269 { 8270 int err; 8271 u8 model_index; 8272 u8 *desc_buf; 8273 struct ufs_dev_info *dev_info = &hba->dev_info; 8274 8275 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8276 if (!desc_buf) { 8277 err = -ENOMEM; 8278 goto out; 8279 } 8280 8281 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8282 QUERY_DESC_MAX_SIZE); 8283 if (err) { 8284 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8285 __func__, err); 8286 goto out; 8287 } 8288 8289 /* 8290 * getting vendor (manufacturerID) and Bank Index in big endian 8291 * format 8292 */ 8293 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8294 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8295 8296 /* getting Specification Version in big endian format */ 8297 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8298 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8299 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8300 8301 dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP]; 8302 8303 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8304 8305 err = ufshcd_read_string_desc(hba, model_index, 8306 &dev_info->model, SD_ASCII_STD); 8307 if (err < 0) { 8308 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8309 __func__, err); 8310 goto out; 8311 } 8312 8313 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8314 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8315 8316 ufs_fixup_device_setup(hba); 8317 8318 ufshcd_wb_probe(hba, desc_buf); 8319 8320 ufshcd_temp_notif_probe(hba, desc_buf); 8321 8322 ufs_init_rtc(hba, desc_buf); 8323 8324 if (hba->ext_iid_sup) 8325 ufshcd_ext_iid_probe(hba, desc_buf); 8326 8327 /* 8328 * ufshcd_read_string_desc returns size of the string 8329 * reset the error value 8330 */ 8331 err = 0; 8332 8333 out: 8334 kfree(desc_buf); 8335 return err; 8336 } 8337 8338 static void ufs_put_device_desc(struct ufs_hba *hba) 8339 { 8340 struct ufs_dev_info *dev_info = &hba->dev_info; 8341 8342 kfree(dev_info->model); 8343 dev_info->model = NULL; 8344 } 8345 8346 /** 8347 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8348 * less than device PA_TACTIVATE time. 8349 * @hba: per-adapter instance 8350 * 8351 * Some UFS devices require host PA_TACTIVATE to be lower than device 8352 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8353 * for such devices. 8354 * 8355 * Return: zero on success, non-zero error value on failure. 8356 */ 8357 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8358 { 8359 int ret = 0; 8360 u32 granularity, peer_granularity; 8361 u32 pa_tactivate, peer_pa_tactivate; 8362 u32 pa_tactivate_us, peer_pa_tactivate_us; 8363 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8364 8365 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8366 &granularity); 8367 if (ret) 8368 goto out; 8369 8370 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8371 &peer_granularity); 8372 if (ret) 8373 goto out; 8374 8375 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8376 (granularity > PA_GRANULARITY_MAX_VAL)) { 8377 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8378 __func__, granularity); 8379 return -EINVAL; 8380 } 8381 8382 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8383 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8384 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8385 __func__, peer_granularity); 8386 return -EINVAL; 8387 } 8388 8389 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8390 if (ret) 8391 goto out; 8392 8393 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8394 &peer_pa_tactivate); 8395 if (ret) 8396 goto out; 8397 8398 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8399 peer_pa_tactivate_us = peer_pa_tactivate * 8400 gran_to_us_table[peer_granularity - 1]; 8401 8402 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8403 u32 new_peer_pa_tactivate; 8404 8405 new_peer_pa_tactivate = pa_tactivate_us / 8406 gran_to_us_table[peer_granularity - 1]; 8407 new_peer_pa_tactivate++; 8408 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8409 new_peer_pa_tactivate); 8410 } 8411 8412 out: 8413 return ret; 8414 } 8415 8416 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8417 { 8418 ufshcd_vops_apply_dev_quirks(hba); 8419 8420 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8421 /* set 1ms timeout for PA_TACTIVATE */ 8422 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8423 8424 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8425 ufshcd_quirk_tune_host_pa_tactivate(hba); 8426 } 8427 8428 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8429 { 8430 hba->ufs_stats.hibern8_exit_cnt = 0; 8431 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8432 hba->req_abort_count = 0; 8433 } 8434 8435 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8436 { 8437 int err; 8438 u8 *desc_buf; 8439 8440 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8441 if (!desc_buf) { 8442 err = -ENOMEM; 8443 goto out; 8444 } 8445 8446 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8447 desc_buf, QUERY_DESC_MAX_SIZE); 8448 if (err) { 8449 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8450 __func__, err); 8451 goto out; 8452 } 8453 8454 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8455 hba->dev_info.max_lu_supported = 32; 8456 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8457 hba->dev_info.max_lu_supported = 8; 8458 8459 out: 8460 kfree(desc_buf); 8461 return err; 8462 } 8463 8464 struct ufs_ref_clk { 8465 unsigned long freq_hz; 8466 enum ufs_ref_clk_freq val; 8467 }; 8468 8469 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8470 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8471 {26000000, REF_CLK_FREQ_26_MHZ}, 8472 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8473 {52000000, REF_CLK_FREQ_52_MHZ}, 8474 {0, REF_CLK_FREQ_INVAL}, 8475 }; 8476 8477 static enum ufs_ref_clk_freq 8478 ufs_get_bref_clk_from_hz(unsigned long freq) 8479 { 8480 int i; 8481 8482 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8483 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8484 return ufs_ref_clk_freqs[i].val; 8485 8486 return REF_CLK_FREQ_INVAL; 8487 } 8488 8489 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8490 { 8491 unsigned long freq; 8492 8493 freq = clk_get_rate(refclk); 8494 8495 hba->dev_ref_clk_freq = 8496 ufs_get_bref_clk_from_hz(freq); 8497 8498 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8499 dev_err(hba->dev, 8500 "invalid ref_clk setting = %ld\n", freq); 8501 } 8502 8503 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8504 { 8505 int err; 8506 u32 ref_clk; 8507 u32 freq = hba->dev_ref_clk_freq; 8508 8509 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8510 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8511 8512 if (err) { 8513 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8514 err); 8515 goto out; 8516 } 8517 8518 if (ref_clk == freq) 8519 goto out; /* nothing to update */ 8520 8521 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8522 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8523 8524 if (err) { 8525 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8526 ufs_ref_clk_freqs[freq].freq_hz); 8527 goto out; 8528 } 8529 8530 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8531 ufs_ref_clk_freqs[freq].freq_hz); 8532 8533 out: 8534 return err; 8535 } 8536 8537 static int ufshcd_device_params_init(struct ufs_hba *hba) 8538 { 8539 bool flag; 8540 int ret; 8541 8542 /* Init UFS geometry descriptor related parameters */ 8543 ret = ufshcd_device_geo_params_init(hba); 8544 if (ret) 8545 goto out; 8546 8547 /* Check and apply UFS device quirks */ 8548 ret = ufs_get_device_desc(hba); 8549 if (ret) { 8550 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8551 __func__, ret); 8552 goto out; 8553 } 8554 8555 ufshcd_set_rtt(hba); 8556 8557 ufshcd_get_ref_clk_gating_wait(hba); 8558 8559 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8560 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8561 hba->dev_info.f_power_on_wp_en = flag; 8562 8563 /* Probe maximum power mode co-supported by both UFS host and device */ 8564 if (ufshcd_get_max_pwr_mode(hba)) 8565 dev_err(hba->dev, 8566 "%s: Failed getting max supported power mode\n", 8567 __func__); 8568 out: 8569 return ret; 8570 } 8571 8572 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8573 { 8574 int err; 8575 struct ufs_query_req *request = NULL; 8576 struct ufs_query_res *response = NULL; 8577 struct ufs_dev_info *dev_info = &hba->dev_info; 8578 struct utp_upiu_query_v4_0 *upiu_data; 8579 8580 if (dev_info->wspecversion < 0x400) 8581 return; 8582 8583 ufshcd_dev_man_lock(hba); 8584 8585 ufshcd_init_query(hba, &request, &response, 8586 UPIU_QUERY_OPCODE_WRITE_ATTR, 8587 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8588 8589 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8590 8591 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8592 8593 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8594 8595 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8596 8597 if (err) 8598 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8599 __func__, err); 8600 8601 ufshcd_dev_man_unlock(hba); 8602 } 8603 8604 /** 8605 * ufshcd_add_lus - probe and add UFS logical units 8606 * @hba: per-adapter instance 8607 * 8608 * Return: 0 upon success; < 0 upon failure. 8609 */ 8610 static int ufshcd_add_lus(struct ufs_hba *hba) 8611 { 8612 int ret; 8613 8614 /* Add required well known logical units to scsi mid layer */ 8615 ret = ufshcd_scsi_add_wlus(hba); 8616 if (ret) 8617 goto out; 8618 8619 /* Initialize devfreq after UFS device is detected */ 8620 if (ufshcd_is_clkscaling_supported(hba)) { 8621 memcpy(&hba->clk_scaling.saved_pwr_info, 8622 &hba->pwr_info, 8623 sizeof(struct ufs_pa_layer_attr)); 8624 hba->clk_scaling.is_allowed = true; 8625 8626 ret = ufshcd_devfreq_init(hba); 8627 if (ret) 8628 goto out; 8629 8630 hba->clk_scaling.is_enabled = true; 8631 ufshcd_init_clk_scaling_sysfs(hba); 8632 } 8633 8634 ufs_bsg_probe(hba); 8635 scsi_scan_host(hba->host); 8636 8637 out: 8638 return ret; 8639 } 8640 8641 /* SDB - Single Doorbell */ 8642 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8643 { 8644 size_t ucdl_size, utrdl_size; 8645 8646 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8647 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8648 hba->ucdl_dma_addr); 8649 8650 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8651 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8652 hba->utrdl_dma_addr); 8653 8654 devm_kfree(hba->dev, hba->lrb); 8655 } 8656 8657 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8658 { 8659 int ret; 8660 int old_nutrs = hba->nutrs; 8661 8662 ret = ufshcd_mcq_decide_queue_depth(hba); 8663 if (ret < 0) 8664 return ret; 8665 8666 hba->nutrs = ret; 8667 ret = ufshcd_mcq_init(hba); 8668 if (ret) 8669 goto err; 8670 8671 /* 8672 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8673 * Number of supported tags in MCQ mode may be larger than SDB mode. 8674 */ 8675 if (hba->nutrs != old_nutrs) { 8676 ufshcd_release_sdb_queue(hba, old_nutrs); 8677 ret = ufshcd_memory_alloc(hba); 8678 if (ret) 8679 goto err; 8680 ufshcd_host_memory_configure(hba); 8681 } 8682 8683 ret = ufshcd_mcq_memory_alloc(hba); 8684 if (ret) 8685 goto err; 8686 8687 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8688 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8689 8690 return 0; 8691 err: 8692 hba->nutrs = old_nutrs; 8693 return ret; 8694 } 8695 8696 static void ufshcd_config_mcq(struct ufs_hba *hba) 8697 { 8698 int ret; 8699 u32 intrs; 8700 8701 ret = ufshcd_mcq_vops_config_esi(hba); 8702 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8703 8704 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8705 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8706 intrs &= ~MCQ_CQ_EVENT_STATUS; 8707 ufshcd_enable_intr(hba, intrs); 8708 ufshcd_mcq_make_queues_operational(hba); 8709 ufshcd_mcq_config_mac(hba, hba->nutrs); 8710 8711 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8712 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8713 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8714 hba->nutrs); 8715 } 8716 8717 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8718 { 8719 int ret; 8720 struct Scsi_Host *host = hba->host; 8721 8722 hba->ufshcd_state = UFSHCD_STATE_RESET; 8723 8724 ret = ufshcd_link_startup(hba); 8725 if (ret) 8726 return ret; 8727 8728 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8729 return ret; 8730 8731 /* Debug counters initialization */ 8732 ufshcd_clear_dbg_ufs_stats(hba); 8733 8734 /* UniPro link is active now */ 8735 ufshcd_set_link_active(hba); 8736 8737 /* Reconfigure MCQ upon reset */ 8738 if (hba->mcq_enabled && !init_dev_params) { 8739 ufshcd_config_mcq(hba); 8740 ufshcd_mcq_enable(hba); 8741 } 8742 8743 /* Verify device initialization by sending NOP OUT UPIU */ 8744 ret = ufshcd_verify_dev_init(hba); 8745 if (ret) 8746 return ret; 8747 8748 /* Initiate UFS initialization, and waiting until completion */ 8749 ret = ufshcd_complete_dev_init(hba); 8750 if (ret) 8751 return ret; 8752 8753 /* 8754 * Initialize UFS device parameters used by driver, these 8755 * parameters are associated with UFS descriptors. 8756 */ 8757 if (init_dev_params) { 8758 ret = ufshcd_device_params_init(hba); 8759 if (ret) 8760 return ret; 8761 if (is_mcq_supported(hba) && !hba->scsi_host_added) { 8762 ufshcd_mcq_enable(hba); 8763 ret = ufshcd_alloc_mcq(hba); 8764 if (!ret) { 8765 ufshcd_config_mcq(hba); 8766 } else { 8767 /* Continue with SDB mode */ 8768 ufshcd_mcq_disable(hba); 8769 use_mcq_mode = false; 8770 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 8771 ret); 8772 } 8773 ret = scsi_add_host(host, hba->dev); 8774 if (ret) { 8775 dev_err(hba->dev, "scsi_add_host failed\n"); 8776 return ret; 8777 } 8778 hba->scsi_host_added = true; 8779 } else if (is_mcq_supported(hba)) { 8780 /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */ 8781 ufshcd_config_mcq(hba); 8782 ufshcd_mcq_enable(hba); 8783 } 8784 } 8785 8786 ufshcd_tune_unipro_params(hba); 8787 8788 /* UFS device is also active now */ 8789 ufshcd_set_ufs_dev_active(hba); 8790 ufshcd_force_reset_auto_bkops(hba); 8791 8792 ufshcd_set_timestamp_attr(hba); 8793 schedule_delayed_work(&hba->ufs_rtc_update_work, 8794 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 8795 8796 /* Gear up to HS gear if supported */ 8797 if (hba->max_pwr_info.is_valid) { 8798 /* 8799 * Set the right value to bRefClkFreq before attempting to 8800 * switch to HS gears. 8801 */ 8802 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8803 ufshcd_set_dev_ref_clk(hba); 8804 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8805 if (ret) { 8806 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8807 __func__, ret); 8808 return ret; 8809 } 8810 } 8811 8812 return 0; 8813 } 8814 8815 /** 8816 * ufshcd_probe_hba - probe hba to detect device and initialize it 8817 * @hba: per-adapter instance 8818 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8819 * 8820 * Execute link-startup and verify device initialization 8821 * 8822 * Return: 0 upon success; < 0 upon failure. 8823 */ 8824 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8825 { 8826 ktime_t start = ktime_get(); 8827 unsigned long flags; 8828 int ret; 8829 8830 ret = ufshcd_device_init(hba, init_dev_params); 8831 if (ret) 8832 goto out; 8833 8834 if (!hba->pm_op_in_progress && 8835 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8836 /* Reset the device and controller before doing reinit */ 8837 ufshcd_device_reset(hba); 8838 ufs_put_device_desc(hba); 8839 ufshcd_hba_stop(hba); 8840 ufshcd_vops_reinit_notify(hba); 8841 ret = ufshcd_hba_enable(hba); 8842 if (ret) { 8843 dev_err(hba->dev, "Host controller enable failed\n"); 8844 ufshcd_print_evt_hist(hba); 8845 ufshcd_print_host_state(hba); 8846 goto out; 8847 } 8848 8849 /* Reinit the device */ 8850 ret = ufshcd_device_init(hba, init_dev_params); 8851 if (ret) 8852 goto out; 8853 } 8854 8855 ufshcd_print_pwr_info(hba); 8856 8857 /* 8858 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8859 * and for removable UFS card as well, hence always set the parameter. 8860 * Note: Error handler may issue the device reset hence resetting 8861 * bActiveICCLevel as well so it is always safe to set this here. 8862 */ 8863 ufshcd_set_active_icc_lvl(hba); 8864 8865 /* Enable UFS Write Booster if supported */ 8866 ufshcd_configure_wb(hba); 8867 8868 if (hba->ee_usr_mask) 8869 ufshcd_write_ee_control(hba); 8870 ufshcd_configure_auto_hibern8(hba); 8871 8872 out: 8873 spin_lock_irqsave(hba->host->host_lock, flags); 8874 if (ret) 8875 hba->ufshcd_state = UFSHCD_STATE_ERROR; 8876 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 8877 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 8878 spin_unlock_irqrestore(hba->host->host_lock, flags); 8879 8880 trace_ufshcd_init(dev_name(hba->dev), ret, 8881 ktime_to_us(ktime_sub(ktime_get(), start)), 8882 hba->curr_dev_pwr_mode, hba->uic_link_state); 8883 return ret; 8884 } 8885 8886 /** 8887 * ufshcd_async_scan - asynchronous execution for probing hba 8888 * @data: data pointer to pass to this function 8889 * @cookie: cookie data 8890 */ 8891 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8892 { 8893 struct ufs_hba *hba = (struct ufs_hba *)data; 8894 int ret; 8895 8896 down(&hba->host_sem); 8897 /* Initialize hba, detect and initialize UFS device */ 8898 ret = ufshcd_probe_hba(hba, true); 8899 up(&hba->host_sem); 8900 if (ret) 8901 goto out; 8902 8903 /* Probe and add UFS logical units */ 8904 ret = ufshcd_add_lus(hba); 8905 8906 out: 8907 pm_runtime_put_sync(hba->dev); 8908 8909 if (ret) 8910 dev_err(hba->dev, "%s failed: %d\n", __func__, ret); 8911 } 8912 8913 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8914 { 8915 struct ufs_hba *hba = shost_priv(scmd->device->host); 8916 8917 if (!hba->system_suspending) { 8918 /* Activate the error handler in the SCSI core. */ 8919 return SCSI_EH_NOT_HANDLED; 8920 } 8921 8922 /* 8923 * If we get here we know that no TMFs are outstanding and also that 8924 * the only pending command is a START STOP UNIT command. Handle the 8925 * timeout of that command directly to prevent a deadlock between 8926 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8927 */ 8928 ufshcd_link_recovery(hba); 8929 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8930 __func__, hba->outstanding_tasks); 8931 8932 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8933 } 8934 8935 static const struct attribute_group *ufshcd_driver_groups[] = { 8936 &ufs_sysfs_unit_descriptor_group, 8937 &ufs_sysfs_lun_attributes_group, 8938 NULL, 8939 }; 8940 8941 static struct ufs_hba_variant_params ufs_hba_vps = { 8942 .hba_enable_delay_us = 1000, 8943 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8944 .devfreq_profile.polling_ms = 100, 8945 .devfreq_profile.target = ufshcd_devfreq_target, 8946 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8947 .ondemand_data.upthreshold = 70, 8948 .ondemand_data.downdifferential = 5, 8949 }; 8950 8951 static const struct scsi_host_template ufshcd_driver_template = { 8952 .module = THIS_MODULE, 8953 .name = UFSHCD, 8954 .proc_name = UFSHCD, 8955 .map_queues = ufshcd_map_queues, 8956 .queuecommand = ufshcd_queuecommand, 8957 .mq_poll = ufshcd_poll, 8958 .slave_alloc = ufshcd_slave_alloc, 8959 .device_configure = ufshcd_device_configure, 8960 .slave_destroy = ufshcd_slave_destroy, 8961 .change_queue_depth = ufshcd_change_queue_depth, 8962 .eh_abort_handler = ufshcd_abort, 8963 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8964 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8965 .eh_timed_out = ufshcd_eh_timed_out, 8966 .this_id = -1, 8967 .sg_tablesize = SG_ALL, 8968 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8969 .max_sectors = SZ_1M / SECTOR_SIZE, 8970 .max_host_blocked = 1, 8971 .track_queue_depth = 1, 8972 .skip_settle_delay = 1, 8973 .sdev_groups = ufshcd_driver_groups, 8974 }; 8975 8976 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8977 int ua) 8978 { 8979 int ret; 8980 8981 if (!vreg) 8982 return 0; 8983 8984 /* 8985 * "set_load" operation shall be required on those regulators 8986 * which specifically configured current limitation. Otherwise 8987 * zero max_uA may cause unexpected behavior when regulator is 8988 * enabled or set as high power mode. 8989 */ 8990 if (!vreg->max_uA) 8991 return 0; 8992 8993 ret = regulator_set_load(vreg->reg, ua); 8994 if (ret < 0) { 8995 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 8996 __func__, vreg->name, ua, ret); 8997 } 8998 8999 return ret; 9000 } 9001 9002 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 9003 struct ufs_vreg *vreg) 9004 { 9005 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 9006 } 9007 9008 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 9009 struct ufs_vreg *vreg) 9010 { 9011 if (!vreg) 9012 return 0; 9013 9014 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 9015 } 9016 9017 static int ufshcd_config_vreg(struct device *dev, 9018 struct ufs_vreg *vreg, bool on) 9019 { 9020 if (regulator_count_voltages(vreg->reg) <= 0) 9021 return 0; 9022 9023 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 9024 } 9025 9026 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 9027 { 9028 int ret = 0; 9029 9030 if (!vreg || vreg->enabled) 9031 goto out; 9032 9033 ret = ufshcd_config_vreg(dev, vreg, true); 9034 if (!ret) 9035 ret = regulator_enable(vreg->reg); 9036 9037 if (!ret) 9038 vreg->enabled = true; 9039 else 9040 dev_err(dev, "%s: %s enable failed, err=%d\n", 9041 __func__, vreg->name, ret); 9042 out: 9043 return ret; 9044 } 9045 9046 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 9047 { 9048 int ret = 0; 9049 9050 if (!vreg || !vreg->enabled || vreg->always_on) 9051 goto out; 9052 9053 ret = regulator_disable(vreg->reg); 9054 9055 if (!ret) { 9056 /* ignore errors on applying disable config */ 9057 ufshcd_config_vreg(dev, vreg, false); 9058 vreg->enabled = false; 9059 } else { 9060 dev_err(dev, "%s: %s disable failed, err=%d\n", 9061 __func__, vreg->name, ret); 9062 } 9063 out: 9064 return ret; 9065 } 9066 9067 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 9068 { 9069 int ret = 0; 9070 struct device *dev = hba->dev; 9071 struct ufs_vreg_info *info = &hba->vreg_info; 9072 9073 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 9074 if (ret) 9075 goto out; 9076 9077 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 9078 if (ret) 9079 goto out; 9080 9081 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 9082 9083 out: 9084 if (ret) { 9085 ufshcd_toggle_vreg(dev, info->vccq2, false); 9086 ufshcd_toggle_vreg(dev, info->vccq, false); 9087 ufshcd_toggle_vreg(dev, info->vcc, false); 9088 } 9089 return ret; 9090 } 9091 9092 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9093 { 9094 struct ufs_vreg_info *info = &hba->vreg_info; 9095 9096 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9097 } 9098 9099 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9100 { 9101 int ret = 0; 9102 9103 if (!vreg) 9104 goto out; 9105 9106 vreg->reg = devm_regulator_get(dev, vreg->name); 9107 if (IS_ERR(vreg->reg)) { 9108 ret = PTR_ERR(vreg->reg); 9109 dev_err(dev, "%s: %s get failed, err=%d\n", 9110 __func__, vreg->name, ret); 9111 } 9112 out: 9113 return ret; 9114 } 9115 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9116 9117 static int ufshcd_init_vreg(struct ufs_hba *hba) 9118 { 9119 int ret = 0; 9120 struct device *dev = hba->dev; 9121 struct ufs_vreg_info *info = &hba->vreg_info; 9122 9123 ret = ufshcd_get_vreg(dev, info->vcc); 9124 if (ret) 9125 goto out; 9126 9127 ret = ufshcd_get_vreg(dev, info->vccq); 9128 if (!ret) 9129 ret = ufshcd_get_vreg(dev, info->vccq2); 9130 out: 9131 return ret; 9132 } 9133 9134 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9135 { 9136 struct ufs_vreg_info *info = &hba->vreg_info; 9137 9138 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9139 } 9140 9141 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9142 { 9143 int ret = 0; 9144 struct ufs_clk_info *clki; 9145 struct list_head *head = &hba->clk_list_head; 9146 unsigned long flags; 9147 ktime_t start = ktime_get(); 9148 bool clk_state_changed = false; 9149 9150 if (list_empty(head)) 9151 goto out; 9152 9153 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9154 if (ret) 9155 return ret; 9156 9157 list_for_each_entry(clki, head, list) { 9158 if (!IS_ERR_OR_NULL(clki->clk)) { 9159 /* 9160 * Don't disable clocks which are needed 9161 * to keep the link active. 9162 */ 9163 if (ufshcd_is_link_active(hba) && 9164 clki->keep_link_active) 9165 continue; 9166 9167 clk_state_changed = on ^ clki->enabled; 9168 if (on && !clki->enabled) { 9169 ret = clk_prepare_enable(clki->clk); 9170 if (ret) { 9171 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9172 __func__, clki->name, ret); 9173 goto out; 9174 } 9175 } else if (!on && clki->enabled) { 9176 clk_disable_unprepare(clki->clk); 9177 } 9178 clki->enabled = on; 9179 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9180 clki->name, on ? "en" : "dis"); 9181 } 9182 } 9183 9184 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9185 if (ret) 9186 return ret; 9187 9188 if (!ufshcd_is_clkscaling_supported(hba)) 9189 ufshcd_pm_qos_update(hba, on); 9190 out: 9191 if (ret) { 9192 list_for_each_entry(clki, head, list) { 9193 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9194 clk_disable_unprepare(clki->clk); 9195 } 9196 } else if (!ret && on) { 9197 spin_lock_irqsave(hba->host->host_lock, flags); 9198 hba->clk_gating.state = CLKS_ON; 9199 trace_ufshcd_clk_gating(dev_name(hba->dev), 9200 hba->clk_gating.state); 9201 spin_unlock_irqrestore(hba->host->host_lock, flags); 9202 } 9203 9204 if (clk_state_changed) 9205 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9206 (on ? "on" : "off"), 9207 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9208 return ret; 9209 } 9210 9211 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9212 { 9213 u32 freq; 9214 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9215 9216 if (ret) { 9217 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9218 return REF_CLK_FREQ_INVAL; 9219 } 9220 9221 return ufs_get_bref_clk_from_hz(freq); 9222 } 9223 9224 static int ufshcd_init_clocks(struct ufs_hba *hba) 9225 { 9226 int ret = 0; 9227 struct ufs_clk_info *clki; 9228 struct device *dev = hba->dev; 9229 struct list_head *head = &hba->clk_list_head; 9230 9231 if (list_empty(head)) 9232 goto out; 9233 9234 list_for_each_entry(clki, head, list) { 9235 if (!clki->name) 9236 continue; 9237 9238 clki->clk = devm_clk_get(dev, clki->name); 9239 if (IS_ERR(clki->clk)) { 9240 ret = PTR_ERR(clki->clk); 9241 dev_err(dev, "%s: %s clk get failed, %d\n", 9242 __func__, clki->name, ret); 9243 goto out; 9244 } 9245 9246 /* 9247 * Parse device ref clk freq as per device tree "ref_clk". 9248 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9249 * in ufshcd_alloc_host(). 9250 */ 9251 if (!strcmp(clki->name, "ref_clk")) 9252 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9253 9254 if (clki->max_freq) { 9255 ret = clk_set_rate(clki->clk, clki->max_freq); 9256 if (ret) { 9257 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9258 __func__, clki->name, 9259 clki->max_freq, ret); 9260 goto out; 9261 } 9262 clki->curr_freq = clki->max_freq; 9263 } 9264 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9265 clki->name, clk_get_rate(clki->clk)); 9266 } 9267 9268 /* Set Max. frequency for all clocks */ 9269 if (hba->use_pm_opp) { 9270 ret = ufshcd_opp_set_rate(hba, ULONG_MAX); 9271 if (ret) { 9272 dev_err(hba->dev, "%s: failed to set OPP: %d", __func__, 9273 ret); 9274 goto out; 9275 } 9276 } 9277 9278 out: 9279 return ret; 9280 } 9281 9282 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9283 { 9284 int err = 0; 9285 9286 if (!hba->vops) 9287 goto out; 9288 9289 err = ufshcd_vops_init(hba); 9290 if (err) 9291 dev_err_probe(hba->dev, err, 9292 "%s: variant %s init failed with err %d\n", 9293 __func__, ufshcd_get_var_name(hba), err); 9294 out: 9295 return err; 9296 } 9297 9298 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9299 { 9300 if (!hba->vops) 9301 return; 9302 9303 ufshcd_vops_exit(hba); 9304 } 9305 9306 static int ufshcd_hba_init(struct ufs_hba *hba) 9307 { 9308 int err; 9309 9310 /* 9311 * Handle host controller power separately from the UFS device power 9312 * rails as it will help controlling the UFS host controller power 9313 * collapse easily which is different than UFS device power collapse. 9314 * Also, enable the host controller power before we go ahead with rest 9315 * of the initialization here. 9316 */ 9317 err = ufshcd_init_hba_vreg(hba); 9318 if (err) 9319 goto out; 9320 9321 err = ufshcd_setup_hba_vreg(hba, true); 9322 if (err) 9323 goto out; 9324 9325 err = ufshcd_init_clocks(hba); 9326 if (err) 9327 goto out_disable_hba_vreg; 9328 9329 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9330 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9331 9332 err = ufshcd_setup_clocks(hba, true); 9333 if (err) 9334 goto out_disable_hba_vreg; 9335 9336 err = ufshcd_init_vreg(hba); 9337 if (err) 9338 goto out_disable_clks; 9339 9340 err = ufshcd_setup_vreg(hba, true); 9341 if (err) 9342 goto out_disable_clks; 9343 9344 err = ufshcd_variant_hba_init(hba); 9345 if (err) 9346 goto out_disable_vreg; 9347 9348 ufs_debugfs_hba_init(hba); 9349 ufs_fault_inject_hba_init(hba); 9350 9351 hba->is_powered = true; 9352 goto out; 9353 9354 out_disable_vreg: 9355 ufshcd_setup_vreg(hba, false); 9356 out_disable_clks: 9357 ufshcd_setup_clocks(hba, false); 9358 out_disable_hba_vreg: 9359 ufshcd_setup_hba_vreg(hba, false); 9360 out: 9361 return err; 9362 } 9363 9364 static void ufshcd_hba_exit(struct ufs_hba *hba) 9365 { 9366 if (hba->is_powered) { 9367 ufshcd_pm_qos_exit(hba); 9368 ufshcd_exit_clk_scaling(hba); 9369 ufshcd_exit_clk_gating(hba); 9370 if (hba->eh_wq) 9371 destroy_workqueue(hba->eh_wq); 9372 ufs_debugfs_hba_exit(hba); 9373 ufshcd_variant_hba_exit(hba); 9374 ufshcd_setup_vreg(hba, false); 9375 ufshcd_setup_clocks(hba, false); 9376 ufshcd_setup_hba_vreg(hba, false); 9377 hba->is_powered = false; 9378 ufs_put_device_desc(hba); 9379 } 9380 } 9381 9382 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9383 enum ufs_dev_pwr_mode pwr_mode, 9384 struct scsi_sense_hdr *sshdr) 9385 { 9386 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9387 struct scsi_failure failure_defs[] = { 9388 { 9389 .allowed = 2, 9390 .result = SCMD_FAILURE_RESULT_ANY, 9391 }, 9392 }; 9393 struct scsi_failures failures = { 9394 .failure_definitions = failure_defs, 9395 }; 9396 const struct scsi_exec_args args = { 9397 .failures = &failures, 9398 .sshdr = sshdr, 9399 .req_flags = BLK_MQ_REQ_PM, 9400 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9401 }; 9402 9403 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9404 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9405 &args); 9406 } 9407 9408 /** 9409 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9410 * power mode 9411 * @hba: per adapter instance 9412 * @pwr_mode: device power mode to set 9413 * 9414 * Return: 0 if requested power mode is set successfully; 9415 * < 0 if failed to set the requested power mode. 9416 */ 9417 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9418 enum ufs_dev_pwr_mode pwr_mode) 9419 { 9420 struct scsi_sense_hdr sshdr; 9421 struct scsi_device *sdp; 9422 unsigned long flags; 9423 int ret; 9424 9425 spin_lock_irqsave(hba->host->host_lock, flags); 9426 sdp = hba->ufs_device_wlun; 9427 if (sdp && scsi_device_online(sdp)) 9428 ret = scsi_device_get(sdp); 9429 else 9430 ret = -ENODEV; 9431 spin_unlock_irqrestore(hba->host->host_lock, flags); 9432 9433 if (ret) 9434 return ret; 9435 9436 /* 9437 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9438 * handling, which would wait for host to be resumed. Since we know 9439 * we are functional while we are here, skip host resume in error 9440 * handling context. 9441 */ 9442 hba->host->eh_noresume = 1; 9443 9444 /* 9445 * Current function would be generally called from the power management 9446 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9447 * already suspended childs. 9448 */ 9449 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9450 if (ret) { 9451 sdev_printk(KERN_WARNING, sdp, 9452 "START_STOP failed for power mode: %d, result %x\n", 9453 pwr_mode, ret); 9454 if (ret > 0) { 9455 if (scsi_sense_valid(&sshdr)) 9456 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9457 ret = -EIO; 9458 } 9459 } else { 9460 hba->curr_dev_pwr_mode = pwr_mode; 9461 } 9462 9463 scsi_device_put(sdp); 9464 hba->host->eh_noresume = 0; 9465 return ret; 9466 } 9467 9468 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9469 enum uic_link_state req_link_state, 9470 bool check_for_bkops) 9471 { 9472 int ret = 0; 9473 9474 if (req_link_state == hba->uic_link_state) 9475 return 0; 9476 9477 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9478 ret = ufshcd_uic_hibern8_enter(hba); 9479 if (!ret) { 9480 ufshcd_set_link_hibern8(hba); 9481 } else { 9482 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9483 __func__, ret); 9484 goto out; 9485 } 9486 } 9487 /* 9488 * If autobkops is enabled, link can't be turned off because 9489 * turning off the link would also turn off the device, except in the 9490 * case of DeepSleep where the device is expected to remain powered. 9491 */ 9492 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9493 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9494 /* 9495 * Let's make sure that link is in low power mode, we are doing 9496 * this currently by putting the link in Hibern8. Otherway to 9497 * put the link in low power mode is to send the DME end point 9498 * to device and then send the DME reset command to local 9499 * unipro. But putting the link in hibern8 is much faster. 9500 * 9501 * Note also that putting the link in Hibern8 is a requirement 9502 * for entering DeepSleep. 9503 */ 9504 ret = ufshcd_uic_hibern8_enter(hba); 9505 if (ret) { 9506 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9507 __func__, ret); 9508 goto out; 9509 } 9510 /* 9511 * Change controller state to "reset state" which 9512 * should also put the link in off/reset state 9513 */ 9514 ufshcd_hba_stop(hba); 9515 /* 9516 * TODO: Check if we need any delay to make sure that 9517 * controller is reset 9518 */ 9519 ufshcd_set_link_off(hba); 9520 } 9521 9522 out: 9523 return ret; 9524 } 9525 9526 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9527 { 9528 bool vcc_off = false; 9529 9530 /* 9531 * It seems some UFS devices may keep drawing more than sleep current 9532 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9533 * To avoid this situation, add 2ms delay before putting these UFS 9534 * rails in LPM mode. 9535 */ 9536 if (!ufshcd_is_link_active(hba) && 9537 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9538 usleep_range(2000, 2100); 9539 9540 /* 9541 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9542 * power. 9543 * 9544 * If UFS device and link is in OFF state, all power supplies (VCC, 9545 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9546 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9547 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9548 * 9549 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9550 * in low power state which would save some power. 9551 * 9552 * If Write Booster is enabled and the device needs to flush the WB 9553 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9554 */ 9555 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9556 !hba->dev_info.is_lu_power_on_wp) { 9557 ufshcd_setup_vreg(hba, false); 9558 vcc_off = true; 9559 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9560 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9561 vcc_off = true; 9562 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9563 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9564 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9565 } 9566 } 9567 9568 /* 9569 * Some UFS devices require delay after VCC power rail is turned-off. 9570 */ 9571 if (vcc_off && hba->vreg_info.vcc && 9572 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9573 usleep_range(5000, 5100); 9574 } 9575 9576 #ifdef CONFIG_PM 9577 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9578 { 9579 int ret = 0; 9580 9581 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9582 !hba->dev_info.is_lu_power_on_wp) { 9583 ret = ufshcd_setup_vreg(hba, true); 9584 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9585 if (!ufshcd_is_link_active(hba)) { 9586 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9587 if (ret) 9588 goto vcc_disable; 9589 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9590 if (ret) 9591 goto vccq_lpm; 9592 } 9593 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9594 } 9595 goto out; 9596 9597 vccq_lpm: 9598 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9599 vcc_disable: 9600 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9601 out: 9602 return ret; 9603 } 9604 #endif /* CONFIG_PM */ 9605 9606 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9607 { 9608 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9609 ufshcd_setup_hba_vreg(hba, false); 9610 } 9611 9612 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9613 { 9614 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9615 ufshcd_setup_hba_vreg(hba, true); 9616 } 9617 9618 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9619 { 9620 int ret = 0; 9621 bool check_for_bkops; 9622 enum ufs_pm_level pm_lvl; 9623 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9624 enum uic_link_state req_link_state; 9625 9626 hba->pm_op_in_progress = true; 9627 if (pm_op != UFS_SHUTDOWN_PM) { 9628 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9629 hba->rpm_lvl : hba->spm_lvl; 9630 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9631 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9632 } else { 9633 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9634 req_link_state = UIC_LINK_OFF_STATE; 9635 } 9636 9637 /* 9638 * If we can't transition into any of the low power modes 9639 * just gate the clocks. 9640 */ 9641 ufshcd_hold(hba); 9642 hba->clk_gating.is_suspended = true; 9643 9644 if (ufshcd_is_clkscaling_supported(hba)) 9645 ufshcd_clk_scaling_suspend(hba, true); 9646 9647 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9648 req_link_state == UIC_LINK_ACTIVE_STATE) { 9649 goto vops_suspend; 9650 } 9651 9652 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9653 (req_link_state == hba->uic_link_state)) 9654 goto enable_scaling; 9655 9656 /* UFS device & link must be active before we enter in this function */ 9657 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9658 /* Wait err handler finish or trigger err recovery */ 9659 if (!ufshcd_eh_in_progress(hba)) 9660 ufshcd_force_error_recovery(hba); 9661 ret = -EBUSY; 9662 goto enable_scaling; 9663 } 9664 9665 if (pm_op == UFS_RUNTIME_PM) { 9666 if (ufshcd_can_autobkops_during_suspend(hba)) { 9667 /* 9668 * The device is idle with no requests in the queue, 9669 * allow background operations if bkops status shows 9670 * that performance might be impacted. 9671 */ 9672 ret = ufshcd_urgent_bkops(hba); 9673 if (ret) { 9674 /* 9675 * If return err in suspend flow, IO will hang. 9676 * Trigger error handler and break suspend for 9677 * error recovery. 9678 */ 9679 ufshcd_force_error_recovery(hba); 9680 ret = -EBUSY; 9681 goto enable_scaling; 9682 } 9683 } else { 9684 /* make sure that auto bkops is disabled */ 9685 ufshcd_disable_auto_bkops(hba); 9686 } 9687 /* 9688 * If device needs to do BKOP or WB buffer flush during 9689 * Hibern8, keep device power mode as "active power mode" 9690 * and VCC supply. 9691 */ 9692 hba->dev_info.b_rpm_dev_flush_capable = 9693 hba->auto_bkops_enabled || 9694 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9695 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9696 ufshcd_is_auto_hibern8_enabled(hba))) && 9697 ufshcd_wb_need_flush(hba)); 9698 } 9699 9700 flush_work(&hba->eeh_work); 9701 9702 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9703 if (ret) 9704 goto enable_scaling; 9705 9706 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9707 if (pm_op != UFS_RUNTIME_PM) 9708 /* ensure that bkops is disabled */ 9709 ufshcd_disable_auto_bkops(hba); 9710 9711 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9712 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9713 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9714 /* 9715 * If return err in suspend flow, IO will hang. 9716 * Trigger error handler and break suspend for 9717 * error recovery. 9718 */ 9719 ufshcd_force_error_recovery(hba); 9720 ret = -EBUSY; 9721 } 9722 if (ret) 9723 goto enable_scaling; 9724 } 9725 } 9726 9727 /* 9728 * In the case of DeepSleep, the device is expected to remain powered 9729 * with the link off, so do not check for bkops. 9730 */ 9731 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9732 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9733 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9734 /* 9735 * If return err in suspend flow, IO will hang. 9736 * Trigger error handler and break suspend for 9737 * error recovery. 9738 */ 9739 ufshcd_force_error_recovery(hba); 9740 ret = -EBUSY; 9741 } 9742 if (ret) 9743 goto set_dev_active; 9744 9745 vops_suspend: 9746 /* 9747 * Call vendor specific suspend callback. As these callbacks may access 9748 * vendor specific host controller register space call them before the 9749 * host clocks are ON. 9750 */ 9751 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9752 if (ret) 9753 goto set_link_active; 9754 9755 cancel_delayed_work_sync(&hba->ufs_rtc_update_work); 9756 goto out; 9757 9758 set_link_active: 9759 /* 9760 * Device hardware reset is required to exit DeepSleep. Also, for 9761 * DeepSleep, the link is off so host reset and restore will be done 9762 * further below. 9763 */ 9764 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9765 ufshcd_device_reset(hba); 9766 WARN_ON(!ufshcd_is_link_off(hba)); 9767 } 9768 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9769 ufshcd_set_link_active(hba); 9770 else if (ufshcd_is_link_off(hba)) 9771 ufshcd_host_reset_and_restore(hba); 9772 set_dev_active: 9773 /* Can also get here needing to exit DeepSleep */ 9774 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9775 ufshcd_device_reset(hba); 9776 ufshcd_host_reset_and_restore(hba); 9777 } 9778 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9779 ufshcd_disable_auto_bkops(hba); 9780 enable_scaling: 9781 if (ufshcd_is_clkscaling_supported(hba)) 9782 ufshcd_clk_scaling_suspend(hba, false); 9783 9784 hba->dev_info.b_rpm_dev_flush_capable = false; 9785 out: 9786 if (hba->dev_info.b_rpm_dev_flush_capable) { 9787 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9788 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9789 } 9790 9791 if (ret) { 9792 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9793 hba->clk_gating.is_suspended = false; 9794 ufshcd_release(hba); 9795 } 9796 hba->pm_op_in_progress = false; 9797 return ret; 9798 } 9799 9800 #ifdef CONFIG_PM 9801 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9802 { 9803 int ret; 9804 enum uic_link_state old_link_state = hba->uic_link_state; 9805 9806 hba->pm_op_in_progress = true; 9807 9808 /* 9809 * Call vendor specific resume callback. As these callbacks may access 9810 * vendor specific host controller register space call them when the 9811 * host clocks are ON. 9812 */ 9813 ret = ufshcd_vops_resume(hba, pm_op); 9814 if (ret) 9815 goto out; 9816 9817 /* For DeepSleep, the only supported option is to have the link off */ 9818 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9819 9820 if (ufshcd_is_link_hibern8(hba)) { 9821 ret = ufshcd_uic_hibern8_exit(hba); 9822 if (!ret) { 9823 ufshcd_set_link_active(hba); 9824 } else { 9825 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9826 __func__, ret); 9827 goto vendor_suspend; 9828 } 9829 } else if (ufshcd_is_link_off(hba)) { 9830 /* 9831 * A full initialization of the host and the device is 9832 * required since the link was put to off during suspend. 9833 * Note, in the case of DeepSleep, the device will exit 9834 * DeepSleep due to device reset. 9835 */ 9836 ret = ufshcd_reset_and_restore(hba); 9837 /* 9838 * ufshcd_reset_and_restore() should have already 9839 * set the link state as active 9840 */ 9841 if (ret || !ufshcd_is_link_active(hba)) 9842 goto vendor_suspend; 9843 } 9844 9845 if (!ufshcd_is_ufs_dev_active(hba)) { 9846 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9847 if (ret) 9848 goto set_old_link_state; 9849 ufshcd_set_timestamp_attr(hba); 9850 schedule_delayed_work(&hba->ufs_rtc_update_work, 9851 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 9852 } 9853 9854 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9855 ufshcd_enable_auto_bkops(hba); 9856 else 9857 /* 9858 * If BKOPs operations are urgently needed at this moment then 9859 * keep auto-bkops enabled or else disable it. 9860 */ 9861 ufshcd_urgent_bkops(hba); 9862 9863 if (hba->ee_usr_mask) 9864 ufshcd_write_ee_control(hba); 9865 9866 if (ufshcd_is_clkscaling_supported(hba)) 9867 ufshcd_clk_scaling_suspend(hba, false); 9868 9869 if (hba->dev_info.b_rpm_dev_flush_capable) { 9870 hba->dev_info.b_rpm_dev_flush_capable = false; 9871 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9872 } 9873 9874 ufshcd_configure_auto_hibern8(hba); 9875 9876 goto out; 9877 9878 set_old_link_state: 9879 ufshcd_link_state_transition(hba, old_link_state, 0); 9880 vendor_suspend: 9881 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9882 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9883 out: 9884 if (ret) 9885 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9886 hba->clk_gating.is_suspended = false; 9887 ufshcd_release(hba); 9888 hba->pm_op_in_progress = false; 9889 return ret; 9890 } 9891 9892 static int ufshcd_wl_runtime_suspend(struct device *dev) 9893 { 9894 struct scsi_device *sdev = to_scsi_device(dev); 9895 struct ufs_hba *hba; 9896 int ret; 9897 ktime_t start = ktime_get(); 9898 9899 hba = shost_priv(sdev->host); 9900 9901 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9902 if (ret) 9903 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9904 9905 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9906 ktime_to_us(ktime_sub(ktime_get(), start)), 9907 hba->curr_dev_pwr_mode, hba->uic_link_state); 9908 9909 return ret; 9910 } 9911 9912 static int ufshcd_wl_runtime_resume(struct device *dev) 9913 { 9914 struct scsi_device *sdev = to_scsi_device(dev); 9915 struct ufs_hba *hba; 9916 int ret = 0; 9917 ktime_t start = ktime_get(); 9918 9919 hba = shost_priv(sdev->host); 9920 9921 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9922 if (ret) 9923 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9924 9925 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9926 ktime_to_us(ktime_sub(ktime_get(), start)), 9927 hba->curr_dev_pwr_mode, hba->uic_link_state); 9928 9929 return ret; 9930 } 9931 #endif 9932 9933 #ifdef CONFIG_PM_SLEEP 9934 static int ufshcd_wl_suspend(struct device *dev) 9935 { 9936 struct scsi_device *sdev = to_scsi_device(dev); 9937 struct ufs_hba *hba; 9938 int ret = 0; 9939 ktime_t start = ktime_get(); 9940 9941 hba = shost_priv(sdev->host); 9942 down(&hba->host_sem); 9943 hba->system_suspending = true; 9944 9945 if (pm_runtime_suspended(dev)) 9946 goto out; 9947 9948 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9949 if (ret) { 9950 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9951 up(&hba->host_sem); 9952 } 9953 9954 out: 9955 if (!ret) 9956 hba->is_sys_suspended = true; 9957 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9958 ktime_to_us(ktime_sub(ktime_get(), start)), 9959 hba->curr_dev_pwr_mode, hba->uic_link_state); 9960 9961 return ret; 9962 } 9963 9964 static int ufshcd_wl_resume(struct device *dev) 9965 { 9966 struct scsi_device *sdev = to_scsi_device(dev); 9967 struct ufs_hba *hba; 9968 int ret = 0; 9969 ktime_t start = ktime_get(); 9970 9971 hba = shost_priv(sdev->host); 9972 9973 if (pm_runtime_suspended(dev)) 9974 goto out; 9975 9976 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9977 if (ret) 9978 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9979 out: 9980 trace_ufshcd_wl_resume(dev_name(dev), ret, 9981 ktime_to_us(ktime_sub(ktime_get(), start)), 9982 hba->curr_dev_pwr_mode, hba->uic_link_state); 9983 if (!ret) 9984 hba->is_sys_suspended = false; 9985 hba->system_suspending = false; 9986 up(&hba->host_sem); 9987 return ret; 9988 } 9989 #endif 9990 9991 /** 9992 * ufshcd_suspend - helper function for suspend operations 9993 * @hba: per adapter instance 9994 * 9995 * This function will put disable irqs, turn off clocks 9996 * and set vreg and hba-vreg in lpm mode. 9997 * 9998 * Return: 0 upon success; < 0 upon failure. 9999 */ 10000 static int ufshcd_suspend(struct ufs_hba *hba) 10001 { 10002 int ret; 10003 10004 if (!hba->is_powered) 10005 return 0; 10006 /* 10007 * Disable the host irq as host controller as there won't be any 10008 * host controller transaction expected till resume. 10009 */ 10010 ufshcd_disable_irq(hba); 10011 ret = ufshcd_setup_clocks(hba, false); 10012 if (ret) { 10013 ufshcd_enable_irq(hba); 10014 return ret; 10015 } 10016 if (ufshcd_is_clkgating_allowed(hba)) { 10017 hba->clk_gating.state = CLKS_OFF; 10018 trace_ufshcd_clk_gating(dev_name(hba->dev), 10019 hba->clk_gating.state); 10020 } 10021 10022 ufshcd_vreg_set_lpm(hba); 10023 /* Put the host controller in low power mode if possible */ 10024 ufshcd_hba_vreg_set_lpm(hba); 10025 ufshcd_pm_qos_update(hba, false); 10026 return ret; 10027 } 10028 10029 #ifdef CONFIG_PM 10030 /** 10031 * ufshcd_resume - helper function for resume operations 10032 * @hba: per adapter instance 10033 * 10034 * This function basically turns on the regulators, clocks and 10035 * irqs of the hba. 10036 * 10037 * Return: 0 for success and non-zero for failure. 10038 */ 10039 static int ufshcd_resume(struct ufs_hba *hba) 10040 { 10041 int ret; 10042 10043 if (!hba->is_powered) 10044 return 0; 10045 10046 ufshcd_hba_vreg_set_hpm(hba); 10047 ret = ufshcd_vreg_set_hpm(hba); 10048 if (ret) 10049 goto out; 10050 10051 /* Make sure clocks are enabled before accessing controller */ 10052 ret = ufshcd_setup_clocks(hba, true); 10053 if (ret) 10054 goto disable_vreg; 10055 10056 /* enable the host irq as host controller would be active soon */ 10057 ufshcd_enable_irq(hba); 10058 10059 goto out; 10060 10061 disable_vreg: 10062 ufshcd_vreg_set_lpm(hba); 10063 out: 10064 if (ret) 10065 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 10066 return ret; 10067 } 10068 #endif /* CONFIG_PM */ 10069 10070 #ifdef CONFIG_PM_SLEEP 10071 /** 10072 * ufshcd_system_suspend - system suspend callback 10073 * @dev: Device associated with the UFS controller. 10074 * 10075 * Executed before putting the system into a sleep state in which the contents 10076 * of main memory are preserved. 10077 * 10078 * Return: 0 for success and non-zero for failure. 10079 */ 10080 int ufshcd_system_suspend(struct device *dev) 10081 { 10082 struct ufs_hba *hba = dev_get_drvdata(dev); 10083 int ret = 0; 10084 ktime_t start = ktime_get(); 10085 10086 if (pm_runtime_suspended(hba->dev)) 10087 goto out; 10088 10089 ret = ufshcd_suspend(hba); 10090 out: 10091 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 10092 ktime_to_us(ktime_sub(ktime_get(), start)), 10093 hba->curr_dev_pwr_mode, hba->uic_link_state); 10094 return ret; 10095 } 10096 EXPORT_SYMBOL(ufshcd_system_suspend); 10097 10098 /** 10099 * ufshcd_system_resume - system resume callback 10100 * @dev: Device associated with the UFS controller. 10101 * 10102 * Executed after waking the system up from a sleep state in which the contents 10103 * of main memory were preserved. 10104 * 10105 * Return: 0 for success and non-zero for failure. 10106 */ 10107 int ufshcd_system_resume(struct device *dev) 10108 { 10109 struct ufs_hba *hba = dev_get_drvdata(dev); 10110 ktime_t start = ktime_get(); 10111 int ret = 0; 10112 10113 if (pm_runtime_suspended(hba->dev)) 10114 goto out; 10115 10116 ret = ufshcd_resume(hba); 10117 10118 out: 10119 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10120 ktime_to_us(ktime_sub(ktime_get(), start)), 10121 hba->curr_dev_pwr_mode, hba->uic_link_state); 10122 10123 return ret; 10124 } 10125 EXPORT_SYMBOL(ufshcd_system_resume); 10126 #endif /* CONFIG_PM_SLEEP */ 10127 10128 #ifdef CONFIG_PM 10129 /** 10130 * ufshcd_runtime_suspend - runtime suspend callback 10131 * @dev: Device associated with the UFS controller. 10132 * 10133 * Check the description of ufshcd_suspend() function for more details. 10134 * 10135 * Return: 0 for success and non-zero for failure. 10136 */ 10137 int ufshcd_runtime_suspend(struct device *dev) 10138 { 10139 struct ufs_hba *hba = dev_get_drvdata(dev); 10140 int ret; 10141 ktime_t start = ktime_get(); 10142 10143 ret = ufshcd_suspend(hba); 10144 10145 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10146 ktime_to_us(ktime_sub(ktime_get(), start)), 10147 hba->curr_dev_pwr_mode, hba->uic_link_state); 10148 return ret; 10149 } 10150 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10151 10152 /** 10153 * ufshcd_runtime_resume - runtime resume routine 10154 * @dev: Device associated with the UFS controller. 10155 * 10156 * This function basically brings controller 10157 * to active state. Following operations are done in this function: 10158 * 10159 * 1. Turn on all the controller related clocks 10160 * 2. Turn ON VCC rail 10161 * 10162 * Return: 0 upon success; < 0 upon failure. 10163 */ 10164 int ufshcd_runtime_resume(struct device *dev) 10165 { 10166 struct ufs_hba *hba = dev_get_drvdata(dev); 10167 int ret; 10168 ktime_t start = ktime_get(); 10169 10170 ret = ufshcd_resume(hba); 10171 10172 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10173 ktime_to_us(ktime_sub(ktime_get(), start)), 10174 hba->curr_dev_pwr_mode, hba->uic_link_state); 10175 return ret; 10176 } 10177 EXPORT_SYMBOL(ufshcd_runtime_resume); 10178 #endif /* CONFIG_PM */ 10179 10180 static void ufshcd_wl_shutdown(struct device *dev) 10181 { 10182 struct scsi_device *sdev = to_scsi_device(dev); 10183 struct ufs_hba *hba = shost_priv(sdev->host); 10184 10185 down(&hba->host_sem); 10186 hba->shutting_down = true; 10187 up(&hba->host_sem); 10188 10189 /* Turn on everything while shutting down */ 10190 ufshcd_rpm_get_sync(hba); 10191 scsi_device_quiesce(sdev); 10192 shost_for_each_device(sdev, hba->host) { 10193 if (sdev == hba->ufs_device_wlun) 10194 continue; 10195 scsi_device_quiesce(sdev); 10196 } 10197 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10198 10199 /* 10200 * Next, turn off the UFS controller and the UFS regulators. Disable 10201 * clocks. 10202 */ 10203 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10204 ufshcd_suspend(hba); 10205 10206 hba->is_powered = false; 10207 } 10208 10209 /** 10210 * ufshcd_remove - de-allocate SCSI host and host memory space 10211 * data structure memory 10212 * @hba: per adapter instance 10213 */ 10214 void ufshcd_remove(struct ufs_hba *hba) 10215 { 10216 if (hba->ufs_device_wlun) 10217 ufshcd_rpm_get_sync(hba); 10218 ufs_hwmon_remove(hba); 10219 ufs_bsg_remove(hba); 10220 ufs_sysfs_remove_nodes(hba->dev); 10221 blk_mq_destroy_queue(hba->tmf_queue); 10222 blk_put_queue(hba->tmf_queue); 10223 blk_mq_free_tag_set(&hba->tmf_tag_set); 10224 if (hba->scsi_host_added) 10225 scsi_remove_host(hba->host); 10226 /* disable interrupts */ 10227 ufshcd_disable_intr(hba, hba->intr_mask); 10228 ufshcd_hba_stop(hba); 10229 ufshcd_hba_exit(hba); 10230 } 10231 EXPORT_SYMBOL_GPL(ufshcd_remove); 10232 10233 #ifdef CONFIG_PM_SLEEP 10234 int ufshcd_system_freeze(struct device *dev) 10235 { 10236 10237 return ufshcd_system_suspend(dev); 10238 10239 } 10240 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10241 10242 int ufshcd_system_restore(struct device *dev) 10243 { 10244 10245 struct ufs_hba *hba = dev_get_drvdata(dev); 10246 int ret; 10247 10248 ret = ufshcd_system_resume(dev); 10249 if (ret) 10250 return ret; 10251 10252 /* Configure UTRL and UTMRL base address registers */ 10253 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10254 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10255 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10256 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10257 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10258 REG_UTP_TASK_REQ_LIST_BASE_L); 10259 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10260 REG_UTP_TASK_REQ_LIST_BASE_H); 10261 /* 10262 * Make sure that UTRL and UTMRL base address registers 10263 * are updated with the latest queue addresses. Only after 10264 * updating these addresses, we can queue the new commands. 10265 */ 10266 ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H); 10267 10268 /* Resuming from hibernate, assume that link was OFF */ 10269 ufshcd_set_link_off(hba); 10270 10271 return 0; 10272 10273 } 10274 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10275 10276 int ufshcd_system_thaw(struct device *dev) 10277 { 10278 return ufshcd_system_resume(dev); 10279 } 10280 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10281 #endif /* CONFIG_PM_SLEEP */ 10282 10283 /** 10284 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10285 * @hba: pointer to Host Bus Adapter (HBA) 10286 */ 10287 void ufshcd_dealloc_host(struct ufs_hba *hba) 10288 { 10289 scsi_host_put(hba->host); 10290 } 10291 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10292 10293 /** 10294 * ufshcd_set_dma_mask - Set dma mask based on the controller 10295 * addressing capability 10296 * @hba: per adapter instance 10297 * 10298 * Return: 0 for success, non-zero for failure. 10299 */ 10300 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10301 { 10302 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10303 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10304 return 0; 10305 } 10306 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10307 } 10308 10309 /** 10310 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10311 * @dev: pointer to device handle 10312 * @hba_handle: driver private handle 10313 * 10314 * Return: 0 on success, non-zero value on failure. 10315 */ 10316 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10317 { 10318 struct Scsi_Host *host; 10319 struct ufs_hba *hba; 10320 int err = 0; 10321 10322 if (!dev) { 10323 dev_err(dev, 10324 "Invalid memory reference for dev is NULL\n"); 10325 err = -ENODEV; 10326 goto out_error; 10327 } 10328 10329 host = scsi_host_alloc(&ufshcd_driver_template, 10330 sizeof(struct ufs_hba)); 10331 if (!host) { 10332 dev_err(dev, "scsi_host_alloc failed\n"); 10333 err = -ENOMEM; 10334 goto out_error; 10335 } 10336 host->nr_maps = HCTX_TYPE_POLL + 1; 10337 hba = shost_priv(host); 10338 hba->host = host; 10339 hba->dev = dev; 10340 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10341 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10342 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10343 INIT_LIST_HEAD(&hba->clk_list_head); 10344 spin_lock_init(&hba->outstanding_lock); 10345 10346 *hba_handle = hba; 10347 10348 out_error: 10349 return err; 10350 } 10351 EXPORT_SYMBOL(ufshcd_alloc_host); 10352 10353 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10354 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10355 const struct blk_mq_queue_data *qd) 10356 { 10357 WARN_ON_ONCE(true); 10358 return BLK_STS_NOTSUPP; 10359 } 10360 10361 static const struct blk_mq_ops ufshcd_tmf_ops = { 10362 .queue_rq = ufshcd_queue_tmf, 10363 }; 10364 10365 /** 10366 * ufshcd_init - Driver initialization routine 10367 * @hba: per-adapter instance 10368 * @mmio_base: base register address 10369 * @irq: Interrupt line of device 10370 * 10371 * Return: 0 on success, non-zero value on failure. 10372 */ 10373 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10374 { 10375 int err; 10376 struct Scsi_Host *host = hba->host; 10377 struct device *dev = hba->dev; 10378 char eh_wq_name[sizeof("ufs_eh_wq_00")]; 10379 10380 /* 10381 * dev_set_drvdata() must be called before any callbacks are registered 10382 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10383 * sysfs). 10384 */ 10385 dev_set_drvdata(dev, hba); 10386 10387 if (!mmio_base) { 10388 dev_err(hba->dev, 10389 "Invalid memory reference for mmio_base is NULL\n"); 10390 err = -ENODEV; 10391 goto out_error; 10392 } 10393 10394 hba->mmio_base = mmio_base; 10395 hba->irq = irq; 10396 hba->vps = &ufs_hba_vps; 10397 10398 err = ufshcd_hba_init(hba); 10399 if (err) 10400 goto out_error; 10401 10402 /* Read capabilities registers */ 10403 err = ufshcd_hba_capabilities(hba); 10404 if (err) 10405 goto out_disable; 10406 10407 /* Get UFS version supported by the controller */ 10408 hba->ufs_version = ufshcd_get_ufs_version(hba); 10409 10410 /* Get Interrupt bit mask per version */ 10411 hba->intr_mask = ufshcd_get_intr_mask(hba); 10412 10413 err = ufshcd_set_dma_mask(hba); 10414 if (err) { 10415 dev_err(hba->dev, "set dma mask failed\n"); 10416 goto out_disable; 10417 } 10418 10419 /* Allocate memory for host memory space */ 10420 err = ufshcd_memory_alloc(hba); 10421 if (err) { 10422 dev_err(hba->dev, "Memory allocation failed\n"); 10423 goto out_disable; 10424 } 10425 10426 /* Configure LRB */ 10427 ufshcd_host_memory_configure(hba); 10428 10429 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10430 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10431 host->max_id = UFSHCD_MAX_ID; 10432 host->max_lun = UFS_MAX_LUNS; 10433 host->max_channel = UFSHCD_MAX_CHANNEL; 10434 host->unique_id = host->host_no; 10435 host->max_cmd_len = UFS_CDB_SIZE; 10436 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10437 10438 /* Use default RPM delay if host not set */ 10439 if (host->rpm_autosuspend_delay == 0) 10440 host->rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS; 10441 10442 hba->max_pwr_info.is_valid = false; 10443 10444 /* Initialize work queues */ 10445 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d", 10446 hba->host->host_no); 10447 hba->eh_wq = create_singlethread_workqueue(eh_wq_name); 10448 if (!hba->eh_wq) { 10449 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10450 __func__); 10451 err = -ENOMEM; 10452 goto out_disable; 10453 } 10454 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10455 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10456 10457 sema_init(&hba->host_sem, 1); 10458 10459 /* Initialize UIC command mutex */ 10460 mutex_init(&hba->uic_cmd_mutex); 10461 10462 /* Initialize mutex for device management commands */ 10463 mutex_init(&hba->dev_cmd.lock); 10464 10465 /* Initialize mutex for exception event control */ 10466 mutex_init(&hba->ee_ctrl_mutex); 10467 10468 mutex_init(&hba->wb_mutex); 10469 init_rwsem(&hba->clk_scaling_lock); 10470 10471 ufshcd_init_clk_gating(hba); 10472 10473 ufshcd_init_clk_scaling(hba); 10474 10475 /* 10476 * In order to avoid any spurious interrupt immediately after 10477 * registering UFS controller interrupt handler, clear any pending UFS 10478 * interrupt status and disable all the UFS interrupts. 10479 */ 10480 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10481 REG_INTERRUPT_STATUS); 10482 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10483 /* 10484 * Make sure that UFS interrupts are disabled and any pending interrupt 10485 * status is cleared before registering UFS interrupt handler. 10486 */ 10487 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 10488 10489 /* IRQ registration */ 10490 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10491 if (err) { 10492 dev_err(hba->dev, "request irq failed\n"); 10493 goto out_disable; 10494 } else { 10495 hba->is_irq_enabled = true; 10496 } 10497 10498 if (!is_mcq_supported(hba)) { 10499 err = scsi_add_host(host, hba->dev); 10500 if (err) { 10501 dev_err(hba->dev, "scsi_add_host failed\n"); 10502 goto out_disable; 10503 } 10504 hba->scsi_host_added = true; 10505 } 10506 10507 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10508 .nr_hw_queues = 1, 10509 .queue_depth = hba->nutmrs, 10510 .ops = &ufshcd_tmf_ops, 10511 .flags = BLK_MQ_F_NO_SCHED, 10512 }; 10513 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10514 if (err < 0) 10515 goto out_remove_scsi_host; 10516 hba->tmf_queue = blk_mq_alloc_queue(&hba->tmf_tag_set, NULL, NULL); 10517 if (IS_ERR(hba->tmf_queue)) { 10518 err = PTR_ERR(hba->tmf_queue); 10519 goto free_tmf_tag_set; 10520 } 10521 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10522 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10523 if (!hba->tmf_rqs) { 10524 err = -ENOMEM; 10525 goto free_tmf_queue; 10526 } 10527 10528 /* Reset the attached device */ 10529 ufshcd_device_reset(hba); 10530 10531 ufshcd_init_crypto(hba); 10532 10533 /* Host controller enable */ 10534 err = ufshcd_hba_enable(hba); 10535 if (err) { 10536 dev_err(hba->dev, "Host controller enable failed\n"); 10537 ufshcd_print_evt_hist(hba); 10538 ufshcd_print_host_state(hba); 10539 goto free_tmf_queue; 10540 } 10541 10542 /* 10543 * Set the default power management level for runtime and system PM. 10544 * Default power saving mode is to keep UFS link in Hibern8 state 10545 * and UFS device in sleep state. 10546 */ 10547 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10548 UFS_SLEEP_PWR_MODE, 10549 UIC_LINK_HIBERN8_STATE); 10550 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10551 UFS_SLEEP_PWR_MODE, 10552 UIC_LINK_HIBERN8_STATE); 10553 10554 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, ufshcd_rpm_dev_flush_recheck_work); 10555 INIT_DELAYED_WORK(&hba->ufs_rtc_update_work, ufshcd_rtc_work); 10556 10557 /* Set the default auto-hiberate idle timer value to 150 ms */ 10558 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10559 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10560 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10561 } 10562 10563 /* Hold auto suspend until async scan completes */ 10564 pm_runtime_get_sync(dev); 10565 atomic_set(&hba->scsi_block_reqs_cnt, 0); 10566 /* 10567 * We are assuming that device wasn't put in sleep/power-down 10568 * state exclusively during the boot stage before kernel. 10569 * This assumption helps avoid doing link startup twice during 10570 * ufshcd_probe_hba(). 10571 */ 10572 ufshcd_set_ufs_dev_active(hba); 10573 10574 async_schedule(ufshcd_async_scan, hba); 10575 ufs_sysfs_add_nodes(hba->dev); 10576 10577 device_enable_async_suspend(dev); 10578 ufshcd_pm_qos_init(hba); 10579 return 0; 10580 10581 free_tmf_queue: 10582 blk_mq_destroy_queue(hba->tmf_queue); 10583 blk_put_queue(hba->tmf_queue); 10584 free_tmf_tag_set: 10585 blk_mq_free_tag_set(&hba->tmf_tag_set); 10586 out_remove_scsi_host: 10587 if (hba->scsi_host_added) 10588 scsi_remove_host(hba->host); 10589 out_disable: 10590 hba->is_irq_enabled = false; 10591 ufshcd_hba_exit(hba); 10592 out_error: 10593 return err; 10594 } 10595 EXPORT_SYMBOL_GPL(ufshcd_init); 10596 10597 void ufshcd_resume_complete(struct device *dev) 10598 { 10599 struct ufs_hba *hba = dev_get_drvdata(dev); 10600 10601 if (hba->complete_put) { 10602 ufshcd_rpm_put(hba); 10603 hba->complete_put = false; 10604 } 10605 } 10606 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10607 10608 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10609 { 10610 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10611 enum ufs_dev_pwr_mode dev_pwr_mode; 10612 enum uic_link_state link_state; 10613 unsigned long flags; 10614 bool res; 10615 10616 spin_lock_irqsave(&dev->power.lock, flags); 10617 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10618 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10619 res = pm_runtime_suspended(dev) && 10620 hba->curr_dev_pwr_mode == dev_pwr_mode && 10621 hba->uic_link_state == link_state && 10622 !hba->dev_info.b_rpm_dev_flush_capable; 10623 spin_unlock_irqrestore(&dev->power.lock, flags); 10624 10625 return res; 10626 } 10627 10628 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10629 { 10630 struct ufs_hba *hba = dev_get_drvdata(dev); 10631 int ret; 10632 10633 /* 10634 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10635 * are same. And it doesn't wake up the device for system-suspend 10636 * if it's runtime suspended. But ufs doesn't follow that. 10637 * Refer ufshcd_resume_complete() 10638 */ 10639 if (hba->ufs_device_wlun) { 10640 /* Prevent runtime suspend */ 10641 ufshcd_rpm_get_noresume(hba); 10642 /* 10643 * Check if already runtime suspended in same state as system 10644 * suspend would be. 10645 */ 10646 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10647 /* RPM state is not ok for SPM, so runtime resume */ 10648 ret = ufshcd_rpm_resume(hba); 10649 if (ret < 0 && ret != -EACCES) { 10650 ufshcd_rpm_put(hba); 10651 return ret; 10652 } 10653 } 10654 hba->complete_put = true; 10655 } 10656 return 0; 10657 } 10658 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10659 10660 int ufshcd_suspend_prepare(struct device *dev) 10661 { 10662 return __ufshcd_suspend_prepare(dev, true); 10663 } 10664 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10665 10666 #ifdef CONFIG_PM_SLEEP 10667 static int ufshcd_wl_poweroff(struct device *dev) 10668 { 10669 struct scsi_device *sdev = to_scsi_device(dev); 10670 struct ufs_hba *hba = shost_priv(sdev->host); 10671 10672 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10673 return 0; 10674 } 10675 #endif 10676 10677 static int ufshcd_wl_probe(struct device *dev) 10678 { 10679 struct scsi_device *sdev = to_scsi_device(dev); 10680 10681 if (!is_device_wlun(sdev)) 10682 return -ENODEV; 10683 10684 blk_pm_runtime_init(sdev->request_queue, dev); 10685 pm_runtime_set_autosuspend_delay(dev, 0); 10686 pm_runtime_allow(dev); 10687 10688 return 0; 10689 } 10690 10691 static int ufshcd_wl_remove(struct device *dev) 10692 { 10693 pm_runtime_forbid(dev); 10694 return 0; 10695 } 10696 10697 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10698 #ifdef CONFIG_PM_SLEEP 10699 .suspend = ufshcd_wl_suspend, 10700 .resume = ufshcd_wl_resume, 10701 .freeze = ufshcd_wl_suspend, 10702 .thaw = ufshcd_wl_resume, 10703 .poweroff = ufshcd_wl_poweroff, 10704 .restore = ufshcd_wl_resume, 10705 #endif 10706 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10707 }; 10708 10709 static void ufshcd_check_header_layout(void) 10710 { 10711 /* 10712 * gcc compilers before version 10 cannot do constant-folding for 10713 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10714 * before. 10715 */ 10716 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10717 return; 10718 10719 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10720 .cci = 3})[0] != 3); 10721 10722 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10723 .ehs_length = 2})[1] != 2); 10724 10725 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10726 .enable_crypto = 1})[2] 10727 != 0x80); 10728 10729 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10730 .command_type = 5, 10731 .data_direction = 3, 10732 .interrupt = 1, 10733 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10734 10735 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10736 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10737 cpu_to_le32(0xdeadbeef)); 10738 10739 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10740 .ocs = 4})[8] != 4); 10741 10742 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10743 .cds = 5})[9] != 5); 10744 10745 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10746 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10747 cpu_to_le32(0xbadcafe)); 10748 10749 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10750 .iid = 0xf })[4] != 0xf0); 10751 10752 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10753 .command_set_type = 0xf })[4] != 0xf); 10754 } 10755 10756 /* 10757 * ufs_dev_wlun_template - describes ufs device wlun 10758 * ufs-device wlun - used to send pm commands 10759 * All luns are consumers of ufs-device wlun. 10760 * 10761 * Currently, no sd driver is present for wluns. 10762 * Hence the no specific pm operations are performed. 10763 * With ufs design, SSU should be sent to ufs-device wlun. 10764 * Hence register a scsi driver for ufs wluns only. 10765 */ 10766 static struct scsi_driver ufs_dev_wlun_template = { 10767 .gendrv = { 10768 .name = "ufs_device_wlun", 10769 .probe = ufshcd_wl_probe, 10770 .remove = ufshcd_wl_remove, 10771 .pm = &ufshcd_wl_pm_ops, 10772 .shutdown = ufshcd_wl_shutdown, 10773 }, 10774 }; 10775 10776 static int __init ufshcd_core_init(void) 10777 { 10778 int ret; 10779 10780 ufshcd_check_header_layout(); 10781 10782 ufs_debugfs_init(); 10783 10784 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10785 if (ret) 10786 ufs_debugfs_exit(); 10787 return ret; 10788 } 10789 10790 static void __exit ufshcd_core_exit(void) 10791 { 10792 ufs_debugfs_exit(); 10793 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10794 } 10795 10796 module_init(ufshcd_core_init); 10797 module_exit(ufshcd_core_exit); 10798 10799 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10800 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10801 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10802 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10803 MODULE_LICENSE("GPL"); 10804