1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/pm_opp.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/sched/clock.h> 26 #include <linux/iopoll.h> 27 #include <scsi/scsi_cmnd.h> 28 #include <scsi/scsi_dbg.h> 29 #include <scsi/scsi_driver.h> 30 #include <scsi/scsi_eh.h> 31 #include "ufshcd-priv.h" 32 #include <ufs/ufs_quirks.h> 33 #include <ufs/unipro.h> 34 #include "ufs-sysfs.h" 35 #include "ufs-debugfs.h" 36 #include "ufs-fault-injection.h" 37 #include "ufs_bsg.h" 38 #include "ufshcd-crypto.h" 39 #include <asm/unaligned.h> 40 41 #define CREATE_TRACE_POINTS 42 #include "ufs_trace.h" 43 44 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 45 UTP_TASK_REQ_COMPL |\ 46 UFSHCD_ERROR_MASK) 47 48 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 49 UFSHCD_ERROR_MASK |\ 50 MCQ_CQ_EVENT_STATUS) 51 52 53 /* UIC command timeout, unit: ms */ 54 enum { 55 UIC_CMD_TIMEOUT_DEFAULT = 500, 56 UIC_CMD_TIMEOUT_MAX = 2000, 57 }; 58 /* NOP OUT retries waiting for NOP IN response */ 59 #define NOP_OUT_RETRIES 10 60 /* Timeout after 50 msecs if NOP OUT hangs without response */ 61 #define NOP_OUT_TIMEOUT 50 /* msecs */ 62 63 /* Query request retries */ 64 #define QUERY_REQ_RETRIES 3 65 /* Query request timeout */ 66 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 67 68 /* Advanced RPMB request timeout */ 69 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 70 71 /* Task management command timeout */ 72 #define TM_CMD_TIMEOUT 100 /* msecs */ 73 74 /* maximum number of retries for a general UIC command */ 75 #define UFS_UIC_COMMAND_RETRIES 3 76 77 /* maximum number of link-startup retries */ 78 #define DME_LINKSTARTUP_RETRIES 3 79 80 /* maximum number of reset retries before giving up */ 81 #define MAX_HOST_RESET_RETRIES 5 82 83 /* Maximum number of error handler retries before giving up */ 84 #define MAX_ERR_HANDLER_RETRIES 5 85 86 /* Expose the flag value from utp_upiu_query.value */ 87 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 88 89 /* Interrupt aggregation default timeout, unit: 40us */ 90 #define INT_AGGR_DEF_TO 0x02 91 92 /* default delay of autosuspend: 2000 ms */ 93 #define RPM_AUTOSUSPEND_DELAY_MS 2000 94 95 /* Default delay of RPM device flush delayed work */ 96 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 97 98 /* Default value of wait time before gating device ref clock */ 99 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 100 101 /* Polling time to wait for fDeviceInit */ 102 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 103 104 /* Default RTC update every 10 seconds */ 105 #define UFS_RTC_UPDATE_INTERVAL_MS (10 * MSEC_PER_SEC) 106 107 /* bMaxNumOfRTT is equal to two after device manufacturing */ 108 #define DEFAULT_MAX_NUM_RTT 2 109 110 /* UFSHC 4.0 compliant HC support this mode. */ 111 static bool use_mcq_mode = true; 112 113 static bool is_mcq_supported(struct ufs_hba *hba) 114 { 115 return hba->mcq_sup && use_mcq_mode; 116 } 117 118 module_param(use_mcq_mode, bool, 0644); 119 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 120 121 static unsigned int uic_cmd_timeout = UIC_CMD_TIMEOUT_DEFAULT; 122 123 static int uic_cmd_timeout_set(const char *val, const struct kernel_param *kp) 124 { 125 return param_set_uint_minmax(val, kp, UIC_CMD_TIMEOUT_DEFAULT, 126 UIC_CMD_TIMEOUT_MAX); 127 } 128 129 static const struct kernel_param_ops uic_cmd_timeout_ops = { 130 .set = uic_cmd_timeout_set, 131 .get = param_get_uint, 132 }; 133 134 module_param_cb(uic_cmd_timeout, &uic_cmd_timeout_ops, &uic_cmd_timeout, 0644); 135 MODULE_PARM_DESC(uic_cmd_timeout, 136 "UFS UIC command timeout in milliseconds. Defaults to 500ms. Supported values range from 500ms to 2 seconds inclusively"); 137 138 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 139 ({ \ 140 int _ret; \ 141 if (_on) \ 142 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 143 else \ 144 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 145 _ret; \ 146 }) 147 148 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 149 size_t __len = (len); \ 150 print_hex_dump(KERN_ERR, prefix_str, \ 151 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 152 16, 4, buf, __len, false); \ 153 } while (0) 154 155 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 156 const char *prefix) 157 { 158 u32 *regs; 159 size_t pos; 160 161 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 162 return -EINVAL; 163 164 regs = kzalloc(len, GFP_ATOMIC); 165 if (!regs) 166 return -ENOMEM; 167 168 for (pos = 0; pos < len; pos += 4) { 169 if (offset == 0 && 170 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 171 pos <= REG_UIC_ERROR_CODE_DME) 172 continue; 173 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 174 } 175 176 ufshcd_hex_dump(prefix, regs, len); 177 kfree(regs); 178 179 return 0; 180 } 181 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 182 183 enum { 184 UFSHCD_MAX_CHANNEL = 0, 185 UFSHCD_MAX_ID = 1, 186 }; 187 188 static const char *const ufshcd_state_name[] = { 189 [UFSHCD_STATE_RESET] = "reset", 190 [UFSHCD_STATE_OPERATIONAL] = "operational", 191 [UFSHCD_STATE_ERROR] = "error", 192 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 193 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 194 }; 195 196 /* UFSHCD error handling flags */ 197 enum { 198 UFSHCD_EH_IN_PROGRESS = (1 << 0), 199 }; 200 201 /* UFSHCD UIC layer error flags */ 202 enum { 203 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 204 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 205 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 206 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 207 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 208 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 209 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 210 }; 211 212 #define ufshcd_set_eh_in_progress(h) \ 213 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 214 #define ufshcd_eh_in_progress(h) \ 215 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 216 #define ufshcd_clear_eh_in_progress(h) \ 217 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 218 219 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 220 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 221 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 222 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 223 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 224 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 225 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 226 /* 227 * For DeepSleep, the link is first put in hibern8 and then off. 228 * Leaving the link in hibern8 is not supported. 229 */ 230 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 231 }; 232 233 static inline enum ufs_dev_pwr_mode 234 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 235 { 236 return ufs_pm_lvl_states[lvl].dev_state; 237 } 238 239 static inline enum uic_link_state 240 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 241 { 242 return ufs_pm_lvl_states[lvl].link_state; 243 } 244 245 static inline enum ufs_pm_level 246 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 247 enum uic_link_state link_state) 248 { 249 enum ufs_pm_level lvl; 250 251 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 252 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 253 (ufs_pm_lvl_states[lvl].link_state == link_state)) 254 return lvl; 255 } 256 257 /* if no match found, return the level 0 */ 258 return UFS_PM_LVL_0; 259 } 260 261 static bool ufshcd_is_ufs_dev_busy(struct ufs_hba *hba) 262 { 263 return (hba->clk_gating.active_reqs || hba->outstanding_reqs || hba->outstanding_tasks || 264 hba->active_uic_cmd || hba->uic_async_done); 265 } 266 267 static const struct ufs_dev_quirk ufs_fixups[] = { 268 /* UFS cards deviations table */ 269 { .wmanufacturerid = UFS_VENDOR_MICRON, 270 .model = UFS_ANY_MODEL, 271 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 272 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 273 .model = UFS_ANY_MODEL, 274 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 275 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 276 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 277 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 278 .model = UFS_ANY_MODEL, 279 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 280 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 281 .model = "hB8aL1" /*H28U62301AMR*/, 282 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 283 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 284 .model = UFS_ANY_MODEL, 285 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 286 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 287 .model = "THGLF2G9C8KBADG", 288 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 289 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 290 .model = "THGLF2G9D8KBADG", 291 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 292 {} 293 }; 294 295 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 296 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 297 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 298 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 299 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 300 static void ufshcd_hba_exit(struct ufs_hba *hba); 301 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params); 302 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 303 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 304 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 305 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 306 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 307 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 308 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 309 bool scale_up); 310 static irqreturn_t ufshcd_intr(int irq, void *__hba); 311 static int ufshcd_change_power_mode(struct ufs_hba *hba, 312 struct ufs_pa_layer_attr *pwr_mode); 313 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 314 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 315 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 316 struct ufs_vreg *vreg); 317 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 318 bool enable); 319 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 320 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 321 322 void ufshcd_enable_irq(struct ufs_hba *hba) 323 { 324 if (!hba->is_irq_enabled) { 325 enable_irq(hba->irq); 326 hba->is_irq_enabled = true; 327 } 328 } 329 EXPORT_SYMBOL_GPL(ufshcd_enable_irq); 330 331 void ufshcd_disable_irq(struct ufs_hba *hba) 332 { 333 if (hba->is_irq_enabled) { 334 disable_irq(hba->irq); 335 hba->is_irq_enabled = false; 336 } 337 } 338 EXPORT_SYMBOL_GPL(ufshcd_disable_irq); 339 340 static void ufshcd_configure_wb(struct ufs_hba *hba) 341 { 342 if (!ufshcd_is_wb_allowed(hba)) 343 return; 344 345 ufshcd_wb_toggle(hba, true); 346 347 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 348 349 if (ufshcd_is_wb_buf_flush_allowed(hba)) 350 ufshcd_wb_toggle_buf_flush(hba, true); 351 } 352 353 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 354 enum ufs_trace_str_t str_t) 355 { 356 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 357 struct utp_upiu_header *header; 358 359 if (!trace_ufshcd_upiu_enabled()) 360 return; 361 362 if (str_t == UFS_CMD_SEND) 363 header = &rq->header; 364 else 365 header = &hba->lrb[tag].ucd_rsp_ptr->header; 366 367 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 368 UFS_TSF_CDB); 369 } 370 371 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 372 enum ufs_trace_str_t str_t, 373 struct utp_upiu_req *rq_rsp) 374 { 375 if (!trace_ufshcd_upiu_enabled()) 376 return; 377 378 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 379 &rq_rsp->qr, UFS_TSF_OSF); 380 } 381 382 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 383 enum ufs_trace_str_t str_t) 384 { 385 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 386 387 if (!trace_ufshcd_upiu_enabled()) 388 return; 389 390 if (str_t == UFS_TM_SEND) 391 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 392 &descp->upiu_req.req_header, 393 &descp->upiu_req.input_param1, 394 UFS_TSF_TM_INPUT); 395 else 396 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 397 &descp->upiu_rsp.rsp_header, 398 &descp->upiu_rsp.output_param1, 399 UFS_TSF_TM_OUTPUT); 400 } 401 402 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 403 const struct uic_command *ucmd, 404 enum ufs_trace_str_t str_t) 405 { 406 u32 cmd; 407 408 if (!trace_ufshcd_uic_command_enabled()) 409 return; 410 411 if (str_t == UFS_CMD_SEND) 412 cmd = ucmd->command; 413 else 414 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 415 416 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 417 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 418 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 419 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 420 } 421 422 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 423 enum ufs_trace_str_t str_t) 424 { 425 u64 lba = 0; 426 u8 opcode = 0, group_id = 0; 427 u32 doorbell = 0; 428 u32 intr; 429 int hwq_id = -1; 430 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 431 struct scsi_cmnd *cmd = lrbp->cmd; 432 struct request *rq = scsi_cmd_to_rq(cmd); 433 int transfer_len = -1; 434 435 if (!cmd) 436 return; 437 438 /* trace UPIU also */ 439 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 440 if (!trace_ufshcd_command_enabled()) 441 return; 442 443 opcode = cmd->cmnd[0]; 444 445 if (opcode == READ_10 || opcode == WRITE_10) { 446 /* 447 * Currently we only fully trace read(10) and write(10) commands 448 */ 449 transfer_len = 450 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 451 lba = scsi_get_lba(cmd); 452 if (opcode == WRITE_10) 453 group_id = lrbp->cmd->cmnd[6]; 454 } else if (opcode == UNMAP) { 455 /* 456 * The number of Bytes to be unmapped beginning with the lba. 457 */ 458 transfer_len = blk_rq_bytes(rq); 459 lba = scsi_get_lba(cmd); 460 } 461 462 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 463 464 if (hba->mcq_enabled) { 465 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 466 467 hwq_id = hwq->id; 468 } else { 469 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 470 } 471 trace_ufshcd_command(cmd->device, str_t, tag, doorbell, hwq_id, 472 transfer_len, intr, lba, opcode, group_id); 473 } 474 475 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 476 { 477 struct ufs_clk_info *clki; 478 struct list_head *head = &hba->clk_list_head; 479 480 if (list_empty(head)) 481 return; 482 483 list_for_each_entry(clki, head, list) { 484 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 485 clki->max_freq) 486 dev_err(hba->dev, "clk: %s, rate: %u\n", 487 clki->name, clki->curr_freq); 488 } 489 } 490 491 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 492 const char *err_name) 493 { 494 int i; 495 bool found = false; 496 const struct ufs_event_hist *e; 497 498 if (id >= UFS_EVT_CNT) 499 return; 500 501 e = &hba->ufs_stats.event[id]; 502 503 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 504 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 505 506 if (e->tstamp[p] == 0) 507 continue; 508 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 509 e->val[p], div_u64(e->tstamp[p], 1000)); 510 found = true; 511 } 512 513 if (!found) 514 dev_err(hba->dev, "No record of %s\n", err_name); 515 else 516 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 517 } 518 519 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 520 { 521 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 522 523 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 524 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 525 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 526 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 527 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 528 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 529 "auto_hibern8_err"); 530 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 531 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 532 "link_startup_fail"); 533 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 534 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 535 "suspend_fail"); 536 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 537 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 538 "wlun suspend_fail"); 539 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 540 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 541 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 542 543 ufshcd_vops_dbg_register_dump(hba); 544 } 545 546 static 547 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 548 { 549 const struct ufshcd_lrb *lrbp; 550 int prdt_length; 551 552 lrbp = &hba->lrb[tag]; 553 554 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 555 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 556 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 557 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 558 dev_err(hba->dev, 559 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 560 tag, (u64)lrbp->utrd_dma_addr); 561 562 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 563 sizeof(struct utp_transfer_req_desc)); 564 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 565 (u64)lrbp->ucd_req_dma_addr); 566 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 567 sizeof(struct utp_upiu_req)); 568 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 569 (u64)lrbp->ucd_rsp_dma_addr); 570 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 571 sizeof(struct utp_upiu_rsp)); 572 573 prdt_length = le16_to_cpu( 574 lrbp->utr_descriptor_ptr->prd_table_length); 575 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 576 prdt_length /= ufshcd_sg_entry_size(hba); 577 578 dev_err(hba->dev, 579 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 580 tag, prdt_length, 581 (u64)lrbp->ucd_prdt_dma_addr); 582 583 if (pr_prdt) 584 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 585 ufshcd_sg_entry_size(hba) * prdt_length); 586 } 587 588 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 589 { 590 struct scsi_device *sdev = req->q->queuedata; 591 struct Scsi_Host *shost = sdev->host; 592 struct ufs_hba *hba = shost_priv(shost); 593 594 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 595 596 return true; 597 } 598 599 /** 600 * ufshcd_print_trs_all - print trs for all started requests. 601 * @hba: per-adapter instance. 602 * @pr_prdt: need to print prdt or not. 603 */ 604 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 605 { 606 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 607 } 608 609 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 610 { 611 int tag; 612 613 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 614 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 615 616 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 617 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 618 } 619 } 620 621 static void ufshcd_print_host_state(struct ufs_hba *hba) 622 { 623 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 624 625 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 626 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 627 hba->outstanding_reqs, hba->outstanding_tasks); 628 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 629 hba->saved_err, hba->saved_uic_err); 630 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 631 hba->curr_dev_pwr_mode, hba->uic_link_state); 632 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 633 hba->pm_op_in_progress, hba->is_sys_suspended); 634 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 635 hba->auto_bkops_enabled, hba->host->host_self_blocked); 636 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 637 dev_err(hba->dev, 638 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 639 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 640 hba->ufs_stats.hibern8_exit_cnt); 641 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 642 div_u64(hba->ufs_stats.last_intr_ts, 1000), 643 hba->ufs_stats.last_intr_status); 644 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 645 hba->eh_flags, hba->req_abort_count); 646 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 647 hba->ufs_version, hba->capabilities, hba->caps); 648 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 649 hba->dev_quirks); 650 if (sdev_ufs) 651 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 652 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 653 654 ufshcd_print_clk_freqs(hba); 655 } 656 657 /** 658 * ufshcd_print_pwr_info - print power params as saved in hba 659 * power info 660 * @hba: per-adapter instance 661 */ 662 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 663 { 664 static const char * const names[] = { 665 "INVALID MODE", 666 "FAST MODE", 667 "SLOW_MODE", 668 "INVALID MODE", 669 "FASTAUTO_MODE", 670 "SLOWAUTO_MODE", 671 "INVALID MODE", 672 }; 673 674 /* 675 * Using dev_dbg to avoid messages during runtime PM to avoid 676 * never-ending cycles of messages written back to storage by user space 677 * causing runtime resume, causing more messages and so on. 678 */ 679 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 680 __func__, 681 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 682 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 683 names[hba->pwr_info.pwr_rx], 684 names[hba->pwr_info.pwr_tx], 685 hba->pwr_info.hs_rate); 686 } 687 688 static void ufshcd_device_reset(struct ufs_hba *hba) 689 { 690 int err; 691 692 err = ufshcd_vops_device_reset(hba); 693 694 if (!err) { 695 ufshcd_set_ufs_dev_active(hba); 696 if (ufshcd_is_wb_allowed(hba)) { 697 hba->dev_info.wb_enabled = false; 698 hba->dev_info.wb_buf_flush_enabled = false; 699 } 700 if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 701 hba->dev_info.rtc_time_baseline = 0; 702 } 703 if (err != -EOPNOTSUPP) 704 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 705 } 706 707 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 708 { 709 if (!us) 710 return; 711 712 if (us < 10) 713 udelay(us); 714 else 715 usleep_range(us, us + tolerance); 716 } 717 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 718 719 /** 720 * ufshcd_wait_for_register - wait for register value to change 721 * @hba: per-adapter interface 722 * @reg: mmio register offset 723 * @mask: mask to apply to the read register value 724 * @val: value to wait for 725 * @interval_us: polling interval in microseconds 726 * @timeout_ms: timeout in milliseconds 727 * 728 * Return: -ETIMEDOUT on error, zero on success. 729 */ 730 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 731 u32 val, unsigned long interval_us, 732 unsigned long timeout_ms) 733 { 734 u32 v; 735 736 val &= mask; /* ignore bits that we don't intend to wait on */ 737 738 return read_poll_timeout(ufshcd_readl, v, (v & mask) == val, 739 interval_us, timeout_ms * 1000, false, hba, reg); 740 } 741 742 /** 743 * ufshcd_get_intr_mask - Get the interrupt bit mask 744 * @hba: Pointer to adapter instance 745 * 746 * Return: interrupt bit mask per version 747 */ 748 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 749 { 750 if (hba->ufs_version <= ufshci_version(2, 0)) 751 return INTERRUPT_MASK_ALL_VER_11; 752 753 return INTERRUPT_MASK_ALL_VER_21; 754 } 755 756 /** 757 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 758 * @hba: Pointer to adapter instance 759 * 760 * Return: UFSHCI version supported by the controller 761 */ 762 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 763 { 764 u32 ufshci_ver; 765 766 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 767 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 768 else 769 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 770 771 /* 772 * UFSHCI v1.x uses a different version scheme, in order 773 * to allow the use of comparisons with the ufshci_version 774 * function, we convert it to the same scheme as ufs 2.0+. 775 */ 776 if (ufshci_ver & 0x00010000) 777 return ufshci_version(1, ufshci_ver & 0x00000100); 778 779 return ufshci_ver; 780 } 781 782 /** 783 * ufshcd_is_device_present - Check if any device connected to 784 * the host controller 785 * @hba: pointer to adapter instance 786 * 787 * Return: true if device present, false if no device detected 788 */ 789 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 790 { 791 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 792 } 793 794 /** 795 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 796 * @lrbp: pointer to local command reference block 797 * @cqe: pointer to the completion queue entry 798 * 799 * This function is used to get the OCS field from UTRD 800 * 801 * Return: the OCS field in the UTRD. 802 */ 803 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 804 struct cq_entry *cqe) 805 { 806 if (cqe) 807 return le32_to_cpu(cqe->status) & MASK_OCS; 808 809 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 810 } 811 812 /** 813 * ufshcd_utrl_clear() - Clear requests from the controller request list. 814 * @hba: per adapter instance 815 * @mask: mask with one bit set for each request to be cleared 816 */ 817 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 818 { 819 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 820 mask = ~mask; 821 /* 822 * From the UFSHCI specification: "UTP Transfer Request List CLear 823 * Register (UTRLCLR): This field is bit significant. Each bit 824 * corresponds to a slot in the UTP Transfer Request List, where bit 0 825 * corresponds to request slot 0. A bit in this field is set to ‘0’ 826 * by host software to indicate to the host controller that a transfer 827 * request slot is cleared. The host controller 828 * shall free up any resources associated to the request slot 829 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 830 * host software indicates no change to request slots by setting the 831 * associated bits in this field to ‘1’. Bits in this field shall only 832 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 833 */ 834 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 835 } 836 837 /** 838 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 839 * @hba: per adapter instance 840 * @pos: position of the bit to be cleared 841 */ 842 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 843 { 844 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 845 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 846 else 847 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 848 } 849 850 /** 851 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 852 * @reg: Register value of host controller status 853 * 854 * Return: 0 on success; a positive value if failed. 855 */ 856 static inline int ufshcd_get_lists_status(u32 reg) 857 { 858 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 859 } 860 861 /** 862 * ufshcd_get_uic_cmd_result - Get the UIC command result 863 * @hba: Pointer to adapter instance 864 * 865 * This function gets the result of UIC command completion 866 * 867 * Return: 0 on success; non-zero value on error. 868 */ 869 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 870 { 871 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 872 MASK_UIC_COMMAND_RESULT; 873 } 874 875 /** 876 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 877 * @hba: Pointer to adapter instance 878 * 879 * This function gets UIC command argument3 880 * 881 * Return: 0 on success; non-zero value on error. 882 */ 883 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 884 { 885 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 886 } 887 888 /** 889 * ufshcd_get_req_rsp - returns the TR response transaction type 890 * @ucd_rsp_ptr: pointer to response UPIU 891 * 892 * Return: UPIU type. 893 */ 894 static inline enum upiu_response_transaction 895 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 896 { 897 return ucd_rsp_ptr->header.transaction_code; 898 } 899 900 /** 901 * ufshcd_is_exception_event - Check if the device raised an exception event 902 * @ucd_rsp_ptr: pointer to response UPIU 903 * 904 * The function checks if the device raised an exception event indicated in 905 * the Device Information field of response UPIU. 906 * 907 * Return: true if exception is raised, false otherwise. 908 */ 909 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 910 { 911 return ucd_rsp_ptr->header.device_information & 1; 912 } 913 914 /** 915 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 916 * @hba: per adapter instance 917 */ 918 static inline void 919 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 920 { 921 ufshcd_writel(hba, INT_AGGR_ENABLE | 922 INT_AGGR_COUNTER_AND_TIMER_RESET, 923 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 924 } 925 926 /** 927 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 928 * @hba: per adapter instance 929 * @cnt: Interrupt aggregation counter threshold 930 * @tmout: Interrupt aggregation timeout value 931 */ 932 static inline void 933 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 934 { 935 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 936 INT_AGGR_COUNTER_THLD_VAL(cnt) | 937 INT_AGGR_TIMEOUT_VAL(tmout), 938 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 939 } 940 941 /** 942 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 943 * @hba: per adapter instance 944 */ 945 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 946 { 947 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 948 } 949 950 /** 951 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 952 * When run-stop registers are set to 1, it indicates the 953 * host controller that it can process the requests 954 * @hba: per adapter instance 955 */ 956 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 957 { 958 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 959 REG_UTP_TASK_REQ_LIST_RUN_STOP); 960 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 961 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 962 } 963 964 /** 965 * ufshcd_hba_start - Start controller initialization sequence 966 * @hba: per adapter instance 967 */ 968 static inline void ufshcd_hba_start(struct ufs_hba *hba) 969 { 970 u32 val = CONTROLLER_ENABLE; 971 972 if (ufshcd_crypto_enable(hba)) 973 val |= CRYPTO_GENERAL_ENABLE; 974 975 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 976 } 977 978 /** 979 * ufshcd_is_hba_active - Get controller state 980 * @hba: per adapter instance 981 * 982 * Return: true if and only if the controller is active. 983 */ 984 bool ufshcd_is_hba_active(struct ufs_hba *hba) 985 { 986 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 987 } 988 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 989 990 /** 991 * ufshcd_pm_qos_init - initialize PM QoS request 992 * @hba: per adapter instance 993 */ 994 void ufshcd_pm_qos_init(struct ufs_hba *hba) 995 { 996 997 if (hba->pm_qos_enabled) 998 return; 999 1000 cpu_latency_qos_add_request(&hba->pm_qos_req, PM_QOS_DEFAULT_VALUE); 1001 1002 if (cpu_latency_qos_request_active(&hba->pm_qos_req)) 1003 hba->pm_qos_enabled = true; 1004 } 1005 1006 /** 1007 * ufshcd_pm_qos_exit - remove request from PM QoS 1008 * @hba: per adapter instance 1009 */ 1010 void ufshcd_pm_qos_exit(struct ufs_hba *hba) 1011 { 1012 if (!hba->pm_qos_enabled) 1013 return; 1014 1015 cpu_latency_qos_remove_request(&hba->pm_qos_req); 1016 hba->pm_qos_enabled = false; 1017 } 1018 1019 /** 1020 * ufshcd_pm_qos_update - update PM QoS request 1021 * @hba: per adapter instance 1022 * @on: If True, vote for perf PM QoS mode otherwise power save mode 1023 */ 1024 static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) 1025 { 1026 if (!hba->pm_qos_enabled) 1027 return; 1028 1029 cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE); 1030 } 1031 1032 /** 1033 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1034 * @hba: per adapter instance 1035 * @scale_up: If True, set max possible frequency othewise set low frequency 1036 * 1037 * Return: 0 if successful; < 0 upon failure. 1038 */ 1039 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1040 { 1041 int ret = 0; 1042 struct ufs_clk_info *clki; 1043 struct list_head *head = &hba->clk_list_head; 1044 1045 if (list_empty(head)) 1046 goto out; 1047 1048 list_for_each_entry(clki, head, list) { 1049 if (!IS_ERR_OR_NULL(clki->clk)) { 1050 if (scale_up && clki->max_freq) { 1051 if (clki->curr_freq == clki->max_freq) 1052 continue; 1053 1054 ret = clk_set_rate(clki->clk, clki->max_freq); 1055 if (ret) { 1056 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1057 __func__, clki->name, 1058 clki->max_freq, ret); 1059 break; 1060 } 1061 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1062 "scaled up", clki->name, 1063 clki->curr_freq, 1064 clki->max_freq); 1065 1066 clki->curr_freq = clki->max_freq; 1067 1068 } else if (!scale_up && clki->min_freq) { 1069 if (clki->curr_freq == clki->min_freq) 1070 continue; 1071 1072 ret = clk_set_rate(clki->clk, clki->min_freq); 1073 if (ret) { 1074 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1075 __func__, clki->name, 1076 clki->min_freq, ret); 1077 break; 1078 } 1079 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1080 "scaled down", clki->name, 1081 clki->curr_freq, 1082 clki->min_freq); 1083 clki->curr_freq = clki->min_freq; 1084 } 1085 } 1086 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1087 clki->name, clk_get_rate(clki->clk)); 1088 } 1089 1090 out: 1091 return ret; 1092 } 1093 1094 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1095 struct dev_pm_opp *opp, void *data, 1096 bool scaling_down) 1097 { 1098 struct ufs_hba *hba = dev_get_drvdata(dev); 1099 struct list_head *head = &hba->clk_list_head; 1100 struct ufs_clk_info *clki; 1101 unsigned long freq; 1102 u8 idx = 0; 1103 int ret; 1104 1105 list_for_each_entry(clki, head, list) { 1106 if (!IS_ERR_OR_NULL(clki->clk)) { 1107 freq = dev_pm_opp_get_freq_indexed(opp, idx++); 1108 1109 /* Do not set rate for clocks having frequency as 0 */ 1110 if (!freq) 1111 continue; 1112 1113 ret = clk_set_rate(clki->clk, freq); 1114 if (ret) { 1115 dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n", 1116 __func__, clki->name, freq, ret); 1117 return ret; 1118 } 1119 1120 trace_ufshcd_clk_scaling(dev_name(dev), 1121 (scaling_down ? "scaled down" : "scaled up"), 1122 clki->name, hba->clk_scaling.target_freq, freq); 1123 } 1124 } 1125 1126 return 0; 1127 } 1128 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks); 1129 1130 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) 1131 { 1132 struct dev_pm_opp *opp; 1133 int ret; 1134 1135 opp = dev_pm_opp_find_freq_floor_indexed(hba->dev, 1136 &freq, 0); 1137 if (IS_ERR(opp)) 1138 return PTR_ERR(opp); 1139 1140 ret = dev_pm_opp_set_opp(hba->dev, opp); 1141 dev_pm_opp_put(opp); 1142 1143 return ret; 1144 } 1145 1146 /** 1147 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1148 * @hba: per adapter instance 1149 * @freq: frequency to scale 1150 * @scale_up: True if scaling up and false if scaling down 1151 * 1152 * Return: 0 if successful; < 0 upon failure. 1153 */ 1154 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 1155 bool scale_up) 1156 { 1157 int ret = 0; 1158 ktime_t start = ktime_get(); 1159 1160 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1161 if (ret) 1162 goto out; 1163 1164 if (hba->use_pm_opp) 1165 ret = ufshcd_opp_set_rate(hba, freq); 1166 else 1167 ret = ufshcd_set_clk_freq(hba, scale_up); 1168 if (ret) 1169 goto out; 1170 1171 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1172 if (ret) { 1173 if (hba->use_pm_opp) 1174 ufshcd_opp_set_rate(hba, 1175 hba->devfreq->previous_freq); 1176 else 1177 ufshcd_set_clk_freq(hba, !scale_up); 1178 goto out; 1179 } 1180 1181 ufshcd_pm_qos_update(hba, scale_up); 1182 1183 out: 1184 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1185 (scale_up ? "up" : "down"), 1186 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1187 return ret; 1188 } 1189 1190 /** 1191 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1192 * @hba: per adapter instance 1193 * @freq: frequency to scale 1194 * @scale_up: True if scaling up and false if scaling down 1195 * 1196 * Return: true if scaling is required, false otherwise. 1197 */ 1198 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1199 unsigned long freq, bool scale_up) 1200 { 1201 struct ufs_clk_info *clki; 1202 struct list_head *head = &hba->clk_list_head; 1203 1204 if (list_empty(head)) 1205 return false; 1206 1207 if (hba->use_pm_opp) 1208 return freq != hba->clk_scaling.target_freq; 1209 1210 list_for_each_entry(clki, head, list) { 1211 if (!IS_ERR_OR_NULL(clki->clk)) { 1212 if (scale_up && clki->max_freq) { 1213 if (clki->curr_freq == clki->max_freq) 1214 continue; 1215 return true; 1216 } else if (!scale_up && clki->min_freq) { 1217 if (clki->curr_freq == clki->min_freq) 1218 continue; 1219 return true; 1220 } 1221 } 1222 } 1223 1224 return false; 1225 } 1226 1227 /* 1228 * Determine the number of pending commands by counting the bits in the SCSI 1229 * device budget maps. This approach has been selected because a bit is set in 1230 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1231 * flag. The host_self_blocked flag can be modified by calling 1232 * scsi_block_requests() or scsi_unblock_requests(). 1233 */ 1234 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1235 { 1236 const struct scsi_device *sdev; 1237 unsigned long flags; 1238 u32 pending = 0; 1239 1240 spin_lock_irqsave(hba->host->host_lock, flags); 1241 __shost_for_each_device(sdev, hba->host) 1242 pending += sbitmap_weight(&sdev->budget_map); 1243 spin_unlock_irqrestore(hba->host->host_lock, flags); 1244 1245 return pending; 1246 } 1247 1248 /* 1249 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1250 * has expired. 1251 * 1252 * Return: 0 upon success; -EBUSY upon timeout. 1253 */ 1254 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1255 u64 wait_timeout_us) 1256 { 1257 int ret = 0; 1258 u32 tm_doorbell; 1259 u32 tr_pending; 1260 bool timeout = false, do_last_check = false; 1261 ktime_t start; 1262 1263 ufshcd_hold(hba); 1264 /* 1265 * Wait for all the outstanding tasks/transfer requests. 1266 * Verify by checking the doorbell registers are clear. 1267 */ 1268 start = ktime_get(); 1269 do { 1270 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1271 ret = -EBUSY; 1272 goto out; 1273 } 1274 1275 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1276 tr_pending = ufshcd_pending_cmds(hba); 1277 if (!tm_doorbell && !tr_pending) { 1278 timeout = false; 1279 break; 1280 } else if (do_last_check) { 1281 break; 1282 } 1283 1284 io_schedule_timeout(msecs_to_jiffies(20)); 1285 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1286 wait_timeout_us) { 1287 timeout = true; 1288 /* 1289 * We might have scheduled out for long time so make 1290 * sure to check if doorbells are cleared by this time 1291 * or not. 1292 */ 1293 do_last_check = true; 1294 } 1295 } while (tm_doorbell || tr_pending); 1296 1297 if (timeout) { 1298 dev_err(hba->dev, 1299 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1300 __func__, tm_doorbell, tr_pending); 1301 ret = -EBUSY; 1302 } 1303 out: 1304 ufshcd_release(hba); 1305 return ret; 1306 } 1307 1308 /** 1309 * ufshcd_scale_gear - scale up/down UFS gear 1310 * @hba: per adapter instance 1311 * @scale_up: True for scaling up gear and false for scaling down 1312 * 1313 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1314 * non-zero for any other errors. 1315 */ 1316 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1317 { 1318 int ret = 0; 1319 struct ufs_pa_layer_attr new_pwr_info; 1320 1321 if (scale_up) { 1322 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1323 sizeof(struct ufs_pa_layer_attr)); 1324 } else { 1325 memcpy(&new_pwr_info, &hba->pwr_info, 1326 sizeof(struct ufs_pa_layer_attr)); 1327 1328 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1329 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1330 /* save the current power mode */ 1331 memcpy(&hba->clk_scaling.saved_pwr_info, 1332 &hba->pwr_info, 1333 sizeof(struct ufs_pa_layer_attr)); 1334 1335 /* scale down gear */ 1336 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1337 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1338 } 1339 } 1340 1341 /* check if the power mode needs to be changed or not? */ 1342 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1343 if (ret) 1344 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1345 __func__, ret, 1346 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1347 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1348 1349 return ret; 1350 } 1351 1352 /* 1353 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1354 * has expired. 1355 * 1356 * Return: 0 upon success; -EBUSY upon timeout. 1357 */ 1358 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1359 { 1360 int ret = 0; 1361 /* 1362 * make sure that there are no outstanding requests when 1363 * clock scaling is in progress 1364 */ 1365 blk_mq_quiesce_tagset(&hba->host->tag_set); 1366 mutex_lock(&hba->wb_mutex); 1367 down_write(&hba->clk_scaling_lock); 1368 1369 if (!hba->clk_scaling.is_allowed || 1370 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1371 ret = -EBUSY; 1372 up_write(&hba->clk_scaling_lock); 1373 mutex_unlock(&hba->wb_mutex); 1374 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1375 goto out; 1376 } 1377 1378 /* let's not get into low power until clock scaling is completed */ 1379 ufshcd_hold(hba); 1380 1381 out: 1382 return ret; 1383 } 1384 1385 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1386 { 1387 up_write(&hba->clk_scaling_lock); 1388 1389 /* Enable Write Booster if we have scaled up else disable it */ 1390 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1391 ufshcd_wb_toggle(hba, scale_up); 1392 1393 mutex_unlock(&hba->wb_mutex); 1394 1395 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1396 ufshcd_release(hba); 1397 } 1398 1399 /** 1400 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1401 * @hba: per adapter instance 1402 * @freq: frequency to scale 1403 * @scale_up: True for scaling up and false for scalin down 1404 * 1405 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1406 * for any other errors. 1407 */ 1408 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, 1409 bool scale_up) 1410 { 1411 int ret = 0; 1412 1413 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1414 if (ret) 1415 return ret; 1416 1417 /* scale down the gear before scaling down clocks */ 1418 if (!scale_up) { 1419 ret = ufshcd_scale_gear(hba, false); 1420 if (ret) 1421 goto out_unprepare; 1422 } 1423 1424 ret = ufshcd_scale_clks(hba, freq, scale_up); 1425 if (ret) { 1426 if (!scale_up) 1427 ufshcd_scale_gear(hba, true); 1428 goto out_unprepare; 1429 } 1430 1431 /* scale up the gear after scaling up clocks */ 1432 if (scale_up) { 1433 ret = ufshcd_scale_gear(hba, true); 1434 if (ret) { 1435 ufshcd_scale_clks(hba, hba->devfreq->previous_freq, 1436 false); 1437 goto out_unprepare; 1438 } 1439 } 1440 1441 out_unprepare: 1442 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1443 return ret; 1444 } 1445 1446 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1447 { 1448 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1449 clk_scaling.suspend_work); 1450 unsigned long irq_flags; 1451 1452 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1453 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1454 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1455 return; 1456 } 1457 hba->clk_scaling.is_suspended = true; 1458 hba->clk_scaling.window_start_t = 0; 1459 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1460 1461 devfreq_suspend_device(hba->devfreq); 1462 } 1463 1464 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1465 { 1466 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1467 clk_scaling.resume_work); 1468 unsigned long irq_flags; 1469 1470 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1471 if (!hba->clk_scaling.is_suspended) { 1472 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1473 return; 1474 } 1475 hba->clk_scaling.is_suspended = false; 1476 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1477 1478 devfreq_resume_device(hba->devfreq); 1479 } 1480 1481 static int ufshcd_devfreq_target(struct device *dev, 1482 unsigned long *freq, u32 flags) 1483 { 1484 int ret = 0; 1485 struct ufs_hba *hba = dev_get_drvdata(dev); 1486 ktime_t start; 1487 bool scale_up = false, sched_clk_scaling_suspend_work = false; 1488 struct list_head *clk_list = &hba->clk_list_head; 1489 struct ufs_clk_info *clki; 1490 unsigned long irq_flags; 1491 1492 if (!ufshcd_is_clkscaling_supported(hba)) 1493 return -EINVAL; 1494 1495 if (hba->use_pm_opp) { 1496 struct dev_pm_opp *opp; 1497 1498 /* Get the recommended frequency from OPP framework */ 1499 opp = devfreq_recommended_opp(dev, freq, flags); 1500 if (IS_ERR(opp)) 1501 return PTR_ERR(opp); 1502 1503 dev_pm_opp_put(opp); 1504 } else { 1505 /* Override with the closest supported frequency */ 1506 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, 1507 list); 1508 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1509 } 1510 1511 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1512 if (ufshcd_eh_in_progress(hba)) { 1513 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1514 return 0; 1515 } 1516 1517 /* Skip scaling clock when clock scaling is suspended */ 1518 if (hba->clk_scaling.is_suspended) { 1519 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1520 dev_warn(hba->dev, "clock scaling is suspended, skip"); 1521 return 0; 1522 } 1523 1524 if (!hba->clk_scaling.active_reqs) 1525 sched_clk_scaling_suspend_work = true; 1526 1527 if (list_empty(clk_list)) { 1528 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1529 goto out; 1530 } 1531 1532 /* Decide based on the target or rounded-off frequency and update */ 1533 if (hba->use_pm_opp) 1534 scale_up = *freq > hba->clk_scaling.target_freq; 1535 else 1536 scale_up = *freq == clki->max_freq; 1537 1538 if (!hba->use_pm_opp && !scale_up) 1539 *freq = clki->min_freq; 1540 1541 /* Update the frequency */ 1542 if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) { 1543 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1544 ret = 0; 1545 goto out; /* no state change required */ 1546 } 1547 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1548 1549 start = ktime_get(); 1550 ret = ufshcd_devfreq_scale(hba, *freq, scale_up); 1551 if (!ret) 1552 hba->clk_scaling.target_freq = *freq; 1553 1554 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1555 (scale_up ? "up" : "down"), 1556 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1557 1558 out: 1559 if (sched_clk_scaling_suspend_work && 1560 (!scale_up || hba->clk_scaling.suspend_on_no_request)) 1561 queue_work(hba->clk_scaling.workq, 1562 &hba->clk_scaling.suspend_work); 1563 1564 return ret; 1565 } 1566 1567 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1568 struct devfreq_dev_status *stat) 1569 { 1570 struct ufs_hba *hba = dev_get_drvdata(dev); 1571 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1572 unsigned long flags; 1573 ktime_t curr_t; 1574 1575 if (!ufshcd_is_clkscaling_supported(hba)) 1576 return -EINVAL; 1577 1578 memset(stat, 0, sizeof(*stat)); 1579 1580 spin_lock_irqsave(hba->host->host_lock, flags); 1581 curr_t = ktime_get(); 1582 if (!scaling->window_start_t) 1583 goto start_window; 1584 1585 /* 1586 * If current frequency is 0, then the ondemand governor considers 1587 * there's no initial frequency set. And it always requests to set 1588 * to max. frequency. 1589 */ 1590 if (hba->use_pm_opp) { 1591 stat->current_frequency = hba->clk_scaling.target_freq; 1592 } else { 1593 struct list_head *clk_list = &hba->clk_list_head; 1594 struct ufs_clk_info *clki; 1595 1596 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1597 stat->current_frequency = clki->curr_freq; 1598 } 1599 1600 if (scaling->is_busy_started) 1601 scaling->tot_busy_t += ktime_us_delta(curr_t, 1602 scaling->busy_start_t); 1603 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1604 stat->busy_time = scaling->tot_busy_t; 1605 start_window: 1606 scaling->window_start_t = curr_t; 1607 scaling->tot_busy_t = 0; 1608 1609 if (scaling->active_reqs) { 1610 scaling->busy_start_t = curr_t; 1611 scaling->is_busy_started = true; 1612 } else { 1613 scaling->busy_start_t = 0; 1614 scaling->is_busy_started = false; 1615 } 1616 spin_unlock_irqrestore(hba->host->host_lock, flags); 1617 return 0; 1618 } 1619 1620 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1621 { 1622 struct list_head *clk_list = &hba->clk_list_head; 1623 struct ufs_clk_info *clki; 1624 struct devfreq *devfreq; 1625 int ret; 1626 1627 /* Skip devfreq if we don't have any clocks in the list */ 1628 if (list_empty(clk_list)) 1629 return 0; 1630 1631 if (!hba->use_pm_opp) { 1632 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1633 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1634 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1635 } 1636 1637 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1638 &hba->vps->ondemand_data); 1639 devfreq = devfreq_add_device(hba->dev, 1640 &hba->vps->devfreq_profile, 1641 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1642 &hba->vps->ondemand_data); 1643 if (IS_ERR(devfreq)) { 1644 ret = PTR_ERR(devfreq); 1645 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1646 1647 if (!hba->use_pm_opp) { 1648 dev_pm_opp_remove(hba->dev, clki->min_freq); 1649 dev_pm_opp_remove(hba->dev, clki->max_freq); 1650 } 1651 return ret; 1652 } 1653 1654 hba->devfreq = devfreq; 1655 1656 return 0; 1657 } 1658 1659 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1660 { 1661 struct list_head *clk_list = &hba->clk_list_head; 1662 1663 if (!hba->devfreq) 1664 return; 1665 1666 devfreq_remove_device(hba->devfreq); 1667 hba->devfreq = NULL; 1668 1669 if (!hba->use_pm_opp) { 1670 struct ufs_clk_info *clki; 1671 1672 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1673 dev_pm_opp_remove(hba->dev, clki->min_freq); 1674 dev_pm_opp_remove(hba->dev, clki->max_freq); 1675 } 1676 } 1677 1678 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1679 { 1680 unsigned long flags; 1681 bool suspend = false; 1682 1683 cancel_work_sync(&hba->clk_scaling.suspend_work); 1684 cancel_work_sync(&hba->clk_scaling.resume_work); 1685 1686 spin_lock_irqsave(hba->host->host_lock, flags); 1687 if (!hba->clk_scaling.is_suspended) { 1688 suspend = true; 1689 hba->clk_scaling.is_suspended = true; 1690 hba->clk_scaling.window_start_t = 0; 1691 } 1692 spin_unlock_irqrestore(hba->host->host_lock, flags); 1693 1694 if (suspend) 1695 devfreq_suspend_device(hba->devfreq); 1696 } 1697 1698 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1699 { 1700 unsigned long flags; 1701 bool resume = false; 1702 1703 spin_lock_irqsave(hba->host->host_lock, flags); 1704 if (hba->clk_scaling.is_suspended) { 1705 resume = true; 1706 hba->clk_scaling.is_suspended = false; 1707 } 1708 spin_unlock_irqrestore(hba->host->host_lock, flags); 1709 1710 if (resume) 1711 devfreq_resume_device(hba->devfreq); 1712 } 1713 1714 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1715 struct device_attribute *attr, char *buf) 1716 { 1717 struct ufs_hba *hba = dev_get_drvdata(dev); 1718 1719 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1720 } 1721 1722 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1723 struct device_attribute *attr, const char *buf, size_t count) 1724 { 1725 struct ufs_hba *hba = dev_get_drvdata(dev); 1726 u32 value; 1727 int err = 0; 1728 1729 if (kstrtou32(buf, 0, &value)) 1730 return -EINVAL; 1731 1732 down(&hba->host_sem); 1733 if (!ufshcd_is_user_access_allowed(hba)) { 1734 err = -EBUSY; 1735 goto out; 1736 } 1737 1738 value = !!value; 1739 if (value == hba->clk_scaling.is_enabled) 1740 goto out; 1741 1742 ufshcd_rpm_get_sync(hba); 1743 ufshcd_hold(hba); 1744 1745 hba->clk_scaling.is_enabled = value; 1746 1747 if (value) { 1748 ufshcd_resume_clkscaling(hba); 1749 } else { 1750 ufshcd_suspend_clkscaling(hba); 1751 err = ufshcd_devfreq_scale(hba, ULONG_MAX, true); 1752 if (err) 1753 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1754 __func__, err); 1755 } 1756 1757 ufshcd_release(hba); 1758 ufshcd_rpm_put_sync(hba); 1759 out: 1760 up(&hba->host_sem); 1761 return err ? err : count; 1762 } 1763 1764 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1765 { 1766 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1767 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1768 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1769 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1770 hba->clk_scaling.enable_attr.attr.mode = 0644; 1771 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1772 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1773 } 1774 1775 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1776 { 1777 if (hba->clk_scaling.enable_attr.attr.name) 1778 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1779 } 1780 1781 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1782 { 1783 if (!ufshcd_is_clkscaling_supported(hba)) 1784 return; 1785 1786 if (!hba->clk_scaling.min_gear) 1787 hba->clk_scaling.min_gear = UFS_HS_G1; 1788 1789 INIT_WORK(&hba->clk_scaling.suspend_work, 1790 ufshcd_clk_scaling_suspend_work); 1791 INIT_WORK(&hba->clk_scaling.resume_work, 1792 ufshcd_clk_scaling_resume_work); 1793 1794 hba->clk_scaling.workq = alloc_ordered_workqueue( 1795 "ufs_clkscaling_%d", WQ_MEM_RECLAIM, hba->host->host_no); 1796 1797 hba->clk_scaling.is_initialized = true; 1798 } 1799 1800 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1801 { 1802 if (!hba->clk_scaling.is_initialized) 1803 return; 1804 1805 ufshcd_remove_clk_scaling_sysfs(hba); 1806 destroy_workqueue(hba->clk_scaling.workq); 1807 ufshcd_devfreq_remove(hba); 1808 hba->clk_scaling.is_initialized = false; 1809 } 1810 1811 static void ufshcd_ungate_work(struct work_struct *work) 1812 { 1813 int ret; 1814 unsigned long flags; 1815 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1816 clk_gating.ungate_work); 1817 1818 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1819 1820 spin_lock_irqsave(hba->host->host_lock, flags); 1821 if (hba->clk_gating.state == CLKS_ON) { 1822 spin_unlock_irqrestore(hba->host->host_lock, flags); 1823 return; 1824 } 1825 1826 spin_unlock_irqrestore(hba->host->host_lock, flags); 1827 ufshcd_hba_vreg_set_hpm(hba); 1828 ufshcd_setup_clocks(hba, true); 1829 1830 ufshcd_enable_irq(hba); 1831 1832 /* Exit from hibern8 */ 1833 if (ufshcd_can_hibern8_during_gating(hba)) { 1834 /* Prevent gating in this path */ 1835 hba->clk_gating.is_suspended = true; 1836 if (ufshcd_is_link_hibern8(hba)) { 1837 ret = ufshcd_uic_hibern8_exit(hba); 1838 if (ret) 1839 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1840 __func__, ret); 1841 else 1842 ufshcd_set_link_active(hba); 1843 } 1844 hba->clk_gating.is_suspended = false; 1845 } 1846 } 1847 1848 /** 1849 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1850 * Also, exit from hibern8 mode and set the link as active. 1851 * @hba: per adapter instance 1852 */ 1853 void ufshcd_hold(struct ufs_hba *hba) 1854 { 1855 bool flush_result; 1856 unsigned long flags; 1857 1858 if (!ufshcd_is_clkgating_allowed(hba) || 1859 !hba->clk_gating.is_initialized) 1860 return; 1861 spin_lock_irqsave(hba->host->host_lock, flags); 1862 hba->clk_gating.active_reqs++; 1863 1864 start: 1865 switch (hba->clk_gating.state) { 1866 case CLKS_ON: 1867 /* 1868 * Wait for the ungate work to complete if in progress. 1869 * Though the clocks may be in ON state, the link could 1870 * still be in hibner8 state if hibern8 is allowed 1871 * during clock gating. 1872 * Make sure we exit hibern8 state also in addition to 1873 * clocks being ON. 1874 */ 1875 if (ufshcd_can_hibern8_during_gating(hba) && 1876 ufshcd_is_link_hibern8(hba)) { 1877 spin_unlock_irqrestore(hba->host->host_lock, flags); 1878 flush_result = flush_work(&hba->clk_gating.ungate_work); 1879 if (hba->clk_gating.is_suspended && !flush_result) 1880 return; 1881 spin_lock_irqsave(hba->host->host_lock, flags); 1882 goto start; 1883 } 1884 break; 1885 case REQ_CLKS_OFF: 1886 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1887 hba->clk_gating.state = CLKS_ON; 1888 trace_ufshcd_clk_gating(dev_name(hba->dev), 1889 hba->clk_gating.state); 1890 break; 1891 } 1892 /* 1893 * If we are here, it means gating work is either done or 1894 * currently running. Hence, fall through to cancel gating 1895 * work and to enable clocks. 1896 */ 1897 fallthrough; 1898 case CLKS_OFF: 1899 hba->clk_gating.state = REQ_CLKS_ON; 1900 trace_ufshcd_clk_gating(dev_name(hba->dev), 1901 hba->clk_gating.state); 1902 queue_work(hba->clk_gating.clk_gating_workq, 1903 &hba->clk_gating.ungate_work); 1904 /* 1905 * fall through to check if we should wait for this 1906 * work to be done or not. 1907 */ 1908 fallthrough; 1909 case REQ_CLKS_ON: 1910 spin_unlock_irqrestore(hba->host->host_lock, flags); 1911 flush_work(&hba->clk_gating.ungate_work); 1912 /* Make sure state is CLKS_ON before returning */ 1913 spin_lock_irqsave(hba->host->host_lock, flags); 1914 goto start; 1915 default: 1916 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1917 __func__, hba->clk_gating.state); 1918 break; 1919 } 1920 spin_unlock_irqrestore(hba->host->host_lock, flags); 1921 } 1922 EXPORT_SYMBOL_GPL(ufshcd_hold); 1923 1924 static void ufshcd_gate_work(struct work_struct *work) 1925 { 1926 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1927 clk_gating.gate_work.work); 1928 unsigned long flags; 1929 int ret; 1930 1931 spin_lock_irqsave(hba->host->host_lock, flags); 1932 /* 1933 * In case you are here to cancel this work the gating state 1934 * would be marked as REQ_CLKS_ON. In this case save time by 1935 * skipping the gating work and exit after changing the clock 1936 * state to CLKS_ON. 1937 */ 1938 if (hba->clk_gating.is_suspended || 1939 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1940 hba->clk_gating.state = CLKS_ON; 1941 trace_ufshcd_clk_gating(dev_name(hba->dev), 1942 hba->clk_gating.state); 1943 goto rel_lock; 1944 } 1945 1946 if (ufshcd_is_ufs_dev_busy(hba) || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) 1947 goto rel_lock; 1948 1949 spin_unlock_irqrestore(hba->host->host_lock, flags); 1950 1951 /* put the link into hibern8 mode before turning off clocks */ 1952 if (ufshcd_can_hibern8_during_gating(hba)) { 1953 ret = ufshcd_uic_hibern8_enter(hba); 1954 if (ret) { 1955 hba->clk_gating.state = CLKS_ON; 1956 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1957 __func__, ret); 1958 trace_ufshcd_clk_gating(dev_name(hba->dev), 1959 hba->clk_gating.state); 1960 goto out; 1961 } 1962 ufshcd_set_link_hibern8(hba); 1963 } 1964 1965 ufshcd_disable_irq(hba); 1966 1967 ufshcd_setup_clocks(hba, false); 1968 1969 /* Put the host controller in low power mode if possible */ 1970 ufshcd_hba_vreg_set_lpm(hba); 1971 /* 1972 * In case you are here to cancel this work the gating state 1973 * would be marked as REQ_CLKS_ON. In this case keep the state 1974 * as REQ_CLKS_ON which would anyway imply that clocks are off 1975 * and a request to turn them on is pending. By doing this way, 1976 * we keep the state machine in tact and this would ultimately 1977 * prevent from doing cancel work multiple times when there are 1978 * new requests arriving before the current cancel work is done. 1979 */ 1980 spin_lock_irqsave(hba->host->host_lock, flags); 1981 if (hba->clk_gating.state == REQ_CLKS_OFF) { 1982 hba->clk_gating.state = CLKS_OFF; 1983 trace_ufshcd_clk_gating(dev_name(hba->dev), 1984 hba->clk_gating.state); 1985 } 1986 rel_lock: 1987 spin_unlock_irqrestore(hba->host->host_lock, flags); 1988 out: 1989 return; 1990 } 1991 1992 /* host lock must be held before calling this variant */ 1993 static void __ufshcd_release(struct ufs_hba *hba) 1994 { 1995 if (!ufshcd_is_clkgating_allowed(hba)) 1996 return; 1997 1998 hba->clk_gating.active_reqs--; 1999 2000 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 2001 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 2002 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 2003 hba->active_uic_cmd || hba->uic_async_done || 2004 hba->clk_gating.state == CLKS_OFF) 2005 return; 2006 2007 hba->clk_gating.state = REQ_CLKS_OFF; 2008 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 2009 queue_delayed_work(hba->clk_gating.clk_gating_workq, 2010 &hba->clk_gating.gate_work, 2011 msecs_to_jiffies(hba->clk_gating.delay_ms)); 2012 } 2013 2014 void ufshcd_release(struct ufs_hba *hba) 2015 { 2016 unsigned long flags; 2017 2018 spin_lock_irqsave(hba->host->host_lock, flags); 2019 __ufshcd_release(hba); 2020 spin_unlock_irqrestore(hba->host->host_lock, flags); 2021 } 2022 EXPORT_SYMBOL_GPL(ufshcd_release); 2023 2024 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 2025 struct device_attribute *attr, char *buf) 2026 { 2027 struct ufs_hba *hba = dev_get_drvdata(dev); 2028 2029 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 2030 } 2031 2032 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 2033 { 2034 struct ufs_hba *hba = dev_get_drvdata(dev); 2035 unsigned long flags; 2036 2037 spin_lock_irqsave(hba->host->host_lock, flags); 2038 hba->clk_gating.delay_ms = value; 2039 spin_unlock_irqrestore(hba->host->host_lock, flags); 2040 } 2041 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 2042 2043 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 2044 struct device_attribute *attr, const char *buf, size_t count) 2045 { 2046 unsigned long value; 2047 2048 if (kstrtoul(buf, 0, &value)) 2049 return -EINVAL; 2050 2051 ufshcd_clkgate_delay_set(dev, value); 2052 return count; 2053 } 2054 2055 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 2056 struct device_attribute *attr, char *buf) 2057 { 2058 struct ufs_hba *hba = dev_get_drvdata(dev); 2059 2060 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 2061 } 2062 2063 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 2064 struct device_attribute *attr, const char *buf, size_t count) 2065 { 2066 struct ufs_hba *hba = dev_get_drvdata(dev); 2067 unsigned long flags; 2068 u32 value; 2069 2070 if (kstrtou32(buf, 0, &value)) 2071 return -EINVAL; 2072 2073 value = !!value; 2074 2075 spin_lock_irqsave(hba->host->host_lock, flags); 2076 if (value == hba->clk_gating.is_enabled) 2077 goto out; 2078 2079 if (value) 2080 __ufshcd_release(hba); 2081 else 2082 hba->clk_gating.active_reqs++; 2083 2084 hba->clk_gating.is_enabled = value; 2085 out: 2086 spin_unlock_irqrestore(hba->host->host_lock, flags); 2087 return count; 2088 } 2089 2090 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 2091 { 2092 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 2093 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 2094 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 2095 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 2096 hba->clk_gating.delay_attr.attr.mode = 0644; 2097 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 2098 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 2099 2100 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 2101 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 2102 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 2103 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 2104 hba->clk_gating.enable_attr.attr.mode = 0644; 2105 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 2106 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 2107 } 2108 2109 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 2110 { 2111 if (hba->clk_gating.delay_attr.attr.name) 2112 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 2113 if (hba->clk_gating.enable_attr.attr.name) 2114 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 2115 } 2116 2117 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 2118 { 2119 if (!ufshcd_is_clkgating_allowed(hba)) 2120 return; 2121 2122 hba->clk_gating.state = CLKS_ON; 2123 2124 hba->clk_gating.delay_ms = 150; 2125 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2126 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2127 2128 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue( 2129 "ufs_clk_gating_%d", WQ_MEM_RECLAIM | WQ_HIGHPRI, 2130 hba->host->host_no); 2131 2132 ufshcd_init_clk_gating_sysfs(hba); 2133 2134 hba->clk_gating.is_enabled = true; 2135 hba->clk_gating.is_initialized = true; 2136 } 2137 2138 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2139 { 2140 if (!hba->clk_gating.is_initialized) 2141 return; 2142 2143 ufshcd_remove_clk_gating_sysfs(hba); 2144 2145 /* Ungate the clock if necessary. */ 2146 ufshcd_hold(hba); 2147 hba->clk_gating.is_initialized = false; 2148 ufshcd_release(hba); 2149 2150 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2151 } 2152 2153 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2154 { 2155 bool queue_resume_work = false; 2156 ktime_t curr_t = ktime_get(); 2157 unsigned long flags; 2158 2159 if (!ufshcd_is_clkscaling_supported(hba)) 2160 return; 2161 2162 spin_lock_irqsave(hba->host->host_lock, flags); 2163 if (!hba->clk_scaling.active_reqs++) 2164 queue_resume_work = true; 2165 2166 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2167 spin_unlock_irqrestore(hba->host->host_lock, flags); 2168 return; 2169 } 2170 2171 if (queue_resume_work) 2172 queue_work(hba->clk_scaling.workq, 2173 &hba->clk_scaling.resume_work); 2174 2175 if (!hba->clk_scaling.window_start_t) { 2176 hba->clk_scaling.window_start_t = curr_t; 2177 hba->clk_scaling.tot_busy_t = 0; 2178 hba->clk_scaling.is_busy_started = false; 2179 } 2180 2181 if (!hba->clk_scaling.is_busy_started) { 2182 hba->clk_scaling.busy_start_t = curr_t; 2183 hba->clk_scaling.is_busy_started = true; 2184 } 2185 spin_unlock_irqrestore(hba->host->host_lock, flags); 2186 } 2187 2188 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2189 { 2190 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2191 unsigned long flags; 2192 2193 if (!ufshcd_is_clkscaling_supported(hba)) 2194 return; 2195 2196 spin_lock_irqsave(hba->host->host_lock, flags); 2197 hba->clk_scaling.active_reqs--; 2198 if (!scaling->active_reqs && scaling->is_busy_started) { 2199 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2200 scaling->busy_start_t)); 2201 scaling->busy_start_t = 0; 2202 scaling->is_busy_started = false; 2203 } 2204 spin_unlock_irqrestore(hba->host->host_lock, flags); 2205 } 2206 2207 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2208 { 2209 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2210 return READ; 2211 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2212 return WRITE; 2213 else 2214 return -EINVAL; 2215 } 2216 2217 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2218 struct ufshcd_lrb *lrbp) 2219 { 2220 const struct ufs_hba_monitor *m = &hba->monitor; 2221 2222 return (m->enabled && lrbp && lrbp->cmd && 2223 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2224 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2225 } 2226 2227 static void ufshcd_start_monitor(struct ufs_hba *hba, 2228 const struct ufshcd_lrb *lrbp) 2229 { 2230 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2231 unsigned long flags; 2232 2233 spin_lock_irqsave(hba->host->host_lock, flags); 2234 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2235 hba->monitor.busy_start_ts[dir] = ktime_get(); 2236 spin_unlock_irqrestore(hba->host->host_lock, flags); 2237 } 2238 2239 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2240 { 2241 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2242 unsigned long flags; 2243 2244 spin_lock_irqsave(hba->host->host_lock, flags); 2245 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2246 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2247 struct ufs_hba_monitor *m = &hba->monitor; 2248 ktime_t now, inc, lat; 2249 2250 now = lrbp->compl_time_stamp; 2251 inc = ktime_sub(now, m->busy_start_ts[dir]); 2252 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2253 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2254 2255 /* Update latencies */ 2256 m->nr_req[dir]++; 2257 lat = ktime_sub(now, lrbp->issue_time_stamp); 2258 m->lat_sum[dir] += lat; 2259 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2260 m->lat_max[dir] = lat; 2261 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2262 m->lat_min[dir] = lat; 2263 2264 m->nr_queued[dir]--; 2265 /* Push forward the busy start of monitor */ 2266 m->busy_start_ts[dir] = now; 2267 } 2268 spin_unlock_irqrestore(hba->host->host_lock, flags); 2269 } 2270 2271 /** 2272 * ufshcd_send_command - Send SCSI or device management commands 2273 * @hba: per adapter instance 2274 * @task_tag: Task tag of the command 2275 * @hwq: pointer to hardware queue instance 2276 */ 2277 static inline 2278 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2279 struct ufs_hw_queue *hwq) 2280 { 2281 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2282 unsigned long flags; 2283 2284 lrbp->issue_time_stamp = ktime_get(); 2285 lrbp->issue_time_stamp_local_clock = local_clock(); 2286 lrbp->compl_time_stamp = ktime_set(0, 0); 2287 lrbp->compl_time_stamp_local_clock = 0; 2288 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2289 if (lrbp->cmd) 2290 ufshcd_clk_scaling_start_busy(hba); 2291 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2292 ufshcd_start_monitor(hba, lrbp); 2293 2294 if (hba->mcq_enabled) { 2295 int utrd_size = sizeof(struct utp_transfer_req_desc); 2296 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2297 struct utp_transfer_req_desc *dest; 2298 2299 spin_lock(&hwq->sq_lock); 2300 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2301 memcpy(dest, src, utrd_size); 2302 ufshcd_inc_sq_tail(hwq); 2303 spin_unlock(&hwq->sq_lock); 2304 } else { 2305 spin_lock_irqsave(&hba->outstanding_lock, flags); 2306 if (hba->vops && hba->vops->setup_xfer_req) 2307 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2308 !!lrbp->cmd); 2309 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2310 ufshcd_writel(hba, 1 << lrbp->task_tag, 2311 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2312 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2313 } 2314 } 2315 2316 /** 2317 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2318 * @lrbp: pointer to local reference block 2319 */ 2320 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2321 { 2322 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2323 u16 resp_len; 2324 int len; 2325 2326 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2327 if (sense_buffer && resp_len) { 2328 int len_to_copy; 2329 2330 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2331 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2332 2333 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2334 len_to_copy); 2335 } 2336 } 2337 2338 /** 2339 * ufshcd_copy_query_response() - Copy the Query Response and the data 2340 * descriptor 2341 * @hba: per adapter instance 2342 * @lrbp: pointer to local reference block 2343 * 2344 * Return: 0 upon success; < 0 upon failure. 2345 */ 2346 static 2347 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2348 { 2349 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2350 2351 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2352 2353 /* Get the descriptor */ 2354 if (hba->dev_cmd.query.descriptor && 2355 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2356 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2357 GENERAL_UPIU_REQUEST_SIZE; 2358 u16 resp_len; 2359 u16 buf_len; 2360 2361 /* data segment length */ 2362 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2363 .data_segment_length); 2364 buf_len = be16_to_cpu( 2365 hba->dev_cmd.query.request.upiu_req.length); 2366 if (likely(buf_len >= resp_len)) { 2367 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2368 } else { 2369 dev_warn(hba->dev, 2370 "%s: rsp size %d is bigger than buffer size %d", 2371 __func__, resp_len, buf_len); 2372 return -EINVAL; 2373 } 2374 } 2375 2376 return 0; 2377 } 2378 2379 /** 2380 * ufshcd_hba_capabilities - Read controller capabilities 2381 * @hba: per adapter instance 2382 * 2383 * Return: 0 on success, negative on error. 2384 */ 2385 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2386 { 2387 int err; 2388 2389 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2390 2391 /* nutrs and nutmrs are 0 based values */ 2392 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS_SDB) + 1; 2393 hba->nutmrs = 2394 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2395 hba->reserved_slot = hba->nutrs - 1; 2396 2397 hba->nortt = FIELD_GET(MASK_NUMBER_OUTSTANDING_RTT, hba->capabilities) + 1; 2398 2399 /* Read crypto capabilities */ 2400 err = ufshcd_hba_init_crypto_capabilities(hba); 2401 if (err) { 2402 dev_err(hba->dev, "crypto setup failed\n"); 2403 return err; 2404 } 2405 2406 /* 2407 * The UFSHCI 3.0 specification does not define MCQ_SUPPORT and 2408 * LSDB_SUPPORT, but [31:29] as reserved bits with reset value 0s, which 2409 * means we can simply read values regardless of version. 2410 */ 2411 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2412 /* 2413 * 0h: legacy single doorbell support is available 2414 * 1h: indicate that legacy single doorbell support has been removed 2415 */ 2416 if (!(hba->quirks & UFSHCD_QUIRK_BROKEN_LSDBS_CAP)) 2417 hba->lsdb_sup = !FIELD_GET(MASK_LSDB_SUPPORT, hba->capabilities); 2418 else 2419 hba->lsdb_sup = true; 2420 2421 if (!hba->mcq_sup) 2422 return 0; 2423 2424 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2425 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2426 hba->mcq_capabilities); 2427 2428 return 0; 2429 } 2430 2431 /** 2432 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2433 * to accept UIC commands 2434 * @hba: per adapter instance 2435 * 2436 * Return: true on success, else false. 2437 */ 2438 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2439 { 2440 u32 val; 2441 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2442 500, uic_cmd_timeout * 1000, false, hba, 2443 REG_CONTROLLER_STATUS); 2444 return ret == 0; 2445 } 2446 2447 /** 2448 * ufshcd_get_upmcrs - Get the power mode change request status 2449 * @hba: Pointer to adapter instance 2450 * 2451 * This function gets the UPMCRS field of HCS register 2452 * 2453 * Return: value of UPMCRS field. 2454 */ 2455 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2456 { 2457 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2458 } 2459 2460 /** 2461 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2462 * @hba: per adapter instance 2463 * @uic_cmd: UIC command 2464 */ 2465 static inline void 2466 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2467 { 2468 lockdep_assert_held(&hba->uic_cmd_mutex); 2469 2470 WARN_ON(hba->active_uic_cmd); 2471 2472 hba->active_uic_cmd = uic_cmd; 2473 2474 /* Write Args */ 2475 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2476 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2477 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2478 2479 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2480 2481 /* Write UIC Cmd */ 2482 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2483 REG_UIC_COMMAND); 2484 } 2485 2486 /** 2487 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2488 * @hba: per adapter instance 2489 * @uic_cmd: UIC command 2490 * 2491 * Return: 0 only if success. 2492 */ 2493 static int 2494 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2495 { 2496 int ret; 2497 unsigned long flags; 2498 2499 lockdep_assert_held(&hba->uic_cmd_mutex); 2500 2501 if (wait_for_completion_timeout(&uic_cmd->done, 2502 msecs_to_jiffies(uic_cmd_timeout))) { 2503 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2504 } else { 2505 ret = -ETIMEDOUT; 2506 dev_err(hba->dev, 2507 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2508 uic_cmd->command, uic_cmd->argument3); 2509 2510 if (!uic_cmd->cmd_active) { 2511 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2512 __func__); 2513 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2514 } 2515 } 2516 2517 spin_lock_irqsave(hba->host->host_lock, flags); 2518 hba->active_uic_cmd = NULL; 2519 spin_unlock_irqrestore(hba->host->host_lock, flags); 2520 2521 return ret; 2522 } 2523 2524 /** 2525 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2526 * @hba: per adapter instance 2527 * @uic_cmd: UIC command 2528 * 2529 * Return: 0 only if success. 2530 */ 2531 static int 2532 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2533 { 2534 lockdep_assert_held(&hba->uic_cmd_mutex); 2535 2536 if (!ufshcd_ready_for_uic_cmd(hba)) { 2537 dev_err(hba->dev, 2538 "Controller not ready to accept UIC commands\n"); 2539 return -EIO; 2540 } 2541 2542 init_completion(&uic_cmd->done); 2543 2544 uic_cmd->cmd_active = 1; 2545 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2546 2547 return 0; 2548 } 2549 2550 /** 2551 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2552 * @hba: per adapter instance 2553 * @uic_cmd: UIC command 2554 * 2555 * Return: 0 only if success. 2556 */ 2557 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2558 { 2559 int ret; 2560 2561 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2562 return 0; 2563 2564 ufshcd_hold(hba); 2565 mutex_lock(&hba->uic_cmd_mutex); 2566 ufshcd_add_delay_before_dme_cmd(hba); 2567 2568 ret = __ufshcd_send_uic_cmd(hba, uic_cmd); 2569 if (!ret) 2570 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2571 2572 mutex_unlock(&hba->uic_cmd_mutex); 2573 2574 ufshcd_release(hba); 2575 return ret; 2576 } 2577 2578 /** 2579 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2580 * @hba: per-adapter instance 2581 * @lrbp: pointer to local reference block 2582 * @sg_entries: The number of sg lists actually used 2583 * @sg_list: Pointer to SG list 2584 */ 2585 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2586 struct scatterlist *sg_list) 2587 { 2588 struct ufshcd_sg_entry *prd; 2589 struct scatterlist *sg; 2590 int i; 2591 2592 if (sg_entries) { 2593 2594 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2595 lrbp->utr_descriptor_ptr->prd_table_length = 2596 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2597 else 2598 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2599 2600 prd = lrbp->ucd_prdt_ptr; 2601 2602 for_each_sg(sg_list, sg, sg_entries, i) { 2603 const unsigned int len = sg_dma_len(sg); 2604 2605 /* 2606 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2607 * based value that indicates the length, in bytes, of 2608 * the data block. A maximum of length of 256KB may 2609 * exist for any entry. Bits 1:0 of this field shall be 2610 * 11b to indicate Dword granularity. A value of '3' 2611 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2612 */ 2613 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2614 prd->size = cpu_to_le32(len - 1); 2615 prd->addr = cpu_to_le64(sg->dma_address); 2616 prd->reserved = 0; 2617 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2618 } 2619 } else { 2620 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2621 } 2622 } 2623 2624 /** 2625 * ufshcd_map_sg - Map scatter-gather list to prdt 2626 * @hba: per adapter instance 2627 * @lrbp: pointer to local reference block 2628 * 2629 * Return: 0 in case of success, non-zero value in case of failure. 2630 */ 2631 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2632 { 2633 struct scsi_cmnd *cmd = lrbp->cmd; 2634 int sg_segments = scsi_dma_map(cmd); 2635 2636 if (sg_segments < 0) 2637 return sg_segments; 2638 2639 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2640 2641 return ufshcd_crypto_fill_prdt(hba, lrbp); 2642 } 2643 2644 /** 2645 * ufshcd_enable_intr - enable interrupts 2646 * @hba: per adapter instance 2647 * @intrs: interrupt bits 2648 */ 2649 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2650 { 2651 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2652 2653 set |= intrs; 2654 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2655 } 2656 2657 /** 2658 * ufshcd_disable_intr - disable interrupts 2659 * @hba: per adapter instance 2660 * @intrs: interrupt bits 2661 */ 2662 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2663 { 2664 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2665 2666 set &= ~intrs; 2667 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2668 } 2669 2670 /** 2671 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2672 * descriptor according to request 2673 * @hba: per adapter instance 2674 * @lrbp: pointer to local reference block 2675 * @upiu_flags: flags required in the header 2676 * @cmd_dir: requests data direction 2677 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2678 */ 2679 static void 2680 ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 2681 u8 *upiu_flags, enum dma_data_direction cmd_dir, 2682 int ehs_length) 2683 { 2684 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2685 struct request_desc_header *h = &req_desc->header; 2686 enum utp_data_direction data_direction; 2687 2688 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2689 2690 *h = (typeof(*h)){ }; 2691 2692 if (cmd_dir == DMA_FROM_DEVICE) { 2693 data_direction = UTP_DEVICE_TO_HOST; 2694 *upiu_flags = UPIU_CMD_FLAGS_READ; 2695 } else if (cmd_dir == DMA_TO_DEVICE) { 2696 data_direction = UTP_HOST_TO_DEVICE; 2697 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2698 } else { 2699 data_direction = UTP_NO_DATA_TRANSFER; 2700 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2701 } 2702 2703 h->command_type = lrbp->command_type; 2704 h->data_direction = data_direction; 2705 h->ehs_length = ehs_length; 2706 2707 if (lrbp->intr_cmd) 2708 h->interrupt = 1; 2709 2710 /* Prepare crypto related dwords */ 2711 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2712 2713 /* 2714 * assigning invalid value for command status. Controller 2715 * updates OCS on command completion, with the command 2716 * status 2717 */ 2718 h->ocs = OCS_INVALID_COMMAND_STATUS; 2719 2720 req_desc->prd_table_length = 0; 2721 } 2722 2723 /** 2724 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2725 * for scsi commands 2726 * @lrbp: local reference block pointer 2727 * @upiu_flags: flags 2728 */ 2729 static 2730 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2731 { 2732 struct scsi_cmnd *cmd = lrbp->cmd; 2733 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2734 unsigned short cdb_len; 2735 2736 ucd_req_ptr->header = (struct utp_upiu_header){ 2737 .transaction_code = UPIU_TRANSACTION_COMMAND, 2738 .flags = upiu_flags, 2739 .lun = lrbp->lun, 2740 .task_tag = lrbp->task_tag, 2741 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2742 }; 2743 2744 WARN_ON_ONCE(ucd_req_ptr->header.task_tag != lrbp->task_tag); 2745 2746 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2747 2748 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2749 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2750 2751 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2752 } 2753 2754 /** 2755 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2756 * @hba: UFS hba 2757 * @lrbp: local reference block pointer 2758 * @upiu_flags: flags 2759 */ 2760 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2761 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2762 { 2763 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2764 struct ufs_query *query = &hba->dev_cmd.query; 2765 u16 len = be16_to_cpu(query->request.upiu_req.length); 2766 2767 /* Query request header */ 2768 ucd_req_ptr->header = (struct utp_upiu_header){ 2769 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2770 .flags = upiu_flags, 2771 .lun = lrbp->lun, 2772 .task_tag = lrbp->task_tag, 2773 .query_function = query->request.query_func, 2774 /* Data segment length only need for WRITE_DESC */ 2775 .data_segment_length = 2776 query->request.upiu_req.opcode == 2777 UPIU_QUERY_OPCODE_WRITE_DESC ? 2778 cpu_to_be16(len) : 2779 0, 2780 }; 2781 2782 /* Copy the Query Request buffer as is */ 2783 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2784 QUERY_OSF_SIZE); 2785 2786 /* Copy the Descriptor */ 2787 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2788 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2789 2790 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2791 } 2792 2793 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2794 { 2795 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2796 2797 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2798 2799 ucd_req_ptr->header = (struct utp_upiu_header){ 2800 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2801 .task_tag = lrbp->task_tag, 2802 }; 2803 2804 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2805 } 2806 2807 /** 2808 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2809 * for Device Management Purposes 2810 * @hba: per adapter instance 2811 * @lrbp: pointer to local reference block 2812 * 2813 * Return: 0 upon success; < 0 upon failure. 2814 */ 2815 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2816 struct ufshcd_lrb *lrbp) 2817 { 2818 u8 upiu_flags; 2819 int ret = 0; 2820 2821 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 2822 2823 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2824 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2825 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2826 ufshcd_prepare_utp_nop_upiu(lrbp); 2827 else 2828 ret = -EINVAL; 2829 2830 return ret; 2831 } 2832 2833 /** 2834 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2835 * for SCSI Purposes 2836 * @hba: per adapter instance 2837 * @lrbp: pointer to local reference block 2838 */ 2839 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2840 { 2841 struct request *rq = scsi_cmd_to_rq(lrbp->cmd); 2842 unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq)); 2843 u8 upiu_flags; 2844 2845 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0); 2846 if (ioprio_class == IOPRIO_CLASS_RT) 2847 upiu_flags |= UPIU_CMD_FLAGS_CP; 2848 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2849 } 2850 2851 static void __ufshcd_setup_cmd(struct ufshcd_lrb *lrbp, struct scsi_cmnd *cmd, u8 lun, int tag) 2852 { 2853 memset(lrbp->ucd_req_ptr, 0, sizeof(*lrbp->ucd_req_ptr)); 2854 2855 lrbp->cmd = cmd; 2856 lrbp->task_tag = tag; 2857 lrbp->lun = lun; 2858 ufshcd_prepare_lrbp_crypto(cmd ? scsi_cmd_to_rq(cmd) : NULL, lrbp); 2859 } 2860 2861 static void ufshcd_setup_scsi_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 2862 struct scsi_cmnd *cmd, u8 lun, int tag) 2863 { 2864 __ufshcd_setup_cmd(lrbp, cmd, lun, tag); 2865 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 2866 lrbp->req_abort_skip = false; 2867 2868 ufshcd_comp_scsi_upiu(hba, lrbp); 2869 } 2870 2871 /** 2872 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2873 * @upiu_wlun_id: UPIU W-LUN id 2874 * 2875 * Return: SCSI W-LUN id. 2876 */ 2877 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2878 { 2879 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2880 } 2881 2882 static inline bool is_device_wlun(struct scsi_device *sdev) 2883 { 2884 return sdev->lun == 2885 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2886 } 2887 2888 /* 2889 * Associate the UFS controller queue with the default and poll HCTX types. 2890 * Initialize the mq_map[] arrays. 2891 */ 2892 static void ufshcd_map_queues(struct Scsi_Host *shost) 2893 { 2894 struct ufs_hba *hba = shost_priv(shost); 2895 int i, queue_offset = 0; 2896 2897 if (!is_mcq_supported(hba)) { 2898 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2899 hba->nr_queues[HCTX_TYPE_READ] = 0; 2900 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2901 hba->nr_hw_queues = 1; 2902 } 2903 2904 for (i = 0; i < shost->nr_maps; i++) { 2905 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2906 2907 map->nr_queues = hba->nr_queues[i]; 2908 if (!map->nr_queues) 2909 continue; 2910 map->queue_offset = queue_offset; 2911 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2912 map->queue_offset = 0; 2913 2914 blk_mq_map_queues(map); 2915 queue_offset += map->nr_queues; 2916 } 2917 } 2918 2919 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2920 { 2921 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2922 i * ufshcd_get_ucd_size(hba); 2923 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2924 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2925 i * ufshcd_get_ucd_size(hba); 2926 u16 response_offset = offsetof(struct utp_transfer_cmd_desc, 2927 response_upiu); 2928 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 2929 2930 lrb->utr_descriptor_ptr = utrdlp + i; 2931 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2932 i * sizeof(struct utp_transfer_req_desc); 2933 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2934 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2935 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2936 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2937 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2938 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2939 } 2940 2941 /** 2942 * ufshcd_queuecommand - main entry point for SCSI requests 2943 * @host: SCSI host pointer 2944 * @cmd: command from SCSI Midlayer 2945 * 2946 * Return: 0 for success, non-zero in case of failure. 2947 */ 2948 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2949 { 2950 struct ufs_hba *hba = shost_priv(host); 2951 int tag = scsi_cmd_to_rq(cmd)->tag; 2952 struct ufshcd_lrb *lrbp; 2953 int err = 0; 2954 struct ufs_hw_queue *hwq = NULL; 2955 2956 switch (hba->ufshcd_state) { 2957 case UFSHCD_STATE_OPERATIONAL: 2958 break; 2959 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2960 /* 2961 * SCSI error handler can call ->queuecommand() while UFS error 2962 * handler is in progress. Error interrupts could change the 2963 * state from UFSHCD_STATE_RESET to 2964 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2965 * being issued in that case. 2966 */ 2967 if (ufshcd_eh_in_progress(hba)) { 2968 err = SCSI_MLQUEUE_HOST_BUSY; 2969 goto out; 2970 } 2971 break; 2972 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2973 /* 2974 * pm_runtime_get_sync() is used at error handling preparation 2975 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2976 * PM ops, it can never be finished if we let SCSI layer keep 2977 * retrying it, which gets err handler stuck forever. Neither 2978 * can we let the scsi cmd pass through, because UFS is in bad 2979 * state, the scsi cmd may eventually time out, which will get 2980 * err handler blocked for too long. So, just fail the scsi cmd 2981 * sent from PM ops, err handler can recover PM error anyways. 2982 */ 2983 if (hba->pm_op_in_progress) { 2984 hba->force_reset = true; 2985 set_host_byte(cmd, DID_BAD_TARGET); 2986 scsi_done(cmd); 2987 goto out; 2988 } 2989 fallthrough; 2990 case UFSHCD_STATE_RESET: 2991 err = SCSI_MLQUEUE_HOST_BUSY; 2992 goto out; 2993 case UFSHCD_STATE_ERROR: 2994 set_host_byte(cmd, DID_ERROR); 2995 scsi_done(cmd); 2996 goto out; 2997 } 2998 2999 hba->req_abort_count = 0; 3000 3001 ufshcd_hold(hba); 3002 3003 lrbp = &hba->lrb[tag]; 3004 3005 ufshcd_setup_scsi_cmd(hba, lrbp, cmd, ufshcd_scsi_to_upiu_lun(cmd->device->lun), tag); 3006 3007 err = ufshcd_map_sg(hba, lrbp); 3008 if (err) { 3009 ufshcd_release(hba); 3010 goto out; 3011 } 3012 3013 if (hba->mcq_enabled) 3014 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 3015 3016 ufshcd_send_command(hba, tag, hwq); 3017 3018 out: 3019 if (ufs_trigger_eh(hba)) { 3020 unsigned long flags; 3021 3022 spin_lock_irqsave(hba->host->host_lock, flags); 3023 ufshcd_schedule_eh_work(hba); 3024 spin_unlock_irqrestore(hba->host->host_lock, flags); 3025 } 3026 3027 return err; 3028 } 3029 3030 static void ufshcd_setup_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3031 enum dev_cmd_type cmd_type, u8 lun, int tag) 3032 { 3033 __ufshcd_setup_cmd(lrbp, NULL, lun, tag); 3034 lrbp->intr_cmd = true; /* No interrupt aggregation */ 3035 hba->dev_cmd.type = cmd_type; 3036 } 3037 3038 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 3039 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 3040 { 3041 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 3042 3043 return ufshcd_compose_devman_upiu(hba, lrbp); 3044 } 3045 3046 /* 3047 * Check with the block layer if the command is inflight 3048 * @cmd: command to check. 3049 * 3050 * Return: true if command is inflight; false if not. 3051 */ 3052 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 3053 { 3054 return cmd && blk_mq_rq_state(scsi_cmd_to_rq(cmd)) == MQ_RQ_IN_FLIGHT; 3055 } 3056 3057 /* 3058 * Clear the pending command in the controller and wait until 3059 * the controller confirms that the command has been cleared. 3060 * @hba: per adapter instance 3061 * @task_tag: The tag number of the command to be cleared. 3062 */ 3063 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 3064 { 3065 u32 mask; 3066 int err; 3067 3068 if (hba->mcq_enabled) { 3069 /* 3070 * MCQ mode. Clean up the MCQ resources similar to 3071 * what the ufshcd_utrl_clear() does for SDB mode. 3072 */ 3073 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 3074 if (err) { 3075 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 3076 __func__, task_tag, err); 3077 return err; 3078 } 3079 return 0; 3080 } 3081 3082 mask = 1U << task_tag; 3083 3084 /* clear outstanding transaction before retry */ 3085 ufshcd_utrl_clear(hba, mask); 3086 3087 /* 3088 * wait for h/w to clear corresponding bit in door-bell. 3089 * max. wait is 1 sec. 3090 */ 3091 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 3092 mask, ~mask, 1000, 1000); 3093 } 3094 3095 /** 3096 * ufshcd_dev_cmd_completion() - handles device management command responses 3097 * @hba: per adapter instance 3098 * @lrbp: pointer to local reference block 3099 * 3100 * Return: 0 upon success; < 0 upon failure. 3101 */ 3102 static int 3103 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 3104 { 3105 enum upiu_response_transaction resp; 3106 int err = 0; 3107 3108 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 3109 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3110 3111 switch (resp) { 3112 case UPIU_TRANSACTION_NOP_IN: 3113 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3114 err = -EINVAL; 3115 dev_err(hba->dev, "%s: unexpected response %x\n", 3116 __func__, resp); 3117 } 3118 break; 3119 case UPIU_TRANSACTION_QUERY_RSP: { 3120 u8 response = lrbp->ucd_rsp_ptr->header.response; 3121 3122 if (response == 0) 3123 err = ufshcd_copy_query_response(hba, lrbp); 3124 break; 3125 } 3126 case UPIU_TRANSACTION_REJECT_UPIU: 3127 /* TODO: handle Reject UPIU Response */ 3128 err = -EPERM; 3129 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3130 __func__); 3131 break; 3132 case UPIU_TRANSACTION_RESPONSE: 3133 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3134 err = -EINVAL; 3135 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3136 } 3137 break; 3138 default: 3139 err = -EINVAL; 3140 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3141 __func__, resp); 3142 break; 3143 } 3144 3145 return err; 3146 } 3147 3148 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3149 struct ufshcd_lrb *lrbp, int max_timeout) 3150 { 3151 unsigned long time_left = msecs_to_jiffies(max_timeout); 3152 unsigned long flags; 3153 bool pending; 3154 int err; 3155 3156 retry: 3157 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3158 time_left); 3159 3160 if (likely(time_left)) { 3161 /* 3162 * The completion handler called complete() and the caller of 3163 * this function still owns the @lrbp tag so the code below does 3164 * not trigger any race conditions. 3165 */ 3166 hba->dev_cmd.complete = NULL; 3167 err = ufshcd_get_tr_ocs(lrbp, NULL); 3168 if (!err) 3169 err = ufshcd_dev_cmd_completion(hba, lrbp); 3170 } else { 3171 err = -ETIMEDOUT; 3172 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3173 __func__, lrbp->task_tag); 3174 3175 /* MCQ mode */ 3176 if (hba->mcq_enabled) { 3177 /* successfully cleared the command, retry if needed */ 3178 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) 3179 err = -EAGAIN; 3180 hba->dev_cmd.complete = NULL; 3181 return err; 3182 } 3183 3184 /* SDB mode */ 3185 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3186 /* successfully cleared the command, retry if needed */ 3187 err = -EAGAIN; 3188 /* 3189 * Since clearing the command succeeded we also need to 3190 * clear the task tag bit from the outstanding_reqs 3191 * variable. 3192 */ 3193 spin_lock_irqsave(&hba->outstanding_lock, flags); 3194 pending = test_bit(lrbp->task_tag, 3195 &hba->outstanding_reqs); 3196 if (pending) { 3197 hba->dev_cmd.complete = NULL; 3198 __clear_bit(lrbp->task_tag, 3199 &hba->outstanding_reqs); 3200 } 3201 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3202 3203 if (!pending) { 3204 /* 3205 * The completion handler ran while we tried to 3206 * clear the command. 3207 */ 3208 time_left = 1; 3209 goto retry; 3210 } 3211 } else { 3212 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3213 __func__, lrbp->task_tag); 3214 3215 spin_lock_irqsave(&hba->outstanding_lock, flags); 3216 pending = test_bit(lrbp->task_tag, 3217 &hba->outstanding_reqs); 3218 if (pending) 3219 hba->dev_cmd.complete = NULL; 3220 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3221 3222 if (!pending) { 3223 /* 3224 * The completion handler ran while we tried to 3225 * clear the command. 3226 */ 3227 time_left = 1; 3228 goto retry; 3229 } 3230 } 3231 } 3232 3233 return err; 3234 } 3235 3236 static void ufshcd_dev_man_lock(struct ufs_hba *hba) 3237 { 3238 ufshcd_hold(hba); 3239 mutex_lock(&hba->dev_cmd.lock); 3240 down_read(&hba->clk_scaling_lock); 3241 } 3242 3243 static void ufshcd_dev_man_unlock(struct ufs_hba *hba) 3244 { 3245 up_read(&hba->clk_scaling_lock); 3246 mutex_unlock(&hba->dev_cmd.lock); 3247 ufshcd_release(hba); 3248 } 3249 3250 static int ufshcd_issue_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3251 const u32 tag, int timeout) 3252 { 3253 DECLARE_COMPLETION_ONSTACK(wait); 3254 int err; 3255 3256 hba->dev_cmd.complete = &wait; 3257 3258 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3259 3260 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3261 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3262 3263 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3264 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3265 3266 return err; 3267 } 3268 3269 /** 3270 * ufshcd_exec_dev_cmd - API for sending device management requests 3271 * @hba: UFS hba 3272 * @cmd_type: specifies the type (NOP, Query...) 3273 * @timeout: timeout in milliseconds 3274 * 3275 * Return: 0 upon success; < 0 upon failure. 3276 * 3277 * NOTE: Since there is only one available tag for device management commands, 3278 * it is expected you hold the hba->dev_cmd.lock mutex. 3279 */ 3280 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3281 enum dev_cmd_type cmd_type, int timeout) 3282 { 3283 const u32 tag = hba->reserved_slot; 3284 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 3285 int err; 3286 3287 /* Protects use of hba->reserved_slot. */ 3288 lockdep_assert_held(&hba->dev_cmd.lock); 3289 3290 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3291 if (unlikely(err)) 3292 return err; 3293 3294 return ufshcd_issue_dev_cmd(hba, lrbp, tag, timeout); 3295 } 3296 3297 /** 3298 * ufshcd_init_query() - init the query response and request parameters 3299 * @hba: per-adapter instance 3300 * @request: address of the request pointer to be initialized 3301 * @response: address of the response pointer to be initialized 3302 * @opcode: operation to perform 3303 * @idn: flag idn to access 3304 * @index: LU number to access 3305 * @selector: query/flag/descriptor further identification 3306 */ 3307 static inline void ufshcd_init_query(struct ufs_hba *hba, 3308 struct ufs_query_req **request, struct ufs_query_res **response, 3309 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3310 { 3311 *request = &hba->dev_cmd.query.request; 3312 *response = &hba->dev_cmd.query.response; 3313 memset(*request, 0, sizeof(struct ufs_query_req)); 3314 memset(*response, 0, sizeof(struct ufs_query_res)); 3315 (*request)->upiu_req.opcode = opcode; 3316 (*request)->upiu_req.idn = idn; 3317 (*request)->upiu_req.index = index; 3318 (*request)->upiu_req.selector = selector; 3319 } 3320 3321 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3322 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3323 { 3324 int ret; 3325 int retries; 3326 3327 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3328 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3329 if (ret) 3330 dev_dbg(hba->dev, 3331 "%s: failed with error %d, retries %d\n", 3332 __func__, ret, retries); 3333 else 3334 break; 3335 } 3336 3337 if (ret) 3338 dev_err(hba->dev, 3339 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3340 __func__, opcode, idn, ret, retries); 3341 return ret; 3342 } 3343 3344 /** 3345 * ufshcd_query_flag() - API function for sending flag query requests 3346 * @hba: per-adapter instance 3347 * @opcode: flag query to perform 3348 * @idn: flag idn to access 3349 * @index: flag index to access 3350 * @flag_res: the flag value after the query request completes 3351 * 3352 * Return: 0 for success, non-zero in case of failure. 3353 */ 3354 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3355 enum flag_idn idn, u8 index, bool *flag_res) 3356 { 3357 struct ufs_query_req *request = NULL; 3358 struct ufs_query_res *response = NULL; 3359 int err, selector = 0; 3360 int timeout = QUERY_REQ_TIMEOUT; 3361 3362 BUG_ON(!hba); 3363 3364 ufshcd_dev_man_lock(hba); 3365 3366 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3367 selector); 3368 3369 switch (opcode) { 3370 case UPIU_QUERY_OPCODE_SET_FLAG: 3371 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3372 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3373 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3374 break; 3375 case UPIU_QUERY_OPCODE_READ_FLAG: 3376 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3377 if (!flag_res) { 3378 /* No dummy reads */ 3379 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3380 __func__); 3381 err = -EINVAL; 3382 goto out_unlock; 3383 } 3384 break; 3385 default: 3386 dev_err(hba->dev, 3387 "%s: Expected query flag opcode but got = %d\n", 3388 __func__, opcode); 3389 err = -EINVAL; 3390 goto out_unlock; 3391 } 3392 3393 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3394 3395 if (err) { 3396 dev_err(hba->dev, 3397 "%s: Sending flag query for idn %d failed, err = %d\n", 3398 __func__, idn, err); 3399 goto out_unlock; 3400 } 3401 3402 if (flag_res) 3403 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3404 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3405 3406 out_unlock: 3407 ufshcd_dev_man_unlock(hba); 3408 return err; 3409 } 3410 3411 /** 3412 * ufshcd_query_attr - API function for sending attribute requests 3413 * @hba: per-adapter instance 3414 * @opcode: attribute opcode 3415 * @idn: attribute idn to access 3416 * @index: index field 3417 * @selector: selector field 3418 * @attr_val: the attribute value after the query request completes 3419 * 3420 * Return: 0 for success, non-zero in case of failure. 3421 */ 3422 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3423 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3424 { 3425 struct ufs_query_req *request = NULL; 3426 struct ufs_query_res *response = NULL; 3427 int err; 3428 3429 BUG_ON(!hba); 3430 3431 if (!attr_val) { 3432 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3433 __func__, opcode); 3434 return -EINVAL; 3435 } 3436 3437 ufshcd_dev_man_lock(hba); 3438 3439 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3440 selector); 3441 3442 switch (opcode) { 3443 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3444 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3445 request->upiu_req.value = cpu_to_be32(*attr_val); 3446 break; 3447 case UPIU_QUERY_OPCODE_READ_ATTR: 3448 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3449 break; 3450 default: 3451 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3452 __func__, opcode); 3453 err = -EINVAL; 3454 goto out_unlock; 3455 } 3456 3457 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3458 3459 if (err) { 3460 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3461 __func__, opcode, idn, index, err); 3462 goto out_unlock; 3463 } 3464 3465 *attr_val = be32_to_cpu(response->upiu_res.value); 3466 3467 out_unlock: 3468 ufshcd_dev_man_unlock(hba); 3469 return err; 3470 } 3471 3472 /** 3473 * ufshcd_query_attr_retry() - API function for sending query 3474 * attribute with retries 3475 * @hba: per-adapter instance 3476 * @opcode: attribute opcode 3477 * @idn: attribute idn to access 3478 * @index: index field 3479 * @selector: selector field 3480 * @attr_val: the attribute value after the query request 3481 * completes 3482 * 3483 * Return: 0 for success, non-zero in case of failure. 3484 */ 3485 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3486 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3487 u32 *attr_val) 3488 { 3489 int ret = 0; 3490 u32 retries; 3491 3492 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3493 ret = ufshcd_query_attr(hba, opcode, idn, index, 3494 selector, attr_val); 3495 if (ret) 3496 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3497 __func__, ret, retries); 3498 else 3499 break; 3500 } 3501 3502 if (ret) 3503 dev_err(hba->dev, 3504 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3505 __func__, idn, ret, QUERY_REQ_RETRIES); 3506 return ret; 3507 } 3508 3509 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3510 enum query_opcode opcode, enum desc_idn idn, u8 index, 3511 u8 selector, u8 *desc_buf, int *buf_len) 3512 { 3513 struct ufs_query_req *request = NULL; 3514 struct ufs_query_res *response = NULL; 3515 int err; 3516 3517 BUG_ON(!hba); 3518 3519 if (!desc_buf) { 3520 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3521 __func__, opcode); 3522 return -EINVAL; 3523 } 3524 3525 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3526 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3527 __func__, *buf_len); 3528 return -EINVAL; 3529 } 3530 3531 ufshcd_dev_man_lock(hba); 3532 3533 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3534 selector); 3535 hba->dev_cmd.query.descriptor = desc_buf; 3536 request->upiu_req.length = cpu_to_be16(*buf_len); 3537 3538 switch (opcode) { 3539 case UPIU_QUERY_OPCODE_WRITE_DESC: 3540 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3541 break; 3542 case UPIU_QUERY_OPCODE_READ_DESC: 3543 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3544 break; 3545 default: 3546 dev_err(hba->dev, 3547 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3548 __func__, opcode); 3549 err = -EINVAL; 3550 goto out_unlock; 3551 } 3552 3553 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3554 3555 if (err) { 3556 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3557 __func__, opcode, idn, index, err); 3558 goto out_unlock; 3559 } 3560 3561 *buf_len = be16_to_cpu(response->upiu_res.length); 3562 3563 out_unlock: 3564 hba->dev_cmd.query.descriptor = NULL; 3565 ufshcd_dev_man_unlock(hba); 3566 return err; 3567 } 3568 3569 /** 3570 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3571 * @hba: per-adapter instance 3572 * @opcode: attribute opcode 3573 * @idn: attribute idn to access 3574 * @index: index field 3575 * @selector: selector field 3576 * @desc_buf: the buffer that contains the descriptor 3577 * @buf_len: length parameter passed to the device 3578 * 3579 * The buf_len parameter will contain, on return, the length parameter 3580 * received on the response. 3581 * 3582 * Return: 0 for success, non-zero in case of failure. 3583 */ 3584 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3585 enum query_opcode opcode, 3586 enum desc_idn idn, u8 index, 3587 u8 selector, 3588 u8 *desc_buf, int *buf_len) 3589 { 3590 int err; 3591 int retries; 3592 3593 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3594 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3595 selector, desc_buf, buf_len); 3596 if (!err || err == -EINVAL) 3597 break; 3598 } 3599 3600 return err; 3601 } 3602 3603 /** 3604 * ufshcd_read_desc_param - read the specified descriptor parameter 3605 * @hba: Pointer to adapter instance 3606 * @desc_id: descriptor idn value 3607 * @desc_index: descriptor index 3608 * @param_offset: offset of the parameter to read 3609 * @param_read_buf: pointer to buffer where parameter would be read 3610 * @param_size: sizeof(param_read_buf) 3611 * 3612 * Return: 0 in case of success, non-zero otherwise. 3613 */ 3614 int ufshcd_read_desc_param(struct ufs_hba *hba, 3615 enum desc_idn desc_id, 3616 int desc_index, 3617 u8 param_offset, 3618 u8 *param_read_buf, 3619 u8 param_size) 3620 { 3621 int ret; 3622 u8 *desc_buf; 3623 int buff_len = QUERY_DESC_MAX_SIZE; 3624 bool is_kmalloc = true; 3625 3626 /* Safety check */ 3627 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3628 return -EINVAL; 3629 3630 /* Check whether we need temp memory */ 3631 if (param_offset != 0 || param_size < buff_len) { 3632 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3633 if (!desc_buf) 3634 return -ENOMEM; 3635 } else { 3636 desc_buf = param_read_buf; 3637 is_kmalloc = false; 3638 } 3639 3640 /* Request for full descriptor */ 3641 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3642 desc_id, desc_index, 0, 3643 desc_buf, &buff_len); 3644 if (ret) { 3645 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3646 __func__, desc_id, desc_index, param_offset, ret); 3647 goto out; 3648 } 3649 3650 /* Update descriptor length */ 3651 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3652 3653 if (param_offset >= buff_len) { 3654 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3655 __func__, param_offset, desc_id, buff_len); 3656 ret = -EINVAL; 3657 goto out; 3658 } 3659 3660 /* Sanity check */ 3661 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3662 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3663 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3664 ret = -EINVAL; 3665 goto out; 3666 } 3667 3668 if (is_kmalloc) { 3669 /* Make sure we don't copy more data than available */ 3670 if (param_offset >= buff_len) 3671 ret = -EINVAL; 3672 else 3673 memcpy(param_read_buf, &desc_buf[param_offset], 3674 min_t(u32, param_size, buff_len - param_offset)); 3675 } 3676 out: 3677 if (is_kmalloc) 3678 kfree(desc_buf); 3679 return ret; 3680 } 3681 3682 /** 3683 * struct uc_string_id - unicode string 3684 * 3685 * @len: size of this descriptor inclusive 3686 * @type: descriptor type 3687 * @uc: unicode string character 3688 */ 3689 struct uc_string_id { 3690 u8 len; 3691 u8 type; 3692 wchar_t uc[]; 3693 } __packed; 3694 3695 /* replace non-printable or non-ASCII characters with spaces */ 3696 static inline char ufshcd_remove_non_printable(u8 ch) 3697 { 3698 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3699 } 3700 3701 /** 3702 * ufshcd_read_string_desc - read string descriptor 3703 * @hba: pointer to adapter instance 3704 * @desc_index: descriptor index 3705 * @buf: pointer to buffer where descriptor would be read, 3706 * the caller should free the memory. 3707 * @ascii: if true convert from unicode to ascii characters 3708 * null terminated string. 3709 * 3710 * Return: 3711 * * string size on success. 3712 * * -ENOMEM: on allocation failure 3713 * * -EINVAL: on a wrong parameter 3714 */ 3715 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3716 u8 **buf, bool ascii) 3717 { 3718 struct uc_string_id *uc_str; 3719 u8 *str; 3720 int ret; 3721 3722 if (!buf) 3723 return -EINVAL; 3724 3725 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3726 if (!uc_str) 3727 return -ENOMEM; 3728 3729 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3730 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3731 if (ret < 0) { 3732 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3733 QUERY_REQ_RETRIES, ret); 3734 str = NULL; 3735 goto out; 3736 } 3737 3738 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3739 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3740 str = NULL; 3741 ret = 0; 3742 goto out; 3743 } 3744 3745 if (ascii) { 3746 ssize_t ascii_len; 3747 int i; 3748 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3749 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3750 str = kzalloc(ascii_len, GFP_KERNEL); 3751 if (!str) { 3752 ret = -ENOMEM; 3753 goto out; 3754 } 3755 3756 /* 3757 * the descriptor contains string in UTF16 format 3758 * we need to convert to utf-8 so it can be displayed 3759 */ 3760 ret = utf16s_to_utf8s(uc_str->uc, 3761 uc_str->len - QUERY_DESC_HDR_SIZE, 3762 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3763 3764 /* replace non-printable or non-ASCII characters with spaces */ 3765 for (i = 0; i < ret; i++) 3766 str[i] = ufshcd_remove_non_printable(str[i]); 3767 3768 str[ret++] = '\0'; 3769 3770 } else { 3771 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3772 if (!str) { 3773 ret = -ENOMEM; 3774 goto out; 3775 } 3776 ret = uc_str->len; 3777 } 3778 out: 3779 *buf = str; 3780 kfree(uc_str); 3781 return ret; 3782 } 3783 3784 /** 3785 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3786 * @hba: Pointer to adapter instance 3787 * @lun: lun id 3788 * @param_offset: offset of the parameter to read 3789 * @param_read_buf: pointer to buffer where parameter would be read 3790 * @param_size: sizeof(param_read_buf) 3791 * 3792 * Return: 0 in case of success, non-zero otherwise. 3793 */ 3794 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3795 int lun, 3796 enum unit_desc_param param_offset, 3797 u8 *param_read_buf, 3798 u32 param_size) 3799 { 3800 /* 3801 * Unit descriptors are only available for general purpose LUs (LUN id 3802 * from 0 to 7) and RPMB Well known LU. 3803 */ 3804 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3805 return -EOPNOTSUPP; 3806 3807 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3808 param_offset, param_read_buf, param_size); 3809 } 3810 3811 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3812 { 3813 int err = 0; 3814 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3815 3816 if (hba->dev_info.wspecversion >= 0x300) { 3817 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3818 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3819 &gating_wait); 3820 if (err) 3821 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3822 err, gating_wait); 3823 3824 if (gating_wait == 0) { 3825 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3826 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3827 gating_wait); 3828 } 3829 3830 hba->dev_info.clk_gating_wait_us = gating_wait; 3831 } 3832 3833 return err; 3834 } 3835 3836 /** 3837 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3838 * @hba: per adapter instance 3839 * 3840 * 1. Allocate DMA memory for Command Descriptor array 3841 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3842 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3843 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3844 * (UTMRDL) 3845 * 4. Allocate memory for local reference block(lrb). 3846 * 3847 * Return: 0 for success, non-zero in case of failure. 3848 */ 3849 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3850 { 3851 size_t utmrdl_size, utrdl_size, ucdl_size; 3852 3853 /* Allocate memory for UTP command descriptors */ 3854 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3855 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3856 ucdl_size, 3857 &hba->ucdl_dma_addr, 3858 GFP_KERNEL); 3859 3860 /* 3861 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3862 */ 3863 if (!hba->ucdl_base_addr || 3864 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3865 dev_err(hba->dev, 3866 "Command Descriptor Memory allocation failed\n"); 3867 goto out; 3868 } 3869 3870 /* 3871 * Allocate memory for UTP Transfer descriptors 3872 * UFSHCI requires 1KB alignment of UTRD 3873 */ 3874 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3875 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3876 utrdl_size, 3877 &hba->utrdl_dma_addr, 3878 GFP_KERNEL); 3879 if (!hba->utrdl_base_addr || 3880 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3881 dev_err(hba->dev, 3882 "Transfer Descriptor Memory allocation failed\n"); 3883 goto out; 3884 } 3885 3886 /* 3887 * Skip utmrdl allocation; it may have been 3888 * allocated during first pass and not released during 3889 * MCQ memory allocation. 3890 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3891 */ 3892 if (hba->utmrdl_base_addr) 3893 goto skip_utmrdl; 3894 /* 3895 * Allocate memory for UTP Task Management descriptors 3896 * UFSHCI requires 1KB alignment of UTMRD 3897 */ 3898 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3899 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3900 utmrdl_size, 3901 &hba->utmrdl_dma_addr, 3902 GFP_KERNEL); 3903 if (!hba->utmrdl_base_addr || 3904 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3905 dev_err(hba->dev, 3906 "Task Management Descriptor Memory allocation failed\n"); 3907 goto out; 3908 } 3909 3910 skip_utmrdl: 3911 /* Allocate memory for local reference block */ 3912 hba->lrb = devm_kcalloc(hba->dev, 3913 hba->nutrs, sizeof(struct ufshcd_lrb), 3914 GFP_KERNEL); 3915 if (!hba->lrb) { 3916 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3917 goto out; 3918 } 3919 return 0; 3920 out: 3921 return -ENOMEM; 3922 } 3923 3924 /** 3925 * ufshcd_host_memory_configure - configure local reference block with 3926 * memory offsets 3927 * @hba: per adapter instance 3928 * 3929 * Configure Host memory space 3930 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3931 * address. 3932 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3933 * and PRDT offset. 3934 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3935 * into local reference block. 3936 */ 3937 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3938 { 3939 struct utp_transfer_req_desc *utrdlp; 3940 dma_addr_t cmd_desc_dma_addr; 3941 dma_addr_t cmd_desc_element_addr; 3942 u16 response_offset; 3943 u16 prdt_offset; 3944 int cmd_desc_size; 3945 int i; 3946 3947 utrdlp = hba->utrdl_base_addr; 3948 3949 response_offset = 3950 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3951 prdt_offset = 3952 offsetof(struct utp_transfer_cmd_desc, prd_table); 3953 3954 cmd_desc_size = ufshcd_get_ucd_size(hba); 3955 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3956 3957 for (i = 0; i < hba->nutrs; i++) { 3958 /* Configure UTRD with command descriptor base address */ 3959 cmd_desc_element_addr = 3960 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3961 utrdlp[i].command_desc_base_addr = 3962 cpu_to_le64(cmd_desc_element_addr); 3963 3964 /* Response upiu and prdt offset should be in double words */ 3965 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3966 utrdlp[i].response_upiu_offset = 3967 cpu_to_le16(response_offset); 3968 utrdlp[i].prd_table_offset = 3969 cpu_to_le16(prdt_offset); 3970 utrdlp[i].response_upiu_length = 3971 cpu_to_le16(ALIGNED_UPIU_SIZE); 3972 } else { 3973 utrdlp[i].response_upiu_offset = 3974 cpu_to_le16(response_offset >> 2); 3975 utrdlp[i].prd_table_offset = 3976 cpu_to_le16(prdt_offset >> 2); 3977 utrdlp[i].response_upiu_length = 3978 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 3979 } 3980 3981 ufshcd_init_lrb(hba, &hba->lrb[i], i); 3982 } 3983 } 3984 3985 /** 3986 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 3987 * @hba: per adapter instance 3988 * 3989 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 3990 * in order to initialize the Unipro link startup procedure. 3991 * Once the Unipro links are up, the device connected to the controller 3992 * is detected. 3993 * 3994 * Return: 0 on success, non-zero value on failure. 3995 */ 3996 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 3997 { 3998 struct uic_command uic_cmd = { 3999 .command = UIC_CMD_DME_LINK_STARTUP, 4000 }; 4001 int ret; 4002 4003 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4004 if (ret) 4005 dev_dbg(hba->dev, 4006 "dme-link-startup: error code %d\n", ret); 4007 return ret; 4008 } 4009 /** 4010 * ufshcd_dme_reset - UIC command for DME_RESET 4011 * @hba: per adapter instance 4012 * 4013 * DME_RESET command is issued in order to reset UniPro stack. 4014 * This function now deals with cold reset. 4015 * 4016 * Return: 0 on success, non-zero value on failure. 4017 */ 4018 static int ufshcd_dme_reset(struct ufs_hba *hba) 4019 { 4020 struct uic_command uic_cmd = { 4021 .command = UIC_CMD_DME_RESET, 4022 }; 4023 int ret; 4024 4025 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4026 if (ret) 4027 dev_err(hba->dev, 4028 "dme-reset: error code %d\n", ret); 4029 4030 return ret; 4031 } 4032 4033 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 4034 int agreed_gear, 4035 int adapt_val) 4036 { 4037 int ret; 4038 4039 if (agreed_gear < UFS_HS_G4) 4040 adapt_val = PA_NO_ADAPT; 4041 4042 ret = ufshcd_dme_set(hba, 4043 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 4044 adapt_val); 4045 return ret; 4046 } 4047 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 4048 4049 /** 4050 * ufshcd_dme_enable - UIC command for DME_ENABLE 4051 * @hba: per adapter instance 4052 * 4053 * DME_ENABLE command is issued in order to enable UniPro stack. 4054 * 4055 * Return: 0 on success, non-zero value on failure. 4056 */ 4057 static int ufshcd_dme_enable(struct ufs_hba *hba) 4058 { 4059 struct uic_command uic_cmd = { 4060 .command = UIC_CMD_DME_ENABLE, 4061 }; 4062 int ret; 4063 4064 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4065 if (ret) 4066 dev_err(hba->dev, 4067 "dme-enable: error code %d\n", ret); 4068 4069 return ret; 4070 } 4071 4072 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 4073 { 4074 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 4075 unsigned long min_sleep_time_us; 4076 4077 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 4078 return; 4079 4080 /* 4081 * last_dme_cmd_tstamp will be 0 only for 1st call to 4082 * this function 4083 */ 4084 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 4085 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 4086 } else { 4087 unsigned long delta = 4088 (unsigned long) ktime_to_us( 4089 ktime_sub(ktime_get(), 4090 hba->last_dme_cmd_tstamp)); 4091 4092 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 4093 min_sleep_time_us = 4094 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 4095 else 4096 min_sleep_time_us = 0; /* no more delay required */ 4097 } 4098 4099 if (min_sleep_time_us > 0) { 4100 /* allow sleep for extra 50us if needed */ 4101 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 4102 } 4103 4104 /* update the last_dme_cmd_tstamp */ 4105 hba->last_dme_cmd_tstamp = ktime_get(); 4106 } 4107 4108 /** 4109 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 4110 * @hba: per adapter instance 4111 * @attr_sel: uic command argument1 4112 * @attr_set: attribute set type as uic command argument2 4113 * @mib_val: setting value as uic command argument3 4114 * @peer: indicate whether peer or local 4115 * 4116 * Return: 0 on success, non-zero value on failure. 4117 */ 4118 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 4119 u8 attr_set, u32 mib_val, u8 peer) 4120 { 4121 struct uic_command uic_cmd = { 4122 .command = peer ? UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET, 4123 .argument1 = attr_sel, 4124 .argument2 = UIC_ARG_ATTR_TYPE(attr_set), 4125 .argument3 = mib_val, 4126 }; 4127 static const char *const action[] = { 4128 "dme-set", 4129 "dme-peer-set" 4130 }; 4131 const char *set = action[!!peer]; 4132 int ret; 4133 int retries = UFS_UIC_COMMAND_RETRIES; 4134 4135 do { 4136 /* for peer attributes we retry upon failure */ 4137 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4138 if (ret) 4139 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4140 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4141 } while (ret && peer && --retries); 4142 4143 if (ret) 4144 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4145 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4146 UFS_UIC_COMMAND_RETRIES - retries); 4147 4148 return ret; 4149 } 4150 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4151 4152 /** 4153 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4154 * @hba: per adapter instance 4155 * @attr_sel: uic command argument1 4156 * @mib_val: the value of the attribute as returned by the UIC command 4157 * @peer: indicate whether peer or local 4158 * 4159 * Return: 0 on success, non-zero value on failure. 4160 */ 4161 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4162 u32 *mib_val, u8 peer) 4163 { 4164 struct uic_command uic_cmd = { 4165 .command = peer ? UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET, 4166 .argument1 = attr_sel, 4167 }; 4168 static const char *const action[] = { 4169 "dme-get", 4170 "dme-peer-get" 4171 }; 4172 const char *get = action[!!peer]; 4173 int ret; 4174 int retries = UFS_UIC_COMMAND_RETRIES; 4175 struct ufs_pa_layer_attr orig_pwr_info; 4176 struct ufs_pa_layer_attr temp_pwr_info; 4177 bool pwr_mode_change = false; 4178 4179 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4180 orig_pwr_info = hba->pwr_info; 4181 temp_pwr_info = orig_pwr_info; 4182 4183 if (orig_pwr_info.pwr_tx == FAST_MODE || 4184 orig_pwr_info.pwr_rx == FAST_MODE) { 4185 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4186 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4187 pwr_mode_change = true; 4188 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4189 orig_pwr_info.pwr_rx == SLOW_MODE) { 4190 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4191 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4192 pwr_mode_change = true; 4193 } 4194 if (pwr_mode_change) { 4195 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4196 if (ret) 4197 goto out; 4198 } 4199 } 4200 4201 do { 4202 /* for peer attributes we retry upon failure */ 4203 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4204 if (ret) 4205 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4206 get, UIC_GET_ATTR_ID(attr_sel), ret); 4207 } while (ret && peer && --retries); 4208 4209 if (ret) 4210 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4211 get, UIC_GET_ATTR_ID(attr_sel), 4212 UFS_UIC_COMMAND_RETRIES - retries); 4213 4214 if (mib_val && !ret) 4215 *mib_val = uic_cmd.argument3; 4216 4217 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4218 && pwr_mode_change) 4219 ufshcd_change_power_mode(hba, &orig_pwr_info); 4220 out: 4221 return ret; 4222 } 4223 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4224 4225 /** 4226 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4227 * state) and waits for it to take effect. 4228 * 4229 * @hba: per adapter instance 4230 * @cmd: UIC command to execute 4231 * 4232 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4233 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4234 * and device UniPro link and hence it's final completion would be indicated by 4235 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4236 * addition to normal UIC command completion Status (UCCS). This function only 4237 * returns after the relevant status bits indicate the completion. 4238 * 4239 * Return: 0 on success, non-zero value on failure. 4240 */ 4241 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4242 { 4243 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4244 unsigned long flags; 4245 u8 status; 4246 int ret; 4247 bool reenable_intr = false; 4248 4249 mutex_lock(&hba->uic_cmd_mutex); 4250 ufshcd_add_delay_before_dme_cmd(hba); 4251 4252 spin_lock_irqsave(hba->host->host_lock, flags); 4253 if (ufshcd_is_link_broken(hba)) { 4254 ret = -ENOLINK; 4255 goto out_unlock; 4256 } 4257 hba->uic_async_done = &uic_async_done; 4258 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4259 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4260 /* 4261 * Make sure UIC command completion interrupt is disabled before 4262 * issuing UIC command. 4263 */ 4264 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 4265 reenable_intr = true; 4266 } 4267 spin_unlock_irqrestore(hba->host->host_lock, flags); 4268 ret = __ufshcd_send_uic_cmd(hba, cmd); 4269 if (ret) { 4270 dev_err(hba->dev, 4271 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4272 cmd->command, cmd->argument3, ret); 4273 goto out; 4274 } 4275 4276 if (!wait_for_completion_timeout(hba->uic_async_done, 4277 msecs_to_jiffies(uic_cmd_timeout))) { 4278 dev_err(hba->dev, 4279 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4280 cmd->command, cmd->argument3); 4281 4282 if (!cmd->cmd_active) { 4283 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4284 __func__); 4285 goto check_upmcrs; 4286 } 4287 4288 ret = -ETIMEDOUT; 4289 goto out; 4290 } 4291 4292 check_upmcrs: 4293 status = ufshcd_get_upmcrs(hba); 4294 if (status != PWR_LOCAL) { 4295 dev_err(hba->dev, 4296 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4297 cmd->command, status); 4298 ret = (status != PWR_OK) ? status : -1; 4299 } 4300 out: 4301 if (ret) { 4302 ufshcd_print_host_state(hba); 4303 ufshcd_print_pwr_info(hba); 4304 ufshcd_print_evt_hist(hba); 4305 } 4306 4307 spin_lock_irqsave(hba->host->host_lock, flags); 4308 hba->active_uic_cmd = NULL; 4309 hba->uic_async_done = NULL; 4310 if (reenable_intr) 4311 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4312 if (ret) { 4313 ufshcd_set_link_broken(hba); 4314 ufshcd_schedule_eh_work(hba); 4315 } 4316 out_unlock: 4317 spin_unlock_irqrestore(hba->host->host_lock, flags); 4318 mutex_unlock(&hba->uic_cmd_mutex); 4319 4320 return ret; 4321 } 4322 4323 /** 4324 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4325 * using DME_SET primitives. 4326 * @hba: per adapter instance 4327 * @mode: powr mode value 4328 * 4329 * Return: 0 on success, non-zero value on failure. 4330 */ 4331 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4332 { 4333 struct uic_command uic_cmd = { 4334 .command = UIC_CMD_DME_SET, 4335 .argument1 = UIC_ARG_MIB(PA_PWRMODE), 4336 .argument3 = mode, 4337 }; 4338 int ret; 4339 4340 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4341 ret = ufshcd_dme_set(hba, 4342 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4343 if (ret) { 4344 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4345 __func__, ret); 4346 goto out; 4347 } 4348 } 4349 4350 ufshcd_hold(hba); 4351 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4352 ufshcd_release(hba); 4353 4354 out: 4355 return ret; 4356 } 4357 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4358 4359 int ufshcd_link_recovery(struct ufs_hba *hba) 4360 { 4361 int ret; 4362 unsigned long flags; 4363 4364 spin_lock_irqsave(hba->host->host_lock, flags); 4365 hba->ufshcd_state = UFSHCD_STATE_RESET; 4366 ufshcd_set_eh_in_progress(hba); 4367 spin_unlock_irqrestore(hba->host->host_lock, flags); 4368 4369 /* Reset the attached device */ 4370 ufshcd_device_reset(hba); 4371 4372 ret = ufshcd_host_reset_and_restore(hba); 4373 4374 spin_lock_irqsave(hba->host->host_lock, flags); 4375 if (ret) 4376 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4377 ufshcd_clear_eh_in_progress(hba); 4378 spin_unlock_irqrestore(hba->host->host_lock, flags); 4379 4380 if (ret) 4381 dev_err(hba->dev, "%s: link recovery failed, err %d", 4382 __func__, ret); 4383 4384 return ret; 4385 } 4386 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4387 4388 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4389 { 4390 struct uic_command uic_cmd = { 4391 .command = UIC_CMD_DME_HIBER_ENTER, 4392 }; 4393 ktime_t start = ktime_get(); 4394 int ret; 4395 4396 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4397 4398 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4399 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4400 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4401 4402 if (ret) 4403 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4404 __func__, ret); 4405 else 4406 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4407 POST_CHANGE); 4408 4409 return ret; 4410 } 4411 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4412 4413 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4414 { 4415 struct uic_command uic_cmd = { 4416 .command = UIC_CMD_DME_HIBER_EXIT, 4417 }; 4418 int ret; 4419 ktime_t start = ktime_get(); 4420 4421 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4422 4423 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4424 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4425 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4426 4427 if (ret) { 4428 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4429 __func__, ret); 4430 } else { 4431 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4432 POST_CHANGE); 4433 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4434 hba->ufs_stats.hibern8_exit_cnt++; 4435 } 4436 4437 return ret; 4438 } 4439 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4440 4441 static void ufshcd_configure_auto_hibern8(struct ufs_hba *hba) 4442 { 4443 if (!ufshcd_is_auto_hibern8_supported(hba)) 4444 return; 4445 4446 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4447 } 4448 4449 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4450 { 4451 const u32 cur_ahit = READ_ONCE(hba->ahit); 4452 4453 if (!ufshcd_is_auto_hibern8_supported(hba) || cur_ahit == ahit) 4454 return; 4455 4456 WRITE_ONCE(hba->ahit, ahit); 4457 if (!pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4458 ufshcd_rpm_get_sync(hba); 4459 ufshcd_hold(hba); 4460 ufshcd_configure_auto_hibern8(hba); 4461 ufshcd_release(hba); 4462 ufshcd_rpm_put_sync(hba); 4463 } 4464 } 4465 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4466 4467 /** 4468 * ufshcd_init_pwr_info - setting the POR (power on reset) 4469 * values in hba power info 4470 * @hba: per-adapter instance 4471 */ 4472 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4473 { 4474 hba->pwr_info.gear_rx = UFS_PWM_G1; 4475 hba->pwr_info.gear_tx = UFS_PWM_G1; 4476 hba->pwr_info.lane_rx = UFS_LANE_1; 4477 hba->pwr_info.lane_tx = UFS_LANE_1; 4478 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4479 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4480 hba->pwr_info.hs_rate = 0; 4481 } 4482 4483 /** 4484 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4485 * @hba: per-adapter instance 4486 * 4487 * Return: 0 upon success; < 0 upon failure. 4488 */ 4489 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4490 { 4491 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4492 4493 if (hba->max_pwr_info.is_valid) 4494 return 0; 4495 4496 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4497 pwr_info->pwr_tx = FASTAUTO_MODE; 4498 pwr_info->pwr_rx = FASTAUTO_MODE; 4499 } else { 4500 pwr_info->pwr_tx = FAST_MODE; 4501 pwr_info->pwr_rx = FAST_MODE; 4502 } 4503 pwr_info->hs_rate = PA_HS_MODE_B; 4504 4505 /* Get the connected lane count */ 4506 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4507 &pwr_info->lane_rx); 4508 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4509 &pwr_info->lane_tx); 4510 4511 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4512 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4513 __func__, 4514 pwr_info->lane_rx, 4515 pwr_info->lane_tx); 4516 return -EINVAL; 4517 } 4518 4519 if (pwr_info->lane_rx != pwr_info->lane_tx) { 4520 dev_err(hba->dev, "%s: asymmetric connected lanes. rx=%d, tx=%d\n", 4521 __func__, 4522 pwr_info->lane_rx, 4523 pwr_info->lane_tx); 4524 return -EINVAL; 4525 } 4526 4527 /* 4528 * First, get the maximum gears of HS speed. 4529 * If a zero value, it means there is no HSGEAR capability. 4530 * Then, get the maximum gears of PWM speed. 4531 */ 4532 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4533 if (!pwr_info->gear_rx) { 4534 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4535 &pwr_info->gear_rx); 4536 if (!pwr_info->gear_rx) { 4537 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4538 __func__, pwr_info->gear_rx); 4539 return -EINVAL; 4540 } 4541 pwr_info->pwr_rx = SLOW_MODE; 4542 } 4543 4544 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4545 &pwr_info->gear_tx); 4546 if (!pwr_info->gear_tx) { 4547 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4548 &pwr_info->gear_tx); 4549 if (!pwr_info->gear_tx) { 4550 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4551 __func__, pwr_info->gear_tx); 4552 return -EINVAL; 4553 } 4554 pwr_info->pwr_tx = SLOW_MODE; 4555 } 4556 4557 hba->max_pwr_info.is_valid = true; 4558 return 0; 4559 } 4560 4561 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4562 struct ufs_pa_layer_attr *pwr_mode) 4563 { 4564 int ret; 4565 4566 /* if already configured to the requested pwr_mode */ 4567 if (!hba->force_pmc && 4568 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4569 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4570 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4571 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4572 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4573 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4574 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4575 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4576 return 0; 4577 } 4578 4579 /* 4580 * Configure attributes for power mode change with below. 4581 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4582 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4583 * - PA_HSSERIES 4584 */ 4585 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4586 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4587 pwr_mode->lane_rx); 4588 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4589 pwr_mode->pwr_rx == FAST_MODE) 4590 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4591 else 4592 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4593 4594 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4595 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4596 pwr_mode->lane_tx); 4597 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4598 pwr_mode->pwr_tx == FAST_MODE) 4599 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4600 else 4601 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4602 4603 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4604 pwr_mode->pwr_tx == FASTAUTO_MODE || 4605 pwr_mode->pwr_rx == FAST_MODE || 4606 pwr_mode->pwr_tx == FAST_MODE) 4607 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4608 pwr_mode->hs_rate); 4609 4610 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4611 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4612 DL_FC0ProtectionTimeOutVal_Default); 4613 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4614 DL_TC0ReplayTimeOutVal_Default); 4615 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4616 DL_AFC0ReqTimeOutVal_Default); 4617 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4618 DL_FC1ProtectionTimeOutVal_Default); 4619 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4620 DL_TC1ReplayTimeOutVal_Default); 4621 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4622 DL_AFC1ReqTimeOutVal_Default); 4623 4624 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4625 DL_FC0ProtectionTimeOutVal_Default); 4626 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4627 DL_TC0ReplayTimeOutVal_Default); 4628 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4629 DL_AFC0ReqTimeOutVal_Default); 4630 } 4631 4632 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4633 | pwr_mode->pwr_tx); 4634 4635 if (ret) { 4636 dev_err(hba->dev, 4637 "%s: power mode change failed %d\n", __func__, ret); 4638 } else { 4639 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4640 pwr_mode); 4641 4642 memcpy(&hba->pwr_info, pwr_mode, 4643 sizeof(struct ufs_pa_layer_attr)); 4644 } 4645 4646 return ret; 4647 } 4648 4649 /** 4650 * ufshcd_config_pwr_mode - configure a new power mode 4651 * @hba: per-adapter instance 4652 * @desired_pwr_mode: desired power configuration 4653 * 4654 * Return: 0 upon success; < 0 upon failure. 4655 */ 4656 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4657 struct ufs_pa_layer_attr *desired_pwr_mode) 4658 { 4659 struct ufs_pa_layer_attr final_params = { 0 }; 4660 int ret; 4661 4662 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4663 desired_pwr_mode, &final_params); 4664 4665 if (ret) 4666 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4667 4668 ret = ufshcd_change_power_mode(hba, &final_params); 4669 4670 return ret; 4671 } 4672 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4673 4674 /** 4675 * ufshcd_complete_dev_init() - checks device readiness 4676 * @hba: per-adapter instance 4677 * 4678 * Set fDeviceInit flag and poll until device toggles it. 4679 * 4680 * Return: 0 upon success; < 0 upon failure. 4681 */ 4682 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4683 { 4684 int err; 4685 bool flag_res = true; 4686 ktime_t timeout; 4687 4688 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4689 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4690 if (err) { 4691 dev_err(hba->dev, 4692 "%s: setting fDeviceInit flag failed with error %d\n", 4693 __func__, err); 4694 goto out; 4695 } 4696 4697 /* Poll fDeviceInit flag to be cleared */ 4698 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4699 do { 4700 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4701 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4702 if (!flag_res) 4703 break; 4704 usleep_range(500, 1000); 4705 } while (ktime_before(ktime_get(), timeout)); 4706 4707 if (err) { 4708 dev_err(hba->dev, 4709 "%s: reading fDeviceInit flag failed with error %d\n", 4710 __func__, err); 4711 } else if (flag_res) { 4712 dev_err(hba->dev, 4713 "%s: fDeviceInit was not cleared by the device\n", 4714 __func__); 4715 err = -EBUSY; 4716 } 4717 out: 4718 return err; 4719 } 4720 4721 /** 4722 * ufshcd_make_hba_operational - Make UFS controller operational 4723 * @hba: per adapter instance 4724 * 4725 * To bring UFS host controller to operational state, 4726 * 1. Enable required interrupts 4727 * 2. Configure interrupt aggregation 4728 * 3. Program UTRL and UTMRL base address 4729 * 4. Configure run-stop-registers 4730 * 4731 * Return: 0 on success, non-zero value on failure. 4732 */ 4733 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4734 { 4735 int err = 0; 4736 u32 reg; 4737 4738 /* Enable required interrupts */ 4739 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4740 4741 /* Configure interrupt aggregation */ 4742 if (ufshcd_is_intr_aggr_allowed(hba)) 4743 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4744 else 4745 ufshcd_disable_intr_aggr(hba); 4746 4747 /* Configure UTRL and UTMRL base address registers */ 4748 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4749 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4750 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4751 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4752 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4753 REG_UTP_TASK_REQ_LIST_BASE_L); 4754 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4755 REG_UTP_TASK_REQ_LIST_BASE_H); 4756 4757 /* 4758 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4759 */ 4760 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4761 if (!(ufshcd_get_lists_status(reg))) { 4762 ufshcd_enable_run_stop_reg(hba); 4763 } else { 4764 dev_err(hba->dev, 4765 "Host controller not ready to process requests"); 4766 err = -EIO; 4767 } 4768 4769 return err; 4770 } 4771 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4772 4773 /** 4774 * ufshcd_hba_stop - Send controller to reset state 4775 * @hba: per adapter instance 4776 */ 4777 void ufshcd_hba_stop(struct ufs_hba *hba) 4778 { 4779 unsigned long flags; 4780 int err; 4781 4782 /* 4783 * Obtain the host lock to prevent that the controller is disabled 4784 * while the UFS interrupt handler is active on another CPU. 4785 */ 4786 spin_lock_irqsave(hba->host->host_lock, flags); 4787 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4788 spin_unlock_irqrestore(hba->host->host_lock, flags); 4789 4790 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4791 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4792 10, 1); 4793 if (err) 4794 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4795 } 4796 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4797 4798 /** 4799 * ufshcd_hba_execute_hce - initialize the controller 4800 * @hba: per adapter instance 4801 * 4802 * The controller resets itself and controller firmware initialization 4803 * sequence kicks off. When controller is ready it will set 4804 * the Host Controller Enable bit to 1. 4805 * 4806 * Return: 0 on success, non-zero value on failure. 4807 */ 4808 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4809 { 4810 int retry; 4811 4812 for (retry = 3; retry > 0; retry--) { 4813 if (ufshcd_is_hba_active(hba)) 4814 /* change controller state to "reset state" */ 4815 ufshcd_hba_stop(hba); 4816 4817 /* UniPro link is disabled at this point */ 4818 ufshcd_set_link_off(hba); 4819 4820 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4821 4822 /* start controller initialization sequence */ 4823 ufshcd_hba_start(hba); 4824 4825 /* 4826 * To initialize a UFS host controller HCE bit must be set to 1. 4827 * During initialization the HCE bit value changes from 1->0->1. 4828 * When the host controller completes initialization sequence 4829 * it sets the value of HCE bit to 1. The same HCE bit is read back 4830 * to check if the controller has completed initialization sequence. 4831 * So without this delay the value HCE = 1, set in the previous 4832 * instruction might be read back. 4833 * This delay can be changed based on the controller. 4834 */ 4835 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4836 4837 /* wait for the host controller to complete initialization */ 4838 if (!ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, CONTROLLER_ENABLE, 4839 CONTROLLER_ENABLE, 1000, 50)) 4840 break; 4841 4842 dev_err(hba->dev, "Enabling the controller failed\n"); 4843 } 4844 4845 if (!retry) 4846 return -EIO; 4847 4848 /* enable UIC related interrupts */ 4849 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4850 4851 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4852 4853 return 0; 4854 } 4855 4856 int ufshcd_hba_enable(struct ufs_hba *hba) 4857 { 4858 int ret; 4859 4860 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4861 ufshcd_set_link_off(hba); 4862 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4863 4864 /* enable UIC related interrupts */ 4865 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4866 ret = ufshcd_dme_reset(hba); 4867 if (ret) { 4868 dev_err(hba->dev, "DME_RESET failed\n"); 4869 return ret; 4870 } 4871 4872 ret = ufshcd_dme_enable(hba); 4873 if (ret) { 4874 dev_err(hba->dev, "Enabling DME failed\n"); 4875 return ret; 4876 } 4877 4878 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4879 } else { 4880 ret = ufshcd_hba_execute_hce(hba); 4881 } 4882 4883 return ret; 4884 } 4885 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4886 4887 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4888 { 4889 int tx_lanes = 0, i, err = 0; 4890 4891 if (!peer) 4892 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4893 &tx_lanes); 4894 else 4895 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4896 &tx_lanes); 4897 for (i = 0; i < tx_lanes; i++) { 4898 if (!peer) 4899 err = ufshcd_dme_set(hba, 4900 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4901 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4902 0); 4903 else 4904 err = ufshcd_dme_peer_set(hba, 4905 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4906 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4907 0); 4908 if (err) { 4909 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4910 __func__, peer, i, err); 4911 break; 4912 } 4913 } 4914 4915 return err; 4916 } 4917 4918 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4919 { 4920 return ufshcd_disable_tx_lcc(hba, true); 4921 } 4922 4923 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4924 { 4925 struct ufs_event_hist *e; 4926 4927 if (id >= UFS_EVT_CNT) 4928 return; 4929 4930 e = &hba->ufs_stats.event[id]; 4931 e->val[e->pos] = val; 4932 e->tstamp[e->pos] = local_clock(); 4933 e->cnt += 1; 4934 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4935 4936 ufshcd_vops_event_notify(hba, id, &val); 4937 } 4938 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4939 4940 /** 4941 * ufshcd_link_startup - Initialize unipro link startup 4942 * @hba: per adapter instance 4943 * 4944 * Return: 0 for success, non-zero in case of failure. 4945 */ 4946 static int ufshcd_link_startup(struct ufs_hba *hba) 4947 { 4948 int ret; 4949 int retries = DME_LINKSTARTUP_RETRIES; 4950 bool link_startup_again = false; 4951 4952 /* 4953 * If UFS device isn't active then we will have to issue link startup 4954 * 2 times to make sure the device state move to active. 4955 */ 4956 if (!ufshcd_is_ufs_dev_active(hba)) 4957 link_startup_again = true; 4958 4959 link_startup: 4960 do { 4961 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4962 4963 ret = ufshcd_dme_link_startup(hba); 4964 4965 /* check if device is detected by inter-connect layer */ 4966 if (!ret && !ufshcd_is_device_present(hba)) { 4967 ufshcd_update_evt_hist(hba, 4968 UFS_EVT_LINK_STARTUP_FAIL, 4969 0); 4970 dev_err(hba->dev, "%s: Device not present\n", __func__); 4971 ret = -ENXIO; 4972 goto out; 4973 } 4974 4975 /* 4976 * DME link lost indication is only received when link is up, 4977 * but we can't be sure if the link is up until link startup 4978 * succeeds. So reset the local Uni-Pro and try again. 4979 */ 4980 if (ret && retries && ufshcd_hba_enable(hba)) { 4981 ufshcd_update_evt_hist(hba, 4982 UFS_EVT_LINK_STARTUP_FAIL, 4983 (u32)ret); 4984 goto out; 4985 } 4986 } while (ret && retries--); 4987 4988 if (ret) { 4989 /* failed to get the link up... retire */ 4990 ufshcd_update_evt_hist(hba, 4991 UFS_EVT_LINK_STARTUP_FAIL, 4992 (u32)ret); 4993 goto out; 4994 } 4995 4996 if (link_startup_again) { 4997 link_startup_again = false; 4998 retries = DME_LINKSTARTUP_RETRIES; 4999 goto link_startup; 5000 } 5001 5002 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 5003 ufshcd_init_pwr_info(hba); 5004 ufshcd_print_pwr_info(hba); 5005 5006 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 5007 ret = ufshcd_disable_device_tx_lcc(hba); 5008 if (ret) 5009 goto out; 5010 } 5011 5012 /* Include any host controller configuration via UIC commands */ 5013 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 5014 if (ret) 5015 goto out; 5016 5017 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 5018 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 5019 ret = ufshcd_make_hba_operational(hba); 5020 out: 5021 if (ret) { 5022 dev_err(hba->dev, "link startup failed %d\n", ret); 5023 ufshcd_print_host_state(hba); 5024 ufshcd_print_pwr_info(hba); 5025 ufshcd_print_evt_hist(hba); 5026 } 5027 return ret; 5028 } 5029 5030 /** 5031 * ufshcd_verify_dev_init() - Verify device initialization 5032 * @hba: per-adapter instance 5033 * 5034 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 5035 * device Transport Protocol (UTP) layer is ready after a reset. 5036 * If the UTP layer at the device side is not initialized, it may 5037 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 5038 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 5039 * 5040 * Return: 0 upon success; < 0 upon failure. 5041 */ 5042 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 5043 { 5044 int err = 0; 5045 int retries; 5046 5047 ufshcd_dev_man_lock(hba); 5048 5049 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 5050 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 5051 hba->nop_out_timeout); 5052 5053 if (!err || err == -ETIMEDOUT) 5054 break; 5055 5056 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 5057 } 5058 5059 ufshcd_dev_man_unlock(hba); 5060 5061 if (err) 5062 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 5063 return err; 5064 } 5065 5066 /** 5067 * ufshcd_setup_links - associate link b/w device wlun and other luns 5068 * @sdev: pointer to SCSI device 5069 * @hba: pointer to ufs hba 5070 */ 5071 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 5072 { 5073 struct device_link *link; 5074 5075 /* 5076 * Device wlun is the supplier & rest of the luns are consumers. 5077 * This ensures that device wlun suspends after all other luns. 5078 */ 5079 if (hba->ufs_device_wlun) { 5080 link = device_link_add(&sdev->sdev_gendev, 5081 &hba->ufs_device_wlun->sdev_gendev, 5082 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 5083 if (!link) { 5084 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 5085 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 5086 return; 5087 } 5088 hba->luns_avail--; 5089 /* Ignore REPORT_LUN wlun probing */ 5090 if (hba->luns_avail == 1) { 5091 ufshcd_rpm_put(hba); 5092 return; 5093 } 5094 } else { 5095 /* 5096 * Device wlun is probed. The assumption is that WLUNs are 5097 * scanned before other LUNs. 5098 */ 5099 hba->luns_avail--; 5100 } 5101 } 5102 5103 /** 5104 * ufshcd_lu_init - Initialize the relevant parameters of the LU 5105 * @hba: per-adapter instance 5106 * @sdev: pointer to SCSI device 5107 */ 5108 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 5109 { 5110 int len = QUERY_DESC_MAX_SIZE; 5111 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 5112 u8 lun_qdepth = hba->nutrs; 5113 u8 *desc_buf; 5114 int ret; 5115 5116 desc_buf = kzalloc(len, GFP_KERNEL); 5117 if (!desc_buf) 5118 goto set_qdepth; 5119 5120 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5121 if (ret < 0) { 5122 if (ret == -EOPNOTSUPP) 5123 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5124 lun_qdepth = 1; 5125 kfree(desc_buf); 5126 goto set_qdepth; 5127 } 5128 5129 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5130 /* 5131 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5132 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5133 */ 5134 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5135 } 5136 /* 5137 * According to UFS device specification, the write protection mode is only supported by 5138 * normal LU, not supported by WLUN. 5139 */ 5140 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5141 !hba->dev_info.is_lu_power_on_wp && 5142 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5143 hba->dev_info.is_lu_power_on_wp = true; 5144 5145 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5146 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5147 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5148 hba->dev_info.b_advanced_rpmb_en = true; 5149 5150 5151 kfree(desc_buf); 5152 set_qdepth: 5153 /* 5154 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5155 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5156 */ 5157 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5158 scsi_change_queue_depth(sdev, lun_qdepth); 5159 } 5160 5161 /** 5162 * ufshcd_slave_alloc - handle initial SCSI device configurations 5163 * @sdev: pointer to SCSI device 5164 * 5165 * Return: success. 5166 */ 5167 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5168 { 5169 struct ufs_hba *hba; 5170 5171 hba = shost_priv(sdev->host); 5172 5173 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5174 sdev->use_10_for_ms = 1; 5175 5176 /* DBD field should be set to 1 in mode sense(10) */ 5177 sdev->set_dbd_for_ms = 1; 5178 5179 /* allow SCSI layer to restart the device in case of errors */ 5180 sdev->allow_restart = 1; 5181 5182 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5183 sdev->no_report_opcodes = 1; 5184 5185 /* WRITE_SAME command is not supported */ 5186 sdev->no_write_same = 1; 5187 5188 ufshcd_lu_init(hba, sdev); 5189 5190 ufshcd_setup_links(hba, sdev); 5191 5192 return 0; 5193 } 5194 5195 /** 5196 * ufshcd_change_queue_depth - change queue depth 5197 * @sdev: pointer to SCSI device 5198 * @depth: required depth to set 5199 * 5200 * Change queue depth and make sure the max. limits are not crossed. 5201 * 5202 * Return: new queue depth. 5203 */ 5204 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5205 { 5206 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5207 } 5208 5209 /** 5210 * ufshcd_device_configure - adjust SCSI device configurations 5211 * @sdev: pointer to SCSI device 5212 * @lim: queue limits 5213 * 5214 * Return: 0 (success). 5215 */ 5216 static int ufshcd_device_configure(struct scsi_device *sdev, 5217 struct queue_limits *lim) 5218 { 5219 struct ufs_hba *hba = shost_priv(sdev->host); 5220 struct request_queue *q = sdev->request_queue; 5221 5222 lim->dma_pad_mask = PRDT_DATA_BYTE_COUNT_PAD - 1; 5223 5224 /* 5225 * Block runtime-pm until all consumers are added. 5226 * Refer ufshcd_setup_links(). 5227 */ 5228 if (is_device_wlun(sdev)) 5229 pm_runtime_get_noresume(&sdev->sdev_gendev); 5230 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5231 sdev->rpm_autosuspend = 1; 5232 /* 5233 * Do not print messages during runtime PM to avoid never-ending cycles 5234 * of messages written back to storage by user space causing runtime 5235 * resume, causing more messages and so on. 5236 */ 5237 sdev->silence_suspend = 1; 5238 5239 ufshcd_crypto_register(hba, q); 5240 5241 return 0; 5242 } 5243 5244 /** 5245 * ufshcd_slave_destroy - remove SCSI device configurations 5246 * @sdev: pointer to SCSI device 5247 */ 5248 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5249 { 5250 struct ufs_hba *hba; 5251 unsigned long flags; 5252 5253 hba = shost_priv(sdev->host); 5254 5255 /* Drop the reference as it won't be needed anymore */ 5256 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5257 spin_lock_irqsave(hba->host->host_lock, flags); 5258 hba->ufs_device_wlun = NULL; 5259 spin_unlock_irqrestore(hba->host->host_lock, flags); 5260 } else if (hba->ufs_device_wlun) { 5261 struct device *supplier = NULL; 5262 5263 /* Ensure UFS Device WLUN exists and does not disappear */ 5264 spin_lock_irqsave(hba->host->host_lock, flags); 5265 if (hba->ufs_device_wlun) { 5266 supplier = &hba->ufs_device_wlun->sdev_gendev; 5267 get_device(supplier); 5268 } 5269 spin_unlock_irqrestore(hba->host->host_lock, flags); 5270 5271 if (supplier) { 5272 /* 5273 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5274 * device will not have been registered but can still 5275 * have a device link holding a reference to the device. 5276 */ 5277 device_link_remove(&sdev->sdev_gendev, supplier); 5278 put_device(supplier); 5279 } 5280 } 5281 } 5282 5283 /** 5284 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5285 * @lrbp: pointer to local reference block of completed command 5286 * @scsi_status: SCSI command status 5287 * 5288 * Return: value base on SCSI command status. 5289 */ 5290 static inline int 5291 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5292 { 5293 int result = 0; 5294 5295 switch (scsi_status) { 5296 case SAM_STAT_CHECK_CONDITION: 5297 ufshcd_copy_sense_data(lrbp); 5298 fallthrough; 5299 case SAM_STAT_GOOD: 5300 result |= DID_OK << 16 | scsi_status; 5301 break; 5302 case SAM_STAT_TASK_SET_FULL: 5303 case SAM_STAT_BUSY: 5304 case SAM_STAT_TASK_ABORTED: 5305 ufshcd_copy_sense_data(lrbp); 5306 result |= scsi_status; 5307 break; 5308 default: 5309 result |= DID_ERROR << 16; 5310 break; 5311 } /* end of switch */ 5312 5313 return result; 5314 } 5315 5316 /** 5317 * ufshcd_transfer_rsp_status - Get overall status of the response 5318 * @hba: per adapter instance 5319 * @lrbp: pointer to local reference block of completed command 5320 * @cqe: pointer to the completion queue entry 5321 * 5322 * Return: result of the command to notify SCSI midlayer. 5323 */ 5324 static inline int 5325 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5326 struct cq_entry *cqe) 5327 { 5328 int result = 0; 5329 int scsi_status; 5330 enum utp_ocs ocs; 5331 u8 upiu_flags; 5332 u32 resid; 5333 5334 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5335 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5336 /* 5337 * Test !overflow instead of underflow to support UFS devices that do 5338 * not set either flag. 5339 */ 5340 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5341 scsi_set_resid(lrbp->cmd, resid); 5342 5343 /* overall command status of utrd */ 5344 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5345 5346 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5347 if (lrbp->ucd_rsp_ptr->header.response || 5348 lrbp->ucd_rsp_ptr->header.status) 5349 ocs = OCS_SUCCESS; 5350 } 5351 5352 switch (ocs) { 5353 case OCS_SUCCESS: 5354 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5355 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5356 case UPIU_TRANSACTION_RESPONSE: 5357 /* 5358 * get the result based on SCSI status response 5359 * to notify the SCSI midlayer of the command status 5360 */ 5361 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5362 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5363 5364 /* 5365 * Currently we are only supporting BKOPs exception 5366 * events hence we can ignore BKOPs exception event 5367 * during power management callbacks. BKOPs exception 5368 * event is not expected to be raised in runtime suspend 5369 * callback as it allows the urgent bkops. 5370 * During system suspend, we are anyway forcefully 5371 * disabling the bkops and if urgent bkops is needed 5372 * it will be enabled on system resume. Long term 5373 * solution could be to abort the system suspend if 5374 * UFS device needs urgent BKOPs. 5375 */ 5376 if (!hba->pm_op_in_progress && 5377 !ufshcd_eh_in_progress(hba) && 5378 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5379 /* Flushed in suspend */ 5380 schedule_work(&hba->eeh_work); 5381 break; 5382 case UPIU_TRANSACTION_REJECT_UPIU: 5383 /* TODO: handle Reject UPIU Response */ 5384 result = DID_ERROR << 16; 5385 dev_err(hba->dev, 5386 "Reject UPIU not fully implemented\n"); 5387 break; 5388 default: 5389 dev_err(hba->dev, 5390 "Unexpected request response code = %x\n", 5391 result); 5392 result = DID_ERROR << 16; 5393 break; 5394 } 5395 break; 5396 case OCS_ABORTED: 5397 result |= DID_ABORT << 16; 5398 break; 5399 case OCS_INVALID_COMMAND_STATUS: 5400 result |= DID_REQUEUE << 16; 5401 break; 5402 case OCS_INVALID_CMD_TABLE_ATTR: 5403 case OCS_INVALID_PRDT_ATTR: 5404 case OCS_MISMATCH_DATA_BUF_SIZE: 5405 case OCS_MISMATCH_RESP_UPIU_SIZE: 5406 case OCS_PEER_COMM_FAILURE: 5407 case OCS_FATAL_ERROR: 5408 case OCS_DEVICE_FATAL_ERROR: 5409 case OCS_INVALID_CRYPTO_CONFIG: 5410 case OCS_GENERAL_CRYPTO_ERROR: 5411 default: 5412 result |= DID_ERROR << 16; 5413 dev_err(hba->dev, 5414 "OCS error from controller = %x for tag %d\n", 5415 ocs, lrbp->task_tag); 5416 ufshcd_print_evt_hist(hba); 5417 ufshcd_print_host_state(hba); 5418 break; 5419 } /* end of switch */ 5420 5421 if ((host_byte(result) != DID_OK) && 5422 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5423 ufshcd_print_tr(hba, lrbp->task_tag, true); 5424 return result; 5425 } 5426 5427 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5428 u32 intr_mask) 5429 { 5430 if (!ufshcd_is_auto_hibern8_supported(hba) || 5431 !ufshcd_is_auto_hibern8_enabled(hba)) 5432 return false; 5433 5434 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5435 return false; 5436 5437 if (hba->active_uic_cmd && 5438 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5439 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5440 return false; 5441 5442 return true; 5443 } 5444 5445 /** 5446 * ufshcd_uic_cmd_compl - handle completion of uic command 5447 * @hba: per adapter instance 5448 * @intr_status: interrupt status generated by the controller 5449 * 5450 * Return: 5451 * IRQ_HANDLED - If interrupt is valid 5452 * IRQ_NONE - If invalid interrupt 5453 */ 5454 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5455 { 5456 irqreturn_t retval = IRQ_NONE; 5457 struct uic_command *cmd; 5458 5459 spin_lock(hba->host->host_lock); 5460 cmd = hba->active_uic_cmd; 5461 if (WARN_ON_ONCE(!cmd)) 5462 goto unlock; 5463 5464 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5465 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5466 5467 if (intr_status & UIC_COMMAND_COMPL) { 5468 cmd->argument2 |= ufshcd_get_uic_cmd_result(hba); 5469 cmd->argument3 = ufshcd_get_dme_attr_val(hba); 5470 if (!hba->uic_async_done) 5471 cmd->cmd_active = 0; 5472 complete(&cmd->done); 5473 retval = IRQ_HANDLED; 5474 } 5475 5476 if (intr_status & UFSHCD_UIC_PWR_MASK && hba->uic_async_done) { 5477 cmd->cmd_active = 0; 5478 complete(hba->uic_async_done); 5479 retval = IRQ_HANDLED; 5480 } 5481 5482 if (retval == IRQ_HANDLED) 5483 ufshcd_add_uic_command_trace(hba, cmd, UFS_CMD_COMP); 5484 5485 unlock: 5486 spin_unlock(hba->host->host_lock); 5487 5488 return retval; 5489 } 5490 5491 /* Release the resources allocated for processing a SCSI command. */ 5492 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5493 struct ufshcd_lrb *lrbp) 5494 { 5495 struct scsi_cmnd *cmd = lrbp->cmd; 5496 5497 scsi_dma_unmap(cmd); 5498 ufshcd_crypto_clear_prdt(hba, lrbp); 5499 ufshcd_release(hba); 5500 ufshcd_clk_scaling_update_busy(hba); 5501 } 5502 5503 /** 5504 * ufshcd_compl_one_cqe - handle a completion queue entry 5505 * @hba: per adapter instance 5506 * @task_tag: the task tag of the request to be completed 5507 * @cqe: pointer to the completion queue entry 5508 */ 5509 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5510 struct cq_entry *cqe) 5511 { 5512 struct ufshcd_lrb *lrbp; 5513 struct scsi_cmnd *cmd; 5514 enum utp_ocs ocs; 5515 5516 lrbp = &hba->lrb[task_tag]; 5517 lrbp->compl_time_stamp = ktime_get(); 5518 cmd = lrbp->cmd; 5519 if (cmd) { 5520 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5521 ufshcd_update_monitor(hba, lrbp); 5522 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5523 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5524 ufshcd_release_scsi_cmd(hba, lrbp); 5525 /* Do not touch lrbp after scsi done */ 5526 scsi_done(cmd); 5527 } else if (hba->dev_cmd.complete) { 5528 if (cqe) { 5529 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5530 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5531 } 5532 complete(hba->dev_cmd.complete); 5533 } 5534 } 5535 5536 /** 5537 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5538 * @hba: per adapter instance 5539 * @completed_reqs: bitmask that indicates which requests to complete 5540 */ 5541 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5542 unsigned long completed_reqs) 5543 { 5544 int tag; 5545 5546 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5547 ufshcd_compl_one_cqe(hba, tag, NULL); 5548 } 5549 5550 /* Any value that is not an existing queue number is fine for this constant. */ 5551 enum { 5552 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5553 }; 5554 5555 static void ufshcd_clear_polled(struct ufs_hba *hba, 5556 unsigned long *completed_reqs) 5557 { 5558 int tag; 5559 5560 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5561 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5562 5563 if (!cmd) 5564 continue; 5565 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5566 __clear_bit(tag, completed_reqs); 5567 } 5568 } 5569 5570 /* 5571 * Return: > 0 if one or more commands have been completed or 0 if no 5572 * requests have been completed. 5573 */ 5574 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5575 { 5576 struct ufs_hba *hba = shost_priv(shost); 5577 unsigned long completed_reqs, flags; 5578 u32 tr_doorbell; 5579 struct ufs_hw_queue *hwq; 5580 5581 if (hba->mcq_enabled) { 5582 hwq = &hba->uhq[queue_num]; 5583 5584 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5585 } 5586 5587 spin_lock_irqsave(&hba->outstanding_lock, flags); 5588 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5589 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5590 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5591 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5592 hba->outstanding_reqs); 5593 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5594 /* Do not complete polled requests from interrupt context. */ 5595 ufshcd_clear_polled(hba, &completed_reqs); 5596 } 5597 hba->outstanding_reqs &= ~completed_reqs; 5598 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5599 5600 if (completed_reqs) 5601 __ufshcd_transfer_req_compl(hba, completed_reqs); 5602 5603 return completed_reqs != 0; 5604 } 5605 5606 /** 5607 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5608 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5609 * to complete the pending transfers and free the resources associated with 5610 * the scsi command. 5611 * 5612 * @hba: per adapter instance 5613 * @force_compl: This flag is set to true when invoked 5614 * from ufshcd_host_reset_and_restore() in which case it requires special 5615 * handling because the host controller has been reset by ufshcd_hba_stop(). 5616 */ 5617 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5618 bool force_compl) 5619 { 5620 struct ufs_hw_queue *hwq; 5621 struct ufshcd_lrb *lrbp; 5622 struct scsi_cmnd *cmd; 5623 unsigned long flags; 5624 int tag; 5625 5626 for (tag = 0; tag < hba->nutrs; tag++) { 5627 lrbp = &hba->lrb[tag]; 5628 cmd = lrbp->cmd; 5629 if (!ufshcd_cmd_inflight(cmd) || 5630 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5631 continue; 5632 5633 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 5634 5635 if (force_compl) { 5636 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5637 /* 5638 * For those cmds of which the cqes are not present 5639 * in the cq, complete them explicitly. 5640 */ 5641 spin_lock_irqsave(&hwq->cq_lock, flags); 5642 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5643 set_host_byte(cmd, DID_REQUEUE); 5644 ufshcd_release_scsi_cmd(hba, lrbp); 5645 scsi_done(cmd); 5646 } 5647 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5648 } else { 5649 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5650 } 5651 } 5652 } 5653 5654 /** 5655 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5656 * @hba: per adapter instance 5657 * 5658 * Return: 5659 * IRQ_HANDLED - If interrupt is valid 5660 * IRQ_NONE - If invalid interrupt 5661 */ 5662 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5663 { 5664 /* Resetting interrupt aggregation counters first and reading the 5665 * DOOR_BELL afterward allows us to handle all the completed requests. 5666 * In order to prevent other interrupts starvation the DB is read once 5667 * after reset. The down side of this solution is the possibility of 5668 * false interrupt if device completes another request after resetting 5669 * aggregation and before reading the DB. 5670 */ 5671 if (ufshcd_is_intr_aggr_allowed(hba) && 5672 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5673 ufshcd_reset_intr_aggr(hba); 5674 5675 if (ufs_fail_completion(hba)) 5676 return IRQ_HANDLED; 5677 5678 /* 5679 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5680 * do not want polling to trigger spurious interrupt complaints. 5681 */ 5682 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5683 5684 return IRQ_HANDLED; 5685 } 5686 5687 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5688 { 5689 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5690 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5691 &ee_ctrl_mask); 5692 } 5693 5694 int ufshcd_write_ee_control(struct ufs_hba *hba) 5695 { 5696 int err; 5697 5698 mutex_lock(&hba->ee_ctrl_mutex); 5699 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5700 mutex_unlock(&hba->ee_ctrl_mutex); 5701 if (err) 5702 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5703 __func__, err); 5704 return err; 5705 } 5706 5707 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5708 const u16 *other_mask, u16 set, u16 clr) 5709 { 5710 u16 new_mask, ee_ctrl_mask; 5711 int err = 0; 5712 5713 mutex_lock(&hba->ee_ctrl_mutex); 5714 new_mask = (*mask & ~clr) | set; 5715 ee_ctrl_mask = new_mask | *other_mask; 5716 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5717 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5718 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5719 if (!err) { 5720 hba->ee_ctrl_mask = ee_ctrl_mask; 5721 *mask = new_mask; 5722 } 5723 mutex_unlock(&hba->ee_ctrl_mutex); 5724 return err; 5725 } 5726 5727 /** 5728 * ufshcd_disable_ee - disable exception event 5729 * @hba: per-adapter instance 5730 * @mask: exception event to disable 5731 * 5732 * Disables exception event in the device so that the EVENT_ALERT 5733 * bit is not set. 5734 * 5735 * Return: zero on success, non-zero error value on failure. 5736 */ 5737 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5738 { 5739 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5740 } 5741 5742 /** 5743 * ufshcd_enable_ee - enable exception event 5744 * @hba: per-adapter instance 5745 * @mask: exception event to enable 5746 * 5747 * Enable corresponding exception event in the device to allow 5748 * device to alert host in critical scenarios. 5749 * 5750 * Return: zero on success, non-zero error value on failure. 5751 */ 5752 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5753 { 5754 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5755 } 5756 5757 /** 5758 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5759 * @hba: per-adapter instance 5760 * 5761 * Allow device to manage background operations on its own. Enabling 5762 * this might lead to inconsistent latencies during normal data transfers 5763 * as the device is allowed to manage its own way of handling background 5764 * operations. 5765 * 5766 * Return: zero on success, non-zero on failure. 5767 */ 5768 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5769 { 5770 int err = 0; 5771 5772 if (hba->auto_bkops_enabled) 5773 goto out; 5774 5775 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5776 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5777 if (err) { 5778 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5779 __func__, err); 5780 goto out; 5781 } 5782 5783 hba->auto_bkops_enabled = true; 5784 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5785 5786 /* No need of URGENT_BKOPS exception from the device */ 5787 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5788 if (err) 5789 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5790 __func__, err); 5791 out: 5792 return err; 5793 } 5794 5795 /** 5796 * ufshcd_disable_auto_bkops - block device in doing background operations 5797 * @hba: per-adapter instance 5798 * 5799 * Disabling background operations improves command response latency but 5800 * has drawback of device moving into critical state where the device is 5801 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5802 * host is idle so that BKOPS are managed effectively without any negative 5803 * impacts. 5804 * 5805 * Return: zero on success, non-zero on failure. 5806 */ 5807 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5808 { 5809 int err = 0; 5810 5811 if (!hba->auto_bkops_enabled) 5812 goto out; 5813 5814 /* 5815 * If host assisted BKOPs is to be enabled, make sure 5816 * urgent bkops exception is allowed. 5817 */ 5818 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5819 if (err) { 5820 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5821 __func__, err); 5822 goto out; 5823 } 5824 5825 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5826 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5827 if (err) { 5828 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5829 __func__, err); 5830 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5831 goto out; 5832 } 5833 5834 hba->auto_bkops_enabled = false; 5835 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5836 hba->is_urgent_bkops_lvl_checked = false; 5837 out: 5838 return err; 5839 } 5840 5841 /** 5842 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5843 * @hba: per adapter instance 5844 * 5845 * After a device reset the device may toggle the BKOPS_EN flag 5846 * to default value. The s/w tracking variables should be updated 5847 * as well. This function would change the auto-bkops state based on 5848 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5849 */ 5850 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5851 { 5852 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5853 hba->auto_bkops_enabled = false; 5854 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5855 ufshcd_enable_auto_bkops(hba); 5856 } else { 5857 hba->auto_bkops_enabled = true; 5858 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5859 ufshcd_disable_auto_bkops(hba); 5860 } 5861 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5862 hba->is_urgent_bkops_lvl_checked = false; 5863 } 5864 5865 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5866 { 5867 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5868 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5869 } 5870 5871 /** 5872 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5873 * @hba: per-adapter instance 5874 * 5875 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5876 * flag in the device to permit background operations if the device 5877 * bkops_status is greater than or equal to the "hba->urgent_bkops_lvl", 5878 * disable otherwise. 5879 * 5880 * Return: 0 for success, non-zero in case of failure. 5881 * 5882 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5883 * to know whether auto bkops is enabled or disabled after this function 5884 * returns control to it. 5885 */ 5886 static int ufshcd_bkops_ctrl(struct ufs_hba *hba) 5887 { 5888 enum bkops_status status = hba->urgent_bkops_lvl; 5889 u32 curr_status = 0; 5890 int err; 5891 5892 err = ufshcd_get_bkops_status(hba, &curr_status); 5893 if (err) { 5894 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5895 __func__, err); 5896 goto out; 5897 } else if (curr_status > BKOPS_STATUS_MAX) { 5898 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5899 __func__, curr_status); 5900 err = -EINVAL; 5901 goto out; 5902 } 5903 5904 if (curr_status >= status) 5905 err = ufshcd_enable_auto_bkops(hba); 5906 else 5907 err = ufshcd_disable_auto_bkops(hba); 5908 out: 5909 return err; 5910 } 5911 5912 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5913 { 5914 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5915 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5916 } 5917 5918 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5919 { 5920 int err; 5921 u32 curr_status = 0; 5922 5923 if (hba->is_urgent_bkops_lvl_checked) 5924 goto enable_auto_bkops; 5925 5926 err = ufshcd_get_bkops_status(hba, &curr_status); 5927 if (err) { 5928 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5929 __func__, err); 5930 goto out; 5931 } 5932 5933 /* 5934 * We are seeing that some devices are raising the urgent bkops 5935 * exception events even when BKOPS status doesn't indicate performace 5936 * impacted or critical. Handle these device by determining their urgent 5937 * bkops status at runtime. 5938 */ 5939 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5940 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5941 __func__, curr_status); 5942 /* update the current status as the urgent bkops level */ 5943 hba->urgent_bkops_lvl = curr_status; 5944 hba->is_urgent_bkops_lvl_checked = true; 5945 } 5946 5947 enable_auto_bkops: 5948 err = ufshcd_enable_auto_bkops(hba); 5949 out: 5950 if (err < 0) 5951 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5952 __func__, err); 5953 } 5954 5955 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5956 { 5957 u32 value; 5958 5959 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5960 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 5961 return; 5962 5963 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 5964 5965 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 5966 5967 /* 5968 * A placeholder for the platform vendors to add whatever additional 5969 * steps required 5970 */ 5971 } 5972 5973 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 5974 { 5975 u8 index; 5976 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 5977 UPIU_QUERY_OPCODE_CLEAR_FLAG; 5978 5979 index = ufshcd_wb_get_query_index(hba); 5980 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 5981 } 5982 5983 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 5984 { 5985 int ret; 5986 5987 if (!ufshcd_is_wb_allowed(hba) || 5988 hba->dev_info.wb_enabled == enable) 5989 return 0; 5990 5991 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 5992 if (ret) { 5993 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 5994 __func__, enable ? "enabling" : "disabling", ret); 5995 return ret; 5996 } 5997 5998 hba->dev_info.wb_enabled = enable; 5999 dev_dbg(hba->dev, "%s: Write Booster %s\n", 6000 __func__, enable ? "enabled" : "disabled"); 6001 6002 return ret; 6003 } 6004 6005 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 6006 bool enable) 6007 { 6008 int ret; 6009 6010 ret = __ufshcd_wb_toggle(hba, enable, 6011 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 6012 if (ret) { 6013 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 6014 __func__, enable ? "enabling" : "disabling", ret); 6015 return; 6016 } 6017 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 6018 __func__, enable ? "enabled" : "disabled"); 6019 } 6020 6021 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 6022 { 6023 int ret; 6024 6025 if (!ufshcd_is_wb_allowed(hba) || 6026 hba->dev_info.wb_buf_flush_enabled == enable) 6027 return 0; 6028 6029 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 6030 if (ret) { 6031 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 6032 __func__, enable ? "enabling" : "disabling", ret); 6033 return ret; 6034 } 6035 6036 hba->dev_info.wb_buf_flush_enabled = enable; 6037 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 6038 __func__, enable ? "enabled" : "disabled"); 6039 6040 return ret; 6041 } 6042 6043 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 6044 u32 avail_buf) 6045 { 6046 u32 cur_buf; 6047 int ret; 6048 u8 index; 6049 6050 index = ufshcd_wb_get_query_index(hba); 6051 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6052 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 6053 index, 0, &cur_buf); 6054 if (ret) { 6055 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 6056 __func__, ret); 6057 return false; 6058 } 6059 6060 if (!cur_buf) { 6061 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 6062 cur_buf); 6063 return false; 6064 } 6065 /* Let it continue to flush when available buffer exceeds threshold */ 6066 return avail_buf < hba->vps->wb_flush_threshold; 6067 } 6068 6069 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 6070 { 6071 if (ufshcd_is_wb_buf_flush_allowed(hba)) 6072 ufshcd_wb_toggle_buf_flush(hba, false); 6073 6074 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 6075 ufshcd_wb_toggle(hba, false); 6076 hba->caps &= ~UFSHCD_CAP_WB_EN; 6077 6078 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 6079 } 6080 6081 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 6082 { 6083 u32 lifetime; 6084 int ret; 6085 u8 index; 6086 6087 index = ufshcd_wb_get_query_index(hba); 6088 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6089 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 6090 index, 0, &lifetime); 6091 if (ret) { 6092 dev_err(hba->dev, 6093 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 6094 __func__, ret); 6095 return false; 6096 } 6097 6098 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6099 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6100 __func__, lifetime); 6101 return false; 6102 } 6103 6104 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6105 __func__, lifetime); 6106 6107 return true; 6108 } 6109 6110 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6111 { 6112 int ret; 6113 u32 avail_buf; 6114 u8 index; 6115 6116 if (!ufshcd_is_wb_allowed(hba)) 6117 return false; 6118 6119 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6120 ufshcd_wb_force_disable(hba); 6121 return false; 6122 } 6123 6124 /* 6125 * The ufs device needs the vcc to be ON to flush. 6126 * With user-space reduction enabled, it's enough to enable flush 6127 * by checking only the available buffer. The threshold 6128 * defined here is > 90% full. 6129 * With user-space preserved enabled, the current-buffer 6130 * should be checked too because the wb buffer size can reduce 6131 * when disk tends to be full. This info is provided by current 6132 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6133 * keeping vcc on when current buffer is empty. 6134 */ 6135 index = ufshcd_wb_get_query_index(hba); 6136 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6137 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6138 index, 0, &avail_buf); 6139 if (ret) { 6140 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6141 __func__, ret); 6142 return false; 6143 } 6144 6145 if (!hba->dev_info.b_presrv_uspc_en) 6146 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6147 6148 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6149 } 6150 6151 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6152 { 6153 struct ufs_hba *hba = container_of(to_delayed_work(work), 6154 struct ufs_hba, 6155 rpm_dev_flush_recheck_work); 6156 /* 6157 * To prevent unnecessary VCC power drain after device finishes 6158 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6159 * after a certain delay to recheck the threshold by next runtime 6160 * suspend. 6161 */ 6162 ufshcd_rpm_get_sync(hba); 6163 ufshcd_rpm_put_sync(hba); 6164 } 6165 6166 /** 6167 * ufshcd_exception_event_handler - handle exceptions raised by device 6168 * @work: pointer to work data 6169 * 6170 * Read bExceptionEventStatus attribute from the device and handle the 6171 * exception event accordingly. 6172 */ 6173 static void ufshcd_exception_event_handler(struct work_struct *work) 6174 { 6175 struct ufs_hba *hba; 6176 int err; 6177 u32 status = 0; 6178 hba = container_of(work, struct ufs_hba, eeh_work); 6179 6180 err = ufshcd_get_ee_status(hba, &status); 6181 if (err) { 6182 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6183 __func__, err); 6184 return; 6185 } 6186 6187 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6188 6189 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6190 ufshcd_bkops_exception_event_handler(hba); 6191 6192 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6193 ufshcd_temp_exception_event_handler(hba, status); 6194 6195 ufs_debugfs_exception_event(hba, status); 6196 } 6197 6198 /* Complete requests that have door-bell cleared */ 6199 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6200 { 6201 if (hba->mcq_enabled) 6202 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6203 else 6204 ufshcd_transfer_req_compl(hba); 6205 6206 ufshcd_tmc_handler(hba); 6207 } 6208 6209 /** 6210 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6211 * to recover from the DL NAC errors or not. 6212 * @hba: per-adapter instance 6213 * 6214 * Return: true if error handling is required, false otherwise. 6215 */ 6216 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6217 { 6218 unsigned long flags; 6219 bool err_handling = true; 6220 6221 spin_lock_irqsave(hba->host->host_lock, flags); 6222 /* 6223 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6224 * device fatal error and/or DL NAC & REPLAY timeout errors. 6225 */ 6226 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6227 goto out; 6228 6229 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6230 ((hba->saved_err & UIC_ERROR) && 6231 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6232 goto out; 6233 6234 if ((hba->saved_err & UIC_ERROR) && 6235 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6236 int err; 6237 /* 6238 * wait for 50ms to see if we can get any other errors or not. 6239 */ 6240 spin_unlock_irqrestore(hba->host->host_lock, flags); 6241 msleep(50); 6242 spin_lock_irqsave(hba->host->host_lock, flags); 6243 6244 /* 6245 * now check if we have got any other severe errors other than 6246 * DL NAC error? 6247 */ 6248 if ((hba->saved_err & INT_FATAL_ERRORS) || 6249 ((hba->saved_err & UIC_ERROR) && 6250 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6251 goto out; 6252 6253 /* 6254 * As DL NAC is the only error received so far, send out NOP 6255 * command to confirm if link is still active or not. 6256 * - If we don't get any response then do error recovery. 6257 * - If we get response then clear the DL NAC error bit. 6258 */ 6259 6260 spin_unlock_irqrestore(hba->host->host_lock, flags); 6261 err = ufshcd_verify_dev_init(hba); 6262 spin_lock_irqsave(hba->host->host_lock, flags); 6263 6264 if (err) 6265 goto out; 6266 6267 /* Link seems to be alive hence ignore the DL NAC errors */ 6268 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6269 hba->saved_err &= ~UIC_ERROR; 6270 /* clear NAC error */ 6271 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6272 if (!hba->saved_uic_err) 6273 err_handling = false; 6274 } 6275 out: 6276 spin_unlock_irqrestore(hba->host->host_lock, flags); 6277 return err_handling; 6278 } 6279 6280 /* host lock must be held before calling this func */ 6281 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6282 { 6283 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6284 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6285 } 6286 6287 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6288 { 6289 lockdep_assert_held(hba->host->host_lock); 6290 6291 /* handle fatal errors only when link is not in error state */ 6292 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6293 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6294 ufshcd_is_saved_err_fatal(hba)) 6295 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6296 else 6297 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6298 queue_work(hba->eh_wq, &hba->eh_work); 6299 } 6300 } 6301 6302 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6303 { 6304 spin_lock_irq(hba->host->host_lock); 6305 hba->force_reset = true; 6306 ufshcd_schedule_eh_work(hba); 6307 spin_unlock_irq(hba->host->host_lock); 6308 } 6309 6310 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6311 { 6312 mutex_lock(&hba->wb_mutex); 6313 down_write(&hba->clk_scaling_lock); 6314 hba->clk_scaling.is_allowed = allow; 6315 up_write(&hba->clk_scaling_lock); 6316 mutex_unlock(&hba->wb_mutex); 6317 } 6318 6319 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6320 { 6321 if (suspend) { 6322 if (hba->clk_scaling.is_enabled) 6323 ufshcd_suspend_clkscaling(hba); 6324 ufshcd_clk_scaling_allow(hba, false); 6325 } else { 6326 ufshcd_clk_scaling_allow(hba, true); 6327 if (hba->clk_scaling.is_enabled) 6328 ufshcd_resume_clkscaling(hba); 6329 } 6330 } 6331 6332 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6333 { 6334 ufshcd_rpm_get_sync(hba); 6335 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6336 hba->is_sys_suspended) { 6337 enum ufs_pm_op pm_op; 6338 6339 /* 6340 * Don't assume anything of resume, if 6341 * resume fails, irq and clocks can be OFF, and powers 6342 * can be OFF or in LPM. 6343 */ 6344 ufshcd_setup_hba_vreg(hba, true); 6345 ufshcd_enable_irq(hba); 6346 ufshcd_setup_vreg(hba, true); 6347 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6348 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6349 ufshcd_hold(hba); 6350 if (!ufshcd_is_clkgating_allowed(hba)) 6351 ufshcd_setup_clocks(hba, true); 6352 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6353 ufshcd_vops_resume(hba, pm_op); 6354 } else { 6355 ufshcd_hold(hba); 6356 if (ufshcd_is_clkscaling_supported(hba) && 6357 hba->clk_scaling.is_enabled) 6358 ufshcd_suspend_clkscaling(hba); 6359 ufshcd_clk_scaling_allow(hba, false); 6360 } 6361 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6362 blk_mq_quiesce_tagset(&hba->host->tag_set); 6363 cancel_work_sync(&hba->eeh_work); 6364 } 6365 6366 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6367 { 6368 blk_mq_unquiesce_tagset(&hba->host->tag_set); 6369 ufshcd_release(hba); 6370 if (ufshcd_is_clkscaling_supported(hba)) 6371 ufshcd_clk_scaling_suspend(hba, false); 6372 ufshcd_rpm_put(hba); 6373 } 6374 6375 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6376 { 6377 return (!hba->is_powered || hba->shutting_down || 6378 !hba->ufs_device_wlun || 6379 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6380 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6381 ufshcd_is_link_broken(hba)))); 6382 } 6383 6384 #ifdef CONFIG_PM 6385 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6386 { 6387 struct Scsi_Host *shost = hba->host; 6388 struct scsi_device *sdev; 6389 struct request_queue *q; 6390 int ret; 6391 6392 hba->is_sys_suspended = false; 6393 /* 6394 * Set RPM status of wlun device to RPM_ACTIVE, 6395 * this also clears its runtime error. 6396 */ 6397 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6398 6399 /* hba device might have a runtime error otherwise */ 6400 if (ret) 6401 ret = pm_runtime_set_active(hba->dev); 6402 /* 6403 * If wlun device had runtime error, we also need to resume those 6404 * consumer scsi devices in case any of them has failed to be 6405 * resumed due to supplier runtime resume failure. This is to unblock 6406 * blk_queue_enter in case there are bios waiting inside it. 6407 */ 6408 if (!ret) { 6409 shost_for_each_device(sdev, shost) { 6410 q = sdev->request_queue; 6411 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6412 q->rpm_status == RPM_SUSPENDING)) 6413 pm_request_resume(q->dev); 6414 } 6415 } 6416 } 6417 #else 6418 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6419 { 6420 } 6421 #endif 6422 6423 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6424 { 6425 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6426 u32 mode; 6427 6428 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6429 6430 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6431 return true; 6432 6433 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6434 return true; 6435 6436 return false; 6437 } 6438 6439 static bool ufshcd_abort_one(struct request *rq, void *priv) 6440 { 6441 int *ret = priv; 6442 u32 tag = rq->tag; 6443 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6444 struct scsi_device *sdev = cmd->device; 6445 struct Scsi_Host *shost = sdev->host; 6446 struct ufs_hba *hba = shost_priv(shost); 6447 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 6448 struct ufs_hw_queue *hwq; 6449 unsigned long flags; 6450 6451 *ret = ufshcd_try_to_abort_task(hba, tag); 6452 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6453 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6454 *ret ? "failed" : "succeeded"); 6455 6456 /* Release cmd in MCQ mode if abort succeeds */ 6457 if (hba->mcq_enabled && (*ret == 0)) { 6458 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 6459 if (!hwq) 6460 return 0; 6461 spin_lock_irqsave(&hwq->cq_lock, flags); 6462 if (ufshcd_cmd_inflight(lrbp->cmd)) 6463 ufshcd_release_scsi_cmd(hba, lrbp); 6464 spin_unlock_irqrestore(&hwq->cq_lock, flags); 6465 } 6466 6467 return *ret == 0; 6468 } 6469 6470 /** 6471 * ufshcd_abort_all - Abort all pending commands. 6472 * @hba: Host bus adapter pointer. 6473 * 6474 * Return: true if and only if the host controller needs to be reset. 6475 */ 6476 static bool ufshcd_abort_all(struct ufs_hba *hba) 6477 { 6478 int tag, ret = 0; 6479 6480 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6481 if (ret) 6482 goto out; 6483 6484 /* Clear pending task management requests */ 6485 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6486 ret = ufshcd_clear_tm_cmd(hba, tag); 6487 if (ret) 6488 goto out; 6489 } 6490 6491 out: 6492 /* Complete the requests that are cleared by s/w */ 6493 ufshcd_complete_requests(hba, false); 6494 6495 return ret != 0; 6496 } 6497 6498 /** 6499 * ufshcd_err_handler - handle UFS errors that require s/w attention 6500 * @work: pointer to work structure 6501 */ 6502 static void ufshcd_err_handler(struct work_struct *work) 6503 { 6504 int retries = MAX_ERR_HANDLER_RETRIES; 6505 struct ufs_hba *hba; 6506 unsigned long flags; 6507 bool needs_restore; 6508 bool needs_reset; 6509 int pmc_err; 6510 6511 hba = container_of(work, struct ufs_hba, eh_work); 6512 6513 dev_info(hba->dev, 6514 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6515 __func__, ufshcd_state_name[hba->ufshcd_state], 6516 hba->is_powered, hba->shutting_down, hba->saved_err, 6517 hba->saved_uic_err, hba->force_reset, 6518 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6519 6520 down(&hba->host_sem); 6521 spin_lock_irqsave(hba->host->host_lock, flags); 6522 if (ufshcd_err_handling_should_stop(hba)) { 6523 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6524 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6525 spin_unlock_irqrestore(hba->host->host_lock, flags); 6526 up(&hba->host_sem); 6527 return; 6528 } 6529 ufshcd_set_eh_in_progress(hba); 6530 spin_unlock_irqrestore(hba->host->host_lock, flags); 6531 ufshcd_err_handling_prepare(hba); 6532 /* Complete requests that have door-bell cleared by h/w */ 6533 ufshcd_complete_requests(hba, false); 6534 spin_lock_irqsave(hba->host->host_lock, flags); 6535 again: 6536 needs_restore = false; 6537 needs_reset = false; 6538 6539 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6540 hba->ufshcd_state = UFSHCD_STATE_RESET; 6541 /* 6542 * A full reset and restore might have happened after preparation 6543 * is finished, double check whether we should stop. 6544 */ 6545 if (ufshcd_err_handling_should_stop(hba)) 6546 goto skip_err_handling; 6547 6548 if ((hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) && 6549 !hba->force_reset) { 6550 bool ret; 6551 6552 spin_unlock_irqrestore(hba->host->host_lock, flags); 6553 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6554 ret = ufshcd_quirk_dl_nac_errors(hba); 6555 spin_lock_irqsave(hba->host->host_lock, flags); 6556 if (!ret && ufshcd_err_handling_should_stop(hba)) 6557 goto skip_err_handling; 6558 } 6559 6560 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6561 (hba->saved_uic_err && 6562 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6563 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6564 6565 spin_unlock_irqrestore(hba->host->host_lock, flags); 6566 ufshcd_print_host_state(hba); 6567 ufshcd_print_pwr_info(hba); 6568 ufshcd_print_evt_hist(hba); 6569 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6570 ufshcd_print_trs_all(hba, pr_prdt); 6571 spin_lock_irqsave(hba->host->host_lock, flags); 6572 } 6573 6574 /* 6575 * if host reset is required then skip clearing the pending 6576 * transfers forcefully because they will get cleared during 6577 * host reset and restore 6578 */ 6579 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6580 ufshcd_is_saved_err_fatal(hba) || 6581 ((hba->saved_err & UIC_ERROR) && 6582 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6583 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6584 needs_reset = true; 6585 goto do_reset; 6586 } 6587 6588 /* 6589 * If LINERESET was caught, UFS might have been put to PWM mode, 6590 * check if power mode restore is needed. 6591 */ 6592 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6593 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6594 if (!hba->saved_uic_err) 6595 hba->saved_err &= ~UIC_ERROR; 6596 spin_unlock_irqrestore(hba->host->host_lock, flags); 6597 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6598 needs_restore = true; 6599 spin_lock_irqsave(hba->host->host_lock, flags); 6600 if (!hba->saved_err && !needs_restore) 6601 goto skip_err_handling; 6602 } 6603 6604 hba->silence_err_logs = true; 6605 /* release lock as clear command might sleep */ 6606 spin_unlock_irqrestore(hba->host->host_lock, flags); 6607 6608 needs_reset = ufshcd_abort_all(hba); 6609 6610 spin_lock_irqsave(hba->host->host_lock, flags); 6611 hba->silence_err_logs = false; 6612 if (needs_reset) 6613 goto do_reset; 6614 6615 /* 6616 * After all reqs and tasks are cleared from doorbell, 6617 * now it is safe to retore power mode. 6618 */ 6619 if (needs_restore) { 6620 spin_unlock_irqrestore(hba->host->host_lock, flags); 6621 /* 6622 * Hold the scaling lock just in case dev cmds 6623 * are sent via bsg and/or sysfs. 6624 */ 6625 down_write(&hba->clk_scaling_lock); 6626 hba->force_pmc = true; 6627 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6628 if (pmc_err) { 6629 needs_reset = true; 6630 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6631 __func__, pmc_err); 6632 } 6633 hba->force_pmc = false; 6634 ufshcd_print_pwr_info(hba); 6635 up_write(&hba->clk_scaling_lock); 6636 spin_lock_irqsave(hba->host->host_lock, flags); 6637 } 6638 6639 do_reset: 6640 /* Fatal errors need reset */ 6641 if (needs_reset) { 6642 int err; 6643 6644 hba->force_reset = false; 6645 spin_unlock_irqrestore(hba->host->host_lock, flags); 6646 err = ufshcd_reset_and_restore(hba); 6647 if (err) 6648 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6649 __func__, err); 6650 else 6651 ufshcd_recover_pm_error(hba); 6652 spin_lock_irqsave(hba->host->host_lock, flags); 6653 } 6654 6655 skip_err_handling: 6656 if (!needs_reset) { 6657 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6658 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6659 if (hba->saved_err || hba->saved_uic_err) 6660 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6661 __func__, hba->saved_err, hba->saved_uic_err); 6662 } 6663 /* Exit in an operational state or dead */ 6664 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6665 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6666 if (--retries) 6667 goto again; 6668 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6669 } 6670 ufshcd_clear_eh_in_progress(hba); 6671 spin_unlock_irqrestore(hba->host->host_lock, flags); 6672 ufshcd_err_handling_unprepare(hba); 6673 up(&hba->host_sem); 6674 6675 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6676 ufshcd_state_name[hba->ufshcd_state]); 6677 } 6678 6679 /** 6680 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6681 * @hba: per-adapter instance 6682 * 6683 * Return: 6684 * IRQ_HANDLED - If interrupt is valid 6685 * IRQ_NONE - If invalid interrupt 6686 */ 6687 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6688 { 6689 u32 reg; 6690 irqreturn_t retval = IRQ_NONE; 6691 6692 /* PHY layer error */ 6693 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6694 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6695 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6696 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6697 /* 6698 * To know whether this error is fatal or not, DB timeout 6699 * must be checked but this error is handled separately. 6700 */ 6701 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6702 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6703 __func__); 6704 6705 /* Got a LINERESET indication. */ 6706 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6707 struct uic_command *cmd = NULL; 6708 6709 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6710 if (hba->uic_async_done && hba->active_uic_cmd) 6711 cmd = hba->active_uic_cmd; 6712 /* 6713 * Ignore the LINERESET during power mode change 6714 * operation via DME_SET command. 6715 */ 6716 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6717 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6718 } 6719 retval |= IRQ_HANDLED; 6720 } 6721 6722 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6723 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6724 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6725 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6726 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6727 6728 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6729 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6730 else if (hba->dev_quirks & 6731 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6732 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6733 hba->uic_error |= 6734 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6735 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6736 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6737 } 6738 retval |= IRQ_HANDLED; 6739 } 6740 6741 /* UIC NL/TL/DME errors needs software retry */ 6742 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6743 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6744 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6745 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6746 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6747 retval |= IRQ_HANDLED; 6748 } 6749 6750 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6751 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6752 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6753 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6754 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6755 retval |= IRQ_HANDLED; 6756 } 6757 6758 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6759 if ((reg & UIC_DME_ERROR) && 6760 (reg & UIC_DME_ERROR_CODE_MASK)) { 6761 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6762 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6763 retval |= IRQ_HANDLED; 6764 } 6765 6766 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6767 __func__, hba->uic_error); 6768 return retval; 6769 } 6770 6771 /** 6772 * ufshcd_check_errors - Check for errors that need s/w attention 6773 * @hba: per-adapter instance 6774 * @intr_status: interrupt status generated by the controller 6775 * 6776 * Return: 6777 * IRQ_HANDLED - If interrupt is valid 6778 * IRQ_NONE - If invalid interrupt 6779 */ 6780 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6781 { 6782 bool queue_eh_work = false; 6783 irqreturn_t retval = IRQ_NONE; 6784 6785 spin_lock(hba->host->host_lock); 6786 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6787 6788 if (hba->errors & INT_FATAL_ERRORS) { 6789 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6790 hba->errors); 6791 queue_eh_work = true; 6792 } 6793 6794 if (hba->errors & UIC_ERROR) { 6795 hba->uic_error = 0; 6796 retval = ufshcd_update_uic_error(hba); 6797 if (hba->uic_error) 6798 queue_eh_work = true; 6799 } 6800 6801 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6802 dev_err(hba->dev, 6803 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6804 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6805 "Enter" : "Exit", 6806 hba->errors, ufshcd_get_upmcrs(hba)); 6807 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6808 hba->errors); 6809 ufshcd_set_link_broken(hba); 6810 queue_eh_work = true; 6811 } 6812 6813 if (queue_eh_work) { 6814 /* 6815 * update the transfer error masks to sticky bits, let's do this 6816 * irrespective of current ufshcd_state. 6817 */ 6818 hba->saved_err |= hba->errors; 6819 hba->saved_uic_err |= hba->uic_error; 6820 6821 /* dump controller state before resetting */ 6822 if ((hba->saved_err & 6823 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6824 (hba->saved_uic_err && 6825 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6826 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6827 __func__, hba->saved_err, 6828 hba->saved_uic_err); 6829 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6830 "host_regs: "); 6831 ufshcd_print_pwr_info(hba); 6832 } 6833 ufshcd_schedule_eh_work(hba); 6834 retval |= IRQ_HANDLED; 6835 } 6836 /* 6837 * if (!queue_eh_work) - 6838 * Other errors are either non-fatal where host recovers 6839 * itself without s/w intervention or errors that will be 6840 * handled by the SCSI core layer. 6841 */ 6842 hba->errors = 0; 6843 hba->uic_error = 0; 6844 spin_unlock(hba->host->host_lock); 6845 return retval; 6846 } 6847 6848 /** 6849 * ufshcd_tmc_handler - handle task management function completion 6850 * @hba: per adapter instance 6851 * 6852 * Return: 6853 * IRQ_HANDLED - If interrupt is valid 6854 * IRQ_NONE - If invalid interrupt 6855 */ 6856 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6857 { 6858 unsigned long flags, pending, issued; 6859 irqreturn_t ret = IRQ_NONE; 6860 int tag; 6861 6862 spin_lock_irqsave(hba->host->host_lock, flags); 6863 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6864 issued = hba->outstanding_tasks & ~pending; 6865 for_each_set_bit(tag, &issued, hba->nutmrs) { 6866 struct request *req = hba->tmf_rqs[tag]; 6867 struct completion *c = req->end_io_data; 6868 6869 complete(c); 6870 ret = IRQ_HANDLED; 6871 } 6872 spin_unlock_irqrestore(hba->host->host_lock, flags); 6873 6874 return ret; 6875 } 6876 6877 /** 6878 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6879 * @hba: per adapter instance 6880 * 6881 * Return: IRQ_HANDLED if interrupt is handled. 6882 */ 6883 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6884 { 6885 struct ufs_hw_queue *hwq; 6886 unsigned long outstanding_cqs; 6887 unsigned int nr_queues; 6888 int i, ret; 6889 u32 events; 6890 6891 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6892 if (ret) 6893 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6894 6895 /* Exclude the poll queues */ 6896 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6897 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6898 hwq = &hba->uhq[i]; 6899 6900 events = ufshcd_mcq_read_cqis(hba, i); 6901 if (events) 6902 ufshcd_mcq_write_cqis(hba, events, i); 6903 6904 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6905 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6906 } 6907 6908 return IRQ_HANDLED; 6909 } 6910 6911 /** 6912 * ufshcd_sl_intr - Interrupt service routine 6913 * @hba: per adapter instance 6914 * @intr_status: contains interrupts generated by the controller 6915 * 6916 * Return: 6917 * IRQ_HANDLED - If interrupt is valid 6918 * IRQ_NONE - If invalid interrupt 6919 */ 6920 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6921 { 6922 irqreturn_t retval = IRQ_NONE; 6923 6924 if (intr_status & UFSHCD_UIC_MASK) 6925 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6926 6927 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6928 retval |= ufshcd_check_errors(hba, intr_status); 6929 6930 if (intr_status & UTP_TASK_REQ_COMPL) 6931 retval |= ufshcd_tmc_handler(hba); 6932 6933 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6934 retval |= ufshcd_transfer_req_compl(hba); 6935 6936 if (intr_status & MCQ_CQ_EVENT_STATUS) 6937 retval |= ufshcd_handle_mcq_cq_events(hba); 6938 6939 return retval; 6940 } 6941 6942 /** 6943 * ufshcd_intr - Main interrupt service routine 6944 * @irq: irq number 6945 * @__hba: pointer to adapter instance 6946 * 6947 * Return: 6948 * IRQ_HANDLED - If interrupt is valid 6949 * IRQ_NONE - If invalid interrupt 6950 */ 6951 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6952 { 6953 u32 intr_status, enabled_intr_status = 0; 6954 irqreturn_t retval = IRQ_NONE; 6955 struct ufs_hba *hba = __hba; 6956 int retries = hba->nutrs; 6957 6958 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6959 hba->ufs_stats.last_intr_status = intr_status; 6960 hba->ufs_stats.last_intr_ts = local_clock(); 6961 6962 /* 6963 * There could be max of hba->nutrs reqs in flight and in worst case 6964 * if the reqs get finished 1 by 1 after the interrupt status is 6965 * read, make sure we handle them by checking the interrupt status 6966 * again in a loop until we process all of the reqs before returning. 6967 */ 6968 while (intr_status && retries--) { 6969 enabled_intr_status = 6970 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6971 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6972 if (enabled_intr_status) 6973 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 6974 6975 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6976 } 6977 6978 if (enabled_intr_status && retval == IRQ_NONE && 6979 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 6980 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 6981 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 6982 __func__, 6983 intr_status, 6984 hba->ufs_stats.last_intr_status, 6985 enabled_intr_status); 6986 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 6987 } 6988 6989 return retval; 6990 } 6991 6992 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 6993 { 6994 int err = 0; 6995 u32 mask = 1 << tag; 6996 6997 if (!test_bit(tag, &hba->outstanding_tasks)) 6998 goto out; 6999 7000 ufshcd_utmrl_clear(hba, tag); 7001 7002 /* poll for max. 1 sec to clear door bell register by h/w */ 7003 err = ufshcd_wait_for_register(hba, 7004 REG_UTP_TASK_REQ_DOOR_BELL, 7005 mask, 0, 1000, 1000); 7006 7007 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 7008 tag, err < 0 ? "failed" : "succeeded"); 7009 7010 out: 7011 return err; 7012 } 7013 7014 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 7015 struct utp_task_req_desc *treq, u8 tm_function) 7016 { 7017 struct request_queue *q = hba->tmf_queue; 7018 struct Scsi_Host *host = hba->host; 7019 DECLARE_COMPLETION_ONSTACK(wait); 7020 struct request *req; 7021 unsigned long flags; 7022 int task_tag, err; 7023 7024 /* 7025 * blk_mq_alloc_request() is used here only to get a free tag. 7026 */ 7027 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 7028 if (IS_ERR(req)) 7029 return PTR_ERR(req); 7030 7031 req->end_io_data = &wait; 7032 ufshcd_hold(hba); 7033 7034 spin_lock_irqsave(host->host_lock, flags); 7035 7036 task_tag = req->tag; 7037 hba->tmf_rqs[req->tag] = req; 7038 treq->upiu_req.req_header.task_tag = task_tag; 7039 7040 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 7041 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 7042 7043 __set_bit(task_tag, &hba->outstanding_tasks); 7044 7045 spin_unlock_irqrestore(host->host_lock, flags); 7046 7047 /* send command to the controller */ 7048 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 7049 7050 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 7051 7052 /* wait until the task management command is completed */ 7053 err = wait_for_completion_io_timeout(&wait, 7054 msecs_to_jiffies(TM_CMD_TIMEOUT)); 7055 if (!err) { 7056 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 7057 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 7058 __func__, tm_function); 7059 if (ufshcd_clear_tm_cmd(hba, task_tag)) 7060 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 7061 __func__, task_tag); 7062 err = -ETIMEDOUT; 7063 } else { 7064 err = 0; 7065 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 7066 7067 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 7068 } 7069 7070 spin_lock_irqsave(hba->host->host_lock, flags); 7071 hba->tmf_rqs[req->tag] = NULL; 7072 __clear_bit(task_tag, &hba->outstanding_tasks); 7073 spin_unlock_irqrestore(hba->host->host_lock, flags); 7074 7075 ufshcd_release(hba); 7076 blk_mq_free_request(req); 7077 7078 return err; 7079 } 7080 7081 /** 7082 * ufshcd_issue_tm_cmd - issues task management commands to controller 7083 * @hba: per adapter instance 7084 * @lun_id: LUN ID to which TM command is sent 7085 * @task_id: task ID to which the TM command is applicable 7086 * @tm_function: task management function opcode 7087 * @tm_response: task management service response return value 7088 * 7089 * Return: non-zero value on error, zero on success. 7090 */ 7091 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7092 u8 tm_function, u8 *tm_response) 7093 { 7094 struct utp_task_req_desc treq = { }; 7095 enum utp_ocs ocs_value; 7096 int err; 7097 7098 /* Configure task request descriptor */ 7099 treq.header.interrupt = 1; 7100 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7101 7102 /* Configure task request UPIU */ 7103 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7104 treq.upiu_req.req_header.lun = lun_id; 7105 treq.upiu_req.req_header.tm_function = tm_function; 7106 7107 /* 7108 * The host shall provide the same value for LUN field in the basic 7109 * header and for Input Parameter. 7110 */ 7111 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7112 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7113 7114 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7115 if (err == -ETIMEDOUT) 7116 return err; 7117 7118 ocs_value = treq.header.ocs & MASK_OCS; 7119 if (ocs_value != OCS_SUCCESS) 7120 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7121 __func__, ocs_value); 7122 else if (tm_response) 7123 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7124 MASK_TM_SERVICE_RESP; 7125 return err; 7126 } 7127 7128 /** 7129 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7130 * @hba: per-adapter instance 7131 * @req_upiu: upiu request 7132 * @rsp_upiu: upiu reply 7133 * @desc_buff: pointer to descriptor buffer, NULL if NA 7134 * @buff_len: descriptor size, 0 if NA 7135 * @cmd_type: specifies the type (NOP, Query...) 7136 * @desc_op: descriptor operation 7137 * 7138 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7139 * Therefore, it "rides" the device management infrastructure: uses its tag and 7140 * tasks work queues. 7141 * 7142 * Since there is only one available tag for device management commands, 7143 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7144 * 7145 * Return: 0 upon success; < 0 upon failure. 7146 */ 7147 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7148 struct utp_upiu_req *req_upiu, 7149 struct utp_upiu_req *rsp_upiu, 7150 u8 *desc_buff, int *buff_len, 7151 enum dev_cmd_type cmd_type, 7152 enum query_opcode desc_op) 7153 { 7154 const u32 tag = hba->reserved_slot; 7155 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7156 int err = 0; 7157 u8 upiu_flags; 7158 7159 /* Protects use of hba->reserved_slot. */ 7160 lockdep_assert_held(&hba->dev_cmd.lock); 7161 7162 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 7163 7164 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 7165 7166 /* update the task tag in the request upiu */ 7167 req_upiu->header.task_tag = tag; 7168 7169 /* just copy the upiu request as it is */ 7170 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7171 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7172 /* The Data Segment Area is optional depending upon the query 7173 * function value. for WRITE DESCRIPTOR, the data segment 7174 * follows right after the tsf. 7175 */ 7176 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7177 *buff_len = 0; 7178 } 7179 7180 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7181 7182 /* 7183 * ignore the returning value here - ufshcd_check_query_response is 7184 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7185 * read the response directly ignoring all errors. 7186 */ 7187 ufshcd_issue_dev_cmd(hba, lrbp, tag, QUERY_REQ_TIMEOUT); 7188 7189 /* just copy the upiu response as it is */ 7190 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7191 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7192 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7193 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7194 .data_segment_length); 7195 7196 if (*buff_len >= resp_len) { 7197 memcpy(desc_buff, descp, resp_len); 7198 *buff_len = resp_len; 7199 } else { 7200 dev_warn(hba->dev, 7201 "%s: rsp size %d is bigger than buffer size %d", 7202 __func__, resp_len, *buff_len); 7203 *buff_len = 0; 7204 err = -EINVAL; 7205 } 7206 } 7207 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7208 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7209 7210 return err; 7211 } 7212 7213 /** 7214 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7215 * @hba: per-adapter instance 7216 * @req_upiu: upiu request 7217 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7218 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7219 * @desc_buff: pointer to descriptor buffer, NULL if NA 7220 * @buff_len: descriptor size, 0 if NA 7221 * @desc_op: descriptor operation 7222 * 7223 * Supports UTP Transfer requests (nop and query), and UTP Task 7224 * Management requests. 7225 * It is up to the caller to fill the upiu conent properly, as it will 7226 * be copied without any further input validations. 7227 * 7228 * Return: 0 upon success; < 0 upon failure. 7229 */ 7230 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7231 struct utp_upiu_req *req_upiu, 7232 struct utp_upiu_req *rsp_upiu, 7233 enum upiu_request_transaction msgcode, 7234 u8 *desc_buff, int *buff_len, 7235 enum query_opcode desc_op) 7236 { 7237 int err; 7238 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7239 struct utp_task_req_desc treq = { }; 7240 enum utp_ocs ocs_value; 7241 u8 tm_f = req_upiu->header.tm_function; 7242 7243 switch (msgcode) { 7244 case UPIU_TRANSACTION_NOP_OUT: 7245 cmd_type = DEV_CMD_TYPE_NOP; 7246 fallthrough; 7247 case UPIU_TRANSACTION_QUERY_REQ: 7248 ufshcd_dev_man_lock(hba); 7249 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7250 desc_buff, buff_len, 7251 cmd_type, desc_op); 7252 ufshcd_dev_man_unlock(hba); 7253 7254 break; 7255 case UPIU_TRANSACTION_TASK_REQ: 7256 treq.header.interrupt = 1; 7257 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7258 7259 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7260 7261 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7262 if (err == -ETIMEDOUT) 7263 break; 7264 7265 ocs_value = treq.header.ocs & MASK_OCS; 7266 if (ocs_value != OCS_SUCCESS) { 7267 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7268 ocs_value); 7269 break; 7270 } 7271 7272 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7273 7274 break; 7275 default: 7276 err = -EINVAL; 7277 7278 break; 7279 } 7280 7281 return err; 7282 } 7283 7284 /** 7285 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7286 * @hba: per adapter instance 7287 * @req_upiu: upiu request 7288 * @rsp_upiu: upiu reply 7289 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7290 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7291 * @sg_cnt: The number of sg lists actually used 7292 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7293 * @dir: DMA direction 7294 * 7295 * Return: zero on success, non-zero on failure. 7296 */ 7297 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7298 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7299 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7300 enum dma_data_direction dir) 7301 { 7302 const u32 tag = hba->reserved_slot; 7303 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7304 int err = 0; 7305 int result; 7306 u8 upiu_flags; 7307 u8 *ehs_data; 7308 u16 ehs_len; 7309 int ehs = (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) ? 2 : 0; 7310 7311 /* Protects use of hba->reserved_slot. */ 7312 ufshcd_dev_man_lock(hba); 7313 7314 ufshcd_setup_dev_cmd(hba, lrbp, DEV_CMD_TYPE_RPMB, UFS_UPIU_RPMB_WLUN, tag); 7315 7316 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, ehs); 7317 7318 /* update the task tag */ 7319 req_upiu->header.task_tag = tag; 7320 7321 /* copy the UPIU(contains CDB) request as it is */ 7322 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7323 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7324 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7325 7326 if (dir != DMA_NONE && sg_list) 7327 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7328 7329 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7330 7331 err = ufshcd_issue_dev_cmd(hba, lrbp, tag, ADVANCED_RPMB_REQ_TIMEOUT); 7332 7333 if (!err) { 7334 /* Just copy the upiu response as it is */ 7335 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7336 /* Get the response UPIU result */ 7337 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7338 lrbp->ucd_rsp_ptr->header.status; 7339 7340 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7341 /* 7342 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7343 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7344 * Message is 02h 7345 */ 7346 if (ehs_len == 2 && rsp_ehs) { 7347 /* 7348 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7349 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7350 */ 7351 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7352 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7353 } 7354 } 7355 7356 ufshcd_dev_man_unlock(hba); 7357 7358 return err ? : result; 7359 } 7360 7361 /** 7362 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7363 * @cmd: SCSI command pointer 7364 * 7365 * Return: SUCCESS or FAILED. 7366 */ 7367 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7368 { 7369 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7370 struct Scsi_Host *host; 7371 struct ufs_hba *hba; 7372 struct ufs_hw_queue *hwq; 7373 struct ufshcd_lrb *lrbp; 7374 u32 pos, not_cleared_mask = 0; 7375 int err; 7376 u8 resp = 0xF, lun; 7377 7378 host = cmd->device->host; 7379 hba = shost_priv(host); 7380 7381 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7382 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7383 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7384 if (!err) 7385 err = resp; 7386 goto out; 7387 } 7388 7389 if (hba->mcq_enabled) { 7390 for (pos = 0; pos < hba->nutrs; pos++) { 7391 lrbp = &hba->lrb[pos]; 7392 if (ufshcd_cmd_inflight(lrbp->cmd) && 7393 lrbp->lun == lun) { 7394 ufshcd_clear_cmd(hba, pos); 7395 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7396 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7397 } 7398 } 7399 err = 0; 7400 goto out; 7401 } 7402 7403 /* clear the commands that were pending for corresponding LUN */ 7404 spin_lock_irqsave(&hba->outstanding_lock, flags); 7405 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7406 if (hba->lrb[pos].lun == lun) 7407 __set_bit(pos, &pending_reqs); 7408 hba->outstanding_reqs &= ~pending_reqs; 7409 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7410 7411 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7412 if (ufshcd_clear_cmd(hba, pos) < 0) { 7413 spin_lock_irqsave(&hba->outstanding_lock, flags); 7414 not_cleared = 1U << pos & 7415 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7416 hba->outstanding_reqs |= not_cleared; 7417 not_cleared_mask |= not_cleared; 7418 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7419 7420 dev_err(hba->dev, "%s: failed to clear request %d\n", 7421 __func__, pos); 7422 } 7423 } 7424 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7425 7426 out: 7427 hba->req_abort_count = 0; 7428 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7429 if (!err) { 7430 err = SUCCESS; 7431 } else { 7432 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7433 err = FAILED; 7434 } 7435 return err; 7436 } 7437 7438 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7439 { 7440 struct ufshcd_lrb *lrbp; 7441 int tag; 7442 7443 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7444 lrbp = &hba->lrb[tag]; 7445 lrbp->req_abort_skip = true; 7446 } 7447 } 7448 7449 /** 7450 * ufshcd_try_to_abort_task - abort a specific task 7451 * @hba: Pointer to adapter instance 7452 * @tag: Task tag/index to be aborted 7453 * 7454 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7455 * command, and in host controller by clearing the door-bell register. There can 7456 * be race between controller sending the command to the device while abort is 7457 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7458 * really issued and then try to abort it. 7459 * 7460 * Return: zero on success, non-zero on failure. 7461 */ 7462 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7463 { 7464 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7465 int err; 7466 int poll_cnt; 7467 u8 resp = 0xF; 7468 7469 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7470 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7471 UFS_QUERY_TASK, &resp); 7472 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7473 /* cmd pending in the device */ 7474 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7475 __func__, tag); 7476 break; 7477 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7478 /* 7479 * cmd not pending in the device, check if it is 7480 * in transition. 7481 */ 7482 dev_info( 7483 hba->dev, 7484 "%s: cmd with tag %d not pending in the device.\n", 7485 __func__, tag); 7486 if (!ufshcd_cmd_inflight(lrbp->cmd)) { 7487 dev_info(hba->dev, 7488 "%s: cmd with tag=%d completed.\n", 7489 __func__, tag); 7490 return 0; 7491 } 7492 usleep_range(100, 200); 7493 } else { 7494 dev_err(hba->dev, 7495 "%s: no response from device. tag = %d, err %d\n", 7496 __func__, tag, err); 7497 return err ? : resp; 7498 } 7499 } 7500 7501 if (!poll_cnt) 7502 return -EBUSY; 7503 7504 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7505 UFS_ABORT_TASK, &resp); 7506 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7507 if (!err) { 7508 err = resp; /* service response error */ 7509 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7510 __func__, tag, err); 7511 } 7512 return err; 7513 } 7514 7515 err = ufshcd_clear_cmd(hba, tag); 7516 if (err) 7517 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7518 __func__, tag, err); 7519 7520 return err; 7521 } 7522 7523 /** 7524 * ufshcd_abort - scsi host template eh_abort_handler callback 7525 * @cmd: SCSI command pointer 7526 * 7527 * Return: SUCCESS or FAILED. 7528 */ 7529 static int ufshcd_abort(struct scsi_cmnd *cmd) 7530 { 7531 struct Scsi_Host *host = cmd->device->host; 7532 struct ufs_hba *hba = shost_priv(host); 7533 int tag = scsi_cmd_to_rq(cmd)->tag; 7534 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7535 unsigned long flags; 7536 int err = FAILED; 7537 bool outstanding; 7538 u32 reg; 7539 7540 ufshcd_hold(hba); 7541 7542 if (!hba->mcq_enabled) { 7543 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7544 if (!test_bit(tag, &hba->outstanding_reqs)) { 7545 /* If command is already aborted/completed, return FAILED. */ 7546 dev_err(hba->dev, 7547 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7548 __func__, tag, hba->outstanding_reqs, reg); 7549 goto release; 7550 } 7551 } 7552 7553 /* Print Transfer Request of aborted task */ 7554 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7555 7556 /* 7557 * Print detailed info about aborted request. 7558 * As more than one request might get aborted at the same time, 7559 * print full information only for the first aborted request in order 7560 * to reduce repeated printouts. For other aborted requests only print 7561 * basic details. 7562 */ 7563 scsi_print_command(cmd); 7564 if (!hba->req_abort_count) { 7565 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7566 ufshcd_print_evt_hist(hba); 7567 ufshcd_print_host_state(hba); 7568 ufshcd_print_pwr_info(hba); 7569 ufshcd_print_tr(hba, tag, true); 7570 } else { 7571 ufshcd_print_tr(hba, tag, false); 7572 } 7573 hba->req_abort_count++; 7574 7575 if (!hba->mcq_enabled && !(reg & (1 << tag))) { 7576 /* only execute this code in single doorbell mode */ 7577 dev_err(hba->dev, 7578 "%s: cmd was completed, but without a notifying intr, tag = %d", 7579 __func__, tag); 7580 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7581 goto release; 7582 } 7583 7584 /* 7585 * Task abort to the device W-LUN is illegal. When this command 7586 * will fail, due to spec violation, scsi err handling next step 7587 * will be to send LU reset which, again, is a spec violation. 7588 * To avoid these unnecessary/illegal steps, first we clean up 7589 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7590 * then queue the eh_work and bail. 7591 */ 7592 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7593 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7594 7595 spin_lock_irqsave(host->host_lock, flags); 7596 hba->force_reset = true; 7597 ufshcd_schedule_eh_work(hba); 7598 spin_unlock_irqrestore(host->host_lock, flags); 7599 goto release; 7600 } 7601 7602 if (hba->mcq_enabled) { 7603 /* MCQ mode. Branch off to handle abort for mcq mode */ 7604 err = ufshcd_mcq_abort(cmd); 7605 goto release; 7606 } 7607 7608 /* Skip task abort in case previous aborts failed and report failure */ 7609 if (lrbp->req_abort_skip) { 7610 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7611 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7612 goto release; 7613 } 7614 7615 err = ufshcd_try_to_abort_task(hba, tag); 7616 if (err) { 7617 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7618 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7619 err = FAILED; 7620 goto release; 7621 } 7622 7623 /* 7624 * Clear the corresponding bit from outstanding_reqs since the command 7625 * has been aborted successfully. 7626 */ 7627 spin_lock_irqsave(&hba->outstanding_lock, flags); 7628 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7629 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7630 7631 if (outstanding) 7632 ufshcd_release_scsi_cmd(hba, lrbp); 7633 7634 err = SUCCESS; 7635 7636 release: 7637 /* Matches the ufshcd_hold() call at the start of this function. */ 7638 ufshcd_release(hba); 7639 return err; 7640 } 7641 7642 /** 7643 * ufshcd_process_probe_result - Process the ufshcd_probe_hba() result. 7644 * @hba: UFS host controller instance. 7645 * @probe_start: time when the ufshcd_probe_hba() call started. 7646 * @ret: ufshcd_probe_hba() return value. 7647 */ 7648 static void ufshcd_process_probe_result(struct ufs_hba *hba, 7649 ktime_t probe_start, int ret) 7650 { 7651 unsigned long flags; 7652 7653 spin_lock_irqsave(hba->host->host_lock, flags); 7654 if (ret) 7655 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7656 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 7657 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 7658 spin_unlock_irqrestore(hba->host->host_lock, flags); 7659 7660 trace_ufshcd_init(dev_name(hba->dev), ret, 7661 ktime_to_us(ktime_sub(ktime_get(), probe_start)), 7662 hba->curr_dev_pwr_mode, hba->uic_link_state); 7663 } 7664 7665 /** 7666 * ufshcd_host_reset_and_restore - reset and restore host controller 7667 * @hba: per-adapter instance 7668 * 7669 * Note that host controller reset may issue DME_RESET to 7670 * local and remote (device) Uni-Pro stack and the attributes 7671 * are reset to default state. 7672 * 7673 * Return: zero on success, non-zero on failure. 7674 */ 7675 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7676 { 7677 int err; 7678 7679 /* 7680 * Stop the host controller and complete the requests 7681 * cleared by h/w 7682 */ 7683 ufshcd_hba_stop(hba); 7684 hba->silence_err_logs = true; 7685 ufshcd_complete_requests(hba, true); 7686 hba->silence_err_logs = false; 7687 7688 /* scale up clocks to max frequency before full reinitialization */ 7689 ufshcd_scale_clks(hba, ULONG_MAX, true); 7690 7691 err = ufshcd_hba_enable(hba); 7692 7693 /* Establish the link again and restore the device */ 7694 if (!err) { 7695 ktime_t probe_start = ktime_get(); 7696 7697 err = ufshcd_device_init(hba, /*init_dev_params=*/false); 7698 if (!err) 7699 err = ufshcd_probe_hba(hba, false); 7700 ufshcd_process_probe_result(hba, probe_start, err); 7701 } 7702 7703 if (err) 7704 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7705 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7706 return err; 7707 } 7708 7709 /** 7710 * ufshcd_reset_and_restore - reset and re-initialize host/device 7711 * @hba: per-adapter instance 7712 * 7713 * Reset and recover device, host and re-establish link. This 7714 * is helpful to recover the communication in fatal error conditions. 7715 * 7716 * Return: zero on success, non-zero on failure. 7717 */ 7718 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7719 { 7720 u32 saved_err = 0; 7721 u32 saved_uic_err = 0; 7722 int err = 0; 7723 unsigned long flags; 7724 int retries = MAX_HOST_RESET_RETRIES; 7725 7726 spin_lock_irqsave(hba->host->host_lock, flags); 7727 do { 7728 /* 7729 * This is a fresh start, cache and clear saved error first, 7730 * in case new error generated during reset and restore. 7731 */ 7732 saved_err |= hba->saved_err; 7733 saved_uic_err |= hba->saved_uic_err; 7734 hba->saved_err = 0; 7735 hba->saved_uic_err = 0; 7736 hba->force_reset = false; 7737 hba->ufshcd_state = UFSHCD_STATE_RESET; 7738 spin_unlock_irqrestore(hba->host->host_lock, flags); 7739 7740 /* Reset the attached device */ 7741 ufshcd_device_reset(hba); 7742 7743 err = ufshcd_host_reset_and_restore(hba); 7744 7745 spin_lock_irqsave(hba->host->host_lock, flags); 7746 if (err) 7747 continue; 7748 /* Do not exit unless operational or dead */ 7749 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7750 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7751 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7752 err = -EAGAIN; 7753 } while (err && --retries); 7754 7755 /* 7756 * Inform scsi mid-layer that we did reset and allow to handle 7757 * Unit Attention properly. 7758 */ 7759 scsi_report_bus_reset(hba->host, 0); 7760 if (err) { 7761 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7762 hba->saved_err |= saved_err; 7763 hba->saved_uic_err |= saved_uic_err; 7764 } 7765 spin_unlock_irqrestore(hba->host->host_lock, flags); 7766 7767 return err; 7768 } 7769 7770 /** 7771 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7772 * @cmd: SCSI command pointer 7773 * 7774 * Return: SUCCESS or FAILED. 7775 */ 7776 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7777 { 7778 int err = SUCCESS; 7779 unsigned long flags; 7780 struct ufs_hba *hba; 7781 7782 hba = shost_priv(cmd->device->host); 7783 7784 /* 7785 * If runtime PM sent SSU and got a timeout, scsi_error_handler is 7786 * stuck in this function waiting for flush_work(&hba->eh_work). And 7787 * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do 7788 * ufshcd_link_recovery instead of eh_work to prevent deadlock. 7789 */ 7790 if (hba->pm_op_in_progress) { 7791 if (ufshcd_link_recovery(hba)) 7792 err = FAILED; 7793 7794 return err; 7795 } 7796 7797 spin_lock_irqsave(hba->host->host_lock, flags); 7798 hba->force_reset = true; 7799 ufshcd_schedule_eh_work(hba); 7800 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7801 spin_unlock_irqrestore(hba->host->host_lock, flags); 7802 7803 flush_work(&hba->eh_work); 7804 7805 spin_lock_irqsave(hba->host->host_lock, flags); 7806 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7807 err = FAILED; 7808 spin_unlock_irqrestore(hba->host->host_lock, flags); 7809 7810 return err; 7811 } 7812 7813 /** 7814 * ufshcd_get_max_icc_level - calculate the ICC level 7815 * @sup_curr_uA: max. current supported by the regulator 7816 * @start_scan: row at the desc table to start scan from 7817 * @buff: power descriptor buffer 7818 * 7819 * Return: calculated max ICC level for specific regulator. 7820 */ 7821 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7822 const char *buff) 7823 { 7824 int i; 7825 int curr_uA; 7826 u16 data; 7827 u16 unit; 7828 7829 for (i = start_scan; i >= 0; i--) { 7830 data = get_unaligned_be16(&buff[2 * i]); 7831 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7832 ATTR_ICC_LVL_UNIT_OFFSET; 7833 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7834 switch (unit) { 7835 case UFSHCD_NANO_AMP: 7836 curr_uA = curr_uA / 1000; 7837 break; 7838 case UFSHCD_MILI_AMP: 7839 curr_uA = curr_uA * 1000; 7840 break; 7841 case UFSHCD_AMP: 7842 curr_uA = curr_uA * 1000 * 1000; 7843 break; 7844 case UFSHCD_MICRO_AMP: 7845 default: 7846 break; 7847 } 7848 if (sup_curr_uA >= curr_uA) 7849 break; 7850 } 7851 if (i < 0) { 7852 i = 0; 7853 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7854 } 7855 7856 return (u32)i; 7857 } 7858 7859 /** 7860 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7861 * In case regulators are not initialized we'll return 0 7862 * @hba: per-adapter instance 7863 * @desc_buf: power descriptor buffer to extract ICC levels from. 7864 * 7865 * Return: calculated ICC level. 7866 */ 7867 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7868 const u8 *desc_buf) 7869 { 7870 u32 icc_level = 0; 7871 7872 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7873 !hba->vreg_info.vccq2) { 7874 /* 7875 * Using dev_dbg to avoid messages during runtime PM to avoid 7876 * never-ending cycles of messages written back to storage by 7877 * user space causing runtime resume, causing more messages and 7878 * so on. 7879 */ 7880 dev_dbg(hba->dev, 7881 "%s: Regulator capability was not set, actvIccLevel=%d", 7882 __func__, icc_level); 7883 goto out; 7884 } 7885 7886 if (hba->vreg_info.vcc->max_uA) 7887 icc_level = ufshcd_get_max_icc_level( 7888 hba->vreg_info.vcc->max_uA, 7889 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7890 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7891 7892 if (hba->vreg_info.vccq->max_uA) 7893 icc_level = ufshcd_get_max_icc_level( 7894 hba->vreg_info.vccq->max_uA, 7895 icc_level, 7896 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7897 7898 if (hba->vreg_info.vccq2->max_uA) 7899 icc_level = ufshcd_get_max_icc_level( 7900 hba->vreg_info.vccq2->max_uA, 7901 icc_level, 7902 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7903 out: 7904 return icc_level; 7905 } 7906 7907 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7908 { 7909 int ret; 7910 u8 *desc_buf; 7911 u32 icc_level; 7912 7913 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7914 if (!desc_buf) 7915 return; 7916 7917 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7918 desc_buf, QUERY_DESC_MAX_SIZE); 7919 if (ret) { 7920 dev_err(hba->dev, 7921 "%s: Failed reading power descriptor ret = %d", 7922 __func__, ret); 7923 goto out; 7924 } 7925 7926 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7927 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7928 7929 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7930 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7931 7932 if (ret) 7933 dev_err(hba->dev, 7934 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7935 __func__, icc_level, ret); 7936 7937 out: 7938 kfree(desc_buf); 7939 } 7940 7941 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7942 { 7943 struct Scsi_Host *shost = sdev->host; 7944 7945 scsi_autopm_get_device(sdev); 7946 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7947 if (sdev->rpm_autosuspend) 7948 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7949 shost->rpm_autosuspend_delay); 7950 scsi_autopm_put_device(sdev); 7951 } 7952 7953 /** 7954 * ufshcd_scsi_add_wlus - Adds required W-LUs 7955 * @hba: per-adapter instance 7956 * 7957 * UFS device specification requires the UFS devices to support 4 well known 7958 * logical units: 7959 * "REPORT_LUNS" (address: 01h) 7960 * "UFS Device" (address: 50h) 7961 * "RPMB" (address: 44h) 7962 * "BOOT" (address: 30h) 7963 * UFS device's power management needs to be controlled by "POWER CONDITION" 7964 * field of SSU (START STOP UNIT) command. But this "power condition" field 7965 * will take effect only when its sent to "UFS device" well known logical unit 7966 * hence we require the scsi_device instance to represent this logical unit in 7967 * order for the UFS host driver to send the SSU command for power management. 7968 * 7969 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 7970 * Block) LU so user space process can control this LU. User space may also 7971 * want to have access to BOOT LU. 7972 * 7973 * This function adds scsi device instances for each of all well known LUs 7974 * (except "REPORT LUNS" LU). 7975 * 7976 * Return: zero on success (all required W-LUs are added successfully), 7977 * non-zero error value on failure (if failed to add any of the required W-LU). 7978 */ 7979 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 7980 { 7981 int ret = 0; 7982 struct scsi_device *sdev_boot, *sdev_rpmb; 7983 7984 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 7985 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 7986 if (IS_ERR(hba->ufs_device_wlun)) { 7987 ret = PTR_ERR(hba->ufs_device_wlun); 7988 hba->ufs_device_wlun = NULL; 7989 goto out; 7990 } 7991 scsi_device_put(hba->ufs_device_wlun); 7992 7993 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 7994 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 7995 if (IS_ERR(sdev_rpmb)) { 7996 ret = PTR_ERR(sdev_rpmb); 7997 goto remove_ufs_device_wlun; 7998 } 7999 ufshcd_blk_pm_runtime_init(sdev_rpmb); 8000 scsi_device_put(sdev_rpmb); 8001 8002 sdev_boot = __scsi_add_device(hba->host, 0, 0, 8003 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 8004 if (IS_ERR(sdev_boot)) { 8005 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 8006 } else { 8007 ufshcd_blk_pm_runtime_init(sdev_boot); 8008 scsi_device_put(sdev_boot); 8009 } 8010 goto out; 8011 8012 remove_ufs_device_wlun: 8013 scsi_remove_device(hba->ufs_device_wlun); 8014 out: 8015 return ret; 8016 } 8017 8018 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 8019 { 8020 struct ufs_dev_info *dev_info = &hba->dev_info; 8021 u8 lun; 8022 u32 d_lu_wb_buf_alloc; 8023 u32 ext_ufs_feature; 8024 8025 if (!ufshcd_is_wb_allowed(hba)) 8026 return; 8027 8028 /* 8029 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 8030 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 8031 * enabled 8032 */ 8033 if (!(dev_info->wspecversion >= 0x310 || 8034 dev_info->wspecversion == 0x220 || 8035 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 8036 goto wb_disabled; 8037 8038 ext_ufs_feature = get_unaligned_be32(desc_buf + 8039 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8040 8041 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 8042 goto wb_disabled; 8043 8044 /* 8045 * WB may be supported but not configured while provisioning. The spec 8046 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 8047 * buffer configured. 8048 */ 8049 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 8050 8051 dev_info->b_presrv_uspc_en = 8052 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 8053 8054 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 8055 if (!get_unaligned_be32(desc_buf + 8056 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 8057 goto wb_disabled; 8058 } else { 8059 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 8060 d_lu_wb_buf_alloc = 0; 8061 ufshcd_read_unit_desc_param(hba, 8062 lun, 8063 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 8064 (u8 *)&d_lu_wb_buf_alloc, 8065 sizeof(d_lu_wb_buf_alloc)); 8066 if (d_lu_wb_buf_alloc) { 8067 dev_info->wb_dedicated_lu = lun; 8068 break; 8069 } 8070 } 8071 8072 if (!d_lu_wb_buf_alloc) 8073 goto wb_disabled; 8074 } 8075 8076 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8077 goto wb_disabled; 8078 8079 return; 8080 8081 wb_disabled: 8082 hba->caps &= ~UFSHCD_CAP_WB_EN; 8083 } 8084 8085 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8086 { 8087 struct ufs_dev_info *dev_info = &hba->dev_info; 8088 u32 ext_ufs_feature; 8089 u8 mask = 0; 8090 8091 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8092 return; 8093 8094 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8095 8096 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8097 mask |= MASK_EE_TOO_LOW_TEMP; 8098 8099 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8100 mask |= MASK_EE_TOO_HIGH_TEMP; 8101 8102 if (mask) { 8103 ufshcd_enable_ee(hba, mask); 8104 ufs_hwmon_probe(hba, mask); 8105 } 8106 } 8107 8108 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8109 { 8110 struct ufs_dev_info *dev_info = &hba->dev_info; 8111 u32 ext_ufs_feature; 8112 u32 ext_iid_en = 0; 8113 int err; 8114 8115 /* Only UFS-4.0 and above may support EXT_IID */ 8116 if (dev_info->wspecversion < 0x400) 8117 goto out; 8118 8119 ext_ufs_feature = get_unaligned_be32(desc_buf + 8120 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8121 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8122 goto out; 8123 8124 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8125 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8126 if (err) 8127 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8128 8129 out: 8130 dev_info->b_ext_iid_en = ext_iid_en; 8131 } 8132 8133 static void ufshcd_set_rtt(struct ufs_hba *hba) 8134 { 8135 struct ufs_dev_info *dev_info = &hba->dev_info; 8136 u32 rtt = 0; 8137 u32 dev_rtt = 0; 8138 int host_rtt_cap = hba->vops && hba->vops->max_num_rtt ? 8139 hba->vops->max_num_rtt : hba->nortt; 8140 8141 /* RTT override makes sense only for UFS-4.0 and above */ 8142 if (dev_info->wspecversion < 0x400) 8143 return; 8144 8145 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8146 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &dev_rtt)) { 8147 dev_err(hba->dev, "failed reading bMaxNumOfRTT\n"); 8148 return; 8149 } 8150 8151 /* do not override if it was already written */ 8152 if (dev_rtt != DEFAULT_MAX_NUM_RTT) 8153 return; 8154 8155 rtt = min_t(int, dev_info->rtt_cap, host_rtt_cap); 8156 8157 if (rtt == dev_rtt) 8158 return; 8159 8160 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8161 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &rtt)) 8162 dev_err(hba->dev, "failed writing bMaxNumOfRTT\n"); 8163 } 8164 8165 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8166 const struct ufs_dev_quirk *fixups) 8167 { 8168 const struct ufs_dev_quirk *f; 8169 struct ufs_dev_info *dev_info = &hba->dev_info; 8170 8171 if (!fixups) 8172 return; 8173 8174 for (f = fixups; f->quirk; f++) { 8175 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8176 f->wmanufacturerid == UFS_ANY_VENDOR) && 8177 ((dev_info->model && 8178 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8179 !strcmp(f->model, UFS_ANY_MODEL))) 8180 hba->dev_quirks |= f->quirk; 8181 } 8182 } 8183 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8184 8185 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8186 { 8187 /* fix by general quirk table */ 8188 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8189 8190 /* allow vendors to fix quirks */ 8191 ufshcd_vops_fixup_dev_quirks(hba); 8192 } 8193 8194 static void ufshcd_update_rtc(struct ufs_hba *hba) 8195 { 8196 struct timespec64 ts64; 8197 int err; 8198 u32 val; 8199 8200 ktime_get_real_ts64(&ts64); 8201 8202 if (ts64.tv_sec < hba->dev_info.rtc_time_baseline) { 8203 dev_warn_once(hba->dev, "%s: Current time precedes previous setting!\n", __func__); 8204 return; 8205 } 8206 8207 /* 8208 * The Absolute RTC mode has a 136-year limit, spanning from 2010 to 2146. If a time beyond 8209 * 2146 is required, it is recommended to choose the relative RTC mode. 8210 */ 8211 val = ts64.tv_sec - hba->dev_info.rtc_time_baseline; 8212 8213 /* Skip update RTC if RPM state is not RPM_ACTIVE */ 8214 if (ufshcd_rpm_get_if_active(hba) <= 0) 8215 return; 8216 8217 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_SECONDS_PASSED, 8218 0, 0, &val); 8219 ufshcd_rpm_put_sync(hba); 8220 8221 if (err) 8222 dev_err(hba->dev, "%s: Failed to update rtc %d\n", __func__, err); 8223 else if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 8224 hba->dev_info.rtc_time_baseline = ts64.tv_sec; 8225 } 8226 8227 static void ufshcd_rtc_work(struct work_struct *work) 8228 { 8229 struct ufs_hba *hba; 8230 8231 hba = container_of(to_delayed_work(work), struct ufs_hba, ufs_rtc_update_work); 8232 8233 /* Update RTC only when there are no requests in progress and UFSHCI is operational */ 8234 if (!ufshcd_is_ufs_dev_busy(hba) && hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) 8235 ufshcd_update_rtc(hba); 8236 8237 if (ufshcd_is_ufs_dev_active(hba) && hba->dev_info.rtc_update_period) 8238 schedule_delayed_work(&hba->ufs_rtc_update_work, 8239 msecs_to_jiffies(hba->dev_info.rtc_update_period)); 8240 } 8241 8242 static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf) 8243 { 8244 u16 periodic_rtc_update = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_FRQ_RTC]); 8245 struct ufs_dev_info *dev_info = &hba->dev_info; 8246 8247 if (periodic_rtc_update & UFS_RTC_TIME_BASELINE) { 8248 dev_info->rtc_type = UFS_RTC_ABSOLUTE; 8249 8250 /* 8251 * The concept of measuring time in Linux as the number of seconds elapsed since 8252 * 00:00:00 UTC on January 1, 1970, and UFS ABS RTC is elapsed from January 1st 8253 * 2010 00:00, here we need to adjust ABS baseline. 8254 */ 8255 dev_info->rtc_time_baseline = mktime64(2010, 1, 1, 0, 0, 0) - 8256 mktime64(1970, 1, 1, 0, 0, 0); 8257 } else { 8258 dev_info->rtc_type = UFS_RTC_RELATIVE; 8259 dev_info->rtc_time_baseline = 0; 8260 } 8261 8262 /* 8263 * We ignore TIME_PERIOD defined in wPeriodicRTCUpdate because Spec does not clearly state 8264 * how to calculate the specific update period for each time unit. And we disable periodic 8265 * RTC update work, let user configure by sysfs node according to specific circumstance. 8266 */ 8267 dev_info->rtc_update_period = 0; 8268 } 8269 8270 static int ufs_get_device_desc(struct ufs_hba *hba) 8271 { 8272 int err; 8273 u8 model_index; 8274 u8 *desc_buf; 8275 struct ufs_dev_info *dev_info = &hba->dev_info; 8276 8277 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8278 if (!desc_buf) { 8279 err = -ENOMEM; 8280 goto out; 8281 } 8282 8283 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8284 QUERY_DESC_MAX_SIZE); 8285 if (err) { 8286 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8287 __func__, err); 8288 goto out; 8289 } 8290 8291 /* 8292 * getting vendor (manufacturerID) and Bank Index in big endian 8293 * format 8294 */ 8295 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8296 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8297 8298 /* getting Specification Version in big endian format */ 8299 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8300 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8301 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8302 8303 dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP]; 8304 8305 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8306 8307 err = ufshcd_read_string_desc(hba, model_index, 8308 &dev_info->model, SD_ASCII_STD); 8309 if (err < 0) { 8310 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8311 __func__, err); 8312 goto out; 8313 } 8314 8315 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8316 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8317 8318 ufs_fixup_device_setup(hba); 8319 8320 ufshcd_wb_probe(hba, desc_buf); 8321 8322 ufshcd_temp_notif_probe(hba, desc_buf); 8323 8324 ufs_init_rtc(hba, desc_buf); 8325 8326 if (hba->ext_iid_sup) 8327 ufshcd_ext_iid_probe(hba, desc_buf); 8328 8329 /* 8330 * ufshcd_read_string_desc returns size of the string 8331 * reset the error value 8332 */ 8333 err = 0; 8334 8335 out: 8336 kfree(desc_buf); 8337 return err; 8338 } 8339 8340 static void ufs_put_device_desc(struct ufs_hba *hba) 8341 { 8342 struct ufs_dev_info *dev_info = &hba->dev_info; 8343 8344 kfree(dev_info->model); 8345 dev_info->model = NULL; 8346 } 8347 8348 /** 8349 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8350 * less than device PA_TACTIVATE time. 8351 * @hba: per-adapter instance 8352 * 8353 * Some UFS devices require host PA_TACTIVATE to be lower than device 8354 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8355 * for such devices. 8356 * 8357 * Return: zero on success, non-zero error value on failure. 8358 */ 8359 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8360 { 8361 int ret = 0; 8362 u32 granularity, peer_granularity; 8363 u32 pa_tactivate, peer_pa_tactivate; 8364 u32 pa_tactivate_us, peer_pa_tactivate_us; 8365 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8366 8367 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8368 &granularity); 8369 if (ret) 8370 goto out; 8371 8372 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8373 &peer_granularity); 8374 if (ret) 8375 goto out; 8376 8377 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8378 (granularity > PA_GRANULARITY_MAX_VAL)) { 8379 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8380 __func__, granularity); 8381 return -EINVAL; 8382 } 8383 8384 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8385 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8386 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8387 __func__, peer_granularity); 8388 return -EINVAL; 8389 } 8390 8391 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8392 if (ret) 8393 goto out; 8394 8395 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8396 &peer_pa_tactivate); 8397 if (ret) 8398 goto out; 8399 8400 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8401 peer_pa_tactivate_us = peer_pa_tactivate * 8402 gran_to_us_table[peer_granularity - 1]; 8403 8404 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8405 u32 new_peer_pa_tactivate; 8406 8407 new_peer_pa_tactivate = pa_tactivate_us / 8408 gran_to_us_table[peer_granularity - 1]; 8409 new_peer_pa_tactivate++; 8410 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8411 new_peer_pa_tactivate); 8412 } 8413 8414 out: 8415 return ret; 8416 } 8417 8418 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8419 { 8420 ufshcd_vops_apply_dev_quirks(hba); 8421 8422 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8423 /* set 1ms timeout for PA_TACTIVATE */ 8424 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8425 8426 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8427 ufshcd_quirk_tune_host_pa_tactivate(hba); 8428 } 8429 8430 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8431 { 8432 hba->ufs_stats.hibern8_exit_cnt = 0; 8433 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8434 hba->req_abort_count = 0; 8435 } 8436 8437 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8438 { 8439 int err; 8440 u8 *desc_buf; 8441 8442 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8443 if (!desc_buf) { 8444 err = -ENOMEM; 8445 goto out; 8446 } 8447 8448 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8449 desc_buf, QUERY_DESC_MAX_SIZE); 8450 if (err) { 8451 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8452 __func__, err); 8453 goto out; 8454 } 8455 8456 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8457 hba->dev_info.max_lu_supported = 32; 8458 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8459 hba->dev_info.max_lu_supported = 8; 8460 8461 out: 8462 kfree(desc_buf); 8463 return err; 8464 } 8465 8466 struct ufs_ref_clk { 8467 unsigned long freq_hz; 8468 enum ufs_ref_clk_freq val; 8469 }; 8470 8471 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8472 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8473 {26000000, REF_CLK_FREQ_26_MHZ}, 8474 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8475 {52000000, REF_CLK_FREQ_52_MHZ}, 8476 {0, REF_CLK_FREQ_INVAL}, 8477 }; 8478 8479 static enum ufs_ref_clk_freq 8480 ufs_get_bref_clk_from_hz(unsigned long freq) 8481 { 8482 int i; 8483 8484 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8485 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8486 return ufs_ref_clk_freqs[i].val; 8487 8488 return REF_CLK_FREQ_INVAL; 8489 } 8490 8491 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8492 { 8493 unsigned long freq; 8494 8495 freq = clk_get_rate(refclk); 8496 8497 hba->dev_ref_clk_freq = 8498 ufs_get_bref_clk_from_hz(freq); 8499 8500 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8501 dev_err(hba->dev, 8502 "invalid ref_clk setting = %ld\n", freq); 8503 } 8504 8505 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8506 { 8507 int err; 8508 u32 ref_clk; 8509 u32 freq = hba->dev_ref_clk_freq; 8510 8511 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8512 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8513 8514 if (err) { 8515 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8516 err); 8517 goto out; 8518 } 8519 8520 if (ref_clk == freq) 8521 goto out; /* nothing to update */ 8522 8523 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8524 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8525 8526 if (err) { 8527 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8528 ufs_ref_clk_freqs[freq].freq_hz); 8529 goto out; 8530 } 8531 8532 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8533 ufs_ref_clk_freqs[freq].freq_hz); 8534 8535 out: 8536 return err; 8537 } 8538 8539 static int ufshcd_device_params_init(struct ufs_hba *hba) 8540 { 8541 bool flag; 8542 int ret; 8543 8544 /* Init UFS geometry descriptor related parameters */ 8545 ret = ufshcd_device_geo_params_init(hba); 8546 if (ret) 8547 goto out; 8548 8549 /* Check and apply UFS device quirks */ 8550 ret = ufs_get_device_desc(hba); 8551 if (ret) { 8552 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8553 __func__, ret); 8554 goto out; 8555 } 8556 8557 ufshcd_set_rtt(hba); 8558 8559 ufshcd_get_ref_clk_gating_wait(hba); 8560 8561 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8562 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8563 hba->dev_info.f_power_on_wp_en = flag; 8564 8565 /* Probe maximum power mode co-supported by both UFS host and device */ 8566 if (ufshcd_get_max_pwr_mode(hba)) 8567 dev_err(hba->dev, 8568 "%s: Failed getting max supported power mode\n", 8569 __func__); 8570 out: 8571 return ret; 8572 } 8573 8574 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8575 { 8576 int err; 8577 struct ufs_query_req *request = NULL; 8578 struct ufs_query_res *response = NULL; 8579 struct ufs_dev_info *dev_info = &hba->dev_info; 8580 struct utp_upiu_query_v4_0 *upiu_data; 8581 8582 if (dev_info->wspecversion < 0x400) 8583 return; 8584 8585 ufshcd_dev_man_lock(hba); 8586 8587 ufshcd_init_query(hba, &request, &response, 8588 UPIU_QUERY_OPCODE_WRITE_ATTR, 8589 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8590 8591 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8592 8593 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8594 8595 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8596 8597 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8598 8599 if (err) 8600 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8601 __func__, err); 8602 8603 ufshcd_dev_man_unlock(hba); 8604 } 8605 8606 /** 8607 * ufshcd_add_lus - probe and add UFS logical units 8608 * @hba: per-adapter instance 8609 * 8610 * Return: 0 upon success; < 0 upon failure. 8611 */ 8612 static int ufshcd_add_lus(struct ufs_hba *hba) 8613 { 8614 int ret; 8615 8616 /* Add required well known logical units to scsi mid layer */ 8617 ret = ufshcd_scsi_add_wlus(hba); 8618 if (ret) 8619 goto out; 8620 8621 /* Initialize devfreq after UFS device is detected */ 8622 if (ufshcd_is_clkscaling_supported(hba)) { 8623 memcpy(&hba->clk_scaling.saved_pwr_info, 8624 &hba->pwr_info, 8625 sizeof(struct ufs_pa_layer_attr)); 8626 hba->clk_scaling.is_allowed = true; 8627 8628 ret = ufshcd_devfreq_init(hba); 8629 if (ret) 8630 goto out; 8631 8632 hba->clk_scaling.is_enabled = true; 8633 ufshcd_init_clk_scaling_sysfs(hba); 8634 } 8635 8636 ufs_bsg_probe(hba); 8637 scsi_scan_host(hba->host); 8638 8639 out: 8640 return ret; 8641 } 8642 8643 /* SDB - Single Doorbell */ 8644 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8645 { 8646 size_t ucdl_size, utrdl_size; 8647 8648 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8649 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8650 hba->ucdl_dma_addr); 8651 8652 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8653 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8654 hba->utrdl_dma_addr); 8655 8656 devm_kfree(hba->dev, hba->lrb); 8657 } 8658 8659 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8660 { 8661 int ret; 8662 int old_nutrs = hba->nutrs; 8663 8664 ret = ufshcd_mcq_decide_queue_depth(hba); 8665 if (ret < 0) 8666 return ret; 8667 8668 hba->nutrs = ret; 8669 ret = ufshcd_mcq_init(hba); 8670 if (ret) 8671 goto err; 8672 8673 /* 8674 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8675 * Number of supported tags in MCQ mode may be larger than SDB mode. 8676 */ 8677 if (hba->nutrs != old_nutrs) { 8678 ufshcd_release_sdb_queue(hba, old_nutrs); 8679 ret = ufshcd_memory_alloc(hba); 8680 if (ret) 8681 goto err; 8682 ufshcd_host_memory_configure(hba); 8683 } 8684 8685 ret = ufshcd_mcq_memory_alloc(hba); 8686 if (ret) 8687 goto err; 8688 8689 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8690 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8691 8692 return 0; 8693 err: 8694 hba->nutrs = old_nutrs; 8695 return ret; 8696 } 8697 8698 static void ufshcd_config_mcq(struct ufs_hba *hba) 8699 { 8700 int ret; 8701 u32 intrs; 8702 8703 ret = ufshcd_mcq_vops_config_esi(hba); 8704 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8705 8706 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8707 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8708 intrs &= ~MCQ_CQ_EVENT_STATUS; 8709 ufshcd_enable_intr(hba, intrs); 8710 ufshcd_mcq_make_queues_operational(hba); 8711 ufshcd_mcq_config_mac(hba, hba->nutrs); 8712 8713 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8714 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8715 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8716 hba->nutrs); 8717 } 8718 8719 static int ufshcd_post_device_init(struct ufs_hba *hba) 8720 { 8721 int ret; 8722 8723 ufshcd_tune_unipro_params(hba); 8724 8725 /* UFS device is also active now */ 8726 ufshcd_set_ufs_dev_active(hba); 8727 ufshcd_force_reset_auto_bkops(hba); 8728 8729 ufshcd_set_timestamp_attr(hba); 8730 schedule_delayed_work(&hba->ufs_rtc_update_work, 8731 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 8732 8733 if (!hba->max_pwr_info.is_valid) 8734 return 0; 8735 8736 /* 8737 * Set the right value to bRefClkFreq before attempting to 8738 * switch to HS gears. 8739 */ 8740 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8741 ufshcd_set_dev_ref_clk(hba); 8742 /* Gear up to HS gear. */ 8743 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8744 if (ret) { 8745 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8746 __func__, ret); 8747 return ret; 8748 } 8749 8750 return 0; 8751 } 8752 8753 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8754 { 8755 int ret; 8756 8757 WARN_ON_ONCE(!hba->scsi_host_added); 8758 8759 hba->ufshcd_state = UFSHCD_STATE_RESET; 8760 8761 ret = ufshcd_link_startup(hba); 8762 if (ret) 8763 return ret; 8764 8765 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8766 return ret; 8767 8768 /* Debug counters initialization */ 8769 ufshcd_clear_dbg_ufs_stats(hba); 8770 8771 /* UniPro link is active now */ 8772 ufshcd_set_link_active(hba); 8773 8774 /* Reconfigure MCQ upon reset */ 8775 if (hba->mcq_enabled && !init_dev_params) { 8776 ufshcd_config_mcq(hba); 8777 ufshcd_mcq_enable(hba); 8778 } 8779 8780 /* Verify device initialization by sending NOP OUT UPIU */ 8781 ret = ufshcd_verify_dev_init(hba); 8782 if (ret) 8783 return ret; 8784 8785 /* Initiate UFS initialization, and waiting until completion */ 8786 ret = ufshcd_complete_dev_init(hba); 8787 if (ret) 8788 return ret; 8789 8790 /* 8791 * Initialize UFS device parameters used by driver, these 8792 * parameters are associated with UFS descriptors. 8793 */ 8794 if (init_dev_params) { 8795 ret = ufshcd_device_params_init(hba); 8796 if (ret) 8797 return ret; 8798 if (is_mcq_supported(hba) && 8799 hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) { 8800 ufshcd_config_mcq(hba); 8801 ufshcd_mcq_enable(hba); 8802 } 8803 } 8804 8805 return ufshcd_post_device_init(hba); 8806 } 8807 8808 /** 8809 * ufshcd_probe_hba - probe hba to detect device and initialize it 8810 * @hba: per-adapter instance 8811 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8812 * 8813 * Execute link-startup and verify device initialization 8814 * 8815 * Return: 0 upon success; < 0 upon failure. 8816 */ 8817 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8818 { 8819 int ret; 8820 8821 if (!hba->pm_op_in_progress && 8822 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8823 /* Reset the device and controller before doing reinit */ 8824 ufshcd_device_reset(hba); 8825 ufs_put_device_desc(hba); 8826 ufshcd_hba_stop(hba); 8827 ufshcd_vops_reinit_notify(hba); 8828 ret = ufshcd_hba_enable(hba); 8829 if (ret) { 8830 dev_err(hba->dev, "Host controller enable failed\n"); 8831 ufshcd_print_evt_hist(hba); 8832 ufshcd_print_host_state(hba); 8833 return ret; 8834 } 8835 8836 /* Reinit the device */ 8837 ret = ufshcd_device_init(hba, init_dev_params); 8838 if (ret) 8839 return ret; 8840 } 8841 8842 ufshcd_print_pwr_info(hba); 8843 8844 /* 8845 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8846 * and for removable UFS card as well, hence always set the parameter. 8847 * Note: Error handler may issue the device reset hence resetting 8848 * bActiveICCLevel as well so it is always safe to set this here. 8849 */ 8850 ufshcd_set_active_icc_lvl(hba); 8851 8852 /* Enable UFS Write Booster if supported */ 8853 ufshcd_configure_wb(hba); 8854 8855 if (hba->ee_usr_mask) 8856 ufshcd_write_ee_control(hba); 8857 ufshcd_configure_auto_hibern8(hba); 8858 8859 return 0; 8860 } 8861 8862 /** 8863 * ufshcd_async_scan - asynchronous execution for probing hba 8864 * @data: data pointer to pass to this function 8865 * @cookie: cookie data 8866 */ 8867 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8868 { 8869 struct ufs_hba *hba = (struct ufs_hba *)data; 8870 ktime_t probe_start; 8871 int ret; 8872 8873 down(&hba->host_sem); 8874 /* Initialize hba, detect and initialize UFS device */ 8875 probe_start = ktime_get(); 8876 ret = ufshcd_probe_hba(hba, true); 8877 ufshcd_process_probe_result(hba, probe_start, ret); 8878 up(&hba->host_sem); 8879 if (ret) 8880 goto out; 8881 8882 /* Probe and add UFS logical units */ 8883 ret = ufshcd_add_lus(hba); 8884 8885 out: 8886 pm_runtime_put_sync(hba->dev); 8887 8888 if (ret) 8889 dev_err(hba->dev, "%s failed: %d\n", __func__, ret); 8890 } 8891 8892 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8893 { 8894 struct ufs_hba *hba = shost_priv(scmd->device->host); 8895 8896 if (!hba->system_suspending) { 8897 /* Activate the error handler in the SCSI core. */ 8898 return SCSI_EH_NOT_HANDLED; 8899 } 8900 8901 /* 8902 * If we get here we know that no TMFs are outstanding and also that 8903 * the only pending command is a START STOP UNIT command. Handle the 8904 * timeout of that command directly to prevent a deadlock between 8905 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8906 */ 8907 ufshcd_link_recovery(hba); 8908 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8909 __func__, hba->outstanding_tasks); 8910 8911 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8912 } 8913 8914 static const struct attribute_group *ufshcd_driver_groups[] = { 8915 &ufs_sysfs_unit_descriptor_group, 8916 &ufs_sysfs_lun_attributes_group, 8917 NULL, 8918 }; 8919 8920 static struct ufs_hba_variant_params ufs_hba_vps = { 8921 .hba_enable_delay_us = 1000, 8922 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8923 .devfreq_profile.polling_ms = 100, 8924 .devfreq_profile.target = ufshcd_devfreq_target, 8925 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8926 .ondemand_data.upthreshold = 70, 8927 .ondemand_data.downdifferential = 5, 8928 }; 8929 8930 static const struct scsi_host_template ufshcd_driver_template = { 8931 .module = THIS_MODULE, 8932 .name = UFSHCD, 8933 .proc_name = UFSHCD, 8934 .map_queues = ufshcd_map_queues, 8935 .queuecommand = ufshcd_queuecommand, 8936 .mq_poll = ufshcd_poll, 8937 .slave_alloc = ufshcd_slave_alloc, 8938 .device_configure = ufshcd_device_configure, 8939 .slave_destroy = ufshcd_slave_destroy, 8940 .change_queue_depth = ufshcd_change_queue_depth, 8941 .eh_abort_handler = ufshcd_abort, 8942 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8943 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8944 .eh_timed_out = ufshcd_eh_timed_out, 8945 .this_id = -1, 8946 .sg_tablesize = SG_ALL, 8947 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8948 .max_sectors = SZ_1M / SECTOR_SIZE, 8949 .max_host_blocked = 1, 8950 .track_queue_depth = 1, 8951 .skip_settle_delay = 1, 8952 .sdev_groups = ufshcd_driver_groups, 8953 }; 8954 8955 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8956 int ua) 8957 { 8958 int ret; 8959 8960 if (!vreg) 8961 return 0; 8962 8963 /* 8964 * "set_load" operation shall be required on those regulators 8965 * which specifically configured current limitation. Otherwise 8966 * zero max_uA may cause unexpected behavior when regulator is 8967 * enabled or set as high power mode. 8968 */ 8969 if (!vreg->max_uA) 8970 return 0; 8971 8972 ret = regulator_set_load(vreg->reg, ua); 8973 if (ret < 0) { 8974 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 8975 __func__, vreg->name, ua, ret); 8976 } 8977 8978 return ret; 8979 } 8980 8981 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 8982 struct ufs_vreg *vreg) 8983 { 8984 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 8985 } 8986 8987 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 8988 struct ufs_vreg *vreg) 8989 { 8990 if (!vreg) 8991 return 0; 8992 8993 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 8994 } 8995 8996 static int ufshcd_config_vreg(struct device *dev, 8997 struct ufs_vreg *vreg, bool on) 8998 { 8999 if (regulator_count_voltages(vreg->reg) <= 0) 9000 return 0; 9001 9002 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 9003 } 9004 9005 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 9006 { 9007 int ret = 0; 9008 9009 if (!vreg || vreg->enabled) 9010 goto out; 9011 9012 ret = ufshcd_config_vreg(dev, vreg, true); 9013 if (!ret) 9014 ret = regulator_enable(vreg->reg); 9015 9016 if (!ret) 9017 vreg->enabled = true; 9018 else 9019 dev_err(dev, "%s: %s enable failed, err=%d\n", 9020 __func__, vreg->name, ret); 9021 out: 9022 return ret; 9023 } 9024 9025 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 9026 { 9027 int ret = 0; 9028 9029 if (!vreg || !vreg->enabled || vreg->always_on) 9030 goto out; 9031 9032 ret = regulator_disable(vreg->reg); 9033 9034 if (!ret) { 9035 /* ignore errors on applying disable config */ 9036 ufshcd_config_vreg(dev, vreg, false); 9037 vreg->enabled = false; 9038 } else { 9039 dev_err(dev, "%s: %s disable failed, err=%d\n", 9040 __func__, vreg->name, ret); 9041 } 9042 out: 9043 return ret; 9044 } 9045 9046 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 9047 { 9048 int ret = 0; 9049 struct device *dev = hba->dev; 9050 struct ufs_vreg_info *info = &hba->vreg_info; 9051 9052 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 9053 if (ret) 9054 goto out; 9055 9056 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 9057 if (ret) 9058 goto out; 9059 9060 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 9061 9062 out: 9063 if (ret) { 9064 ufshcd_toggle_vreg(dev, info->vccq2, false); 9065 ufshcd_toggle_vreg(dev, info->vccq, false); 9066 ufshcd_toggle_vreg(dev, info->vcc, false); 9067 } 9068 return ret; 9069 } 9070 9071 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9072 { 9073 struct ufs_vreg_info *info = &hba->vreg_info; 9074 9075 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9076 } 9077 9078 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9079 { 9080 int ret = 0; 9081 9082 if (!vreg) 9083 goto out; 9084 9085 vreg->reg = devm_regulator_get(dev, vreg->name); 9086 if (IS_ERR(vreg->reg)) { 9087 ret = PTR_ERR(vreg->reg); 9088 dev_err(dev, "%s: %s get failed, err=%d\n", 9089 __func__, vreg->name, ret); 9090 } 9091 out: 9092 return ret; 9093 } 9094 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9095 9096 static int ufshcd_init_vreg(struct ufs_hba *hba) 9097 { 9098 int ret = 0; 9099 struct device *dev = hba->dev; 9100 struct ufs_vreg_info *info = &hba->vreg_info; 9101 9102 ret = ufshcd_get_vreg(dev, info->vcc); 9103 if (ret) 9104 goto out; 9105 9106 ret = ufshcd_get_vreg(dev, info->vccq); 9107 if (!ret) 9108 ret = ufshcd_get_vreg(dev, info->vccq2); 9109 out: 9110 return ret; 9111 } 9112 9113 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9114 { 9115 struct ufs_vreg_info *info = &hba->vreg_info; 9116 9117 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9118 } 9119 9120 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9121 { 9122 int ret = 0; 9123 struct ufs_clk_info *clki; 9124 struct list_head *head = &hba->clk_list_head; 9125 unsigned long flags; 9126 ktime_t start = ktime_get(); 9127 bool clk_state_changed = false; 9128 9129 if (list_empty(head)) 9130 goto out; 9131 9132 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9133 if (ret) 9134 return ret; 9135 9136 list_for_each_entry(clki, head, list) { 9137 if (!IS_ERR_OR_NULL(clki->clk)) { 9138 /* 9139 * Don't disable clocks which are needed 9140 * to keep the link active. 9141 */ 9142 if (ufshcd_is_link_active(hba) && 9143 clki->keep_link_active) 9144 continue; 9145 9146 clk_state_changed = on ^ clki->enabled; 9147 if (on && !clki->enabled) { 9148 ret = clk_prepare_enable(clki->clk); 9149 if (ret) { 9150 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9151 __func__, clki->name, ret); 9152 goto out; 9153 } 9154 } else if (!on && clki->enabled) { 9155 clk_disable_unprepare(clki->clk); 9156 } 9157 clki->enabled = on; 9158 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9159 clki->name, on ? "en" : "dis"); 9160 } 9161 } 9162 9163 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9164 if (ret) 9165 return ret; 9166 9167 if (!ufshcd_is_clkscaling_supported(hba)) 9168 ufshcd_pm_qos_update(hba, on); 9169 out: 9170 if (ret) { 9171 list_for_each_entry(clki, head, list) { 9172 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9173 clk_disable_unprepare(clki->clk); 9174 } 9175 } else if (!ret && on) { 9176 spin_lock_irqsave(hba->host->host_lock, flags); 9177 hba->clk_gating.state = CLKS_ON; 9178 trace_ufshcd_clk_gating(dev_name(hba->dev), 9179 hba->clk_gating.state); 9180 spin_unlock_irqrestore(hba->host->host_lock, flags); 9181 } 9182 9183 if (clk_state_changed) 9184 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9185 (on ? "on" : "off"), 9186 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9187 return ret; 9188 } 9189 9190 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9191 { 9192 u32 freq; 9193 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9194 9195 if (ret) { 9196 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9197 return REF_CLK_FREQ_INVAL; 9198 } 9199 9200 return ufs_get_bref_clk_from_hz(freq); 9201 } 9202 9203 static int ufshcd_init_clocks(struct ufs_hba *hba) 9204 { 9205 int ret = 0; 9206 struct ufs_clk_info *clki; 9207 struct device *dev = hba->dev; 9208 struct list_head *head = &hba->clk_list_head; 9209 9210 if (list_empty(head)) 9211 goto out; 9212 9213 list_for_each_entry(clki, head, list) { 9214 if (!clki->name) 9215 continue; 9216 9217 clki->clk = devm_clk_get(dev, clki->name); 9218 if (IS_ERR(clki->clk)) { 9219 ret = PTR_ERR(clki->clk); 9220 dev_err(dev, "%s: %s clk get failed, %d\n", 9221 __func__, clki->name, ret); 9222 goto out; 9223 } 9224 9225 /* 9226 * Parse device ref clk freq as per device tree "ref_clk". 9227 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9228 * in ufshcd_alloc_host(). 9229 */ 9230 if (!strcmp(clki->name, "ref_clk")) 9231 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9232 9233 if (clki->max_freq) { 9234 ret = clk_set_rate(clki->clk, clki->max_freq); 9235 if (ret) { 9236 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9237 __func__, clki->name, 9238 clki->max_freq, ret); 9239 goto out; 9240 } 9241 clki->curr_freq = clki->max_freq; 9242 } 9243 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9244 clki->name, clk_get_rate(clki->clk)); 9245 } 9246 9247 /* Set Max. frequency for all clocks */ 9248 if (hba->use_pm_opp) { 9249 ret = ufshcd_opp_set_rate(hba, ULONG_MAX); 9250 if (ret) { 9251 dev_err(hba->dev, "%s: failed to set OPP: %d", __func__, 9252 ret); 9253 goto out; 9254 } 9255 } 9256 9257 out: 9258 return ret; 9259 } 9260 9261 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9262 { 9263 int err = 0; 9264 9265 if (!hba->vops) 9266 goto out; 9267 9268 err = ufshcd_vops_init(hba); 9269 if (err) 9270 dev_err_probe(hba->dev, err, 9271 "%s: variant %s init failed with err %d\n", 9272 __func__, ufshcd_get_var_name(hba), err); 9273 out: 9274 return err; 9275 } 9276 9277 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9278 { 9279 if (!hba->vops) 9280 return; 9281 9282 ufshcd_vops_exit(hba); 9283 } 9284 9285 static int ufshcd_hba_init(struct ufs_hba *hba) 9286 { 9287 int err; 9288 9289 /* 9290 * Handle host controller power separately from the UFS device power 9291 * rails as it will help controlling the UFS host controller power 9292 * collapse easily which is different than UFS device power collapse. 9293 * Also, enable the host controller power before we go ahead with rest 9294 * of the initialization here. 9295 */ 9296 err = ufshcd_init_hba_vreg(hba); 9297 if (err) 9298 goto out; 9299 9300 err = ufshcd_setup_hba_vreg(hba, true); 9301 if (err) 9302 goto out; 9303 9304 err = ufshcd_init_clocks(hba); 9305 if (err) 9306 goto out_disable_hba_vreg; 9307 9308 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9309 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9310 9311 err = ufshcd_setup_clocks(hba, true); 9312 if (err) 9313 goto out_disable_hba_vreg; 9314 9315 err = ufshcd_init_vreg(hba); 9316 if (err) 9317 goto out_disable_clks; 9318 9319 err = ufshcd_setup_vreg(hba, true); 9320 if (err) 9321 goto out_disable_clks; 9322 9323 err = ufshcd_variant_hba_init(hba); 9324 if (err) 9325 goto out_disable_vreg; 9326 9327 ufs_debugfs_hba_init(hba); 9328 ufs_fault_inject_hba_init(hba); 9329 9330 hba->is_powered = true; 9331 goto out; 9332 9333 out_disable_vreg: 9334 ufshcd_setup_vreg(hba, false); 9335 out_disable_clks: 9336 ufshcd_setup_clocks(hba, false); 9337 out_disable_hba_vreg: 9338 ufshcd_setup_hba_vreg(hba, false); 9339 out: 9340 return err; 9341 } 9342 9343 static void ufshcd_hba_exit(struct ufs_hba *hba) 9344 { 9345 if (hba->is_powered) { 9346 ufshcd_pm_qos_exit(hba); 9347 ufshcd_exit_clk_scaling(hba); 9348 ufshcd_exit_clk_gating(hba); 9349 if (hba->eh_wq) 9350 destroy_workqueue(hba->eh_wq); 9351 ufs_debugfs_hba_exit(hba); 9352 ufshcd_variant_hba_exit(hba); 9353 ufshcd_setup_vreg(hba, false); 9354 ufshcd_setup_clocks(hba, false); 9355 ufshcd_setup_hba_vreg(hba, false); 9356 hba->is_powered = false; 9357 ufs_put_device_desc(hba); 9358 } 9359 } 9360 9361 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9362 enum ufs_dev_pwr_mode pwr_mode, 9363 struct scsi_sense_hdr *sshdr) 9364 { 9365 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9366 struct scsi_failure failure_defs[] = { 9367 { 9368 .allowed = 2, 9369 .result = SCMD_FAILURE_RESULT_ANY, 9370 }, 9371 }; 9372 struct scsi_failures failures = { 9373 .failure_definitions = failure_defs, 9374 }; 9375 const struct scsi_exec_args args = { 9376 .failures = &failures, 9377 .sshdr = sshdr, 9378 .req_flags = BLK_MQ_REQ_PM, 9379 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9380 }; 9381 9382 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9383 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9384 &args); 9385 } 9386 9387 /** 9388 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9389 * power mode 9390 * @hba: per adapter instance 9391 * @pwr_mode: device power mode to set 9392 * 9393 * Return: 0 if requested power mode is set successfully; 9394 * < 0 if failed to set the requested power mode. 9395 */ 9396 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9397 enum ufs_dev_pwr_mode pwr_mode) 9398 { 9399 struct scsi_sense_hdr sshdr; 9400 struct scsi_device *sdp; 9401 unsigned long flags; 9402 int ret; 9403 9404 spin_lock_irqsave(hba->host->host_lock, flags); 9405 sdp = hba->ufs_device_wlun; 9406 if (sdp && scsi_device_online(sdp)) 9407 ret = scsi_device_get(sdp); 9408 else 9409 ret = -ENODEV; 9410 spin_unlock_irqrestore(hba->host->host_lock, flags); 9411 9412 if (ret) 9413 return ret; 9414 9415 /* 9416 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9417 * handling, which would wait for host to be resumed. Since we know 9418 * we are functional while we are here, skip host resume in error 9419 * handling context. 9420 */ 9421 hba->host->eh_noresume = 1; 9422 9423 /* 9424 * Current function would be generally called from the power management 9425 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9426 * already suspended childs. 9427 */ 9428 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9429 if (ret) { 9430 sdev_printk(KERN_WARNING, sdp, 9431 "START_STOP failed for power mode: %d, result %x\n", 9432 pwr_mode, ret); 9433 if (ret > 0) { 9434 if (scsi_sense_valid(&sshdr)) 9435 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9436 ret = -EIO; 9437 } 9438 } else { 9439 hba->curr_dev_pwr_mode = pwr_mode; 9440 } 9441 9442 scsi_device_put(sdp); 9443 hba->host->eh_noresume = 0; 9444 return ret; 9445 } 9446 9447 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9448 enum uic_link_state req_link_state, 9449 bool check_for_bkops) 9450 { 9451 int ret = 0; 9452 9453 if (req_link_state == hba->uic_link_state) 9454 return 0; 9455 9456 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9457 ret = ufshcd_uic_hibern8_enter(hba); 9458 if (!ret) { 9459 ufshcd_set_link_hibern8(hba); 9460 } else { 9461 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9462 __func__, ret); 9463 goto out; 9464 } 9465 } 9466 /* 9467 * If autobkops is enabled, link can't be turned off because 9468 * turning off the link would also turn off the device, except in the 9469 * case of DeepSleep where the device is expected to remain powered. 9470 */ 9471 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9472 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9473 /* 9474 * Let's make sure that link is in low power mode, we are doing 9475 * this currently by putting the link in Hibern8. Otherway to 9476 * put the link in low power mode is to send the DME end point 9477 * to device and then send the DME reset command to local 9478 * unipro. But putting the link in hibern8 is much faster. 9479 * 9480 * Note also that putting the link in Hibern8 is a requirement 9481 * for entering DeepSleep. 9482 */ 9483 ret = ufshcd_uic_hibern8_enter(hba); 9484 if (ret) { 9485 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9486 __func__, ret); 9487 goto out; 9488 } 9489 /* 9490 * Change controller state to "reset state" which 9491 * should also put the link in off/reset state 9492 */ 9493 ufshcd_hba_stop(hba); 9494 /* 9495 * TODO: Check if we need any delay to make sure that 9496 * controller is reset 9497 */ 9498 ufshcd_set_link_off(hba); 9499 } 9500 9501 out: 9502 return ret; 9503 } 9504 9505 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9506 { 9507 bool vcc_off = false; 9508 9509 /* 9510 * It seems some UFS devices may keep drawing more than sleep current 9511 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9512 * To avoid this situation, add 2ms delay before putting these UFS 9513 * rails in LPM mode. 9514 */ 9515 if (!ufshcd_is_link_active(hba) && 9516 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9517 usleep_range(2000, 2100); 9518 9519 /* 9520 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9521 * power. 9522 * 9523 * If UFS device and link is in OFF state, all power supplies (VCC, 9524 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9525 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9526 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9527 * 9528 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9529 * in low power state which would save some power. 9530 * 9531 * If Write Booster is enabled and the device needs to flush the WB 9532 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9533 */ 9534 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9535 !hba->dev_info.is_lu_power_on_wp) { 9536 ufshcd_setup_vreg(hba, false); 9537 vcc_off = true; 9538 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9539 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9540 vcc_off = true; 9541 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9542 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9543 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9544 } 9545 } 9546 9547 /* 9548 * Some UFS devices require delay after VCC power rail is turned-off. 9549 */ 9550 if (vcc_off && hba->vreg_info.vcc && 9551 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9552 usleep_range(5000, 5100); 9553 } 9554 9555 #ifdef CONFIG_PM 9556 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9557 { 9558 int ret = 0; 9559 9560 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9561 !hba->dev_info.is_lu_power_on_wp) { 9562 ret = ufshcd_setup_vreg(hba, true); 9563 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9564 if (!ufshcd_is_link_active(hba)) { 9565 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9566 if (ret) 9567 goto vcc_disable; 9568 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9569 if (ret) 9570 goto vccq_lpm; 9571 } 9572 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9573 } 9574 goto out; 9575 9576 vccq_lpm: 9577 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9578 vcc_disable: 9579 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9580 out: 9581 return ret; 9582 } 9583 #endif /* CONFIG_PM */ 9584 9585 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9586 { 9587 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9588 ufshcd_setup_hba_vreg(hba, false); 9589 } 9590 9591 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9592 { 9593 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9594 ufshcd_setup_hba_vreg(hba, true); 9595 } 9596 9597 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9598 { 9599 int ret = 0; 9600 bool check_for_bkops; 9601 enum ufs_pm_level pm_lvl; 9602 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9603 enum uic_link_state req_link_state; 9604 9605 hba->pm_op_in_progress = true; 9606 if (pm_op != UFS_SHUTDOWN_PM) { 9607 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9608 hba->rpm_lvl : hba->spm_lvl; 9609 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9610 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9611 } else { 9612 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9613 req_link_state = UIC_LINK_OFF_STATE; 9614 } 9615 9616 /* 9617 * If we can't transition into any of the low power modes 9618 * just gate the clocks. 9619 */ 9620 ufshcd_hold(hba); 9621 hba->clk_gating.is_suspended = true; 9622 9623 if (ufshcd_is_clkscaling_supported(hba)) 9624 ufshcd_clk_scaling_suspend(hba, true); 9625 9626 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9627 req_link_state == UIC_LINK_ACTIVE_STATE) { 9628 goto vops_suspend; 9629 } 9630 9631 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9632 (req_link_state == hba->uic_link_state)) 9633 goto enable_scaling; 9634 9635 /* UFS device & link must be active before we enter in this function */ 9636 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9637 /* Wait err handler finish or trigger err recovery */ 9638 if (!ufshcd_eh_in_progress(hba)) 9639 ufshcd_force_error_recovery(hba); 9640 ret = -EBUSY; 9641 goto enable_scaling; 9642 } 9643 9644 if (pm_op == UFS_RUNTIME_PM) { 9645 if (ufshcd_can_autobkops_during_suspend(hba)) { 9646 /* 9647 * The device is idle with no requests in the queue, 9648 * allow background operations if bkops status shows 9649 * that performance might be impacted. 9650 */ 9651 ret = ufshcd_bkops_ctrl(hba); 9652 if (ret) { 9653 /* 9654 * If return err in suspend flow, IO will hang. 9655 * Trigger error handler and break suspend for 9656 * error recovery. 9657 */ 9658 ufshcd_force_error_recovery(hba); 9659 ret = -EBUSY; 9660 goto enable_scaling; 9661 } 9662 } else { 9663 /* make sure that auto bkops is disabled */ 9664 ufshcd_disable_auto_bkops(hba); 9665 } 9666 /* 9667 * If device needs to do BKOP or WB buffer flush during 9668 * Hibern8, keep device power mode as "active power mode" 9669 * and VCC supply. 9670 */ 9671 hba->dev_info.b_rpm_dev_flush_capable = 9672 hba->auto_bkops_enabled || 9673 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9674 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9675 ufshcd_is_auto_hibern8_enabled(hba))) && 9676 ufshcd_wb_need_flush(hba)); 9677 } 9678 9679 flush_work(&hba->eeh_work); 9680 9681 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9682 if (ret) 9683 goto enable_scaling; 9684 9685 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9686 if (pm_op != UFS_RUNTIME_PM) 9687 /* ensure that bkops is disabled */ 9688 ufshcd_disable_auto_bkops(hba); 9689 9690 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9691 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9692 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9693 /* 9694 * If return err in suspend flow, IO will hang. 9695 * Trigger error handler and break suspend for 9696 * error recovery. 9697 */ 9698 ufshcd_force_error_recovery(hba); 9699 ret = -EBUSY; 9700 } 9701 if (ret) 9702 goto enable_scaling; 9703 } 9704 } 9705 9706 /* 9707 * In the case of DeepSleep, the device is expected to remain powered 9708 * with the link off, so do not check for bkops. 9709 */ 9710 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9711 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9712 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9713 /* 9714 * If return err in suspend flow, IO will hang. 9715 * Trigger error handler and break suspend for 9716 * error recovery. 9717 */ 9718 ufshcd_force_error_recovery(hba); 9719 ret = -EBUSY; 9720 } 9721 if (ret) 9722 goto set_dev_active; 9723 9724 vops_suspend: 9725 /* 9726 * Call vendor specific suspend callback. As these callbacks may access 9727 * vendor specific host controller register space call them before the 9728 * host clocks are ON. 9729 */ 9730 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9731 if (ret) 9732 goto set_link_active; 9733 9734 cancel_delayed_work_sync(&hba->ufs_rtc_update_work); 9735 goto out; 9736 9737 set_link_active: 9738 /* 9739 * Device hardware reset is required to exit DeepSleep. Also, for 9740 * DeepSleep, the link is off so host reset and restore will be done 9741 * further below. 9742 */ 9743 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9744 ufshcd_device_reset(hba); 9745 WARN_ON(!ufshcd_is_link_off(hba)); 9746 } 9747 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9748 ufshcd_set_link_active(hba); 9749 else if (ufshcd_is_link_off(hba)) 9750 ufshcd_host_reset_and_restore(hba); 9751 set_dev_active: 9752 /* Can also get here needing to exit DeepSleep */ 9753 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9754 ufshcd_device_reset(hba); 9755 ufshcd_host_reset_and_restore(hba); 9756 } 9757 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9758 ufshcd_disable_auto_bkops(hba); 9759 enable_scaling: 9760 if (ufshcd_is_clkscaling_supported(hba)) 9761 ufshcd_clk_scaling_suspend(hba, false); 9762 9763 hba->dev_info.b_rpm_dev_flush_capable = false; 9764 out: 9765 if (hba->dev_info.b_rpm_dev_flush_capable) { 9766 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9767 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9768 } 9769 9770 if (ret) { 9771 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9772 hba->clk_gating.is_suspended = false; 9773 ufshcd_release(hba); 9774 } 9775 hba->pm_op_in_progress = false; 9776 return ret; 9777 } 9778 9779 #ifdef CONFIG_PM 9780 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9781 { 9782 int ret; 9783 enum uic_link_state old_link_state = hba->uic_link_state; 9784 9785 hba->pm_op_in_progress = true; 9786 9787 /* 9788 * Call vendor specific resume callback. As these callbacks may access 9789 * vendor specific host controller register space call them when the 9790 * host clocks are ON. 9791 */ 9792 ret = ufshcd_vops_resume(hba, pm_op); 9793 if (ret) 9794 goto out; 9795 9796 /* For DeepSleep, the only supported option is to have the link off */ 9797 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9798 9799 if (ufshcd_is_link_hibern8(hba)) { 9800 ret = ufshcd_uic_hibern8_exit(hba); 9801 if (!ret) { 9802 ufshcd_set_link_active(hba); 9803 } else { 9804 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9805 __func__, ret); 9806 goto vendor_suspend; 9807 } 9808 } else if (ufshcd_is_link_off(hba)) { 9809 /* 9810 * A full initialization of the host and the device is 9811 * required since the link was put to off during suspend. 9812 * Note, in the case of DeepSleep, the device will exit 9813 * DeepSleep due to device reset. 9814 */ 9815 ret = ufshcd_reset_and_restore(hba); 9816 /* 9817 * ufshcd_reset_and_restore() should have already 9818 * set the link state as active 9819 */ 9820 if (ret || !ufshcd_is_link_active(hba)) 9821 goto vendor_suspend; 9822 } 9823 9824 if (!ufshcd_is_ufs_dev_active(hba)) { 9825 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9826 if (ret) 9827 goto set_old_link_state; 9828 ufshcd_set_timestamp_attr(hba); 9829 schedule_delayed_work(&hba->ufs_rtc_update_work, 9830 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 9831 } 9832 9833 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9834 ufshcd_enable_auto_bkops(hba); 9835 else 9836 /* 9837 * If BKOPs operations are urgently needed at this moment then 9838 * keep auto-bkops enabled or else disable it. 9839 */ 9840 ufshcd_bkops_ctrl(hba); 9841 9842 if (hba->ee_usr_mask) 9843 ufshcd_write_ee_control(hba); 9844 9845 if (ufshcd_is_clkscaling_supported(hba)) 9846 ufshcd_clk_scaling_suspend(hba, false); 9847 9848 if (hba->dev_info.b_rpm_dev_flush_capable) { 9849 hba->dev_info.b_rpm_dev_flush_capable = false; 9850 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9851 } 9852 9853 ufshcd_configure_auto_hibern8(hba); 9854 9855 goto out; 9856 9857 set_old_link_state: 9858 ufshcd_link_state_transition(hba, old_link_state, 0); 9859 vendor_suspend: 9860 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9861 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9862 out: 9863 if (ret) 9864 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9865 hba->clk_gating.is_suspended = false; 9866 ufshcd_release(hba); 9867 hba->pm_op_in_progress = false; 9868 return ret; 9869 } 9870 9871 static int ufshcd_wl_runtime_suspend(struct device *dev) 9872 { 9873 struct scsi_device *sdev = to_scsi_device(dev); 9874 struct ufs_hba *hba; 9875 int ret; 9876 ktime_t start = ktime_get(); 9877 9878 hba = shost_priv(sdev->host); 9879 9880 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9881 if (ret) 9882 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9883 9884 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9885 ktime_to_us(ktime_sub(ktime_get(), start)), 9886 hba->curr_dev_pwr_mode, hba->uic_link_state); 9887 9888 return ret; 9889 } 9890 9891 static int ufshcd_wl_runtime_resume(struct device *dev) 9892 { 9893 struct scsi_device *sdev = to_scsi_device(dev); 9894 struct ufs_hba *hba; 9895 int ret = 0; 9896 ktime_t start = ktime_get(); 9897 9898 hba = shost_priv(sdev->host); 9899 9900 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9901 if (ret) 9902 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9903 9904 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9905 ktime_to_us(ktime_sub(ktime_get(), start)), 9906 hba->curr_dev_pwr_mode, hba->uic_link_state); 9907 9908 return ret; 9909 } 9910 #endif 9911 9912 #ifdef CONFIG_PM_SLEEP 9913 static int ufshcd_wl_suspend(struct device *dev) 9914 { 9915 struct scsi_device *sdev = to_scsi_device(dev); 9916 struct ufs_hba *hba; 9917 int ret = 0; 9918 ktime_t start = ktime_get(); 9919 9920 hba = shost_priv(sdev->host); 9921 down(&hba->host_sem); 9922 hba->system_suspending = true; 9923 9924 if (pm_runtime_suspended(dev)) 9925 goto out; 9926 9927 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9928 if (ret) { 9929 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9930 up(&hba->host_sem); 9931 } 9932 9933 out: 9934 if (!ret) 9935 hba->is_sys_suspended = true; 9936 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9937 ktime_to_us(ktime_sub(ktime_get(), start)), 9938 hba->curr_dev_pwr_mode, hba->uic_link_state); 9939 9940 return ret; 9941 } 9942 9943 static int ufshcd_wl_resume(struct device *dev) 9944 { 9945 struct scsi_device *sdev = to_scsi_device(dev); 9946 struct ufs_hba *hba; 9947 int ret = 0; 9948 ktime_t start = ktime_get(); 9949 9950 hba = shost_priv(sdev->host); 9951 9952 if (pm_runtime_suspended(dev)) 9953 goto out; 9954 9955 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9956 if (ret) 9957 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9958 out: 9959 trace_ufshcd_wl_resume(dev_name(dev), ret, 9960 ktime_to_us(ktime_sub(ktime_get(), start)), 9961 hba->curr_dev_pwr_mode, hba->uic_link_state); 9962 if (!ret) 9963 hba->is_sys_suspended = false; 9964 hba->system_suspending = false; 9965 up(&hba->host_sem); 9966 return ret; 9967 } 9968 #endif 9969 9970 /** 9971 * ufshcd_suspend - helper function for suspend operations 9972 * @hba: per adapter instance 9973 * 9974 * This function will put disable irqs, turn off clocks 9975 * and set vreg and hba-vreg in lpm mode. 9976 * 9977 * Return: 0 upon success; < 0 upon failure. 9978 */ 9979 static int ufshcd_suspend(struct ufs_hba *hba) 9980 { 9981 int ret; 9982 9983 if (!hba->is_powered) 9984 return 0; 9985 /* 9986 * Disable the host irq as host controller as there won't be any 9987 * host controller transaction expected till resume. 9988 */ 9989 ufshcd_disable_irq(hba); 9990 ret = ufshcd_setup_clocks(hba, false); 9991 if (ret) { 9992 ufshcd_enable_irq(hba); 9993 return ret; 9994 } 9995 if (ufshcd_is_clkgating_allowed(hba)) { 9996 hba->clk_gating.state = CLKS_OFF; 9997 trace_ufshcd_clk_gating(dev_name(hba->dev), 9998 hba->clk_gating.state); 9999 } 10000 10001 ufshcd_vreg_set_lpm(hba); 10002 /* Put the host controller in low power mode if possible */ 10003 ufshcd_hba_vreg_set_lpm(hba); 10004 ufshcd_pm_qos_update(hba, false); 10005 return ret; 10006 } 10007 10008 #ifdef CONFIG_PM 10009 /** 10010 * ufshcd_resume - helper function for resume operations 10011 * @hba: per adapter instance 10012 * 10013 * This function basically turns on the regulators, clocks and 10014 * irqs of the hba. 10015 * 10016 * Return: 0 for success and non-zero for failure. 10017 */ 10018 static int ufshcd_resume(struct ufs_hba *hba) 10019 { 10020 int ret; 10021 10022 if (!hba->is_powered) 10023 return 0; 10024 10025 ufshcd_hba_vreg_set_hpm(hba); 10026 ret = ufshcd_vreg_set_hpm(hba); 10027 if (ret) 10028 goto out; 10029 10030 /* Make sure clocks are enabled before accessing controller */ 10031 ret = ufshcd_setup_clocks(hba, true); 10032 if (ret) 10033 goto disable_vreg; 10034 10035 /* enable the host irq as host controller would be active soon */ 10036 ufshcd_enable_irq(hba); 10037 10038 goto out; 10039 10040 disable_vreg: 10041 ufshcd_vreg_set_lpm(hba); 10042 out: 10043 if (ret) 10044 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 10045 return ret; 10046 } 10047 #endif /* CONFIG_PM */ 10048 10049 #ifdef CONFIG_PM_SLEEP 10050 /** 10051 * ufshcd_system_suspend - system suspend callback 10052 * @dev: Device associated with the UFS controller. 10053 * 10054 * Executed before putting the system into a sleep state in which the contents 10055 * of main memory are preserved. 10056 * 10057 * Return: 0 for success and non-zero for failure. 10058 */ 10059 int ufshcd_system_suspend(struct device *dev) 10060 { 10061 struct ufs_hba *hba = dev_get_drvdata(dev); 10062 int ret = 0; 10063 ktime_t start = ktime_get(); 10064 10065 if (pm_runtime_suspended(hba->dev)) 10066 goto out; 10067 10068 ret = ufshcd_suspend(hba); 10069 out: 10070 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 10071 ktime_to_us(ktime_sub(ktime_get(), start)), 10072 hba->curr_dev_pwr_mode, hba->uic_link_state); 10073 return ret; 10074 } 10075 EXPORT_SYMBOL(ufshcd_system_suspend); 10076 10077 /** 10078 * ufshcd_system_resume - system resume callback 10079 * @dev: Device associated with the UFS controller. 10080 * 10081 * Executed after waking the system up from a sleep state in which the contents 10082 * of main memory were preserved. 10083 * 10084 * Return: 0 for success and non-zero for failure. 10085 */ 10086 int ufshcd_system_resume(struct device *dev) 10087 { 10088 struct ufs_hba *hba = dev_get_drvdata(dev); 10089 ktime_t start = ktime_get(); 10090 int ret = 0; 10091 10092 if (pm_runtime_suspended(hba->dev)) 10093 goto out; 10094 10095 ret = ufshcd_resume(hba); 10096 10097 out: 10098 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10099 ktime_to_us(ktime_sub(ktime_get(), start)), 10100 hba->curr_dev_pwr_mode, hba->uic_link_state); 10101 10102 return ret; 10103 } 10104 EXPORT_SYMBOL(ufshcd_system_resume); 10105 #endif /* CONFIG_PM_SLEEP */ 10106 10107 #ifdef CONFIG_PM 10108 /** 10109 * ufshcd_runtime_suspend - runtime suspend callback 10110 * @dev: Device associated with the UFS controller. 10111 * 10112 * Check the description of ufshcd_suspend() function for more details. 10113 * 10114 * Return: 0 for success and non-zero for failure. 10115 */ 10116 int ufshcd_runtime_suspend(struct device *dev) 10117 { 10118 struct ufs_hba *hba = dev_get_drvdata(dev); 10119 int ret; 10120 ktime_t start = ktime_get(); 10121 10122 ret = ufshcd_suspend(hba); 10123 10124 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10125 ktime_to_us(ktime_sub(ktime_get(), start)), 10126 hba->curr_dev_pwr_mode, hba->uic_link_state); 10127 return ret; 10128 } 10129 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10130 10131 /** 10132 * ufshcd_runtime_resume - runtime resume routine 10133 * @dev: Device associated with the UFS controller. 10134 * 10135 * This function basically brings controller 10136 * to active state. Following operations are done in this function: 10137 * 10138 * 1. Turn on all the controller related clocks 10139 * 2. Turn ON VCC rail 10140 * 10141 * Return: 0 upon success; < 0 upon failure. 10142 */ 10143 int ufshcd_runtime_resume(struct device *dev) 10144 { 10145 struct ufs_hba *hba = dev_get_drvdata(dev); 10146 int ret; 10147 ktime_t start = ktime_get(); 10148 10149 ret = ufshcd_resume(hba); 10150 10151 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10152 ktime_to_us(ktime_sub(ktime_get(), start)), 10153 hba->curr_dev_pwr_mode, hba->uic_link_state); 10154 return ret; 10155 } 10156 EXPORT_SYMBOL(ufshcd_runtime_resume); 10157 #endif /* CONFIG_PM */ 10158 10159 static void ufshcd_wl_shutdown(struct device *dev) 10160 { 10161 struct scsi_device *sdev = to_scsi_device(dev); 10162 struct ufs_hba *hba = shost_priv(sdev->host); 10163 10164 down(&hba->host_sem); 10165 hba->shutting_down = true; 10166 up(&hba->host_sem); 10167 10168 /* Turn on everything while shutting down */ 10169 ufshcd_rpm_get_sync(hba); 10170 scsi_device_quiesce(sdev); 10171 shost_for_each_device(sdev, hba->host) { 10172 if (sdev == hba->ufs_device_wlun) 10173 continue; 10174 scsi_device_quiesce(sdev); 10175 } 10176 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10177 10178 /* 10179 * Next, turn off the UFS controller and the UFS regulators. Disable 10180 * clocks. 10181 */ 10182 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10183 ufshcd_suspend(hba); 10184 10185 hba->is_powered = false; 10186 } 10187 10188 /** 10189 * ufshcd_remove - de-allocate SCSI host and host memory space 10190 * data structure memory 10191 * @hba: per adapter instance 10192 */ 10193 void ufshcd_remove(struct ufs_hba *hba) 10194 { 10195 if (hba->ufs_device_wlun) 10196 ufshcd_rpm_get_sync(hba); 10197 ufs_hwmon_remove(hba); 10198 ufs_bsg_remove(hba); 10199 ufs_sysfs_remove_nodes(hba->dev); 10200 blk_mq_destroy_queue(hba->tmf_queue); 10201 blk_put_queue(hba->tmf_queue); 10202 blk_mq_free_tag_set(&hba->tmf_tag_set); 10203 if (hba->scsi_host_added) 10204 scsi_remove_host(hba->host); 10205 /* disable interrupts */ 10206 ufshcd_disable_intr(hba, hba->intr_mask); 10207 ufshcd_hba_stop(hba); 10208 ufshcd_hba_exit(hba); 10209 } 10210 EXPORT_SYMBOL_GPL(ufshcd_remove); 10211 10212 #ifdef CONFIG_PM_SLEEP 10213 int ufshcd_system_freeze(struct device *dev) 10214 { 10215 10216 return ufshcd_system_suspend(dev); 10217 10218 } 10219 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10220 10221 int ufshcd_system_restore(struct device *dev) 10222 { 10223 10224 struct ufs_hba *hba = dev_get_drvdata(dev); 10225 int ret; 10226 10227 ret = ufshcd_system_resume(dev); 10228 if (ret) 10229 return ret; 10230 10231 /* Configure UTRL and UTMRL base address registers */ 10232 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10233 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10234 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10235 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10236 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10237 REG_UTP_TASK_REQ_LIST_BASE_L); 10238 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10239 REG_UTP_TASK_REQ_LIST_BASE_H); 10240 /* 10241 * Make sure that UTRL and UTMRL base address registers 10242 * are updated with the latest queue addresses. Only after 10243 * updating these addresses, we can queue the new commands. 10244 */ 10245 ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H); 10246 10247 return 0; 10248 10249 } 10250 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10251 10252 int ufshcd_system_thaw(struct device *dev) 10253 { 10254 return ufshcd_system_resume(dev); 10255 } 10256 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10257 #endif /* CONFIG_PM_SLEEP */ 10258 10259 /** 10260 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10261 * @hba: pointer to Host Bus Adapter (HBA) 10262 */ 10263 void ufshcd_dealloc_host(struct ufs_hba *hba) 10264 { 10265 scsi_host_put(hba->host); 10266 } 10267 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10268 10269 /** 10270 * ufshcd_set_dma_mask - Set dma mask based on the controller 10271 * addressing capability 10272 * @hba: per adapter instance 10273 * 10274 * Return: 0 for success, non-zero for failure. 10275 */ 10276 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10277 { 10278 if (hba->vops && hba->vops->set_dma_mask) 10279 return hba->vops->set_dma_mask(hba); 10280 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10281 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10282 return 0; 10283 } 10284 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10285 } 10286 10287 /** 10288 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10289 * @dev: pointer to device handle 10290 * @hba_handle: driver private handle 10291 * 10292 * Return: 0 on success, non-zero value on failure. 10293 */ 10294 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10295 { 10296 struct Scsi_Host *host; 10297 struct ufs_hba *hba; 10298 int err = 0; 10299 10300 if (!dev) { 10301 dev_err(dev, 10302 "Invalid memory reference for dev is NULL\n"); 10303 err = -ENODEV; 10304 goto out_error; 10305 } 10306 10307 host = scsi_host_alloc(&ufshcd_driver_template, 10308 sizeof(struct ufs_hba)); 10309 if (!host) { 10310 dev_err(dev, "scsi_host_alloc failed\n"); 10311 err = -ENOMEM; 10312 goto out_error; 10313 } 10314 host->nr_maps = HCTX_TYPE_POLL + 1; 10315 hba = shost_priv(host); 10316 hba->host = host; 10317 hba->dev = dev; 10318 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10319 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10320 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10321 INIT_LIST_HEAD(&hba->clk_list_head); 10322 spin_lock_init(&hba->outstanding_lock); 10323 10324 *hba_handle = hba; 10325 10326 out_error: 10327 return err; 10328 } 10329 EXPORT_SYMBOL(ufshcd_alloc_host); 10330 10331 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10332 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10333 const struct blk_mq_queue_data *qd) 10334 { 10335 WARN_ON_ONCE(true); 10336 return BLK_STS_NOTSUPP; 10337 } 10338 10339 static const struct blk_mq_ops ufshcd_tmf_ops = { 10340 .queue_rq = ufshcd_queue_tmf, 10341 }; 10342 10343 static int ufshcd_add_scsi_host(struct ufs_hba *hba) 10344 { 10345 int err; 10346 10347 if (is_mcq_supported(hba)) { 10348 ufshcd_mcq_enable(hba); 10349 err = ufshcd_alloc_mcq(hba); 10350 if (!err) { 10351 ufshcd_config_mcq(hba); 10352 } else { 10353 /* Continue with SDB mode */ 10354 ufshcd_mcq_disable(hba); 10355 use_mcq_mode = false; 10356 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 10357 err); 10358 } 10359 err = scsi_add_host(hba->host, hba->dev); 10360 if (err) { 10361 dev_err(hba->dev, "scsi_add_host failed\n"); 10362 return err; 10363 } 10364 hba->scsi_host_added = true; 10365 } else { 10366 if (!hba->lsdb_sup) { 10367 dev_err(hba->dev, 10368 "%s: failed to initialize (legacy doorbell mode not supported)\n", 10369 __func__); 10370 return -EINVAL; 10371 } 10372 err = scsi_add_host(hba->host, hba->dev); 10373 if (err) { 10374 dev_err(hba->dev, "scsi_add_host failed\n"); 10375 return err; 10376 } 10377 hba->scsi_host_added = true; 10378 } 10379 10380 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10381 .nr_hw_queues = 1, 10382 .queue_depth = hba->nutmrs, 10383 .ops = &ufshcd_tmf_ops, 10384 .flags = BLK_MQ_F_NO_SCHED, 10385 }; 10386 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10387 if (err < 0) 10388 goto remove_scsi_host; 10389 hba->tmf_queue = blk_mq_alloc_queue(&hba->tmf_tag_set, NULL, NULL); 10390 if (IS_ERR(hba->tmf_queue)) { 10391 err = PTR_ERR(hba->tmf_queue); 10392 goto free_tmf_tag_set; 10393 } 10394 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10395 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10396 if (!hba->tmf_rqs) { 10397 err = -ENOMEM; 10398 goto free_tmf_queue; 10399 } 10400 10401 return 0; 10402 10403 free_tmf_queue: 10404 blk_mq_destroy_queue(hba->tmf_queue); 10405 blk_put_queue(hba->tmf_queue); 10406 10407 free_tmf_tag_set: 10408 blk_mq_free_tag_set(&hba->tmf_tag_set); 10409 10410 remove_scsi_host: 10411 if (hba->scsi_host_added) 10412 scsi_remove_host(hba->host); 10413 10414 return err; 10415 } 10416 10417 /** 10418 * ufshcd_init - Driver initialization routine 10419 * @hba: per-adapter instance 10420 * @mmio_base: base register address 10421 * @irq: Interrupt line of device 10422 * 10423 * Return: 0 on success, non-zero value on failure. 10424 */ 10425 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10426 { 10427 int err; 10428 struct Scsi_Host *host = hba->host; 10429 struct device *dev = hba->dev; 10430 10431 /* 10432 * dev_set_drvdata() must be called before any callbacks are registered 10433 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10434 * sysfs). 10435 */ 10436 dev_set_drvdata(dev, hba); 10437 10438 if (!mmio_base) { 10439 dev_err(hba->dev, 10440 "Invalid memory reference for mmio_base is NULL\n"); 10441 err = -ENODEV; 10442 goto out_error; 10443 } 10444 10445 hba->mmio_base = mmio_base; 10446 hba->irq = irq; 10447 hba->vps = &ufs_hba_vps; 10448 10449 err = ufshcd_hba_init(hba); 10450 if (err) 10451 goto out_error; 10452 10453 /* Read capabilities registers */ 10454 err = ufshcd_hba_capabilities(hba); 10455 if (err) 10456 goto out_disable; 10457 10458 /* Get UFS version supported by the controller */ 10459 hba->ufs_version = ufshcd_get_ufs_version(hba); 10460 10461 /* Get Interrupt bit mask per version */ 10462 hba->intr_mask = ufshcd_get_intr_mask(hba); 10463 10464 err = ufshcd_set_dma_mask(hba); 10465 if (err) { 10466 dev_err(hba->dev, "set dma mask failed\n"); 10467 goto out_disable; 10468 } 10469 10470 /* Allocate memory for host memory space */ 10471 err = ufshcd_memory_alloc(hba); 10472 if (err) { 10473 dev_err(hba->dev, "Memory allocation failed\n"); 10474 goto out_disable; 10475 } 10476 10477 /* Configure LRB */ 10478 ufshcd_host_memory_configure(hba); 10479 10480 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10481 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10482 host->max_id = UFSHCD_MAX_ID; 10483 host->max_lun = UFS_MAX_LUNS; 10484 host->max_channel = UFSHCD_MAX_CHANNEL; 10485 host->unique_id = host->host_no; 10486 host->max_cmd_len = UFS_CDB_SIZE; 10487 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10488 10489 /* Use default RPM delay if host not set */ 10490 if (host->rpm_autosuspend_delay == 0) 10491 host->rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS; 10492 10493 hba->max_pwr_info.is_valid = false; 10494 10495 /* Initialize work queues */ 10496 hba->eh_wq = alloc_ordered_workqueue("ufs_eh_wq_%d", WQ_MEM_RECLAIM, 10497 hba->host->host_no); 10498 if (!hba->eh_wq) { 10499 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10500 __func__); 10501 err = -ENOMEM; 10502 goto out_disable; 10503 } 10504 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10505 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10506 10507 sema_init(&hba->host_sem, 1); 10508 10509 /* Initialize UIC command mutex */ 10510 mutex_init(&hba->uic_cmd_mutex); 10511 10512 /* Initialize mutex for device management commands */ 10513 mutex_init(&hba->dev_cmd.lock); 10514 10515 /* Initialize mutex for exception event control */ 10516 mutex_init(&hba->ee_ctrl_mutex); 10517 10518 mutex_init(&hba->wb_mutex); 10519 init_rwsem(&hba->clk_scaling_lock); 10520 10521 ufshcd_init_clk_gating(hba); 10522 10523 ufshcd_init_clk_scaling(hba); 10524 10525 /* 10526 * In order to avoid any spurious interrupt immediately after 10527 * registering UFS controller interrupt handler, clear any pending UFS 10528 * interrupt status and disable all the UFS interrupts. 10529 */ 10530 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10531 REG_INTERRUPT_STATUS); 10532 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10533 /* 10534 * Make sure that UFS interrupts are disabled and any pending interrupt 10535 * status is cleared before registering UFS interrupt handler. 10536 */ 10537 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 10538 10539 /* IRQ registration */ 10540 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10541 if (err) { 10542 dev_err(hba->dev, "request irq failed\n"); 10543 goto out_disable; 10544 } else { 10545 hba->is_irq_enabled = true; 10546 } 10547 10548 /* Reset the attached device */ 10549 ufshcd_device_reset(hba); 10550 10551 ufshcd_init_crypto(hba); 10552 10553 /* Host controller enable */ 10554 err = ufshcd_hba_enable(hba); 10555 if (err) { 10556 dev_err(hba->dev, "Host controller enable failed\n"); 10557 ufshcd_print_evt_hist(hba); 10558 ufshcd_print_host_state(hba); 10559 goto out_disable; 10560 } 10561 10562 /* 10563 * Set the default power management level for runtime and system PM. 10564 * Default power saving mode is to keep UFS link in Hibern8 state 10565 * and UFS device in sleep state. 10566 */ 10567 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10568 UFS_SLEEP_PWR_MODE, 10569 UIC_LINK_HIBERN8_STATE); 10570 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10571 UFS_SLEEP_PWR_MODE, 10572 UIC_LINK_HIBERN8_STATE); 10573 10574 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, ufshcd_rpm_dev_flush_recheck_work); 10575 INIT_DELAYED_WORK(&hba->ufs_rtc_update_work, ufshcd_rtc_work); 10576 10577 /* Set the default auto-hiberate idle timer value to 150 ms */ 10578 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10579 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10580 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10581 } 10582 10583 /* Hold auto suspend until async scan completes */ 10584 pm_runtime_get_sync(dev); 10585 10586 /* 10587 * We are assuming that device wasn't put in sleep/power-down 10588 * state exclusively during the boot stage before kernel. 10589 * This assumption helps avoid doing link startup twice during 10590 * ufshcd_probe_hba(). 10591 */ 10592 ufshcd_set_ufs_dev_active(hba); 10593 10594 /* Initialize hba, detect and initialize UFS device */ 10595 ktime_t probe_start = ktime_get(); 10596 10597 hba->ufshcd_state = UFSHCD_STATE_RESET; 10598 10599 err = ufshcd_link_startup(hba); 10600 if (err) 10601 goto out_disable; 10602 10603 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 10604 goto initialized; 10605 10606 /* Debug counters initialization */ 10607 ufshcd_clear_dbg_ufs_stats(hba); 10608 10609 /* UniPro link is active now */ 10610 ufshcd_set_link_active(hba); 10611 10612 /* Verify device initialization by sending NOP OUT UPIU */ 10613 err = ufshcd_verify_dev_init(hba); 10614 if (err) 10615 goto out_disable; 10616 10617 /* Initiate UFS initialization, and waiting until completion */ 10618 err = ufshcd_complete_dev_init(hba); 10619 if (err) 10620 goto out_disable; 10621 10622 err = ufshcd_device_params_init(hba); 10623 if (err) 10624 goto out_disable; 10625 10626 err = ufshcd_post_device_init(hba); 10627 10628 initialized: 10629 ufshcd_process_probe_result(hba, probe_start, err); 10630 if (err) 10631 goto out_disable; 10632 10633 err = ufshcd_add_scsi_host(hba); 10634 if (err) 10635 goto out_disable; 10636 10637 async_schedule(ufshcd_async_scan, hba); 10638 ufs_sysfs_add_nodes(hba->dev); 10639 10640 device_enable_async_suspend(dev); 10641 ufshcd_pm_qos_init(hba); 10642 return 0; 10643 10644 out_disable: 10645 hba->is_irq_enabled = false; 10646 ufshcd_hba_exit(hba); 10647 out_error: 10648 return err; 10649 } 10650 EXPORT_SYMBOL_GPL(ufshcd_init); 10651 10652 void ufshcd_resume_complete(struct device *dev) 10653 { 10654 struct ufs_hba *hba = dev_get_drvdata(dev); 10655 10656 if (hba->complete_put) { 10657 ufshcd_rpm_put(hba); 10658 hba->complete_put = false; 10659 } 10660 } 10661 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10662 10663 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10664 { 10665 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10666 enum ufs_dev_pwr_mode dev_pwr_mode; 10667 enum uic_link_state link_state; 10668 unsigned long flags; 10669 bool res; 10670 10671 spin_lock_irqsave(&dev->power.lock, flags); 10672 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10673 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10674 res = pm_runtime_suspended(dev) && 10675 hba->curr_dev_pwr_mode == dev_pwr_mode && 10676 hba->uic_link_state == link_state && 10677 !hba->dev_info.b_rpm_dev_flush_capable; 10678 spin_unlock_irqrestore(&dev->power.lock, flags); 10679 10680 return res; 10681 } 10682 10683 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10684 { 10685 struct ufs_hba *hba = dev_get_drvdata(dev); 10686 int ret; 10687 10688 /* 10689 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10690 * are same. And it doesn't wake up the device for system-suspend 10691 * if it's runtime suspended. But ufs doesn't follow that. 10692 * Refer ufshcd_resume_complete() 10693 */ 10694 if (hba->ufs_device_wlun) { 10695 /* Prevent runtime suspend */ 10696 ufshcd_rpm_get_noresume(hba); 10697 /* 10698 * Check if already runtime suspended in same state as system 10699 * suspend would be. 10700 */ 10701 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10702 /* RPM state is not ok for SPM, so runtime resume */ 10703 ret = ufshcd_rpm_resume(hba); 10704 if (ret < 0 && ret != -EACCES) { 10705 ufshcd_rpm_put(hba); 10706 return ret; 10707 } 10708 } 10709 hba->complete_put = true; 10710 } 10711 return 0; 10712 } 10713 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10714 10715 int ufshcd_suspend_prepare(struct device *dev) 10716 { 10717 return __ufshcd_suspend_prepare(dev, true); 10718 } 10719 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10720 10721 #ifdef CONFIG_PM_SLEEP 10722 static int ufshcd_wl_poweroff(struct device *dev) 10723 { 10724 struct scsi_device *sdev = to_scsi_device(dev); 10725 struct ufs_hba *hba = shost_priv(sdev->host); 10726 10727 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10728 return 0; 10729 } 10730 #endif 10731 10732 static int ufshcd_wl_probe(struct device *dev) 10733 { 10734 struct scsi_device *sdev = to_scsi_device(dev); 10735 10736 if (!is_device_wlun(sdev)) 10737 return -ENODEV; 10738 10739 blk_pm_runtime_init(sdev->request_queue, dev); 10740 pm_runtime_set_autosuspend_delay(dev, 0); 10741 pm_runtime_allow(dev); 10742 10743 return 0; 10744 } 10745 10746 static int ufshcd_wl_remove(struct device *dev) 10747 { 10748 pm_runtime_forbid(dev); 10749 return 0; 10750 } 10751 10752 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10753 #ifdef CONFIG_PM_SLEEP 10754 .suspend = ufshcd_wl_suspend, 10755 .resume = ufshcd_wl_resume, 10756 .freeze = ufshcd_wl_suspend, 10757 .thaw = ufshcd_wl_resume, 10758 .poweroff = ufshcd_wl_poweroff, 10759 .restore = ufshcd_wl_resume, 10760 #endif 10761 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10762 }; 10763 10764 static void ufshcd_check_header_layout(void) 10765 { 10766 /* 10767 * gcc compilers before version 10 cannot do constant-folding for 10768 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10769 * before. 10770 */ 10771 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10772 return; 10773 10774 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10775 .cci = 3})[0] != 3); 10776 10777 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10778 .ehs_length = 2})[1] != 2); 10779 10780 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10781 .enable_crypto = 1})[2] 10782 != 0x80); 10783 10784 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10785 .command_type = 5, 10786 .data_direction = 3, 10787 .interrupt = 1, 10788 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10789 10790 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10791 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10792 cpu_to_le32(0xdeadbeef)); 10793 10794 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10795 .ocs = 4})[8] != 4); 10796 10797 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10798 .cds = 5})[9] != 5); 10799 10800 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10801 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10802 cpu_to_le32(0xbadcafe)); 10803 10804 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10805 .iid = 0xf })[4] != 0xf0); 10806 10807 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10808 .command_set_type = 0xf })[4] != 0xf); 10809 } 10810 10811 /* 10812 * ufs_dev_wlun_template - describes ufs device wlun 10813 * ufs-device wlun - used to send pm commands 10814 * All luns are consumers of ufs-device wlun. 10815 * 10816 * Currently, no sd driver is present for wluns. 10817 * Hence the no specific pm operations are performed. 10818 * With ufs design, SSU should be sent to ufs-device wlun. 10819 * Hence register a scsi driver for ufs wluns only. 10820 */ 10821 static struct scsi_driver ufs_dev_wlun_template = { 10822 .gendrv = { 10823 .name = "ufs_device_wlun", 10824 .probe = ufshcd_wl_probe, 10825 .remove = ufshcd_wl_remove, 10826 .pm = &ufshcd_wl_pm_ops, 10827 .shutdown = ufshcd_wl_shutdown, 10828 }, 10829 }; 10830 10831 static int __init ufshcd_core_init(void) 10832 { 10833 int ret; 10834 10835 ufshcd_check_header_layout(); 10836 10837 ufs_debugfs_init(); 10838 10839 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10840 if (ret) 10841 ufs_debugfs_exit(); 10842 return ret; 10843 } 10844 10845 static void __exit ufshcd_core_exit(void) 10846 { 10847 ufs_debugfs_exit(); 10848 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10849 } 10850 10851 module_init(ufshcd_core_init); 10852 module_exit(ufshcd_core_exit); 10853 10854 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10855 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10856 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10857 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10858 MODULE_LICENSE("GPL"); 10859