1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/pm_opp.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/sched/clock.h> 26 #include <linux/iopoll.h> 27 #include <scsi/scsi_cmnd.h> 28 #include <scsi/scsi_dbg.h> 29 #include <scsi/scsi_driver.h> 30 #include <scsi/scsi_eh.h> 31 #include "ufshcd-priv.h" 32 #include <ufs/ufs_quirks.h> 33 #include <ufs/unipro.h> 34 #include "ufs-sysfs.h" 35 #include "ufs-debugfs.h" 36 #include "ufs-fault-injection.h" 37 #include "ufs_bsg.h" 38 #include "ufshcd-crypto.h" 39 #include <asm/unaligned.h> 40 41 #define CREATE_TRACE_POINTS 42 #include <trace/events/ufs.h> 43 44 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 45 UTP_TASK_REQ_COMPL |\ 46 UFSHCD_ERROR_MASK) 47 48 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 49 UFSHCD_ERROR_MASK |\ 50 MCQ_CQ_EVENT_STATUS) 51 52 53 /* UIC command timeout, unit: ms */ 54 #define UIC_CMD_TIMEOUT 500 55 56 /* NOP OUT retries waiting for NOP IN response */ 57 #define NOP_OUT_RETRIES 10 58 /* Timeout after 50 msecs if NOP OUT hangs without response */ 59 #define NOP_OUT_TIMEOUT 50 /* msecs */ 60 61 /* Query request retries */ 62 #define QUERY_REQ_RETRIES 3 63 /* Query request timeout */ 64 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 65 66 /* Advanced RPMB request timeout */ 67 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 68 69 /* Task management command timeout */ 70 #define TM_CMD_TIMEOUT 100 /* msecs */ 71 72 /* maximum number of retries for a general UIC command */ 73 #define UFS_UIC_COMMAND_RETRIES 3 74 75 /* maximum number of link-startup retries */ 76 #define DME_LINKSTARTUP_RETRIES 3 77 78 /* maximum number of reset retries before giving up */ 79 #define MAX_HOST_RESET_RETRIES 5 80 81 /* Maximum number of error handler retries before giving up */ 82 #define MAX_ERR_HANDLER_RETRIES 5 83 84 /* Expose the flag value from utp_upiu_query.value */ 85 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 86 87 /* Interrupt aggregation default timeout, unit: 40us */ 88 #define INT_AGGR_DEF_TO 0x02 89 90 /* default delay of autosuspend: 2000 ms */ 91 #define RPM_AUTOSUSPEND_DELAY_MS 2000 92 93 /* Default delay of RPM device flush delayed work */ 94 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 95 96 /* Default value of wait time before gating device ref clock */ 97 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 98 99 /* Polling time to wait for fDeviceInit */ 100 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 101 102 /* UFSHC 4.0 compliant HC support this mode. */ 103 static bool use_mcq_mode = true; 104 105 static bool is_mcq_supported(struct ufs_hba *hba) 106 { 107 return hba->mcq_sup && use_mcq_mode; 108 } 109 110 module_param(use_mcq_mode, bool, 0644); 111 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 112 113 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 114 ({ \ 115 int _ret; \ 116 if (_on) \ 117 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 118 else \ 119 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 120 _ret; \ 121 }) 122 123 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 124 size_t __len = (len); \ 125 print_hex_dump(KERN_ERR, prefix_str, \ 126 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 127 16, 4, buf, __len, false); \ 128 } while (0) 129 130 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 131 const char *prefix) 132 { 133 u32 *regs; 134 size_t pos; 135 136 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 137 return -EINVAL; 138 139 regs = kzalloc(len, GFP_ATOMIC); 140 if (!regs) 141 return -ENOMEM; 142 143 for (pos = 0; pos < len; pos += 4) { 144 if (offset == 0 && 145 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 146 pos <= REG_UIC_ERROR_CODE_DME) 147 continue; 148 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 149 } 150 151 ufshcd_hex_dump(prefix, regs, len); 152 kfree(regs); 153 154 return 0; 155 } 156 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 157 158 enum { 159 UFSHCD_MAX_CHANNEL = 0, 160 UFSHCD_MAX_ID = 1, 161 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED, 162 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED, 163 }; 164 165 static const char *const ufshcd_state_name[] = { 166 [UFSHCD_STATE_RESET] = "reset", 167 [UFSHCD_STATE_OPERATIONAL] = "operational", 168 [UFSHCD_STATE_ERROR] = "error", 169 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 170 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 171 }; 172 173 /* UFSHCD error handling flags */ 174 enum { 175 UFSHCD_EH_IN_PROGRESS = (1 << 0), 176 }; 177 178 /* UFSHCD UIC layer error flags */ 179 enum { 180 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 181 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 182 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 183 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 184 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 185 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 186 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 187 }; 188 189 #define ufshcd_set_eh_in_progress(h) \ 190 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 191 #define ufshcd_eh_in_progress(h) \ 192 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 193 #define ufshcd_clear_eh_in_progress(h) \ 194 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 195 196 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 197 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 198 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 199 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 200 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 201 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 202 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 203 /* 204 * For DeepSleep, the link is first put in hibern8 and then off. 205 * Leaving the link in hibern8 is not supported. 206 */ 207 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 208 }; 209 210 static inline enum ufs_dev_pwr_mode 211 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 212 { 213 return ufs_pm_lvl_states[lvl].dev_state; 214 } 215 216 static inline enum uic_link_state 217 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 218 { 219 return ufs_pm_lvl_states[lvl].link_state; 220 } 221 222 static inline enum ufs_pm_level 223 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 224 enum uic_link_state link_state) 225 { 226 enum ufs_pm_level lvl; 227 228 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 229 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 230 (ufs_pm_lvl_states[lvl].link_state == link_state)) 231 return lvl; 232 } 233 234 /* if no match found, return the level 0 */ 235 return UFS_PM_LVL_0; 236 } 237 238 static const struct ufs_dev_quirk ufs_fixups[] = { 239 /* UFS cards deviations table */ 240 { .wmanufacturerid = UFS_VENDOR_MICRON, 241 .model = UFS_ANY_MODEL, 242 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 243 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 244 .model = UFS_ANY_MODEL, 245 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 246 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 247 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 248 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 249 .model = UFS_ANY_MODEL, 250 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 251 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 252 .model = "hB8aL1" /*H28U62301AMR*/, 253 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 254 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 255 .model = UFS_ANY_MODEL, 256 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 257 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 258 .model = "THGLF2G9C8KBADG", 259 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 260 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 261 .model = "THGLF2G9D8KBADG", 262 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 263 {} 264 }; 265 266 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 267 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 268 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 269 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 270 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 271 static void ufshcd_hba_exit(struct ufs_hba *hba); 272 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 273 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 274 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 275 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 276 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 277 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 278 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 279 bool scale_up); 280 static irqreturn_t ufshcd_intr(int irq, void *__hba); 281 static int ufshcd_change_power_mode(struct ufs_hba *hba, 282 struct ufs_pa_layer_attr *pwr_mode); 283 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 284 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 285 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 286 struct ufs_vreg *vreg); 287 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 288 bool enable); 289 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 290 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 291 292 static inline void ufshcd_enable_irq(struct ufs_hba *hba) 293 { 294 if (!hba->is_irq_enabled) { 295 enable_irq(hba->irq); 296 hba->is_irq_enabled = true; 297 } 298 } 299 300 static inline void ufshcd_disable_irq(struct ufs_hba *hba) 301 { 302 if (hba->is_irq_enabled) { 303 disable_irq(hba->irq); 304 hba->is_irq_enabled = false; 305 } 306 } 307 308 static void ufshcd_configure_wb(struct ufs_hba *hba) 309 { 310 if (!ufshcd_is_wb_allowed(hba)) 311 return; 312 313 ufshcd_wb_toggle(hba, true); 314 315 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 316 317 if (ufshcd_is_wb_buf_flush_allowed(hba)) 318 ufshcd_wb_toggle_buf_flush(hba, true); 319 } 320 321 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba) 322 { 323 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt)) 324 scsi_unblock_requests(hba->host); 325 } 326 327 static void ufshcd_scsi_block_requests(struct ufs_hba *hba) 328 { 329 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1) 330 scsi_block_requests(hba->host); 331 } 332 333 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 334 enum ufs_trace_str_t str_t) 335 { 336 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 337 struct utp_upiu_header *header; 338 339 if (!trace_ufshcd_upiu_enabled()) 340 return; 341 342 if (str_t == UFS_CMD_SEND) 343 header = &rq->header; 344 else 345 header = &hba->lrb[tag].ucd_rsp_ptr->header; 346 347 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 348 UFS_TSF_CDB); 349 } 350 351 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 352 enum ufs_trace_str_t str_t, 353 struct utp_upiu_req *rq_rsp) 354 { 355 if (!trace_ufshcd_upiu_enabled()) 356 return; 357 358 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 359 &rq_rsp->qr, UFS_TSF_OSF); 360 } 361 362 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 363 enum ufs_trace_str_t str_t) 364 { 365 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 366 367 if (!trace_ufshcd_upiu_enabled()) 368 return; 369 370 if (str_t == UFS_TM_SEND) 371 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 372 &descp->upiu_req.req_header, 373 &descp->upiu_req.input_param1, 374 UFS_TSF_TM_INPUT); 375 else 376 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 377 &descp->upiu_rsp.rsp_header, 378 &descp->upiu_rsp.output_param1, 379 UFS_TSF_TM_OUTPUT); 380 } 381 382 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 383 const struct uic_command *ucmd, 384 enum ufs_trace_str_t str_t) 385 { 386 u32 cmd; 387 388 if (!trace_ufshcd_uic_command_enabled()) 389 return; 390 391 if (str_t == UFS_CMD_SEND) 392 cmd = ucmd->command; 393 else 394 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 395 396 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 397 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 398 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 399 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 400 } 401 402 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 403 enum ufs_trace_str_t str_t) 404 { 405 u64 lba = 0; 406 u8 opcode = 0, group_id = 0; 407 u32 doorbell = 0; 408 u32 intr; 409 int hwq_id = -1; 410 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 411 struct scsi_cmnd *cmd = lrbp->cmd; 412 struct request *rq = scsi_cmd_to_rq(cmd); 413 int transfer_len = -1; 414 415 if (!cmd) 416 return; 417 418 /* trace UPIU also */ 419 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 420 if (!trace_ufshcd_command_enabled()) 421 return; 422 423 opcode = cmd->cmnd[0]; 424 425 if (opcode == READ_10 || opcode == WRITE_10) { 426 /* 427 * Currently we only fully trace read(10) and write(10) commands 428 */ 429 transfer_len = 430 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 431 lba = scsi_get_lba(cmd); 432 if (opcode == WRITE_10) 433 group_id = lrbp->cmd->cmnd[6]; 434 } else if (opcode == UNMAP) { 435 /* 436 * The number of Bytes to be unmapped beginning with the lba. 437 */ 438 transfer_len = blk_rq_bytes(rq); 439 lba = scsi_get_lba(cmd); 440 } 441 442 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 443 444 if (is_mcq_enabled(hba)) { 445 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 446 447 hwq_id = hwq->id; 448 } else { 449 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 450 } 451 trace_ufshcd_command(cmd->device, str_t, tag, doorbell, hwq_id, 452 transfer_len, intr, lba, opcode, group_id); 453 } 454 455 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 456 { 457 struct ufs_clk_info *clki; 458 struct list_head *head = &hba->clk_list_head; 459 460 if (list_empty(head)) 461 return; 462 463 list_for_each_entry(clki, head, list) { 464 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 465 clki->max_freq) 466 dev_err(hba->dev, "clk: %s, rate: %u\n", 467 clki->name, clki->curr_freq); 468 } 469 } 470 471 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 472 const char *err_name) 473 { 474 int i; 475 bool found = false; 476 const struct ufs_event_hist *e; 477 478 if (id >= UFS_EVT_CNT) 479 return; 480 481 e = &hba->ufs_stats.event[id]; 482 483 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 484 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 485 486 if (e->tstamp[p] == 0) 487 continue; 488 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 489 e->val[p], div_u64(e->tstamp[p], 1000)); 490 found = true; 491 } 492 493 if (!found) 494 dev_err(hba->dev, "No record of %s\n", err_name); 495 else 496 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 497 } 498 499 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 500 { 501 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 502 503 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 504 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 505 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 506 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 507 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 508 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 509 "auto_hibern8_err"); 510 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 511 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 512 "link_startup_fail"); 513 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 514 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 515 "suspend_fail"); 516 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 517 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 518 "wlun suspend_fail"); 519 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 520 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 521 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 522 523 ufshcd_vops_dbg_register_dump(hba); 524 } 525 526 static 527 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 528 { 529 const struct ufshcd_lrb *lrbp; 530 int prdt_length; 531 532 lrbp = &hba->lrb[tag]; 533 534 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 535 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 536 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 537 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 538 dev_err(hba->dev, 539 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 540 tag, (u64)lrbp->utrd_dma_addr); 541 542 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 543 sizeof(struct utp_transfer_req_desc)); 544 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 545 (u64)lrbp->ucd_req_dma_addr); 546 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 547 sizeof(struct utp_upiu_req)); 548 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 549 (u64)lrbp->ucd_rsp_dma_addr); 550 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 551 sizeof(struct utp_upiu_rsp)); 552 553 prdt_length = le16_to_cpu( 554 lrbp->utr_descriptor_ptr->prd_table_length); 555 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 556 prdt_length /= ufshcd_sg_entry_size(hba); 557 558 dev_err(hba->dev, 559 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 560 tag, prdt_length, 561 (u64)lrbp->ucd_prdt_dma_addr); 562 563 if (pr_prdt) 564 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 565 ufshcd_sg_entry_size(hba) * prdt_length); 566 } 567 568 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 569 { 570 struct scsi_device *sdev = req->q->queuedata; 571 struct Scsi_Host *shost = sdev->host; 572 struct ufs_hba *hba = shost_priv(shost); 573 574 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 575 576 return true; 577 } 578 579 /** 580 * ufshcd_print_trs_all - print trs for all started requests. 581 * @hba: per-adapter instance. 582 * @pr_prdt: need to print prdt or not. 583 */ 584 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 585 { 586 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 587 } 588 589 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 590 { 591 int tag; 592 593 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 594 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 595 596 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 597 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 598 } 599 } 600 601 static void ufshcd_print_host_state(struct ufs_hba *hba) 602 { 603 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 604 605 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 606 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 607 hba->outstanding_reqs, hba->outstanding_tasks); 608 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 609 hba->saved_err, hba->saved_uic_err); 610 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 611 hba->curr_dev_pwr_mode, hba->uic_link_state); 612 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 613 hba->pm_op_in_progress, hba->is_sys_suspended); 614 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 615 hba->auto_bkops_enabled, hba->host->host_self_blocked); 616 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 617 dev_err(hba->dev, 618 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 619 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 620 hba->ufs_stats.hibern8_exit_cnt); 621 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 622 div_u64(hba->ufs_stats.last_intr_ts, 1000), 623 hba->ufs_stats.last_intr_status); 624 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 625 hba->eh_flags, hba->req_abort_count); 626 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 627 hba->ufs_version, hba->capabilities, hba->caps); 628 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 629 hba->dev_quirks); 630 if (sdev_ufs) 631 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 632 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 633 634 ufshcd_print_clk_freqs(hba); 635 } 636 637 /** 638 * ufshcd_print_pwr_info - print power params as saved in hba 639 * power info 640 * @hba: per-adapter instance 641 */ 642 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 643 { 644 static const char * const names[] = { 645 "INVALID MODE", 646 "FAST MODE", 647 "SLOW_MODE", 648 "INVALID MODE", 649 "FASTAUTO_MODE", 650 "SLOWAUTO_MODE", 651 "INVALID MODE", 652 }; 653 654 /* 655 * Using dev_dbg to avoid messages during runtime PM to avoid 656 * never-ending cycles of messages written back to storage by user space 657 * causing runtime resume, causing more messages and so on. 658 */ 659 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 660 __func__, 661 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 662 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 663 names[hba->pwr_info.pwr_rx], 664 names[hba->pwr_info.pwr_tx], 665 hba->pwr_info.hs_rate); 666 } 667 668 static void ufshcd_device_reset(struct ufs_hba *hba) 669 { 670 int err; 671 672 err = ufshcd_vops_device_reset(hba); 673 674 if (!err) { 675 ufshcd_set_ufs_dev_active(hba); 676 if (ufshcd_is_wb_allowed(hba)) { 677 hba->dev_info.wb_enabled = false; 678 hba->dev_info.wb_buf_flush_enabled = false; 679 } 680 } 681 if (err != -EOPNOTSUPP) 682 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 683 } 684 685 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 686 { 687 if (!us) 688 return; 689 690 if (us < 10) 691 udelay(us); 692 else 693 usleep_range(us, us + tolerance); 694 } 695 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 696 697 /** 698 * ufshcd_wait_for_register - wait for register value to change 699 * @hba: per-adapter interface 700 * @reg: mmio register offset 701 * @mask: mask to apply to the read register value 702 * @val: value to wait for 703 * @interval_us: polling interval in microseconds 704 * @timeout_ms: timeout in milliseconds 705 * 706 * Return: -ETIMEDOUT on error, zero on success. 707 */ 708 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 709 u32 val, unsigned long interval_us, 710 unsigned long timeout_ms) 711 { 712 int err = 0; 713 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 714 715 /* ignore bits that we don't intend to wait on */ 716 val = val & mask; 717 718 while ((ufshcd_readl(hba, reg) & mask) != val) { 719 usleep_range(interval_us, interval_us + 50); 720 if (time_after(jiffies, timeout)) { 721 if ((ufshcd_readl(hba, reg) & mask) != val) 722 err = -ETIMEDOUT; 723 break; 724 } 725 } 726 727 return err; 728 } 729 730 /** 731 * ufshcd_get_intr_mask - Get the interrupt bit mask 732 * @hba: Pointer to adapter instance 733 * 734 * Return: interrupt bit mask per version 735 */ 736 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 737 { 738 if (hba->ufs_version == ufshci_version(1, 0)) 739 return INTERRUPT_MASK_ALL_VER_10; 740 if (hba->ufs_version <= ufshci_version(2, 0)) 741 return INTERRUPT_MASK_ALL_VER_11; 742 743 return INTERRUPT_MASK_ALL_VER_21; 744 } 745 746 /** 747 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 748 * @hba: Pointer to adapter instance 749 * 750 * Return: UFSHCI version supported by the controller 751 */ 752 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 753 { 754 u32 ufshci_ver; 755 756 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 757 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 758 else 759 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 760 761 /* 762 * UFSHCI v1.x uses a different version scheme, in order 763 * to allow the use of comparisons with the ufshci_version 764 * function, we convert it to the same scheme as ufs 2.0+. 765 */ 766 if (ufshci_ver & 0x00010000) 767 return ufshci_version(1, ufshci_ver & 0x00000100); 768 769 return ufshci_ver; 770 } 771 772 /** 773 * ufshcd_is_device_present - Check if any device connected to 774 * the host controller 775 * @hba: pointer to adapter instance 776 * 777 * Return: true if device present, false if no device detected 778 */ 779 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 780 { 781 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 782 } 783 784 /** 785 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 786 * @lrbp: pointer to local command reference block 787 * @cqe: pointer to the completion queue entry 788 * 789 * This function is used to get the OCS field from UTRD 790 * 791 * Return: the OCS field in the UTRD. 792 */ 793 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 794 struct cq_entry *cqe) 795 { 796 if (cqe) 797 return le32_to_cpu(cqe->status) & MASK_OCS; 798 799 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 800 } 801 802 /** 803 * ufshcd_utrl_clear() - Clear requests from the controller request list. 804 * @hba: per adapter instance 805 * @mask: mask with one bit set for each request to be cleared 806 */ 807 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 808 { 809 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 810 mask = ~mask; 811 /* 812 * From the UFSHCI specification: "UTP Transfer Request List CLear 813 * Register (UTRLCLR): This field is bit significant. Each bit 814 * corresponds to a slot in the UTP Transfer Request List, where bit 0 815 * corresponds to request slot 0. A bit in this field is set to ‘0’ 816 * by host software to indicate to the host controller that a transfer 817 * request slot is cleared. The host controller 818 * shall free up any resources associated to the request slot 819 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 820 * host software indicates no change to request slots by setting the 821 * associated bits in this field to ‘1’. Bits in this field shall only 822 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 823 */ 824 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 825 } 826 827 /** 828 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 829 * @hba: per adapter instance 830 * @pos: position of the bit to be cleared 831 */ 832 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 833 { 834 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 835 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 836 else 837 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 838 } 839 840 /** 841 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 842 * @reg: Register value of host controller status 843 * 844 * Return: 0 on success; a positive value if failed. 845 */ 846 static inline int ufshcd_get_lists_status(u32 reg) 847 { 848 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 849 } 850 851 /** 852 * ufshcd_get_uic_cmd_result - Get the UIC command result 853 * @hba: Pointer to adapter instance 854 * 855 * This function gets the result of UIC command completion 856 * 857 * Return: 0 on success; non-zero value on error. 858 */ 859 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 860 { 861 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 862 MASK_UIC_COMMAND_RESULT; 863 } 864 865 /** 866 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 867 * @hba: Pointer to adapter instance 868 * 869 * This function gets UIC command argument3 870 * 871 * Return: 0 on success; non-zero value on error. 872 */ 873 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 874 { 875 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 876 } 877 878 /** 879 * ufshcd_get_req_rsp - returns the TR response transaction type 880 * @ucd_rsp_ptr: pointer to response UPIU 881 * 882 * Return: UPIU type. 883 */ 884 static inline enum upiu_response_transaction 885 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 886 { 887 return ucd_rsp_ptr->header.transaction_code; 888 } 889 890 /** 891 * ufshcd_is_exception_event - Check if the device raised an exception event 892 * @ucd_rsp_ptr: pointer to response UPIU 893 * 894 * The function checks if the device raised an exception event indicated in 895 * the Device Information field of response UPIU. 896 * 897 * Return: true if exception is raised, false otherwise. 898 */ 899 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 900 { 901 return ucd_rsp_ptr->header.device_information & 1; 902 } 903 904 /** 905 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 906 * @hba: per adapter instance 907 */ 908 static inline void 909 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 910 { 911 ufshcd_writel(hba, INT_AGGR_ENABLE | 912 INT_AGGR_COUNTER_AND_TIMER_RESET, 913 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 914 } 915 916 /** 917 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 918 * @hba: per adapter instance 919 * @cnt: Interrupt aggregation counter threshold 920 * @tmout: Interrupt aggregation timeout value 921 */ 922 static inline void 923 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 924 { 925 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 926 INT_AGGR_COUNTER_THLD_VAL(cnt) | 927 INT_AGGR_TIMEOUT_VAL(tmout), 928 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 929 } 930 931 /** 932 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 933 * @hba: per adapter instance 934 */ 935 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 936 { 937 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 938 } 939 940 /** 941 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 942 * When run-stop registers are set to 1, it indicates the 943 * host controller that it can process the requests 944 * @hba: per adapter instance 945 */ 946 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 947 { 948 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 949 REG_UTP_TASK_REQ_LIST_RUN_STOP); 950 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 951 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 952 } 953 954 /** 955 * ufshcd_hba_start - Start controller initialization sequence 956 * @hba: per adapter instance 957 */ 958 static inline void ufshcd_hba_start(struct ufs_hba *hba) 959 { 960 u32 val = CONTROLLER_ENABLE; 961 962 if (ufshcd_crypto_enable(hba)) 963 val |= CRYPTO_GENERAL_ENABLE; 964 965 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 966 } 967 968 /** 969 * ufshcd_is_hba_active - Get controller state 970 * @hba: per adapter instance 971 * 972 * Return: true if and only if the controller is active. 973 */ 974 bool ufshcd_is_hba_active(struct ufs_hba *hba) 975 { 976 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 977 } 978 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 979 980 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba) 981 { 982 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */ 983 if (hba->ufs_version <= ufshci_version(1, 1)) 984 return UFS_UNIPRO_VER_1_41; 985 else 986 return UFS_UNIPRO_VER_1_6; 987 } 988 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver); 989 990 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba) 991 { 992 /* 993 * If both host and device support UniPro ver1.6 or later, PA layer 994 * parameters tuning happens during link startup itself. 995 * 996 * We can manually tune PA layer parameters if either host or device 997 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning 998 * logic simple, we will only do manual tuning if local unipro version 999 * doesn't support ver1.6 or later. 1000 */ 1001 return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6; 1002 } 1003 1004 /** 1005 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1006 * @hba: per adapter instance 1007 * @scale_up: If True, set max possible frequency othewise set low frequency 1008 * 1009 * Return: 0 if successful; < 0 upon failure. 1010 */ 1011 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1012 { 1013 int ret = 0; 1014 struct ufs_clk_info *clki; 1015 struct list_head *head = &hba->clk_list_head; 1016 1017 if (list_empty(head)) 1018 goto out; 1019 1020 list_for_each_entry(clki, head, list) { 1021 if (!IS_ERR_OR_NULL(clki->clk)) { 1022 if (scale_up && clki->max_freq) { 1023 if (clki->curr_freq == clki->max_freq) 1024 continue; 1025 1026 ret = clk_set_rate(clki->clk, clki->max_freq); 1027 if (ret) { 1028 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1029 __func__, clki->name, 1030 clki->max_freq, ret); 1031 break; 1032 } 1033 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1034 "scaled up", clki->name, 1035 clki->curr_freq, 1036 clki->max_freq); 1037 1038 clki->curr_freq = clki->max_freq; 1039 1040 } else if (!scale_up && clki->min_freq) { 1041 if (clki->curr_freq == clki->min_freq) 1042 continue; 1043 1044 ret = clk_set_rate(clki->clk, clki->min_freq); 1045 if (ret) { 1046 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1047 __func__, clki->name, 1048 clki->min_freq, ret); 1049 break; 1050 } 1051 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1052 "scaled down", clki->name, 1053 clki->curr_freq, 1054 clki->min_freq); 1055 clki->curr_freq = clki->min_freq; 1056 } 1057 } 1058 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1059 clki->name, clk_get_rate(clki->clk)); 1060 } 1061 1062 out: 1063 return ret; 1064 } 1065 1066 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1067 struct dev_pm_opp *opp, void *data, 1068 bool scaling_down) 1069 { 1070 struct ufs_hba *hba = dev_get_drvdata(dev); 1071 struct list_head *head = &hba->clk_list_head; 1072 struct ufs_clk_info *clki; 1073 unsigned long freq; 1074 u8 idx = 0; 1075 int ret; 1076 1077 list_for_each_entry(clki, head, list) { 1078 if (!IS_ERR_OR_NULL(clki->clk)) { 1079 freq = dev_pm_opp_get_freq_indexed(opp, idx++); 1080 1081 /* Do not set rate for clocks having frequency as 0 */ 1082 if (!freq) 1083 continue; 1084 1085 ret = clk_set_rate(clki->clk, freq); 1086 if (ret) { 1087 dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n", 1088 __func__, clki->name, freq, ret); 1089 return ret; 1090 } 1091 1092 trace_ufshcd_clk_scaling(dev_name(dev), 1093 (scaling_down ? "scaled down" : "scaled up"), 1094 clki->name, hba->clk_scaling.target_freq, freq); 1095 } 1096 } 1097 1098 return 0; 1099 } 1100 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks); 1101 1102 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) 1103 { 1104 struct dev_pm_opp *opp; 1105 int ret; 1106 1107 opp = dev_pm_opp_find_freq_floor_indexed(hba->dev, 1108 &freq, 0); 1109 if (IS_ERR(opp)) 1110 return PTR_ERR(opp); 1111 1112 ret = dev_pm_opp_set_opp(hba->dev, opp); 1113 dev_pm_opp_put(opp); 1114 1115 return ret; 1116 } 1117 1118 /** 1119 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1120 * @hba: per adapter instance 1121 * @freq: frequency to scale 1122 * @scale_up: True if scaling up and false if scaling down 1123 * 1124 * Return: 0 if successful; < 0 upon failure. 1125 */ 1126 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 1127 bool scale_up) 1128 { 1129 int ret = 0; 1130 ktime_t start = ktime_get(); 1131 1132 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1133 if (ret) 1134 goto out; 1135 1136 if (hba->use_pm_opp) 1137 ret = ufshcd_opp_set_rate(hba, freq); 1138 else 1139 ret = ufshcd_set_clk_freq(hba, scale_up); 1140 if (ret) 1141 goto out; 1142 1143 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1144 if (ret) { 1145 if (hba->use_pm_opp) 1146 ufshcd_opp_set_rate(hba, 1147 hba->devfreq->previous_freq); 1148 else 1149 ufshcd_set_clk_freq(hba, !scale_up); 1150 } 1151 1152 out: 1153 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1154 (scale_up ? "up" : "down"), 1155 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1156 return ret; 1157 } 1158 1159 /** 1160 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1161 * @hba: per adapter instance 1162 * @freq: frequency to scale 1163 * @scale_up: True if scaling up and false if scaling down 1164 * 1165 * Return: true if scaling is required, false otherwise. 1166 */ 1167 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1168 unsigned long freq, bool scale_up) 1169 { 1170 struct ufs_clk_info *clki; 1171 struct list_head *head = &hba->clk_list_head; 1172 1173 if (list_empty(head)) 1174 return false; 1175 1176 if (hba->use_pm_opp) 1177 return freq != hba->clk_scaling.target_freq; 1178 1179 list_for_each_entry(clki, head, list) { 1180 if (!IS_ERR_OR_NULL(clki->clk)) { 1181 if (scale_up && clki->max_freq) { 1182 if (clki->curr_freq == clki->max_freq) 1183 continue; 1184 return true; 1185 } else if (!scale_up && clki->min_freq) { 1186 if (clki->curr_freq == clki->min_freq) 1187 continue; 1188 return true; 1189 } 1190 } 1191 } 1192 1193 return false; 1194 } 1195 1196 /* 1197 * Determine the number of pending commands by counting the bits in the SCSI 1198 * device budget maps. This approach has been selected because a bit is set in 1199 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1200 * flag. The host_self_blocked flag can be modified by calling 1201 * scsi_block_requests() or scsi_unblock_requests(). 1202 */ 1203 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1204 { 1205 const struct scsi_device *sdev; 1206 u32 pending = 0; 1207 1208 lockdep_assert_held(hba->host->host_lock); 1209 __shost_for_each_device(sdev, hba->host) 1210 pending += sbitmap_weight(&sdev->budget_map); 1211 1212 return pending; 1213 } 1214 1215 /* 1216 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1217 * has expired. 1218 * 1219 * Return: 0 upon success; -EBUSY upon timeout. 1220 */ 1221 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1222 u64 wait_timeout_us) 1223 { 1224 unsigned long flags; 1225 int ret = 0; 1226 u32 tm_doorbell; 1227 u32 tr_pending; 1228 bool timeout = false, do_last_check = false; 1229 ktime_t start; 1230 1231 ufshcd_hold(hba); 1232 spin_lock_irqsave(hba->host->host_lock, flags); 1233 /* 1234 * Wait for all the outstanding tasks/transfer requests. 1235 * Verify by checking the doorbell registers are clear. 1236 */ 1237 start = ktime_get(); 1238 do { 1239 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1240 ret = -EBUSY; 1241 goto out; 1242 } 1243 1244 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1245 tr_pending = ufshcd_pending_cmds(hba); 1246 if (!tm_doorbell && !tr_pending) { 1247 timeout = false; 1248 break; 1249 } else if (do_last_check) { 1250 break; 1251 } 1252 1253 spin_unlock_irqrestore(hba->host->host_lock, flags); 1254 io_schedule_timeout(msecs_to_jiffies(20)); 1255 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1256 wait_timeout_us) { 1257 timeout = true; 1258 /* 1259 * We might have scheduled out for long time so make 1260 * sure to check if doorbells are cleared by this time 1261 * or not. 1262 */ 1263 do_last_check = true; 1264 } 1265 spin_lock_irqsave(hba->host->host_lock, flags); 1266 } while (tm_doorbell || tr_pending); 1267 1268 if (timeout) { 1269 dev_err(hba->dev, 1270 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1271 __func__, tm_doorbell, tr_pending); 1272 ret = -EBUSY; 1273 } 1274 out: 1275 spin_unlock_irqrestore(hba->host->host_lock, flags); 1276 ufshcd_release(hba); 1277 return ret; 1278 } 1279 1280 /** 1281 * ufshcd_scale_gear - scale up/down UFS gear 1282 * @hba: per adapter instance 1283 * @scale_up: True for scaling up gear and false for scaling down 1284 * 1285 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1286 * non-zero for any other errors. 1287 */ 1288 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1289 { 1290 int ret = 0; 1291 struct ufs_pa_layer_attr new_pwr_info; 1292 1293 if (scale_up) { 1294 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1295 sizeof(struct ufs_pa_layer_attr)); 1296 } else { 1297 memcpy(&new_pwr_info, &hba->pwr_info, 1298 sizeof(struct ufs_pa_layer_attr)); 1299 1300 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1301 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1302 /* save the current power mode */ 1303 memcpy(&hba->clk_scaling.saved_pwr_info, 1304 &hba->pwr_info, 1305 sizeof(struct ufs_pa_layer_attr)); 1306 1307 /* scale down gear */ 1308 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1309 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1310 } 1311 } 1312 1313 /* check if the power mode needs to be changed or not? */ 1314 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1315 if (ret) 1316 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1317 __func__, ret, 1318 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1319 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1320 1321 return ret; 1322 } 1323 1324 /* 1325 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1326 * has expired. 1327 * 1328 * Return: 0 upon success; -EBUSY upon timeout. 1329 */ 1330 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1331 { 1332 int ret = 0; 1333 /* 1334 * make sure that there are no outstanding requests when 1335 * clock scaling is in progress 1336 */ 1337 ufshcd_scsi_block_requests(hba); 1338 mutex_lock(&hba->wb_mutex); 1339 down_write(&hba->clk_scaling_lock); 1340 1341 if (!hba->clk_scaling.is_allowed || 1342 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1343 ret = -EBUSY; 1344 up_write(&hba->clk_scaling_lock); 1345 mutex_unlock(&hba->wb_mutex); 1346 ufshcd_scsi_unblock_requests(hba); 1347 goto out; 1348 } 1349 1350 /* let's not get into low power until clock scaling is completed */ 1351 ufshcd_hold(hba); 1352 1353 out: 1354 return ret; 1355 } 1356 1357 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1358 { 1359 up_write(&hba->clk_scaling_lock); 1360 1361 /* Enable Write Booster if we have scaled up else disable it */ 1362 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1363 ufshcd_wb_toggle(hba, scale_up); 1364 1365 mutex_unlock(&hba->wb_mutex); 1366 1367 ufshcd_scsi_unblock_requests(hba); 1368 ufshcd_release(hba); 1369 } 1370 1371 /** 1372 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1373 * @hba: per adapter instance 1374 * @freq: frequency to scale 1375 * @scale_up: True for scaling up and false for scalin down 1376 * 1377 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1378 * for any other errors. 1379 */ 1380 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, 1381 bool scale_up) 1382 { 1383 int ret = 0; 1384 1385 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1386 if (ret) 1387 return ret; 1388 1389 /* scale down the gear before scaling down clocks */ 1390 if (!scale_up) { 1391 ret = ufshcd_scale_gear(hba, false); 1392 if (ret) 1393 goto out_unprepare; 1394 } 1395 1396 ret = ufshcd_scale_clks(hba, freq, scale_up); 1397 if (ret) { 1398 if (!scale_up) 1399 ufshcd_scale_gear(hba, true); 1400 goto out_unprepare; 1401 } 1402 1403 /* scale up the gear after scaling up clocks */ 1404 if (scale_up) { 1405 ret = ufshcd_scale_gear(hba, true); 1406 if (ret) { 1407 ufshcd_scale_clks(hba, hba->devfreq->previous_freq, 1408 false); 1409 goto out_unprepare; 1410 } 1411 } 1412 1413 out_unprepare: 1414 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1415 return ret; 1416 } 1417 1418 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1419 { 1420 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1421 clk_scaling.suspend_work); 1422 unsigned long irq_flags; 1423 1424 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1425 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1426 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1427 return; 1428 } 1429 hba->clk_scaling.is_suspended = true; 1430 hba->clk_scaling.window_start_t = 0; 1431 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1432 1433 devfreq_suspend_device(hba->devfreq); 1434 } 1435 1436 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1437 { 1438 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1439 clk_scaling.resume_work); 1440 unsigned long irq_flags; 1441 1442 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1443 if (!hba->clk_scaling.is_suspended) { 1444 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1445 return; 1446 } 1447 hba->clk_scaling.is_suspended = false; 1448 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1449 1450 devfreq_resume_device(hba->devfreq); 1451 } 1452 1453 static int ufshcd_devfreq_target(struct device *dev, 1454 unsigned long *freq, u32 flags) 1455 { 1456 int ret = 0; 1457 struct ufs_hba *hba = dev_get_drvdata(dev); 1458 ktime_t start; 1459 bool scale_up, sched_clk_scaling_suspend_work = false; 1460 struct list_head *clk_list = &hba->clk_list_head; 1461 struct ufs_clk_info *clki; 1462 unsigned long irq_flags; 1463 1464 if (!ufshcd_is_clkscaling_supported(hba)) 1465 return -EINVAL; 1466 1467 if (hba->use_pm_opp) { 1468 struct dev_pm_opp *opp; 1469 1470 /* Get the recommended frequency from OPP framework */ 1471 opp = devfreq_recommended_opp(dev, freq, flags); 1472 if (IS_ERR(opp)) 1473 return PTR_ERR(opp); 1474 1475 dev_pm_opp_put(opp); 1476 } else { 1477 /* Override with the closest supported frequency */ 1478 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, 1479 list); 1480 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1481 } 1482 1483 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1484 if (ufshcd_eh_in_progress(hba)) { 1485 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1486 return 0; 1487 } 1488 1489 /* Skip scaling clock when clock scaling is suspended */ 1490 if (hba->clk_scaling.is_suspended) { 1491 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1492 dev_warn(hba->dev, "clock scaling is suspended, skip"); 1493 return 0; 1494 } 1495 1496 if (!hba->clk_scaling.active_reqs) 1497 sched_clk_scaling_suspend_work = true; 1498 1499 if (list_empty(clk_list)) { 1500 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1501 goto out; 1502 } 1503 1504 /* Decide based on the target or rounded-off frequency and update */ 1505 if (hba->use_pm_opp) 1506 scale_up = *freq > hba->clk_scaling.target_freq; 1507 else 1508 scale_up = *freq == clki->max_freq; 1509 1510 if (!hba->use_pm_opp && !scale_up) 1511 *freq = clki->min_freq; 1512 1513 /* Update the frequency */ 1514 if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) { 1515 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1516 ret = 0; 1517 goto out; /* no state change required */ 1518 } 1519 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1520 1521 start = ktime_get(); 1522 ret = ufshcd_devfreq_scale(hba, *freq, scale_up); 1523 if (!ret) 1524 hba->clk_scaling.target_freq = *freq; 1525 1526 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1527 (scale_up ? "up" : "down"), 1528 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1529 1530 out: 1531 if (sched_clk_scaling_suspend_work && !scale_up) 1532 queue_work(hba->clk_scaling.workq, 1533 &hba->clk_scaling.suspend_work); 1534 1535 return ret; 1536 } 1537 1538 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1539 struct devfreq_dev_status *stat) 1540 { 1541 struct ufs_hba *hba = dev_get_drvdata(dev); 1542 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1543 unsigned long flags; 1544 ktime_t curr_t; 1545 1546 if (!ufshcd_is_clkscaling_supported(hba)) 1547 return -EINVAL; 1548 1549 memset(stat, 0, sizeof(*stat)); 1550 1551 spin_lock_irqsave(hba->host->host_lock, flags); 1552 curr_t = ktime_get(); 1553 if (!scaling->window_start_t) 1554 goto start_window; 1555 1556 /* 1557 * If current frequency is 0, then the ondemand governor considers 1558 * there's no initial frequency set. And it always requests to set 1559 * to max. frequency. 1560 */ 1561 if (hba->use_pm_opp) { 1562 stat->current_frequency = hba->clk_scaling.target_freq; 1563 } else { 1564 struct list_head *clk_list = &hba->clk_list_head; 1565 struct ufs_clk_info *clki; 1566 1567 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1568 stat->current_frequency = clki->curr_freq; 1569 } 1570 1571 if (scaling->is_busy_started) 1572 scaling->tot_busy_t += ktime_us_delta(curr_t, 1573 scaling->busy_start_t); 1574 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1575 stat->busy_time = scaling->tot_busy_t; 1576 start_window: 1577 scaling->window_start_t = curr_t; 1578 scaling->tot_busy_t = 0; 1579 1580 if (scaling->active_reqs) { 1581 scaling->busy_start_t = curr_t; 1582 scaling->is_busy_started = true; 1583 } else { 1584 scaling->busy_start_t = 0; 1585 scaling->is_busy_started = false; 1586 } 1587 spin_unlock_irqrestore(hba->host->host_lock, flags); 1588 return 0; 1589 } 1590 1591 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1592 { 1593 struct list_head *clk_list = &hba->clk_list_head; 1594 struct ufs_clk_info *clki; 1595 struct devfreq *devfreq; 1596 int ret; 1597 1598 /* Skip devfreq if we don't have any clocks in the list */ 1599 if (list_empty(clk_list)) 1600 return 0; 1601 1602 if (!hba->use_pm_opp) { 1603 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1604 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1605 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1606 } 1607 1608 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1609 &hba->vps->ondemand_data); 1610 devfreq = devfreq_add_device(hba->dev, 1611 &hba->vps->devfreq_profile, 1612 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1613 &hba->vps->ondemand_data); 1614 if (IS_ERR(devfreq)) { 1615 ret = PTR_ERR(devfreq); 1616 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1617 1618 if (!hba->use_pm_opp) { 1619 dev_pm_opp_remove(hba->dev, clki->min_freq); 1620 dev_pm_opp_remove(hba->dev, clki->max_freq); 1621 } 1622 return ret; 1623 } 1624 1625 hba->devfreq = devfreq; 1626 1627 return 0; 1628 } 1629 1630 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1631 { 1632 struct list_head *clk_list = &hba->clk_list_head; 1633 1634 if (!hba->devfreq) 1635 return; 1636 1637 devfreq_remove_device(hba->devfreq); 1638 hba->devfreq = NULL; 1639 1640 if (!hba->use_pm_opp) { 1641 struct ufs_clk_info *clki; 1642 1643 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1644 dev_pm_opp_remove(hba->dev, clki->min_freq); 1645 dev_pm_opp_remove(hba->dev, clki->max_freq); 1646 } 1647 } 1648 1649 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1650 { 1651 unsigned long flags; 1652 bool suspend = false; 1653 1654 cancel_work_sync(&hba->clk_scaling.suspend_work); 1655 cancel_work_sync(&hba->clk_scaling.resume_work); 1656 1657 spin_lock_irqsave(hba->host->host_lock, flags); 1658 if (!hba->clk_scaling.is_suspended) { 1659 suspend = true; 1660 hba->clk_scaling.is_suspended = true; 1661 hba->clk_scaling.window_start_t = 0; 1662 } 1663 spin_unlock_irqrestore(hba->host->host_lock, flags); 1664 1665 if (suspend) 1666 devfreq_suspend_device(hba->devfreq); 1667 } 1668 1669 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1670 { 1671 unsigned long flags; 1672 bool resume = false; 1673 1674 spin_lock_irqsave(hba->host->host_lock, flags); 1675 if (hba->clk_scaling.is_suspended) { 1676 resume = true; 1677 hba->clk_scaling.is_suspended = false; 1678 } 1679 spin_unlock_irqrestore(hba->host->host_lock, flags); 1680 1681 if (resume) 1682 devfreq_resume_device(hba->devfreq); 1683 } 1684 1685 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1686 struct device_attribute *attr, char *buf) 1687 { 1688 struct ufs_hba *hba = dev_get_drvdata(dev); 1689 1690 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1691 } 1692 1693 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1694 struct device_attribute *attr, const char *buf, size_t count) 1695 { 1696 struct ufs_hba *hba = dev_get_drvdata(dev); 1697 u32 value; 1698 int err = 0; 1699 1700 if (kstrtou32(buf, 0, &value)) 1701 return -EINVAL; 1702 1703 down(&hba->host_sem); 1704 if (!ufshcd_is_user_access_allowed(hba)) { 1705 err = -EBUSY; 1706 goto out; 1707 } 1708 1709 value = !!value; 1710 if (value == hba->clk_scaling.is_enabled) 1711 goto out; 1712 1713 ufshcd_rpm_get_sync(hba); 1714 ufshcd_hold(hba); 1715 1716 hba->clk_scaling.is_enabled = value; 1717 1718 if (value) { 1719 ufshcd_resume_clkscaling(hba); 1720 } else { 1721 ufshcd_suspend_clkscaling(hba); 1722 err = ufshcd_devfreq_scale(hba, ULONG_MAX, true); 1723 if (err) 1724 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1725 __func__, err); 1726 } 1727 1728 ufshcd_release(hba); 1729 ufshcd_rpm_put_sync(hba); 1730 out: 1731 up(&hba->host_sem); 1732 return err ? err : count; 1733 } 1734 1735 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1736 { 1737 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1738 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1739 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1740 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1741 hba->clk_scaling.enable_attr.attr.mode = 0644; 1742 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1743 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1744 } 1745 1746 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1747 { 1748 if (hba->clk_scaling.enable_attr.attr.name) 1749 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1750 } 1751 1752 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1753 { 1754 char wq_name[sizeof("ufs_clkscaling_00")]; 1755 1756 if (!ufshcd_is_clkscaling_supported(hba)) 1757 return; 1758 1759 if (!hba->clk_scaling.min_gear) 1760 hba->clk_scaling.min_gear = UFS_HS_G1; 1761 1762 INIT_WORK(&hba->clk_scaling.suspend_work, 1763 ufshcd_clk_scaling_suspend_work); 1764 INIT_WORK(&hba->clk_scaling.resume_work, 1765 ufshcd_clk_scaling_resume_work); 1766 1767 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d", 1768 hba->host->host_no); 1769 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name); 1770 1771 hba->clk_scaling.is_initialized = true; 1772 } 1773 1774 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1775 { 1776 if (!hba->clk_scaling.is_initialized) 1777 return; 1778 1779 ufshcd_remove_clk_scaling_sysfs(hba); 1780 destroy_workqueue(hba->clk_scaling.workq); 1781 ufshcd_devfreq_remove(hba); 1782 hba->clk_scaling.is_initialized = false; 1783 } 1784 1785 static void ufshcd_ungate_work(struct work_struct *work) 1786 { 1787 int ret; 1788 unsigned long flags; 1789 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1790 clk_gating.ungate_work); 1791 1792 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1793 1794 spin_lock_irqsave(hba->host->host_lock, flags); 1795 if (hba->clk_gating.state == CLKS_ON) { 1796 spin_unlock_irqrestore(hba->host->host_lock, flags); 1797 return; 1798 } 1799 1800 spin_unlock_irqrestore(hba->host->host_lock, flags); 1801 ufshcd_hba_vreg_set_hpm(hba); 1802 ufshcd_setup_clocks(hba, true); 1803 1804 ufshcd_enable_irq(hba); 1805 1806 /* Exit from hibern8 */ 1807 if (ufshcd_can_hibern8_during_gating(hba)) { 1808 /* Prevent gating in this path */ 1809 hba->clk_gating.is_suspended = true; 1810 if (ufshcd_is_link_hibern8(hba)) { 1811 ret = ufshcd_uic_hibern8_exit(hba); 1812 if (ret) 1813 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1814 __func__, ret); 1815 else 1816 ufshcd_set_link_active(hba); 1817 } 1818 hba->clk_gating.is_suspended = false; 1819 } 1820 } 1821 1822 /** 1823 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1824 * Also, exit from hibern8 mode and set the link as active. 1825 * @hba: per adapter instance 1826 */ 1827 void ufshcd_hold(struct ufs_hba *hba) 1828 { 1829 bool flush_result; 1830 unsigned long flags; 1831 1832 if (!ufshcd_is_clkgating_allowed(hba) || 1833 !hba->clk_gating.is_initialized) 1834 return; 1835 spin_lock_irqsave(hba->host->host_lock, flags); 1836 hba->clk_gating.active_reqs++; 1837 1838 start: 1839 switch (hba->clk_gating.state) { 1840 case CLKS_ON: 1841 /* 1842 * Wait for the ungate work to complete if in progress. 1843 * Though the clocks may be in ON state, the link could 1844 * still be in hibner8 state if hibern8 is allowed 1845 * during clock gating. 1846 * Make sure we exit hibern8 state also in addition to 1847 * clocks being ON. 1848 */ 1849 if (ufshcd_can_hibern8_during_gating(hba) && 1850 ufshcd_is_link_hibern8(hba)) { 1851 spin_unlock_irqrestore(hba->host->host_lock, flags); 1852 flush_result = flush_work(&hba->clk_gating.ungate_work); 1853 if (hba->clk_gating.is_suspended && !flush_result) 1854 return; 1855 spin_lock_irqsave(hba->host->host_lock, flags); 1856 goto start; 1857 } 1858 break; 1859 case REQ_CLKS_OFF: 1860 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1861 hba->clk_gating.state = CLKS_ON; 1862 trace_ufshcd_clk_gating(dev_name(hba->dev), 1863 hba->clk_gating.state); 1864 break; 1865 } 1866 /* 1867 * If we are here, it means gating work is either done or 1868 * currently running. Hence, fall through to cancel gating 1869 * work and to enable clocks. 1870 */ 1871 fallthrough; 1872 case CLKS_OFF: 1873 hba->clk_gating.state = REQ_CLKS_ON; 1874 trace_ufshcd_clk_gating(dev_name(hba->dev), 1875 hba->clk_gating.state); 1876 queue_work(hba->clk_gating.clk_gating_workq, 1877 &hba->clk_gating.ungate_work); 1878 /* 1879 * fall through to check if we should wait for this 1880 * work to be done or not. 1881 */ 1882 fallthrough; 1883 case REQ_CLKS_ON: 1884 spin_unlock_irqrestore(hba->host->host_lock, flags); 1885 flush_work(&hba->clk_gating.ungate_work); 1886 /* Make sure state is CLKS_ON before returning */ 1887 spin_lock_irqsave(hba->host->host_lock, flags); 1888 goto start; 1889 default: 1890 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1891 __func__, hba->clk_gating.state); 1892 break; 1893 } 1894 spin_unlock_irqrestore(hba->host->host_lock, flags); 1895 } 1896 EXPORT_SYMBOL_GPL(ufshcd_hold); 1897 1898 static void ufshcd_gate_work(struct work_struct *work) 1899 { 1900 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1901 clk_gating.gate_work.work); 1902 unsigned long flags; 1903 int ret; 1904 1905 spin_lock_irqsave(hba->host->host_lock, flags); 1906 /* 1907 * In case you are here to cancel this work the gating state 1908 * would be marked as REQ_CLKS_ON. In this case save time by 1909 * skipping the gating work and exit after changing the clock 1910 * state to CLKS_ON. 1911 */ 1912 if (hba->clk_gating.is_suspended || 1913 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1914 hba->clk_gating.state = CLKS_ON; 1915 trace_ufshcd_clk_gating(dev_name(hba->dev), 1916 hba->clk_gating.state); 1917 goto rel_lock; 1918 } 1919 1920 if (hba->clk_gating.active_reqs 1921 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL 1922 || hba->outstanding_reqs || hba->outstanding_tasks 1923 || hba->active_uic_cmd || hba->uic_async_done) 1924 goto rel_lock; 1925 1926 spin_unlock_irqrestore(hba->host->host_lock, flags); 1927 1928 /* put the link into hibern8 mode before turning off clocks */ 1929 if (ufshcd_can_hibern8_during_gating(hba)) { 1930 ret = ufshcd_uic_hibern8_enter(hba); 1931 if (ret) { 1932 hba->clk_gating.state = CLKS_ON; 1933 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1934 __func__, ret); 1935 trace_ufshcd_clk_gating(dev_name(hba->dev), 1936 hba->clk_gating.state); 1937 goto out; 1938 } 1939 ufshcd_set_link_hibern8(hba); 1940 } 1941 1942 ufshcd_disable_irq(hba); 1943 1944 ufshcd_setup_clocks(hba, false); 1945 1946 /* Put the host controller in low power mode if possible */ 1947 ufshcd_hba_vreg_set_lpm(hba); 1948 /* 1949 * In case you are here to cancel this work the gating state 1950 * would be marked as REQ_CLKS_ON. In this case keep the state 1951 * as REQ_CLKS_ON which would anyway imply that clocks are off 1952 * and a request to turn them on is pending. By doing this way, 1953 * we keep the state machine in tact and this would ultimately 1954 * prevent from doing cancel work multiple times when there are 1955 * new requests arriving before the current cancel work is done. 1956 */ 1957 spin_lock_irqsave(hba->host->host_lock, flags); 1958 if (hba->clk_gating.state == REQ_CLKS_OFF) { 1959 hba->clk_gating.state = CLKS_OFF; 1960 trace_ufshcd_clk_gating(dev_name(hba->dev), 1961 hba->clk_gating.state); 1962 } 1963 rel_lock: 1964 spin_unlock_irqrestore(hba->host->host_lock, flags); 1965 out: 1966 return; 1967 } 1968 1969 /* host lock must be held before calling this variant */ 1970 static void __ufshcd_release(struct ufs_hba *hba) 1971 { 1972 if (!ufshcd_is_clkgating_allowed(hba)) 1973 return; 1974 1975 hba->clk_gating.active_reqs--; 1976 1977 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 1978 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 1979 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 1980 hba->active_uic_cmd || hba->uic_async_done || 1981 hba->clk_gating.state == CLKS_OFF) 1982 return; 1983 1984 hba->clk_gating.state = REQ_CLKS_OFF; 1985 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 1986 queue_delayed_work(hba->clk_gating.clk_gating_workq, 1987 &hba->clk_gating.gate_work, 1988 msecs_to_jiffies(hba->clk_gating.delay_ms)); 1989 } 1990 1991 void ufshcd_release(struct ufs_hba *hba) 1992 { 1993 unsigned long flags; 1994 1995 spin_lock_irqsave(hba->host->host_lock, flags); 1996 __ufshcd_release(hba); 1997 spin_unlock_irqrestore(hba->host->host_lock, flags); 1998 } 1999 EXPORT_SYMBOL_GPL(ufshcd_release); 2000 2001 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 2002 struct device_attribute *attr, char *buf) 2003 { 2004 struct ufs_hba *hba = dev_get_drvdata(dev); 2005 2006 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 2007 } 2008 2009 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 2010 { 2011 struct ufs_hba *hba = dev_get_drvdata(dev); 2012 unsigned long flags; 2013 2014 spin_lock_irqsave(hba->host->host_lock, flags); 2015 hba->clk_gating.delay_ms = value; 2016 spin_unlock_irqrestore(hba->host->host_lock, flags); 2017 } 2018 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 2019 2020 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 2021 struct device_attribute *attr, const char *buf, size_t count) 2022 { 2023 unsigned long value; 2024 2025 if (kstrtoul(buf, 0, &value)) 2026 return -EINVAL; 2027 2028 ufshcd_clkgate_delay_set(dev, value); 2029 return count; 2030 } 2031 2032 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 2033 struct device_attribute *attr, char *buf) 2034 { 2035 struct ufs_hba *hba = dev_get_drvdata(dev); 2036 2037 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 2038 } 2039 2040 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 2041 struct device_attribute *attr, const char *buf, size_t count) 2042 { 2043 struct ufs_hba *hba = dev_get_drvdata(dev); 2044 unsigned long flags; 2045 u32 value; 2046 2047 if (kstrtou32(buf, 0, &value)) 2048 return -EINVAL; 2049 2050 value = !!value; 2051 2052 spin_lock_irqsave(hba->host->host_lock, flags); 2053 if (value == hba->clk_gating.is_enabled) 2054 goto out; 2055 2056 if (value) 2057 __ufshcd_release(hba); 2058 else 2059 hba->clk_gating.active_reqs++; 2060 2061 hba->clk_gating.is_enabled = value; 2062 out: 2063 spin_unlock_irqrestore(hba->host->host_lock, flags); 2064 return count; 2065 } 2066 2067 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 2068 { 2069 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 2070 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 2071 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 2072 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 2073 hba->clk_gating.delay_attr.attr.mode = 0644; 2074 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 2075 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 2076 2077 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 2078 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 2079 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 2080 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 2081 hba->clk_gating.enable_attr.attr.mode = 0644; 2082 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 2083 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 2084 } 2085 2086 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 2087 { 2088 if (hba->clk_gating.delay_attr.attr.name) 2089 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 2090 if (hba->clk_gating.enable_attr.attr.name) 2091 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 2092 } 2093 2094 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 2095 { 2096 char wq_name[sizeof("ufs_clk_gating_00")]; 2097 2098 if (!ufshcd_is_clkgating_allowed(hba)) 2099 return; 2100 2101 hba->clk_gating.state = CLKS_ON; 2102 2103 hba->clk_gating.delay_ms = 150; 2104 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2105 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2106 2107 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d", 2108 hba->host->host_no); 2109 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name, 2110 WQ_MEM_RECLAIM | WQ_HIGHPRI); 2111 2112 ufshcd_init_clk_gating_sysfs(hba); 2113 2114 hba->clk_gating.is_enabled = true; 2115 hba->clk_gating.is_initialized = true; 2116 } 2117 2118 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2119 { 2120 if (!hba->clk_gating.is_initialized) 2121 return; 2122 2123 ufshcd_remove_clk_gating_sysfs(hba); 2124 2125 /* Ungate the clock if necessary. */ 2126 ufshcd_hold(hba); 2127 hba->clk_gating.is_initialized = false; 2128 ufshcd_release(hba); 2129 2130 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2131 } 2132 2133 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2134 { 2135 bool queue_resume_work = false; 2136 ktime_t curr_t = ktime_get(); 2137 unsigned long flags; 2138 2139 if (!ufshcd_is_clkscaling_supported(hba)) 2140 return; 2141 2142 spin_lock_irqsave(hba->host->host_lock, flags); 2143 if (!hba->clk_scaling.active_reqs++) 2144 queue_resume_work = true; 2145 2146 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2147 spin_unlock_irqrestore(hba->host->host_lock, flags); 2148 return; 2149 } 2150 2151 if (queue_resume_work) 2152 queue_work(hba->clk_scaling.workq, 2153 &hba->clk_scaling.resume_work); 2154 2155 if (!hba->clk_scaling.window_start_t) { 2156 hba->clk_scaling.window_start_t = curr_t; 2157 hba->clk_scaling.tot_busy_t = 0; 2158 hba->clk_scaling.is_busy_started = false; 2159 } 2160 2161 if (!hba->clk_scaling.is_busy_started) { 2162 hba->clk_scaling.busy_start_t = curr_t; 2163 hba->clk_scaling.is_busy_started = true; 2164 } 2165 spin_unlock_irqrestore(hba->host->host_lock, flags); 2166 } 2167 2168 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2169 { 2170 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2171 unsigned long flags; 2172 2173 if (!ufshcd_is_clkscaling_supported(hba)) 2174 return; 2175 2176 spin_lock_irqsave(hba->host->host_lock, flags); 2177 hba->clk_scaling.active_reqs--; 2178 if (!scaling->active_reqs && scaling->is_busy_started) { 2179 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2180 scaling->busy_start_t)); 2181 scaling->busy_start_t = 0; 2182 scaling->is_busy_started = false; 2183 } 2184 spin_unlock_irqrestore(hba->host->host_lock, flags); 2185 } 2186 2187 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2188 { 2189 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2190 return READ; 2191 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2192 return WRITE; 2193 else 2194 return -EINVAL; 2195 } 2196 2197 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2198 struct ufshcd_lrb *lrbp) 2199 { 2200 const struct ufs_hba_monitor *m = &hba->monitor; 2201 2202 return (m->enabled && lrbp && lrbp->cmd && 2203 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2204 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2205 } 2206 2207 static void ufshcd_start_monitor(struct ufs_hba *hba, 2208 const struct ufshcd_lrb *lrbp) 2209 { 2210 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2211 unsigned long flags; 2212 2213 spin_lock_irqsave(hba->host->host_lock, flags); 2214 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2215 hba->monitor.busy_start_ts[dir] = ktime_get(); 2216 spin_unlock_irqrestore(hba->host->host_lock, flags); 2217 } 2218 2219 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2220 { 2221 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2222 unsigned long flags; 2223 2224 spin_lock_irqsave(hba->host->host_lock, flags); 2225 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2226 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2227 struct ufs_hba_monitor *m = &hba->monitor; 2228 ktime_t now, inc, lat; 2229 2230 now = lrbp->compl_time_stamp; 2231 inc = ktime_sub(now, m->busy_start_ts[dir]); 2232 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2233 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2234 2235 /* Update latencies */ 2236 m->nr_req[dir]++; 2237 lat = ktime_sub(now, lrbp->issue_time_stamp); 2238 m->lat_sum[dir] += lat; 2239 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2240 m->lat_max[dir] = lat; 2241 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2242 m->lat_min[dir] = lat; 2243 2244 m->nr_queued[dir]--; 2245 /* Push forward the busy start of monitor */ 2246 m->busy_start_ts[dir] = now; 2247 } 2248 spin_unlock_irqrestore(hba->host->host_lock, flags); 2249 } 2250 2251 /** 2252 * ufshcd_send_command - Send SCSI or device management commands 2253 * @hba: per adapter instance 2254 * @task_tag: Task tag of the command 2255 * @hwq: pointer to hardware queue instance 2256 */ 2257 static inline 2258 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2259 struct ufs_hw_queue *hwq) 2260 { 2261 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2262 unsigned long flags; 2263 2264 lrbp->issue_time_stamp = ktime_get(); 2265 lrbp->issue_time_stamp_local_clock = local_clock(); 2266 lrbp->compl_time_stamp = ktime_set(0, 0); 2267 lrbp->compl_time_stamp_local_clock = 0; 2268 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2269 if (lrbp->cmd) 2270 ufshcd_clk_scaling_start_busy(hba); 2271 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2272 ufshcd_start_monitor(hba, lrbp); 2273 2274 if (is_mcq_enabled(hba)) { 2275 int utrd_size = sizeof(struct utp_transfer_req_desc); 2276 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2277 struct utp_transfer_req_desc *dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2278 2279 spin_lock(&hwq->sq_lock); 2280 memcpy(dest, src, utrd_size); 2281 ufshcd_inc_sq_tail(hwq); 2282 spin_unlock(&hwq->sq_lock); 2283 } else { 2284 spin_lock_irqsave(&hba->outstanding_lock, flags); 2285 if (hba->vops && hba->vops->setup_xfer_req) 2286 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2287 !!lrbp->cmd); 2288 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2289 ufshcd_writel(hba, 1 << lrbp->task_tag, 2290 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2291 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2292 } 2293 } 2294 2295 /** 2296 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2297 * @lrbp: pointer to local reference block 2298 */ 2299 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2300 { 2301 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2302 u16 resp_len; 2303 int len; 2304 2305 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2306 if (sense_buffer && resp_len) { 2307 int len_to_copy; 2308 2309 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2310 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2311 2312 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2313 len_to_copy); 2314 } 2315 } 2316 2317 /** 2318 * ufshcd_copy_query_response() - Copy the Query Response and the data 2319 * descriptor 2320 * @hba: per adapter instance 2321 * @lrbp: pointer to local reference block 2322 * 2323 * Return: 0 upon success; < 0 upon failure. 2324 */ 2325 static 2326 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2327 { 2328 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2329 2330 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2331 2332 /* Get the descriptor */ 2333 if (hba->dev_cmd.query.descriptor && 2334 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2335 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2336 GENERAL_UPIU_REQUEST_SIZE; 2337 u16 resp_len; 2338 u16 buf_len; 2339 2340 /* data segment length */ 2341 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2342 .data_segment_length); 2343 buf_len = be16_to_cpu( 2344 hba->dev_cmd.query.request.upiu_req.length); 2345 if (likely(buf_len >= resp_len)) { 2346 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2347 } else { 2348 dev_warn(hba->dev, 2349 "%s: rsp size %d is bigger than buffer size %d", 2350 __func__, resp_len, buf_len); 2351 return -EINVAL; 2352 } 2353 } 2354 2355 return 0; 2356 } 2357 2358 /** 2359 * ufshcd_hba_capabilities - Read controller capabilities 2360 * @hba: per adapter instance 2361 * 2362 * Return: 0 on success, negative on error. 2363 */ 2364 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2365 { 2366 int err; 2367 2368 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2369 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) 2370 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT; 2371 2372 /* nutrs and nutmrs are 0 based values */ 2373 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1; 2374 hba->nutmrs = 2375 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2376 hba->reserved_slot = hba->nutrs - 1; 2377 2378 /* Read crypto capabilities */ 2379 err = ufshcd_hba_init_crypto_capabilities(hba); 2380 if (err) { 2381 dev_err(hba->dev, "crypto setup failed\n"); 2382 return err; 2383 } 2384 2385 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2386 if (!hba->mcq_sup) 2387 return 0; 2388 2389 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2390 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2391 hba->mcq_capabilities); 2392 2393 return 0; 2394 } 2395 2396 /** 2397 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2398 * to accept UIC commands 2399 * @hba: per adapter instance 2400 * 2401 * Return: true on success, else false. 2402 */ 2403 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2404 { 2405 u32 val; 2406 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2407 500, UIC_CMD_TIMEOUT * 1000, false, hba, 2408 REG_CONTROLLER_STATUS); 2409 return ret == 0; 2410 } 2411 2412 /** 2413 * ufshcd_get_upmcrs - Get the power mode change request status 2414 * @hba: Pointer to adapter instance 2415 * 2416 * This function gets the UPMCRS field of HCS register 2417 * 2418 * Return: value of UPMCRS field. 2419 */ 2420 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2421 { 2422 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2423 } 2424 2425 /** 2426 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2427 * @hba: per adapter instance 2428 * @uic_cmd: UIC command 2429 */ 2430 static inline void 2431 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2432 { 2433 lockdep_assert_held(&hba->uic_cmd_mutex); 2434 2435 WARN_ON(hba->active_uic_cmd); 2436 2437 hba->active_uic_cmd = uic_cmd; 2438 2439 /* Write Args */ 2440 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2441 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2442 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2443 2444 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2445 2446 /* Write UIC Cmd */ 2447 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2448 REG_UIC_COMMAND); 2449 } 2450 2451 /** 2452 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2453 * @hba: per adapter instance 2454 * @uic_cmd: UIC command 2455 * 2456 * Return: 0 only if success. 2457 */ 2458 static int 2459 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2460 { 2461 int ret; 2462 unsigned long flags; 2463 2464 lockdep_assert_held(&hba->uic_cmd_mutex); 2465 2466 if (wait_for_completion_timeout(&uic_cmd->done, 2467 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 2468 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2469 } else { 2470 ret = -ETIMEDOUT; 2471 dev_err(hba->dev, 2472 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2473 uic_cmd->command, uic_cmd->argument3); 2474 2475 if (!uic_cmd->cmd_active) { 2476 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2477 __func__); 2478 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2479 } 2480 } 2481 2482 spin_lock_irqsave(hba->host->host_lock, flags); 2483 hba->active_uic_cmd = NULL; 2484 spin_unlock_irqrestore(hba->host->host_lock, flags); 2485 2486 return ret; 2487 } 2488 2489 /** 2490 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2491 * @hba: per adapter instance 2492 * @uic_cmd: UIC command 2493 * @completion: initialize the completion only if this is set to true 2494 * 2495 * Return: 0 only if success. 2496 */ 2497 static int 2498 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd, 2499 bool completion) 2500 { 2501 lockdep_assert_held(&hba->uic_cmd_mutex); 2502 2503 if (!ufshcd_ready_for_uic_cmd(hba)) { 2504 dev_err(hba->dev, 2505 "Controller not ready to accept UIC commands\n"); 2506 return -EIO; 2507 } 2508 2509 if (completion) 2510 init_completion(&uic_cmd->done); 2511 2512 uic_cmd->cmd_active = 1; 2513 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2514 2515 return 0; 2516 } 2517 2518 /** 2519 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2520 * @hba: per adapter instance 2521 * @uic_cmd: UIC command 2522 * 2523 * Return: 0 only if success. 2524 */ 2525 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2526 { 2527 int ret; 2528 2529 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2530 return 0; 2531 2532 ufshcd_hold(hba); 2533 mutex_lock(&hba->uic_cmd_mutex); 2534 ufshcd_add_delay_before_dme_cmd(hba); 2535 2536 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true); 2537 if (!ret) 2538 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2539 2540 mutex_unlock(&hba->uic_cmd_mutex); 2541 2542 ufshcd_release(hba); 2543 return ret; 2544 } 2545 2546 /** 2547 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2548 * @hba: per-adapter instance 2549 * @lrbp: pointer to local reference block 2550 * @sg_entries: The number of sg lists actually used 2551 * @sg_list: Pointer to SG list 2552 */ 2553 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2554 struct scatterlist *sg_list) 2555 { 2556 struct ufshcd_sg_entry *prd; 2557 struct scatterlist *sg; 2558 int i; 2559 2560 if (sg_entries) { 2561 2562 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2563 lrbp->utr_descriptor_ptr->prd_table_length = 2564 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2565 else 2566 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2567 2568 prd = lrbp->ucd_prdt_ptr; 2569 2570 for_each_sg(sg_list, sg, sg_entries, i) { 2571 const unsigned int len = sg_dma_len(sg); 2572 2573 /* 2574 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2575 * based value that indicates the length, in bytes, of 2576 * the data block. A maximum of length of 256KB may 2577 * exist for any entry. Bits 1:0 of this field shall be 2578 * 11b to indicate Dword granularity. A value of '3' 2579 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2580 */ 2581 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2582 prd->size = cpu_to_le32(len - 1); 2583 prd->addr = cpu_to_le64(sg->dma_address); 2584 prd->reserved = 0; 2585 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2586 } 2587 } else { 2588 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2589 } 2590 } 2591 2592 /** 2593 * ufshcd_map_sg - Map scatter-gather list to prdt 2594 * @hba: per adapter instance 2595 * @lrbp: pointer to local reference block 2596 * 2597 * Return: 0 in case of success, non-zero value in case of failure. 2598 */ 2599 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2600 { 2601 struct scsi_cmnd *cmd = lrbp->cmd; 2602 int sg_segments = scsi_dma_map(cmd); 2603 2604 if (sg_segments < 0) 2605 return sg_segments; 2606 2607 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2608 2609 return 0; 2610 } 2611 2612 /** 2613 * ufshcd_enable_intr - enable interrupts 2614 * @hba: per adapter instance 2615 * @intrs: interrupt bits 2616 */ 2617 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2618 { 2619 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2620 2621 if (hba->ufs_version == ufshci_version(1, 0)) { 2622 u32 rw; 2623 rw = set & INTERRUPT_MASK_RW_VER_10; 2624 set = rw | ((set ^ intrs) & intrs); 2625 } else { 2626 set |= intrs; 2627 } 2628 2629 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2630 } 2631 2632 /** 2633 * ufshcd_disable_intr - disable interrupts 2634 * @hba: per adapter instance 2635 * @intrs: interrupt bits 2636 */ 2637 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2638 { 2639 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2640 2641 if (hba->ufs_version == ufshci_version(1, 0)) { 2642 u32 rw; 2643 rw = (set & INTERRUPT_MASK_RW_VER_10) & 2644 ~(intrs & INTERRUPT_MASK_RW_VER_10); 2645 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10); 2646 2647 } else { 2648 set &= ~intrs; 2649 } 2650 2651 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2652 } 2653 2654 /** 2655 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2656 * descriptor according to request 2657 * @lrbp: pointer to local reference block 2658 * @upiu_flags: flags required in the header 2659 * @cmd_dir: requests data direction 2660 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2661 */ 2662 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, u8 *upiu_flags, 2663 enum dma_data_direction cmd_dir, int ehs_length) 2664 { 2665 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2666 struct request_desc_header *h = &req_desc->header; 2667 enum utp_data_direction data_direction; 2668 2669 *h = (typeof(*h)){ }; 2670 2671 if (cmd_dir == DMA_FROM_DEVICE) { 2672 data_direction = UTP_DEVICE_TO_HOST; 2673 *upiu_flags = UPIU_CMD_FLAGS_READ; 2674 } else if (cmd_dir == DMA_TO_DEVICE) { 2675 data_direction = UTP_HOST_TO_DEVICE; 2676 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2677 } else { 2678 data_direction = UTP_NO_DATA_TRANSFER; 2679 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2680 } 2681 2682 h->command_type = lrbp->command_type; 2683 h->data_direction = data_direction; 2684 h->ehs_length = ehs_length; 2685 2686 if (lrbp->intr_cmd) 2687 h->interrupt = 1; 2688 2689 /* Prepare crypto related dwords */ 2690 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2691 2692 /* 2693 * assigning invalid value for command status. Controller 2694 * updates OCS on command completion, with the command 2695 * status 2696 */ 2697 h->ocs = OCS_INVALID_COMMAND_STATUS; 2698 2699 req_desc->prd_table_length = 0; 2700 } 2701 2702 /** 2703 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2704 * for scsi commands 2705 * @lrbp: local reference block pointer 2706 * @upiu_flags: flags 2707 */ 2708 static 2709 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2710 { 2711 struct scsi_cmnd *cmd = lrbp->cmd; 2712 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2713 unsigned short cdb_len; 2714 2715 ucd_req_ptr->header = (struct utp_upiu_header){ 2716 .transaction_code = UPIU_TRANSACTION_COMMAND, 2717 .flags = upiu_flags, 2718 .lun = lrbp->lun, 2719 .task_tag = lrbp->task_tag, 2720 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2721 }; 2722 2723 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2724 2725 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2726 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 2727 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2728 2729 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2730 } 2731 2732 /** 2733 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2734 * @hba: UFS hba 2735 * @lrbp: local reference block pointer 2736 * @upiu_flags: flags 2737 */ 2738 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2739 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2740 { 2741 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2742 struct ufs_query *query = &hba->dev_cmd.query; 2743 u16 len = be16_to_cpu(query->request.upiu_req.length); 2744 2745 /* Query request header */ 2746 ucd_req_ptr->header = (struct utp_upiu_header){ 2747 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2748 .flags = upiu_flags, 2749 .lun = lrbp->lun, 2750 .task_tag = lrbp->task_tag, 2751 .query_function = query->request.query_func, 2752 /* Data segment length only need for WRITE_DESC */ 2753 .data_segment_length = 2754 query->request.upiu_req.opcode == 2755 UPIU_QUERY_OPCODE_WRITE_DESC ? 2756 cpu_to_be16(len) : 2757 0, 2758 }; 2759 2760 /* Copy the Query Request buffer as is */ 2761 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2762 QUERY_OSF_SIZE); 2763 2764 /* Copy the Descriptor */ 2765 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2766 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2767 2768 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2769 } 2770 2771 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2772 { 2773 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2774 2775 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2776 2777 ucd_req_ptr->header = (struct utp_upiu_header){ 2778 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2779 .task_tag = lrbp->task_tag, 2780 }; 2781 2782 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2783 } 2784 2785 /** 2786 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2787 * for Device Management Purposes 2788 * @hba: per adapter instance 2789 * @lrbp: pointer to local reference block 2790 * 2791 * Return: 0 upon success; < 0 upon failure. 2792 */ 2793 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2794 struct ufshcd_lrb *lrbp) 2795 { 2796 u8 upiu_flags; 2797 int ret = 0; 2798 2799 if (hba->ufs_version <= ufshci_version(1, 1)) 2800 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; 2801 else 2802 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2803 2804 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0); 2805 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2806 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2807 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2808 ufshcd_prepare_utp_nop_upiu(lrbp); 2809 else 2810 ret = -EINVAL; 2811 2812 return ret; 2813 } 2814 2815 /** 2816 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2817 * for SCSI Purposes 2818 * @hba: per adapter instance 2819 * @lrbp: pointer to local reference block 2820 */ 2821 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2822 { 2823 struct request *rq = scsi_cmd_to_rq(lrbp->cmd); 2824 unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq)); 2825 u8 upiu_flags; 2826 2827 if (hba->ufs_version <= ufshci_version(1, 1)) 2828 lrbp->command_type = UTP_CMD_TYPE_SCSI; 2829 else 2830 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2831 2832 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, 2833 lrbp->cmd->sc_data_direction, 0); 2834 if (ioprio_class == IOPRIO_CLASS_RT) 2835 upiu_flags |= UPIU_CMD_FLAGS_CP; 2836 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2837 } 2838 2839 /** 2840 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2841 * @upiu_wlun_id: UPIU W-LUN id 2842 * 2843 * Return: SCSI W-LUN id. 2844 */ 2845 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2846 { 2847 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2848 } 2849 2850 static inline bool is_device_wlun(struct scsi_device *sdev) 2851 { 2852 return sdev->lun == 2853 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2854 } 2855 2856 /* 2857 * Associate the UFS controller queue with the default and poll HCTX types. 2858 * Initialize the mq_map[] arrays. 2859 */ 2860 static void ufshcd_map_queues(struct Scsi_Host *shost) 2861 { 2862 struct ufs_hba *hba = shost_priv(shost); 2863 int i, queue_offset = 0; 2864 2865 if (!is_mcq_supported(hba)) { 2866 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2867 hba->nr_queues[HCTX_TYPE_READ] = 0; 2868 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2869 hba->nr_hw_queues = 1; 2870 } 2871 2872 for (i = 0; i < shost->nr_maps; i++) { 2873 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2874 2875 map->nr_queues = hba->nr_queues[i]; 2876 if (!map->nr_queues) 2877 continue; 2878 map->queue_offset = queue_offset; 2879 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2880 map->queue_offset = 0; 2881 2882 blk_mq_map_queues(map); 2883 queue_offset += map->nr_queues; 2884 } 2885 } 2886 2887 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2888 { 2889 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2890 i * ufshcd_get_ucd_size(hba); 2891 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2892 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2893 i * ufshcd_get_ucd_size(hba); 2894 u16 response_offset = offsetof(struct utp_transfer_cmd_desc, 2895 response_upiu); 2896 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 2897 2898 lrb->utr_descriptor_ptr = utrdlp + i; 2899 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2900 i * sizeof(struct utp_transfer_req_desc); 2901 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2902 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2903 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2904 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2905 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2906 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2907 } 2908 2909 /** 2910 * ufshcd_queuecommand - main entry point for SCSI requests 2911 * @host: SCSI host pointer 2912 * @cmd: command from SCSI Midlayer 2913 * 2914 * Return: 0 for success, non-zero in case of failure. 2915 */ 2916 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2917 { 2918 struct ufs_hba *hba = shost_priv(host); 2919 int tag = scsi_cmd_to_rq(cmd)->tag; 2920 struct ufshcd_lrb *lrbp; 2921 int err = 0; 2922 struct ufs_hw_queue *hwq = NULL; 2923 2924 switch (hba->ufshcd_state) { 2925 case UFSHCD_STATE_OPERATIONAL: 2926 break; 2927 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2928 /* 2929 * SCSI error handler can call ->queuecommand() while UFS error 2930 * handler is in progress. Error interrupts could change the 2931 * state from UFSHCD_STATE_RESET to 2932 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2933 * being issued in that case. 2934 */ 2935 if (ufshcd_eh_in_progress(hba)) { 2936 err = SCSI_MLQUEUE_HOST_BUSY; 2937 goto out; 2938 } 2939 break; 2940 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2941 /* 2942 * pm_runtime_get_sync() is used at error handling preparation 2943 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2944 * PM ops, it can never be finished if we let SCSI layer keep 2945 * retrying it, which gets err handler stuck forever. Neither 2946 * can we let the scsi cmd pass through, because UFS is in bad 2947 * state, the scsi cmd may eventually time out, which will get 2948 * err handler blocked for too long. So, just fail the scsi cmd 2949 * sent from PM ops, err handler can recover PM error anyways. 2950 */ 2951 if (hba->pm_op_in_progress) { 2952 hba->force_reset = true; 2953 set_host_byte(cmd, DID_BAD_TARGET); 2954 scsi_done(cmd); 2955 goto out; 2956 } 2957 fallthrough; 2958 case UFSHCD_STATE_RESET: 2959 err = SCSI_MLQUEUE_HOST_BUSY; 2960 goto out; 2961 case UFSHCD_STATE_ERROR: 2962 set_host_byte(cmd, DID_ERROR); 2963 scsi_done(cmd); 2964 goto out; 2965 } 2966 2967 hba->req_abort_count = 0; 2968 2969 ufshcd_hold(hba); 2970 2971 lrbp = &hba->lrb[tag]; 2972 lrbp->cmd = cmd; 2973 lrbp->task_tag = tag; 2974 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 2975 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 2976 2977 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp); 2978 2979 lrbp->req_abort_skip = false; 2980 2981 ufshcd_comp_scsi_upiu(hba, lrbp); 2982 2983 err = ufshcd_map_sg(hba, lrbp); 2984 if (err) { 2985 ufshcd_release(hba); 2986 goto out; 2987 } 2988 2989 if (is_mcq_enabled(hba)) 2990 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 2991 2992 ufshcd_send_command(hba, tag, hwq); 2993 2994 out: 2995 if (ufs_trigger_eh()) { 2996 unsigned long flags; 2997 2998 spin_lock_irqsave(hba->host->host_lock, flags); 2999 ufshcd_schedule_eh_work(hba); 3000 spin_unlock_irqrestore(hba->host->host_lock, flags); 3001 } 3002 3003 return err; 3004 } 3005 3006 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 3007 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 3008 { 3009 lrbp->cmd = NULL; 3010 lrbp->task_tag = tag; 3011 lrbp->lun = 0; /* device management cmd is not specific to any LUN */ 3012 lrbp->intr_cmd = true; /* No interrupt aggregation */ 3013 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 3014 hba->dev_cmd.type = cmd_type; 3015 3016 return ufshcd_compose_devman_upiu(hba, lrbp); 3017 } 3018 3019 /* 3020 * Check with the block layer if the command is inflight 3021 * @cmd: command to check. 3022 * 3023 * Return: true if command is inflight; false if not. 3024 */ 3025 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 3026 { 3027 struct request *rq; 3028 3029 if (!cmd) 3030 return false; 3031 3032 rq = scsi_cmd_to_rq(cmd); 3033 if (!blk_mq_request_started(rq)) 3034 return false; 3035 3036 return true; 3037 } 3038 3039 /* 3040 * Clear the pending command in the controller and wait until 3041 * the controller confirms that the command has been cleared. 3042 * @hba: per adapter instance 3043 * @task_tag: The tag number of the command to be cleared. 3044 */ 3045 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 3046 { 3047 u32 mask = 1U << task_tag; 3048 unsigned long flags; 3049 int err; 3050 3051 if (is_mcq_enabled(hba)) { 3052 /* 3053 * MCQ mode. Clean up the MCQ resources similar to 3054 * what the ufshcd_utrl_clear() does for SDB mode. 3055 */ 3056 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 3057 if (err) { 3058 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 3059 __func__, task_tag, err); 3060 return err; 3061 } 3062 return 0; 3063 } 3064 3065 /* clear outstanding transaction before retry */ 3066 spin_lock_irqsave(hba->host->host_lock, flags); 3067 ufshcd_utrl_clear(hba, mask); 3068 spin_unlock_irqrestore(hba->host->host_lock, flags); 3069 3070 /* 3071 * wait for h/w to clear corresponding bit in door-bell. 3072 * max. wait is 1 sec. 3073 */ 3074 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 3075 mask, ~mask, 1000, 1000); 3076 } 3077 3078 /** 3079 * ufshcd_dev_cmd_completion() - handles device management command responses 3080 * @hba: per adapter instance 3081 * @lrbp: pointer to local reference block 3082 * 3083 * Return: 0 upon success; < 0 upon failure. 3084 */ 3085 static int 3086 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 3087 { 3088 enum upiu_response_transaction resp; 3089 int err = 0; 3090 3091 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 3092 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3093 3094 switch (resp) { 3095 case UPIU_TRANSACTION_NOP_IN: 3096 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3097 err = -EINVAL; 3098 dev_err(hba->dev, "%s: unexpected response %x\n", 3099 __func__, resp); 3100 } 3101 break; 3102 case UPIU_TRANSACTION_QUERY_RSP: { 3103 u8 response = lrbp->ucd_rsp_ptr->header.response; 3104 3105 if (response == 0) 3106 err = ufshcd_copy_query_response(hba, lrbp); 3107 break; 3108 } 3109 case UPIU_TRANSACTION_REJECT_UPIU: 3110 /* TODO: handle Reject UPIU Response */ 3111 err = -EPERM; 3112 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3113 __func__); 3114 break; 3115 case UPIU_TRANSACTION_RESPONSE: 3116 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3117 err = -EINVAL; 3118 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3119 } 3120 break; 3121 default: 3122 err = -EINVAL; 3123 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3124 __func__, resp); 3125 break; 3126 } 3127 3128 return err; 3129 } 3130 3131 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3132 struct ufshcd_lrb *lrbp, int max_timeout) 3133 { 3134 unsigned long time_left = msecs_to_jiffies(max_timeout); 3135 unsigned long flags; 3136 bool pending; 3137 int err; 3138 3139 retry: 3140 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3141 time_left); 3142 3143 if (likely(time_left)) { 3144 /* 3145 * The completion handler called complete() and the caller of 3146 * this function still owns the @lrbp tag so the code below does 3147 * not trigger any race conditions. 3148 */ 3149 hba->dev_cmd.complete = NULL; 3150 err = ufshcd_get_tr_ocs(lrbp, NULL); 3151 if (!err) 3152 err = ufshcd_dev_cmd_completion(hba, lrbp); 3153 } else { 3154 err = -ETIMEDOUT; 3155 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3156 __func__, lrbp->task_tag); 3157 3158 /* MCQ mode */ 3159 if (is_mcq_enabled(hba)) { 3160 err = ufshcd_clear_cmd(hba, lrbp->task_tag); 3161 hba->dev_cmd.complete = NULL; 3162 return err; 3163 } 3164 3165 /* SDB mode */ 3166 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3167 /* successfully cleared the command, retry if needed */ 3168 err = -EAGAIN; 3169 /* 3170 * Since clearing the command succeeded we also need to 3171 * clear the task tag bit from the outstanding_reqs 3172 * variable. 3173 */ 3174 spin_lock_irqsave(&hba->outstanding_lock, flags); 3175 pending = test_bit(lrbp->task_tag, 3176 &hba->outstanding_reqs); 3177 if (pending) { 3178 hba->dev_cmd.complete = NULL; 3179 __clear_bit(lrbp->task_tag, 3180 &hba->outstanding_reqs); 3181 } 3182 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3183 3184 if (!pending) { 3185 /* 3186 * The completion handler ran while we tried to 3187 * clear the command. 3188 */ 3189 time_left = 1; 3190 goto retry; 3191 } 3192 } else { 3193 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3194 __func__, lrbp->task_tag); 3195 3196 spin_lock_irqsave(&hba->outstanding_lock, flags); 3197 pending = test_bit(lrbp->task_tag, 3198 &hba->outstanding_reqs); 3199 if (pending) 3200 hba->dev_cmd.complete = NULL; 3201 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3202 3203 if (!pending) { 3204 /* 3205 * The completion handler ran while we tried to 3206 * clear the command. 3207 */ 3208 time_left = 1; 3209 goto retry; 3210 } 3211 } 3212 } 3213 3214 return err; 3215 } 3216 3217 /** 3218 * ufshcd_exec_dev_cmd - API for sending device management requests 3219 * @hba: UFS hba 3220 * @cmd_type: specifies the type (NOP, Query...) 3221 * @timeout: timeout in milliseconds 3222 * 3223 * Return: 0 upon success; < 0 upon failure. 3224 * 3225 * NOTE: Since there is only one available tag for device management commands, 3226 * it is expected you hold the hba->dev_cmd.lock mutex. 3227 */ 3228 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3229 enum dev_cmd_type cmd_type, int timeout) 3230 { 3231 DECLARE_COMPLETION_ONSTACK(wait); 3232 const u32 tag = hba->reserved_slot; 3233 struct ufshcd_lrb *lrbp; 3234 int err; 3235 3236 /* Protects use of hba->reserved_slot. */ 3237 lockdep_assert_held(&hba->dev_cmd.lock); 3238 3239 down_read(&hba->clk_scaling_lock); 3240 3241 lrbp = &hba->lrb[tag]; 3242 lrbp->cmd = NULL; 3243 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3244 if (unlikely(err)) 3245 goto out; 3246 3247 hba->dev_cmd.complete = &wait; 3248 3249 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3250 3251 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3252 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3253 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3254 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3255 3256 out: 3257 up_read(&hba->clk_scaling_lock); 3258 return err; 3259 } 3260 3261 /** 3262 * ufshcd_init_query() - init the query response and request parameters 3263 * @hba: per-adapter instance 3264 * @request: address of the request pointer to be initialized 3265 * @response: address of the response pointer to be initialized 3266 * @opcode: operation to perform 3267 * @idn: flag idn to access 3268 * @index: LU number to access 3269 * @selector: query/flag/descriptor further identification 3270 */ 3271 static inline void ufshcd_init_query(struct ufs_hba *hba, 3272 struct ufs_query_req **request, struct ufs_query_res **response, 3273 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3274 { 3275 *request = &hba->dev_cmd.query.request; 3276 *response = &hba->dev_cmd.query.response; 3277 memset(*request, 0, sizeof(struct ufs_query_req)); 3278 memset(*response, 0, sizeof(struct ufs_query_res)); 3279 (*request)->upiu_req.opcode = opcode; 3280 (*request)->upiu_req.idn = idn; 3281 (*request)->upiu_req.index = index; 3282 (*request)->upiu_req.selector = selector; 3283 } 3284 3285 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3286 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3287 { 3288 int ret; 3289 int retries; 3290 3291 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3292 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3293 if (ret) 3294 dev_dbg(hba->dev, 3295 "%s: failed with error %d, retries %d\n", 3296 __func__, ret, retries); 3297 else 3298 break; 3299 } 3300 3301 if (ret) 3302 dev_err(hba->dev, 3303 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3304 __func__, opcode, idn, ret, retries); 3305 return ret; 3306 } 3307 3308 /** 3309 * ufshcd_query_flag() - API function for sending flag query requests 3310 * @hba: per-adapter instance 3311 * @opcode: flag query to perform 3312 * @idn: flag idn to access 3313 * @index: flag index to access 3314 * @flag_res: the flag value after the query request completes 3315 * 3316 * Return: 0 for success, non-zero in case of failure. 3317 */ 3318 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3319 enum flag_idn idn, u8 index, bool *flag_res) 3320 { 3321 struct ufs_query_req *request = NULL; 3322 struct ufs_query_res *response = NULL; 3323 int err, selector = 0; 3324 int timeout = QUERY_REQ_TIMEOUT; 3325 3326 BUG_ON(!hba); 3327 3328 ufshcd_hold(hba); 3329 mutex_lock(&hba->dev_cmd.lock); 3330 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3331 selector); 3332 3333 switch (opcode) { 3334 case UPIU_QUERY_OPCODE_SET_FLAG: 3335 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3336 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3337 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3338 break; 3339 case UPIU_QUERY_OPCODE_READ_FLAG: 3340 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3341 if (!flag_res) { 3342 /* No dummy reads */ 3343 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3344 __func__); 3345 err = -EINVAL; 3346 goto out_unlock; 3347 } 3348 break; 3349 default: 3350 dev_err(hba->dev, 3351 "%s: Expected query flag opcode but got = %d\n", 3352 __func__, opcode); 3353 err = -EINVAL; 3354 goto out_unlock; 3355 } 3356 3357 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3358 3359 if (err) { 3360 dev_err(hba->dev, 3361 "%s: Sending flag query for idn %d failed, err = %d\n", 3362 __func__, idn, err); 3363 goto out_unlock; 3364 } 3365 3366 if (flag_res) 3367 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3368 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3369 3370 out_unlock: 3371 mutex_unlock(&hba->dev_cmd.lock); 3372 ufshcd_release(hba); 3373 return err; 3374 } 3375 3376 /** 3377 * ufshcd_query_attr - API function for sending attribute requests 3378 * @hba: per-adapter instance 3379 * @opcode: attribute opcode 3380 * @idn: attribute idn to access 3381 * @index: index field 3382 * @selector: selector field 3383 * @attr_val: the attribute value after the query request completes 3384 * 3385 * Return: 0 for success, non-zero in case of failure. 3386 */ 3387 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3388 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3389 { 3390 struct ufs_query_req *request = NULL; 3391 struct ufs_query_res *response = NULL; 3392 int err; 3393 3394 BUG_ON(!hba); 3395 3396 if (!attr_val) { 3397 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3398 __func__, opcode); 3399 return -EINVAL; 3400 } 3401 3402 ufshcd_hold(hba); 3403 3404 mutex_lock(&hba->dev_cmd.lock); 3405 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3406 selector); 3407 3408 switch (opcode) { 3409 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3410 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3411 request->upiu_req.value = cpu_to_be32(*attr_val); 3412 break; 3413 case UPIU_QUERY_OPCODE_READ_ATTR: 3414 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3415 break; 3416 default: 3417 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3418 __func__, opcode); 3419 err = -EINVAL; 3420 goto out_unlock; 3421 } 3422 3423 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3424 3425 if (err) { 3426 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3427 __func__, opcode, idn, index, err); 3428 goto out_unlock; 3429 } 3430 3431 *attr_val = be32_to_cpu(response->upiu_res.value); 3432 3433 out_unlock: 3434 mutex_unlock(&hba->dev_cmd.lock); 3435 ufshcd_release(hba); 3436 return err; 3437 } 3438 3439 /** 3440 * ufshcd_query_attr_retry() - API function for sending query 3441 * attribute with retries 3442 * @hba: per-adapter instance 3443 * @opcode: attribute opcode 3444 * @idn: attribute idn to access 3445 * @index: index field 3446 * @selector: selector field 3447 * @attr_val: the attribute value after the query request 3448 * completes 3449 * 3450 * Return: 0 for success, non-zero in case of failure. 3451 */ 3452 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3453 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3454 u32 *attr_val) 3455 { 3456 int ret = 0; 3457 u32 retries; 3458 3459 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3460 ret = ufshcd_query_attr(hba, opcode, idn, index, 3461 selector, attr_val); 3462 if (ret) 3463 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3464 __func__, ret, retries); 3465 else 3466 break; 3467 } 3468 3469 if (ret) 3470 dev_err(hba->dev, 3471 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3472 __func__, idn, ret, QUERY_REQ_RETRIES); 3473 return ret; 3474 } 3475 3476 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3477 enum query_opcode opcode, enum desc_idn idn, u8 index, 3478 u8 selector, u8 *desc_buf, int *buf_len) 3479 { 3480 struct ufs_query_req *request = NULL; 3481 struct ufs_query_res *response = NULL; 3482 int err; 3483 3484 BUG_ON(!hba); 3485 3486 if (!desc_buf) { 3487 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3488 __func__, opcode); 3489 return -EINVAL; 3490 } 3491 3492 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3493 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3494 __func__, *buf_len); 3495 return -EINVAL; 3496 } 3497 3498 ufshcd_hold(hba); 3499 3500 mutex_lock(&hba->dev_cmd.lock); 3501 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3502 selector); 3503 hba->dev_cmd.query.descriptor = desc_buf; 3504 request->upiu_req.length = cpu_to_be16(*buf_len); 3505 3506 switch (opcode) { 3507 case UPIU_QUERY_OPCODE_WRITE_DESC: 3508 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3509 break; 3510 case UPIU_QUERY_OPCODE_READ_DESC: 3511 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3512 break; 3513 default: 3514 dev_err(hba->dev, 3515 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3516 __func__, opcode); 3517 err = -EINVAL; 3518 goto out_unlock; 3519 } 3520 3521 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3522 3523 if (err) { 3524 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3525 __func__, opcode, idn, index, err); 3526 goto out_unlock; 3527 } 3528 3529 *buf_len = be16_to_cpu(response->upiu_res.length); 3530 3531 out_unlock: 3532 hba->dev_cmd.query.descriptor = NULL; 3533 mutex_unlock(&hba->dev_cmd.lock); 3534 ufshcd_release(hba); 3535 return err; 3536 } 3537 3538 /** 3539 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3540 * @hba: per-adapter instance 3541 * @opcode: attribute opcode 3542 * @idn: attribute idn to access 3543 * @index: index field 3544 * @selector: selector field 3545 * @desc_buf: the buffer that contains the descriptor 3546 * @buf_len: length parameter passed to the device 3547 * 3548 * The buf_len parameter will contain, on return, the length parameter 3549 * received on the response. 3550 * 3551 * Return: 0 for success, non-zero in case of failure. 3552 */ 3553 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3554 enum query_opcode opcode, 3555 enum desc_idn idn, u8 index, 3556 u8 selector, 3557 u8 *desc_buf, int *buf_len) 3558 { 3559 int err; 3560 int retries; 3561 3562 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3563 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3564 selector, desc_buf, buf_len); 3565 if (!err || err == -EINVAL) 3566 break; 3567 } 3568 3569 return err; 3570 } 3571 3572 /** 3573 * ufshcd_read_desc_param - read the specified descriptor parameter 3574 * @hba: Pointer to adapter instance 3575 * @desc_id: descriptor idn value 3576 * @desc_index: descriptor index 3577 * @param_offset: offset of the parameter to read 3578 * @param_read_buf: pointer to buffer where parameter would be read 3579 * @param_size: sizeof(param_read_buf) 3580 * 3581 * Return: 0 in case of success, non-zero otherwise. 3582 */ 3583 int ufshcd_read_desc_param(struct ufs_hba *hba, 3584 enum desc_idn desc_id, 3585 int desc_index, 3586 u8 param_offset, 3587 u8 *param_read_buf, 3588 u8 param_size) 3589 { 3590 int ret; 3591 u8 *desc_buf; 3592 int buff_len = QUERY_DESC_MAX_SIZE; 3593 bool is_kmalloc = true; 3594 3595 /* Safety check */ 3596 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3597 return -EINVAL; 3598 3599 /* Check whether we need temp memory */ 3600 if (param_offset != 0 || param_size < buff_len) { 3601 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3602 if (!desc_buf) 3603 return -ENOMEM; 3604 } else { 3605 desc_buf = param_read_buf; 3606 is_kmalloc = false; 3607 } 3608 3609 /* Request for full descriptor */ 3610 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3611 desc_id, desc_index, 0, 3612 desc_buf, &buff_len); 3613 if (ret) { 3614 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3615 __func__, desc_id, desc_index, param_offset, ret); 3616 goto out; 3617 } 3618 3619 /* Update descriptor length */ 3620 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3621 3622 if (param_offset >= buff_len) { 3623 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3624 __func__, param_offset, desc_id, buff_len); 3625 ret = -EINVAL; 3626 goto out; 3627 } 3628 3629 /* Sanity check */ 3630 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3631 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3632 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3633 ret = -EINVAL; 3634 goto out; 3635 } 3636 3637 if (is_kmalloc) { 3638 /* Make sure we don't copy more data than available */ 3639 if (param_offset >= buff_len) 3640 ret = -EINVAL; 3641 else 3642 memcpy(param_read_buf, &desc_buf[param_offset], 3643 min_t(u32, param_size, buff_len - param_offset)); 3644 } 3645 out: 3646 if (is_kmalloc) 3647 kfree(desc_buf); 3648 return ret; 3649 } 3650 3651 /** 3652 * struct uc_string_id - unicode string 3653 * 3654 * @len: size of this descriptor inclusive 3655 * @type: descriptor type 3656 * @uc: unicode string character 3657 */ 3658 struct uc_string_id { 3659 u8 len; 3660 u8 type; 3661 wchar_t uc[]; 3662 } __packed; 3663 3664 /* replace non-printable or non-ASCII characters with spaces */ 3665 static inline char ufshcd_remove_non_printable(u8 ch) 3666 { 3667 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3668 } 3669 3670 /** 3671 * ufshcd_read_string_desc - read string descriptor 3672 * @hba: pointer to adapter instance 3673 * @desc_index: descriptor index 3674 * @buf: pointer to buffer where descriptor would be read, 3675 * the caller should free the memory. 3676 * @ascii: if true convert from unicode to ascii characters 3677 * null terminated string. 3678 * 3679 * Return: 3680 * * string size on success. 3681 * * -ENOMEM: on allocation failure 3682 * * -EINVAL: on a wrong parameter 3683 */ 3684 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3685 u8 **buf, bool ascii) 3686 { 3687 struct uc_string_id *uc_str; 3688 u8 *str; 3689 int ret; 3690 3691 if (!buf) 3692 return -EINVAL; 3693 3694 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3695 if (!uc_str) 3696 return -ENOMEM; 3697 3698 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3699 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3700 if (ret < 0) { 3701 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3702 QUERY_REQ_RETRIES, ret); 3703 str = NULL; 3704 goto out; 3705 } 3706 3707 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3708 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3709 str = NULL; 3710 ret = 0; 3711 goto out; 3712 } 3713 3714 if (ascii) { 3715 ssize_t ascii_len; 3716 int i; 3717 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3718 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3719 str = kzalloc(ascii_len, GFP_KERNEL); 3720 if (!str) { 3721 ret = -ENOMEM; 3722 goto out; 3723 } 3724 3725 /* 3726 * the descriptor contains string in UTF16 format 3727 * we need to convert to utf-8 so it can be displayed 3728 */ 3729 ret = utf16s_to_utf8s(uc_str->uc, 3730 uc_str->len - QUERY_DESC_HDR_SIZE, 3731 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3732 3733 /* replace non-printable or non-ASCII characters with spaces */ 3734 for (i = 0; i < ret; i++) 3735 str[i] = ufshcd_remove_non_printable(str[i]); 3736 3737 str[ret++] = '\0'; 3738 3739 } else { 3740 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3741 if (!str) { 3742 ret = -ENOMEM; 3743 goto out; 3744 } 3745 ret = uc_str->len; 3746 } 3747 out: 3748 *buf = str; 3749 kfree(uc_str); 3750 return ret; 3751 } 3752 3753 /** 3754 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3755 * @hba: Pointer to adapter instance 3756 * @lun: lun id 3757 * @param_offset: offset of the parameter to read 3758 * @param_read_buf: pointer to buffer where parameter would be read 3759 * @param_size: sizeof(param_read_buf) 3760 * 3761 * Return: 0 in case of success, non-zero otherwise. 3762 */ 3763 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3764 int lun, 3765 enum unit_desc_param param_offset, 3766 u8 *param_read_buf, 3767 u32 param_size) 3768 { 3769 /* 3770 * Unit descriptors are only available for general purpose LUs (LUN id 3771 * from 0 to 7) and RPMB Well known LU. 3772 */ 3773 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3774 return -EOPNOTSUPP; 3775 3776 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3777 param_offset, param_read_buf, param_size); 3778 } 3779 3780 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3781 { 3782 int err = 0; 3783 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3784 3785 if (hba->dev_info.wspecversion >= 0x300) { 3786 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3787 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3788 &gating_wait); 3789 if (err) 3790 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3791 err, gating_wait); 3792 3793 if (gating_wait == 0) { 3794 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3795 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3796 gating_wait); 3797 } 3798 3799 hba->dev_info.clk_gating_wait_us = gating_wait; 3800 } 3801 3802 return err; 3803 } 3804 3805 /** 3806 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3807 * @hba: per adapter instance 3808 * 3809 * 1. Allocate DMA memory for Command Descriptor array 3810 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3811 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3812 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3813 * (UTMRDL) 3814 * 4. Allocate memory for local reference block(lrb). 3815 * 3816 * Return: 0 for success, non-zero in case of failure. 3817 */ 3818 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3819 { 3820 size_t utmrdl_size, utrdl_size, ucdl_size; 3821 3822 /* Allocate memory for UTP command descriptors */ 3823 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3824 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3825 ucdl_size, 3826 &hba->ucdl_dma_addr, 3827 GFP_KERNEL); 3828 3829 /* 3830 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3831 */ 3832 if (!hba->ucdl_base_addr || 3833 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3834 dev_err(hba->dev, 3835 "Command Descriptor Memory allocation failed\n"); 3836 goto out; 3837 } 3838 3839 /* 3840 * Allocate memory for UTP Transfer descriptors 3841 * UFSHCI requires 1KB alignment of UTRD 3842 */ 3843 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3844 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3845 utrdl_size, 3846 &hba->utrdl_dma_addr, 3847 GFP_KERNEL); 3848 if (!hba->utrdl_base_addr || 3849 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3850 dev_err(hba->dev, 3851 "Transfer Descriptor Memory allocation failed\n"); 3852 goto out; 3853 } 3854 3855 /* 3856 * Skip utmrdl allocation; it may have been 3857 * allocated during first pass and not released during 3858 * MCQ memory allocation. 3859 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3860 */ 3861 if (hba->utmrdl_base_addr) 3862 goto skip_utmrdl; 3863 /* 3864 * Allocate memory for UTP Task Management descriptors 3865 * UFSHCI requires 1KB alignment of UTMRD 3866 */ 3867 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3868 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3869 utmrdl_size, 3870 &hba->utmrdl_dma_addr, 3871 GFP_KERNEL); 3872 if (!hba->utmrdl_base_addr || 3873 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3874 dev_err(hba->dev, 3875 "Task Management Descriptor Memory allocation failed\n"); 3876 goto out; 3877 } 3878 3879 skip_utmrdl: 3880 /* Allocate memory for local reference block */ 3881 hba->lrb = devm_kcalloc(hba->dev, 3882 hba->nutrs, sizeof(struct ufshcd_lrb), 3883 GFP_KERNEL); 3884 if (!hba->lrb) { 3885 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3886 goto out; 3887 } 3888 return 0; 3889 out: 3890 return -ENOMEM; 3891 } 3892 3893 /** 3894 * ufshcd_host_memory_configure - configure local reference block with 3895 * memory offsets 3896 * @hba: per adapter instance 3897 * 3898 * Configure Host memory space 3899 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3900 * address. 3901 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3902 * and PRDT offset. 3903 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3904 * into local reference block. 3905 */ 3906 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3907 { 3908 struct utp_transfer_req_desc *utrdlp; 3909 dma_addr_t cmd_desc_dma_addr; 3910 dma_addr_t cmd_desc_element_addr; 3911 u16 response_offset; 3912 u16 prdt_offset; 3913 int cmd_desc_size; 3914 int i; 3915 3916 utrdlp = hba->utrdl_base_addr; 3917 3918 response_offset = 3919 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3920 prdt_offset = 3921 offsetof(struct utp_transfer_cmd_desc, prd_table); 3922 3923 cmd_desc_size = ufshcd_get_ucd_size(hba); 3924 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3925 3926 for (i = 0; i < hba->nutrs; i++) { 3927 /* Configure UTRD with command descriptor base address */ 3928 cmd_desc_element_addr = 3929 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3930 utrdlp[i].command_desc_base_addr = 3931 cpu_to_le64(cmd_desc_element_addr); 3932 3933 /* Response upiu and prdt offset should be in double words */ 3934 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3935 utrdlp[i].response_upiu_offset = 3936 cpu_to_le16(response_offset); 3937 utrdlp[i].prd_table_offset = 3938 cpu_to_le16(prdt_offset); 3939 utrdlp[i].response_upiu_length = 3940 cpu_to_le16(ALIGNED_UPIU_SIZE); 3941 } else { 3942 utrdlp[i].response_upiu_offset = 3943 cpu_to_le16(response_offset >> 2); 3944 utrdlp[i].prd_table_offset = 3945 cpu_to_le16(prdt_offset >> 2); 3946 utrdlp[i].response_upiu_length = 3947 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 3948 } 3949 3950 ufshcd_init_lrb(hba, &hba->lrb[i], i); 3951 } 3952 } 3953 3954 /** 3955 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 3956 * @hba: per adapter instance 3957 * 3958 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 3959 * in order to initialize the Unipro link startup procedure. 3960 * Once the Unipro links are up, the device connected to the controller 3961 * is detected. 3962 * 3963 * Return: 0 on success, non-zero value on failure. 3964 */ 3965 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 3966 { 3967 struct uic_command uic_cmd = {0}; 3968 int ret; 3969 3970 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 3971 3972 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3973 if (ret) 3974 dev_dbg(hba->dev, 3975 "dme-link-startup: error code %d\n", ret); 3976 return ret; 3977 } 3978 /** 3979 * ufshcd_dme_reset - UIC command for DME_RESET 3980 * @hba: per adapter instance 3981 * 3982 * DME_RESET command is issued in order to reset UniPro stack. 3983 * This function now deals with cold reset. 3984 * 3985 * Return: 0 on success, non-zero value on failure. 3986 */ 3987 static int ufshcd_dme_reset(struct ufs_hba *hba) 3988 { 3989 struct uic_command uic_cmd = {0}; 3990 int ret; 3991 3992 uic_cmd.command = UIC_CMD_DME_RESET; 3993 3994 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3995 if (ret) 3996 dev_err(hba->dev, 3997 "dme-reset: error code %d\n", ret); 3998 3999 return ret; 4000 } 4001 4002 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 4003 int agreed_gear, 4004 int adapt_val) 4005 { 4006 int ret; 4007 4008 if (agreed_gear < UFS_HS_G4) 4009 adapt_val = PA_NO_ADAPT; 4010 4011 ret = ufshcd_dme_set(hba, 4012 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 4013 adapt_val); 4014 return ret; 4015 } 4016 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 4017 4018 /** 4019 * ufshcd_dme_enable - UIC command for DME_ENABLE 4020 * @hba: per adapter instance 4021 * 4022 * DME_ENABLE command is issued in order to enable UniPro stack. 4023 * 4024 * Return: 0 on success, non-zero value on failure. 4025 */ 4026 static int ufshcd_dme_enable(struct ufs_hba *hba) 4027 { 4028 struct uic_command uic_cmd = {0}; 4029 int ret; 4030 4031 uic_cmd.command = UIC_CMD_DME_ENABLE; 4032 4033 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4034 if (ret) 4035 dev_err(hba->dev, 4036 "dme-enable: error code %d\n", ret); 4037 4038 return ret; 4039 } 4040 4041 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 4042 { 4043 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 4044 unsigned long min_sleep_time_us; 4045 4046 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 4047 return; 4048 4049 /* 4050 * last_dme_cmd_tstamp will be 0 only for 1st call to 4051 * this function 4052 */ 4053 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 4054 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 4055 } else { 4056 unsigned long delta = 4057 (unsigned long) ktime_to_us( 4058 ktime_sub(ktime_get(), 4059 hba->last_dme_cmd_tstamp)); 4060 4061 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 4062 min_sleep_time_us = 4063 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 4064 else 4065 return; /* no more delay required */ 4066 } 4067 4068 /* allow sleep for extra 50us if needed */ 4069 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 4070 } 4071 4072 /** 4073 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 4074 * @hba: per adapter instance 4075 * @attr_sel: uic command argument1 4076 * @attr_set: attribute set type as uic command argument2 4077 * @mib_val: setting value as uic command argument3 4078 * @peer: indicate whether peer or local 4079 * 4080 * Return: 0 on success, non-zero value on failure. 4081 */ 4082 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 4083 u8 attr_set, u32 mib_val, u8 peer) 4084 { 4085 struct uic_command uic_cmd = {0}; 4086 static const char *const action[] = { 4087 "dme-set", 4088 "dme-peer-set" 4089 }; 4090 const char *set = action[!!peer]; 4091 int ret; 4092 int retries = UFS_UIC_COMMAND_RETRIES; 4093 4094 uic_cmd.command = peer ? 4095 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 4096 uic_cmd.argument1 = attr_sel; 4097 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 4098 uic_cmd.argument3 = mib_val; 4099 4100 do { 4101 /* for peer attributes we retry upon failure */ 4102 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4103 if (ret) 4104 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4105 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4106 } while (ret && peer && --retries); 4107 4108 if (ret) 4109 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4110 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4111 UFS_UIC_COMMAND_RETRIES - retries); 4112 4113 return ret; 4114 } 4115 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4116 4117 /** 4118 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4119 * @hba: per adapter instance 4120 * @attr_sel: uic command argument1 4121 * @mib_val: the value of the attribute as returned by the UIC command 4122 * @peer: indicate whether peer or local 4123 * 4124 * Return: 0 on success, non-zero value on failure. 4125 */ 4126 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4127 u32 *mib_val, u8 peer) 4128 { 4129 struct uic_command uic_cmd = {0}; 4130 static const char *const action[] = { 4131 "dme-get", 4132 "dme-peer-get" 4133 }; 4134 const char *get = action[!!peer]; 4135 int ret; 4136 int retries = UFS_UIC_COMMAND_RETRIES; 4137 struct ufs_pa_layer_attr orig_pwr_info; 4138 struct ufs_pa_layer_attr temp_pwr_info; 4139 bool pwr_mode_change = false; 4140 4141 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4142 orig_pwr_info = hba->pwr_info; 4143 temp_pwr_info = orig_pwr_info; 4144 4145 if (orig_pwr_info.pwr_tx == FAST_MODE || 4146 orig_pwr_info.pwr_rx == FAST_MODE) { 4147 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4148 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4149 pwr_mode_change = true; 4150 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4151 orig_pwr_info.pwr_rx == SLOW_MODE) { 4152 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4153 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4154 pwr_mode_change = true; 4155 } 4156 if (pwr_mode_change) { 4157 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4158 if (ret) 4159 goto out; 4160 } 4161 } 4162 4163 uic_cmd.command = peer ? 4164 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 4165 uic_cmd.argument1 = attr_sel; 4166 4167 do { 4168 /* for peer attributes we retry upon failure */ 4169 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4170 if (ret) 4171 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4172 get, UIC_GET_ATTR_ID(attr_sel), ret); 4173 } while (ret && peer && --retries); 4174 4175 if (ret) 4176 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4177 get, UIC_GET_ATTR_ID(attr_sel), 4178 UFS_UIC_COMMAND_RETRIES - retries); 4179 4180 if (mib_val && !ret) 4181 *mib_val = uic_cmd.argument3; 4182 4183 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4184 && pwr_mode_change) 4185 ufshcd_change_power_mode(hba, &orig_pwr_info); 4186 out: 4187 return ret; 4188 } 4189 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4190 4191 /** 4192 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4193 * state) and waits for it to take effect. 4194 * 4195 * @hba: per adapter instance 4196 * @cmd: UIC command to execute 4197 * 4198 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4199 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4200 * and device UniPro link and hence it's final completion would be indicated by 4201 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4202 * addition to normal UIC command completion Status (UCCS). This function only 4203 * returns after the relevant status bits indicate the completion. 4204 * 4205 * Return: 0 on success, non-zero value on failure. 4206 */ 4207 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4208 { 4209 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4210 unsigned long flags; 4211 u8 status; 4212 int ret; 4213 bool reenable_intr = false; 4214 4215 mutex_lock(&hba->uic_cmd_mutex); 4216 ufshcd_add_delay_before_dme_cmd(hba); 4217 4218 spin_lock_irqsave(hba->host->host_lock, flags); 4219 if (ufshcd_is_link_broken(hba)) { 4220 ret = -ENOLINK; 4221 goto out_unlock; 4222 } 4223 hba->uic_async_done = &uic_async_done; 4224 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4225 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4226 /* 4227 * Make sure UIC command completion interrupt is disabled before 4228 * issuing UIC command. 4229 */ 4230 wmb(); 4231 reenable_intr = true; 4232 } 4233 spin_unlock_irqrestore(hba->host->host_lock, flags); 4234 ret = __ufshcd_send_uic_cmd(hba, cmd, false); 4235 if (ret) { 4236 dev_err(hba->dev, 4237 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4238 cmd->command, cmd->argument3, ret); 4239 goto out; 4240 } 4241 4242 if (!wait_for_completion_timeout(hba->uic_async_done, 4243 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 4244 dev_err(hba->dev, 4245 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4246 cmd->command, cmd->argument3); 4247 4248 if (!cmd->cmd_active) { 4249 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4250 __func__); 4251 goto check_upmcrs; 4252 } 4253 4254 ret = -ETIMEDOUT; 4255 goto out; 4256 } 4257 4258 check_upmcrs: 4259 status = ufshcd_get_upmcrs(hba); 4260 if (status != PWR_LOCAL) { 4261 dev_err(hba->dev, 4262 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4263 cmd->command, status); 4264 ret = (status != PWR_OK) ? status : -1; 4265 } 4266 out: 4267 if (ret) { 4268 ufshcd_print_host_state(hba); 4269 ufshcd_print_pwr_info(hba); 4270 ufshcd_print_evt_hist(hba); 4271 } 4272 4273 spin_lock_irqsave(hba->host->host_lock, flags); 4274 hba->active_uic_cmd = NULL; 4275 hba->uic_async_done = NULL; 4276 if (reenable_intr) 4277 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4278 if (ret) { 4279 ufshcd_set_link_broken(hba); 4280 ufshcd_schedule_eh_work(hba); 4281 } 4282 out_unlock: 4283 spin_unlock_irqrestore(hba->host->host_lock, flags); 4284 mutex_unlock(&hba->uic_cmd_mutex); 4285 4286 return ret; 4287 } 4288 4289 /** 4290 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4291 * using DME_SET primitives. 4292 * @hba: per adapter instance 4293 * @mode: powr mode value 4294 * 4295 * Return: 0 on success, non-zero value on failure. 4296 */ 4297 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4298 { 4299 struct uic_command uic_cmd = {0}; 4300 int ret; 4301 4302 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4303 ret = ufshcd_dme_set(hba, 4304 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4305 if (ret) { 4306 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4307 __func__, ret); 4308 goto out; 4309 } 4310 } 4311 4312 uic_cmd.command = UIC_CMD_DME_SET; 4313 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 4314 uic_cmd.argument3 = mode; 4315 ufshcd_hold(hba); 4316 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4317 ufshcd_release(hba); 4318 4319 out: 4320 return ret; 4321 } 4322 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4323 4324 int ufshcd_link_recovery(struct ufs_hba *hba) 4325 { 4326 int ret; 4327 unsigned long flags; 4328 4329 spin_lock_irqsave(hba->host->host_lock, flags); 4330 hba->ufshcd_state = UFSHCD_STATE_RESET; 4331 ufshcd_set_eh_in_progress(hba); 4332 spin_unlock_irqrestore(hba->host->host_lock, flags); 4333 4334 /* Reset the attached device */ 4335 ufshcd_device_reset(hba); 4336 4337 ret = ufshcd_host_reset_and_restore(hba); 4338 4339 spin_lock_irqsave(hba->host->host_lock, flags); 4340 if (ret) 4341 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4342 ufshcd_clear_eh_in_progress(hba); 4343 spin_unlock_irqrestore(hba->host->host_lock, flags); 4344 4345 if (ret) 4346 dev_err(hba->dev, "%s: link recovery failed, err %d", 4347 __func__, ret); 4348 4349 return ret; 4350 } 4351 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4352 4353 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4354 { 4355 int ret; 4356 struct uic_command uic_cmd = {0}; 4357 ktime_t start = ktime_get(); 4358 4359 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4360 4361 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER; 4362 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4363 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4364 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4365 4366 if (ret) 4367 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4368 __func__, ret); 4369 else 4370 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4371 POST_CHANGE); 4372 4373 return ret; 4374 } 4375 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4376 4377 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4378 { 4379 struct uic_command uic_cmd = {0}; 4380 int ret; 4381 ktime_t start = ktime_get(); 4382 4383 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4384 4385 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT; 4386 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4387 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4388 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4389 4390 if (ret) { 4391 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4392 __func__, ret); 4393 } else { 4394 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4395 POST_CHANGE); 4396 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4397 hba->ufs_stats.hibern8_exit_cnt++; 4398 } 4399 4400 return ret; 4401 } 4402 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4403 4404 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4405 { 4406 unsigned long flags; 4407 bool update = false; 4408 4409 if (!ufshcd_is_auto_hibern8_supported(hba)) 4410 return; 4411 4412 spin_lock_irqsave(hba->host->host_lock, flags); 4413 if (hba->ahit != ahit) { 4414 hba->ahit = ahit; 4415 update = true; 4416 } 4417 spin_unlock_irqrestore(hba->host->host_lock, flags); 4418 4419 if (update && 4420 !pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4421 ufshcd_rpm_get_sync(hba); 4422 ufshcd_hold(hba); 4423 ufshcd_auto_hibern8_enable(hba); 4424 ufshcd_release(hba); 4425 ufshcd_rpm_put_sync(hba); 4426 } 4427 } 4428 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4429 4430 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba) 4431 { 4432 if (!ufshcd_is_auto_hibern8_supported(hba)) 4433 return; 4434 4435 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4436 } 4437 4438 /** 4439 * ufshcd_init_pwr_info - setting the POR (power on reset) 4440 * values in hba power info 4441 * @hba: per-adapter instance 4442 */ 4443 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4444 { 4445 hba->pwr_info.gear_rx = UFS_PWM_G1; 4446 hba->pwr_info.gear_tx = UFS_PWM_G1; 4447 hba->pwr_info.lane_rx = UFS_LANE_1; 4448 hba->pwr_info.lane_tx = UFS_LANE_1; 4449 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4450 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4451 hba->pwr_info.hs_rate = 0; 4452 } 4453 4454 /** 4455 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4456 * @hba: per-adapter instance 4457 * 4458 * Return: 0 upon success; < 0 upon failure. 4459 */ 4460 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4461 { 4462 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4463 4464 if (hba->max_pwr_info.is_valid) 4465 return 0; 4466 4467 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4468 pwr_info->pwr_tx = FASTAUTO_MODE; 4469 pwr_info->pwr_rx = FASTAUTO_MODE; 4470 } else { 4471 pwr_info->pwr_tx = FAST_MODE; 4472 pwr_info->pwr_rx = FAST_MODE; 4473 } 4474 pwr_info->hs_rate = PA_HS_MODE_B; 4475 4476 /* Get the connected lane count */ 4477 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4478 &pwr_info->lane_rx); 4479 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4480 &pwr_info->lane_tx); 4481 4482 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4483 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4484 __func__, 4485 pwr_info->lane_rx, 4486 pwr_info->lane_tx); 4487 return -EINVAL; 4488 } 4489 4490 /* 4491 * First, get the maximum gears of HS speed. 4492 * If a zero value, it means there is no HSGEAR capability. 4493 * Then, get the maximum gears of PWM speed. 4494 */ 4495 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4496 if (!pwr_info->gear_rx) { 4497 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4498 &pwr_info->gear_rx); 4499 if (!pwr_info->gear_rx) { 4500 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4501 __func__, pwr_info->gear_rx); 4502 return -EINVAL; 4503 } 4504 pwr_info->pwr_rx = SLOW_MODE; 4505 } 4506 4507 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4508 &pwr_info->gear_tx); 4509 if (!pwr_info->gear_tx) { 4510 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4511 &pwr_info->gear_tx); 4512 if (!pwr_info->gear_tx) { 4513 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4514 __func__, pwr_info->gear_tx); 4515 return -EINVAL; 4516 } 4517 pwr_info->pwr_tx = SLOW_MODE; 4518 } 4519 4520 hba->max_pwr_info.is_valid = true; 4521 return 0; 4522 } 4523 4524 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4525 struct ufs_pa_layer_attr *pwr_mode) 4526 { 4527 int ret; 4528 4529 /* if already configured to the requested pwr_mode */ 4530 if (!hba->force_pmc && 4531 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4532 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4533 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4534 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4535 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4536 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4537 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4538 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4539 return 0; 4540 } 4541 4542 /* 4543 * Configure attributes for power mode change with below. 4544 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4545 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4546 * - PA_HSSERIES 4547 */ 4548 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4549 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4550 pwr_mode->lane_rx); 4551 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4552 pwr_mode->pwr_rx == FAST_MODE) 4553 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4554 else 4555 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4556 4557 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4558 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4559 pwr_mode->lane_tx); 4560 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4561 pwr_mode->pwr_tx == FAST_MODE) 4562 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4563 else 4564 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4565 4566 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4567 pwr_mode->pwr_tx == FASTAUTO_MODE || 4568 pwr_mode->pwr_rx == FAST_MODE || 4569 pwr_mode->pwr_tx == FAST_MODE) 4570 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4571 pwr_mode->hs_rate); 4572 4573 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4574 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4575 DL_FC0ProtectionTimeOutVal_Default); 4576 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4577 DL_TC0ReplayTimeOutVal_Default); 4578 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4579 DL_AFC0ReqTimeOutVal_Default); 4580 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4581 DL_FC1ProtectionTimeOutVal_Default); 4582 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4583 DL_TC1ReplayTimeOutVal_Default); 4584 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4585 DL_AFC1ReqTimeOutVal_Default); 4586 4587 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4588 DL_FC0ProtectionTimeOutVal_Default); 4589 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4590 DL_TC0ReplayTimeOutVal_Default); 4591 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4592 DL_AFC0ReqTimeOutVal_Default); 4593 } 4594 4595 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4596 | pwr_mode->pwr_tx); 4597 4598 if (ret) { 4599 dev_err(hba->dev, 4600 "%s: power mode change failed %d\n", __func__, ret); 4601 } else { 4602 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4603 pwr_mode); 4604 4605 memcpy(&hba->pwr_info, pwr_mode, 4606 sizeof(struct ufs_pa_layer_attr)); 4607 } 4608 4609 return ret; 4610 } 4611 4612 /** 4613 * ufshcd_config_pwr_mode - configure a new power mode 4614 * @hba: per-adapter instance 4615 * @desired_pwr_mode: desired power configuration 4616 * 4617 * Return: 0 upon success; < 0 upon failure. 4618 */ 4619 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4620 struct ufs_pa_layer_attr *desired_pwr_mode) 4621 { 4622 struct ufs_pa_layer_attr final_params = { 0 }; 4623 int ret; 4624 4625 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4626 desired_pwr_mode, &final_params); 4627 4628 if (ret) 4629 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4630 4631 ret = ufshcd_change_power_mode(hba, &final_params); 4632 4633 return ret; 4634 } 4635 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4636 4637 /** 4638 * ufshcd_complete_dev_init() - checks device readiness 4639 * @hba: per-adapter instance 4640 * 4641 * Set fDeviceInit flag and poll until device toggles it. 4642 * 4643 * Return: 0 upon success; < 0 upon failure. 4644 */ 4645 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4646 { 4647 int err; 4648 bool flag_res = true; 4649 ktime_t timeout; 4650 4651 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4652 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4653 if (err) { 4654 dev_err(hba->dev, 4655 "%s: setting fDeviceInit flag failed with error %d\n", 4656 __func__, err); 4657 goto out; 4658 } 4659 4660 /* Poll fDeviceInit flag to be cleared */ 4661 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4662 do { 4663 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4664 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4665 if (!flag_res) 4666 break; 4667 usleep_range(500, 1000); 4668 } while (ktime_before(ktime_get(), timeout)); 4669 4670 if (err) { 4671 dev_err(hba->dev, 4672 "%s: reading fDeviceInit flag failed with error %d\n", 4673 __func__, err); 4674 } else if (flag_res) { 4675 dev_err(hba->dev, 4676 "%s: fDeviceInit was not cleared by the device\n", 4677 __func__); 4678 err = -EBUSY; 4679 } 4680 out: 4681 return err; 4682 } 4683 4684 /** 4685 * ufshcd_make_hba_operational - Make UFS controller operational 4686 * @hba: per adapter instance 4687 * 4688 * To bring UFS host controller to operational state, 4689 * 1. Enable required interrupts 4690 * 2. Configure interrupt aggregation 4691 * 3. Program UTRL and UTMRL base address 4692 * 4. Configure run-stop-registers 4693 * 4694 * Return: 0 on success, non-zero value on failure. 4695 */ 4696 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4697 { 4698 int err = 0; 4699 u32 reg; 4700 4701 /* Enable required interrupts */ 4702 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4703 4704 /* Configure interrupt aggregation */ 4705 if (ufshcd_is_intr_aggr_allowed(hba)) 4706 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4707 else 4708 ufshcd_disable_intr_aggr(hba); 4709 4710 /* Configure UTRL and UTMRL base address registers */ 4711 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4712 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4713 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4714 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4715 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4716 REG_UTP_TASK_REQ_LIST_BASE_L); 4717 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4718 REG_UTP_TASK_REQ_LIST_BASE_H); 4719 4720 /* 4721 * Make sure base address and interrupt setup are updated before 4722 * enabling the run/stop registers below. 4723 */ 4724 wmb(); 4725 4726 /* 4727 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4728 */ 4729 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4730 if (!(ufshcd_get_lists_status(reg))) { 4731 ufshcd_enable_run_stop_reg(hba); 4732 } else { 4733 dev_err(hba->dev, 4734 "Host controller not ready to process requests"); 4735 err = -EIO; 4736 } 4737 4738 return err; 4739 } 4740 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4741 4742 /** 4743 * ufshcd_hba_stop - Send controller to reset state 4744 * @hba: per adapter instance 4745 */ 4746 void ufshcd_hba_stop(struct ufs_hba *hba) 4747 { 4748 unsigned long flags; 4749 int err; 4750 4751 /* 4752 * Obtain the host lock to prevent that the controller is disabled 4753 * while the UFS interrupt handler is active on another CPU. 4754 */ 4755 spin_lock_irqsave(hba->host->host_lock, flags); 4756 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4757 spin_unlock_irqrestore(hba->host->host_lock, flags); 4758 4759 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4760 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4761 10, 1); 4762 if (err) 4763 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4764 } 4765 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4766 4767 /** 4768 * ufshcd_hba_execute_hce - initialize the controller 4769 * @hba: per adapter instance 4770 * 4771 * The controller resets itself and controller firmware initialization 4772 * sequence kicks off. When controller is ready it will set 4773 * the Host Controller Enable bit to 1. 4774 * 4775 * Return: 0 on success, non-zero value on failure. 4776 */ 4777 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4778 { 4779 int retry_outer = 3; 4780 int retry_inner; 4781 4782 start: 4783 if (ufshcd_is_hba_active(hba)) 4784 /* change controller state to "reset state" */ 4785 ufshcd_hba_stop(hba); 4786 4787 /* UniPro link is disabled at this point */ 4788 ufshcd_set_link_off(hba); 4789 4790 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4791 4792 /* start controller initialization sequence */ 4793 ufshcd_hba_start(hba); 4794 4795 /* 4796 * To initialize a UFS host controller HCE bit must be set to 1. 4797 * During initialization the HCE bit value changes from 1->0->1. 4798 * When the host controller completes initialization sequence 4799 * it sets the value of HCE bit to 1. The same HCE bit is read back 4800 * to check if the controller has completed initialization sequence. 4801 * So without this delay the value HCE = 1, set in the previous 4802 * instruction might be read back. 4803 * This delay can be changed based on the controller. 4804 */ 4805 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4806 4807 /* wait for the host controller to complete initialization */ 4808 retry_inner = 50; 4809 while (!ufshcd_is_hba_active(hba)) { 4810 if (retry_inner) { 4811 retry_inner--; 4812 } else { 4813 dev_err(hba->dev, 4814 "Controller enable failed\n"); 4815 if (retry_outer) { 4816 retry_outer--; 4817 goto start; 4818 } 4819 return -EIO; 4820 } 4821 usleep_range(1000, 1100); 4822 } 4823 4824 /* enable UIC related interrupts */ 4825 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4826 4827 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4828 4829 return 0; 4830 } 4831 4832 int ufshcd_hba_enable(struct ufs_hba *hba) 4833 { 4834 int ret; 4835 4836 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4837 ufshcd_set_link_off(hba); 4838 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4839 4840 /* enable UIC related interrupts */ 4841 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4842 ret = ufshcd_dme_reset(hba); 4843 if (ret) { 4844 dev_err(hba->dev, "DME_RESET failed\n"); 4845 return ret; 4846 } 4847 4848 ret = ufshcd_dme_enable(hba); 4849 if (ret) { 4850 dev_err(hba->dev, "Enabling DME failed\n"); 4851 return ret; 4852 } 4853 4854 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4855 } else { 4856 ret = ufshcd_hba_execute_hce(hba); 4857 } 4858 4859 return ret; 4860 } 4861 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4862 4863 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4864 { 4865 int tx_lanes = 0, i, err = 0; 4866 4867 if (!peer) 4868 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4869 &tx_lanes); 4870 else 4871 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4872 &tx_lanes); 4873 for (i = 0; i < tx_lanes; i++) { 4874 if (!peer) 4875 err = ufshcd_dme_set(hba, 4876 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4877 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4878 0); 4879 else 4880 err = ufshcd_dme_peer_set(hba, 4881 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4882 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4883 0); 4884 if (err) { 4885 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4886 __func__, peer, i, err); 4887 break; 4888 } 4889 } 4890 4891 return err; 4892 } 4893 4894 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4895 { 4896 return ufshcd_disable_tx_lcc(hba, true); 4897 } 4898 4899 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4900 { 4901 struct ufs_event_hist *e; 4902 4903 if (id >= UFS_EVT_CNT) 4904 return; 4905 4906 e = &hba->ufs_stats.event[id]; 4907 e->val[e->pos] = val; 4908 e->tstamp[e->pos] = local_clock(); 4909 e->cnt += 1; 4910 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4911 4912 ufshcd_vops_event_notify(hba, id, &val); 4913 } 4914 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4915 4916 /** 4917 * ufshcd_link_startup - Initialize unipro link startup 4918 * @hba: per adapter instance 4919 * 4920 * Return: 0 for success, non-zero in case of failure. 4921 */ 4922 static int ufshcd_link_startup(struct ufs_hba *hba) 4923 { 4924 int ret; 4925 int retries = DME_LINKSTARTUP_RETRIES; 4926 bool link_startup_again = false; 4927 4928 /* 4929 * If UFS device isn't active then we will have to issue link startup 4930 * 2 times to make sure the device state move to active. 4931 */ 4932 if (!ufshcd_is_ufs_dev_active(hba)) 4933 link_startup_again = true; 4934 4935 link_startup: 4936 do { 4937 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4938 4939 ret = ufshcd_dme_link_startup(hba); 4940 4941 /* check if device is detected by inter-connect layer */ 4942 if (!ret && !ufshcd_is_device_present(hba)) { 4943 ufshcd_update_evt_hist(hba, 4944 UFS_EVT_LINK_STARTUP_FAIL, 4945 0); 4946 dev_err(hba->dev, "%s: Device not present\n", __func__); 4947 ret = -ENXIO; 4948 goto out; 4949 } 4950 4951 /* 4952 * DME link lost indication is only received when link is up, 4953 * but we can't be sure if the link is up until link startup 4954 * succeeds. So reset the local Uni-Pro and try again. 4955 */ 4956 if (ret && retries && ufshcd_hba_enable(hba)) { 4957 ufshcd_update_evt_hist(hba, 4958 UFS_EVT_LINK_STARTUP_FAIL, 4959 (u32)ret); 4960 goto out; 4961 } 4962 } while (ret && retries--); 4963 4964 if (ret) { 4965 /* failed to get the link up... retire */ 4966 ufshcd_update_evt_hist(hba, 4967 UFS_EVT_LINK_STARTUP_FAIL, 4968 (u32)ret); 4969 goto out; 4970 } 4971 4972 if (link_startup_again) { 4973 link_startup_again = false; 4974 retries = DME_LINKSTARTUP_RETRIES; 4975 goto link_startup; 4976 } 4977 4978 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 4979 ufshcd_init_pwr_info(hba); 4980 ufshcd_print_pwr_info(hba); 4981 4982 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 4983 ret = ufshcd_disable_device_tx_lcc(hba); 4984 if (ret) 4985 goto out; 4986 } 4987 4988 /* Include any host controller configuration via UIC commands */ 4989 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 4990 if (ret) 4991 goto out; 4992 4993 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 4994 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 4995 ret = ufshcd_make_hba_operational(hba); 4996 out: 4997 if (ret) { 4998 dev_err(hba->dev, "link startup failed %d\n", ret); 4999 ufshcd_print_host_state(hba); 5000 ufshcd_print_pwr_info(hba); 5001 ufshcd_print_evt_hist(hba); 5002 } 5003 return ret; 5004 } 5005 5006 /** 5007 * ufshcd_verify_dev_init() - Verify device initialization 5008 * @hba: per-adapter instance 5009 * 5010 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 5011 * device Transport Protocol (UTP) layer is ready after a reset. 5012 * If the UTP layer at the device side is not initialized, it may 5013 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 5014 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 5015 * 5016 * Return: 0 upon success; < 0 upon failure. 5017 */ 5018 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 5019 { 5020 int err = 0; 5021 int retries; 5022 5023 ufshcd_hold(hba); 5024 mutex_lock(&hba->dev_cmd.lock); 5025 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 5026 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 5027 hba->nop_out_timeout); 5028 5029 if (!err || err == -ETIMEDOUT) 5030 break; 5031 5032 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 5033 } 5034 mutex_unlock(&hba->dev_cmd.lock); 5035 ufshcd_release(hba); 5036 5037 if (err) 5038 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 5039 return err; 5040 } 5041 5042 /** 5043 * ufshcd_setup_links - associate link b/w device wlun and other luns 5044 * @sdev: pointer to SCSI device 5045 * @hba: pointer to ufs hba 5046 */ 5047 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 5048 { 5049 struct device_link *link; 5050 5051 /* 5052 * Device wlun is the supplier & rest of the luns are consumers. 5053 * This ensures that device wlun suspends after all other luns. 5054 */ 5055 if (hba->ufs_device_wlun) { 5056 link = device_link_add(&sdev->sdev_gendev, 5057 &hba->ufs_device_wlun->sdev_gendev, 5058 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 5059 if (!link) { 5060 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 5061 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 5062 return; 5063 } 5064 hba->luns_avail--; 5065 /* Ignore REPORT_LUN wlun probing */ 5066 if (hba->luns_avail == 1) { 5067 ufshcd_rpm_put(hba); 5068 return; 5069 } 5070 } else { 5071 /* 5072 * Device wlun is probed. The assumption is that WLUNs are 5073 * scanned before other LUNs. 5074 */ 5075 hba->luns_avail--; 5076 } 5077 } 5078 5079 /** 5080 * ufshcd_lu_init - Initialize the relevant parameters of the LU 5081 * @hba: per-adapter instance 5082 * @sdev: pointer to SCSI device 5083 */ 5084 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 5085 { 5086 int len = QUERY_DESC_MAX_SIZE; 5087 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 5088 u8 lun_qdepth = hba->nutrs; 5089 u8 *desc_buf; 5090 int ret; 5091 5092 desc_buf = kzalloc(len, GFP_KERNEL); 5093 if (!desc_buf) 5094 goto set_qdepth; 5095 5096 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5097 if (ret < 0) { 5098 if (ret == -EOPNOTSUPP) 5099 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5100 lun_qdepth = 1; 5101 kfree(desc_buf); 5102 goto set_qdepth; 5103 } 5104 5105 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5106 /* 5107 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5108 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5109 */ 5110 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5111 } 5112 /* 5113 * According to UFS device specification, the write protection mode is only supported by 5114 * normal LU, not supported by WLUN. 5115 */ 5116 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5117 !hba->dev_info.is_lu_power_on_wp && 5118 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5119 hba->dev_info.is_lu_power_on_wp = true; 5120 5121 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5122 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5123 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5124 hba->dev_info.b_advanced_rpmb_en = true; 5125 5126 5127 kfree(desc_buf); 5128 set_qdepth: 5129 /* 5130 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5131 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5132 */ 5133 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5134 scsi_change_queue_depth(sdev, lun_qdepth); 5135 } 5136 5137 /** 5138 * ufshcd_slave_alloc - handle initial SCSI device configurations 5139 * @sdev: pointer to SCSI device 5140 * 5141 * Return: success. 5142 */ 5143 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5144 { 5145 struct ufs_hba *hba; 5146 5147 hba = shost_priv(sdev->host); 5148 5149 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5150 sdev->use_10_for_ms = 1; 5151 5152 /* DBD field should be set to 1 in mode sense(10) */ 5153 sdev->set_dbd_for_ms = 1; 5154 5155 /* allow SCSI layer to restart the device in case of errors */ 5156 sdev->allow_restart = 1; 5157 5158 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5159 sdev->no_report_opcodes = 1; 5160 5161 /* WRITE_SAME command is not supported */ 5162 sdev->no_write_same = 1; 5163 5164 ufshcd_lu_init(hba, sdev); 5165 5166 ufshcd_setup_links(hba, sdev); 5167 5168 return 0; 5169 } 5170 5171 /** 5172 * ufshcd_change_queue_depth - change queue depth 5173 * @sdev: pointer to SCSI device 5174 * @depth: required depth to set 5175 * 5176 * Change queue depth and make sure the max. limits are not crossed. 5177 * 5178 * Return: new queue depth. 5179 */ 5180 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5181 { 5182 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5183 } 5184 5185 /** 5186 * ufshcd_slave_configure - adjust SCSI device configurations 5187 * @sdev: pointer to SCSI device 5188 * 5189 * Return: 0 (success). 5190 */ 5191 static int ufshcd_slave_configure(struct scsi_device *sdev) 5192 { 5193 struct ufs_hba *hba = shost_priv(sdev->host); 5194 struct request_queue *q = sdev->request_queue; 5195 5196 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1); 5197 5198 /* 5199 * Block runtime-pm until all consumers are added. 5200 * Refer ufshcd_setup_links(). 5201 */ 5202 if (is_device_wlun(sdev)) 5203 pm_runtime_get_noresume(&sdev->sdev_gendev); 5204 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5205 sdev->rpm_autosuspend = 1; 5206 /* 5207 * Do not print messages during runtime PM to avoid never-ending cycles 5208 * of messages written back to storage by user space causing runtime 5209 * resume, causing more messages and so on. 5210 */ 5211 sdev->silence_suspend = 1; 5212 5213 if (hba->vops && hba->vops->config_scsi_dev) 5214 hba->vops->config_scsi_dev(sdev); 5215 5216 ufshcd_crypto_register(hba, q); 5217 5218 return 0; 5219 } 5220 5221 /** 5222 * ufshcd_slave_destroy - remove SCSI device configurations 5223 * @sdev: pointer to SCSI device 5224 */ 5225 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5226 { 5227 struct ufs_hba *hba; 5228 unsigned long flags; 5229 5230 hba = shost_priv(sdev->host); 5231 5232 /* Drop the reference as it won't be needed anymore */ 5233 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5234 spin_lock_irqsave(hba->host->host_lock, flags); 5235 hba->ufs_device_wlun = NULL; 5236 spin_unlock_irqrestore(hba->host->host_lock, flags); 5237 } else if (hba->ufs_device_wlun) { 5238 struct device *supplier = NULL; 5239 5240 /* Ensure UFS Device WLUN exists and does not disappear */ 5241 spin_lock_irqsave(hba->host->host_lock, flags); 5242 if (hba->ufs_device_wlun) { 5243 supplier = &hba->ufs_device_wlun->sdev_gendev; 5244 get_device(supplier); 5245 } 5246 spin_unlock_irqrestore(hba->host->host_lock, flags); 5247 5248 if (supplier) { 5249 /* 5250 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5251 * device will not have been registered but can still 5252 * have a device link holding a reference to the device. 5253 */ 5254 device_link_remove(&sdev->sdev_gendev, supplier); 5255 put_device(supplier); 5256 } 5257 } 5258 } 5259 5260 /** 5261 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5262 * @lrbp: pointer to local reference block of completed command 5263 * @scsi_status: SCSI command status 5264 * 5265 * Return: value base on SCSI command status. 5266 */ 5267 static inline int 5268 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5269 { 5270 int result = 0; 5271 5272 switch (scsi_status) { 5273 case SAM_STAT_CHECK_CONDITION: 5274 ufshcd_copy_sense_data(lrbp); 5275 fallthrough; 5276 case SAM_STAT_GOOD: 5277 result |= DID_OK << 16 | scsi_status; 5278 break; 5279 case SAM_STAT_TASK_SET_FULL: 5280 case SAM_STAT_BUSY: 5281 case SAM_STAT_TASK_ABORTED: 5282 ufshcd_copy_sense_data(lrbp); 5283 result |= scsi_status; 5284 break; 5285 default: 5286 result |= DID_ERROR << 16; 5287 break; 5288 } /* end of switch */ 5289 5290 return result; 5291 } 5292 5293 /** 5294 * ufshcd_transfer_rsp_status - Get overall status of the response 5295 * @hba: per adapter instance 5296 * @lrbp: pointer to local reference block of completed command 5297 * @cqe: pointer to the completion queue entry 5298 * 5299 * Return: result of the command to notify SCSI midlayer. 5300 */ 5301 static inline int 5302 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5303 struct cq_entry *cqe) 5304 { 5305 int result = 0; 5306 int scsi_status; 5307 enum utp_ocs ocs; 5308 u8 upiu_flags; 5309 u32 resid; 5310 5311 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5312 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5313 /* 5314 * Test !overflow instead of underflow to support UFS devices that do 5315 * not set either flag. 5316 */ 5317 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5318 scsi_set_resid(lrbp->cmd, resid); 5319 5320 /* overall command status of utrd */ 5321 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5322 5323 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5324 if (lrbp->ucd_rsp_ptr->header.response || 5325 lrbp->ucd_rsp_ptr->header.status) 5326 ocs = OCS_SUCCESS; 5327 } 5328 5329 switch (ocs) { 5330 case OCS_SUCCESS: 5331 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5332 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5333 case UPIU_TRANSACTION_RESPONSE: 5334 /* 5335 * get the result based on SCSI status response 5336 * to notify the SCSI midlayer of the command status 5337 */ 5338 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5339 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5340 5341 /* 5342 * Currently we are only supporting BKOPs exception 5343 * events hence we can ignore BKOPs exception event 5344 * during power management callbacks. BKOPs exception 5345 * event is not expected to be raised in runtime suspend 5346 * callback as it allows the urgent bkops. 5347 * During system suspend, we are anyway forcefully 5348 * disabling the bkops and if urgent bkops is needed 5349 * it will be enabled on system resume. Long term 5350 * solution could be to abort the system suspend if 5351 * UFS device needs urgent BKOPs. 5352 */ 5353 if (!hba->pm_op_in_progress && 5354 !ufshcd_eh_in_progress(hba) && 5355 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5356 /* Flushed in suspend */ 5357 schedule_work(&hba->eeh_work); 5358 break; 5359 case UPIU_TRANSACTION_REJECT_UPIU: 5360 /* TODO: handle Reject UPIU Response */ 5361 result = DID_ERROR << 16; 5362 dev_err(hba->dev, 5363 "Reject UPIU not fully implemented\n"); 5364 break; 5365 default: 5366 dev_err(hba->dev, 5367 "Unexpected request response code = %x\n", 5368 result); 5369 result = DID_ERROR << 16; 5370 break; 5371 } 5372 break; 5373 case OCS_ABORTED: 5374 result |= DID_ABORT << 16; 5375 break; 5376 case OCS_INVALID_COMMAND_STATUS: 5377 result |= DID_REQUEUE << 16; 5378 break; 5379 case OCS_INVALID_CMD_TABLE_ATTR: 5380 case OCS_INVALID_PRDT_ATTR: 5381 case OCS_MISMATCH_DATA_BUF_SIZE: 5382 case OCS_MISMATCH_RESP_UPIU_SIZE: 5383 case OCS_PEER_COMM_FAILURE: 5384 case OCS_FATAL_ERROR: 5385 case OCS_DEVICE_FATAL_ERROR: 5386 case OCS_INVALID_CRYPTO_CONFIG: 5387 case OCS_GENERAL_CRYPTO_ERROR: 5388 default: 5389 result |= DID_ERROR << 16; 5390 dev_err(hba->dev, 5391 "OCS error from controller = %x for tag %d\n", 5392 ocs, lrbp->task_tag); 5393 ufshcd_print_evt_hist(hba); 5394 ufshcd_print_host_state(hba); 5395 break; 5396 } /* end of switch */ 5397 5398 if ((host_byte(result) != DID_OK) && 5399 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5400 ufshcd_print_tr(hba, lrbp->task_tag, true); 5401 return result; 5402 } 5403 5404 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5405 u32 intr_mask) 5406 { 5407 if (!ufshcd_is_auto_hibern8_supported(hba) || 5408 !ufshcd_is_auto_hibern8_enabled(hba)) 5409 return false; 5410 5411 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5412 return false; 5413 5414 if (hba->active_uic_cmd && 5415 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5416 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5417 return false; 5418 5419 return true; 5420 } 5421 5422 /** 5423 * ufshcd_uic_cmd_compl - handle completion of uic command 5424 * @hba: per adapter instance 5425 * @intr_status: interrupt status generated by the controller 5426 * 5427 * Return: 5428 * IRQ_HANDLED - If interrupt is valid 5429 * IRQ_NONE - If invalid interrupt 5430 */ 5431 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5432 { 5433 irqreturn_t retval = IRQ_NONE; 5434 5435 spin_lock(hba->host->host_lock); 5436 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5437 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5438 5439 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { 5440 hba->active_uic_cmd->argument2 |= 5441 ufshcd_get_uic_cmd_result(hba); 5442 hba->active_uic_cmd->argument3 = 5443 ufshcd_get_dme_attr_val(hba); 5444 if (!hba->uic_async_done) 5445 hba->active_uic_cmd->cmd_active = 0; 5446 complete(&hba->active_uic_cmd->done); 5447 retval = IRQ_HANDLED; 5448 } 5449 5450 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { 5451 hba->active_uic_cmd->cmd_active = 0; 5452 complete(hba->uic_async_done); 5453 retval = IRQ_HANDLED; 5454 } 5455 5456 if (retval == IRQ_HANDLED) 5457 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd, 5458 UFS_CMD_COMP); 5459 spin_unlock(hba->host->host_lock); 5460 return retval; 5461 } 5462 5463 /* Release the resources allocated for processing a SCSI command. */ 5464 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5465 struct ufshcd_lrb *lrbp) 5466 { 5467 struct scsi_cmnd *cmd = lrbp->cmd; 5468 5469 scsi_dma_unmap(cmd); 5470 ufshcd_release(hba); 5471 ufshcd_clk_scaling_update_busy(hba); 5472 } 5473 5474 /** 5475 * ufshcd_compl_one_cqe - handle a completion queue entry 5476 * @hba: per adapter instance 5477 * @task_tag: the task tag of the request to be completed 5478 * @cqe: pointer to the completion queue entry 5479 */ 5480 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5481 struct cq_entry *cqe) 5482 { 5483 struct ufshcd_lrb *lrbp; 5484 struct scsi_cmnd *cmd; 5485 enum utp_ocs ocs; 5486 5487 lrbp = &hba->lrb[task_tag]; 5488 lrbp->compl_time_stamp = ktime_get(); 5489 cmd = lrbp->cmd; 5490 if (cmd) { 5491 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5492 ufshcd_update_monitor(hba, lrbp); 5493 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5494 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5495 ufshcd_release_scsi_cmd(hba, lrbp); 5496 /* Do not touch lrbp after scsi done */ 5497 scsi_done(cmd); 5498 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE || 5499 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) { 5500 if (hba->dev_cmd.complete) { 5501 if (cqe) { 5502 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5503 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5504 } 5505 complete(hba->dev_cmd.complete); 5506 } 5507 } 5508 } 5509 5510 /** 5511 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5512 * @hba: per adapter instance 5513 * @completed_reqs: bitmask that indicates which requests to complete 5514 */ 5515 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5516 unsigned long completed_reqs) 5517 { 5518 int tag; 5519 5520 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5521 ufshcd_compl_one_cqe(hba, tag, NULL); 5522 } 5523 5524 /* Any value that is not an existing queue number is fine for this constant. */ 5525 enum { 5526 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5527 }; 5528 5529 static void ufshcd_clear_polled(struct ufs_hba *hba, 5530 unsigned long *completed_reqs) 5531 { 5532 int tag; 5533 5534 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5535 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5536 5537 if (!cmd) 5538 continue; 5539 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5540 __clear_bit(tag, completed_reqs); 5541 } 5542 } 5543 5544 /* 5545 * Return: > 0 if one or more commands have been completed or 0 if no 5546 * requests have been completed. 5547 */ 5548 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5549 { 5550 struct ufs_hba *hba = shost_priv(shost); 5551 unsigned long completed_reqs, flags; 5552 u32 tr_doorbell; 5553 struct ufs_hw_queue *hwq; 5554 5555 if (is_mcq_enabled(hba)) { 5556 hwq = &hba->uhq[queue_num]; 5557 5558 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5559 } 5560 5561 spin_lock_irqsave(&hba->outstanding_lock, flags); 5562 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5563 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5564 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5565 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5566 hba->outstanding_reqs); 5567 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5568 /* Do not complete polled requests from interrupt context. */ 5569 ufshcd_clear_polled(hba, &completed_reqs); 5570 } 5571 hba->outstanding_reqs &= ~completed_reqs; 5572 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5573 5574 if (completed_reqs) 5575 __ufshcd_transfer_req_compl(hba, completed_reqs); 5576 5577 return completed_reqs != 0; 5578 } 5579 5580 /** 5581 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5582 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5583 * to complete the pending transfers and free the resources associated with 5584 * the scsi command. 5585 * 5586 * @hba: per adapter instance 5587 * @force_compl: This flag is set to true when invoked 5588 * from ufshcd_host_reset_and_restore() in which case it requires special 5589 * handling because the host controller has been reset by ufshcd_hba_stop(). 5590 */ 5591 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5592 bool force_compl) 5593 { 5594 struct ufs_hw_queue *hwq; 5595 struct ufshcd_lrb *lrbp; 5596 struct scsi_cmnd *cmd; 5597 unsigned long flags; 5598 u32 hwq_num, utag; 5599 int tag; 5600 5601 for (tag = 0; tag < hba->nutrs; tag++) { 5602 lrbp = &hba->lrb[tag]; 5603 cmd = lrbp->cmd; 5604 if (!ufshcd_cmd_inflight(cmd) || 5605 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5606 continue; 5607 5608 utag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 5609 hwq_num = blk_mq_unique_tag_to_hwq(utag); 5610 hwq = &hba->uhq[hwq_num]; 5611 5612 if (force_compl) { 5613 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5614 /* 5615 * For those cmds of which the cqes are not present 5616 * in the cq, complete them explicitly. 5617 */ 5618 spin_lock_irqsave(&hwq->cq_lock, flags); 5619 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5620 set_host_byte(cmd, DID_REQUEUE); 5621 ufshcd_release_scsi_cmd(hba, lrbp); 5622 scsi_done(cmd); 5623 } 5624 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5625 } else { 5626 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5627 } 5628 } 5629 } 5630 5631 /** 5632 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5633 * @hba: per adapter instance 5634 * 5635 * Return: 5636 * IRQ_HANDLED - If interrupt is valid 5637 * IRQ_NONE - If invalid interrupt 5638 */ 5639 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5640 { 5641 /* Resetting interrupt aggregation counters first and reading the 5642 * DOOR_BELL afterward allows us to handle all the completed requests. 5643 * In order to prevent other interrupts starvation the DB is read once 5644 * after reset. The down side of this solution is the possibility of 5645 * false interrupt if device completes another request after resetting 5646 * aggregation and before reading the DB. 5647 */ 5648 if (ufshcd_is_intr_aggr_allowed(hba) && 5649 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5650 ufshcd_reset_intr_aggr(hba); 5651 5652 if (ufs_fail_completion()) 5653 return IRQ_HANDLED; 5654 5655 /* 5656 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5657 * do not want polling to trigger spurious interrupt complaints. 5658 */ 5659 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5660 5661 return IRQ_HANDLED; 5662 } 5663 5664 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5665 { 5666 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5667 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5668 &ee_ctrl_mask); 5669 } 5670 5671 int ufshcd_write_ee_control(struct ufs_hba *hba) 5672 { 5673 int err; 5674 5675 mutex_lock(&hba->ee_ctrl_mutex); 5676 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5677 mutex_unlock(&hba->ee_ctrl_mutex); 5678 if (err) 5679 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5680 __func__, err); 5681 return err; 5682 } 5683 5684 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5685 const u16 *other_mask, u16 set, u16 clr) 5686 { 5687 u16 new_mask, ee_ctrl_mask; 5688 int err = 0; 5689 5690 mutex_lock(&hba->ee_ctrl_mutex); 5691 new_mask = (*mask & ~clr) | set; 5692 ee_ctrl_mask = new_mask | *other_mask; 5693 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5694 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5695 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5696 if (!err) { 5697 hba->ee_ctrl_mask = ee_ctrl_mask; 5698 *mask = new_mask; 5699 } 5700 mutex_unlock(&hba->ee_ctrl_mutex); 5701 return err; 5702 } 5703 5704 /** 5705 * ufshcd_disable_ee - disable exception event 5706 * @hba: per-adapter instance 5707 * @mask: exception event to disable 5708 * 5709 * Disables exception event in the device so that the EVENT_ALERT 5710 * bit is not set. 5711 * 5712 * Return: zero on success, non-zero error value on failure. 5713 */ 5714 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5715 { 5716 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5717 } 5718 5719 /** 5720 * ufshcd_enable_ee - enable exception event 5721 * @hba: per-adapter instance 5722 * @mask: exception event to enable 5723 * 5724 * Enable corresponding exception event in the device to allow 5725 * device to alert host in critical scenarios. 5726 * 5727 * Return: zero on success, non-zero error value on failure. 5728 */ 5729 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5730 { 5731 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5732 } 5733 5734 /** 5735 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5736 * @hba: per-adapter instance 5737 * 5738 * Allow device to manage background operations on its own. Enabling 5739 * this might lead to inconsistent latencies during normal data transfers 5740 * as the device is allowed to manage its own way of handling background 5741 * operations. 5742 * 5743 * Return: zero on success, non-zero on failure. 5744 */ 5745 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5746 { 5747 int err = 0; 5748 5749 if (hba->auto_bkops_enabled) 5750 goto out; 5751 5752 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5753 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5754 if (err) { 5755 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5756 __func__, err); 5757 goto out; 5758 } 5759 5760 hba->auto_bkops_enabled = true; 5761 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5762 5763 /* No need of URGENT_BKOPS exception from the device */ 5764 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5765 if (err) 5766 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5767 __func__, err); 5768 out: 5769 return err; 5770 } 5771 5772 /** 5773 * ufshcd_disable_auto_bkops - block device in doing background operations 5774 * @hba: per-adapter instance 5775 * 5776 * Disabling background operations improves command response latency but 5777 * has drawback of device moving into critical state where the device is 5778 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5779 * host is idle so that BKOPS are managed effectively without any negative 5780 * impacts. 5781 * 5782 * Return: zero on success, non-zero on failure. 5783 */ 5784 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5785 { 5786 int err = 0; 5787 5788 if (!hba->auto_bkops_enabled) 5789 goto out; 5790 5791 /* 5792 * If host assisted BKOPs is to be enabled, make sure 5793 * urgent bkops exception is allowed. 5794 */ 5795 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5796 if (err) { 5797 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5798 __func__, err); 5799 goto out; 5800 } 5801 5802 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5803 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5804 if (err) { 5805 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5806 __func__, err); 5807 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5808 goto out; 5809 } 5810 5811 hba->auto_bkops_enabled = false; 5812 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5813 hba->is_urgent_bkops_lvl_checked = false; 5814 out: 5815 return err; 5816 } 5817 5818 /** 5819 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5820 * @hba: per adapter instance 5821 * 5822 * After a device reset the device may toggle the BKOPS_EN flag 5823 * to default value. The s/w tracking variables should be updated 5824 * as well. This function would change the auto-bkops state based on 5825 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5826 */ 5827 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5828 { 5829 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5830 hba->auto_bkops_enabled = false; 5831 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5832 ufshcd_enable_auto_bkops(hba); 5833 } else { 5834 hba->auto_bkops_enabled = true; 5835 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5836 ufshcd_disable_auto_bkops(hba); 5837 } 5838 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5839 hba->is_urgent_bkops_lvl_checked = false; 5840 } 5841 5842 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5843 { 5844 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5845 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5846 } 5847 5848 /** 5849 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5850 * @hba: per-adapter instance 5851 * @status: bkops_status value 5852 * 5853 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5854 * flag in the device to permit background operations if the device 5855 * bkops_status is greater than or equal to "status" argument passed to 5856 * this function, disable otherwise. 5857 * 5858 * Return: 0 for success, non-zero in case of failure. 5859 * 5860 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5861 * to know whether auto bkops is enabled or disabled after this function 5862 * returns control to it. 5863 */ 5864 static int ufshcd_bkops_ctrl(struct ufs_hba *hba, 5865 enum bkops_status status) 5866 { 5867 int err; 5868 u32 curr_status = 0; 5869 5870 err = ufshcd_get_bkops_status(hba, &curr_status); 5871 if (err) { 5872 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5873 __func__, err); 5874 goto out; 5875 } else if (curr_status > BKOPS_STATUS_MAX) { 5876 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5877 __func__, curr_status); 5878 err = -EINVAL; 5879 goto out; 5880 } 5881 5882 if (curr_status >= status) 5883 err = ufshcd_enable_auto_bkops(hba); 5884 else 5885 err = ufshcd_disable_auto_bkops(hba); 5886 out: 5887 return err; 5888 } 5889 5890 /** 5891 * ufshcd_urgent_bkops - handle urgent bkops exception event 5892 * @hba: per-adapter instance 5893 * 5894 * Enable fBackgroundOpsEn flag in the device to permit background 5895 * operations. 5896 * 5897 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled 5898 * and negative error value for any other failure. 5899 * 5900 * Return: 0 upon success; < 0 upon failure. 5901 */ 5902 static int ufshcd_urgent_bkops(struct ufs_hba *hba) 5903 { 5904 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl); 5905 } 5906 5907 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5908 { 5909 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5910 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5911 } 5912 5913 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5914 { 5915 int err; 5916 u32 curr_status = 0; 5917 5918 if (hba->is_urgent_bkops_lvl_checked) 5919 goto enable_auto_bkops; 5920 5921 err = ufshcd_get_bkops_status(hba, &curr_status); 5922 if (err) { 5923 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5924 __func__, err); 5925 goto out; 5926 } 5927 5928 /* 5929 * We are seeing that some devices are raising the urgent bkops 5930 * exception events even when BKOPS status doesn't indicate performace 5931 * impacted or critical. Handle these device by determining their urgent 5932 * bkops status at runtime. 5933 */ 5934 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5935 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5936 __func__, curr_status); 5937 /* update the current status as the urgent bkops level */ 5938 hba->urgent_bkops_lvl = curr_status; 5939 hba->is_urgent_bkops_lvl_checked = true; 5940 } 5941 5942 enable_auto_bkops: 5943 err = ufshcd_enable_auto_bkops(hba); 5944 out: 5945 if (err < 0) 5946 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5947 __func__, err); 5948 } 5949 5950 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5951 { 5952 u32 value; 5953 5954 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5955 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 5956 return; 5957 5958 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 5959 5960 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 5961 5962 /* 5963 * A placeholder for the platform vendors to add whatever additional 5964 * steps required 5965 */ 5966 } 5967 5968 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 5969 { 5970 u8 index; 5971 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 5972 UPIU_QUERY_OPCODE_CLEAR_FLAG; 5973 5974 index = ufshcd_wb_get_query_index(hba); 5975 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 5976 } 5977 5978 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 5979 { 5980 int ret; 5981 5982 if (!ufshcd_is_wb_allowed(hba) || 5983 hba->dev_info.wb_enabled == enable) 5984 return 0; 5985 5986 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 5987 if (ret) { 5988 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 5989 __func__, enable ? "enabling" : "disabling", ret); 5990 return ret; 5991 } 5992 5993 hba->dev_info.wb_enabled = enable; 5994 dev_dbg(hba->dev, "%s: Write Booster %s\n", 5995 __func__, enable ? "enabled" : "disabled"); 5996 5997 return ret; 5998 } 5999 6000 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 6001 bool enable) 6002 { 6003 int ret; 6004 6005 ret = __ufshcd_wb_toggle(hba, enable, 6006 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 6007 if (ret) { 6008 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 6009 __func__, enable ? "enabling" : "disabling", ret); 6010 return; 6011 } 6012 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 6013 __func__, enable ? "enabled" : "disabled"); 6014 } 6015 6016 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 6017 { 6018 int ret; 6019 6020 if (!ufshcd_is_wb_allowed(hba) || 6021 hba->dev_info.wb_buf_flush_enabled == enable) 6022 return 0; 6023 6024 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 6025 if (ret) { 6026 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 6027 __func__, enable ? "enabling" : "disabling", ret); 6028 return ret; 6029 } 6030 6031 hba->dev_info.wb_buf_flush_enabled = enable; 6032 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 6033 __func__, enable ? "enabled" : "disabled"); 6034 6035 return ret; 6036 } 6037 6038 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 6039 u32 avail_buf) 6040 { 6041 u32 cur_buf; 6042 int ret; 6043 u8 index; 6044 6045 index = ufshcd_wb_get_query_index(hba); 6046 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6047 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 6048 index, 0, &cur_buf); 6049 if (ret) { 6050 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 6051 __func__, ret); 6052 return false; 6053 } 6054 6055 if (!cur_buf) { 6056 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 6057 cur_buf); 6058 return false; 6059 } 6060 /* Let it continue to flush when available buffer exceeds threshold */ 6061 return avail_buf < hba->vps->wb_flush_threshold; 6062 } 6063 6064 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 6065 { 6066 if (ufshcd_is_wb_buf_flush_allowed(hba)) 6067 ufshcd_wb_toggle_buf_flush(hba, false); 6068 6069 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 6070 ufshcd_wb_toggle(hba, false); 6071 hba->caps &= ~UFSHCD_CAP_WB_EN; 6072 6073 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 6074 } 6075 6076 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 6077 { 6078 u32 lifetime; 6079 int ret; 6080 u8 index; 6081 6082 index = ufshcd_wb_get_query_index(hba); 6083 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6084 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 6085 index, 0, &lifetime); 6086 if (ret) { 6087 dev_err(hba->dev, 6088 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 6089 __func__, ret); 6090 return false; 6091 } 6092 6093 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6094 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6095 __func__, lifetime); 6096 return false; 6097 } 6098 6099 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6100 __func__, lifetime); 6101 6102 return true; 6103 } 6104 6105 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6106 { 6107 int ret; 6108 u32 avail_buf; 6109 u8 index; 6110 6111 if (!ufshcd_is_wb_allowed(hba)) 6112 return false; 6113 6114 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6115 ufshcd_wb_force_disable(hba); 6116 return false; 6117 } 6118 6119 /* 6120 * The ufs device needs the vcc to be ON to flush. 6121 * With user-space reduction enabled, it's enough to enable flush 6122 * by checking only the available buffer. The threshold 6123 * defined here is > 90% full. 6124 * With user-space preserved enabled, the current-buffer 6125 * should be checked too because the wb buffer size can reduce 6126 * when disk tends to be full. This info is provided by current 6127 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6128 * keeping vcc on when current buffer is empty. 6129 */ 6130 index = ufshcd_wb_get_query_index(hba); 6131 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6132 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6133 index, 0, &avail_buf); 6134 if (ret) { 6135 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6136 __func__, ret); 6137 return false; 6138 } 6139 6140 if (!hba->dev_info.b_presrv_uspc_en) 6141 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6142 6143 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6144 } 6145 6146 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6147 { 6148 struct ufs_hba *hba = container_of(to_delayed_work(work), 6149 struct ufs_hba, 6150 rpm_dev_flush_recheck_work); 6151 /* 6152 * To prevent unnecessary VCC power drain after device finishes 6153 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6154 * after a certain delay to recheck the threshold by next runtime 6155 * suspend. 6156 */ 6157 ufshcd_rpm_get_sync(hba); 6158 ufshcd_rpm_put_sync(hba); 6159 } 6160 6161 /** 6162 * ufshcd_exception_event_handler - handle exceptions raised by device 6163 * @work: pointer to work data 6164 * 6165 * Read bExceptionEventStatus attribute from the device and handle the 6166 * exception event accordingly. 6167 */ 6168 static void ufshcd_exception_event_handler(struct work_struct *work) 6169 { 6170 struct ufs_hba *hba; 6171 int err; 6172 u32 status = 0; 6173 hba = container_of(work, struct ufs_hba, eeh_work); 6174 6175 ufshcd_scsi_block_requests(hba); 6176 err = ufshcd_get_ee_status(hba, &status); 6177 if (err) { 6178 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6179 __func__, err); 6180 goto out; 6181 } 6182 6183 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6184 6185 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6186 ufshcd_bkops_exception_event_handler(hba); 6187 6188 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6189 ufshcd_temp_exception_event_handler(hba, status); 6190 6191 ufs_debugfs_exception_event(hba, status); 6192 out: 6193 ufshcd_scsi_unblock_requests(hba); 6194 } 6195 6196 /* Complete requests that have door-bell cleared */ 6197 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6198 { 6199 if (is_mcq_enabled(hba)) 6200 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6201 else 6202 ufshcd_transfer_req_compl(hba); 6203 6204 ufshcd_tmc_handler(hba); 6205 } 6206 6207 /** 6208 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6209 * to recover from the DL NAC errors or not. 6210 * @hba: per-adapter instance 6211 * 6212 * Return: true if error handling is required, false otherwise. 6213 */ 6214 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6215 { 6216 unsigned long flags; 6217 bool err_handling = true; 6218 6219 spin_lock_irqsave(hba->host->host_lock, flags); 6220 /* 6221 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6222 * device fatal error and/or DL NAC & REPLAY timeout errors. 6223 */ 6224 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6225 goto out; 6226 6227 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6228 ((hba->saved_err & UIC_ERROR) && 6229 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6230 goto out; 6231 6232 if ((hba->saved_err & UIC_ERROR) && 6233 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6234 int err; 6235 /* 6236 * wait for 50ms to see if we can get any other errors or not. 6237 */ 6238 spin_unlock_irqrestore(hba->host->host_lock, flags); 6239 msleep(50); 6240 spin_lock_irqsave(hba->host->host_lock, flags); 6241 6242 /* 6243 * now check if we have got any other severe errors other than 6244 * DL NAC error? 6245 */ 6246 if ((hba->saved_err & INT_FATAL_ERRORS) || 6247 ((hba->saved_err & UIC_ERROR) && 6248 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6249 goto out; 6250 6251 /* 6252 * As DL NAC is the only error received so far, send out NOP 6253 * command to confirm if link is still active or not. 6254 * - If we don't get any response then do error recovery. 6255 * - If we get response then clear the DL NAC error bit. 6256 */ 6257 6258 spin_unlock_irqrestore(hba->host->host_lock, flags); 6259 err = ufshcd_verify_dev_init(hba); 6260 spin_lock_irqsave(hba->host->host_lock, flags); 6261 6262 if (err) 6263 goto out; 6264 6265 /* Link seems to be alive hence ignore the DL NAC errors */ 6266 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6267 hba->saved_err &= ~UIC_ERROR; 6268 /* clear NAC error */ 6269 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6270 if (!hba->saved_uic_err) 6271 err_handling = false; 6272 } 6273 out: 6274 spin_unlock_irqrestore(hba->host->host_lock, flags); 6275 return err_handling; 6276 } 6277 6278 /* host lock must be held before calling this func */ 6279 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6280 { 6281 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6282 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6283 } 6284 6285 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6286 { 6287 lockdep_assert_held(hba->host->host_lock); 6288 6289 /* handle fatal errors only when link is not in error state */ 6290 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6291 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6292 ufshcd_is_saved_err_fatal(hba)) 6293 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6294 else 6295 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6296 queue_work(hba->eh_wq, &hba->eh_work); 6297 } 6298 } 6299 6300 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6301 { 6302 spin_lock_irq(hba->host->host_lock); 6303 hba->force_reset = true; 6304 ufshcd_schedule_eh_work(hba); 6305 spin_unlock_irq(hba->host->host_lock); 6306 } 6307 6308 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6309 { 6310 mutex_lock(&hba->wb_mutex); 6311 down_write(&hba->clk_scaling_lock); 6312 hba->clk_scaling.is_allowed = allow; 6313 up_write(&hba->clk_scaling_lock); 6314 mutex_unlock(&hba->wb_mutex); 6315 } 6316 6317 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6318 { 6319 if (suspend) { 6320 if (hba->clk_scaling.is_enabled) 6321 ufshcd_suspend_clkscaling(hba); 6322 ufshcd_clk_scaling_allow(hba, false); 6323 } else { 6324 ufshcd_clk_scaling_allow(hba, true); 6325 if (hba->clk_scaling.is_enabled) 6326 ufshcd_resume_clkscaling(hba); 6327 } 6328 } 6329 6330 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6331 { 6332 ufshcd_rpm_get_sync(hba); 6333 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6334 hba->is_sys_suspended) { 6335 enum ufs_pm_op pm_op; 6336 6337 /* 6338 * Don't assume anything of resume, if 6339 * resume fails, irq and clocks can be OFF, and powers 6340 * can be OFF or in LPM. 6341 */ 6342 ufshcd_setup_hba_vreg(hba, true); 6343 ufshcd_enable_irq(hba); 6344 ufshcd_setup_vreg(hba, true); 6345 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6346 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6347 ufshcd_hold(hba); 6348 if (!ufshcd_is_clkgating_allowed(hba)) 6349 ufshcd_setup_clocks(hba, true); 6350 ufshcd_release(hba); 6351 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6352 ufshcd_vops_resume(hba, pm_op); 6353 } else { 6354 ufshcd_hold(hba); 6355 if (ufshcd_is_clkscaling_supported(hba) && 6356 hba->clk_scaling.is_enabled) 6357 ufshcd_suspend_clkscaling(hba); 6358 ufshcd_clk_scaling_allow(hba, false); 6359 } 6360 ufshcd_scsi_block_requests(hba); 6361 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6362 blk_mq_wait_quiesce_done(&hba->host->tag_set); 6363 cancel_work_sync(&hba->eeh_work); 6364 } 6365 6366 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6367 { 6368 ufshcd_scsi_unblock_requests(hba); 6369 ufshcd_release(hba); 6370 if (ufshcd_is_clkscaling_supported(hba)) 6371 ufshcd_clk_scaling_suspend(hba, false); 6372 ufshcd_rpm_put(hba); 6373 } 6374 6375 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6376 { 6377 return (!hba->is_powered || hba->shutting_down || 6378 !hba->ufs_device_wlun || 6379 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6380 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6381 ufshcd_is_link_broken(hba)))); 6382 } 6383 6384 #ifdef CONFIG_PM 6385 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6386 { 6387 struct Scsi_Host *shost = hba->host; 6388 struct scsi_device *sdev; 6389 struct request_queue *q; 6390 int ret; 6391 6392 hba->is_sys_suspended = false; 6393 /* 6394 * Set RPM status of wlun device to RPM_ACTIVE, 6395 * this also clears its runtime error. 6396 */ 6397 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6398 6399 /* hba device might have a runtime error otherwise */ 6400 if (ret) 6401 ret = pm_runtime_set_active(hba->dev); 6402 /* 6403 * If wlun device had runtime error, we also need to resume those 6404 * consumer scsi devices in case any of them has failed to be 6405 * resumed due to supplier runtime resume failure. This is to unblock 6406 * blk_queue_enter in case there are bios waiting inside it. 6407 */ 6408 if (!ret) { 6409 shost_for_each_device(sdev, shost) { 6410 q = sdev->request_queue; 6411 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6412 q->rpm_status == RPM_SUSPENDING)) 6413 pm_request_resume(q->dev); 6414 } 6415 } 6416 } 6417 #else 6418 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6419 { 6420 } 6421 #endif 6422 6423 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6424 { 6425 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6426 u32 mode; 6427 6428 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6429 6430 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6431 return true; 6432 6433 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6434 return true; 6435 6436 return false; 6437 } 6438 6439 static bool ufshcd_abort_one(struct request *rq, void *priv) 6440 { 6441 int *ret = priv; 6442 u32 tag = rq->tag; 6443 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6444 struct scsi_device *sdev = cmd->device; 6445 struct Scsi_Host *shost = sdev->host; 6446 struct ufs_hba *hba = shost_priv(shost); 6447 6448 *ret = ufshcd_try_to_abort_task(hba, tag); 6449 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6450 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6451 *ret ? "failed" : "succeeded"); 6452 return *ret == 0; 6453 } 6454 6455 /** 6456 * ufshcd_abort_all - Abort all pending commands. 6457 * @hba: Host bus adapter pointer. 6458 * 6459 * Return: true if and only if the host controller needs to be reset. 6460 */ 6461 static bool ufshcd_abort_all(struct ufs_hba *hba) 6462 { 6463 int tag, ret = 0; 6464 6465 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6466 if (ret) 6467 goto out; 6468 6469 /* Clear pending task management requests */ 6470 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6471 ret = ufshcd_clear_tm_cmd(hba, tag); 6472 if (ret) 6473 goto out; 6474 } 6475 6476 out: 6477 /* Complete the requests that are cleared by s/w */ 6478 ufshcd_complete_requests(hba, false); 6479 6480 return ret != 0; 6481 } 6482 6483 /** 6484 * ufshcd_err_handler - handle UFS errors that require s/w attention 6485 * @work: pointer to work structure 6486 */ 6487 static void ufshcd_err_handler(struct work_struct *work) 6488 { 6489 int retries = MAX_ERR_HANDLER_RETRIES; 6490 struct ufs_hba *hba; 6491 unsigned long flags; 6492 bool needs_restore; 6493 bool needs_reset; 6494 int pmc_err; 6495 6496 hba = container_of(work, struct ufs_hba, eh_work); 6497 6498 dev_info(hba->dev, 6499 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6500 __func__, ufshcd_state_name[hba->ufshcd_state], 6501 hba->is_powered, hba->shutting_down, hba->saved_err, 6502 hba->saved_uic_err, hba->force_reset, 6503 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6504 6505 down(&hba->host_sem); 6506 spin_lock_irqsave(hba->host->host_lock, flags); 6507 if (ufshcd_err_handling_should_stop(hba)) { 6508 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6509 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6510 spin_unlock_irqrestore(hba->host->host_lock, flags); 6511 up(&hba->host_sem); 6512 return; 6513 } 6514 ufshcd_set_eh_in_progress(hba); 6515 spin_unlock_irqrestore(hba->host->host_lock, flags); 6516 ufshcd_err_handling_prepare(hba); 6517 /* Complete requests that have door-bell cleared by h/w */ 6518 ufshcd_complete_requests(hba, false); 6519 spin_lock_irqsave(hba->host->host_lock, flags); 6520 again: 6521 needs_restore = false; 6522 needs_reset = false; 6523 6524 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6525 hba->ufshcd_state = UFSHCD_STATE_RESET; 6526 /* 6527 * A full reset and restore might have happened after preparation 6528 * is finished, double check whether we should stop. 6529 */ 6530 if (ufshcd_err_handling_should_stop(hba)) 6531 goto skip_err_handling; 6532 6533 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6534 bool ret; 6535 6536 spin_unlock_irqrestore(hba->host->host_lock, flags); 6537 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6538 ret = ufshcd_quirk_dl_nac_errors(hba); 6539 spin_lock_irqsave(hba->host->host_lock, flags); 6540 if (!ret && ufshcd_err_handling_should_stop(hba)) 6541 goto skip_err_handling; 6542 } 6543 6544 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6545 (hba->saved_uic_err && 6546 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6547 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6548 6549 spin_unlock_irqrestore(hba->host->host_lock, flags); 6550 ufshcd_print_host_state(hba); 6551 ufshcd_print_pwr_info(hba); 6552 ufshcd_print_evt_hist(hba); 6553 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6554 ufshcd_print_trs_all(hba, pr_prdt); 6555 spin_lock_irqsave(hba->host->host_lock, flags); 6556 } 6557 6558 /* 6559 * if host reset is required then skip clearing the pending 6560 * transfers forcefully because they will get cleared during 6561 * host reset and restore 6562 */ 6563 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6564 ufshcd_is_saved_err_fatal(hba) || 6565 ((hba->saved_err & UIC_ERROR) && 6566 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6567 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6568 needs_reset = true; 6569 goto do_reset; 6570 } 6571 6572 /* 6573 * If LINERESET was caught, UFS might have been put to PWM mode, 6574 * check if power mode restore is needed. 6575 */ 6576 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6577 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6578 if (!hba->saved_uic_err) 6579 hba->saved_err &= ~UIC_ERROR; 6580 spin_unlock_irqrestore(hba->host->host_lock, flags); 6581 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6582 needs_restore = true; 6583 spin_lock_irqsave(hba->host->host_lock, flags); 6584 if (!hba->saved_err && !needs_restore) 6585 goto skip_err_handling; 6586 } 6587 6588 hba->silence_err_logs = true; 6589 /* release lock as clear command might sleep */ 6590 spin_unlock_irqrestore(hba->host->host_lock, flags); 6591 6592 needs_reset = ufshcd_abort_all(hba); 6593 6594 spin_lock_irqsave(hba->host->host_lock, flags); 6595 hba->silence_err_logs = false; 6596 if (needs_reset) 6597 goto do_reset; 6598 6599 /* 6600 * After all reqs and tasks are cleared from doorbell, 6601 * now it is safe to retore power mode. 6602 */ 6603 if (needs_restore) { 6604 spin_unlock_irqrestore(hba->host->host_lock, flags); 6605 /* 6606 * Hold the scaling lock just in case dev cmds 6607 * are sent via bsg and/or sysfs. 6608 */ 6609 down_write(&hba->clk_scaling_lock); 6610 hba->force_pmc = true; 6611 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6612 if (pmc_err) { 6613 needs_reset = true; 6614 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6615 __func__, pmc_err); 6616 } 6617 hba->force_pmc = false; 6618 ufshcd_print_pwr_info(hba); 6619 up_write(&hba->clk_scaling_lock); 6620 spin_lock_irqsave(hba->host->host_lock, flags); 6621 } 6622 6623 do_reset: 6624 /* Fatal errors need reset */ 6625 if (needs_reset) { 6626 int err; 6627 6628 hba->force_reset = false; 6629 spin_unlock_irqrestore(hba->host->host_lock, flags); 6630 err = ufshcd_reset_and_restore(hba); 6631 if (err) 6632 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6633 __func__, err); 6634 else 6635 ufshcd_recover_pm_error(hba); 6636 spin_lock_irqsave(hba->host->host_lock, flags); 6637 } 6638 6639 skip_err_handling: 6640 if (!needs_reset) { 6641 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6642 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6643 if (hba->saved_err || hba->saved_uic_err) 6644 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6645 __func__, hba->saved_err, hba->saved_uic_err); 6646 } 6647 /* Exit in an operational state or dead */ 6648 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6649 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6650 if (--retries) 6651 goto again; 6652 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6653 } 6654 ufshcd_clear_eh_in_progress(hba); 6655 spin_unlock_irqrestore(hba->host->host_lock, flags); 6656 ufshcd_err_handling_unprepare(hba); 6657 up(&hba->host_sem); 6658 6659 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6660 ufshcd_state_name[hba->ufshcd_state]); 6661 } 6662 6663 /** 6664 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6665 * @hba: per-adapter instance 6666 * 6667 * Return: 6668 * IRQ_HANDLED - If interrupt is valid 6669 * IRQ_NONE - If invalid interrupt 6670 */ 6671 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6672 { 6673 u32 reg; 6674 irqreturn_t retval = IRQ_NONE; 6675 6676 /* PHY layer error */ 6677 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6678 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6679 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6680 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6681 /* 6682 * To know whether this error is fatal or not, DB timeout 6683 * must be checked but this error is handled separately. 6684 */ 6685 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6686 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6687 __func__); 6688 6689 /* Got a LINERESET indication. */ 6690 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6691 struct uic_command *cmd = NULL; 6692 6693 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6694 if (hba->uic_async_done && hba->active_uic_cmd) 6695 cmd = hba->active_uic_cmd; 6696 /* 6697 * Ignore the LINERESET during power mode change 6698 * operation via DME_SET command. 6699 */ 6700 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6701 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6702 } 6703 retval |= IRQ_HANDLED; 6704 } 6705 6706 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6707 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6708 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6709 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6710 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6711 6712 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6713 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6714 else if (hba->dev_quirks & 6715 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6716 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6717 hba->uic_error |= 6718 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6719 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6720 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6721 } 6722 retval |= IRQ_HANDLED; 6723 } 6724 6725 /* UIC NL/TL/DME errors needs software retry */ 6726 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6727 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6728 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6729 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6730 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6731 retval |= IRQ_HANDLED; 6732 } 6733 6734 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6735 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6736 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6737 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6738 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6739 retval |= IRQ_HANDLED; 6740 } 6741 6742 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6743 if ((reg & UIC_DME_ERROR) && 6744 (reg & UIC_DME_ERROR_CODE_MASK)) { 6745 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6746 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6747 retval |= IRQ_HANDLED; 6748 } 6749 6750 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6751 __func__, hba->uic_error); 6752 return retval; 6753 } 6754 6755 /** 6756 * ufshcd_check_errors - Check for errors that need s/w attention 6757 * @hba: per-adapter instance 6758 * @intr_status: interrupt status generated by the controller 6759 * 6760 * Return: 6761 * IRQ_HANDLED - If interrupt is valid 6762 * IRQ_NONE - If invalid interrupt 6763 */ 6764 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6765 { 6766 bool queue_eh_work = false; 6767 irqreturn_t retval = IRQ_NONE; 6768 6769 spin_lock(hba->host->host_lock); 6770 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6771 6772 if (hba->errors & INT_FATAL_ERRORS) { 6773 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6774 hba->errors); 6775 queue_eh_work = true; 6776 } 6777 6778 if (hba->errors & UIC_ERROR) { 6779 hba->uic_error = 0; 6780 retval = ufshcd_update_uic_error(hba); 6781 if (hba->uic_error) 6782 queue_eh_work = true; 6783 } 6784 6785 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6786 dev_err(hba->dev, 6787 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6788 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6789 "Enter" : "Exit", 6790 hba->errors, ufshcd_get_upmcrs(hba)); 6791 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6792 hba->errors); 6793 ufshcd_set_link_broken(hba); 6794 queue_eh_work = true; 6795 } 6796 6797 if (queue_eh_work) { 6798 /* 6799 * update the transfer error masks to sticky bits, let's do this 6800 * irrespective of current ufshcd_state. 6801 */ 6802 hba->saved_err |= hba->errors; 6803 hba->saved_uic_err |= hba->uic_error; 6804 6805 /* dump controller state before resetting */ 6806 if ((hba->saved_err & 6807 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6808 (hba->saved_uic_err && 6809 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6810 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6811 __func__, hba->saved_err, 6812 hba->saved_uic_err); 6813 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6814 "host_regs: "); 6815 ufshcd_print_pwr_info(hba); 6816 } 6817 ufshcd_schedule_eh_work(hba); 6818 retval |= IRQ_HANDLED; 6819 } 6820 /* 6821 * if (!queue_eh_work) - 6822 * Other errors are either non-fatal where host recovers 6823 * itself without s/w intervention or errors that will be 6824 * handled by the SCSI core layer. 6825 */ 6826 hba->errors = 0; 6827 hba->uic_error = 0; 6828 spin_unlock(hba->host->host_lock); 6829 return retval; 6830 } 6831 6832 /** 6833 * ufshcd_tmc_handler - handle task management function completion 6834 * @hba: per adapter instance 6835 * 6836 * Return: 6837 * IRQ_HANDLED - If interrupt is valid 6838 * IRQ_NONE - If invalid interrupt 6839 */ 6840 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6841 { 6842 unsigned long flags, pending, issued; 6843 irqreturn_t ret = IRQ_NONE; 6844 int tag; 6845 6846 spin_lock_irqsave(hba->host->host_lock, flags); 6847 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6848 issued = hba->outstanding_tasks & ~pending; 6849 for_each_set_bit(tag, &issued, hba->nutmrs) { 6850 struct request *req = hba->tmf_rqs[tag]; 6851 struct completion *c = req->end_io_data; 6852 6853 complete(c); 6854 ret = IRQ_HANDLED; 6855 } 6856 spin_unlock_irqrestore(hba->host->host_lock, flags); 6857 6858 return ret; 6859 } 6860 6861 /** 6862 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6863 * @hba: per adapter instance 6864 * 6865 * Return: IRQ_HANDLED if interrupt is handled. 6866 */ 6867 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6868 { 6869 struct ufs_hw_queue *hwq; 6870 unsigned long outstanding_cqs; 6871 unsigned int nr_queues; 6872 int i, ret; 6873 u32 events; 6874 6875 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6876 if (ret) 6877 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6878 6879 /* Exclude the poll queues */ 6880 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6881 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6882 hwq = &hba->uhq[i]; 6883 6884 events = ufshcd_mcq_read_cqis(hba, i); 6885 if (events) 6886 ufshcd_mcq_write_cqis(hba, events, i); 6887 6888 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6889 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6890 } 6891 6892 return IRQ_HANDLED; 6893 } 6894 6895 /** 6896 * ufshcd_sl_intr - Interrupt service routine 6897 * @hba: per adapter instance 6898 * @intr_status: contains interrupts generated by the controller 6899 * 6900 * Return: 6901 * IRQ_HANDLED - If interrupt is valid 6902 * IRQ_NONE - If invalid interrupt 6903 */ 6904 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6905 { 6906 irqreturn_t retval = IRQ_NONE; 6907 6908 if (intr_status & UFSHCD_UIC_MASK) 6909 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6910 6911 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6912 retval |= ufshcd_check_errors(hba, intr_status); 6913 6914 if (intr_status & UTP_TASK_REQ_COMPL) 6915 retval |= ufshcd_tmc_handler(hba); 6916 6917 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6918 retval |= ufshcd_transfer_req_compl(hba); 6919 6920 if (intr_status & MCQ_CQ_EVENT_STATUS) 6921 retval |= ufshcd_handle_mcq_cq_events(hba); 6922 6923 return retval; 6924 } 6925 6926 /** 6927 * ufshcd_intr - Main interrupt service routine 6928 * @irq: irq number 6929 * @__hba: pointer to adapter instance 6930 * 6931 * Return: 6932 * IRQ_HANDLED - If interrupt is valid 6933 * IRQ_NONE - If invalid interrupt 6934 */ 6935 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6936 { 6937 u32 intr_status, enabled_intr_status = 0; 6938 irqreturn_t retval = IRQ_NONE; 6939 struct ufs_hba *hba = __hba; 6940 int retries = hba->nutrs; 6941 6942 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6943 hba->ufs_stats.last_intr_status = intr_status; 6944 hba->ufs_stats.last_intr_ts = local_clock(); 6945 6946 /* 6947 * There could be max of hba->nutrs reqs in flight and in worst case 6948 * if the reqs get finished 1 by 1 after the interrupt status is 6949 * read, make sure we handle them by checking the interrupt status 6950 * again in a loop until we process all of the reqs before returning. 6951 */ 6952 while (intr_status && retries--) { 6953 enabled_intr_status = 6954 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6955 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6956 if (enabled_intr_status) 6957 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 6958 6959 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6960 } 6961 6962 if (enabled_intr_status && retval == IRQ_NONE && 6963 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 6964 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 6965 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 6966 __func__, 6967 intr_status, 6968 hba->ufs_stats.last_intr_status, 6969 enabled_intr_status); 6970 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 6971 } 6972 6973 return retval; 6974 } 6975 6976 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 6977 { 6978 int err = 0; 6979 u32 mask = 1 << tag; 6980 unsigned long flags; 6981 6982 if (!test_bit(tag, &hba->outstanding_tasks)) 6983 goto out; 6984 6985 spin_lock_irqsave(hba->host->host_lock, flags); 6986 ufshcd_utmrl_clear(hba, tag); 6987 spin_unlock_irqrestore(hba->host->host_lock, flags); 6988 6989 /* poll for max. 1 sec to clear door bell register by h/w */ 6990 err = ufshcd_wait_for_register(hba, 6991 REG_UTP_TASK_REQ_DOOR_BELL, 6992 mask, 0, 1000, 1000); 6993 6994 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 6995 tag, err < 0 ? "failed" : "succeeded"); 6996 6997 out: 6998 return err; 6999 } 7000 7001 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 7002 struct utp_task_req_desc *treq, u8 tm_function) 7003 { 7004 struct request_queue *q = hba->tmf_queue; 7005 struct Scsi_Host *host = hba->host; 7006 DECLARE_COMPLETION_ONSTACK(wait); 7007 struct request *req; 7008 unsigned long flags; 7009 int task_tag, err; 7010 7011 /* 7012 * blk_mq_alloc_request() is used here only to get a free tag. 7013 */ 7014 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 7015 if (IS_ERR(req)) 7016 return PTR_ERR(req); 7017 7018 req->end_io_data = &wait; 7019 ufshcd_hold(hba); 7020 7021 spin_lock_irqsave(host->host_lock, flags); 7022 7023 task_tag = req->tag; 7024 hba->tmf_rqs[req->tag] = req; 7025 treq->upiu_req.req_header.task_tag = task_tag; 7026 7027 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 7028 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 7029 7030 /* send command to the controller */ 7031 __set_bit(task_tag, &hba->outstanding_tasks); 7032 7033 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 7034 /* Make sure that doorbell is committed immediately */ 7035 wmb(); 7036 7037 spin_unlock_irqrestore(host->host_lock, flags); 7038 7039 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 7040 7041 /* wait until the task management command is completed */ 7042 err = wait_for_completion_io_timeout(&wait, 7043 msecs_to_jiffies(TM_CMD_TIMEOUT)); 7044 if (!err) { 7045 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 7046 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 7047 __func__, tm_function); 7048 if (ufshcd_clear_tm_cmd(hba, task_tag)) 7049 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 7050 __func__, task_tag); 7051 err = -ETIMEDOUT; 7052 } else { 7053 err = 0; 7054 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 7055 7056 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 7057 } 7058 7059 spin_lock_irqsave(hba->host->host_lock, flags); 7060 hba->tmf_rqs[req->tag] = NULL; 7061 __clear_bit(task_tag, &hba->outstanding_tasks); 7062 spin_unlock_irqrestore(hba->host->host_lock, flags); 7063 7064 ufshcd_release(hba); 7065 blk_mq_free_request(req); 7066 7067 return err; 7068 } 7069 7070 /** 7071 * ufshcd_issue_tm_cmd - issues task management commands to controller 7072 * @hba: per adapter instance 7073 * @lun_id: LUN ID to which TM command is sent 7074 * @task_id: task ID to which the TM command is applicable 7075 * @tm_function: task management function opcode 7076 * @tm_response: task management service response return value 7077 * 7078 * Return: non-zero value on error, zero on success. 7079 */ 7080 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7081 u8 tm_function, u8 *tm_response) 7082 { 7083 struct utp_task_req_desc treq = { }; 7084 enum utp_ocs ocs_value; 7085 int err; 7086 7087 /* Configure task request descriptor */ 7088 treq.header.interrupt = 1; 7089 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7090 7091 /* Configure task request UPIU */ 7092 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7093 treq.upiu_req.req_header.lun = lun_id; 7094 treq.upiu_req.req_header.tm_function = tm_function; 7095 7096 /* 7097 * The host shall provide the same value for LUN field in the basic 7098 * header and for Input Parameter. 7099 */ 7100 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7101 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7102 7103 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7104 if (err == -ETIMEDOUT) 7105 return err; 7106 7107 ocs_value = treq.header.ocs & MASK_OCS; 7108 if (ocs_value != OCS_SUCCESS) 7109 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7110 __func__, ocs_value); 7111 else if (tm_response) 7112 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7113 MASK_TM_SERVICE_RESP; 7114 return err; 7115 } 7116 7117 /** 7118 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7119 * @hba: per-adapter instance 7120 * @req_upiu: upiu request 7121 * @rsp_upiu: upiu reply 7122 * @desc_buff: pointer to descriptor buffer, NULL if NA 7123 * @buff_len: descriptor size, 0 if NA 7124 * @cmd_type: specifies the type (NOP, Query...) 7125 * @desc_op: descriptor operation 7126 * 7127 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7128 * Therefore, it "rides" the device management infrastructure: uses its tag and 7129 * tasks work queues. 7130 * 7131 * Since there is only one available tag for device management commands, 7132 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7133 * 7134 * Return: 0 upon success; < 0 upon failure. 7135 */ 7136 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7137 struct utp_upiu_req *req_upiu, 7138 struct utp_upiu_req *rsp_upiu, 7139 u8 *desc_buff, int *buff_len, 7140 enum dev_cmd_type cmd_type, 7141 enum query_opcode desc_op) 7142 { 7143 DECLARE_COMPLETION_ONSTACK(wait); 7144 const u32 tag = hba->reserved_slot; 7145 struct ufshcd_lrb *lrbp; 7146 int err = 0; 7147 u8 upiu_flags; 7148 7149 /* Protects use of hba->reserved_slot. */ 7150 lockdep_assert_held(&hba->dev_cmd.lock); 7151 7152 down_read(&hba->clk_scaling_lock); 7153 7154 lrbp = &hba->lrb[tag]; 7155 lrbp->cmd = NULL; 7156 lrbp->task_tag = tag; 7157 lrbp->lun = 0; 7158 lrbp->intr_cmd = true; 7159 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 7160 hba->dev_cmd.type = cmd_type; 7161 7162 if (hba->ufs_version <= ufshci_version(1, 1)) 7163 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; 7164 else 7165 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 7166 7167 /* update the task tag in the request upiu */ 7168 req_upiu->header.task_tag = tag; 7169 7170 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0); 7171 7172 /* just copy the upiu request as it is */ 7173 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7174 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7175 /* The Data Segment Area is optional depending upon the query 7176 * function value. for WRITE DESCRIPTOR, the data segment 7177 * follows right after the tsf. 7178 */ 7179 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7180 *buff_len = 0; 7181 } 7182 7183 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7184 7185 hba->dev_cmd.complete = &wait; 7186 7187 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 7188 7189 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 7190 /* 7191 * ignore the returning value here - ufshcd_check_query_response is 7192 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7193 * read the response directly ignoring all errors. 7194 */ 7195 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT); 7196 7197 /* just copy the upiu response as it is */ 7198 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7199 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7200 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7201 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7202 .data_segment_length); 7203 7204 if (*buff_len >= resp_len) { 7205 memcpy(desc_buff, descp, resp_len); 7206 *buff_len = resp_len; 7207 } else { 7208 dev_warn(hba->dev, 7209 "%s: rsp size %d is bigger than buffer size %d", 7210 __func__, resp_len, *buff_len); 7211 *buff_len = 0; 7212 err = -EINVAL; 7213 } 7214 } 7215 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7216 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7217 7218 up_read(&hba->clk_scaling_lock); 7219 return err; 7220 } 7221 7222 /** 7223 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7224 * @hba: per-adapter instance 7225 * @req_upiu: upiu request 7226 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7227 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7228 * @desc_buff: pointer to descriptor buffer, NULL if NA 7229 * @buff_len: descriptor size, 0 if NA 7230 * @desc_op: descriptor operation 7231 * 7232 * Supports UTP Transfer requests (nop and query), and UTP Task 7233 * Management requests. 7234 * It is up to the caller to fill the upiu conent properly, as it will 7235 * be copied without any further input validations. 7236 * 7237 * Return: 0 upon success; < 0 upon failure. 7238 */ 7239 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7240 struct utp_upiu_req *req_upiu, 7241 struct utp_upiu_req *rsp_upiu, 7242 enum upiu_request_transaction msgcode, 7243 u8 *desc_buff, int *buff_len, 7244 enum query_opcode desc_op) 7245 { 7246 int err; 7247 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7248 struct utp_task_req_desc treq = { }; 7249 enum utp_ocs ocs_value; 7250 u8 tm_f = req_upiu->header.tm_function; 7251 7252 switch (msgcode) { 7253 case UPIU_TRANSACTION_NOP_OUT: 7254 cmd_type = DEV_CMD_TYPE_NOP; 7255 fallthrough; 7256 case UPIU_TRANSACTION_QUERY_REQ: 7257 ufshcd_hold(hba); 7258 mutex_lock(&hba->dev_cmd.lock); 7259 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7260 desc_buff, buff_len, 7261 cmd_type, desc_op); 7262 mutex_unlock(&hba->dev_cmd.lock); 7263 ufshcd_release(hba); 7264 7265 break; 7266 case UPIU_TRANSACTION_TASK_REQ: 7267 treq.header.interrupt = 1; 7268 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7269 7270 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7271 7272 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7273 if (err == -ETIMEDOUT) 7274 break; 7275 7276 ocs_value = treq.header.ocs & MASK_OCS; 7277 if (ocs_value != OCS_SUCCESS) { 7278 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7279 ocs_value); 7280 break; 7281 } 7282 7283 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7284 7285 break; 7286 default: 7287 err = -EINVAL; 7288 7289 break; 7290 } 7291 7292 return err; 7293 } 7294 7295 /** 7296 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7297 * @hba: per adapter instance 7298 * @req_upiu: upiu request 7299 * @rsp_upiu: upiu reply 7300 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7301 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7302 * @sg_cnt: The number of sg lists actually used 7303 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7304 * @dir: DMA direction 7305 * 7306 * Return: zero on success, non-zero on failure. 7307 */ 7308 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7309 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7310 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7311 enum dma_data_direction dir) 7312 { 7313 DECLARE_COMPLETION_ONSTACK(wait); 7314 const u32 tag = hba->reserved_slot; 7315 struct ufshcd_lrb *lrbp; 7316 int err = 0; 7317 int result; 7318 u8 upiu_flags; 7319 u8 *ehs_data; 7320 u16 ehs_len; 7321 7322 /* Protects use of hba->reserved_slot. */ 7323 ufshcd_hold(hba); 7324 mutex_lock(&hba->dev_cmd.lock); 7325 down_read(&hba->clk_scaling_lock); 7326 7327 lrbp = &hba->lrb[tag]; 7328 lrbp->cmd = NULL; 7329 lrbp->task_tag = tag; 7330 lrbp->lun = UFS_UPIU_RPMB_WLUN; 7331 7332 lrbp->intr_cmd = true; 7333 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 7334 hba->dev_cmd.type = DEV_CMD_TYPE_RPMB; 7335 7336 /* Advanced RPMB starts from UFS 4.0, so its command type is UTP_CMD_TYPE_UFS_STORAGE */ 7337 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 7338 7339 /* 7340 * According to UFSHCI 4.0 specification page 24, if EHSLUTRDS is 0, host controller takes 7341 * EHS length from CMD UPIU, and SW driver use EHS Length field in CMD UPIU. if it is 1, 7342 * HW controller takes EHS length from UTRD. 7343 */ 7344 if (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) 7345 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 2); 7346 else 7347 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 0); 7348 7349 /* update the task tag */ 7350 req_upiu->header.task_tag = tag; 7351 7352 /* copy the UPIU(contains CDB) request as it is */ 7353 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7354 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7355 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7356 7357 if (dir != DMA_NONE && sg_list) 7358 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7359 7360 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7361 7362 hba->dev_cmd.complete = &wait; 7363 7364 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 7365 7366 err = ufshcd_wait_for_dev_cmd(hba, lrbp, ADVANCED_RPMB_REQ_TIMEOUT); 7367 7368 if (!err) { 7369 /* Just copy the upiu response as it is */ 7370 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7371 /* Get the response UPIU result */ 7372 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7373 lrbp->ucd_rsp_ptr->header.status; 7374 7375 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7376 /* 7377 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7378 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7379 * Message is 02h 7380 */ 7381 if (ehs_len == 2 && rsp_ehs) { 7382 /* 7383 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7384 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7385 */ 7386 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7387 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7388 } 7389 } 7390 7391 up_read(&hba->clk_scaling_lock); 7392 mutex_unlock(&hba->dev_cmd.lock); 7393 ufshcd_release(hba); 7394 return err ? : result; 7395 } 7396 7397 /** 7398 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7399 * @cmd: SCSI command pointer 7400 * 7401 * Return: SUCCESS or FAILED. 7402 */ 7403 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7404 { 7405 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7406 struct Scsi_Host *host; 7407 struct ufs_hba *hba; 7408 struct ufs_hw_queue *hwq; 7409 struct ufshcd_lrb *lrbp; 7410 u32 pos, not_cleared_mask = 0; 7411 int err; 7412 u8 resp = 0xF, lun; 7413 7414 host = cmd->device->host; 7415 hba = shost_priv(host); 7416 7417 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7418 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7419 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7420 if (!err) 7421 err = resp; 7422 goto out; 7423 } 7424 7425 if (is_mcq_enabled(hba)) { 7426 for (pos = 0; pos < hba->nutrs; pos++) { 7427 lrbp = &hba->lrb[pos]; 7428 if (ufshcd_cmd_inflight(lrbp->cmd) && 7429 lrbp->lun == lun) { 7430 ufshcd_clear_cmd(hba, pos); 7431 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7432 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7433 } 7434 } 7435 err = 0; 7436 goto out; 7437 } 7438 7439 /* clear the commands that were pending for corresponding LUN */ 7440 spin_lock_irqsave(&hba->outstanding_lock, flags); 7441 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7442 if (hba->lrb[pos].lun == lun) 7443 __set_bit(pos, &pending_reqs); 7444 hba->outstanding_reqs &= ~pending_reqs; 7445 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7446 7447 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7448 if (ufshcd_clear_cmd(hba, pos) < 0) { 7449 spin_lock_irqsave(&hba->outstanding_lock, flags); 7450 not_cleared = 1U << pos & 7451 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7452 hba->outstanding_reqs |= not_cleared; 7453 not_cleared_mask |= not_cleared; 7454 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7455 7456 dev_err(hba->dev, "%s: failed to clear request %d\n", 7457 __func__, pos); 7458 } 7459 } 7460 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7461 7462 out: 7463 hba->req_abort_count = 0; 7464 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7465 if (!err) { 7466 err = SUCCESS; 7467 } else { 7468 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7469 err = FAILED; 7470 } 7471 return err; 7472 } 7473 7474 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7475 { 7476 struct ufshcd_lrb *lrbp; 7477 int tag; 7478 7479 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7480 lrbp = &hba->lrb[tag]; 7481 lrbp->req_abort_skip = true; 7482 } 7483 } 7484 7485 /** 7486 * ufshcd_try_to_abort_task - abort a specific task 7487 * @hba: Pointer to adapter instance 7488 * @tag: Task tag/index to be aborted 7489 * 7490 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7491 * command, and in host controller by clearing the door-bell register. There can 7492 * be race between controller sending the command to the device while abort is 7493 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7494 * really issued and then try to abort it. 7495 * 7496 * Return: zero on success, non-zero on failure. 7497 */ 7498 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7499 { 7500 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7501 int err = 0; 7502 int poll_cnt; 7503 u8 resp = 0xF; 7504 u32 reg; 7505 7506 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7507 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7508 UFS_QUERY_TASK, &resp); 7509 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7510 /* cmd pending in the device */ 7511 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7512 __func__, tag); 7513 break; 7514 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7515 /* 7516 * cmd not pending in the device, check if it is 7517 * in transition. 7518 */ 7519 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n", 7520 __func__, tag); 7521 if (is_mcq_enabled(hba)) { 7522 /* MCQ mode */ 7523 if (ufshcd_cmd_inflight(lrbp->cmd)) { 7524 /* sleep for max. 200us same delay as in SDB mode */ 7525 usleep_range(100, 200); 7526 continue; 7527 } 7528 /* command completed already */ 7529 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n", 7530 __func__, tag); 7531 goto out; 7532 } 7533 7534 /* Single Doorbell Mode */ 7535 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7536 if (reg & (1 << tag)) { 7537 /* sleep for max. 200us to stabilize */ 7538 usleep_range(100, 200); 7539 continue; 7540 } 7541 /* command completed already */ 7542 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n", 7543 __func__, tag); 7544 goto out; 7545 } else { 7546 dev_err(hba->dev, 7547 "%s: no response from device. tag = %d, err %d\n", 7548 __func__, tag, err); 7549 if (!err) 7550 err = resp; /* service response error */ 7551 goto out; 7552 } 7553 } 7554 7555 if (!poll_cnt) { 7556 err = -EBUSY; 7557 goto out; 7558 } 7559 7560 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7561 UFS_ABORT_TASK, &resp); 7562 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7563 if (!err) { 7564 err = resp; /* service response error */ 7565 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7566 __func__, tag, err); 7567 } 7568 goto out; 7569 } 7570 7571 err = ufshcd_clear_cmd(hba, tag); 7572 if (err) 7573 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7574 __func__, tag, err); 7575 7576 out: 7577 return err; 7578 } 7579 7580 /** 7581 * ufshcd_abort - scsi host template eh_abort_handler callback 7582 * @cmd: SCSI command pointer 7583 * 7584 * Return: SUCCESS or FAILED. 7585 */ 7586 static int ufshcd_abort(struct scsi_cmnd *cmd) 7587 { 7588 struct Scsi_Host *host = cmd->device->host; 7589 struct ufs_hba *hba = shost_priv(host); 7590 int tag = scsi_cmd_to_rq(cmd)->tag; 7591 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7592 unsigned long flags; 7593 int err = FAILED; 7594 bool outstanding; 7595 u32 reg; 7596 7597 ufshcd_hold(hba); 7598 7599 if (!is_mcq_enabled(hba)) { 7600 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7601 if (!test_bit(tag, &hba->outstanding_reqs)) { 7602 /* If command is already aborted/completed, return FAILED. */ 7603 dev_err(hba->dev, 7604 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7605 __func__, tag, hba->outstanding_reqs, reg); 7606 goto release; 7607 } 7608 } 7609 7610 /* Print Transfer Request of aborted task */ 7611 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7612 7613 /* 7614 * Print detailed info about aborted request. 7615 * As more than one request might get aborted at the same time, 7616 * print full information only for the first aborted request in order 7617 * to reduce repeated printouts. For other aborted requests only print 7618 * basic details. 7619 */ 7620 scsi_print_command(cmd); 7621 if (!hba->req_abort_count) { 7622 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7623 ufshcd_print_evt_hist(hba); 7624 ufshcd_print_host_state(hba); 7625 ufshcd_print_pwr_info(hba); 7626 ufshcd_print_tr(hba, tag, true); 7627 } else { 7628 ufshcd_print_tr(hba, tag, false); 7629 } 7630 hba->req_abort_count++; 7631 7632 if (!is_mcq_enabled(hba) && !(reg & (1 << tag))) { 7633 /* only execute this code in single doorbell mode */ 7634 dev_err(hba->dev, 7635 "%s: cmd was completed, but without a notifying intr, tag = %d", 7636 __func__, tag); 7637 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7638 goto release; 7639 } 7640 7641 /* 7642 * Task abort to the device W-LUN is illegal. When this command 7643 * will fail, due to spec violation, scsi err handling next step 7644 * will be to send LU reset which, again, is a spec violation. 7645 * To avoid these unnecessary/illegal steps, first we clean up 7646 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7647 * then queue the eh_work and bail. 7648 */ 7649 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7650 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7651 7652 spin_lock_irqsave(host->host_lock, flags); 7653 hba->force_reset = true; 7654 ufshcd_schedule_eh_work(hba); 7655 spin_unlock_irqrestore(host->host_lock, flags); 7656 goto release; 7657 } 7658 7659 if (is_mcq_enabled(hba)) { 7660 /* MCQ mode. Branch off to handle abort for mcq mode */ 7661 err = ufshcd_mcq_abort(cmd); 7662 goto release; 7663 } 7664 7665 /* Skip task abort in case previous aborts failed and report failure */ 7666 if (lrbp->req_abort_skip) { 7667 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7668 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7669 goto release; 7670 } 7671 7672 err = ufshcd_try_to_abort_task(hba, tag); 7673 if (err) { 7674 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7675 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7676 err = FAILED; 7677 goto release; 7678 } 7679 7680 /* 7681 * Clear the corresponding bit from outstanding_reqs since the command 7682 * has been aborted successfully. 7683 */ 7684 spin_lock_irqsave(&hba->outstanding_lock, flags); 7685 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7686 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7687 7688 if (outstanding) 7689 ufshcd_release_scsi_cmd(hba, lrbp); 7690 7691 err = SUCCESS; 7692 7693 release: 7694 /* Matches the ufshcd_hold() call at the start of this function. */ 7695 ufshcd_release(hba); 7696 return err; 7697 } 7698 7699 /** 7700 * ufshcd_host_reset_and_restore - reset and restore host controller 7701 * @hba: per-adapter instance 7702 * 7703 * Note that host controller reset may issue DME_RESET to 7704 * local and remote (device) Uni-Pro stack and the attributes 7705 * are reset to default state. 7706 * 7707 * Return: zero on success, non-zero on failure. 7708 */ 7709 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7710 { 7711 int err; 7712 7713 /* 7714 * Stop the host controller and complete the requests 7715 * cleared by h/w 7716 */ 7717 ufshcd_hba_stop(hba); 7718 hba->silence_err_logs = true; 7719 ufshcd_complete_requests(hba, true); 7720 hba->silence_err_logs = false; 7721 7722 /* scale up clocks to max frequency before full reinitialization */ 7723 ufshcd_scale_clks(hba, ULONG_MAX, true); 7724 7725 err = ufshcd_hba_enable(hba); 7726 7727 /* Establish the link again and restore the device */ 7728 if (!err) 7729 err = ufshcd_probe_hba(hba, false); 7730 7731 if (err) 7732 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7733 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7734 return err; 7735 } 7736 7737 /** 7738 * ufshcd_reset_and_restore - reset and re-initialize host/device 7739 * @hba: per-adapter instance 7740 * 7741 * Reset and recover device, host and re-establish link. This 7742 * is helpful to recover the communication in fatal error conditions. 7743 * 7744 * Return: zero on success, non-zero on failure. 7745 */ 7746 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7747 { 7748 u32 saved_err = 0; 7749 u32 saved_uic_err = 0; 7750 int err = 0; 7751 unsigned long flags; 7752 int retries = MAX_HOST_RESET_RETRIES; 7753 7754 spin_lock_irqsave(hba->host->host_lock, flags); 7755 do { 7756 /* 7757 * This is a fresh start, cache and clear saved error first, 7758 * in case new error generated during reset and restore. 7759 */ 7760 saved_err |= hba->saved_err; 7761 saved_uic_err |= hba->saved_uic_err; 7762 hba->saved_err = 0; 7763 hba->saved_uic_err = 0; 7764 hba->force_reset = false; 7765 hba->ufshcd_state = UFSHCD_STATE_RESET; 7766 spin_unlock_irqrestore(hba->host->host_lock, flags); 7767 7768 /* Reset the attached device */ 7769 ufshcd_device_reset(hba); 7770 7771 err = ufshcd_host_reset_and_restore(hba); 7772 7773 spin_lock_irqsave(hba->host->host_lock, flags); 7774 if (err) 7775 continue; 7776 /* Do not exit unless operational or dead */ 7777 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7778 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7779 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7780 err = -EAGAIN; 7781 } while (err && --retries); 7782 7783 /* 7784 * Inform scsi mid-layer that we did reset and allow to handle 7785 * Unit Attention properly. 7786 */ 7787 scsi_report_bus_reset(hba->host, 0); 7788 if (err) { 7789 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7790 hba->saved_err |= saved_err; 7791 hba->saved_uic_err |= saved_uic_err; 7792 } 7793 spin_unlock_irqrestore(hba->host->host_lock, flags); 7794 7795 return err; 7796 } 7797 7798 /** 7799 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7800 * @cmd: SCSI command pointer 7801 * 7802 * Return: SUCCESS or FAILED. 7803 */ 7804 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7805 { 7806 int err = SUCCESS; 7807 unsigned long flags; 7808 struct ufs_hba *hba; 7809 7810 hba = shost_priv(cmd->device->host); 7811 7812 /* 7813 * If runtime PM sent SSU and got a timeout, scsi_error_handler is 7814 * stuck in this function waiting for flush_work(&hba->eh_work). And 7815 * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do 7816 * ufshcd_link_recovery instead of eh_work to prevent deadlock. 7817 */ 7818 if (hba->pm_op_in_progress) { 7819 if (ufshcd_link_recovery(hba)) 7820 err = FAILED; 7821 7822 return err; 7823 } 7824 7825 spin_lock_irqsave(hba->host->host_lock, flags); 7826 hba->force_reset = true; 7827 ufshcd_schedule_eh_work(hba); 7828 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7829 spin_unlock_irqrestore(hba->host->host_lock, flags); 7830 7831 flush_work(&hba->eh_work); 7832 7833 spin_lock_irqsave(hba->host->host_lock, flags); 7834 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7835 err = FAILED; 7836 spin_unlock_irqrestore(hba->host->host_lock, flags); 7837 7838 return err; 7839 } 7840 7841 /** 7842 * ufshcd_get_max_icc_level - calculate the ICC level 7843 * @sup_curr_uA: max. current supported by the regulator 7844 * @start_scan: row at the desc table to start scan from 7845 * @buff: power descriptor buffer 7846 * 7847 * Return: calculated max ICC level for specific regulator. 7848 */ 7849 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7850 const char *buff) 7851 { 7852 int i; 7853 int curr_uA; 7854 u16 data; 7855 u16 unit; 7856 7857 for (i = start_scan; i >= 0; i--) { 7858 data = get_unaligned_be16(&buff[2 * i]); 7859 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7860 ATTR_ICC_LVL_UNIT_OFFSET; 7861 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7862 switch (unit) { 7863 case UFSHCD_NANO_AMP: 7864 curr_uA = curr_uA / 1000; 7865 break; 7866 case UFSHCD_MILI_AMP: 7867 curr_uA = curr_uA * 1000; 7868 break; 7869 case UFSHCD_AMP: 7870 curr_uA = curr_uA * 1000 * 1000; 7871 break; 7872 case UFSHCD_MICRO_AMP: 7873 default: 7874 break; 7875 } 7876 if (sup_curr_uA >= curr_uA) 7877 break; 7878 } 7879 if (i < 0) { 7880 i = 0; 7881 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7882 } 7883 7884 return (u32)i; 7885 } 7886 7887 /** 7888 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7889 * In case regulators are not initialized we'll return 0 7890 * @hba: per-adapter instance 7891 * @desc_buf: power descriptor buffer to extract ICC levels from. 7892 * 7893 * Return: calculated ICC level. 7894 */ 7895 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7896 const u8 *desc_buf) 7897 { 7898 u32 icc_level = 0; 7899 7900 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7901 !hba->vreg_info.vccq2) { 7902 /* 7903 * Using dev_dbg to avoid messages during runtime PM to avoid 7904 * never-ending cycles of messages written back to storage by 7905 * user space causing runtime resume, causing more messages and 7906 * so on. 7907 */ 7908 dev_dbg(hba->dev, 7909 "%s: Regulator capability was not set, actvIccLevel=%d", 7910 __func__, icc_level); 7911 goto out; 7912 } 7913 7914 if (hba->vreg_info.vcc->max_uA) 7915 icc_level = ufshcd_get_max_icc_level( 7916 hba->vreg_info.vcc->max_uA, 7917 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7918 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7919 7920 if (hba->vreg_info.vccq->max_uA) 7921 icc_level = ufshcd_get_max_icc_level( 7922 hba->vreg_info.vccq->max_uA, 7923 icc_level, 7924 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7925 7926 if (hba->vreg_info.vccq2->max_uA) 7927 icc_level = ufshcd_get_max_icc_level( 7928 hba->vreg_info.vccq2->max_uA, 7929 icc_level, 7930 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7931 out: 7932 return icc_level; 7933 } 7934 7935 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7936 { 7937 int ret; 7938 u8 *desc_buf; 7939 u32 icc_level; 7940 7941 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7942 if (!desc_buf) 7943 return; 7944 7945 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7946 desc_buf, QUERY_DESC_MAX_SIZE); 7947 if (ret) { 7948 dev_err(hba->dev, 7949 "%s: Failed reading power descriptor ret = %d", 7950 __func__, ret); 7951 goto out; 7952 } 7953 7954 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7955 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7956 7957 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7958 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7959 7960 if (ret) 7961 dev_err(hba->dev, 7962 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7963 __func__, icc_level, ret); 7964 7965 out: 7966 kfree(desc_buf); 7967 } 7968 7969 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7970 { 7971 scsi_autopm_get_device(sdev); 7972 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7973 if (sdev->rpm_autosuspend) 7974 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7975 RPM_AUTOSUSPEND_DELAY_MS); 7976 scsi_autopm_put_device(sdev); 7977 } 7978 7979 /** 7980 * ufshcd_scsi_add_wlus - Adds required W-LUs 7981 * @hba: per-adapter instance 7982 * 7983 * UFS device specification requires the UFS devices to support 4 well known 7984 * logical units: 7985 * "REPORT_LUNS" (address: 01h) 7986 * "UFS Device" (address: 50h) 7987 * "RPMB" (address: 44h) 7988 * "BOOT" (address: 30h) 7989 * UFS device's power management needs to be controlled by "POWER CONDITION" 7990 * field of SSU (START STOP UNIT) command. But this "power condition" field 7991 * will take effect only when its sent to "UFS device" well known logical unit 7992 * hence we require the scsi_device instance to represent this logical unit in 7993 * order for the UFS host driver to send the SSU command for power management. 7994 * 7995 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 7996 * Block) LU so user space process can control this LU. User space may also 7997 * want to have access to BOOT LU. 7998 * 7999 * This function adds scsi device instances for each of all well known LUs 8000 * (except "REPORT LUNS" LU). 8001 * 8002 * Return: zero on success (all required W-LUs are added successfully), 8003 * non-zero error value on failure (if failed to add any of the required W-LU). 8004 */ 8005 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 8006 { 8007 int ret = 0; 8008 struct scsi_device *sdev_boot, *sdev_rpmb; 8009 8010 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 8011 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 8012 if (IS_ERR(hba->ufs_device_wlun)) { 8013 ret = PTR_ERR(hba->ufs_device_wlun); 8014 hba->ufs_device_wlun = NULL; 8015 goto out; 8016 } 8017 scsi_device_put(hba->ufs_device_wlun); 8018 8019 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 8020 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 8021 if (IS_ERR(sdev_rpmb)) { 8022 ret = PTR_ERR(sdev_rpmb); 8023 goto remove_ufs_device_wlun; 8024 } 8025 ufshcd_blk_pm_runtime_init(sdev_rpmb); 8026 scsi_device_put(sdev_rpmb); 8027 8028 sdev_boot = __scsi_add_device(hba->host, 0, 0, 8029 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 8030 if (IS_ERR(sdev_boot)) { 8031 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 8032 } else { 8033 ufshcd_blk_pm_runtime_init(sdev_boot); 8034 scsi_device_put(sdev_boot); 8035 } 8036 goto out; 8037 8038 remove_ufs_device_wlun: 8039 scsi_remove_device(hba->ufs_device_wlun); 8040 out: 8041 return ret; 8042 } 8043 8044 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 8045 { 8046 struct ufs_dev_info *dev_info = &hba->dev_info; 8047 u8 lun; 8048 u32 d_lu_wb_buf_alloc; 8049 u32 ext_ufs_feature; 8050 8051 if (!ufshcd_is_wb_allowed(hba)) 8052 return; 8053 8054 /* 8055 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 8056 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 8057 * enabled 8058 */ 8059 if (!(dev_info->wspecversion >= 0x310 || 8060 dev_info->wspecversion == 0x220 || 8061 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 8062 goto wb_disabled; 8063 8064 ext_ufs_feature = get_unaligned_be32(desc_buf + 8065 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8066 8067 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 8068 goto wb_disabled; 8069 8070 /* 8071 * WB may be supported but not configured while provisioning. The spec 8072 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 8073 * buffer configured. 8074 */ 8075 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 8076 8077 dev_info->b_presrv_uspc_en = 8078 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 8079 8080 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 8081 if (!get_unaligned_be32(desc_buf + 8082 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 8083 goto wb_disabled; 8084 } else { 8085 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 8086 d_lu_wb_buf_alloc = 0; 8087 ufshcd_read_unit_desc_param(hba, 8088 lun, 8089 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 8090 (u8 *)&d_lu_wb_buf_alloc, 8091 sizeof(d_lu_wb_buf_alloc)); 8092 if (d_lu_wb_buf_alloc) { 8093 dev_info->wb_dedicated_lu = lun; 8094 break; 8095 } 8096 } 8097 8098 if (!d_lu_wb_buf_alloc) 8099 goto wb_disabled; 8100 } 8101 8102 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8103 goto wb_disabled; 8104 8105 return; 8106 8107 wb_disabled: 8108 hba->caps &= ~UFSHCD_CAP_WB_EN; 8109 } 8110 8111 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8112 { 8113 struct ufs_dev_info *dev_info = &hba->dev_info; 8114 u32 ext_ufs_feature; 8115 u8 mask = 0; 8116 8117 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8118 return; 8119 8120 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8121 8122 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8123 mask |= MASK_EE_TOO_LOW_TEMP; 8124 8125 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8126 mask |= MASK_EE_TOO_HIGH_TEMP; 8127 8128 if (mask) { 8129 ufshcd_enable_ee(hba, mask); 8130 ufs_hwmon_probe(hba, mask); 8131 } 8132 } 8133 8134 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8135 { 8136 struct ufs_dev_info *dev_info = &hba->dev_info; 8137 u32 ext_ufs_feature; 8138 u32 ext_iid_en = 0; 8139 int err; 8140 8141 /* Only UFS-4.0 and above may support EXT_IID */ 8142 if (dev_info->wspecversion < 0x400) 8143 goto out; 8144 8145 ext_ufs_feature = get_unaligned_be32(desc_buf + 8146 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8147 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8148 goto out; 8149 8150 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8151 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8152 if (err) 8153 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8154 8155 out: 8156 dev_info->b_ext_iid_en = ext_iid_en; 8157 } 8158 8159 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8160 const struct ufs_dev_quirk *fixups) 8161 { 8162 const struct ufs_dev_quirk *f; 8163 struct ufs_dev_info *dev_info = &hba->dev_info; 8164 8165 if (!fixups) 8166 return; 8167 8168 for (f = fixups; f->quirk; f++) { 8169 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8170 f->wmanufacturerid == UFS_ANY_VENDOR) && 8171 ((dev_info->model && 8172 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8173 !strcmp(f->model, UFS_ANY_MODEL))) 8174 hba->dev_quirks |= f->quirk; 8175 } 8176 } 8177 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8178 8179 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8180 { 8181 /* fix by general quirk table */ 8182 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8183 8184 /* allow vendors to fix quirks */ 8185 ufshcd_vops_fixup_dev_quirks(hba); 8186 } 8187 8188 static int ufs_get_device_desc(struct ufs_hba *hba) 8189 { 8190 int err; 8191 u8 model_index; 8192 u8 *desc_buf; 8193 struct ufs_dev_info *dev_info = &hba->dev_info; 8194 8195 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8196 if (!desc_buf) { 8197 err = -ENOMEM; 8198 goto out; 8199 } 8200 8201 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8202 QUERY_DESC_MAX_SIZE); 8203 if (err) { 8204 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8205 __func__, err); 8206 goto out; 8207 } 8208 8209 /* 8210 * getting vendor (manufacturerID) and Bank Index in big endian 8211 * format 8212 */ 8213 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8214 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8215 8216 /* getting Specification Version in big endian format */ 8217 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8218 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8219 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8220 8221 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8222 8223 err = ufshcd_read_string_desc(hba, model_index, 8224 &dev_info->model, SD_ASCII_STD); 8225 if (err < 0) { 8226 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8227 __func__, err); 8228 goto out; 8229 } 8230 8231 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8232 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8233 8234 ufs_fixup_device_setup(hba); 8235 8236 ufshcd_wb_probe(hba, desc_buf); 8237 8238 ufshcd_temp_notif_probe(hba, desc_buf); 8239 8240 if (hba->ext_iid_sup) 8241 ufshcd_ext_iid_probe(hba, desc_buf); 8242 8243 /* 8244 * ufshcd_read_string_desc returns size of the string 8245 * reset the error value 8246 */ 8247 err = 0; 8248 8249 out: 8250 kfree(desc_buf); 8251 return err; 8252 } 8253 8254 static void ufs_put_device_desc(struct ufs_hba *hba) 8255 { 8256 struct ufs_dev_info *dev_info = &hba->dev_info; 8257 8258 kfree(dev_info->model); 8259 dev_info->model = NULL; 8260 } 8261 8262 /** 8263 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro 8264 * @hba: per-adapter instance 8265 * 8266 * PA_TActivate parameter can be tuned manually if UniPro version is less than 8267 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's 8268 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce 8269 * the hibern8 exit latency. 8270 * 8271 * Return: zero on success, non-zero error value on failure. 8272 */ 8273 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba) 8274 { 8275 int ret = 0; 8276 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate; 8277 8278 ret = ufshcd_dme_peer_get(hba, 8279 UIC_ARG_MIB_SEL( 8280 RX_MIN_ACTIVATETIME_CAPABILITY, 8281 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 8282 &peer_rx_min_activatetime); 8283 if (ret) 8284 goto out; 8285 8286 /* make sure proper unit conversion is applied */ 8287 tuned_pa_tactivate = 8288 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US) 8289 / PA_TACTIVATE_TIME_UNIT_US); 8290 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8291 tuned_pa_tactivate); 8292 8293 out: 8294 return ret; 8295 } 8296 8297 /** 8298 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro 8299 * @hba: per-adapter instance 8300 * 8301 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than 8302 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's 8303 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY. 8304 * This optimal value can help reduce the hibern8 exit latency. 8305 * 8306 * Return: zero on success, non-zero error value on failure. 8307 */ 8308 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba) 8309 { 8310 int ret = 0; 8311 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0; 8312 u32 max_hibern8_time, tuned_pa_hibern8time; 8313 8314 ret = ufshcd_dme_get(hba, 8315 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY, 8316 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 8317 &local_tx_hibern8_time_cap); 8318 if (ret) 8319 goto out; 8320 8321 ret = ufshcd_dme_peer_get(hba, 8322 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY, 8323 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 8324 &peer_rx_hibern8_time_cap); 8325 if (ret) 8326 goto out; 8327 8328 max_hibern8_time = max(local_tx_hibern8_time_cap, 8329 peer_rx_hibern8_time_cap); 8330 /* make sure proper unit conversion is applied */ 8331 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US) 8332 / PA_HIBERN8_TIME_UNIT_US); 8333 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 8334 tuned_pa_hibern8time); 8335 out: 8336 return ret; 8337 } 8338 8339 /** 8340 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8341 * less than device PA_TACTIVATE time. 8342 * @hba: per-adapter instance 8343 * 8344 * Some UFS devices require host PA_TACTIVATE to be lower than device 8345 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8346 * for such devices. 8347 * 8348 * Return: zero on success, non-zero error value on failure. 8349 */ 8350 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8351 { 8352 int ret = 0; 8353 u32 granularity, peer_granularity; 8354 u32 pa_tactivate, peer_pa_tactivate; 8355 u32 pa_tactivate_us, peer_pa_tactivate_us; 8356 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8357 8358 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8359 &granularity); 8360 if (ret) 8361 goto out; 8362 8363 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8364 &peer_granularity); 8365 if (ret) 8366 goto out; 8367 8368 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8369 (granularity > PA_GRANULARITY_MAX_VAL)) { 8370 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8371 __func__, granularity); 8372 return -EINVAL; 8373 } 8374 8375 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8376 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8377 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8378 __func__, peer_granularity); 8379 return -EINVAL; 8380 } 8381 8382 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8383 if (ret) 8384 goto out; 8385 8386 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8387 &peer_pa_tactivate); 8388 if (ret) 8389 goto out; 8390 8391 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8392 peer_pa_tactivate_us = peer_pa_tactivate * 8393 gran_to_us_table[peer_granularity - 1]; 8394 8395 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8396 u32 new_peer_pa_tactivate; 8397 8398 new_peer_pa_tactivate = pa_tactivate_us / 8399 gran_to_us_table[peer_granularity - 1]; 8400 new_peer_pa_tactivate++; 8401 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8402 new_peer_pa_tactivate); 8403 } 8404 8405 out: 8406 return ret; 8407 } 8408 8409 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8410 { 8411 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) { 8412 ufshcd_tune_pa_tactivate(hba); 8413 ufshcd_tune_pa_hibern8time(hba); 8414 } 8415 8416 ufshcd_vops_apply_dev_quirks(hba); 8417 8418 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8419 /* set 1ms timeout for PA_TACTIVATE */ 8420 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8421 8422 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8423 ufshcd_quirk_tune_host_pa_tactivate(hba); 8424 } 8425 8426 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8427 { 8428 hba->ufs_stats.hibern8_exit_cnt = 0; 8429 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8430 hba->req_abort_count = 0; 8431 } 8432 8433 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8434 { 8435 int err; 8436 u8 *desc_buf; 8437 8438 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8439 if (!desc_buf) { 8440 err = -ENOMEM; 8441 goto out; 8442 } 8443 8444 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8445 desc_buf, QUERY_DESC_MAX_SIZE); 8446 if (err) { 8447 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8448 __func__, err); 8449 goto out; 8450 } 8451 8452 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8453 hba->dev_info.max_lu_supported = 32; 8454 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8455 hba->dev_info.max_lu_supported = 8; 8456 8457 out: 8458 kfree(desc_buf); 8459 return err; 8460 } 8461 8462 struct ufs_ref_clk { 8463 unsigned long freq_hz; 8464 enum ufs_ref_clk_freq val; 8465 }; 8466 8467 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8468 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8469 {26000000, REF_CLK_FREQ_26_MHZ}, 8470 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8471 {52000000, REF_CLK_FREQ_52_MHZ}, 8472 {0, REF_CLK_FREQ_INVAL}, 8473 }; 8474 8475 static enum ufs_ref_clk_freq 8476 ufs_get_bref_clk_from_hz(unsigned long freq) 8477 { 8478 int i; 8479 8480 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8481 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8482 return ufs_ref_clk_freqs[i].val; 8483 8484 return REF_CLK_FREQ_INVAL; 8485 } 8486 8487 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8488 { 8489 unsigned long freq; 8490 8491 freq = clk_get_rate(refclk); 8492 8493 hba->dev_ref_clk_freq = 8494 ufs_get_bref_clk_from_hz(freq); 8495 8496 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8497 dev_err(hba->dev, 8498 "invalid ref_clk setting = %ld\n", freq); 8499 } 8500 8501 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8502 { 8503 int err; 8504 u32 ref_clk; 8505 u32 freq = hba->dev_ref_clk_freq; 8506 8507 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8508 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8509 8510 if (err) { 8511 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8512 err); 8513 goto out; 8514 } 8515 8516 if (ref_clk == freq) 8517 goto out; /* nothing to update */ 8518 8519 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8520 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8521 8522 if (err) { 8523 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8524 ufs_ref_clk_freqs[freq].freq_hz); 8525 goto out; 8526 } 8527 8528 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8529 ufs_ref_clk_freqs[freq].freq_hz); 8530 8531 out: 8532 return err; 8533 } 8534 8535 static int ufshcd_device_params_init(struct ufs_hba *hba) 8536 { 8537 bool flag; 8538 int ret; 8539 8540 /* Init UFS geometry descriptor related parameters */ 8541 ret = ufshcd_device_geo_params_init(hba); 8542 if (ret) 8543 goto out; 8544 8545 /* Check and apply UFS device quirks */ 8546 ret = ufs_get_device_desc(hba); 8547 if (ret) { 8548 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8549 __func__, ret); 8550 goto out; 8551 } 8552 8553 ufshcd_get_ref_clk_gating_wait(hba); 8554 8555 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8556 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8557 hba->dev_info.f_power_on_wp_en = flag; 8558 8559 /* Probe maximum power mode co-supported by both UFS host and device */ 8560 if (ufshcd_get_max_pwr_mode(hba)) 8561 dev_err(hba->dev, 8562 "%s: Failed getting max supported power mode\n", 8563 __func__); 8564 out: 8565 return ret; 8566 } 8567 8568 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8569 { 8570 int err; 8571 struct ufs_query_req *request = NULL; 8572 struct ufs_query_res *response = NULL; 8573 struct ufs_dev_info *dev_info = &hba->dev_info; 8574 struct utp_upiu_query_v4_0 *upiu_data; 8575 8576 if (dev_info->wspecversion < 0x400) 8577 return; 8578 8579 ufshcd_hold(hba); 8580 8581 mutex_lock(&hba->dev_cmd.lock); 8582 8583 ufshcd_init_query(hba, &request, &response, 8584 UPIU_QUERY_OPCODE_WRITE_ATTR, 8585 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8586 8587 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8588 8589 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8590 8591 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8592 8593 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8594 8595 if (err) 8596 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8597 __func__, err); 8598 8599 mutex_unlock(&hba->dev_cmd.lock); 8600 ufshcd_release(hba); 8601 } 8602 8603 /** 8604 * ufshcd_add_lus - probe and add UFS logical units 8605 * @hba: per-adapter instance 8606 * 8607 * Return: 0 upon success; < 0 upon failure. 8608 */ 8609 static int ufshcd_add_lus(struct ufs_hba *hba) 8610 { 8611 int ret; 8612 8613 /* Add required well known logical units to scsi mid layer */ 8614 ret = ufshcd_scsi_add_wlus(hba); 8615 if (ret) 8616 goto out; 8617 8618 /* Initialize devfreq after UFS device is detected */ 8619 if (ufshcd_is_clkscaling_supported(hba)) { 8620 memcpy(&hba->clk_scaling.saved_pwr_info, 8621 &hba->pwr_info, 8622 sizeof(struct ufs_pa_layer_attr)); 8623 hba->clk_scaling.is_allowed = true; 8624 8625 ret = ufshcd_devfreq_init(hba); 8626 if (ret) 8627 goto out; 8628 8629 hba->clk_scaling.is_enabled = true; 8630 ufshcd_init_clk_scaling_sysfs(hba); 8631 } 8632 8633 ufs_bsg_probe(hba); 8634 scsi_scan_host(hba->host); 8635 pm_runtime_put_sync(hba->dev); 8636 8637 out: 8638 return ret; 8639 } 8640 8641 /* SDB - Single Doorbell */ 8642 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8643 { 8644 size_t ucdl_size, utrdl_size; 8645 8646 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8647 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8648 hba->ucdl_dma_addr); 8649 8650 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8651 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8652 hba->utrdl_dma_addr); 8653 8654 devm_kfree(hba->dev, hba->lrb); 8655 } 8656 8657 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8658 { 8659 int ret; 8660 int old_nutrs = hba->nutrs; 8661 8662 ret = ufshcd_mcq_decide_queue_depth(hba); 8663 if (ret < 0) 8664 return ret; 8665 8666 hba->nutrs = ret; 8667 ret = ufshcd_mcq_init(hba); 8668 if (ret) 8669 goto err; 8670 8671 /* 8672 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8673 * Number of supported tags in MCQ mode may be larger than SDB mode. 8674 */ 8675 if (hba->nutrs != old_nutrs) { 8676 ufshcd_release_sdb_queue(hba, old_nutrs); 8677 ret = ufshcd_memory_alloc(hba); 8678 if (ret) 8679 goto err; 8680 ufshcd_host_memory_configure(hba); 8681 } 8682 8683 ret = ufshcd_mcq_memory_alloc(hba); 8684 if (ret) 8685 goto err; 8686 8687 return 0; 8688 err: 8689 hba->nutrs = old_nutrs; 8690 return ret; 8691 } 8692 8693 static void ufshcd_config_mcq(struct ufs_hba *hba) 8694 { 8695 int ret; 8696 u32 intrs; 8697 8698 ret = ufshcd_mcq_vops_config_esi(hba); 8699 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8700 8701 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8702 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8703 intrs &= ~MCQ_CQ_EVENT_STATUS; 8704 ufshcd_enable_intr(hba, intrs); 8705 ufshcd_mcq_make_queues_operational(hba); 8706 ufshcd_mcq_config_mac(hba, hba->nutrs); 8707 8708 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8709 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8710 8711 /* Select MCQ mode */ 8712 ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1, 8713 REG_UFS_MEM_CFG); 8714 hba->mcq_enabled = true; 8715 8716 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8717 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8718 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8719 hba->nutrs); 8720 } 8721 8722 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8723 { 8724 int ret; 8725 struct Scsi_Host *host = hba->host; 8726 8727 hba->ufshcd_state = UFSHCD_STATE_RESET; 8728 8729 ret = ufshcd_link_startup(hba); 8730 if (ret) 8731 return ret; 8732 8733 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8734 return ret; 8735 8736 /* Debug counters initialization */ 8737 ufshcd_clear_dbg_ufs_stats(hba); 8738 8739 /* UniPro link is active now */ 8740 ufshcd_set_link_active(hba); 8741 8742 /* Reconfigure MCQ upon reset */ 8743 if (is_mcq_enabled(hba) && !init_dev_params) 8744 ufshcd_config_mcq(hba); 8745 8746 /* Verify device initialization by sending NOP OUT UPIU */ 8747 ret = ufshcd_verify_dev_init(hba); 8748 if (ret) 8749 return ret; 8750 8751 /* Initiate UFS initialization, and waiting until completion */ 8752 ret = ufshcd_complete_dev_init(hba); 8753 if (ret) 8754 return ret; 8755 8756 /* 8757 * Initialize UFS device parameters used by driver, these 8758 * parameters are associated with UFS descriptors. 8759 */ 8760 if (init_dev_params) { 8761 ret = ufshcd_device_params_init(hba); 8762 if (ret) 8763 return ret; 8764 if (is_mcq_supported(hba) && !hba->scsi_host_added) { 8765 ret = ufshcd_alloc_mcq(hba); 8766 if (!ret) { 8767 ufshcd_config_mcq(hba); 8768 } else { 8769 /* Continue with SDB mode */ 8770 use_mcq_mode = false; 8771 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 8772 ret); 8773 } 8774 ret = scsi_add_host(host, hba->dev); 8775 if (ret) { 8776 dev_err(hba->dev, "scsi_add_host failed\n"); 8777 return ret; 8778 } 8779 hba->scsi_host_added = true; 8780 } else if (is_mcq_supported(hba)) { 8781 /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */ 8782 ufshcd_config_mcq(hba); 8783 } 8784 } 8785 8786 ufshcd_tune_unipro_params(hba); 8787 8788 /* UFS device is also active now */ 8789 ufshcd_set_ufs_dev_active(hba); 8790 ufshcd_force_reset_auto_bkops(hba); 8791 8792 ufshcd_set_timestamp_attr(hba); 8793 8794 /* Gear up to HS gear if supported */ 8795 if (hba->max_pwr_info.is_valid) { 8796 /* 8797 * Set the right value to bRefClkFreq before attempting to 8798 * switch to HS gears. 8799 */ 8800 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8801 ufshcd_set_dev_ref_clk(hba); 8802 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8803 if (ret) { 8804 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8805 __func__, ret); 8806 return ret; 8807 } 8808 } 8809 8810 return 0; 8811 } 8812 8813 /** 8814 * ufshcd_probe_hba - probe hba to detect device and initialize it 8815 * @hba: per-adapter instance 8816 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8817 * 8818 * Execute link-startup and verify device initialization 8819 * 8820 * Return: 0 upon success; < 0 upon failure. 8821 */ 8822 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8823 { 8824 ktime_t start = ktime_get(); 8825 unsigned long flags; 8826 int ret; 8827 8828 ret = ufshcd_device_init(hba, init_dev_params); 8829 if (ret) 8830 goto out; 8831 8832 if (!hba->pm_op_in_progress && 8833 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8834 /* Reset the device and controller before doing reinit */ 8835 ufshcd_device_reset(hba); 8836 ufshcd_hba_stop(hba); 8837 ufshcd_vops_reinit_notify(hba); 8838 ret = ufshcd_hba_enable(hba); 8839 if (ret) { 8840 dev_err(hba->dev, "Host controller enable failed\n"); 8841 ufshcd_print_evt_hist(hba); 8842 ufshcd_print_host_state(hba); 8843 goto out; 8844 } 8845 8846 /* Reinit the device */ 8847 ret = ufshcd_device_init(hba, init_dev_params); 8848 if (ret) 8849 goto out; 8850 } 8851 8852 ufshcd_print_pwr_info(hba); 8853 8854 /* 8855 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8856 * and for removable UFS card as well, hence always set the parameter. 8857 * Note: Error handler may issue the device reset hence resetting 8858 * bActiveICCLevel as well so it is always safe to set this here. 8859 */ 8860 ufshcd_set_active_icc_lvl(hba); 8861 8862 /* Enable UFS Write Booster if supported */ 8863 ufshcd_configure_wb(hba); 8864 8865 if (hba->ee_usr_mask) 8866 ufshcd_write_ee_control(hba); 8867 /* Enable Auto-Hibernate if configured */ 8868 ufshcd_auto_hibern8_enable(hba); 8869 8870 out: 8871 spin_lock_irqsave(hba->host->host_lock, flags); 8872 if (ret) 8873 hba->ufshcd_state = UFSHCD_STATE_ERROR; 8874 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 8875 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 8876 spin_unlock_irqrestore(hba->host->host_lock, flags); 8877 8878 trace_ufshcd_init(dev_name(hba->dev), ret, 8879 ktime_to_us(ktime_sub(ktime_get(), start)), 8880 hba->curr_dev_pwr_mode, hba->uic_link_state); 8881 return ret; 8882 } 8883 8884 /** 8885 * ufshcd_async_scan - asynchronous execution for probing hba 8886 * @data: data pointer to pass to this function 8887 * @cookie: cookie data 8888 */ 8889 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8890 { 8891 struct ufs_hba *hba = (struct ufs_hba *)data; 8892 int ret; 8893 8894 down(&hba->host_sem); 8895 /* Initialize hba, detect and initialize UFS device */ 8896 ret = ufshcd_probe_hba(hba, true); 8897 up(&hba->host_sem); 8898 if (ret) 8899 goto out; 8900 8901 /* Probe and add UFS logical units */ 8902 ret = ufshcd_add_lus(hba); 8903 out: 8904 /* 8905 * If we failed to initialize the device or the device is not 8906 * present, turn off the power/clocks etc. 8907 */ 8908 if (ret) { 8909 pm_runtime_put_sync(hba->dev); 8910 ufshcd_hba_exit(hba); 8911 } 8912 } 8913 8914 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8915 { 8916 struct ufs_hba *hba = shost_priv(scmd->device->host); 8917 8918 if (!hba->system_suspending) { 8919 /* Activate the error handler in the SCSI core. */ 8920 return SCSI_EH_NOT_HANDLED; 8921 } 8922 8923 /* 8924 * If we get here we know that no TMFs are outstanding and also that 8925 * the only pending command is a START STOP UNIT command. Handle the 8926 * timeout of that command directly to prevent a deadlock between 8927 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8928 */ 8929 ufshcd_link_recovery(hba); 8930 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8931 __func__, hba->outstanding_tasks); 8932 8933 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8934 } 8935 8936 static const struct attribute_group *ufshcd_driver_groups[] = { 8937 &ufs_sysfs_unit_descriptor_group, 8938 &ufs_sysfs_lun_attributes_group, 8939 NULL, 8940 }; 8941 8942 static struct ufs_hba_variant_params ufs_hba_vps = { 8943 .hba_enable_delay_us = 1000, 8944 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8945 .devfreq_profile.polling_ms = 100, 8946 .devfreq_profile.target = ufshcd_devfreq_target, 8947 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8948 .ondemand_data.upthreshold = 70, 8949 .ondemand_data.downdifferential = 5, 8950 }; 8951 8952 static const struct scsi_host_template ufshcd_driver_template = { 8953 .module = THIS_MODULE, 8954 .name = UFSHCD, 8955 .proc_name = UFSHCD, 8956 .map_queues = ufshcd_map_queues, 8957 .queuecommand = ufshcd_queuecommand, 8958 .mq_poll = ufshcd_poll, 8959 .slave_alloc = ufshcd_slave_alloc, 8960 .slave_configure = ufshcd_slave_configure, 8961 .slave_destroy = ufshcd_slave_destroy, 8962 .change_queue_depth = ufshcd_change_queue_depth, 8963 .eh_abort_handler = ufshcd_abort, 8964 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8965 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8966 .eh_timed_out = ufshcd_eh_timed_out, 8967 .this_id = -1, 8968 .sg_tablesize = SG_ALL, 8969 .cmd_per_lun = UFSHCD_CMD_PER_LUN, 8970 .can_queue = UFSHCD_CAN_QUEUE, 8971 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8972 .max_sectors = SZ_1M / SECTOR_SIZE, 8973 .max_host_blocked = 1, 8974 .track_queue_depth = 1, 8975 .skip_settle_delay = 1, 8976 .sdev_groups = ufshcd_driver_groups, 8977 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS, 8978 }; 8979 8980 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8981 int ua) 8982 { 8983 int ret; 8984 8985 if (!vreg) 8986 return 0; 8987 8988 /* 8989 * "set_load" operation shall be required on those regulators 8990 * which specifically configured current limitation. Otherwise 8991 * zero max_uA may cause unexpected behavior when regulator is 8992 * enabled or set as high power mode. 8993 */ 8994 if (!vreg->max_uA) 8995 return 0; 8996 8997 ret = regulator_set_load(vreg->reg, ua); 8998 if (ret < 0) { 8999 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 9000 __func__, vreg->name, ua, ret); 9001 } 9002 9003 return ret; 9004 } 9005 9006 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 9007 struct ufs_vreg *vreg) 9008 { 9009 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 9010 } 9011 9012 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 9013 struct ufs_vreg *vreg) 9014 { 9015 if (!vreg) 9016 return 0; 9017 9018 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 9019 } 9020 9021 static int ufshcd_config_vreg(struct device *dev, 9022 struct ufs_vreg *vreg, bool on) 9023 { 9024 if (regulator_count_voltages(vreg->reg) <= 0) 9025 return 0; 9026 9027 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 9028 } 9029 9030 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 9031 { 9032 int ret = 0; 9033 9034 if (!vreg || vreg->enabled) 9035 goto out; 9036 9037 ret = ufshcd_config_vreg(dev, vreg, true); 9038 if (!ret) 9039 ret = regulator_enable(vreg->reg); 9040 9041 if (!ret) 9042 vreg->enabled = true; 9043 else 9044 dev_err(dev, "%s: %s enable failed, err=%d\n", 9045 __func__, vreg->name, ret); 9046 out: 9047 return ret; 9048 } 9049 9050 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 9051 { 9052 int ret = 0; 9053 9054 if (!vreg || !vreg->enabled || vreg->always_on) 9055 goto out; 9056 9057 ret = regulator_disable(vreg->reg); 9058 9059 if (!ret) { 9060 /* ignore errors on applying disable config */ 9061 ufshcd_config_vreg(dev, vreg, false); 9062 vreg->enabled = false; 9063 } else { 9064 dev_err(dev, "%s: %s disable failed, err=%d\n", 9065 __func__, vreg->name, ret); 9066 } 9067 out: 9068 return ret; 9069 } 9070 9071 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 9072 { 9073 int ret = 0; 9074 struct device *dev = hba->dev; 9075 struct ufs_vreg_info *info = &hba->vreg_info; 9076 9077 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 9078 if (ret) 9079 goto out; 9080 9081 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 9082 if (ret) 9083 goto out; 9084 9085 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 9086 9087 out: 9088 if (ret) { 9089 ufshcd_toggle_vreg(dev, info->vccq2, false); 9090 ufshcd_toggle_vreg(dev, info->vccq, false); 9091 ufshcd_toggle_vreg(dev, info->vcc, false); 9092 } 9093 return ret; 9094 } 9095 9096 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9097 { 9098 struct ufs_vreg_info *info = &hba->vreg_info; 9099 9100 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9101 } 9102 9103 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9104 { 9105 int ret = 0; 9106 9107 if (!vreg) 9108 goto out; 9109 9110 vreg->reg = devm_regulator_get(dev, vreg->name); 9111 if (IS_ERR(vreg->reg)) { 9112 ret = PTR_ERR(vreg->reg); 9113 dev_err(dev, "%s: %s get failed, err=%d\n", 9114 __func__, vreg->name, ret); 9115 } 9116 out: 9117 return ret; 9118 } 9119 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9120 9121 static int ufshcd_init_vreg(struct ufs_hba *hba) 9122 { 9123 int ret = 0; 9124 struct device *dev = hba->dev; 9125 struct ufs_vreg_info *info = &hba->vreg_info; 9126 9127 ret = ufshcd_get_vreg(dev, info->vcc); 9128 if (ret) 9129 goto out; 9130 9131 ret = ufshcd_get_vreg(dev, info->vccq); 9132 if (!ret) 9133 ret = ufshcd_get_vreg(dev, info->vccq2); 9134 out: 9135 return ret; 9136 } 9137 9138 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9139 { 9140 struct ufs_vreg_info *info = &hba->vreg_info; 9141 9142 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9143 } 9144 9145 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9146 { 9147 int ret = 0; 9148 struct ufs_clk_info *clki; 9149 struct list_head *head = &hba->clk_list_head; 9150 unsigned long flags; 9151 ktime_t start = ktime_get(); 9152 bool clk_state_changed = false; 9153 9154 if (list_empty(head)) 9155 goto out; 9156 9157 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9158 if (ret) 9159 return ret; 9160 9161 list_for_each_entry(clki, head, list) { 9162 if (!IS_ERR_OR_NULL(clki->clk)) { 9163 /* 9164 * Don't disable clocks which are needed 9165 * to keep the link active. 9166 */ 9167 if (ufshcd_is_link_active(hba) && 9168 clki->keep_link_active) 9169 continue; 9170 9171 clk_state_changed = on ^ clki->enabled; 9172 if (on && !clki->enabled) { 9173 ret = clk_prepare_enable(clki->clk); 9174 if (ret) { 9175 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9176 __func__, clki->name, ret); 9177 goto out; 9178 } 9179 } else if (!on && clki->enabled) { 9180 clk_disable_unprepare(clki->clk); 9181 } 9182 clki->enabled = on; 9183 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9184 clki->name, on ? "en" : "dis"); 9185 } 9186 } 9187 9188 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9189 if (ret) 9190 return ret; 9191 9192 out: 9193 if (ret) { 9194 list_for_each_entry(clki, head, list) { 9195 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9196 clk_disable_unprepare(clki->clk); 9197 } 9198 } else if (!ret && on) { 9199 spin_lock_irqsave(hba->host->host_lock, flags); 9200 hba->clk_gating.state = CLKS_ON; 9201 trace_ufshcd_clk_gating(dev_name(hba->dev), 9202 hba->clk_gating.state); 9203 spin_unlock_irqrestore(hba->host->host_lock, flags); 9204 } 9205 9206 if (clk_state_changed) 9207 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9208 (on ? "on" : "off"), 9209 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9210 return ret; 9211 } 9212 9213 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9214 { 9215 u32 freq; 9216 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9217 9218 if (ret) { 9219 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9220 return REF_CLK_FREQ_INVAL; 9221 } 9222 9223 return ufs_get_bref_clk_from_hz(freq); 9224 } 9225 9226 static int ufshcd_init_clocks(struct ufs_hba *hba) 9227 { 9228 int ret = 0; 9229 struct ufs_clk_info *clki; 9230 struct device *dev = hba->dev; 9231 struct list_head *head = &hba->clk_list_head; 9232 9233 if (list_empty(head)) 9234 goto out; 9235 9236 list_for_each_entry(clki, head, list) { 9237 if (!clki->name) 9238 continue; 9239 9240 clki->clk = devm_clk_get(dev, clki->name); 9241 if (IS_ERR(clki->clk)) { 9242 ret = PTR_ERR(clki->clk); 9243 dev_err(dev, "%s: %s clk get failed, %d\n", 9244 __func__, clki->name, ret); 9245 goto out; 9246 } 9247 9248 /* 9249 * Parse device ref clk freq as per device tree "ref_clk". 9250 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9251 * in ufshcd_alloc_host(). 9252 */ 9253 if (!strcmp(clki->name, "ref_clk")) 9254 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9255 9256 if (clki->max_freq) { 9257 ret = clk_set_rate(clki->clk, clki->max_freq); 9258 if (ret) { 9259 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9260 __func__, clki->name, 9261 clki->max_freq, ret); 9262 goto out; 9263 } 9264 clki->curr_freq = clki->max_freq; 9265 } 9266 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9267 clki->name, clk_get_rate(clki->clk)); 9268 } 9269 9270 /* Set Max. frequency for all clocks */ 9271 if (hba->use_pm_opp) { 9272 ret = ufshcd_opp_set_rate(hba, ULONG_MAX); 9273 if (ret) { 9274 dev_err(hba->dev, "%s: failed to set OPP: %d", __func__, 9275 ret); 9276 goto out; 9277 } 9278 } 9279 9280 out: 9281 return ret; 9282 } 9283 9284 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9285 { 9286 int err = 0; 9287 9288 if (!hba->vops) 9289 goto out; 9290 9291 err = ufshcd_vops_init(hba); 9292 if (err) 9293 dev_err_probe(hba->dev, err, 9294 "%s: variant %s init failed with err %d\n", 9295 __func__, ufshcd_get_var_name(hba), err); 9296 out: 9297 return err; 9298 } 9299 9300 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9301 { 9302 if (!hba->vops) 9303 return; 9304 9305 ufshcd_vops_exit(hba); 9306 } 9307 9308 static int ufshcd_hba_init(struct ufs_hba *hba) 9309 { 9310 int err; 9311 9312 /* 9313 * Handle host controller power separately from the UFS device power 9314 * rails as it will help controlling the UFS host controller power 9315 * collapse easily which is different than UFS device power collapse. 9316 * Also, enable the host controller power before we go ahead with rest 9317 * of the initialization here. 9318 */ 9319 err = ufshcd_init_hba_vreg(hba); 9320 if (err) 9321 goto out; 9322 9323 err = ufshcd_setup_hba_vreg(hba, true); 9324 if (err) 9325 goto out; 9326 9327 err = ufshcd_init_clocks(hba); 9328 if (err) 9329 goto out_disable_hba_vreg; 9330 9331 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9332 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9333 9334 err = ufshcd_setup_clocks(hba, true); 9335 if (err) 9336 goto out_disable_hba_vreg; 9337 9338 err = ufshcd_init_vreg(hba); 9339 if (err) 9340 goto out_disable_clks; 9341 9342 err = ufshcd_setup_vreg(hba, true); 9343 if (err) 9344 goto out_disable_clks; 9345 9346 err = ufshcd_variant_hba_init(hba); 9347 if (err) 9348 goto out_disable_vreg; 9349 9350 ufs_debugfs_hba_init(hba); 9351 9352 hba->is_powered = true; 9353 goto out; 9354 9355 out_disable_vreg: 9356 ufshcd_setup_vreg(hba, false); 9357 out_disable_clks: 9358 ufshcd_setup_clocks(hba, false); 9359 out_disable_hba_vreg: 9360 ufshcd_setup_hba_vreg(hba, false); 9361 out: 9362 return err; 9363 } 9364 9365 static void ufshcd_hba_exit(struct ufs_hba *hba) 9366 { 9367 if (hba->is_powered) { 9368 ufshcd_exit_clk_scaling(hba); 9369 ufshcd_exit_clk_gating(hba); 9370 if (hba->eh_wq) 9371 destroy_workqueue(hba->eh_wq); 9372 ufs_debugfs_hba_exit(hba); 9373 ufshcd_variant_hba_exit(hba); 9374 ufshcd_setup_vreg(hba, false); 9375 ufshcd_setup_clocks(hba, false); 9376 ufshcd_setup_hba_vreg(hba, false); 9377 hba->is_powered = false; 9378 ufs_put_device_desc(hba); 9379 } 9380 } 9381 9382 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9383 enum ufs_dev_pwr_mode pwr_mode, 9384 struct scsi_sense_hdr *sshdr) 9385 { 9386 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9387 const struct scsi_exec_args args = { 9388 .sshdr = sshdr, 9389 .req_flags = BLK_MQ_REQ_PM, 9390 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9391 }; 9392 9393 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9394 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9395 &args); 9396 } 9397 9398 /** 9399 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9400 * power mode 9401 * @hba: per adapter instance 9402 * @pwr_mode: device power mode to set 9403 * 9404 * Return: 0 if requested power mode is set successfully; 9405 * < 0 if failed to set the requested power mode. 9406 */ 9407 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9408 enum ufs_dev_pwr_mode pwr_mode) 9409 { 9410 struct scsi_sense_hdr sshdr; 9411 struct scsi_device *sdp; 9412 unsigned long flags; 9413 int ret, retries; 9414 9415 spin_lock_irqsave(hba->host->host_lock, flags); 9416 sdp = hba->ufs_device_wlun; 9417 if (sdp && scsi_device_online(sdp)) 9418 ret = scsi_device_get(sdp); 9419 else 9420 ret = -ENODEV; 9421 spin_unlock_irqrestore(hba->host->host_lock, flags); 9422 9423 if (ret) 9424 return ret; 9425 9426 /* 9427 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9428 * handling, which would wait for host to be resumed. Since we know 9429 * we are functional while we are here, skip host resume in error 9430 * handling context. 9431 */ 9432 hba->host->eh_noresume = 1; 9433 9434 /* 9435 * Current function would be generally called from the power management 9436 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9437 * already suspended childs. 9438 */ 9439 for (retries = 3; retries > 0; --retries) { 9440 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9441 /* 9442 * scsi_execute() only returns a negative value if the request 9443 * queue is dying. 9444 */ 9445 if (ret <= 0) 9446 break; 9447 } 9448 if (ret) { 9449 sdev_printk(KERN_WARNING, sdp, 9450 "START_STOP failed for power mode: %d, result %x\n", 9451 pwr_mode, ret); 9452 if (ret > 0) { 9453 if (scsi_sense_valid(&sshdr)) 9454 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9455 ret = -EIO; 9456 } 9457 } else { 9458 hba->curr_dev_pwr_mode = pwr_mode; 9459 } 9460 9461 scsi_device_put(sdp); 9462 hba->host->eh_noresume = 0; 9463 return ret; 9464 } 9465 9466 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9467 enum uic_link_state req_link_state, 9468 bool check_for_bkops) 9469 { 9470 int ret = 0; 9471 9472 if (req_link_state == hba->uic_link_state) 9473 return 0; 9474 9475 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9476 ret = ufshcd_uic_hibern8_enter(hba); 9477 if (!ret) { 9478 ufshcd_set_link_hibern8(hba); 9479 } else { 9480 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9481 __func__, ret); 9482 goto out; 9483 } 9484 } 9485 /* 9486 * If autobkops is enabled, link can't be turned off because 9487 * turning off the link would also turn off the device, except in the 9488 * case of DeepSleep where the device is expected to remain powered. 9489 */ 9490 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9491 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9492 /* 9493 * Let's make sure that link is in low power mode, we are doing 9494 * this currently by putting the link in Hibern8. Otherway to 9495 * put the link in low power mode is to send the DME end point 9496 * to device and then send the DME reset command to local 9497 * unipro. But putting the link in hibern8 is much faster. 9498 * 9499 * Note also that putting the link in Hibern8 is a requirement 9500 * for entering DeepSleep. 9501 */ 9502 ret = ufshcd_uic_hibern8_enter(hba); 9503 if (ret) { 9504 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9505 __func__, ret); 9506 goto out; 9507 } 9508 /* 9509 * Change controller state to "reset state" which 9510 * should also put the link in off/reset state 9511 */ 9512 ufshcd_hba_stop(hba); 9513 /* 9514 * TODO: Check if we need any delay to make sure that 9515 * controller is reset 9516 */ 9517 ufshcd_set_link_off(hba); 9518 } 9519 9520 out: 9521 return ret; 9522 } 9523 9524 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9525 { 9526 bool vcc_off = false; 9527 9528 /* 9529 * It seems some UFS devices may keep drawing more than sleep current 9530 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9531 * To avoid this situation, add 2ms delay before putting these UFS 9532 * rails in LPM mode. 9533 */ 9534 if (!ufshcd_is_link_active(hba) && 9535 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9536 usleep_range(2000, 2100); 9537 9538 /* 9539 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9540 * power. 9541 * 9542 * If UFS device and link is in OFF state, all power supplies (VCC, 9543 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9544 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9545 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9546 * 9547 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9548 * in low power state which would save some power. 9549 * 9550 * If Write Booster is enabled and the device needs to flush the WB 9551 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9552 */ 9553 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9554 !hba->dev_info.is_lu_power_on_wp) { 9555 ufshcd_setup_vreg(hba, false); 9556 vcc_off = true; 9557 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9558 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9559 vcc_off = true; 9560 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9561 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9562 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9563 } 9564 } 9565 9566 /* 9567 * Some UFS devices require delay after VCC power rail is turned-off. 9568 */ 9569 if (vcc_off && hba->vreg_info.vcc && 9570 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9571 usleep_range(5000, 5100); 9572 } 9573 9574 #ifdef CONFIG_PM 9575 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9576 { 9577 int ret = 0; 9578 9579 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9580 !hba->dev_info.is_lu_power_on_wp) { 9581 ret = ufshcd_setup_vreg(hba, true); 9582 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9583 if (!ufshcd_is_link_active(hba)) { 9584 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9585 if (ret) 9586 goto vcc_disable; 9587 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9588 if (ret) 9589 goto vccq_lpm; 9590 } 9591 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9592 } 9593 goto out; 9594 9595 vccq_lpm: 9596 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9597 vcc_disable: 9598 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9599 out: 9600 return ret; 9601 } 9602 #endif /* CONFIG_PM */ 9603 9604 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9605 { 9606 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9607 ufshcd_setup_hba_vreg(hba, false); 9608 } 9609 9610 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9611 { 9612 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9613 ufshcd_setup_hba_vreg(hba, true); 9614 } 9615 9616 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9617 { 9618 int ret = 0; 9619 bool check_for_bkops; 9620 enum ufs_pm_level pm_lvl; 9621 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9622 enum uic_link_state req_link_state; 9623 9624 hba->pm_op_in_progress = true; 9625 if (pm_op != UFS_SHUTDOWN_PM) { 9626 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9627 hba->rpm_lvl : hba->spm_lvl; 9628 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9629 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9630 } else { 9631 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9632 req_link_state = UIC_LINK_OFF_STATE; 9633 } 9634 9635 /* 9636 * If we can't transition into any of the low power modes 9637 * just gate the clocks. 9638 */ 9639 ufshcd_hold(hba); 9640 hba->clk_gating.is_suspended = true; 9641 9642 if (ufshcd_is_clkscaling_supported(hba)) 9643 ufshcd_clk_scaling_suspend(hba, true); 9644 9645 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9646 req_link_state == UIC_LINK_ACTIVE_STATE) { 9647 goto vops_suspend; 9648 } 9649 9650 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9651 (req_link_state == hba->uic_link_state)) 9652 goto enable_scaling; 9653 9654 /* UFS device & link must be active before we enter in this function */ 9655 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9656 ret = -EINVAL; 9657 goto enable_scaling; 9658 } 9659 9660 if (pm_op == UFS_RUNTIME_PM) { 9661 if (ufshcd_can_autobkops_during_suspend(hba)) { 9662 /* 9663 * The device is idle with no requests in the queue, 9664 * allow background operations if bkops status shows 9665 * that performance might be impacted. 9666 */ 9667 ret = ufshcd_urgent_bkops(hba); 9668 if (ret) { 9669 /* 9670 * If return err in suspend flow, IO will hang. 9671 * Trigger error handler and break suspend for 9672 * error recovery. 9673 */ 9674 ufshcd_force_error_recovery(hba); 9675 ret = -EBUSY; 9676 goto enable_scaling; 9677 } 9678 } else { 9679 /* make sure that auto bkops is disabled */ 9680 ufshcd_disable_auto_bkops(hba); 9681 } 9682 /* 9683 * If device needs to do BKOP or WB buffer flush during 9684 * Hibern8, keep device power mode as "active power mode" 9685 * and VCC supply. 9686 */ 9687 hba->dev_info.b_rpm_dev_flush_capable = 9688 hba->auto_bkops_enabled || 9689 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9690 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9691 ufshcd_is_auto_hibern8_enabled(hba))) && 9692 ufshcd_wb_need_flush(hba)); 9693 } 9694 9695 flush_work(&hba->eeh_work); 9696 9697 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9698 if (ret) 9699 goto enable_scaling; 9700 9701 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9702 if (pm_op != UFS_RUNTIME_PM) 9703 /* ensure that bkops is disabled */ 9704 ufshcd_disable_auto_bkops(hba); 9705 9706 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9707 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9708 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9709 /* 9710 * If return err in suspend flow, IO will hang. 9711 * Trigger error handler and break suspend for 9712 * error recovery. 9713 */ 9714 ufshcd_force_error_recovery(hba); 9715 ret = -EBUSY; 9716 } 9717 if (ret) 9718 goto enable_scaling; 9719 } 9720 } 9721 9722 /* 9723 * In the case of DeepSleep, the device is expected to remain powered 9724 * with the link off, so do not check for bkops. 9725 */ 9726 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9727 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9728 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9729 /* 9730 * If return err in suspend flow, IO will hang. 9731 * Trigger error handler and break suspend for 9732 * error recovery. 9733 */ 9734 ufshcd_force_error_recovery(hba); 9735 ret = -EBUSY; 9736 } 9737 if (ret) 9738 goto set_dev_active; 9739 9740 vops_suspend: 9741 /* 9742 * Call vendor specific suspend callback. As these callbacks may access 9743 * vendor specific host controller register space call them before the 9744 * host clocks are ON. 9745 */ 9746 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9747 if (ret) 9748 goto set_link_active; 9749 goto out; 9750 9751 set_link_active: 9752 /* 9753 * Device hardware reset is required to exit DeepSleep. Also, for 9754 * DeepSleep, the link is off so host reset and restore will be done 9755 * further below. 9756 */ 9757 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9758 ufshcd_device_reset(hba); 9759 WARN_ON(!ufshcd_is_link_off(hba)); 9760 } 9761 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9762 ufshcd_set_link_active(hba); 9763 else if (ufshcd_is_link_off(hba)) 9764 ufshcd_host_reset_and_restore(hba); 9765 set_dev_active: 9766 /* Can also get here needing to exit DeepSleep */ 9767 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9768 ufshcd_device_reset(hba); 9769 ufshcd_host_reset_and_restore(hba); 9770 } 9771 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9772 ufshcd_disable_auto_bkops(hba); 9773 enable_scaling: 9774 if (ufshcd_is_clkscaling_supported(hba)) 9775 ufshcd_clk_scaling_suspend(hba, false); 9776 9777 hba->dev_info.b_rpm_dev_flush_capable = false; 9778 out: 9779 if (hba->dev_info.b_rpm_dev_flush_capable) { 9780 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9781 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9782 } 9783 9784 if (ret) { 9785 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9786 hba->clk_gating.is_suspended = false; 9787 ufshcd_release(hba); 9788 } 9789 hba->pm_op_in_progress = false; 9790 return ret; 9791 } 9792 9793 #ifdef CONFIG_PM 9794 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9795 { 9796 int ret; 9797 enum uic_link_state old_link_state = hba->uic_link_state; 9798 9799 hba->pm_op_in_progress = true; 9800 9801 /* 9802 * Call vendor specific resume callback. As these callbacks may access 9803 * vendor specific host controller register space call them when the 9804 * host clocks are ON. 9805 */ 9806 ret = ufshcd_vops_resume(hba, pm_op); 9807 if (ret) 9808 goto out; 9809 9810 /* For DeepSleep, the only supported option is to have the link off */ 9811 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9812 9813 if (ufshcd_is_link_hibern8(hba)) { 9814 ret = ufshcd_uic_hibern8_exit(hba); 9815 if (!ret) { 9816 ufshcd_set_link_active(hba); 9817 } else { 9818 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9819 __func__, ret); 9820 goto vendor_suspend; 9821 } 9822 } else if (ufshcd_is_link_off(hba)) { 9823 /* 9824 * A full initialization of the host and the device is 9825 * required since the link was put to off during suspend. 9826 * Note, in the case of DeepSleep, the device will exit 9827 * DeepSleep due to device reset. 9828 */ 9829 ret = ufshcd_reset_and_restore(hba); 9830 /* 9831 * ufshcd_reset_and_restore() should have already 9832 * set the link state as active 9833 */ 9834 if (ret || !ufshcd_is_link_active(hba)) 9835 goto vendor_suspend; 9836 } 9837 9838 if (!ufshcd_is_ufs_dev_active(hba)) { 9839 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9840 if (ret) 9841 goto set_old_link_state; 9842 ufshcd_set_timestamp_attr(hba); 9843 } 9844 9845 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9846 ufshcd_enable_auto_bkops(hba); 9847 else 9848 /* 9849 * If BKOPs operations are urgently needed at this moment then 9850 * keep auto-bkops enabled or else disable it. 9851 */ 9852 ufshcd_urgent_bkops(hba); 9853 9854 if (hba->ee_usr_mask) 9855 ufshcd_write_ee_control(hba); 9856 9857 if (ufshcd_is_clkscaling_supported(hba)) 9858 ufshcd_clk_scaling_suspend(hba, false); 9859 9860 if (hba->dev_info.b_rpm_dev_flush_capable) { 9861 hba->dev_info.b_rpm_dev_flush_capable = false; 9862 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9863 } 9864 9865 /* Enable Auto-Hibernate if configured */ 9866 ufshcd_auto_hibern8_enable(hba); 9867 9868 goto out; 9869 9870 set_old_link_state: 9871 ufshcd_link_state_transition(hba, old_link_state, 0); 9872 vendor_suspend: 9873 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9874 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9875 out: 9876 if (ret) 9877 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9878 hba->clk_gating.is_suspended = false; 9879 ufshcd_release(hba); 9880 hba->pm_op_in_progress = false; 9881 return ret; 9882 } 9883 9884 static int ufshcd_wl_runtime_suspend(struct device *dev) 9885 { 9886 struct scsi_device *sdev = to_scsi_device(dev); 9887 struct ufs_hba *hba; 9888 int ret; 9889 ktime_t start = ktime_get(); 9890 9891 hba = shost_priv(sdev->host); 9892 9893 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9894 if (ret) 9895 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9896 9897 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9898 ktime_to_us(ktime_sub(ktime_get(), start)), 9899 hba->curr_dev_pwr_mode, hba->uic_link_state); 9900 9901 return ret; 9902 } 9903 9904 static int ufshcd_wl_runtime_resume(struct device *dev) 9905 { 9906 struct scsi_device *sdev = to_scsi_device(dev); 9907 struct ufs_hba *hba; 9908 int ret = 0; 9909 ktime_t start = ktime_get(); 9910 9911 hba = shost_priv(sdev->host); 9912 9913 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9914 if (ret) 9915 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9916 9917 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9918 ktime_to_us(ktime_sub(ktime_get(), start)), 9919 hba->curr_dev_pwr_mode, hba->uic_link_state); 9920 9921 return ret; 9922 } 9923 #endif 9924 9925 #ifdef CONFIG_PM_SLEEP 9926 static int ufshcd_wl_suspend(struct device *dev) 9927 { 9928 struct scsi_device *sdev = to_scsi_device(dev); 9929 struct ufs_hba *hba; 9930 int ret = 0; 9931 ktime_t start = ktime_get(); 9932 9933 hba = shost_priv(sdev->host); 9934 down(&hba->host_sem); 9935 hba->system_suspending = true; 9936 9937 if (pm_runtime_suspended(dev)) 9938 goto out; 9939 9940 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9941 if (ret) { 9942 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9943 up(&hba->host_sem); 9944 } 9945 9946 out: 9947 if (!ret) 9948 hba->is_sys_suspended = true; 9949 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9950 ktime_to_us(ktime_sub(ktime_get(), start)), 9951 hba->curr_dev_pwr_mode, hba->uic_link_state); 9952 9953 return ret; 9954 } 9955 9956 static int ufshcd_wl_resume(struct device *dev) 9957 { 9958 struct scsi_device *sdev = to_scsi_device(dev); 9959 struct ufs_hba *hba; 9960 int ret = 0; 9961 ktime_t start = ktime_get(); 9962 9963 hba = shost_priv(sdev->host); 9964 9965 if (pm_runtime_suspended(dev)) 9966 goto out; 9967 9968 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9969 if (ret) 9970 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9971 out: 9972 trace_ufshcd_wl_resume(dev_name(dev), ret, 9973 ktime_to_us(ktime_sub(ktime_get(), start)), 9974 hba->curr_dev_pwr_mode, hba->uic_link_state); 9975 if (!ret) 9976 hba->is_sys_suspended = false; 9977 hba->system_suspending = false; 9978 up(&hba->host_sem); 9979 return ret; 9980 } 9981 #endif 9982 9983 /** 9984 * ufshcd_suspend - helper function for suspend operations 9985 * @hba: per adapter instance 9986 * 9987 * This function will put disable irqs, turn off clocks 9988 * and set vreg and hba-vreg in lpm mode. 9989 * 9990 * Return: 0 upon success; < 0 upon failure. 9991 */ 9992 static int ufshcd_suspend(struct ufs_hba *hba) 9993 { 9994 int ret; 9995 9996 if (!hba->is_powered) 9997 return 0; 9998 /* 9999 * Disable the host irq as host controller as there won't be any 10000 * host controller transaction expected till resume. 10001 */ 10002 ufshcd_disable_irq(hba); 10003 ret = ufshcd_setup_clocks(hba, false); 10004 if (ret) { 10005 ufshcd_enable_irq(hba); 10006 return ret; 10007 } 10008 if (ufshcd_is_clkgating_allowed(hba)) { 10009 hba->clk_gating.state = CLKS_OFF; 10010 trace_ufshcd_clk_gating(dev_name(hba->dev), 10011 hba->clk_gating.state); 10012 } 10013 10014 ufshcd_vreg_set_lpm(hba); 10015 /* Put the host controller in low power mode if possible */ 10016 ufshcd_hba_vreg_set_lpm(hba); 10017 return ret; 10018 } 10019 10020 #ifdef CONFIG_PM 10021 /** 10022 * ufshcd_resume - helper function for resume operations 10023 * @hba: per adapter instance 10024 * 10025 * This function basically turns on the regulators, clocks and 10026 * irqs of the hba. 10027 * 10028 * Return: 0 for success and non-zero for failure. 10029 */ 10030 static int ufshcd_resume(struct ufs_hba *hba) 10031 { 10032 int ret; 10033 10034 if (!hba->is_powered) 10035 return 0; 10036 10037 ufshcd_hba_vreg_set_hpm(hba); 10038 ret = ufshcd_vreg_set_hpm(hba); 10039 if (ret) 10040 goto out; 10041 10042 /* Make sure clocks are enabled before accessing controller */ 10043 ret = ufshcd_setup_clocks(hba, true); 10044 if (ret) 10045 goto disable_vreg; 10046 10047 /* enable the host irq as host controller would be active soon */ 10048 ufshcd_enable_irq(hba); 10049 10050 goto out; 10051 10052 disable_vreg: 10053 ufshcd_vreg_set_lpm(hba); 10054 out: 10055 if (ret) 10056 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 10057 return ret; 10058 } 10059 #endif /* CONFIG_PM */ 10060 10061 #ifdef CONFIG_PM_SLEEP 10062 /** 10063 * ufshcd_system_suspend - system suspend callback 10064 * @dev: Device associated with the UFS controller. 10065 * 10066 * Executed before putting the system into a sleep state in which the contents 10067 * of main memory are preserved. 10068 * 10069 * Return: 0 for success and non-zero for failure. 10070 */ 10071 int ufshcd_system_suspend(struct device *dev) 10072 { 10073 struct ufs_hba *hba = dev_get_drvdata(dev); 10074 int ret = 0; 10075 ktime_t start = ktime_get(); 10076 10077 if (pm_runtime_suspended(hba->dev)) 10078 goto out; 10079 10080 ret = ufshcd_suspend(hba); 10081 out: 10082 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 10083 ktime_to_us(ktime_sub(ktime_get(), start)), 10084 hba->curr_dev_pwr_mode, hba->uic_link_state); 10085 return ret; 10086 } 10087 EXPORT_SYMBOL(ufshcd_system_suspend); 10088 10089 /** 10090 * ufshcd_system_resume - system resume callback 10091 * @dev: Device associated with the UFS controller. 10092 * 10093 * Executed after waking the system up from a sleep state in which the contents 10094 * of main memory were preserved. 10095 * 10096 * Return: 0 for success and non-zero for failure. 10097 */ 10098 int ufshcd_system_resume(struct device *dev) 10099 { 10100 struct ufs_hba *hba = dev_get_drvdata(dev); 10101 ktime_t start = ktime_get(); 10102 int ret = 0; 10103 10104 if (pm_runtime_suspended(hba->dev)) 10105 goto out; 10106 10107 ret = ufshcd_resume(hba); 10108 10109 out: 10110 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10111 ktime_to_us(ktime_sub(ktime_get(), start)), 10112 hba->curr_dev_pwr_mode, hba->uic_link_state); 10113 10114 return ret; 10115 } 10116 EXPORT_SYMBOL(ufshcd_system_resume); 10117 #endif /* CONFIG_PM_SLEEP */ 10118 10119 #ifdef CONFIG_PM 10120 /** 10121 * ufshcd_runtime_suspend - runtime suspend callback 10122 * @dev: Device associated with the UFS controller. 10123 * 10124 * Check the description of ufshcd_suspend() function for more details. 10125 * 10126 * Return: 0 for success and non-zero for failure. 10127 */ 10128 int ufshcd_runtime_suspend(struct device *dev) 10129 { 10130 struct ufs_hba *hba = dev_get_drvdata(dev); 10131 int ret; 10132 ktime_t start = ktime_get(); 10133 10134 ret = ufshcd_suspend(hba); 10135 10136 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10137 ktime_to_us(ktime_sub(ktime_get(), start)), 10138 hba->curr_dev_pwr_mode, hba->uic_link_state); 10139 return ret; 10140 } 10141 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10142 10143 /** 10144 * ufshcd_runtime_resume - runtime resume routine 10145 * @dev: Device associated with the UFS controller. 10146 * 10147 * This function basically brings controller 10148 * to active state. Following operations are done in this function: 10149 * 10150 * 1. Turn on all the controller related clocks 10151 * 2. Turn ON VCC rail 10152 * 10153 * Return: 0 upon success; < 0 upon failure. 10154 */ 10155 int ufshcd_runtime_resume(struct device *dev) 10156 { 10157 struct ufs_hba *hba = dev_get_drvdata(dev); 10158 int ret; 10159 ktime_t start = ktime_get(); 10160 10161 ret = ufshcd_resume(hba); 10162 10163 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10164 ktime_to_us(ktime_sub(ktime_get(), start)), 10165 hba->curr_dev_pwr_mode, hba->uic_link_state); 10166 return ret; 10167 } 10168 EXPORT_SYMBOL(ufshcd_runtime_resume); 10169 #endif /* CONFIG_PM */ 10170 10171 static void ufshcd_wl_shutdown(struct device *dev) 10172 { 10173 struct scsi_device *sdev = to_scsi_device(dev); 10174 struct ufs_hba *hba = shost_priv(sdev->host); 10175 10176 down(&hba->host_sem); 10177 hba->shutting_down = true; 10178 up(&hba->host_sem); 10179 10180 /* Turn on everything while shutting down */ 10181 ufshcd_rpm_get_sync(hba); 10182 scsi_device_quiesce(sdev); 10183 shost_for_each_device(sdev, hba->host) { 10184 if (sdev == hba->ufs_device_wlun) 10185 continue; 10186 scsi_device_quiesce(sdev); 10187 } 10188 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10189 10190 /* 10191 * Next, turn off the UFS controller and the UFS regulators. Disable 10192 * clocks. 10193 */ 10194 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10195 ufshcd_suspend(hba); 10196 10197 hba->is_powered = false; 10198 } 10199 10200 /** 10201 * ufshcd_remove - de-allocate SCSI host and host memory space 10202 * data structure memory 10203 * @hba: per adapter instance 10204 */ 10205 void ufshcd_remove(struct ufs_hba *hba) 10206 { 10207 if (hba->ufs_device_wlun) 10208 ufshcd_rpm_get_sync(hba); 10209 ufs_hwmon_remove(hba); 10210 ufs_bsg_remove(hba); 10211 ufs_sysfs_remove_nodes(hba->dev); 10212 blk_mq_destroy_queue(hba->tmf_queue); 10213 blk_put_queue(hba->tmf_queue); 10214 blk_mq_free_tag_set(&hba->tmf_tag_set); 10215 scsi_remove_host(hba->host); 10216 /* disable interrupts */ 10217 ufshcd_disable_intr(hba, hba->intr_mask); 10218 ufshcd_hba_stop(hba); 10219 ufshcd_hba_exit(hba); 10220 } 10221 EXPORT_SYMBOL_GPL(ufshcd_remove); 10222 10223 #ifdef CONFIG_PM_SLEEP 10224 int ufshcd_system_freeze(struct device *dev) 10225 { 10226 10227 return ufshcd_system_suspend(dev); 10228 10229 } 10230 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10231 10232 int ufshcd_system_restore(struct device *dev) 10233 { 10234 10235 struct ufs_hba *hba = dev_get_drvdata(dev); 10236 int ret; 10237 10238 ret = ufshcd_system_resume(dev); 10239 if (ret) 10240 return ret; 10241 10242 /* Configure UTRL and UTMRL base address registers */ 10243 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10244 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10245 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10246 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10247 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10248 REG_UTP_TASK_REQ_LIST_BASE_L); 10249 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10250 REG_UTP_TASK_REQ_LIST_BASE_H); 10251 /* 10252 * Make sure that UTRL and UTMRL base address registers 10253 * are updated with the latest queue addresses. Only after 10254 * updating these addresses, we can queue the new commands. 10255 */ 10256 mb(); 10257 10258 /* Resuming from hibernate, assume that link was OFF */ 10259 ufshcd_set_link_off(hba); 10260 10261 return 0; 10262 10263 } 10264 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10265 10266 int ufshcd_system_thaw(struct device *dev) 10267 { 10268 return ufshcd_system_resume(dev); 10269 } 10270 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10271 #endif /* CONFIG_PM_SLEEP */ 10272 10273 /** 10274 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10275 * @hba: pointer to Host Bus Adapter (HBA) 10276 */ 10277 void ufshcd_dealloc_host(struct ufs_hba *hba) 10278 { 10279 scsi_host_put(hba->host); 10280 } 10281 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10282 10283 /** 10284 * ufshcd_set_dma_mask - Set dma mask based on the controller 10285 * addressing capability 10286 * @hba: per adapter instance 10287 * 10288 * Return: 0 for success, non-zero for failure. 10289 */ 10290 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10291 { 10292 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10293 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10294 return 0; 10295 } 10296 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10297 } 10298 10299 /** 10300 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10301 * @dev: pointer to device handle 10302 * @hba_handle: driver private handle 10303 * 10304 * Return: 0 on success, non-zero value on failure. 10305 */ 10306 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10307 { 10308 struct Scsi_Host *host; 10309 struct ufs_hba *hba; 10310 int err = 0; 10311 10312 if (!dev) { 10313 dev_err(dev, 10314 "Invalid memory reference for dev is NULL\n"); 10315 err = -ENODEV; 10316 goto out_error; 10317 } 10318 10319 host = scsi_host_alloc(&ufshcd_driver_template, 10320 sizeof(struct ufs_hba)); 10321 if (!host) { 10322 dev_err(dev, "scsi_host_alloc failed\n"); 10323 err = -ENOMEM; 10324 goto out_error; 10325 } 10326 host->nr_maps = HCTX_TYPE_POLL + 1; 10327 hba = shost_priv(host); 10328 hba->host = host; 10329 hba->dev = dev; 10330 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10331 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10332 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10333 INIT_LIST_HEAD(&hba->clk_list_head); 10334 spin_lock_init(&hba->outstanding_lock); 10335 10336 *hba_handle = hba; 10337 10338 out_error: 10339 return err; 10340 } 10341 EXPORT_SYMBOL(ufshcd_alloc_host); 10342 10343 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10344 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10345 const struct blk_mq_queue_data *qd) 10346 { 10347 WARN_ON_ONCE(true); 10348 return BLK_STS_NOTSUPP; 10349 } 10350 10351 static const struct blk_mq_ops ufshcd_tmf_ops = { 10352 .queue_rq = ufshcd_queue_tmf, 10353 }; 10354 10355 /** 10356 * ufshcd_init - Driver initialization routine 10357 * @hba: per-adapter instance 10358 * @mmio_base: base register address 10359 * @irq: Interrupt line of device 10360 * 10361 * Return: 0 on success, non-zero value on failure. 10362 */ 10363 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10364 { 10365 int err; 10366 struct Scsi_Host *host = hba->host; 10367 struct device *dev = hba->dev; 10368 char eh_wq_name[sizeof("ufs_eh_wq_00")]; 10369 10370 /* 10371 * dev_set_drvdata() must be called before any callbacks are registered 10372 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10373 * sysfs). 10374 */ 10375 dev_set_drvdata(dev, hba); 10376 10377 if (!mmio_base) { 10378 dev_err(hba->dev, 10379 "Invalid memory reference for mmio_base is NULL\n"); 10380 err = -ENODEV; 10381 goto out_error; 10382 } 10383 10384 hba->mmio_base = mmio_base; 10385 hba->irq = irq; 10386 hba->vps = &ufs_hba_vps; 10387 10388 err = ufshcd_hba_init(hba); 10389 if (err) 10390 goto out_error; 10391 10392 /* Read capabilities registers */ 10393 err = ufshcd_hba_capabilities(hba); 10394 if (err) 10395 goto out_disable; 10396 10397 /* Get UFS version supported by the controller */ 10398 hba->ufs_version = ufshcd_get_ufs_version(hba); 10399 10400 /* Get Interrupt bit mask per version */ 10401 hba->intr_mask = ufshcd_get_intr_mask(hba); 10402 10403 err = ufshcd_set_dma_mask(hba); 10404 if (err) { 10405 dev_err(hba->dev, "set dma mask failed\n"); 10406 goto out_disable; 10407 } 10408 10409 /* Allocate memory for host memory space */ 10410 err = ufshcd_memory_alloc(hba); 10411 if (err) { 10412 dev_err(hba->dev, "Memory allocation failed\n"); 10413 goto out_disable; 10414 } 10415 10416 /* Configure LRB */ 10417 ufshcd_host_memory_configure(hba); 10418 10419 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10420 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10421 host->max_id = UFSHCD_MAX_ID; 10422 host->max_lun = UFS_MAX_LUNS; 10423 host->max_channel = UFSHCD_MAX_CHANNEL; 10424 host->unique_id = host->host_no; 10425 host->max_cmd_len = UFS_CDB_SIZE; 10426 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10427 10428 hba->max_pwr_info.is_valid = false; 10429 10430 /* Initialize work queues */ 10431 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d", 10432 hba->host->host_no); 10433 hba->eh_wq = create_singlethread_workqueue(eh_wq_name); 10434 if (!hba->eh_wq) { 10435 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10436 __func__); 10437 err = -ENOMEM; 10438 goto out_disable; 10439 } 10440 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10441 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10442 10443 sema_init(&hba->host_sem, 1); 10444 10445 /* Initialize UIC command mutex */ 10446 mutex_init(&hba->uic_cmd_mutex); 10447 10448 /* Initialize mutex for device management commands */ 10449 mutex_init(&hba->dev_cmd.lock); 10450 10451 /* Initialize mutex for exception event control */ 10452 mutex_init(&hba->ee_ctrl_mutex); 10453 10454 mutex_init(&hba->wb_mutex); 10455 init_rwsem(&hba->clk_scaling_lock); 10456 10457 ufshcd_init_clk_gating(hba); 10458 10459 ufshcd_init_clk_scaling(hba); 10460 10461 /* 10462 * In order to avoid any spurious interrupt immediately after 10463 * registering UFS controller interrupt handler, clear any pending UFS 10464 * interrupt status and disable all the UFS interrupts. 10465 */ 10466 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10467 REG_INTERRUPT_STATUS); 10468 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10469 /* 10470 * Make sure that UFS interrupts are disabled and any pending interrupt 10471 * status is cleared before registering UFS interrupt handler. 10472 */ 10473 mb(); 10474 10475 /* IRQ registration */ 10476 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10477 if (err) { 10478 dev_err(hba->dev, "request irq failed\n"); 10479 goto out_disable; 10480 } else { 10481 hba->is_irq_enabled = true; 10482 } 10483 10484 if (!is_mcq_supported(hba)) { 10485 err = scsi_add_host(host, hba->dev); 10486 if (err) { 10487 dev_err(hba->dev, "scsi_add_host failed\n"); 10488 goto out_disable; 10489 } 10490 } 10491 10492 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10493 .nr_hw_queues = 1, 10494 .queue_depth = hba->nutmrs, 10495 .ops = &ufshcd_tmf_ops, 10496 .flags = BLK_MQ_F_NO_SCHED, 10497 }; 10498 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10499 if (err < 0) 10500 goto out_remove_scsi_host; 10501 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set); 10502 if (IS_ERR(hba->tmf_queue)) { 10503 err = PTR_ERR(hba->tmf_queue); 10504 goto free_tmf_tag_set; 10505 } 10506 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10507 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10508 if (!hba->tmf_rqs) { 10509 err = -ENOMEM; 10510 goto free_tmf_queue; 10511 } 10512 10513 /* Reset the attached device */ 10514 ufshcd_device_reset(hba); 10515 10516 ufshcd_init_crypto(hba); 10517 10518 /* Host controller enable */ 10519 err = ufshcd_hba_enable(hba); 10520 if (err) { 10521 dev_err(hba->dev, "Host controller enable failed\n"); 10522 ufshcd_print_evt_hist(hba); 10523 ufshcd_print_host_state(hba); 10524 goto free_tmf_queue; 10525 } 10526 10527 /* 10528 * Set the default power management level for runtime and system PM. 10529 * Default power saving mode is to keep UFS link in Hibern8 state 10530 * and UFS device in sleep state. 10531 */ 10532 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10533 UFS_SLEEP_PWR_MODE, 10534 UIC_LINK_HIBERN8_STATE); 10535 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10536 UFS_SLEEP_PWR_MODE, 10537 UIC_LINK_HIBERN8_STATE); 10538 10539 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, 10540 ufshcd_rpm_dev_flush_recheck_work); 10541 10542 /* Set the default auto-hiberate idle timer value to 150 ms */ 10543 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10544 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10545 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10546 } 10547 10548 /* Hold auto suspend until async scan completes */ 10549 pm_runtime_get_sync(dev); 10550 atomic_set(&hba->scsi_block_reqs_cnt, 0); 10551 /* 10552 * We are assuming that device wasn't put in sleep/power-down 10553 * state exclusively during the boot stage before kernel. 10554 * This assumption helps avoid doing link startup twice during 10555 * ufshcd_probe_hba(). 10556 */ 10557 ufshcd_set_ufs_dev_active(hba); 10558 10559 async_schedule(ufshcd_async_scan, hba); 10560 ufs_sysfs_add_nodes(hba->dev); 10561 10562 device_enable_async_suspend(dev); 10563 return 0; 10564 10565 free_tmf_queue: 10566 blk_mq_destroy_queue(hba->tmf_queue); 10567 blk_put_queue(hba->tmf_queue); 10568 free_tmf_tag_set: 10569 blk_mq_free_tag_set(&hba->tmf_tag_set); 10570 out_remove_scsi_host: 10571 scsi_remove_host(hba->host); 10572 out_disable: 10573 hba->is_irq_enabled = false; 10574 ufshcd_hba_exit(hba); 10575 out_error: 10576 return err; 10577 } 10578 EXPORT_SYMBOL_GPL(ufshcd_init); 10579 10580 void ufshcd_resume_complete(struct device *dev) 10581 { 10582 struct ufs_hba *hba = dev_get_drvdata(dev); 10583 10584 if (hba->complete_put) { 10585 ufshcd_rpm_put(hba); 10586 hba->complete_put = false; 10587 } 10588 } 10589 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10590 10591 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10592 { 10593 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10594 enum ufs_dev_pwr_mode dev_pwr_mode; 10595 enum uic_link_state link_state; 10596 unsigned long flags; 10597 bool res; 10598 10599 spin_lock_irqsave(&dev->power.lock, flags); 10600 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10601 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10602 res = pm_runtime_suspended(dev) && 10603 hba->curr_dev_pwr_mode == dev_pwr_mode && 10604 hba->uic_link_state == link_state && 10605 !hba->dev_info.b_rpm_dev_flush_capable; 10606 spin_unlock_irqrestore(&dev->power.lock, flags); 10607 10608 return res; 10609 } 10610 10611 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10612 { 10613 struct ufs_hba *hba = dev_get_drvdata(dev); 10614 int ret; 10615 10616 /* 10617 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10618 * are same. And it doesn't wake up the device for system-suspend 10619 * if it's runtime suspended. But ufs doesn't follow that. 10620 * Refer ufshcd_resume_complete() 10621 */ 10622 if (hba->ufs_device_wlun) { 10623 /* Prevent runtime suspend */ 10624 ufshcd_rpm_get_noresume(hba); 10625 /* 10626 * Check if already runtime suspended in same state as system 10627 * suspend would be. 10628 */ 10629 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10630 /* RPM state is not ok for SPM, so runtime resume */ 10631 ret = ufshcd_rpm_resume(hba); 10632 if (ret < 0 && ret != -EACCES) { 10633 ufshcd_rpm_put(hba); 10634 return ret; 10635 } 10636 } 10637 hba->complete_put = true; 10638 } 10639 return 0; 10640 } 10641 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10642 10643 int ufshcd_suspend_prepare(struct device *dev) 10644 { 10645 return __ufshcd_suspend_prepare(dev, true); 10646 } 10647 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10648 10649 #ifdef CONFIG_PM_SLEEP 10650 static int ufshcd_wl_poweroff(struct device *dev) 10651 { 10652 struct scsi_device *sdev = to_scsi_device(dev); 10653 struct ufs_hba *hba = shost_priv(sdev->host); 10654 10655 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10656 return 0; 10657 } 10658 #endif 10659 10660 static int ufshcd_wl_probe(struct device *dev) 10661 { 10662 struct scsi_device *sdev = to_scsi_device(dev); 10663 10664 if (!is_device_wlun(sdev)) 10665 return -ENODEV; 10666 10667 blk_pm_runtime_init(sdev->request_queue, dev); 10668 pm_runtime_set_autosuspend_delay(dev, 0); 10669 pm_runtime_allow(dev); 10670 10671 return 0; 10672 } 10673 10674 static int ufshcd_wl_remove(struct device *dev) 10675 { 10676 pm_runtime_forbid(dev); 10677 return 0; 10678 } 10679 10680 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10681 #ifdef CONFIG_PM_SLEEP 10682 .suspend = ufshcd_wl_suspend, 10683 .resume = ufshcd_wl_resume, 10684 .freeze = ufshcd_wl_suspend, 10685 .thaw = ufshcd_wl_resume, 10686 .poweroff = ufshcd_wl_poweroff, 10687 .restore = ufshcd_wl_resume, 10688 #endif 10689 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10690 }; 10691 10692 static void ufshcd_check_header_layout(void) 10693 { 10694 /* 10695 * gcc compilers before version 10 cannot do constant-folding for 10696 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10697 * before. 10698 */ 10699 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10700 return; 10701 10702 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10703 .cci = 3})[0] != 3); 10704 10705 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10706 .ehs_length = 2})[1] != 2); 10707 10708 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10709 .enable_crypto = 1})[2] 10710 != 0x80); 10711 10712 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10713 .command_type = 5, 10714 .data_direction = 3, 10715 .interrupt = 1, 10716 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10717 10718 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10719 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10720 cpu_to_le32(0xdeadbeef)); 10721 10722 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10723 .ocs = 4})[8] != 4); 10724 10725 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10726 .cds = 5})[9] != 5); 10727 10728 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10729 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10730 cpu_to_le32(0xbadcafe)); 10731 10732 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10733 .iid = 0xf })[4] != 0xf0); 10734 10735 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10736 .command_set_type = 0xf })[4] != 0xf); 10737 } 10738 10739 /* 10740 * ufs_dev_wlun_template - describes ufs device wlun 10741 * ufs-device wlun - used to send pm commands 10742 * All luns are consumers of ufs-device wlun. 10743 * 10744 * Currently, no sd driver is present for wluns. 10745 * Hence the no specific pm operations are performed. 10746 * With ufs design, SSU should be sent to ufs-device wlun. 10747 * Hence register a scsi driver for ufs wluns only. 10748 */ 10749 static struct scsi_driver ufs_dev_wlun_template = { 10750 .gendrv = { 10751 .name = "ufs_device_wlun", 10752 .owner = THIS_MODULE, 10753 .probe = ufshcd_wl_probe, 10754 .remove = ufshcd_wl_remove, 10755 .pm = &ufshcd_wl_pm_ops, 10756 .shutdown = ufshcd_wl_shutdown, 10757 }, 10758 }; 10759 10760 static int __init ufshcd_core_init(void) 10761 { 10762 int ret; 10763 10764 ufshcd_check_header_layout(); 10765 10766 ufs_debugfs_init(); 10767 10768 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10769 if (ret) 10770 ufs_debugfs_exit(); 10771 return ret; 10772 } 10773 10774 static void __exit ufshcd_core_exit(void) 10775 { 10776 ufs_debugfs_exit(); 10777 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10778 } 10779 10780 module_init(ufshcd_core_init); 10781 module_exit(ufshcd_core_exit); 10782 10783 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10784 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10785 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10786 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10787 MODULE_LICENSE("GPL"); 10788