1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/pm_opp.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/sched/clock.h> 26 #include <linux/iopoll.h> 27 #include <scsi/scsi_cmnd.h> 28 #include <scsi/scsi_dbg.h> 29 #include <scsi/scsi_driver.h> 30 #include <scsi/scsi_eh.h> 31 #include "ufshcd-priv.h" 32 #include <ufs/ufs_quirks.h> 33 #include <ufs/unipro.h> 34 #include "ufs-sysfs.h" 35 #include "ufs-debugfs.h" 36 #include "ufs-fault-injection.h" 37 #include "ufs_bsg.h" 38 #include "ufshcd-crypto.h" 39 #include <asm/unaligned.h> 40 41 #define CREATE_TRACE_POINTS 42 #include <trace/events/ufs.h> 43 44 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 45 UTP_TASK_REQ_COMPL |\ 46 UFSHCD_ERROR_MASK) 47 48 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 49 UFSHCD_ERROR_MASK |\ 50 MCQ_CQ_EVENT_STATUS) 51 52 53 /* UIC command timeout, unit: ms */ 54 #define UIC_CMD_TIMEOUT 500 55 56 /* NOP OUT retries waiting for NOP IN response */ 57 #define NOP_OUT_RETRIES 10 58 /* Timeout after 50 msecs if NOP OUT hangs without response */ 59 #define NOP_OUT_TIMEOUT 50 /* msecs */ 60 61 /* Query request retries */ 62 #define QUERY_REQ_RETRIES 3 63 /* Query request timeout */ 64 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 65 66 /* Advanced RPMB request timeout */ 67 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 68 69 /* Task management command timeout */ 70 #define TM_CMD_TIMEOUT 100 /* msecs */ 71 72 /* maximum number of retries for a general UIC command */ 73 #define UFS_UIC_COMMAND_RETRIES 3 74 75 /* maximum number of link-startup retries */ 76 #define DME_LINKSTARTUP_RETRIES 3 77 78 /* maximum number of reset retries before giving up */ 79 #define MAX_HOST_RESET_RETRIES 5 80 81 /* Maximum number of error handler retries before giving up */ 82 #define MAX_ERR_HANDLER_RETRIES 5 83 84 /* Expose the flag value from utp_upiu_query.value */ 85 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 86 87 /* Interrupt aggregation default timeout, unit: 40us */ 88 #define INT_AGGR_DEF_TO 0x02 89 90 /* default delay of autosuspend: 2000 ms */ 91 #define RPM_AUTOSUSPEND_DELAY_MS 2000 92 93 /* Default delay of RPM device flush delayed work */ 94 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 95 96 /* Default value of wait time before gating device ref clock */ 97 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 98 99 /* Polling time to wait for fDeviceInit */ 100 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 101 102 /* Default RTC update every 10 seconds */ 103 #define UFS_RTC_UPDATE_INTERVAL_MS (10 * MSEC_PER_SEC) 104 105 /* UFSHC 4.0 compliant HC support this mode. */ 106 static bool use_mcq_mode = true; 107 108 static bool is_mcq_supported(struct ufs_hba *hba) 109 { 110 return hba->mcq_sup && use_mcq_mode; 111 } 112 113 module_param(use_mcq_mode, bool, 0644); 114 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 115 116 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 117 ({ \ 118 int _ret; \ 119 if (_on) \ 120 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 121 else \ 122 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 123 _ret; \ 124 }) 125 126 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 127 size_t __len = (len); \ 128 print_hex_dump(KERN_ERR, prefix_str, \ 129 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 130 16, 4, buf, __len, false); \ 131 } while (0) 132 133 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 134 const char *prefix) 135 { 136 u32 *regs; 137 size_t pos; 138 139 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 140 return -EINVAL; 141 142 regs = kzalloc(len, GFP_ATOMIC); 143 if (!regs) 144 return -ENOMEM; 145 146 for (pos = 0; pos < len; pos += 4) { 147 if (offset == 0 && 148 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 149 pos <= REG_UIC_ERROR_CODE_DME) 150 continue; 151 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 152 } 153 154 ufshcd_hex_dump(prefix, regs, len); 155 kfree(regs); 156 157 return 0; 158 } 159 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 160 161 enum { 162 UFSHCD_MAX_CHANNEL = 0, 163 UFSHCD_MAX_ID = 1, 164 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED, 165 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED, 166 }; 167 168 static const char *const ufshcd_state_name[] = { 169 [UFSHCD_STATE_RESET] = "reset", 170 [UFSHCD_STATE_OPERATIONAL] = "operational", 171 [UFSHCD_STATE_ERROR] = "error", 172 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 173 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 174 }; 175 176 /* UFSHCD error handling flags */ 177 enum { 178 UFSHCD_EH_IN_PROGRESS = (1 << 0), 179 }; 180 181 /* UFSHCD UIC layer error flags */ 182 enum { 183 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 184 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 185 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 186 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 187 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 188 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 189 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 190 }; 191 192 #define ufshcd_set_eh_in_progress(h) \ 193 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 194 #define ufshcd_eh_in_progress(h) \ 195 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 196 #define ufshcd_clear_eh_in_progress(h) \ 197 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 198 199 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 200 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 201 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 202 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 203 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 204 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 205 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 206 /* 207 * For DeepSleep, the link is first put in hibern8 and then off. 208 * Leaving the link in hibern8 is not supported. 209 */ 210 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 211 }; 212 213 static inline enum ufs_dev_pwr_mode 214 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 215 { 216 return ufs_pm_lvl_states[lvl].dev_state; 217 } 218 219 static inline enum uic_link_state 220 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 221 { 222 return ufs_pm_lvl_states[lvl].link_state; 223 } 224 225 static inline enum ufs_pm_level 226 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 227 enum uic_link_state link_state) 228 { 229 enum ufs_pm_level lvl; 230 231 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 232 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 233 (ufs_pm_lvl_states[lvl].link_state == link_state)) 234 return lvl; 235 } 236 237 /* if no match found, return the level 0 */ 238 return UFS_PM_LVL_0; 239 } 240 241 static bool ufshcd_is_ufs_dev_busy(struct ufs_hba *hba) 242 { 243 return (hba->clk_gating.active_reqs || hba->outstanding_reqs || hba->outstanding_tasks || 244 hba->active_uic_cmd || hba->uic_async_done); 245 } 246 247 static const struct ufs_dev_quirk ufs_fixups[] = { 248 /* UFS cards deviations table */ 249 { .wmanufacturerid = UFS_VENDOR_MICRON, 250 .model = UFS_ANY_MODEL, 251 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 252 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 253 .model = UFS_ANY_MODEL, 254 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 255 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 256 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 257 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 258 .model = UFS_ANY_MODEL, 259 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 260 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 261 .model = "hB8aL1" /*H28U62301AMR*/, 262 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 263 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 264 .model = UFS_ANY_MODEL, 265 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 266 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 267 .model = "THGLF2G9C8KBADG", 268 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 269 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 270 .model = "THGLF2G9D8KBADG", 271 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 272 {} 273 }; 274 275 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 276 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 277 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 278 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 279 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 280 static void ufshcd_hba_exit(struct ufs_hba *hba); 281 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 282 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 283 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 284 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 285 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 286 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 287 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 288 bool scale_up); 289 static irqreturn_t ufshcd_intr(int irq, void *__hba); 290 static int ufshcd_change_power_mode(struct ufs_hba *hba, 291 struct ufs_pa_layer_attr *pwr_mode); 292 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 293 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 294 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 295 struct ufs_vreg *vreg); 296 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 297 bool enable); 298 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 299 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 300 301 void ufshcd_enable_irq(struct ufs_hba *hba) 302 { 303 if (!hba->is_irq_enabled) { 304 enable_irq(hba->irq); 305 hba->is_irq_enabled = true; 306 } 307 } 308 EXPORT_SYMBOL_GPL(ufshcd_enable_irq); 309 310 void ufshcd_disable_irq(struct ufs_hba *hba) 311 { 312 if (hba->is_irq_enabled) { 313 disable_irq(hba->irq); 314 hba->is_irq_enabled = false; 315 } 316 } 317 EXPORT_SYMBOL_GPL(ufshcd_disable_irq); 318 319 static void ufshcd_configure_wb(struct ufs_hba *hba) 320 { 321 if (!ufshcd_is_wb_allowed(hba)) 322 return; 323 324 ufshcd_wb_toggle(hba, true); 325 326 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 327 328 if (ufshcd_is_wb_buf_flush_allowed(hba)) 329 ufshcd_wb_toggle_buf_flush(hba, true); 330 } 331 332 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba) 333 { 334 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt)) 335 scsi_unblock_requests(hba->host); 336 } 337 338 static void ufshcd_scsi_block_requests(struct ufs_hba *hba) 339 { 340 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1) 341 scsi_block_requests(hba->host); 342 } 343 344 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 345 enum ufs_trace_str_t str_t) 346 { 347 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 348 struct utp_upiu_header *header; 349 350 if (!trace_ufshcd_upiu_enabled()) 351 return; 352 353 if (str_t == UFS_CMD_SEND) 354 header = &rq->header; 355 else 356 header = &hba->lrb[tag].ucd_rsp_ptr->header; 357 358 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 359 UFS_TSF_CDB); 360 } 361 362 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 363 enum ufs_trace_str_t str_t, 364 struct utp_upiu_req *rq_rsp) 365 { 366 if (!trace_ufshcd_upiu_enabled()) 367 return; 368 369 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 370 &rq_rsp->qr, UFS_TSF_OSF); 371 } 372 373 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 374 enum ufs_trace_str_t str_t) 375 { 376 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 377 378 if (!trace_ufshcd_upiu_enabled()) 379 return; 380 381 if (str_t == UFS_TM_SEND) 382 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 383 &descp->upiu_req.req_header, 384 &descp->upiu_req.input_param1, 385 UFS_TSF_TM_INPUT); 386 else 387 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 388 &descp->upiu_rsp.rsp_header, 389 &descp->upiu_rsp.output_param1, 390 UFS_TSF_TM_OUTPUT); 391 } 392 393 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 394 const struct uic_command *ucmd, 395 enum ufs_trace_str_t str_t) 396 { 397 u32 cmd; 398 399 if (!trace_ufshcd_uic_command_enabled()) 400 return; 401 402 if (str_t == UFS_CMD_SEND) 403 cmd = ucmd->command; 404 else 405 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 406 407 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 408 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 409 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 410 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 411 } 412 413 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 414 enum ufs_trace_str_t str_t) 415 { 416 u64 lba = 0; 417 u8 opcode = 0, group_id = 0; 418 u32 doorbell = 0; 419 u32 intr; 420 int hwq_id = -1; 421 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 422 struct scsi_cmnd *cmd = lrbp->cmd; 423 struct request *rq = scsi_cmd_to_rq(cmd); 424 int transfer_len = -1; 425 426 if (!cmd) 427 return; 428 429 /* trace UPIU also */ 430 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 431 if (!trace_ufshcd_command_enabled()) 432 return; 433 434 opcode = cmd->cmnd[0]; 435 436 if (opcode == READ_10 || opcode == WRITE_10) { 437 /* 438 * Currently we only fully trace read(10) and write(10) commands 439 */ 440 transfer_len = 441 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 442 lba = scsi_get_lba(cmd); 443 if (opcode == WRITE_10) 444 group_id = lrbp->cmd->cmnd[6]; 445 } else if (opcode == UNMAP) { 446 /* 447 * The number of Bytes to be unmapped beginning with the lba. 448 */ 449 transfer_len = blk_rq_bytes(rq); 450 lba = scsi_get_lba(cmd); 451 } 452 453 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 454 455 if (is_mcq_enabled(hba)) { 456 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 457 458 hwq_id = hwq->id; 459 } else { 460 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 461 } 462 trace_ufshcd_command(cmd->device, str_t, tag, doorbell, hwq_id, 463 transfer_len, intr, lba, opcode, group_id); 464 } 465 466 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 467 { 468 struct ufs_clk_info *clki; 469 struct list_head *head = &hba->clk_list_head; 470 471 if (list_empty(head)) 472 return; 473 474 list_for_each_entry(clki, head, list) { 475 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 476 clki->max_freq) 477 dev_err(hba->dev, "clk: %s, rate: %u\n", 478 clki->name, clki->curr_freq); 479 } 480 } 481 482 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 483 const char *err_name) 484 { 485 int i; 486 bool found = false; 487 const struct ufs_event_hist *e; 488 489 if (id >= UFS_EVT_CNT) 490 return; 491 492 e = &hba->ufs_stats.event[id]; 493 494 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 495 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 496 497 if (e->tstamp[p] == 0) 498 continue; 499 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 500 e->val[p], div_u64(e->tstamp[p], 1000)); 501 found = true; 502 } 503 504 if (!found) 505 dev_err(hba->dev, "No record of %s\n", err_name); 506 else 507 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 508 } 509 510 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 511 { 512 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 513 514 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 515 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 516 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 517 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 518 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 519 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 520 "auto_hibern8_err"); 521 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 522 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 523 "link_startup_fail"); 524 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 525 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 526 "suspend_fail"); 527 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 528 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 529 "wlun suspend_fail"); 530 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 531 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 532 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 533 534 ufshcd_vops_dbg_register_dump(hba); 535 } 536 537 static 538 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 539 { 540 const struct ufshcd_lrb *lrbp; 541 int prdt_length; 542 543 lrbp = &hba->lrb[tag]; 544 545 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 546 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 547 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 548 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 549 dev_err(hba->dev, 550 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 551 tag, (u64)lrbp->utrd_dma_addr); 552 553 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 554 sizeof(struct utp_transfer_req_desc)); 555 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 556 (u64)lrbp->ucd_req_dma_addr); 557 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 558 sizeof(struct utp_upiu_req)); 559 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 560 (u64)lrbp->ucd_rsp_dma_addr); 561 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 562 sizeof(struct utp_upiu_rsp)); 563 564 prdt_length = le16_to_cpu( 565 lrbp->utr_descriptor_ptr->prd_table_length); 566 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 567 prdt_length /= ufshcd_sg_entry_size(hba); 568 569 dev_err(hba->dev, 570 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 571 tag, prdt_length, 572 (u64)lrbp->ucd_prdt_dma_addr); 573 574 if (pr_prdt) 575 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 576 ufshcd_sg_entry_size(hba) * prdt_length); 577 } 578 579 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 580 { 581 struct scsi_device *sdev = req->q->queuedata; 582 struct Scsi_Host *shost = sdev->host; 583 struct ufs_hba *hba = shost_priv(shost); 584 585 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 586 587 return true; 588 } 589 590 /** 591 * ufshcd_print_trs_all - print trs for all started requests. 592 * @hba: per-adapter instance. 593 * @pr_prdt: need to print prdt or not. 594 */ 595 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 596 { 597 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 598 } 599 600 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 601 { 602 int tag; 603 604 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 605 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 606 607 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 608 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 609 } 610 } 611 612 static void ufshcd_print_host_state(struct ufs_hba *hba) 613 { 614 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 615 616 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 617 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 618 hba->outstanding_reqs, hba->outstanding_tasks); 619 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 620 hba->saved_err, hba->saved_uic_err); 621 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 622 hba->curr_dev_pwr_mode, hba->uic_link_state); 623 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 624 hba->pm_op_in_progress, hba->is_sys_suspended); 625 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 626 hba->auto_bkops_enabled, hba->host->host_self_blocked); 627 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 628 dev_err(hba->dev, 629 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 630 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 631 hba->ufs_stats.hibern8_exit_cnt); 632 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 633 div_u64(hba->ufs_stats.last_intr_ts, 1000), 634 hba->ufs_stats.last_intr_status); 635 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 636 hba->eh_flags, hba->req_abort_count); 637 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 638 hba->ufs_version, hba->capabilities, hba->caps); 639 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 640 hba->dev_quirks); 641 if (sdev_ufs) 642 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 643 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 644 645 ufshcd_print_clk_freqs(hba); 646 } 647 648 /** 649 * ufshcd_print_pwr_info - print power params as saved in hba 650 * power info 651 * @hba: per-adapter instance 652 */ 653 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 654 { 655 static const char * const names[] = { 656 "INVALID MODE", 657 "FAST MODE", 658 "SLOW_MODE", 659 "INVALID MODE", 660 "FASTAUTO_MODE", 661 "SLOWAUTO_MODE", 662 "INVALID MODE", 663 }; 664 665 /* 666 * Using dev_dbg to avoid messages during runtime PM to avoid 667 * never-ending cycles of messages written back to storage by user space 668 * causing runtime resume, causing more messages and so on. 669 */ 670 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 671 __func__, 672 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 673 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 674 names[hba->pwr_info.pwr_rx], 675 names[hba->pwr_info.pwr_tx], 676 hba->pwr_info.hs_rate); 677 } 678 679 static void ufshcd_device_reset(struct ufs_hba *hba) 680 { 681 int err; 682 683 err = ufshcd_vops_device_reset(hba); 684 685 if (!err) { 686 ufshcd_set_ufs_dev_active(hba); 687 if (ufshcd_is_wb_allowed(hba)) { 688 hba->dev_info.wb_enabled = false; 689 hba->dev_info.wb_buf_flush_enabled = false; 690 } 691 if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 692 hba->dev_info.rtc_time_baseline = 0; 693 } 694 if (err != -EOPNOTSUPP) 695 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 696 } 697 698 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 699 { 700 if (!us) 701 return; 702 703 if (us < 10) 704 udelay(us); 705 else 706 usleep_range(us, us + tolerance); 707 } 708 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 709 710 /** 711 * ufshcd_wait_for_register - wait for register value to change 712 * @hba: per-adapter interface 713 * @reg: mmio register offset 714 * @mask: mask to apply to the read register value 715 * @val: value to wait for 716 * @interval_us: polling interval in microseconds 717 * @timeout_ms: timeout in milliseconds 718 * 719 * Return: -ETIMEDOUT on error, zero on success. 720 */ 721 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 722 u32 val, unsigned long interval_us, 723 unsigned long timeout_ms) 724 { 725 int err = 0; 726 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 727 728 /* ignore bits that we don't intend to wait on */ 729 val = val & mask; 730 731 while ((ufshcd_readl(hba, reg) & mask) != val) { 732 usleep_range(interval_us, interval_us + 50); 733 if (time_after(jiffies, timeout)) { 734 if ((ufshcd_readl(hba, reg) & mask) != val) 735 err = -ETIMEDOUT; 736 break; 737 } 738 } 739 740 return err; 741 } 742 743 /** 744 * ufshcd_get_intr_mask - Get the interrupt bit mask 745 * @hba: Pointer to adapter instance 746 * 747 * Return: interrupt bit mask per version 748 */ 749 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 750 { 751 if (hba->ufs_version <= ufshci_version(2, 0)) 752 return INTERRUPT_MASK_ALL_VER_11; 753 754 return INTERRUPT_MASK_ALL_VER_21; 755 } 756 757 /** 758 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 759 * @hba: Pointer to adapter instance 760 * 761 * Return: UFSHCI version supported by the controller 762 */ 763 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 764 { 765 u32 ufshci_ver; 766 767 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 768 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 769 else 770 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 771 772 /* 773 * UFSHCI v1.x uses a different version scheme, in order 774 * to allow the use of comparisons with the ufshci_version 775 * function, we convert it to the same scheme as ufs 2.0+. 776 */ 777 if (ufshci_ver & 0x00010000) 778 return ufshci_version(1, ufshci_ver & 0x00000100); 779 780 return ufshci_ver; 781 } 782 783 /** 784 * ufshcd_is_device_present - Check if any device connected to 785 * the host controller 786 * @hba: pointer to adapter instance 787 * 788 * Return: true if device present, false if no device detected 789 */ 790 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 791 { 792 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 793 } 794 795 /** 796 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 797 * @lrbp: pointer to local command reference block 798 * @cqe: pointer to the completion queue entry 799 * 800 * This function is used to get the OCS field from UTRD 801 * 802 * Return: the OCS field in the UTRD. 803 */ 804 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 805 struct cq_entry *cqe) 806 { 807 if (cqe) 808 return le32_to_cpu(cqe->status) & MASK_OCS; 809 810 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 811 } 812 813 /** 814 * ufshcd_utrl_clear() - Clear requests from the controller request list. 815 * @hba: per adapter instance 816 * @mask: mask with one bit set for each request to be cleared 817 */ 818 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 819 { 820 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 821 mask = ~mask; 822 /* 823 * From the UFSHCI specification: "UTP Transfer Request List CLear 824 * Register (UTRLCLR): This field is bit significant. Each bit 825 * corresponds to a slot in the UTP Transfer Request List, where bit 0 826 * corresponds to request slot 0. A bit in this field is set to ‘0’ 827 * by host software to indicate to the host controller that a transfer 828 * request slot is cleared. The host controller 829 * shall free up any resources associated to the request slot 830 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 831 * host software indicates no change to request slots by setting the 832 * associated bits in this field to ‘1’. Bits in this field shall only 833 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 834 */ 835 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 836 } 837 838 /** 839 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 840 * @hba: per adapter instance 841 * @pos: position of the bit to be cleared 842 */ 843 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 844 { 845 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 846 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 847 else 848 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 849 } 850 851 /** 852 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 853 * @reg: Register value of host controller status 854 * 855 * Return: 0 on success; a positive value if failed. 856 */ 857 static inline int ufshcd_get_lists_status(u32 reg) 858 { 859 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 860 } 861 862 /** 863 * ufshcd_get_uic_cmd_result - Get the UIC command result 864 * @hba: Pointer to adapter instance 865 * 866 * This function gets the result of UIC command completion 867 * 868 * Return: 0 on success; non-zero value on error. 869 */ 870 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 871 { 872 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 873 MASK_UIC_COMMAND_RESULT; 874 } 875 876 /** 877 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 878 * @hba: Pointer to adapter instance 879 * 880 * This function gets UIC command argument3 881 * 882 * Return: 0 on success; non-zero value on error. 883 */ 884 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 885 { 886 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 887 } 888 889 /** 890 * ufshcd_get_req_rsp - returns the TR response transaction type 891 * @ucd_rsp_ptr: pointer to response UPIU 892 * 893 * Return: UPIU type. 894 */ 895 static inline enum upiu_response_transaction 896 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 897 { 898 return ucd_rsp_ptr->header.transaction_code; 899 } 900 901 /** 902 * ufshcd_is_exception_event - Check if the device raised an exception event 903 * @ucd_rsp_ptr: pointer to response UPIU 904 * 905 * The function checks if the device raised an exception event indicated in 906 * the Device Information field of response UPIU. 907 * 908 * Return: true if exception is raised, false otherwise. 909 */ 910 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 911 { 912 return ucd_rsp_ptr->header.device_information & 1; 913 } 914 915 /** 916 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 917 * @hba: per adapter instance 918 */ 919 static inline void 920 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 921 { 922 ufshcd_writel(hba, INT_AGGR_ENABLE | 923 INT_AGGR_COUNTER_AND_TIMER_RESET, 924 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 925 } 926 927 /** 928 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 929 * @hba: per adapter instance 930 * @cnt: Interrupt aggregation counter threshold 931 * @tmout: Interrupt aggregation timeout value 932 */ 933 static inline void 934 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 935 { 936 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 937 INT_AGGR_COUNTER_THLD_VAL(cnt) | 938 INT_AGGR_TIMEOUT_VAL(tmout), 939 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 940 } 941 942 /** 943 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 944 * @hba: per adapter instance 945 */ 946 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 947 { 948 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 949 } 950 951 /** 952 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 953 * When run-stop registers are set to 1, it indicates the 954 * host controller that it can process the requests 955 * @hba: per adapter instance 956 */ 957 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 958 { 959 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 960 REG_UTP_TASK_REQ_LIST_RUN_STOP); 961 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 962 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 963 } 964 965 /** 966 * ufshcd_hba_start - Start controller initialization sequence 967 * @hba: per adapter instance 968 */ 969 static inline void ufshcd_hba_start(struct ufs_hba *hba) 970 { 971 u32 val = CONTROLLER_ENABLE; 972 973 if (ufshcd_crypto_enable(hba)) 974 val |= CRYPTO_GENERAL_ENABLE; 975 976 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 977 } 978 979 /** 980 * ufshcd_is_hba_active - Get controller state 981 * @hba: per adapter instance 982 * 983 * Return: true if and only if the controller is active. 984 */ 985 bool ufshcd_is_hba_active(struct ufs_hba *hba) 986 { 987 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 988 } 989 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 990 991 /** 992 * ufshcd_pm_qos_init - initialize PM QoS request 993 * @hba: per adapter instance 994 */ 995 void ufshcd_pm_qos_init(struct ufs_hba *hba) 996 { 997 998 if (hba->pm_qos_enabled) 999 return; 1000 1001 cpu_latency_qos_add_request(&hba->pm_qos_req, PM_QOS_DEFAULT_VALUE); 1002 1003 if (cpu_latency_qos_request_active(&hba->pm_qos_req)) 1004 hba->pm_qos_enabled = true; 1005 } 1006 1007 /** 1008 * ufshcd_pm_qos_exit - remove request from PM QoS 1009 * @hba: per adapter instance 1010 */ 1011 void ufshcd_pm_qos_exit(struct ufs_hba *hba) 1012 { 1013 if (!hba->pm_qos_enabled) 1014 return; 1015 1016 cpu_latency_qos_remove_request(&hba->pm_qos_req); 1017 hba->pm_qos_enabled = false; 1018 } 1019 1020 /** 1021 * ufshcd_pm_qos_update - update PM QoS request 1022 * @hba: per adapter instance 1023 * @on: If True, vote for perf PM QoS mode otherwise power save mode 1024 */ 1025 static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) 1026 { 1027 if (!hba->pm_qos_enabled) 1028 return; 1029 1030 cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE); 1031 } 1032 1033 /** 1034 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1035 * @hba: per adapter instance 1036 * @scale_up: If True, set max possible frequency othewise set low frequency 1037 * 1038 * Return: 0 if successful; < 0 upon failure. 1039 */ 1040 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1041 { 1042 int ret = 0; 1043 struct ufs_clk_info *clki; 1044 struct list_head *head = &hba->clk_list_head; 1045 1046 if (list_empty(head)) 1047 goto out; 1048 1049 list_for_each_entry(clki, head, list) { 1050 if (!IS_ERR_OR_NULL(clki->clk)) { 1051 if (scale_up && clki->max_freq) { 1052 if (clki->curr_freq == clki->max_freq) 1053 continue; 1054 1055 ret = clk_set_rate(clki->clk, clki->max_freq); 1056 if (ret) { 1057 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1058 __func__, clki->name, 1059 clki->max_freq, ret); 1060 break; 1061 } 1062 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1063 "scaled up", clki->name, 1064 clki->curr_freq, 1065 clki->max_freq); 1066 1067 clki->curr_freq = clki->max_freq; 1068 1069 } else if (!scale_up && clki->min_freq) { 1070 if (clki->curr_freq == clki->min_freq) 1071 continue; 1072 1073 ret = clk_set_rate(clki->clk, clki->min_freq); 1074 if (ret) { 1075 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1076 __func__, clki->name, 1077 clki->min_freq, ret); 1078 break; 1079 } 1080 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1081 "scaled down", clki->name, 1082 clki->curr_freq, 1083 clki->min_freq); 1084 clki->curr_freq = clki->min_freq; 1085 } 1086 } 1087 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1088 clki->name, clk_get_rate(clki->clk)); 1089 } 1090 1091 out: 1092 return ret; 1093 } 1094 1095 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1096 struct dev_pm_opp *opp, void *data, 1097 bool scaling_down) 1098 { 1099 struct ufs_hba *hba = dev_get_drvdata(dev); 1100 struct list_head *head = &hba->clk_list_head; 1101 struct ufs_clk_info *clki; 1102 unsigned long freq; 1103 u8 idx = 0; 1104 int ret; 1105 1106 list_for_each_entry(clki, head, list) { 1107 if (!IS_ERR_OR_NULL(clki->clk)) { 1108 freq = dev_pm_opp_get_freq_indexed(opp, idx++); 1109 1110 /* Do not set rate for clocks having frequency as 0 */ 1111 if (!freq) 1112 continue; 1113 1114 ret = clk_set_rate(clki->clk, freq); 1115 if (ret) { 1116 dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n", 1117 __func__, clki->name, freq, ret); 1118 return ret; 1119 } 1120 1121 trace_ufshcd_clk_scaling(dev_name(dev), 1122 (scaling_down ? "scaled down" : "scaled up"), 1123 clki->name, hba->clk_scaling.target_freq, freq); 1124 } 1125 } 1126 1127 return 0; 1128 } 1129 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks); 1130 1131 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) 1132 { 1133 struct dev_pm_opp *opp; 1134 int ret; 1135 1136 opp = dev_pm_opp_find_freq_floor_indexed(hba->dev, 1137 &freq, 0); 1138 if (IS_ERR(opp)) 1139 return PTR_ERR(opp); 1140 1141 ret = dev_pm_opp_set_opp(hba->dev, opp); 1142 dev_pm_opp_put(opp); 1143 1144 return ret; 1145 } 1146 1147 /** 1148 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1149 * @hba: per adapter instance 1150 * @freq: frequency to scale 1151 * @scale_up: True if scaling up and false if scaling down 1152 * 1153 * Return: 0 if successful; < 0 upon failure. 1154 */ 1155 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 1156 bool scale_up) 1157 { 1158 int ret = 0; 1159 ktime_t start = ktime_get(); 1160 1161 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1162 if (ret) 1163 goto out; 1164 1165 if (hba->use_pm_opp) 1166 ret = ufshcd_opp_set_rate(hba, freq); 1167 else 1168 ret = ufshcd_set_clk_freq(hba, scale_up); 1169 if (ret) 1170 goto out; 1171 1172 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1173 if (ret) { 1174 if (hba->use_pm_opp) 1175 ufshcd_opp_set_rate(hba, 1176 hba->devfreq->previous_freq); 1177 else 1178 ufshcd_set_clk_freq(hba, !scale_up); 1179 goto out; 1180 } 1181 1182 ufshcd_pm_qos_update(hba, scale_up); 1183 1184 out: 1185 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1186 (scale_up ? "up" : "down"), 1187 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1188 return ret; 1189 } 1190 1191 /** 1192 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1193 * @hba: per adapter instance 1194 * @freq: frequency to scale 1195 * @scale_up: True if scaling up and false if scaling down 1196 * 1197 * Return: true if scaling is required, false otherwise. 1198 */ 1199 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1200 unsigned long freq, bool scale_up) 1201 { 1202 struct ufs_clk_info *clki; 1203 struct list_head *head = &hba->clk_list_head; 1204 1205 if (list_empty(head)) 1206 return false; 1207 1208 if (hba->use_pm_opp) 1209 return freq != hba->clk_scaling.target_freq; 1210 1211 list_for_each_entry(clki, head, list) { 1212 if (!IS_ERR_OR_NULL(clki->clk)) { 1213 if (scale_up && clki->max_freq) { 1214 if (clki->curr_freq == clki->max_freq) 1215 continue; 1216 return true; 1217 } else if (!scale_up && clki->min_freq) { 1218 if (clki->curr_freq == clki->min_freq) 1219 continue; 1220 return true; 1221 } 1222 } 1223 } 1224 1225 return false; 1226 } 1227 1228 /* 1229 * Determine the number of pending commands by counting the bits in the SCSI 1230 * device budget maps. This approach has been selected because a bit is set in 1231 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1232 * flag. The host_self_blocked flag can be modified by calling 1233 * scsi_block_requests() or scsi_unblock_requests(). 1234 */ 1235 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1236 { 1237 const struct scsi_device *sdev; 1238 u32 pending = 0; 1239 1240 lockdep_assert_held(hba->host->host_lock); 1241 __shost_for_each_device(sdev, hba->host) 1242 pending += sbitmap_weight(&sdev->budget_map); 1243 1244 return pending; 1245 } 1246 1247 /* 1248 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1249 * has expired. 1250 * 1251 * Return: 0 upon success; -EBUSY upon timeout. 1252 */ 1253 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1254 u64 wait_timeout_us) 1255 { 1256 unsigned long flags; 1257 int ret = 0; 1258 u32 tm_doorbell; 1259 u32 tr_pending; 1260 bool timeout = false, do_last_check = false; 1261 ktime_t start; 1262 1263 ufshcd_hold(hba); 1264 spin_lock_irqsave(hba->host->host_lock, flags); 1265 /* 1266 * Wait for all the outstanding tasks/transfer requests. 1267 * Verify by checking the doorbell registers are clear. 1268 */ 1269 start = ktime_get(); 1270 do { 1271 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1272 ret = -EBUSY; 1273 goto out; 1274 } 1275 1276 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1277 tr_pending = ufshcd_pending_cmds(hba); 1278 if (!tm_doorbell && !tr_pending) { 1279 timeout = false; 1280 break; 1281 } else if (do_last_check) { 1282 break; 1283 } 1284 1285 spin_unlock_irqrestore(hba->host->host_lock, flags); 1286 io_schedule_timeout(msecs_to_jiffies(20)); 1287 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1288 wait_timeout_us) { 1289 timeout = true; 1290 /* 1291 * We might have scheduled out for long time so make 1292 * sure to check if doorbells are cleared by this time 1293 * or not. 1294 */ 1295 do_last_check = true; 1296 } 1297 spin_lock_irqsave(hba->host->host_lock, flags); 1298 } while (tm_doorbell || tr_pending); 1299 1300 if (timeout) { 1301 dev_err(hba->dev, 1302 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1303 __func__, tm_doorbell, tr_pending); 1304 ret = -EBUSY; 1305 } 1306 out: 1307 spin_unlock_irqrestore(hba->host->host_lock, flags); 1308 ufshcd_release(hba); 1309 return ret; 1310 } 1311 1312 /** 1313 * ufshcd_scale_gear - scale up/down UFS gear 1314 * @hba: per adapter instance 1315 * @scale_up: True for scaling up gear and false for scaling down 1316 * 1317 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1318 * non-zero for any other errors. 1319 */ 1320 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1321 { 1322 int ret = 0; 1323 struct ufs_pa_layer_attr new_pwr_info; 1324 1325 if (scale_up) { 1326 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1327 sizeof(struct ufs_pa_layer_attr)); 1328 } else { 1329 memcpy(&new_pwr_info, &hba->pwr_info, 1330 sizeof(struct ufs_pa_layer_attr)); 1331 1332 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1333 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1334 /* save the current power mode */ 1335 memcpy(&hba->clk_scaling.saved_pwr_info, 1336 &hba->pwr_info, 1337 sizeof(struct ufs_pa_layer_attr)); 1338 1339 /* scale down gear */ 1340 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1341 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1342 } 1343 } 1344 1345 /* check if the power mode needs to be changed or not? */ 1346 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1347 if (ret) 1348 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1349 __func__, ret, 1350 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1351 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1352 1353 return ret; 1354 } 1355 1356 /* 1357 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1358 * has expired. 1359 * 1360 * Return: 0 upon success; -EBUSY upon timeout. 1361 */ 1362 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1363 { 1364 int ret = 0; 1365 /* 1366 * make sure that there are no outstanding requests when 1367 * clock scaling is in progress 1368 */ 1369 ufshcd_scsi_block_requests(hba); 1370 mutex_lock(&hba->wb_mutex); 1371 down_write(&hba->clk_scaling_lock); 1372 1373 if (!hba->clk_scaling.is_allowed || 1374 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1375 ret = -EBUSY; 1376 up_write(&hba->clk_scaling_lock); 1377 mutex_unlock(&hba->wb_mutex); 1378 ufshcd_scsi_unblock_requests(hba); 1379 goto out; 1380 } 1381 1382 /* let's not get into low power until clock scaling is completed */ 1383 ufshcd_hold(hba); 1384 1385 out: 1386 return ret; 1387 } 1388 1389 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1390 { 1391 up_write(&hba->clk_scaling_lock); 1392 1393 /* Enable Write Booster if we have scaled up else disable it */ 1394 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1395 ufshcd_wb_toggle(hba, scale_up); 1396 1397 mutex_unlock(&hba->wb_mutex); 1398 1399 ufshcd_scsi_unblock_requests(hba); 1400 ufshcd_release(hba); 1401 } 1402 1403 /** 1404 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1405 * @hba: per adapter instance 1406 * @freq: frequency to scale 1407 * @scale_up: True for scaling up and false for scalin down 1408 * 1409 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1410 * for any other errors. 1411 */ 1412 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, 1413 bool scale_up) 1414 { 1415 int ret = 0; 1416 1417 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1418 if (ret) 1419 return ret; 1420 1421 /* scale down the gear before scaling down clocks */ 1422 if (!scale_up) { 1423 ret = ufshcd_scale_gear(hba, false); 1424 if (ret) 1425 goto out_unprepare; 1426 } 1427 1428 ret = ufshcd_scale_clks(hba, freq, scale_up); 1429 if (ret) { 1430 if (!scale_up) 1431 ufshcd_scale_gear(hba, true); 1432 goto out_unprepare; 1433 } 1434 1435 /* scale up the gear after scaling up clocks */ 1436 if (scale_up) { 1437 ret = ufshcd_scale_gear(hba, true); 1438 if (ret) { 1439 ufshcd_scale_clks(hba, hba->devfreq->previous_freq, 1440 false); 1441 goto out_unprepare; 1442 } 1443 } 1444 1445 out_unprepare: 1446 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1447 return ret; 1448 } 1449 1450 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1451 { 1452 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1453 clk_scaling.suspend_work); 1454 unsigned long irq_flags; 1455 1456 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1457 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1458 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1459 return; 1460 } 1461 hba->clk_scaling.is_suspended = true; 1462 hba->clk_scaling.window_start_t = 0; 1463 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1464 1465 devfreq_suspend_device(hba->devfreq); 1466 } 1467 1468 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1469 { 1470 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1471 clk_scaling.resume_work); 1472 unsigned long irq_flags; 1473 1474 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1475 if (!hba->clk_scaling.is_suspended) { 1476 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1477 return; 1478 } 1479 hba->clk_scaling.is_suspended = false; 1480 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1481 1482 devfreq_resume_device(hba->devfreq); 1483 } 1484 1485 static int ufshcd_devfreq_target(struct device *dev, 1486 unsigned long *freq, u32 flags) 1487 { 1488 int ret = 0; 1489 struct ufs_hba *hba = dev_get_drvdata(dev); 1490 ktime_t start; 1491 bool scale_up = false, sched_clk_scaling_suspend_work = false; 1492 struct list_head *clk_list = &hba->clk_list_head; 1493 struct ufs_clk_info *clki; 1494 unsigned long irq_flags; 1495 1496 if (!ufshcd_is_clkscaling_supported(hba)) 1497 return -EINVAL; 1498 1499 if (hba->use_pm_opp) { 1500 struct dev_pm_opp *opp; 1501 1502 /* Get the recommended frequency from OPP framework */ 1503 opp = devfreq_recommended_opp(dev, freq, flags); 1504 if (IS_ERR(opp)) 1505 return PTR_ERR(opp); 1506 1507 dev_pm_opp_put(opp); 1508 } else { 1509 /* Override with the closest supported frequency */ 1510 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, 1511 list); 1512 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1513 } 1514 1515 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1516 if (ufshcd_eh_in_progress(hba)) { 1517 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1518 return 0; 1519 } 1520 1521 /* Skip scaling clock when clock scaling is suspended */ 1522 if (hba->clk_scaling.is_suspended) { 1523 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1524 dev_warn(hba->dev, "clock scaling is suspended, skip"); 1525 return 0; 1526 } 1527 1528 if (!hba->clk_scaling.active_reqs) 1529 sched_clk_scaling_suspend_work = true; 1530 1531 if (list_empty(clk_list)) { 1532 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1533 goto out; 1534 } 1535 1536 /* Decide based on the target or rounded-off frequency and update */ 1537 if (hba->use_pm_opp) 1538 scale_up = *freq > hba->clk_scaling.target_freq; 1539 else 1540 scale_up = *freq == clki->max_freq; 1541 1542 if (!hba->use_pm_opp && !scale_up) 1543 *freq = clki->min_freq; 1544 1545 /* Update the frequency */ 1546 if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) { 1547 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1548 ret = 0; 1549 goto out; /* no state change required */ 1550 } 1551 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1552 1553 start = ktime_get(); 1554 ret = ufshcd_devfreq_scale(hba, *freq, scale_up); 1555 if (!ret) 1556 hba->clk_scaling.target_freq = *freq; 1557 1558 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1559 (scale_up ? "up" : "down"), 1560 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1561 1562 out: 1563 if (sched_clk_scaling_suspend_work && !scale_up) 1564 queue_work(hba->clk_scaling.workq, 1565 &hba->clk_scaling.suspend_work); 1566 1567 return ret; 1568 } 1569 1570 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1571 struct devfreq_dev_status *stat) 1572 { 1573 struct ufs_hba *hba = dev_get_drvdata(dev); 1574 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1575 unsigned long flags; 1576 ktime_t curr_t; 1577 1578 if (!ufshcd_is_clkscaling_supported(hba)) 1579 return -EINVAL; 1580 1581 memset(stat, 0, sizeof(*stat)); 1582 1583 spin_lock_irqsave(hba->host->host_lock, flags); 1584 curr_t = ktime_get(); 1585 if (!scaling->window_start_t) 1586 goto start_window; 1587 1588 /* 1589 * If current frequency is 0, then the ondemand governor considers 1590 * there's no initial frequency set. And it always requests to set 1591 * to max. frequency. 1592 */ 1593 if (hba->use_pm_opp) { 1594 stat->current_frequency = hba->clk_scaling.target_freq; 1595 } else { 1596 struct list_head *clk_list = &hba->clk_list_head; 1597 struct ufs_clk_info *clki; 1598 1599 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1600 stat->current_frequency = clki->curr_freq; 1601 } 1602 1603 if (scaling->is_busy_started) 1604 scaling->tot_busy_t += ktime_us_delta(curr_t, 1605 scaling->busy_start_t); 1606 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1607 stat->busy_time = scaling->tot_busy_t; 1608 start_window: 1609 scaling->window_start_t = curr_t; 1610 scaling->tot_busy_t = 0; 1611 1612 if (scaling->active_reqs) { 1613 scaling->busy_start_t = curr_t; 1614 scaling->is_busy_started = true; 1615 } else { 1616 scaling->busy_start_t = 0; 1617 scaling->is_busy_started = false; 1618 } 1619 spin_unlock_irqrestore(hba->host->host_lock, flags); 1620 return 0; 1621 } 1622 1623 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1624 { 1625 struct list_head *clk_list = &hba->clk_list_head; 1626 struct ufs_clk_info *clki; 1627 struct devfreq *devfreq; 1628 int ret; 1629 1630 /* Skip devfreq if we don't have any clocks in the list */ 1631 if (list_empty(clk_list)) 1632 return 0; 1633 1634 if (!hba->use_pm_opp) { 1635 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1636 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1637 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1638 } 1639 1640 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1641 &hba->vps->ondemand_data); 1642 devfreq = devfreq_add_device(hba->dev, 1643 &hba->vps->devfreq_profile, 1644 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1645 &hba->vps->ondemand_data); 1646 if (IS_ERR(devfreq)) { 1647 ret = PTR_ERR(devfreq); 1648 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1649 1650 if (!hba->use_pm_opp) { 1651 dev_pm_opp_remove(hba->dev, clki->min_freq); 1652 dev_pm_opp_remove(hba->dev, clki->max_freq); 1653 } 1654 return ret; 1655 } 1656 1657 hba->devfreq = devfreq; 1658 1659 return 0; 1660 } 1661 1662 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1663 { 1664 struct list_head *clk_list = &hba->clk_list_head; 1665 1666 if (!hba->devfreq) 1667 return; 1668 1669 devfreq_remove_device(hba->devfreq); 1670 hba->devfreq = NULL; 1671 1672 if (!hba->use_pm_opp) { 1673 struct ufs_clk_info *clki; 1674 1675 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1676 dev_pm_opp_remove(hba->dev, clki->min_freq); 1677 dev_pm_opp_remove(hba->dev, clki->max_freq); 1678 } 1679 } 1680 1681 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1682 { 1683 unsigned long flags; 1684 bool suspend = false; 1685 1686 cancel_work_sync(&hba->clk_scaling.suspend_work); 1687 cancel_work_sync(&hba->clk_scaling.resume_work); 1688 1689 spin_lock_irqsave(hba->host->host_lock, flags); 1690 if (!hba->clk_scaling.is_suspended) { 1691 suspend = true; 1692 hba->clk_scaling.is_suspended = true; 1693 hba->clk_scaling.window_start_t = 0; 1694 } 1695 spin_unlock_irqrestore(hba->host->host_lock, flags); 1696 1697 if (suspend) 1698 devfreq_suspend_device(hba->devfreq); 1699 } 1700 1701 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1702 { 1703 unsigned long flags; 1704 bool resume = false; 1705 1706 spin_lock_irqsave(hba->host->host_lock, flags); 1707 if (hba->clk_scaling.is_suspended) { 1708 resume = true; 1709 hba->clk_scaling.is_suspended = false; 1710 } 1711 spin_unlock_irqrestore(hba->host->host_lock, flags); 1712 1713 if (resume) 1714 devfreq_resume_device(hba->devfreq); 1715 } 1716 1717 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1718 struct device_attribute *attr, char *buf) 1719 { 1720 struct ufs_hba *hba = dev_get_drvdata(dev); 1721 1722 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1723 } 1724 1725 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1726 struct device_attribute *attr, const char *buf, size_t count) 1727 { 1728 struct ufs_hba *hba = dev_get_drvdata(dev); 1729 u32 value; 1730 int err = 0; 1731 1732 if (kstrtou32(buf, 0, &value)) 1733 return -EINVAL; 1734 1735 down(&hba->host_sem); 1736 if (!ufshcd_is_user_access_allowed(hba)) { 1737 err = -EBUSY; 1738 goto out; 1739 } 1740 1741 value = !!value; 1742 if (value == hba->clk_scaling.is_enabled) 1743 goto out; 1744 1745 ufshcd_rpm_get_sync(hba); 1746 ufshcd_hold(hba); 1747 1748 hba->clk_scaling.is_enabled = value; 1749 1750 if (value) { 1751 ufshcd_resume_clkscaling(hba); 1752 } else { 1753 ufshcd_suspend_clkscaling(hba); 1754 err = ufshcd_devfreq_scale(hba, ULONG_MAX, true); 1755 if (err) 1756 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1757 __func__, err); 1758 } 1759 1760 ufshcd_release(hba); 1761 ufshcd_rpm_put_sync(hba); 1762 out: 1763 up(&hba->host_sem); 1764 return err ? err : count; 1765 } 1766 1767 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1768 { 1769 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1770 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1771 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1772 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1773 hba->clk_scaling.enable_attr.attr.mode = 0644; 1774 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1775 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1776 } 1777 1778 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1779 { 1780 if (hba->clk_scaling.enable_attr.attr.name) 1781 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1782 } 1783 1784 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1785 { 1786 char wq_name[sizeof("ufs_clkscaling_00")]; 1787 1788 if (!ufshcd_is_clkscaling_supported(hba)) 1789 return; 1790 1791 if (!hba->clk_scaling.min_gear) 1792 hba->clk_scaling.min_gear = UFS_HS_G1; 1793 1794 INIT_WORK(&hba->clk_scaling.suspend_work, 1795 ufshcd_clk_scaling_suspend_work); 1796 INIT_WORK(&hba->clk_scaling.resume_work, 1797 ufshcd_clk_scaling_resume_work); 1798 1799 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d", 1800 hba->host->host_no); 1801 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name); 1802 1803 hba->clk_scaling.is_initialized = true; 1804 } 1805 1806 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1807 { 1808 if (!hba->clk_scaling.is_initialized) 1809 return; 1810 1811 ufshcd_remove_clk_scaling_sysfs(hba); 1812 destroy_workqueue(hba->clk_scaling.workq); 1813 ufshcd_devfreq_remove(hba); 1814 hba->clk_scaling.is_initialized = false; 1815 } 1816 1817 static void ufshcd_ungate_work(struct work_struct *work) 1818 { 1819 int ret; 1820 unsigned long flags; 1821 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1822 clk_gating.ungate_work); 1823 1824 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1825 1826 spin_lock_irqsave(hba->host->host_lock, flags); 1827 if (hba->clk_gating.state == CLKS_ON) { 1828 spin_unlock_irqrestore(hba->host->host_lock, flags); 1829 return; 1830 } 1831 1832 spin_unlock_irqrestore(hba->host->host_lock, flags); 1833 ufshcd_hba_vreg_set_hpm(hba); 1834 ufshcd_setup_clocks(hba, true); 1835 1836 ufshcd_enable_irq(hba); 1837 1838 /* Exit from hibern8 */ 1839 if (ufshcd_can_hibern8_during_gating(hba)) { 1840 /* Prevent gating in this path */ 1841 hba->clk_gating.is_suspended = true; 1842 if (ufshcd_is_link_hibern8(hba)) { 1843 ret = ufshcd_uic_hibern8_exit(hba); 1844 if (ret) 1845 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1846 __func__, ret); 1847 else 1848 ufshcd_set_link_active(hba); 1849 } 1850 hba->clk_gating.is_suspended = false; 1851 } 1852 } 1853 1854 /** 1855 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1856 * Also, exit from hibern8 mode and set the link as active. 1857 * @hba: per adapter instance 1858 */ 1859 void ufshcd_hold(struct ufs_hba *hba) 1860 { 1861 bool flush_result; 1862 unsigned long flags; 1863 1864 if (!ufshcd_is_clkgating_allowed(hba) || 1865 !hba->clk_gating.is_initialized) 1866 return; 1867 spin_lock_irqsave(hba->host->host_lock, flags); 1868 hba->clk_gating.active_reqs++; 1869 1870 start: 1871 switch (hba->clk_gating.state) { 1872 case CLKS_ON: 1873 /* 1874 * Wait for the ungate work to complete if in progress. 1875 * Though the clocks may be in ON state, the link could 1876 * still be in hibner8 state if hibern8 is allowed 1877 * during clock gating. 1878 * Make sure we exit hibern8 state also in addition to 1879 * clocks being ON. 1880 */ 1881 if (ufshcd_can_hibern8_during_gating(hba) && 1882 ufshcd_is_link_hibern8(hba)) { 1883 spin_unlock_irqrestore(hba->host->host_lock, flags); 1884 flush_result = flush_work(&hba->clk_gating.ungate_work); 1885 if (hba->clk_gating.is_suspended && !flush_result) 1886 return; 1887 spin_lock_irqsave(hba->host->host_lock, flags); 1888 goto start; 1889 } 1890 break; 1891 case REQ_CLKS_OFF: 1892 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1893 hba->clk_gating.state = CLKS_ON; 1894 trace_ufshcd_clk_gating(dev_name(hba->dev), 1895 hba->clk_gating.state); 1896 break; 1897 } 1898 /* 1899 * If we are here, it means gating work is either done or 1900 * currently running. Hence, fall through to cancel gating 1901 * work and to enable clocks. 1902 */ 1903 fallthrough; 1904 case CLKS_OFF: 1905 hba->clk_gating.state = REQ_CLKS_ON; 1906 trace_ufshcd_clk_gating(dev_name(hba->dev), 1907 hba->clk_gating.state); 1908 queue_work(hba->clk_gating.clk_gating_workq, 1909 &hba->clk_gating.ungate_work); 1910 /* 1911 * fall through to check if we should wait for this 1912 * work to be done or not. 1913 */ 1914 fallthrough; 1915 case REQ_CLKS_ON: 1916 spin_unlock_irqrestore(hba->host->host_lock, flags); 1917 flush_work(&hba->clk_gating.ungate_work); 1918 /* Make sure state is CLKS_ON before returning */ 1919 spin_lock_irqsave(hba->host->host_lock, flags); 1920 goto start; 1921 default: 1922 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1923 __func__, hba->clk_gating.state); 1924 break; 1925 } 1926 spin_unlock_irqrestore(hba->host->host_lock, flags); 1927 } 1928 EXPORT_SYMBOL_GPL(ufshcd_hold); 1929 1930 static void ufshcd_gate_work(struct work_struct *work) 1931 { 1932 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1933 clk_gating.gate_work.work); 1934 unsigned long flags; 1935 int ret; 1936 1937 spin_lock_irqsave(hba->host->host_lock, flags); 1938 /* 1939 * In case you are here to cancel this work the gating state 1940 * would be marked as REQ_CLKS_ON. In this case save time by 1941 * skipping the gating work and exit after changing the clock 1942 * state to CLKS_ON. 1943 */ 1944 if (hba->clk_gating.is_suspended || 1945 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1946 hba->clk_gating.state = CLKS_ON; 1947 trace_ufshcd_clk_gating(dev_name(hba->dev), 1948 hba->clk_gating.state); 1949 goto rel_lock; 1950 } 1951 1952 if (ufshcd_is_ufs_dev_busy(hba) || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) 1953 goto rel_lock; 1954 1955 spin_unlock_irqrestore(hba->host->host_lock, flags); 1956 1957 /* put the link into hibern8 mode before turning off clocks */ 1958 if (ufshcd_can_hibern8_during_gating(hba)) { 1959 ret = ufshcd_uic_hibern8_enter(hba); 1960 if (ret) { 1961 hba->clk_gating.state = CLKS_ON; 1962 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1963 __func__, ret); 1964 trace_ufshcd_clk_gating(dev_name(hba->dev), 1965 hba->clk_gating.state); 1966 goto out; 1967 } 1968 ufshcd_set_link_hibern8(hba); 1969 } 1970 1971 ufshcd_disable_irq(hba); 1972 1973 ufshcd_setup_clocks(hba, false); 1974 1975 /* Put the host controller in low power mode if possible */ 1976 ufshcd_hba_vreg_set_lpm(hba); 1977 /* 1978 * In case you are here to cancel this work the gating state 1979 * would be marked as REQ_CLKS_ON. In this case keep the state 1980 * as REQ_CLKS_ON which would anyway imply that clocks are off 1981 * and a request to turn them on is pending. By doing this way, 1982 * we keep the state machine in tact and this would ultimately 1983 * prevent from doing cancel work multiple times when there are 1984 * new requests arriving before the current cancel work is done. 1985 */ 1986 spin_lock_irqsave(hba->host->host_lock, flags); 1987 if (hba->clk_gating.state == REQ_CLKS_OFF) { 1988 hba->clk_gating.state = CLKS_OFF; 1989 trace_ufshcd_clk_gating(dev_name(hba->dev), 1990 hba->clk_gating.state); 1991 } 1992 rel_lock: 1993 spin_unlock_irqrestore(hba->host->host_lock, flags); 1994 out: 1995 return; 1996 } 1997 1998 /* host lock must be held before calling this variant */ 1999 static void __ufshcd_release(struct ufs_hba *hba) 2000 { 2001 if (!ufshcd_is_clkgating_allowed(hba)) 2002 return; 2003 2004 hba->clk_gating.active_reqs--; 2005 2006 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 2007 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 2008 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 2009 hba->active_uic_cmd || hba->uic_async_done || 2010 hba->clk_gating.state == CLKS_OFF) 2011 return; 2012 2013 hba->clk_gating.state = REQ_CLKS_OFF; 2014 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 2015 queue_delayed_work(hba->clk_gating.clk_gating_workq, 2016 &hba->clk_gating.gate_work, 2017 msecs_to_jiffies(hba->clk_gating.delay_ms)); 2018 } 2019 2020 void ufshcd_release(struct ufs_hba *hba) 2021 { 2022 unsigned long flags; 2023 2024 spin_lock_irqsave(hba->host->host_lock, flags); 2025 __ufshcd_release(hba); 2026 spin_unlock_irqrestore(hba->host->host_lock, flags); 2027 } 2028 EXPORT_SYMBOL_GPL(ufshcd_release); 2029 2030 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 2031 struct device_attribute *attr, char *buf) 2032 { 2033 struct ufs_hba *hba = dev_get_drvdata(dev); 2034 2035 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 2036 } 2037 2038 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 2039 { 2040 struct ufs_hba *hba = dev_get_drvdata(dev); 2041 unsigned long flags; 2042 2043 spin_lock_irqsave(hba->host->host_lock, flags); 2044 hba->clk_gating.delay_ms = value; 2045 spin_unlock_irqrestore(hba->host->host_lock, flags); 2046 } 2047 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 2048 2049 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 2050 struct device_attribute *attr, const char *buf, size_t count) 2051 { 2052 unsigned long value; 2053 2054 if (kstrtoul(buf, 0, &value)) 2055 return -EINVAL; 2056 2057 ufshcd_clkgate_delay_set(dev, value); 2058 return count; 2059 } 2060 2061 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 2062 struct device_attribute *attr, char *buf) 2063 { 2064 struct ufs_hba *hba = dev_get_drvdata(dev); 2065 2066 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 2067 } 2068 2069 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 2070 struct device_attribute *attr, const char *buf, size_t count) 2071 { 2072 struct ufs_hba *hba = dev_get_drvdata(dev); 2073 unsigned long flags; 2074 u32 value; 2075 2076 if (kstrtou32(buf, 0, &value)) 2077 return -EINVAL; 2078 2079 value = !!value; 2080 2081 spin_lock_irqsave(hba->host->host_lock, flags); 2082 if (value == hba->clk_gating.is_enabled) 2083 goto out; 2084 2085 if (value) 2086 __ufshcd_release(hba); 2087 else 2088 hba->clk_gating.active_reqs++; 2089 2090 hba->clk_gating.is_enabled = value; 2091 out: 2092 spin_unlock_irqrestore(hba->host->host_lock, flags); 2093 return count; 2094 } 2095 2096 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 2097 { 2098 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 2099 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 2100 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 2101 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 2102 hba->clk_gating.delay_attr.attr.mode = 0644; 2103 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 2104 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 2105 2106 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 2107 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 2108 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 2109 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 2110 hba->clk_gating.enable_attr.attr.mode = 0644; 2111 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 2112 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 2113 } 2114 2115 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 2116 { 2117 if (hba->clk_gating.delay_attr.attr.name) 2118 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 2119 if (hba->clk_gating.enable_attr.attr.name) 2120 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 2121 } 2122 2123 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 2124 { 2125 char wq_name[sizeof("ufs_clk_gating_00")]; 2126 2127 if (!ufshcd_is_clkgating_allowed(hba)) 2128 return; 2129 2130 hba->clk_gating.state = CLKS_ON; 2131 2132 hba->clk_gating.delay_ms = 150; 2133 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2134 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2135 2136 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d", 2137 hba->host->host_no); 2138 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name, 2139 WQ_MEM_RECLAIM | WQ_HIGHPRI); 2140 2141 ufshcd_init_clk_gating_sysfs(hba); 2142 2143 hba->clk_gating.is_enabled = true; 2144 hba->clk_gating.is_initialized = true; 2145 } 2146 2147 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2148 { 2149 if (!hba->clk_gating.is_initialized) 2150 return; 2151 2152 ufshcd_remove_clk_gating_sysfs(hba); 2153 2154 /* Ungate the clock if necessary. */ 2155 ufshcd_hold(hba); 2156 hba->clk_gating.is_initialized = false; 2157 ufshcd_release(hba); 2158 2159 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2160 } 2161 2162 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2163 { 2164 bool queue_resume_work = false; 2165 ktime_t curr_t = ktime_get(); 2166 unsigned long flags; 2167 2168 if (!ufshcd_is_clkscaling_supported(hba)) 2169 return; 2170 2171 spin_lock_irqsave(hba->host->host_lock, flags); 2172 if (!hba->clk_scaling.active_reqs++) 2173 queue_resume_work = true; 2174 2175 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2176 spin_unlock_irqrestore(hba->host->host_lock, flags); 2177 return; 2178 } 2179 2180 if (queue_resume_work) 2181 queue_work(hba->clk_scaling.workq, 2182 &hba->clk_scaling.resume_work); 2183 2184 if (!hba->clk_scaling.window_start_t) { 2185 hba->clk_scaling.window_start_t = curr_t; 2186 hba->clk_scaling.tot_busy_t = 0; 2187 hba->clk_scaling.is_busy_started = false; 2188 } 2189 2190 if (!hba->clk_scaling.is_busy_started) { 2191 hba->clk_scaling.busy_start_t = curr_t; 2192 hba->clk_scaling.is_busy_started = true; 2193 } 2194 spin_unlock_irqrestore(hba->host->host_lock, flags); 2195 } 2196 2197 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2198 { 2199 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2200 unsigned long flags; 2201 2202 if (!ufshcd_is_clkscaling_supported(hba)) 2203 return; 2204 2205 spin_lock_irqsave(hba->host->host_lock, flags); 2206 hba->clk_scaling.active_reqs--; 2207 if (!scaling->active_reqs && scaling->is_busy_started) { 2208 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2209 scaling->busy_start_t)); 2210 scaling->busy_start_t = 0; 2211 scaling->is_busy_started = false; 2212 } 2213 spin_unlock_irqrestore(hba->host->host_lock, flags); 2214 } 2215 2216 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2217 { 2218 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2219 return READ; 2220 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2221 return WRITE; 2222 else 2223 return -EINVAL; 2224 } 2225 2226 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2227 struct ufshcd_lrb *lrbp) 2228 { 2229 const struct ufs_hba_monitor *m = &hba->monitor; 2230 2231 return (m->enabled && lrbp && lrbp->cmd && 2232 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2233 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2234 } 2235 2236 static void ufshcd_start_monitor(struct ufs_hba *hba, 2237 const struct ufshcd_lrb *lrbp) 2238 { 2239 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2240 unsigned long flags; 2241 2242 spin_lock_irqsave(hba->host->host_lock, flags); 2243 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2244 hba->monitor.busy_start_ts[dir] = ktime_get(); 2245 spin_unlock_irqrestore(hba->host->host_lock, flags); 2246 } 2247 2248 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2249 { 2250 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2251 unsigned long flags; 2252 2253 spin_lock_irqsave(hba->host->host_lock, flags); 2254 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2255 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2256 struct ufs_hba_monitor *m = &hba->monitor; 2257 ktime_t now, inc, lat; 2258 2259 now = lrbp->compl_time_stamp; 2260 inc = ktime_sub(now, m->busy_start_ts[dir]); 2261 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2262 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2263 2264 /* Update latencies */ 2265 m->nr_req[dir]++; 2266 lat = ktime_sub(now, lrbp->issue_time_stamp); 2267 m->lat_sum[dir] += lat; 2268 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2269 m->lat_max[dir] = lat; 2270 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2271 m->lat_min[dir] = lat; 2272 2273 m->nr_queued[dir]--; 2274 /* Push forward the busy start of monitor */ 2275 m->busy_start_ts[dir] = now; 2276 } 2277 spin_unlock_irqrestore(hba->host->host_lock, flags); 2278 } 2279 2280 /** 2281 * ufshcd_send_command - Send SCSI or device management commands 2282 * @hba: per adapter instance 2283 * @task_tag: Task tag of the command 2284 * @hwq: pointer to hardware queue instance 2285 */ 2286 static inline 2287 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2288 struct ufs_hw_queue *hwq) 2289 { 2290 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2291 unsigned long flags; 2292 2293 lrbp->issue_time_stamp = ktime_get(); 2294 lrbp->issue_time_stamp_local_clock = local_clock(); 2295 lrbp->compl_time_stamp = ktime_set(0, 0); 2296 lrbp->compl_time_stamp_local_clock = 0; 2297 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2298 if (lrbp->cmd) 2299 ufshcd_clk_scaling_start_busy(hba); 2300 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2301 ufshcd_start_monitor(hba, lrbp); 2302 2303 if (is_mcq_enabled(hba)) { 2304 int utrd_size = sizeof(struct utp_transfer_req_desc); 2305 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2306 struct utp_transfer_req_desc *dest; 2307 2308 spin_lock(&hwq->sq_lock); 2309 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2310 memcpy(dest, src, utrd_size); 2311 ufshcd_inc_sq_tail(hwq); 2312 spin_unlock(&hwq->sq_lock); 2313 } else { 2314 spin_lock_irqsave(&hba->outstanding_lock, flags); 2315 if (hba->vops && hba->vops->setup_xfer_req) 2316 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2317 !!lrbp->cmd); 2318 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2319 ufshcd_writel(hba, 1 << lrbp->task_tag, 2320 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2321 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2322 } 2323 } 2324 2325 /** 2326 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2327 * @lrbp: pointer to local reference block 2328 */ 2329 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2330 { 2331 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2332 u16 resp_len; 2333 int len; 2334 2335 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2336 if (sense_buffer && resp_len) { 2337 int len_to_copy; 2338 2339 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2340 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2341 2342 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2343 len_to_copy); 2344 } 2345 } 2346 2347 /** 2348 * ufshcd_copy_query_response() - Copy the Query Response and the data 2349 * descriptor 2350 * @hba: per adapter instance 2351 * @lrbp: pointer to local reference block 2352 * 2353 * Return: 0 upon success; < 0 upon failure. 2354 */ 2355 static 2356 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2357 { 2358 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2359 2360 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2361 2362 /* Get the descriptor */ 2363 if (hba->dev_cmd.query.descriptor && 2364 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2365 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2366 GENERAL_UPIU_REQUEST_SIZE; 2367 u16 resp_len; 2368 u16 buf_len; 2369 2370 /* data segment length */ 2371 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2372 .data_segment_length); 2373 buf_len = be16_to_cpu( 2374 hba->dev_cmd.query.request.upiu_req.length); 2375 if (likely(buf_len >= resp_len)) { 2376 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2377 } else { 2378 dev_warn(hba->dev, 2379 "%s: rsp size %d is bigger than buffer size %d", 2380 __func__, resp_len, buf_len); 2381 return -EINVAL; 2382 } 2383 } 2384 2385 return 0; 2386 } 2387 2388 /** 2389 * ufshcd_hba_capabilities - Read controller capabilities 2390 * @hba: per adapter instance 2391 * 2392 * Return: 0 on success, negative on error. 2393 */ 2394 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2395 { 2396 int err; 2397 2398 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2399 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) 2400 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT; 2401 2402 /* nutrs and nutmrs are 0 based values */ 2403 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1; 2404 hba->nutmrs = 2405 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2406 hba->reserved_slot = hba->nutrs - 1; 2407 2408 /* Read crypto capabilities */ 2409 err = ufshcd_hba_init_crypto_capabilities(hba); 2410 if (err) { 2411 dev_err(hba->dev, "crypto setup failed\n"); 2412 return err; 2413 } 2414 2415 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2416 if (!hba->mcq_sup) 2417 return 0; 2418 2419 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2420 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2421 hba->mcq_capabilities); 2422 2423 return 0; 2424 } 2425 2426 /** 2427 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2428 * to accept UIC commands 2429 * @hba: per adapter instance 2430 * 2431 * Return: true on success, else false. 2432 */ 2433 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2434 { 2435 u32 val; 2436 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2437 500, UIC_CMD_TIMEOUT * 1000, false, hba, 2438 REG_CONTROLLER_STATUS); 2439 return ret == 0; 2440 } 2441 2442 /** 2443 * ufshcd_get_upmcrs - Get the power mode change request status 2444 * @hba: Pointer to adapter instance 2445 * 2446 * This function gets the UPMCRS field of HCS register 2447 * 2448 * Return: value of UPMCRS field. 2449 */ 2450 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2451 { 2452 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2453 } 2454 2455 /** 2456 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2457 * @hba: per adapter instance 2458 * @uic_cmd: UIC command 2459 */ 2460 static inline void 2461 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2462 { 2463 lockdep_assert_held(&hba->uic_cmd_mutex); 2464 2465 WARN_ON(hba->active_uic_cmd); 2466 2467 hba->active_uic_cmd = uic_cmd; 2468 2469 /* Write Args */ 2470 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2471 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2472 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2473 2474 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2475 2476 /* Write UIC Cmd */ 2477 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2478 REG_UIC_COMMAND); 2479 } 2480 2481 /** 2482 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2483 * @hba: per adapter instance 2484 * @uic_cmd: UIC command 2485 * 2486 * Return: 0 only if success. 2487 */ 2488 static int 2489 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2490 { 2491 int ret; 2492 unsigned long flags; 2493 2494 lockdep_assert_held(&hba->uic_cmd_mutex); 2495 2496 if (wait_for_completion_timeout(&uic_cmd->done, 2497 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 2498 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2499 } else { 2500 ret = -ETIMEDOUT; 2501 dev_err(hba->dev, 2502 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2503 uic_cmd->command, uic_cmd->argument3); 2504 2505 if (!uic_cmd->cmd_active) { 2506 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2507 __func__); 2508 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2509 } 2510 } 2511 2512 spin_lock_irqsave(hba->host->host_lock, flags); 2513 hba->active_uic_cmd = NULL; 2514 spin_unlock_irqrestore(hba->host->host_lock, flags); 2515 2516 return ret; 2517 } 2518 2519 /** 2520 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2521 * @hba: per adapter instance 2522 * @uic_cmd: UIC command 2523 * @completion: initialize the completion only if this is set to true 2524 * 2525 * Return: 0 only if success. 2526 */ 2527 static int 2528 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd, 2529 bool completion) 2530 { 2531 lockdep_assert_held(&hba->uic_cmd_mutex); 2532 2533 if (!ufshcd_ready_for_uic_cmd(hba)) { 2534 dev_err(hba->dev, 2535 "Controller not ready to accept UIC commands\n"); 2536 return -EIO; 2537 } 2538 2539 if (completion) 2540 init_completion(&uic_cmd->done); 2541 2542 uic_cmd->cmd_active = 1; 2543 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2544 2545 return 0; 2546 } 2547 2548 /** 2549 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2550 * @hba: per adapter instance 2551 * @uic_cmd: UIC command 2552 * 2553 * Return: 0 only if success. 2554 */ 2555 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2556 { 2557 int ret; 2558 2559 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2560 return 0; 2561 2562 ufshcd_hold(hba); 2563 mutex_lock(&hba->uic_cmd_mutex); 2564 ufshcd_add_delay_before_dme_cmd(hba); 2565 2566 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true); 2567 if (!ret) 2568 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2569 2570 mutex_unlock(&hba->uic_cmd_mutex); 2571 2572 ufshcd_release(hba); 2573 return ret; 2574 } 2575 2576 /** 2577 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2578 * @hba: per-adapter instance 2579 * @lrbp: pointer to local reference block 2580 * @sg_entries: The number of sg lists actually used 2581 * @sg_list: Pointer to SG list 2582 */ 2583 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2584 struct scatterlist *sg_list) 2585 { 2586 struct ufshcd_sg_entry *prd; 2587 struct scatterlist *sg; 2588 int i; 2589 2590 if (sg_entries) { 2591 2592 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2593 lrbp->utr_descriptor_ptr->prd_table_length = 2594 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2595 else 2596 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2597 2598 prd = lrbp->ucd_prdt_ptr; 2599 2600 for_each_sg(sg_list, sg, sg_entries, i) { 2601 const unsigned int len = sg_dma_len(sg); 2602 2603 /* 2604 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2605 * based value that indicates the length, in bytes, of 2606 * the data block. A maximum of length of 256KB may 2607 * exist for any entry. Bits 1:0 of this field shall be 2608 * 11b to indicate Dword granularity. A value of '3' 2609 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2610 */ 2611 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2612 prd->size = cpu_to_le32(len - 1); 2613 prd->addr = cpu_to_le64(sg->dma_address); 2614 prd->reserved = 0; 2615 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2616 } 2617 } else { 2618 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2619 } 2620 } 2621 2622 /** 2623 * ufshcd_map_sg - Map scatter-gather list to prdt 2624 * @hba: per adapter instance 2625 * @lrbp: pointer to local reference block 2626 * 2627 * Return: 0 in case of success, non-zero value in case of failure. 2628 */ 2629 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2630 { 2631 struct scsi_cmnd *cmd = lrbp->cmd; 2632 int sg_segments = scsi_dma_map(cmd); 2633 2634 if (sg_segments < 0) 2635 return sg_segments; 2636 2637 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2638 2639 return 0; 2640 } 2641 2642 /** 2643 * ufshcd_enable_intr - enable interrupts 2644 * @hba: per adapter instance 2645 * @intrs: interrupt bits 2646 */ 2647 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2648 { 2649 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2650 2651 set |= intrs; 2652 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2653 } 2654 2655 /** 2656 * ufshcd_disable_intr - disable interrupts 2657 * @hba: per adapter instance 2658 * @intrs: interrupt bits 2659 */ 2660 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2661 { 2662 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2663 2664 set &= ~intrs; 2665 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2666 } 2667 2668 /** 2669 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2670 * descriptor according to request 2671 * @hba: per adapter instance 2672 * @lrbp: pointer to local reference block 2673 * @upiu_flags: flags required in the header 2674 * @cmd_dir: requests data direction 2675 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2676 */ 2677 static void 2678 ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 2679 u8 *upiu_flags, enum dma_data_direction cmd_dir, 2680 int ehs_length) 2681 { 2682 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2683 struct request_desc_header *h = &req_desc->header; 2684 enum utp_data_direction data_direction; 2685 2686 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2687 2688 *h = (typeof(*h)){ }; 2689 2690 if (cmd_dir == DMA_FROM_DEVICE) { 2691 data_direction = UTP_DEVICE_TO_HOST; 2692 *upiu_flags = UPIU_CMD_FLAGS_READ; 2693 } else if (cmd_dir == DMA_TO_DEVICE) { 2694 data_direction = UTP_HOST_TO_DEVICE; 2695 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2696 } else { 2697 data_direction = UTP_NO_DATA_TRANSFER; 2698 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2699 } 2700 2701 h->command_type = lrbp->command_type; 2702 h->data_direction = data_direction; 2703 h->ehs_length = ehs_length; 2704 2705 if (lrbp->intr_cmd) 2706 h->interrupt = 1; 2707 2708 /* Prepare crypto related dwords */ 2709 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2710 2711 /* 2712 * assigning invalid value for command status. Controller 2713 * updates OCS on command completion, with the command 2714 * status 2715 */ 2716 h->ocs = OCS_INVALID_COMMAND_STATUS; 2717 2718 req_desc->prd_table_length = 0; 2719 } 2720 2721 /** 2722 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2723 * for scsi commands 2724 * @lrbp: local reference block pointer 2725 * @upiu_flags: flags 2726 */ 2727 static 2728 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2729 { 2730 struct scsi_cmnd *cmd = lrbp->cmd; 2731 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2732 unsigned short cdb_len; 2733 2734 ucd_req_ptr->header = (struct utp_upiu_header){ 2735 .transaction_code = UPIU_TRANSACTION_COMMAND, 2736 .flags = upiu_flags, 2737 .lun = lrbp->lun, 2738 .task_tag = lrbp->task_tag, 2739 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2740 }; 2741 2742 WARN_ON_ONCE(ucd_req_ptr->header.task_tag != lrbp->task_tag); 2743 2744 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2745 2746 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2747 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 2748 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2749 2750 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2751 } 2752 2753 /** 2754 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2755 * @hba: UFS hba 2756 * @lrbp: local reference block pointer 2757 * @upiu_flags: flags 2758 */ 2759 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2760 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2761 { 2762 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2763 struct ufs_query *query = &hba->dev_cmd.query; 2764 u16 len = be16_to_cpu(query->request.upiu_req.length); 2765 2766 /* Query request header */ 2767 ucd_req_ptr->header = (struct utp_upiu_header){ 2768 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2769 .flags = upiu_flags, 2770 .lun = lrbp->lun, 2771 .task_tag = lrbp->task_tag, 2772 .query_function = query->request.query_func, 2773 /* Data segment length only need for WRITE_DESC */ 2774 .data_segment_length = 2775 query->request.upiu_req.opcode == 2776 UPIU_QUERY_OPCODE_WRITE_DESC ? 2777 cpu_to_be16(len) : 2778 0, 2779 }; 2780 2781 /* Copy the Query Request buffer as is */ 2782 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2783 QUERY_OSF_SIZE); 2784 2785 /* Copy the Descriptor */ 2786 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2787 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2788 2789 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2790 } 2791 2792 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2793 { 2794 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2795 2796 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2797 2798 ucd_req_ptr->header = (struct utp_upiu_header){ 2799 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2800 .task_tag = lrbp->task_tag, 2801 }; 2802 2803 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2804 } 2805 2806 /** 2807 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2808 * for Device Management Purposes 2809 * @hba: per adapter instance 2810 * @lrbp: pointer to local reference block 2811 * 2812 * Return: 0 upon success; < 0 upon failure. 2813 */ 2814 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2815 struct ufshcd_lrb *lrbp) 2816 { 2817 u8 upiu_flags; 2818 int ret = 0; 2819 2820 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 2821 2822 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2823 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2824 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2825 ufshcd_prepare_utp_nop_upiu(lrbp); 2826 else 2827 ret = -EINVAL; 2828 2829 return ret; 2830 } 2831 2832 /** 2833 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2834 * for SCSI Purposes 2835 * @hba: per adapter instance 2836 * @lrbp: pointer to local reference block 2837 */ 2838 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2839 { 2840 struct request *rq = scsi_cmd_to_rq(lrbp->cmd); 2841 unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq)); 2842 u8 upiu_flags; 2843 2844 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0); 2845 if (ioprio_class == IOPRIO_CLASS_RT) 2846 upiu_flags |= UPIU_CMD_FLAGS_CP; 2847 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2848 } 2849 2850 /** 2851 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2852 * @upiu_wlun_id: UPIU W-LUN id 2853 * 2854 * Return: SCSI W-LUN id. 2855 */ 2856 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2857 { 2858 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2859 } 2860 2861 static inline bool is_device_wlun(struct scsi_device *sdev) 2862 { 2863 return sdev->lun == 2864 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2865 } 2866 2867 /* 2868 * Associate the UFS controller queue with the default and poll HCTX types. 2869 * Initialize the mq_map[] arrays. 2870 */ 2871 static void ufshcd_map_queues(struct Scsi_Host *shost) 2872 { 2873 struct ufs_hba *hba = shost_priv(shost); 2874 int i, queue_offset = 0; 2875 2876 if (!is_mcq_supported(hba)) { 2877 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2878 hba->nr_queues[HCTX_TYPE_READ] = 0; 2879 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2880 hba->nr_hw_queues = 1; 2881 } 2882 2883 for (i = 0; i < shost->nr_maps; i++) { 2884 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2885 2886 map->nr_queues = hba->nr_queues[i]; 2887 if (!map->nr_queues) 2888 continue; 2889 map->queue_offset = queue_offset; 2890 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2891 map->queue_offset = 0; 2892 2893 blk_mq_map_queues(map); 2894 queue_offset += map->nr_queues; 2895 } 2896 } 2897 2898 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2899 { 2900 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2901 i * ufshcd_get_ucd_size(hba); 2902 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2903 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2904 i * ufshcd_get_ucd_size(hba); 2905 u16 response_offset = offsetof(struct utp_transfer_cmd_desc, 2906 response_upiu); 2907 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 2908 2909 lrb->utr_descriptor_ptr = utrdlp + i; 2910 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2911 i * sizeof(struct utp_transfer_req_desc); 2912 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2913 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2914 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2915 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2916 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2917 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2918 } 2919 2920 /** 2921 * ufshcd_queuecommand - main entry point for SCSI requests 2922 * @host: SCSI host pointer 2923 * @cmd: command from SCSI Midlayer 2924 * 2925 * Return: 0 for success, non-zero in case of failure. 2926 */ 2927 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2928 { 2929 struct ufs_hba *hba = shost_priv(host); 2930 int tag = scsi_cmd_to_rq(cmd)->tag; 2931 struct ufshcd_lrb *lrbp; 2932 int err = 0; 2933 struct ufs_hw_queue *hwq = NULL; 2934 2935 switch (hba->ufshcd_state) { 2936 case UFSHCD_STATE_OPERATIONAL: 2937 break; 2938 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2939 /* 2940 * SCSI error handler can call ->queuecommand() while UFS error 2941 * handler is in progress. Error interrupts could change the 2942 * state from UFSHCD_STATE_RESET to 2943 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2944 * being issued in that case. 2945 */ 2946 if (ufshcd_eh_in_progress(hba)) { 2947 err = SCSI_MLQUEUE_HOST_BUSY; 2948 goto out; 2949 } 2950 break; 2951 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2952 /* 2953 * pm_runtime_get_sync() is used at error handling preparation 2954 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2955 * PM ops, it can never be finished if we let SCSI layer keep 2956 * retrying it, which gets err handler stuck forever. Neither 2957 * can we let the scsi cmd pass through, because UFS is in bad 2958 * state, the scsi cmd may eventually time out, which will get 2959 * err handler blocked for too long. So, just fail the scsi cmd 2960 * sent from PM ops, err handler can recover PM error anyways. 2961 */ 2962 if (hba->pm_op_in_progress) { 2963 hba->force_reset = true; 2964 set_host_byte(cmd, DID_BAD_TARGET); 2965 scsi_done(cmd); 2966 goto out; 2967 } 2968 fallthrough; 2969 case UFSHCD_STATE_RESET: 2970 err = SCSI_MLQUEUE_HOST_BUSY; 2971 goto out; 2972 case UFSHCD_STATE_ERROR: 2973 set_host_byte(cmd, DID_ERROR); 2974 scsi_done(cmd); 2975 goto out; 2976 } 2977 2978 hba->req_abort_count = 0; 2979 2980 ufshcd_hold(hba); 2981 2982 lrbp = &hba->lrb[tag]; 2983 lrbp->cmd = cmd; 2984 lrbp->task_tag = tag; 2985 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 2986 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 2987 2988 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp); 2989 2990 lrbp->req_abort_skip = false; 2991 2992 ufshcd_comp_scsi_upiu(hba, lrbp); 2993 2994 err = ufshcd_map_sg(hba, lrbp); 2995 if (err) { 2996 ufshcd_release(hba); 2997 goto out; 2998 } 2999 3000 if (is_mcq_enabled(hba)) 3001 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 3002 3003 ufshcd_send_command(hba, tag, hwq); 3004 3005 out: 3006 if (ufs_trigger_eh(hba)) { 3007 unsigned long flags; 3008 3009 spin_lock_irqsave(hba->host->host_lock, flags); 3010 ufshcd_schedule_eh_work(hba); 3011 spin_unlock_irqrestore(hba->host->host_lock, flags); 3012 } 3013 3014 return err; 3015 } 3016 3017 static void ufshcd_setup_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3018 enum dev_cmd_type cmd_type, u8 lun, int tag) 3019 { 3020 lrbp->cmd = NULL; 3021 lrbp->task_tag = tag; 3022 lrbp->lun = lun; 3023 lrbp->intr_cmd = true; /* No interrupt aggregation */ 3024 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 3025 hba->dev_cmd.type = cmd_type; 3026 } 3027 3028 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 3029 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 3030 { 3031 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 3032 3033 return ufshcd_compose_devman_upiu(hba, lrbp); 3034 } 3035 3036 /* 3037 * Check with the block layer if the command is inflight 3038 * @cmd: command to check. 3039 * 3040 * Return: true if command is inflight; false if not. 3041 */ 3042 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 3043 { 3044 return cmd && blk_mq_rq_state(scsi_cmd_to_rq(cmd)) == MQ_RQ_IN_FLIGHT; 3045 } 3046 3047 /* 3048 * Clear the pending command in the controller and wait until 3049 * the controller confirms that the command has been cleared. 3050 * @hba: per adapter instance 3051 * @task_tag: The tag number of the command to be cleared. 3052 */ 3053 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 3054 { 3055 u32 mask; 3056 unsigned long flags; 3057 int err; 3058 3059 if (is_mcq_enabled(hba)) { 3060 /* 3061 * MCQ mode. Clean up the MCQ resources similar to 3062 * what the ufshcd_utrl_clear() does for SDB mode. 3063 */ 3064 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 3065 if (err) { 3066 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 3067 __func__, task_tag, err); 3068 return err; 3069 } 3070 return 0; 3071 } 3072 3073 mask = 1U << task_tag; 3074 3075 /* clear outstanding transaction before retry */ 3076 spin_lock_irqsave(hba->host->host_lock, flags); 3077 ufshcd_utrl_clear(hba, mask); 3078 spin_unlock_irqrestore(hba->host->host_lock, flags); 3079 3080 /* 3081 * wait for h/w to clear corresponding bit in door-bell. 3082 * max. wait is 1 sec. 3083 */ 3084 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 3085 mask, ~mask, 1000, 1000); 3086 } 3087 3088 /** 3089 * ufshcd_dev_cmd_completion() - handles device management command responses 3090 * @hba: per adapter instance 3091 * @lrbp: pointer to local reference block 3092 * 3093 * Return: 0 upon success; < 0 upon failure. 3094 */ 3095 static int 3096 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 3097 { 3098 enum upiu_response_transaction resp; 3099 int err = 0; 3100 3101 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 3102 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3103 3104 switch (resp) { 3105 case UPIU_TRANSACTION_NOP_IN: 3106 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3107 err = -EINVAL; 3108 dev_err(hba->dev, "%s: unexpected response %x\n", 3109 __func__, resp); 3110 } 3111 break; 3112 case UPIU_TRANSACTION_QUERY_RSP: { 3113 u8 response = lrbp->ucd_rsp_ptr->header.response; 3114 3115 if (response == 0) 3116 err = ufshcd_copy_query_response(hba, lrbp); 3117 break; 3118 } 3119 case UPIU_TRANSACTION_REJECT_UPIU: 3120 /* TODO: handle Reject UPIU Response */ 3121 err = -EPERM; 3122 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3123 __func__); 3124 break; 3125 case UPIU_TRANSACTION_RESPONSE: 3126 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3127 err = -EINVAL; 3128 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3129 } 3130 break; 3131 default: 3132 err = -EINVAL; 3133 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3134 __func__, resp); 3135 break; 3136 } 3137 3138 return err; 3139 } 3140 3141 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3142 struct ufshcd_lrb *lrbp, int max_timeout) 3143 { 3144 unsigned long time_left = msecs_to_jiffies(max_timeout); 3145 unsigned long flags; 3146 bool pending; 3147 int err; 3148 3149 retry: 3150 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3151 time_left); 3152 3153 if (likely(time_left)) { 3154 /* 3155 * The completion handler called complete() and the caller of 3156 * this function still owns the @lrbp tag so the code below does 3157 * not trigger any race conditions. 3158 */ 3159 hba->dev_cmd.complete = NULL; 3160 err = ufshcd_get_tr_ocs(lrbp, NULL); 3161 if (!err) 3162 err = ufshcd_dev_cmd_completion(hba, lrbp); 3163 } else { 3164 err = -ETIMEDOUT; 3165 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3166 __func__, lrbp->task_tag); 3167 3168 /* MCQ mode */ 3169 if (is_mcq_enabled(hba)) { 3170 /* successfully cleared the command, retry if needed */ 3171 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) 3172 err = -EAGAIN; 3173 hba->dev_cmd.complete = NULL; 3174 return err; 3175 } 3176 3177 /* SDB mode */ 3178 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3179 /* successfully cleared the command, retry if needed */ 3180 err = -EAGAIN; 3181 /* 3182 * Since clearing the command succeeded we also need to 3183 * clear the task tag bit from the outstanding_reqs 3184 * variable. 3185 */ 3186 spin_lock_irqsave(&hba->outstanding_lock, flags); 3187 pending = test_bit(lrbp->task_tag, 3188 &hba->outstanding_reqs); 3189 if (pending) { 3190 hba->dev_cmd.complete = NULL; 3191 __clear_bit(lrbp->task_tag, 3192 &hba->outstanding_reqs); 3193 } 3194 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3195 3196 if (!pending) { 3197 /* 3198 * The completion handler ran while we tried to 3199 * clear the command. 3200 */ 3201 time_left = 1; 3202 goto retry; 3203 } 3204 } else { 3205 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3206 __func__, lrbp->task_tag); 3207 3208 spin_lock_irqsave(&hba->outstanding_lock, flags); 3209 pending = test_bit(lrbp->task_tag, 3210 &hba->outstanding_reqs); 3211 if (pending) 3212 hba->dev_cmd.complete = NULL; 3213 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3214 3215 if (!pending) { 3216 /* 3217 * The completion handler ran while we tried to 3218 * clear the command. 3219 */ 3220 time_left = 1; 3221 goto retry; 3222 } 3223 } 3224 } 3225 3226 return err; 3227 } 3228 3229 static void ufshcd_dev_man_lock(struct ufs_hba *hba) 3230 { 3231 ufshcd_hold(hba); 3232 mutex_lock(&hba->dev_cmd.lock); 3233 down_read(&hba->clk_scaling_lock); 3234 } 3235 3236 static void ufshcd_dev_man_unlock(struct ufs_hba *hba) 3237 { 3238 up_read(&hba->clk_scaling_lock); 3239 mutex_unlock(&hba->dev_cmd.lock); 3240 ufshcd_release(hba); 3241 } 3242 3243 static int ufshcd_issue_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3244 const u32 tag, int timeout) 3245 { 3246 DECLARE_COMPLETION_ONSTACK(wait); 3247 int err; 3248 3249 hba->dev_cmd.complete = &wait; 3250 3251 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3252 3253 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3254 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3255 3256 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3257 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3258 3259 return err; 3260 } 3261 3262 /** 3263 * ufshcd_exec_dev_cmd - API for sending device management requests 3264 * @hba: UFS hba 3265 * @cmd_type: specifies the type (NOP, Query...) 3266 * @timeout: timeout in milliseconds 3267 * 3268 * Return: 0 upon success; < 0 upon failure. 3269 * 3270 * NOTE: Since there is only one available tag for device management commands, 3271 * it is expected you hold the hba->dev_cmd.lock mutex. 3272 */ 3273 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3274 enum dev_cmd_type cmd_type, int timeout) 3275 { 3276 const u32 tag = hba->reserved_slot; 3277 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 3278 int err; 3279 3280 /* Protects use of hba->reserved_slot. */ 3281 lockdep_assert_held(&hba->dev_cmd.lock); 3282 3283 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3284 if (unlikely(err)) 3285 return err; 3286 3287 return ufshcd_issue_dev_cmd(hba, lrbp, tag, timeout); 3288 } 3289 3290 /** 3291 * ufshcd_init_query() - init the query response and request parameters 3292 * @hba: per-adapter instance 3293 * @request: address of the request pointer to be initialized 3294 * @response: address of the response pointer to be initialized 3295 * @opcode: operation to perform 3296 * @idn: flag idn to access 3297 * @index: LU number to access 3298 * @selector: query/flag/descriptor further identification 3299 */ 3300 static inline void ufshcd_init_query(struct ufs_hba *hba, 3301 struct ufs_query_req **request, struct ufs_query_res **response, 3302 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3303 { 3304 *request = &hba->dev_cmd.query.request; 3305 *response = &hba->dev_cmd.query.response; 3306 memset(*request, 0, sizeof(struct ufs_query_req)); 3307 memset(*response, 0, sizeof(struct ufs_query_res)); 3308 (*request)->upiu_req.opcode = opcode; 3309 (*request)->upiu_req.idn = idn; 3310 (*request)->upiu_req.index = index; 3311 (*request)->upiu_req.selector = selector; 3312 } 3313 3314 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3315 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3316 { 3317 int ret; 3318 int retries; 3319 3320 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3321 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3322 if (ret) 3323 dev_dbg(hba->dev, 3324 "%s: failed with error %d, retries %d\n", 3325 __func__, ret, retries); 3326 else 3327 break; 3328 } 3329 3330 if (ret) 3331 dev_err(hba->dev, 3332 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3333 __func__, opcode, idn, ret, retries); 3334 return ret; 3335 } 3336 3337 /** 3338 * ufshcd_query_flag() - API function for sending flag query requests 3339 * @hba: per-adapter instance 3340 * @opcode: flag query to perform 3341 * @idn: flag idn to access 3342 * @index: flag index to access 3343 * @flag_res: the flag value after the query request completes 3344 * 3345 * Return: 0 for success, non-zero in case of failure. 3346 */ 3347 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3348 enum flag_idn idn, u8 index, bool *flag_res) 3349 { 3350 struct ufs_query_req *request = NULL; 3351 struct ufs_query_res *response = NULL; 3352 int err, selector = 0; 3353 int timeout = QUERY_REQ_TIMEOUT; 3354 3355 BUG_ON(!hba); 3356 3357 ufshcd_dev_man_lock(hba); 3358 3359 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3360 selector); 3361 3362 switch (opcode) { 3363 case UPIU_QUERY_OPCODE_SET_FLAG: 3364 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3365 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3366 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3367 break; 3368 case UPIU_QUERY_OPCODE_READ_FLAG: 3369 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3370 if (!flag_res) { 3371 /* No dummy reads */ 3372 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3373 __func__); 3374 err = -EINVAL; 3375 goto out_unlock; 3376 } 3377 break; 3378 default: 3379 dev_err(hba->dev, 3380 "%s: Expected query flag opcode but got = %d\n", 3381 __func__, opcode); 3382 err = -EINVAL; 3383 goto out_unlock; 3384 } 3385 3386 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3387 3388 if (err) { 3389 dev_err(hba->dev, 3390 "%s: Sending flag query for idn %d failed, err = %d\n", 3391 __func__, idn, err); 3392 goto out_unlock; 3393 } 3394 3395 if (flag_res) 3396 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3397 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3398 3399 out_unlock: 3400 ufshcd_dev_man_unlock(hba); 3401 return err; 3402 } 3403 3404 /** 3405 * ufshcd_query_attr - API function for sending attribute requests 3406 * @hba: per-adapter instance 3407 * @opcode: attribute opcode 3408 * @idn: attribute idn to access 3409 * @index: index field 3410 * @selector: selector field 3411 * @attr_val: the attribute value after the query request completes 3412 * 3413 * Return: 0 for success, non-zero in case of failure. 3414 */ 3415 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3416 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3417 { 3418 struct ufs_query_req *request = NULL; 3419 struct ufs_query_res *response = NULL; 3420 int err; 3421 3422 BUG_ON(!hba); 3423 3424 if (!attr_val) { 3425 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3426 __func__, opcode); 3427 return -EINVAL; 3428 } 3429 3430 ufshcd_dev_man_lock(hba); 3431 3432 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3433 selector); 3434 3435 switch (opcode) { 3436 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3437 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3438 request->upiu_req.value = cpu_to_be32(*attr_val); 3439 break; 3440 case UPIU_QUERY_OPCODE_READ_ATTR: 3441 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3442 break; 3443 default: 3444 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3445 __func__, opcode); 3446 err = -EINVAL; 3447 goto out_unlock; 3448 } 3449 3450 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3451 3452 if (err) { 3453 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3454 __func__, opcode, idn, index, err); 3455 goto out_unlock; 3456 } 3457 3458 *attr_val = be32_to_cpu(response->upiu_res.value); 3459 3460 out_unlock: 3461 ufshcd_dev_man_unlock(hba); 3462 return err; 3463 } 3464 3465 /** 3466 * ufshcd_query_attr_retry() - API function for sending query 3467 * attribute with retries 3468 * @hba: per-adapter instance 3469 * @opcode: attribute opcode 3470 * @idn: attribute idn to access 3471 * @index: index field 3472 * @selector: selector field 3473 * @attr_val: the attribute value after the query request 3474 * completes 3475 * 3476 * Return: 0 for success, non-zero in case of failure. 3477 */ 3478 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3479 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3480 u32 *attr_val) 3481 { 3482 int ret = 0; 3483 u32 retries; 3484 3485 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3486 ret = ufshcd_query_attr(hba, opcode, idn, index, 3487 selector, attr_val); 3488 if (ret) 3489 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3490 __func__, ret, retries); 3491 else 3492 break; 3493 } 3494 3495 if (ret) 3496 dev_err(hba->dev, 3497 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3498 __func__, idn, ret, QUERY_REQ_RETRIES); 3499 return ret; 3500 } 3501 3502 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3503 enum query_opcode opcode, enum desc_idn idn, u8 index, 3504 u8 selector, u8 *desc_buf, int *buf_len) 3505 { 3506 struct ufs_query_req *request = NULL; 3507 struct ufs_query_res *response = NULL; 3508 int err; 3509 3510 BUG_ON(!hba); 3511 3512 if (!desc_buf) { 3513 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3514 __func__, opcode); 3515 return -EINVAL; 3516 } 3517 3518 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3519 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3520 __func__, *buf_len); 3521 return -EINVAL; 3522 } 3523 3524 ufshcd_dev_man_lock(hba); 3525 3526 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3527 selector); 3528 hba->dev_cmd.query.descriptor = desc_buf; 3529 request->upiu_req.length = cpu_to_be16(*buf_len); 3530 3531 switch (opcode) { 3532 case UPIU_QUERY_OPCODE_WRITE_DESC: 3533 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3534 break; 3535 case UPIU_QUERY_OPCODE_READ_DESC: 3536 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3537 break; 3538 default: 3539 dev_err(hba->dev, 3540 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3541 __func__, opcode); 3542 err = -EINVAL; 3543 goto out_unlock; 3544 } 3545 3546 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3547 3548 if (err) { 3549 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3550 __func__, opcode, idn, index, err); 3551 goto out_unlock; 3552 } 3553 3554 *buf_len = be16_to_cpu(response->upiu_res.length); 3555 3556 out_unlock: 3557 hba->dev_cmd.query.descriptor = NULL; 3558 ufshcd_dev_man_unlock(hba); 3559 return err; 3560 } 3561 3562 /** 3563 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3564 * @hba: per-adapter instance 3565 * @opcode: attribute opcode 3566 * @idn: attribute idn to access 3567 * @index: index field 3568 * @selector: selector field 3569 * @desc_buf: the buffer that contains the descriptor 3570 * @buf_len: length parameter passed to the device 3571 * 3572 * The buf_len parameter will contain, on return, the length parameter 3573 * received on the response. 3574 * 3575 * Return: 0 for success, non-zero in case of failure. 3576 */ 3577 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3578 enum query_opcode opcode, 3579 enum desc_idn idn, u8 index, 3580 u8 selector, 3581 u8 *desc_buf, int *buf_len) 3582 { 3583 int err; 3584 int retries; 3585 3586 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3587 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3588 selector, desc_buf, buf_len); 3589 if (!err || err == -EINVAL) 3590 break; 3591 } 3592 3593 return err; 3594 } 3595 3596 /** 3597 * ufshcd_read_desc_param - read the specified descriptor parameter 3598 * @hba: Pointer to adapter instance 3599 * @desc_id: descriptor idn value 3600 * @desc_index: descriptor index 3601 * @param_offset: offset of the parameter to read 3602 * @param_read_buf: pointer to buffer where parameter would be read 3603 * @param_size: sizeof(param_read_buf) 3604 * 3605 * Return: 0 in case of success, non-zero otherwise. 3606 */ 3607 int ufshcd_read_desc_param(struct ufs_hba *hba, 3608 enum desc_idn desc_id, 3609 int desc_index, 3610 u8 param_offset, 3611 u8 *param_read_buf, 3612 u8 param_size) 3613 { 3614 int ret; 3615 u8 *desc_buf; 3616 int buff_len = QUERY_DESC_MAX_SIZE; 3617 bool is_kmalloc = true; 3618 3619 /* Safety check */ 3620 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3621 return -EINVAL; 3622 3623 /* Check whether we need temp memory */ 3624 if (param_offset != 0 || param_size < buff_len) { 3625 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3626 if (!desc_buf) 3627 return -ENOMEM; 3628 } else { 3629 desc_buf = param_read_buf; 3630 is_kmalloc = false; 3631 } 3632 3633 /* Request for full descriptor */ 3634 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3635 desc_id, desc_index, 0, 3636 desc_buf, &buff_len); 3637 if (ret) { 3638 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3639 __func__, desc_id, desc_index, param_offset, ret); 3640 goto out; 3641 } 3642 3643 /* Update descriptor length */ 3644 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3645 3646 if (param_offset >= buff_len) { 3647 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3648 __func__, param_offset, desc_id, buff_len); 3649 ret = -EINVAL; 3650 goto out; 3651 } 3652 3653 /* Sanity check */ 3654 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3655 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3656 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3657 ret = -EINVAL; 3658 goto out; 3659 } 3660 3661 if (is_kmalloc) { 3662 /* Make sure we don't copy more data than available */ 3663 if (param_offset >= buff_len) 3664 ret = -EINVAL; 3665 else 3666 memcpy(param_read_buf, &desc_buf[param_offset], 3667 min_t(u32, param_size, buff_len - param_offset)); 3668 } 3669 out: 3670 if (is_kmalloc) 3671 kfree(desc_buf); 3672 return ret; 3673 } 3674 3675 /** 3676 * struct uc_string_id - unicode string 3677 * 3678 * @len: size of this descriptor inclusive 3679 * @type: descriptor type 3680 * @uc: unicode string character 3681 */ 3682 struct uc_string_id { 3683 u8 len; 3684 u8 type; 3685 wchar_t uc[]; 3686 } __packed; 3687 3688 /* replace non-printable or non-ASCII characters with spaces */ 3689 static inline char ufshcd_remove_non_printable(u8 ch) 3690 { 3691 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3692 } 3693 3694 /** 3695 * ufshcd_read_string_desc - read string descriptor 3696 * @hba: pointer to adapter instance 3697 * @desc_index: descriptor index 3698 * @buf: pointer to buffer where descriptor would be read, 3699 * the caller should free the memory. 3700 * @ascii: if true convert from unicode to ascii characters 3701 * null terminated string. 3702 * 3703 * Return: 3704 * * string size on success. 3705 * * -ENOMEM: on allocation failure 3706 * * -EINVAL: on a wrong parameter 3707 */ 3708 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3709 u8 **buf, bool ascii) 3710 { 3711 struct uc_string_id *uc_str; 3712 u8 *str; 3713 int ret; 3714 3715 if (!buf) 3716 return -EINVAL; 3717 3718 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3719 if (!uc_str) 3720 return -ENOMEM; 3721 3722 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3723 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3724 if (ret < 0) { 3725 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3726 QUERY_REQ_RETRIES, ret); 3727 str = NULL; 3728 goto out; 3729 } 3730 3731 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3732 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3733 str = NULL; 3734 ret = 0; 3735 goto out; 3736 } 3737 3738 if (ascii) { 3739 ssize_t ascii_len; 3740 int i; 3741 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3742 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3743 str = kzalloc(ascii_len, GFP_KERNEL); 3744 if (!str) { 3745 ret = -ENOMEM; 3746 goto out; 3747 } 3748 3749 /* 3750 * the descriptor contains string in UTF16 format 3751 * we need to convert to utf-8 so it can be displayed 3752 */ 3753 ret = utf16s_to_utf8s(uc_str->uc, 3754 uc_str->len - QUERY_DESC_HDR_SIZE, 3755 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3756 3757 /* replace non-printable or non-ASCII characters with spaces */ 3758 for (i = 0; i < ret; i++) 3759 str[i] = ufshcd_remove_non_printable(str[i]); 3760 3761 str[ret++] = '\0'; 3762 3763 } else { 3764 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3765 if (!str) { 3766 ret = -ENOMEM; 3767 goto out; 3768 } 3769 ret = uc_str->len; 3770 } 3771 out: 3772 *buf = str; 3773 kfree(uc_str); 3774 return ret; 3775 } 3776 3777 /** 3778 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3779 * @hba: Pointer to adapter instance 3780 * @lun: lun id 3781 * @param_offset: offset of the parameter to read 3782 * @param_read_buf: pointer to buffer where parameter would be read 3783 * @param_size: sizeof(param_read_buf) 3784 * 3785 * Return: 0 in case of success, non-zero otherwise. 3786 */ 3787 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3788 int lun, 3789 enum unit_desc_param param_offset, 3790 u8 *param_read_buf, 3791 u32 param_size) 3792 { 3793 /* 3794 * Unit descriptors are only available for general purpose LUs (LUN id 3795 * from 0 to 7) and RPMB Well known LU. 3796 */ 3797 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3798 return -EOPNOTSUPP; 3799 3800 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3801 param_offset, param_read_buf, param_size); 3802 } 3803 3804 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3805 { 3806 int err = 0; 3807 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3808 3809 if (hba->dev_info.wspecversion >= 0x300) { 3810 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3811 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3812 &gating_wait); 3813 if (err) 3814 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3815 err, gating_wait); 3816 3817 if (gating_wait == 0) { 3818 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3819 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3820 gating_wait); 3821 } 3822 3823 hba->dev_info.clk_gating_wait_us = gating_wait; 3824 } 3825 3826 return err; 3827 } 3828 3829 /** 3830 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3831 * @hba: per adapter instance 3832 * 3833 * 1. Allocate DMA memory for Command Descriptor array 3834 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3835 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3836 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3837 * (UTMRDL) 3838 * 4. Allocate memory for local reference block(lrb). 3839 * 3840 * Return: 0 for success, non-zero in case of failure. 3841 */ 3842 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3843 { 3844 size_t utmrdl_size, utrdl_size, ucdl_size; 3845 3846 /* Allocate memory for UTP command descriptors */ 3847 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3848 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3849 ucdl_size, 3850 &hba->ucdl_dma_addr, 3851 GFP_KERNEL); 3852 3853 /* 3854 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3855 */ 3856 if (!hba->ucdl_base_addr || 3857 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3858 dev_err(hba->dev, 3859 "Command Descriptor Memory allocation failed\n"); 3860 goto out; 3861 } 3862 3863 /* 3864 * Allocate memory for UTP Transfer descriptors 3865 * UFSHCI requires 1KB alignment of UTRD 3866 */ 3867 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3868 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3869 utrdl_size, 3870 &hba->utrdl_dma_addr, 3871 GFP_KERNEL); 3872 if (!hba->utrdl_base_addr || 3873 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3874 dev_err(hba->dev, 3875 "Transfer Descriptor Memory allocation failed\n"); 3876 goto out; 3877 } 3878 3879 /* 3880 * Skip utmrdl allocation; it may have been 3881 * allocated during first pass and not released during 3882 * MCQ memory allocation. 3883 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3884 */ 3885 if (hba->utmrdl_base_addr) 3886 goto skip_utmrdl; 3887 /* 3888 * Allocate memory for UTP Task Management descriptors 3889 * UFSHCI requires 1KB alignment of UTMRD 3890 */ 3891 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3892 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3893 utmrdl_size, 3894 &hba->utmrdl_dma_addr, 3895 GFP_KERNEL); 3896 if (!hba->utmrdl_base_addr || 3897 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3898 dev_err(hba->dev, 3899 "Task Management Descriptor Memory allocation failed\n"); 3900 goto out; 3901 } 3902 3903 skip_utmrdl: 3904 /* Allocate memory for local reference block */ 3905 hba->lrb = devm_kcalloc(hba->dev, 3906 hba->nutrs, sizeof(struct ufshcd_lrb), 3907 GFP_KERNEL); 3908 if (!hba->lrb) { 3909 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3910 goto out; 3911 } 3912 return 0; 3913 out: 3914 return -ENOMEM; 3915 } 3916 3917 /** 3918 * ufshcd_host_memory_configure - configure local reference block with 3919 * memory offsets 3920 * @hba: per adapter instance 3921 * 3922 * Configure Host memory space 3923 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3924 * address. 3925 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3926 * and PRDT offset. 3927 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3928 * into local reference block. 3929 */ 3930 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3931 { 3932 struct utp_transfer_req_desc *utrdlp; 3933 dma_addr_t cmd_desc_dma_addr; 3934 dma_addr_t cmd_desc_element_addr; 3935 u16 response_offset; 3936 u16 prdt_offset; 3937 int cmd_desc_size; 3938 int i; 3939 3940 utrdlp = hba->utrdl_base_addr; 3941 3942 response_offset = 3943 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3944 prdt_offset = 3945 offsetof(struct utp_transfer_cmd_desc, prd_table); 3946 3947 cmd_desc_size = ufshcd_get_ucd_size(hba); 3948 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3949 3950 for (i = 0; i < hba->nutrs; i++) { 3951 /* Configure UTRD with command descriptor base address */ 3952 cmd_desc_element_addr = 3953 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3954 utrdlp[i].command_desc_base_addr = 3955 cpu_to_le64(cmd_desc_element_addr); 3956 3957 /* Response upiu and prdt offset should be in double words */ 3958 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3959 utrdlp[i].response_upiu_offset = 3960 cpu_to_le16(response_offset); 3961 utrdlp[i].prd_table_offset = 3962 cpu_to_le16(prdt_offset); 3963 utrdlp[i].response_upiu_length = 3964 cpu_to_le16(ALIGNED_UPIU_SIZE); 3965 } else { 3966 utrdlp[i].response_upiu_offset = 3967 cpu_to_le16(response_offset >> 2); 3968 utrdlp[i].prd_table_offset = 3969 cpu_to_le16(prdt_offset >> 2); 3970 utrdlp[i].response_upiu_length = 3971 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 3972 } 3973 3974 ufshcd_init_lrb(hba, &hba->lrb[i], i); 3975 } 3976 } 3977 3978 /** 3979 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 3980 * @hba: per adapter instance 3981 * 3982 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 3983 * in order to initialize the Unipro link startup procedure. 3984 * Once the Unipro links are up, the device connected to the controller 3985 * is detected. 3986 * 3987 * Return: 0 on success, non-zero value on failure. 3988 */ 3989 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 3990 { 3991 struct uic_command uic_cmd = {0}; 3992 int ret; 3993 3994 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 3995 3996 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3997 if (ret) 3998 dev_dbg(hba->dev, 3999 "dme-link-startup: error code %d\n", ret); 4000 return ret; 4001 } 4002 /** 4003 * ufshcd_dme_reset - UIC command for DME_RESET 4004 * @hba: per adapter instance 4005 * 4006 * DME_RESET command is issued in order to reset UniPro stack. 4007 * This function now deals with cold reset. 4008 * 4009 * Return: 0 on success, non-zero value on failure. 4010 */ 4011 static int ufshcd_dme_reset(struct ufs_hba *hba) 4012 { 4013 struct uic_command uic_cmd = {0}; 4014 int ret; 4015 4016 uic_cmd.command = UIC_CMD_DME_RESET; 4017 4018 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4019 if (ret) 4020 dev_err(hba->dev, 4021 "dme-reset: error code %d\n", ret); 4022 4023 return ret; 4024 } 4025 4026 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 4027 int agreed_gear, 4028 int adapt_val) 4029 { 4030 int ret; 4031 4032 if (agreed_gear < UFS_HS_G4) 4033 adapt_val = PA_NO_ADAPT; 4034 4035 ret = ufshcd_dme_set(hba, 4036 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 4037 adapt_val); 4038 return ret; 4039 } 4040 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 4041 4042 /** 4043 * ufshcd_dme_enable - UIC command for DME_ENABLE 4044 * @hba: per adapter instance 4045 * 4046 * DME_ENABLE command is issued in order to enable UniPro stack. 4047 * 4048 * Return: 0 on success, non-zero value on failure. 4049 */ 4050 static int ufshcd_dme_enable(struct ufs_hba *hba) 4051 { 4052 struct uic_command uic_cmd = {0}; 4053 int ret; 4054 4055 uic_cmd.command = UIC_CMD_DME_ENABLE; 4056 4057 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4058 if (ret) 4059 dev_err(hba->dev, 4060 "dme-enable: error code %d\n", ret); 4061 4062 return ret; 4063 } 4064 4065 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 4066 { 4067 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 4068 unsigned long min_sleep_time_us; 4069 4070 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 4071 return; 4072 4073 /* 4074 * last_dme_cmd_tstamp will be 0 only for 1st call to 4075 * this function 4076 */ 4077 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 4078 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 4079 } else { 4080 unsigned long delta = 4081 (unsigned long) ktime_to_us( 4082 ktime_sub(ktime_get(), 4083 hba->last_dme_cmd_tstamp)); 4084 4085 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 4086 min_sleep_time_us = 4087 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 4088 else 4089 return; /* no more delay required */ 4090 } 4091 4092 /* allow sleep for extra 50us if needed */ 4093 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 4094 } 4095 4096 /** 4097 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 4098 * @hba: per adapter instance 4099 * @attr_sel: uic command argument1 4100 * @attr_set: attribute set type as uic command argument2 4101 * @mib_val: setting value as uic command argument3 4102 * @peer: indicate whether peer or local 4103 * 4104 * Return: 0 on success, non-zero value on failure. 4105 */ 4106 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 4107 u8 attr_set, u32 mib_val, u8 peer) 4108 { 4109 struct uic_command uic_cmd = {0}; 4110 static const char *const action[] = { 4111 "dme-set", 4112 "dme-peer-set" 4113 }; 4114 const char *set = action[!!peer]; 4115 int ret; 4116 int retries = UFS_UIC_COMMAND_RETRIES; 4117 4118 uic_cmd.command = peer ? 4119 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 4120 uic_cmd.argument1 = attr_sel; 4121 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 4122 uic_cmd.argument3 = mib_val; 4123 4124 do { 4125 /* for peer attributes we retry upon failure */ 4126 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4127 if (ret) 4128 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4129 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4130 } while (ret && peer && --retries); 4131 4132 if (ret) 4133 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4134 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4135 UFS_UIC_COMMAND_RETRIES - retries); 4136 4137 return ret; 4138 } 4139 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4140 4141 /** 4142 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4143 * @hba: per adapter instance 4144 * @attr_sel: uic command argument1 4145 * @mib_val: the value of the attribute as returned by the UIC command 4146 * @peer: indicate whether peer or local 4147 * 4148 * Return: 0 on success, non-zero value on failure. 4149 */ 4150 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4151 u32 *mib_val, u8 peer) 4152 { 4153 struct uic_command uic_cmd = {0}; 4154 static const char *const action[] = { 4155 "dme-get", 4156 "dme-peer-get" 4157 }; 4158 const char *get = action[!!peer]; 4159 int ret; 4160 int retries = UFS_UIC_COMMAND_RETRIES; 4161 struct ufs_pa_layer_attr orig_pwr_info; 4162 struct ufs_pa_layer_attr temp_pwr_info; 4163 bool pwr_mode_change = false; 4164 4165 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4166 orig_pwr_info = hba->pwr_info; 4167 temp_pwr_info = orig_pwr_info; 4168 4169 if (orig_pwr_info.pwr_tx == FAST_MODE || 4170 orig_pwr_info.pwr_rx == FAST_MODE) { 4171 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4172 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4173 pwr_mode_change = true; 4174 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4175 orig_pwr_info.pwr_rx == SLOW_MODE) { 4176 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4177 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4178 pwr_mode_change = true; 4179 } 4180 if (pwr_mode_change) { 4181 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4182 if (ret) 4183 goto out; 4184 } 4185 } 4186 4187 uic_cmd.command = peer ? 4188 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 4189 uic_cmd.argument1 = attr_sel; 4190 4191 do { 4192 /* for peer attributes we retry upon failure */ 4193 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4194 if (ret) 4195 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4196 get, UIC_GET_ATTR_ID(attr_sel), ret); 4197 } while (ret && peer && --retries); 4198 4199 if (ret) 4200 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4201 get, UIC_GET_ATTR_ID(attr_sel), 4202 UFS_UIC_COMMAND_RETRIES - retries); 4203 4204 if (mib_val && !ret) 4205 *mib_val = uic_cmd.argument3; 4206 4207 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4208 && pwr_mode_change) 4209 ufshcd_change_power_mode(hba, &orig_pwr_info); 4210 out: 4211 return ret; 4212 } 4213 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4214 4215 /** 4216 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4217 * state) and waits for it to take effect. 4218 * 4219 * @hba: per adapter instance 4220 * @cmd: UIC command to execute 4221 * 4222 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4223 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4224 * and device UniPro link and hence it's final completion would be indicated by 4225 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4226 * addition to normal UIC command completion Status (UCCS). This function only 4227 * returns after the relevant status bits indicate the completion. 4228 * 4229 * Return: 0 on success, non-zero value on failure. 4230 */ 4231 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4232 { 4233 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4234 unsigned long flags; 4235 u8 status; 4236 int ret; 4237 bool reenable_intr = false; 4238 4239 mutex_lock(&hba->uic_cmd_mutex); 4240 ufshcd_add_delay_before_dme_cmd(hba); 4241 4242 spin_lock_irqsave(hba->host->host_lock, flags); 4243 if (ufshcd_is_link_broken(hba)) { 4244 ret = -ENOLINK; 4245 goto out_unlock; 4246 } 4247 hba->uic_async_done = &uic_async_done; 4248 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4249 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4250 /* 4251 * Make sure UIC command completion interrupt is disabled before 4252 * issuing UIC command. 4253 */ 4254 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 4255 reenable_intr = true; 4256 } 4257 spin_unlock_irqrestore(hba->host->host_lock, flags); 4258 ret = __ufshcd_send_uic_cmd(hba, cmd, false); 4259 if (ret) { 4260 dev_err(hba->dev, 4261 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4262 cmd->command, cmd->argument3, ret); 4263 goto out; 4264 } 4265 4266 if (!wait_for_completion_timeout(hba->uic_async_done, 4267 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 4268 dev_err(hba->dev, 4269 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4270 cmd->command, cmd->argument3); 4271 4272 if (!cmd->cmd_active) { 4273 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4274 __func__); 4275 goto check_upmcrs; 4276 } 4277 4278 ret = -ETIMEDOUT; 4279 goto out; 4280 } 4281 4282 check_upmcrs: 4283 status = ufshcd_get_upmcrs(hba); 4284 if (status != PWR_LOCAL) { 4285 dev_err(hba->dev, 4286 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4287 cmd->command, status); 4288 ret = (status != PWR_OK) ? status : -1; 4289 } 4290 out: 4291 if (ret) { 4292 ufshcd_print_host_state(hba); 4293 ufshcd_print_pwr_info(hba); 4294 ufshcd_print_evt_hist(hba); 4295 } 4296 4297 spin_lock_irqsave(hba->host->host_lock, flags); 4298 hba->active_uic_cmd = NULL; 4299 hba->uic_async_done = NULL; 4300 if (reenable_intr) 4301 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4302 if (ret) { 4303 ufshcd_set_link_broken(hba); 4304 ufshcd_schedule_eh_work(hba); 4305 } 4306 out_unlock: 4307 spin_unlock_irqrestore(hba->host->host_lock, flags); 4308 mutex_unlock(&hba->uic_cmd_mutex); 4309 4310 return ret; 4311 } 4312 4313 /** 4314 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4315 * using DME_SET primitives. 4316 * @hba: per adapter instance 4317 * @mode: powr mode value 4318 * 4319 * Return: 0 on success, non-zero value on failure. 4320 */ 4321 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4322 { 4323 struct uic_command uic_cmd = {0}; 4324 int ret; 4325 4326 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4327 ret = ufshcd_dme_set(hba, 4328 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4329 if (ret) { 4330 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4331 __func__, ret); 4332 goto out; 4333 } 4334 } 4335 4336 uic_cmd.command = UIC_CMD_DME_SET; 4337 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 4338 uic_cmd.argument3 = mode; 4339 ufshcd_hold(hba); 4340 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4341 ufshcd_release(hba); 4342 4343 out: 4344 return ret; 4345 } 4346 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4347 4348 int ufshcd_link_recovery(struct ufs_hba *hba) 4349 { 4350 int ret; 4351 unsigned long flags; 4352 4353 spin_lock_irqsave(hba->host->host_lock, flags); 4354 hba->ufshcd_state = UFSHCD_STATE_RESET; 4355 ufshcd_set_eh_in_progress(hba); 4356 spin_unlock_irqrestore(hba->host->host_lock, flags); 4357 4358 /* Reset the attached device */ 4359 ufshcd_device_reset(hba); 4360 4361 ret = ufshcd_host_reset_and_restore(hba); 4362 4363 spin_lock_irqsave(hba->host->host_lock, flags); 4364 if (ret) 4365 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4366 ufshcd_clear_eh_in_progress(hba); 4367 spin_unlock_irqrestore(hba->host->host_lock, flags); 4368 4369 if (ret) 4370 dev_err(hba->dev, "%s: link recovery failed, err %d", 4371 __func__, ret); 4372 4373 return ret; 4374 } 4375 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4376 4377 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4378 { 4379 int ret; 4380 struct uic_command uic_cmd = {0}; 4381 ktime_t start = ktime_get(); 4382 4383 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4384 4385 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER; 4386 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4387 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4388 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4389 4390 if (ret) 4391 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4392 __func__, ret); 4393 else 4394 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4395 POST_CHANGE); 4396 4397 return ret; 4398 } 4399 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4400 4401 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4402 { 4403 struct uic_command uic_cmd = {0}; 4404 int ret; 4405 ktime_t start = ktime_get(); 4406 4407 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4408 4409 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT; 4410 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4411 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4412 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4413 4414 if (ret) { 4415 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4416 __func__, ret); 4417 } else { 4418 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4419 POST_CHANGE); 4420 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4421 hba->ufs_stats.hibern8_exit_cnt++; 4422 } 4423 4424 return ret; 4425 } 4426 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4427 4428 static void ufshcd_configure_auto_hibern8(struct ufs_hba *hba) 4429 { 4430 if (!ufshcd_is_auto_hibern8_supported(hba)) 4431 return; 4432 4433 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4434 } 4435 4436 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4437 { 4438 const u32 cur_ahit = READ_ONCE(hba->ahit); 4439 4440 if (!ufshcd_is_auto_hibern8_supported(hba) || cur_ahit == ahit) 4441 return; 4442 4443 WRITE_ONCE(hba->ahit, ahit); 4444 if (!pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4445 ufshcd_rpm_get_sync(hba); 4446 ufshcd_hold(hba); 4447 ufshcd_configure_auto_hibern8(hba); 4448 ufshcd_release(hba); 4449 ufshcd_rpm_put_sync(hba); 4450 } 4451 } 4452 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4453 4454 /** 4455 * ufshcd_init_pwr_info - setting the POR (power on reset) 4456 * values in hba power info 4457 * @hba: per-adapter instance 4458 */ 4459 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4460 { 4461 hba->pwr_info.gear_rx = UFS_PWM_G1; 4462 hba->pwr_info.gear_tx = UFS_PWM_G1; 4463 hba->pwr_info.lane_rx = UFS_LANE_1; 4464 hba->pwr_info.lane_tx = UFS_LANE_1; 4465 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4466 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4467 hba->pwr_info.hs_rate = 0; 4468 } 4469 4470 /** 4471 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4472 * @hba: per-adapter instance 4473 * 4474 * Return: 0 upon success; < 0 upon failure. 4475 */ 4476 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4477 { 4478 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4479 4480 if (hba->max_pwr_info.is_valid) 4481 return 0; 4482 4483 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4484 pwr_info->pwr_tx = FASTAUTO_MODE; 4485 pwr_info->pwr_rx = FASTAUTO_MODE; 4486 } else { 4487 pwr_info->pwr_tx = FAST_MODE; 4488 pwr_info->pwr_rx = FAST_MODE; 4489 } 4490 pwr_info->hs_rate = PA_HS_MODE_B; 4491 4492 /* Get the connected lane count */ 4493 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4494 &pwr_info->lane_rx); 4495 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4496 &pwr_info->lane_tx); 4497 4498 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4499 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4500 __func__, 4501 pwr_info->lane_rx, 4502 pwr_info->lane_tx); 4503 return -EINVAL; 4504 } 4505 4506 /* 4507 * First, get the maximum gears of HS speed. 4508 * If a zero value, it means there is no HSGEAR capability. 4509 * Then, get the maximum gears of PWM speed. 4510 */ 4511 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4512 if (!pwr_info->gear_rx) { 4513 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4514 &pwr_info->gear_rx); 4515 if (!pwr_info->gear_rx) { 4516 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4517 __func__, pwr_info->gear_rx); 4518 return -EINVAL; 4519 } 4520 pwr_info->pwr_rx = SLOW_MODE; 4521 } 4522 4523 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4524 &pwr_info->gear_tx); 4525 if (!pwr_info->gear_tx) { 4526 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4527 &pwr_info->gear_tx); 4528 if (!pwr_info->gear_tx) { 4529 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4530 __func__, pwr_info->gear_tx); 4531 return -EINVAL; 4532 } 4533 pwr_info->pwr_tx = SLOW_MODE; 4534 } 4535 4536 hba->max_pwr_info.is_valid = true; 4537 return 0; 4538 } 4539 4540 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4541 struct ufs_pa_layer_attr *pwr_mode) 4542 { 4543 int ret; 4544 4545 /* if already configured to the requested pwr_mode */ 4546 if (!hba->force_pmc && 4547 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4548 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4549 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4550 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4551 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4552 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4553 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4554 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4555 return 0; 4556 } 4557 4558 /* 4559 * Configure attributes for power mode change with below. 4560 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4561 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4562 * - PA_HSSERIES 4563 */ 4564 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4565 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4566 pwr_mode->lane_rx); 4567 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4568 pwr_mode->pwr_rx == FAST_MODE) 4569 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4570 else 4571 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4572 4573 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4574 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4575 pwr_mode->lane_tx); 4576 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4577 pwr_mode->pwr_tx == FAST_MODE) 4578 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4579 else 4580 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4581 4582 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4583 pwr_mode->pwr_tx == FASTAUTO_MODE || 4584 pwr_mode->pwr_rx == FAST_MODE || 4585 pwr_mode->pwr_tx == FAST_MODE) 4586 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4587 pwr_mode->hs_rate); 4588 4589 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4590 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4591 DL_FC0ProtectionTimeOutVal_Default); 4592 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4593 DL_TC0ReplayTimeOutVal_Default); 4594 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4595 DL_AFC0ReqTimeOutVal_Default); 4596 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4597 DL_FC1ProtectionTimeOutVal_Default); 4598 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4599 DL_TC1ReplayTimeOutVal_Default); 4600 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4601 DL_AFC1ReqTimeOutVal_Default); 4602 4603 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4604 DL_FC0ProtectionTimeOutVal_Default); 4605 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4606 DL_TC0ReplayTimeOutVal_Default); 4607 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4608 DL_AFC0ReqTimeOutVal_Default); 4609 } 4610 4611 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4612 | pwr_mode->pwr_tx); 4613 4614 if (ret) { 4615 dev_err(hba->dev, 4616 "%s: power mode change failed %d\n", __func__, ret); 4617 } else { 4618 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4619 pwr_mode); 4620 4621 memcpy(&hba->pwr_info, pwr_mode, 4622 sizeof(struct ufs_pa_layer_attr)); 4623 } 4624 4625 return ret; 4626 } 4627 4628 /** 4629 * ufshcd_config_pwr_mode - configure a new power mode 4630 * @hba: per-adapter instance 4631 * @desired_pwr_mode: desired power configuration 4632 * 4633 * Return: 0 upon success; < 0 upon failure. 4634 */ 4635 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4636 struct ufs_pa_layer_attr *desired_pwr_mode) 4637 { 4638 struct ufs_pa_layer_attr final_params = { 0 }; 4639 int ret; 4640 4641 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4642 desired_pwr_mode, &final_params); 4643 4644 if (ret) 4645 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4646 4647 ret = ufshcd_change_power_mode(hba, &final_params); 4648 4649 return ret; 4650 } 4651 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4652 4653 /** 4654 * ufshcd_complete_dev_init() - checks device readiness 4655 * @hba: per-adapter instance 4656 * 4657 * Set fDeviceInit flag and poll until device toggles it. 4658 * 4659 * Return: 0 upon success; < 0 upon failure. 4660 */ 4661 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4662 { 4663 int err; 4664 bool flag_res = true; 4665 ktime_t timeout; 4666 4667 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4668 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4669 if (err) { 4670 dev_err(hba->dev, 4671 "%s: setting fDeviceInit flag failed with error %d\n", 4672 __func__, err); 4673 goto out; 4674 } 4675 4676 /* Poll fDeviceInit flag to be cleared */ 4677 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4678 do { 4679 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4680 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4681 if (!flag_res) 4682 break; 4683 usleep_range(500, 1000); 4684 } while (ktime_before(ktime_get(), timeout)); 4685 4686 if (err) { 4687 dev_err(hba->dev, 4688 "%s: reading fDeviceInit flag failed with error %d\n", 4689 __func__, err); 4690 } else if (flag_res) { 4691 dev_err(hba->dev, 4692 "%s: fDeviceInit was not cleared by the device\n", 4693 __func__); 4694 err = -EBUSY; 4695 } 4696 out: 4697 return err; 4698 } 4699 4700 /** 4701 * ufshcd_make_hba_operational - Make UFS controller operational 4702 * @hba: per adapter instance 4703 * 4704 * To bring UFS host controller to operational state, 4705 * 1. Enable required interrupts 4706 * 2. Configure interrupt aggregation 4707 * 3. Program UTRL and UTMRL base address 4708 * 4. Configure run-stop-registers 4709 * 4710 * Return: 0 on success, non-zero value on failure. 4711 */ 4712 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4713 { 4714 int err = 0; 4715 u32 reg; 4716 4717 /* Enable required interrupts */ 4718 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4719 4720 /* Configure interrupt aggregation */ 4721 if (ufshcd_is_intr_aggr_allowed(hba)) 4722 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4723 else 4724 ufshcd_disable_intr_aggr(hba); 4725 4726 /* Configure UTRL and UTMRL base address registers */ 4727 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4728 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4729 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4730 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4731 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4732 REG_UTP_TASK_REQ_LIST_BASE_L); 4733 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4734 REG_UTP_TASK_REQ_LIST_BASE_H); 4735 4736 /* 4737 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4738 */ 4739 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4740 if (!(ufshcd_get_lists_status(reg))) { 4741 ufshcd_enable_run_stop_reg(hba); 4742 } else { 4743 dev_err(hba->dev, 4744 "Host controller not ready to process requests"); 4745 err = -EIO; 4746 } 4747 4748 return err; 4749 } 4750 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4751 4752 /** 4753 * ufshcd_hba_stop - Send controller to reset state 4754 * @hba: per adapter instance 4755 */ 4756 void ufshcd_hba_stop(struct ufs_hba *hba) 4757 { 4758 unsigned long flags; 4759 int err; 4760 4761 /* 4762 * Obtain the host lock to prevent that the controller is disabled 4763 * while the UFS interrupt handler is active on another CPU. 4764 */ 4765 spin_lock_irqsave(hba->host->host_lock, flags); 4766 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4767 spin_unlock_irqrestore(hba->host->host_lock, flags); 4768 4769 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4770 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4771 10, 1); 4772 if (err) 4773 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4774 } 4775 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4776 4777 /** 4778 * ufshcd_hba_execute_hce - initialize the controller 4779 * @hba: per adapter instance 4780 * 4781 * The controller resets itself and controller firmware initialization 4782 * sequence kicks off. When controller is ready it will set 4783 * the Host Controller Enable bit to 1. 4784 * 4785 * Return: 0 on success, non-zero value on failure. 4786 */ 4787 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4788 { 4789 int retry_outer = 3; 4790 int retry_inner; 4791 4792 start: 4793 if (ufshcd_is_hba_active(hba)) 4794 /* change controller state to "reset state" */ 4795 ufshcd_hba_stop(hba); 4796 4797 /* UniPro link is disabled at this point */ 4798 ufshcd_set_link_off(hba); 4799 4800 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4801 4802 /* start controller initialization sequence */ 4803 ufshcd_hba_start(hba); 4804 4805 /* 4806 * To initialize a UFS host controller HCE bit must be set to 1. 4807 * During initialization the HCE bit value changes from 1->0->1. 4808 * When the host controller completes initialization sequence 4809 * it sets the value of HCE bit to 1. The same HCE bit is read back 4810 * to check if the controller has completed initialization sequence. 4811 * So without this delay the value HCE = 1, set in the previous 4812 * instruction might be read back. 4813 * This delay can be changed based on the controller. 4814 */ 4815 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4816 4817 /* wait for the host controller to complete initialization */ 4818 retry_inner = 50; 4819 while (!ufshcd_is_hba_active(hba)) { 4820 if (retry_inner) { 4821 retry_inner--; 4822 } else { 4823 dev_err(hba->dev, 4824 "Controller enable failed\n"); 4825 if (retry_outer) { 4826 retry_outer--; 4827 goto start; 4828 } 4829 return -EIO; 4830 } 4831 usleep_range(1000, 1100); 4832 } 4833 4834 /* enable UIC related interrupts */ 4835 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4836 4837 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4838 4839 return 0; 4840 } 4841 4842 int ufshcd_hba_enable(struct ufs_hba *hba) 4843 { 4844 int ret; 4845 4846 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4847 ufshcd_set_link_off(hba); 4848 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4849 4850 /* enable UIC related interrupts */ 4851 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4852 ret = ufshcd_dme_reset(hba); 4853 if (ret) { 4854 dev_err(hba->dev, "DME_RESET failed\n"); 4855 return ret; 4856 } 4857 4858 ret = ufshcd_dme_enable(hba); 4859 if (ret) { 4860 dev_err(hba->dev, "Enabling DME failed\n"); 4861 return ret; 4862 } 4863 4864 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4865 } else { 4866 ret = ufshcd_hba_execute_hce(hba); 4867 } 4868 4869 return ret; 4870 } 4871 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4872 4873 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4874 { 4875 int tx_lanes = 0, i, err = 0; 4876 4877 if (!peer) 4878 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4879 &tx_lanes); 4880 else 4881 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4882 &tx_lanes); 4883 for (i = 0; i < tx_lanes; i++) { 4884 if (!peer) 4885 err = ufshcd_dme_set(hba, 4886 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4887 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4888 0); 4889 else 4890 err = ufshcd_dme_peer_set(hba, 4891 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4892 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4893 0); 4894 if (err) { 4895 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4896 __func__, peer, i, err); 4897 break; 4898 } 4899 } 4900 4901 return err; 4902 } 4903 4904 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4905 { 4906 return ufshcd_disable_tx_lcc(hba, true); 4907 } 4908 4909 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4910 { 4911 struct ufs_event_hist *e; 4912 4913 if (id >= UFS_EVT_CNT) 4914 return; 4915 4916 e = &hba->ufs_stats.event[id]; 4917 e->val[e->pos] = val; 4918 e->tstamp[e->pos] = local_clock(); 4919 e->cnt += 1; 4920 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4921 4922 ufshcd_vops_event_notify(hba, id, &val); 4923 } 4924 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4925 4926 /** 4927 * ufshcd_link_startup - Initialize unipro link startup 4928 * @hba: per adapter instance 4929 * 4930 * Return: 0 for success, non-zero in case of failure. 4931 */ 4932 static int ufshcd_link_startup(struct ufs_hba *hba) 4933 { 4934 int ret; 4935 int retries = DME_LINKSTARTUP_RETRIES; 4936 bool link_startup_again = false; 4937 4938 /* 4939 * If UFS device isn't active then we will have to issue link startup 4940 * 2 times to make sure the device state move to active. 4941 */ 4942 if (!ufshcd_is_ufs_dev_active(hba)) 4943 link_startup_again = true; 4944 4945 link_startup: 4946 do { 4947 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4948 4949 ret = ufshcd_dme_link_startup(hba); 4950 4951 /* check if device is detected by inter-connect layer */ 4952 if (!ret && !ufshcd_is_device_present(hba)) { 4953 ufshcd_update_evt_hist(hba, 4954 UFS_EVT_LINK_STARTUP_FAIL, 4955 0); 4956 dev_err(hba->dev, "%s: Device not present\n", __func__); 4957 ret = -ENXIO; 4958 goto out; 4959 } 4960 4961 /* 4962 * DME link lost indication is only received when link is up, 4963 * but we can't be sure if the link is up until link startup 4964 * succeeds. So reset the local Uni-Pro and try again. 4965 */ 4966 if (ret && retries && ufshcd_hba_enable(hba)) { 4967 ufshcd_update_evt_hist(hba, 4968 UFS_EVT_LINK_STARTUP_FAIL, 4969 (u32)ret); 4970 goto out; 4971 } 4972 } while (ret && retries--); 4973 4974 if (ret) { 4975 /* failed to get the link up... retire */ 4976 ufshcd_update_evt_hist(hba, 4977 UFS_EVT_LINK_STARTUP_FAIL, 4978 (u32)ret); 4979 goto out; 4980 } 4981 4982 if (link_startup_again) { 4983 link_startup_again = false; 4984 retries = DME_LINKSTARTUP_RETRIES; 4985 goto link_startup; 4986 } 4987 4988 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 4989 ufshcd_init_pwr_info(hba); 4990 ufshcd_print_pwr_info(hba); 4991 4992 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 4993 ret = ufshcd_disable_device_tx_lcc(hba); 4994 if (ret) 4995 goto out; 4996 } 4997 4998 /* Include any host controller configuration via UIC commands */ 4999 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 5000 if (ret) 5001 goto out; 5002 5003 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 5004 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 5005 ret = ufshcd_make_hba_operational(hba); 5006 out: 5007 if (ret) { 5008 dev_err(hba->dev, "link startup failed %d\n", ret); 5009 ufshcd_print_host_state(hba); 5010 ufshcd_print_pwr_info(hba); 5011 ufshcd_print_evt_hist(hba); 5012 } 5013 return ret; 5014 } 5015 5016 /** 5017 * ufshcd_verify_dev_init() - Verify device initialization 5018 * @hba: per-adapter instance 5019 * 5020 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 5021 * device Transport Protocol (UTP) layer is ready after a reset. 5022 * If the UTP layer at the device side is not initialized, it may 5023 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 5024 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 5025 * 5026 * Return: 0 upon success; < 0 upon failure. 5027 */ 5028 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 5029 { 5030 int err = 0; 5031 int retries; 5032 5033 ufshcd_dev_man_lock(hba); 5034 5035 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 5036 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 5037 hba->nop_out_timeout); 5038 5039 if (!err || err == -ETIMEDOUT) 5040 break; 5041 5042 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 5043 } 5044 5045 ufshcd_dev_man_unlock(hba); 5046 5047 if (err) 5048 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 5049 return err; 5050 } 5051 5052 /** 5053 * ufshcd_setup_links - associate link b/w device wlun and other luns 5054 * @sdev: pointer to SCSI device 5055 * @hba: pointer to ufs hba 5056 */ 5057 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 5058 { 5059 struct device_link *link; 5060 5061 /* 5062 * Device wlun is the supplier & rest of the luns are consumers. 5063 * This ensures that device wlun suspends after all other luns. 5064 */ 5065 if (hba->ufs_device_wlun) { 5066 link = device_link_add(&sdev->sdev_gendev, 5067 &hba->ufs_device_wlun->sdev_gendev, 5068 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 5069 if (!link) { 5070 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 5071 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 5072 return; 5073 } 5074 hba->luns_avail--; 5075 /* Ignore REPORT_LUN wlun probing */ 5076 if (hba->luns_avail == 1) { 5077 ufshcd_rpm_put(hba); 5078 return; 5079 } 5080 } else { 5081 /* 5082 * Device wlun is probed. The assumption is that WLUNs are 5083 * scanned before other LUNs. 5084 */ 5085 hba->luns_avail--; 5086 } 5087 } 5088 5089 /** 5090 * ufshcd_lu_init - Initialize the relevant parameters of the LU 5091 * @hba: per-adapter instance 5092 * @sdev: pointer to SCSI device 5093 */ 5094 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 5095 { 5096 int len = QUERY_DESC_MAX_SIZE; 5097 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 5098 u8 lun_qdepth = hba->nutrs; 5099 u8 *desc_buf; 5100 int ret; 5101 5102 desc_buf = kzalloc(len, GFP_KERNEL); 5103 if (!desc_buf) 5104 goto set_qdepth; 5105 5106 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5107 if (ret < 0) { 5108 if (ret == -EOPNOTSUPP) 5109 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5110 lun_qdepth = 1; 5111 kfree(desc_buf); 5112 goto set_qdepth; 5113 } 5114 5115 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5116 /* 5117 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5118 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5119 */ 5120 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5121 } 5122 /* 5123 * According to UFS device specification, the write protection mode is only supported by 5124 * normal LU, not supported by WLUN. 5125 */ 5126 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5127 !hba->dev_info.is_lu_power_on_wp && 5128 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5129 hba->dev_info.is_lu_power_on_wp = true; 5130 5131 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5132 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5133 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5134 hba->dev_info.b_advanced_rpmb_en = true; 5135 5136 5137 kfree(desc_buf); 5138 set_qdepth: 5139 /* 5140 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5141 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5142 */ 5143 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5144 scsi_change_queue_depth(sdev, lun_qdepth); 5145 } 5146 5147 /** 5148 * ufshcd_slave_alloc - handle initial SCSI device configurations 5149 * @sdev: pointer to SCSI device 5150 * 5151 * Return: success. 5152 */ 5153 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5154 { 5155 struct ufs_hba *hba; 5156 5157 hba = shost_priv(sdev->host); 5158 5159 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5160 sdev->use_10_for_ms = 1; 5161 5162 /* DBD field should be set to 1 in mode sense(10) */ 5163 sdev->set_dbd_for_ms = 1; 5164 5165 /* allow SCSI layer to restart the device in case of errors */ 5166 sdev->allow_restart = 1; 5167 5168 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5169 sdev->no_report_opcodes = 1; 5170 5171 /* WRITE_SAME command is not supported */ 5172 sdev->no_write_same = 1; 5173 5174 ufshcd_lu_init(hba, sdev); 5175 5176 ufshcd_setup_links(hba, sdev); 5177 5178 return 0; 5179 } 5180 5181 /** 5182 * ufshcd_change_queue_depth - change queue depth 5183 * @sdev: pointer to SCSI device 5184 * @depth: required depth to set 5185 * 5186 * Change queue depth and make sure the max. limits are not crossed. 5187 * 5188 * Return: new queue depth. 5189 */ 5190 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5191 { 5192 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5193 } 5194 5195 /** 5196 * ufshcd_device_configure - adjust SCSI device configurations 5197 * @sdev: pointer to SCSI device 5198 * @lim: queue limits 5199 * 5200 * Return: 0 (success). 5201 */ 5202 static int ufshcd_device_configure(struct scsi_device *sdev, 5203 struct queue_limits *lim) 5204 { 5205 struct ufs_hba *hba = shost_priv(sdev->host); 5206 struct request_queue *q = sdev->request_queue; 5207 5208 lim->dma_pad_mask = PRDT_DATA_BYTE_COUNT_PAD - 1; 5209 5210 /* 5211 * Block runtime-pm until all consumers are added. 5212 * Refer ufshcd_setup_links(). 5213 */ 5214 if (is_device_wlun(sdev)) 5215 pm_runtime_get_noresume(&sdev->sdev_gendev); 5216 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5217 sdev->rpm_autosuspend = 1; 5218 /* 5219 * Do not print messages during runtime PM to avoid never-ending cycles 5220 * of messages written back to storage by user space causing runtime 5221 * resume, causing more messages and so on. 5222 */ 5223 sdev->silence_suspend = 1; 5224 5225 ufshcd_crypto_register(hba, q); 5226 5227 return 0; 5228 } 5229 5230 /** 5231 * ufshcd_slave_destroy - remove SCSI device configurations 5232 * @sdev: pointer to SCSI device 5233 */ 5234 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5235 { 5236 struct ufs_hba *hba; 5237 unsigned long flags; 5238 5239 hba = shost_priv(sdev->host); 5240 5241 /* Drop the reference as it won't be needed anymore */ 5242 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5243 spin_lock_irqsave(hba->host->host_lock, flags); 5244 hba->ufs_device_wlun = NULL; 5245 spin_unlock_irqrestore(hba->host->host_lock, flags); 5246 } else if (hba->ufs_device_wlun) { 5247 struct device *supplier = NULL; 5248 5249 /* Ensure UFS Device WLUN exists and does not disappear */ 5250 spin_lock_irqsave(hba->host->host_lock, flags); 5251 if (hba->ufs_device_wlun) { 5252 supplier = &hba->ufs_device_wlun->sdev_gendev; 5253 get_device(supplier); 5254 } 5255 spin_unlock_irqrestore(hba->host->host_lock, flags); 5256 5257 if (supplier) { 5258 /* 5259 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5260 * device will not have been registered but can still 5261 * have a device link holding a reference to the device. 5262 */ 5263 device_link_remove(&sdev->sdev_gendev, supplier); 5264 put_device(supplier); 5265 } 5266 } 5267 } 5268 5269 /** 5270 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5271 * @lrbp: pointer to local reference block of completed command 5272 * @scsi_status: SCSI command status 5273 * 5274 * Return: value base on SCSI command status. 5275 */ 5276 static inline int 5277 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5278 { 5279 int result = 0; 5280 5281 switch (scsi_status) { 5282 case SAM_STAT_CHECK_CONDITION: 5283 ufshcd_copy_sense_data(lrbp); 5284 fallthrough; 5285 case SAM_STAT_GOOD: 5286 result |= DID_OK << 16 | scsi_status; 5287 break; 5288 case SAM_STAT_TASK_SET_FULL: 5289 case SAM_STAT_BUSY: 5290 case SAM_STAT_TASK_ABORTED: 5291 ufshcd_copy_sense_data(lrbp); 5292 result |= scsi_status; 5293 break; 5294 default: 5295 result |= DID_ERROR << 16; 5296 break; 5297 } /* end of switch */ 5298 5299 return result; 5300 } 5301 5302 /** 5303 * ufshcd_transfer_rsp_status - Get overall status of the response 5304 * @hba: per adapter instance 5305 * @lrbp: pointer to local reference block of completed command 5306 * @cqe: pointer to the completion queue entry 5307 * 5308 * Return: result of the command to notify SCSI midlayer. 5309 */ 5310 static inline int 5311 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5312 struct cq_entry *cqe) 5313 { 5314 int result = 0; 5315 int scsi_status; 5316 enum utp_ocs ocs; 5317 u8 upiu_flags; 5318 u32 resid; 5319 5320 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5321 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5322 /* 5323 * Test !overflow instead of underflow to support UFS devices that do 5324 * not set either flag. 5325 */ 5326 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5327 scsi_set_resid(lrbp->cmd, resid); 5328 5329 /* overall command status of utrd */ 5330 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5331 5332 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5333 if (lrbp->ucd_rsp_ptr->header.response || 5334 lrbp->ucd_rsp_ptr->header.status) 5335 ocs = OCS_SUCCESS; 5336 } 5337 5338 switch (ocs) { 5339 case OCS_SUCCESS: 5340 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5341 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5342 case UPIU_TRANSACTION_RESPONSE: 5343 /* 5344 * get the result based on SCSI status response 5345 * to notify the SCSI midlayer of the command status 5346 */ 5347 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5348 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5349 5350 /* 5351 * Currently we are only supporting BKOPs exception 5352 * events hence we can ignore BKOPs exception event 5353 * during power management callbacks. BKOPs exception 5354 * event is not expected to be raised in runtime suspend 5355 * callback as it allows the urgent bkops. 5356 * During system suspend, we are anyway forcefully 5357 * disabling the bkops and if urgent bkops is needed 5358 * it will be enabled on system resume. Long term 5359 * solution could be to abort the system suspend if 5360 * UFS device needs urgent BKOPs. 5361 */ 5362 if (!hba->pm_op_in_progress && 5363 !ufshcd_eh_in_progress(hba) && 5364 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5365 /* Flushed in suspend */ 5366 schedule_work(&hba->eeh_work); 5367 break; 5368 case UPIU_TRANSACTION_REJECT_UPIU: 5369 /* TODO: handle Reject UPIU Response */ 5370 result = DID_ERROR << 16; 5371 dev_err(hba->dev, 5372 "Reject UPIU not fully implemented\n"); 5373 break; 5374 default: 5375 dev_err(hba->dev, 5376 "Unexpected request response code = %x\n", 5377 result); 5378 result = DID_ERROR << 16; 5379 break; 5380 } 5381 break; 5382 case OCS_ABORTED: 5383 result |= DID_ABORT << 16; 5384 break; 5385 case OCS_INVALID_COMMAND_STATUS: 5386 result |= DID_REQUEUE << 16; 5387 break; 5388 case OCS_INVALID_CMD_TABLE_ATTR: 5389 case OCS_INVALID_PRDT_ATTR: 5390 case OCS_MISMATCH_DATA_BUF_SIZE: 5391 case OCS_MISMATCH_RESP_UPIU_SIZE: 5392 case OCS_PEER_COMM_FAILURE: 5393 case OCS_FATAL_ERROR: 5394 case OCS_DEVICE_FATAL_ERROR: 5395 case OCS_INVALID_CRYPTO_CONFIG: 5396 case OCS_GENERAL_CRYPTO_ERROR: 5397 default: 5398 result |= DID_ERROR << 16; 5399 dev_err(hba->dev, 5400 "OCS error from controller = %x for tag %d\n", 5401 ocs, lrbp->task_tag); 5402 ufshcd_print_evt_hist(hba); 5403 ufshcd_print_host_state(hba); 5404 break; 5405 } /* end of switch */ 5406 5407 if ((host_byte(result) != DID_OK) && 5408 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5409 ufshcd_print_tr(hba, lrbp->task_tag, true); 5410 return result; 5411 } 5412 5413 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5414 u32 intr_mask) 5415 { 5416 if (!ufshcd_is_auto_hibern8_supported(hba) || 5417 !ufshcd_is_auto_hibern8_enabled(hba)) 5418 return false; 5419 5420 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5421 return false; 5422 5423 if (hba->active_uic_cmd && 5424 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5425 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5426 return false; 5427 5428 return true; 5429 } 5430 5431 /** 5432 * ufshcd_uic_cmd_compl - handle completion of uic command 5433 * @hba: per adapter instance 5434 * @intr_status: interrupt status generated by the controller 5435 * 5436 * Return: 5437 * IRQ_HANDLED - If interrupt is valid 5438 * IRQ_NONE - If invalid interrupt 5439 */ 5440 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5441 { 5442 irqreturn_t retval = IRQ_NONE; 5443 5444 spin_lock(hba->host->host_lock); 5445 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5446 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5447 5448 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { 5449 hba->active_uic_cmd->argument2 |= 5450 ufshcd_get_uic_cmd_result(hba); 5451 hba->active_uic_cmd->argument3 = 5452 ufshcd_get_dme_attr_val(hba); 5453 if (!hba->uic_async_done) 5454 hba->active_uic_cmd->cmd_active = 0; 5455 complete(&hba->active_uic_cmd->done); 5456 retval = IRQ_HANDLED; 5457 } 5458 5459 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { 5460 hba->active_uic_cmd->cmd_active = 0; 5461 complete(hba->uic_async_done); 5462 retval = IRQ_HANDLED; 5463 } 5464 5465 if (retval == IRQ_HANDLED) 5466 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd, 5467 UFS_CMD_COMP); 5468 spin_unlock(hba->host->host_lock); 5469 return retval; 5470 } 5471 5472 /* Release the resources allocated for processing a SCSI command. */ 5473 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5474 struct ufshcd_lrb *lrbp) 5475 { 5476 struct scsi_cmnd *cmd = lrbp->cmd; 5477 5478 scsi_dma_unmap(cmd); 5479 ufshcd_release(hba); 5480 ufshcd_clk_scaling_update_busy(hba); 5481 } 5482 5483 /** 5484 * ufshcd_compl_one_cqe - handle a completion queue entry 5485 * @hba: per adapter instance 5486 * @task_tag: the task tag of the request to be completed 5487 * @cqe: pointer to the completion queue entry 5488 */ 5489 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5490 struct cq_entry *cqe) 5491 { 5492 struct ufshcd_lrb *lrbp; 5493 struct scsi_cmnd *cmd; 5494 enum utp_ocs ocs; 5495 5496 lrbp = &hba->lrb[task_tag]; 5497 lrbp->compl_time_stamp = ktime_get(); 5498 cmd = lrbp->cmd; 5499 if (cmd) { 5500 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5501 ufshcd_update_monitor(hba, lrbp); 5502 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5503 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5504 ufshcd_release_scsi_cmd(hba, lrbp); 5505 /* Do not touch lrbp after scsi done */ 5506 scsi_done(cmd); 5507 } else if (hba->dev_cmd.complete) { 5508 if (cqe) { 5509 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5510 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5511 } 5512 complete(hba->dev_cmd.complete); 5513 } 5514 } 5515 5516 /** 5517 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5518 * @hba: per adapter instance 5519 * @completed_reqs: bitmask that indicates which requests to complete 5520 */ 5521 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5522 unsigned long completed_reqs) 5523 { 5524 int tag; 5525 5526 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5527 ufshcd_compl_one_cqe(hba, tag, NULL); 5528 } 5529 5530 /* Any value that is not an existing queue number is fine for this constant. */ 5531 enum { 5532 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5533 }; 5534 5535 static void ufshcd_clear_polled(struct ufs_hba *hba, 5536 unsigned long *completed_reqs) 5537 { 5538 int tag; 5539 5540 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5541 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5542 5543 if (!cmd) 5544 continue; 5545 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5546 __clear_bit(tag, completed_reqs); 5547 } 5548 } 5549 5550 /* 5551 * Return: > 0 if one or more commands have been completed or 0 if no 5552 * requests have been completed. 5553 */ 5554 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5555 { 5556 struct ufs_hba *hba = shost_priv(shost); 5557 unsigned long completed_reqs, flags; 5558 u32 tr_doorbell; 5559 struct ufs_hw_queue *hwq; 5560 5561 if (is_mcq_enabled(hba)) { 5562 hwq = &hba->uhq[queue_num]; 5563 5564 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5565 } 5566 5567 spin_lock_irqsave(&hba->outstanding_lock, flags); 5568 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5569 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5570 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5571 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5572 hba->outstanding_reqs); 5573 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5574 /* Do not complete polled requests from interrupt context. */ 5575 ufshcd_clear_polled(hba, &completed_reqs); 5576 } 5577 hba->outstanding_reqs &= ~completed_reqs; 5578 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5579 5580 if (completed_reqs) 5581 __ufshcd_transfer_req_compl(hba, completed_reqs); 5582 5583 return completed_reqs != 0; 5584 } 5585 5586 /** 5587 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5588 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5589 * to complete the pending transfers and free the resources associated with 5590 * the scsi command. 5591 * 5592 * @hba: per adapter instance 5593 * @force_compl: This flag is set to true when invoked 5594 * from ufshcd_host_reset_and_restore() in which case it requires special 5595 * handling because the host controller has been reset by ufshcd_hba_stop(). 5596 */ 5597 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5598 bool force_compl) 5599 { 5600 struct ufs_hw_queue *hwq; 5601 struct ufshcd_lrb *lrbp; 5602 struct scsi_cmnd *cmd; 5603 unsigned long flags; 5604 int tag; 5605 5606 for (tag = 0; tag < hba->nutrs; tag++) { 5607 lrbp = &hba->lrb[tag]; 5608 cmd = lrbp->cmd; 5609 if (!ufshcd_cmd_inflight(cmd) || 5610 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5611 continue; 5612 5613 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 5614 5615 if (force_compl) { 5616 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5617 /* 5618 * For those cmds of which the cqes are not present 5619 * in the cq, complete them explicitly. 5620 */ 5621 spin_lock_irqsave(&hwq->cq_lock, flags); 5622 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5623 set_host_byte(cmd, DID_REQUEUE); 5624 ufshcd_release_scsi_cmd(hba, lrbp); 5625 scsi_done(cmd); 5626 } 5627 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5628 } else { 5629 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5630 } 5631 } 5632 } 5633 5634 /** 5635 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5636 * @hba: per adapter instance 5637 * 5638 * Return: 5639 * IRQ_HANDLED - If interrupt is valid 5640 * IRQ_NONE - If invalid interrupt 5641 */ 5642 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5643 { 5644 /* Resetting interrupt aggregation counters first and reading the 5645 * DOOR_BELL afterward allows us to handle all the completed requests. 5646 * In order to prevent other interrupts starvation the DB is read once 5647 * after reset. The down side of this solution is the possibility of 5648 * false interrupt if device completes another request after resetting 5649 * aggregation and before reading the DB. 5650 */ 5651 if (ufshcd_is_intr_aggr_allowed(hba) && 5652 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5653 ufshcd_reset_intr_aggr(hba); 5654 5655 if (ufs_fail_completion(hba)) 5656 return IRQ_HANDLED; 5657 5658 /* 5659 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5660 * do not want polling to trigger spurious interrupt complaints. 5661 */ 5662 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5663 5664 return IRQ_HANDLED; 5665 } 5666 5667 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5668 { 5669 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5670 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5671 &ee_ctrl_mask); 5672 } 5673 5674 int ufshcd_write_ee_control(struct ufs_hba *hba) 5675 { 5676 int err; 5677 5678 mutex_lock(&hba->ee_ctrl_mutex); 5679 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5680 mutex_unlock(&hba->ee_ctrl_mutex); 5681 if (err) 5682 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5683 __func__, err); 5684 return err; 5685 } 5686 5687 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5688 const u16 *other_mask, u16 set, u16 clr) 5689 { 5690 u16 new_mask, ee_ctrl_mask; 5691 int err = 0; 5692 5693 mutex_lock(&hba->ee_ctrl_mutex); 5694 new_mask = (*mask & ~clr) | set; 5695 ee_ctrl_mask = new_mask | *other_mask; 5696 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5697 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5698 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5699 if (!err) { 5700 hba->ee_ctrl_mask = ee_ctrl_mask; 5701 *mask = new_mask; 5702 } 5703 mutex_unlock(&hba->ee_ctrl_mutex); 5704 return err; 5705 } 5706 5707 /** 5708 * ufshcd_disable_ee - disable exception event 5709 * @hba: per-adapter instance 5710 * @mask: exception event to disable 5711 * 5712 * Disables exception event in the device so that the EVENT_ALERT 5713 * bit is not set. 5714 * 5715 * Return: zero on success, non-zero error value on failure. 5716 */ 5717 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5718 { 5719 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5720 } 5721 5722 /** 5723 * ufshcd_enable_ee - enable exception event 5724 * @hba: per-adapter instance 5725 * @mask: exception event to enable 5726 * 5727 * Enable corresponding exception event in the device to allow 5728 * device to alert host in critical scenarios. 5729 * 5730 * Return: zero on success, non-zero error value on failure. 5731 */ 5732 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5733 { 5734 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5735 } 5736 5737 /** 5738 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5739 * @hba: per-adapter instance 5740 * 5741 * Allow device to manage background operations on its own. Enabling 5742 * this might lead to inconsistent latencies during normal data transfers 5743 * as the device is allowed to manage its own way of handling background 5744 * operations. 5745 * 5746 * Return: zero on success, non-zero on failure. 5747 */ 5748 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5749 { 5750 int err = 0; 5751 5752 if (hba->auto_bkops_enabled) 5753 goto out; 5754 5755 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5756 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5757 if (err) { 5758 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5759 __func__, err); 5760 goto out; 5761 } 5762 5763 hba->auto_bkops_enabled = true; 5764 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5765 5766 /* No need of URGENT_BKOPS exception from the device */ 5767 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5768 if (err) 5769 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5770 __func__, err); 5771 out: 5772 return err; 5773 } 5774 5775 /** 5776 * ufshcd_disable_auto_bkops - block device in doing background operations 5777 * @hba: per-adapter instance 5778 * 5779 * Disabling background operations improves command response latency but 5780 * has drawback of device moving into critical state where the device is 5781 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5782 * host is idle so that BKOPS are managed effectively without any negative 5783 * impacts. 5784 * 5785 * Return: zero on success, non-zero on failure. 5786 */ 5787 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5788 { 5789 int err = 0; 5790 5791 if (!hba->auto_bkops_enabled) 5792 goto out; 5793 5794 /* 5795 * If host assisted BKOPs is to be enabled, make sure 5796 * urgent bkops exception is allowed. 5797 */ 5798 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5799 if (err) { 5800 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5801 __func__, err); 5802 goto out; 5803 } 5804 5805 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5806 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5807 if (err) { 5808 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5809 __func__, err); 5810 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5811 goto out; 5812 } 5813 5814 hba->auto_bkops_enabled = false; 5815 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5816 hba->is_urgent_bkops_lvl_checked = false; 5817 out: 5818 return err; 5819 } 5820 5821 /** 5822 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5823 * @hba: per adapter instance 5824 * 5825 * After a device reset the device may toggle the BKOPS_EN flag 5826 * to default value. The s/w tracking variables should be updated 5827 * as well. This function would change the auto-bkops state based on 5828 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5829 */ 5830 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5831 { 5832 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5833 hba->auto_bkops_enabled = false; 5834 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5835 ufshcd_enable_auto_bkops(hba); 5836 } else { 5837 hba->auto_bkops_enabled = true; 5838 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5839 ufshcd_disable_auto_bkops(hba); 5840 } 5841 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5842 hba->is_urgent_bkops_lvl_checked = false; 5843 } 5844 5845 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5846 { 5847 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5848 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5849 } 5850 5851 /** 5852 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5853 * @hba: per-adapter instance 5854 * @status: bkops_status value 5855 * 5856 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5857 * flag in the device to permit background operations if the device 5858 * bkops_status is greater than or equal to "status" argument passed to 5859 * this function, disable otherwise. 5860 * 5861 * Return: 0 for success, non-zero in case of failure. 5862 * 5863 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5864 * to know whether auto bkops is enabled or disabled after this function 5865 * returns control to it. 5866 */ 5867 static int ufshcd_bkops_ctrl(struct ufs_hba *hba, 5868 enum bkops_status status) 5869 { 5870 int err; 5871 u32 curr_status = 0; 5872 5873 err = ufshcd_get_bkops_status(hba, &curr_status); 5874 if (err) { 5875 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5876 __func__, err); 5877 goto out; 5878 } else if (curr_status > BKOPS_STATUS_MAX) { 5879 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5880 __func__, curr_status); 5881 err = -EINVAL; 5882 goto out; 5883 } 5884 5885 if (curr_status >= status) 5886 err = ufshcd_enable_auto_bkops(hba); 5887 else 5888 err = ufshcd_disable_auto_bkops(hba); 5889 out: 5890 return err; 5891 } 5892 5893 /** 5894 * ufshcd_urgent_bkops - handle urgent bkops exception event 5895 * @hba: per-adapter instance 5896 * 5897 * Enable fBackgroundOpsEn flag in the device to permit background 5898 * operations. 5899 * 5900 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled 5901 * and negative error value for any other failure. 5902 * 5903 * Return: 0 upon success; < 0 upon failure. 5904 */ 5905 static int ufshcd_urgent_bkops(struct ufs_hba *hba) 5906 { 5907 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl); 5908 } 5909 5910 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5911 { 5912 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5913 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5914 } 5915 5916 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5917 { 5918 int err; 5919 u32 curr_status = 0; 5920 5921 if (hba->is_urgent_bkops_lvl_checked) 5922 goto enable_auto_bkops; 5923 5924 err = ufshcd_get_bkops_status(hba, &curr_status); 5925 if (err) { 5926 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5927 __func__, err); 5928 goto out; 5929 } 5930 5931 /* 5932 * We are seeing that some devices are raising the urgent bkops 5933 * exception events even when BKOPS status doesn't indicate performace 5934 * impacted or critical. Handle these device by determining their urgent 5935 * bkops status at runtime. 5936 */ 5937 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5938 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5939 __func__, curr_status); 5940 /* update the current status as the urgent bkops level */ 5941 hba->urgent_bkops_lvl = curr_status; 5942 hba->is_urgent_bkops_lvl_checked = true; 5943 } 5944 5945 enable_auto_bkops: 5946 err = ufshcd_enable_auto_bkops(hba); 5947 out: 5948 if (err < 0) 5949 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5950 __func__, err); 5951 } 5952 5953 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5954 { 5955 u32 value; 5956 5957 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5958 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 5959 return; 5960 5961 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 5962 5963 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 5964 5965 /* 5966 * A placeholder for the platform vendors to add whatever additional 5967 * steps required 5968 */ 5969 } 5970 5971 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 5972 { 5973 u8 index; 5974 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 5975 UPIU_QUERY_OPCODE_CLEAR_FLAG; 5976 5977 index = ufshcd_wb_get_query_index(hba); 5978 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 5979 } 5980 5981 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 5982 { 5983 int ret; 5984 5985 if (!ufshcd_is_wb_allowed(hba) || 5986 hba->dev_info.wb_enabled == enable) 5987 return 0; 5988 5989 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 5990 if (ret) { 5991 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 5992 __func__, enable ? "enabling" : "disabling", ret); 5993 return ret; 5994 } 5995 5996 hba->dev_info.wb_enabled = enable; 5997 dev_dbg(hba->dev, "%s: Write Booster %s\n", 5998 __func__, enable ? "enabled" : "disabled"); 5999 6000 return ret; 6001 } 6002 6003 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 6004 bool enable) 6005 { 6006 int ret; 6007 6008 ret = __ufshcd_wb_toggle(hba, enable, 6009 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 6010 if (ret) { 6011 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 6012 __func__, enable ? "enabling" : "disabling", ret); 6013 return; 6014 } 6015 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 6016 __func__, enable ? "enabled" : "disabled"); 6017 } 6018 6019 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 6020 { 6021 int ret; 6022 6023 if (!ufshcd_is_wb_allowed(hba) || 6024 hba->dev_info.wb_buf_flush_enabled == enable) 6025 return 0; 6026 6027 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 6028 if (ret) { 6029 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 6030 __func__, enable ? "enabling" : "disabling", ret); 6031 return ret; 6032 } 6033 6034 hba->dev_info.wb_buf_flush_enabled = enable; 6035 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 6036 __func__, enable ? "enabled" : "disabled"); 6037 6038 return ret; 6039 } 6040 6041 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 6042 u32 avail_buf) 6043 { 6044 u32 cur_buf; 6045 int ret; 6046 u8 index; 6047 6048 index = ufshcd_wb_get_query_index(hba); 6049 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6050 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 6051 index, 0, &cur_buf); 6052 if (ret) { 6053 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 6054 __func__, ret); 6055 return false; 6056 } 6057 6058 if (!cur_buf) { 6059 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 6060 cur_buf); 6061 return false; 6062 } 6063 /* Let it continue to flush when available buffer exceeds threshold */ 6064 return avail_buf < hba->vps->wb_flush_threshold; 6065 } 6066 6067 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 6068 { 6069 if (ufshcd_is_wb_buf_flush_allowed(hba)) 6070 ufshcd_wb_toggle_buf_flush(hba, false); 6071 6072 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 6073 ufshcd_wb_toggle(hba, false); 6074 hba->caps &= ~UFSHCD_CAP_WB_EN; 6075 6076 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 6077 } 6078 6079 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 6080 { 6081 u32 lifetime; 6082 int ret; 6083 u8 index; 6084 6085 index = ufshcd_wb_get_query_index(hba); 6086 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6087 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 6088 index, 0, &lifetime); 6089 if (ret) { 6090 dev_err(hba->dev, 6091 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 6092 __func__, ret); 6093 return false; 6094 } 6095 6096 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6097 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6098 __func__, lifetime); 6099 return false; 6100 } 6101 6102 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6103 __func__, lifetime); 6104 6105 return true; 6106 } 6107 6108 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6109 { 6110 int ret; 6111 u32 avail_buf; 6112 u8 index; 6113 6114 if (!ufshcd_is_wb_allowed(hba)) 6115 return false; 6116 6117 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6118 ufshcd_wb_force_disable(hba); 6119 return false; 6120 } 6121 6122 /* 6123 * The ufs device needs the vcc to be ON to flush. 6124 * With user-space reduction enabled, it's enough to enable flush 6125 * by checking only the available buffer. The threshold 6126 * defined here is > 90% full. 6127 * With user-space preserved enabled, the current-buffer 6128 * should be checked too because the wb buffer size can reduce 6129 * when disk tends to be full. This info is provided by current 6130 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6131 * keeping vcc on when current buffer is empty. 6132 */ 6133 index = ufshcd_wb_get_query_index(hba); 6134 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6135 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6136 index, 0, &avail_buf); 6137 if (ret) { 6138 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6139 __func__, ret); 6140 return false; 6141 } 6142 6143 if (!hba->dev_info.b_presrv_uspc_en) 6144 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6145 6146 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6147 } 6148 6149 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6150 { 6151 struct ufs_hba *hba = container_of(to_delayed_work(work), 6152 struct ufs_hba, 6153 rpm_dev_flush_recheck_work); 6154 /* 6155 * To prevent unnecessary VCC power drain after device finishes 6156 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6157 * after a certain delay to recheck the threshold by next runtime 6158 * suspend. 6159 */ 6160 ufshcd_rpm_get_sync(hba); 6161 ufshcd_rpm_put_sync(hba); 6162 } 6163 6164 /** 6165 * ufshcd_exception_event_handler - handle exceptions raised by device 6166 * @work: pointer to work data 6167 * 6168 * Read bExceptionEventStatus attribute from the device and handle the 6169 * exception event accordingly. 6170 */ 6171 static void ufshcd_exception_event_handler(struct work_struct *work) 6172 { 6173 struct ufs_hba *hba; 6174 int err; 6175 u32 status = 0; 6176 hba = container_of(work, struct ufs_hba, eeh_work); 6177 6178 ufshcd_scsi_block_requests(hba); 6179 err = ufshcd_get_ee_status(hba, &status); 6180 if (err) { 6181 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6182 __func__, err); 6183 goto out; 6184 } 6185 6186 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6187 6188 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6189 ufshcd_bkops_exception_event_handler(hba); 6190 6191 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6192 ufshcd_temp_exception_event_handler(hba, status); 6193 6194 ufs_debugfs_exception_event(hba, status); 6195 out: 6196 ufshcd_scsi_unblock_requests(hba); 6197 } 6198 6199 /* Complete requests that have door-bell cleared */ 6200 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6201 { 6202 if (is_mcq_enabled(hba)) 6203 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6204 else 6205 ufshcd_transfer_req_compl(hba); 6206 6207 ufshcd_tmc_handler(hba); 6208 } 6209 6210 /** 6211 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6212 * to recover from the DL NAC errors or not. 6213 * @hba: per-adapter instance 6214 * 6215 * Return: true if error handling is required, false otherwise. 6216 */ 6217 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6218 { 6219 unsigned long flags; 6220 bool err_handling = true; 6221 6222 spin_lock_irqsave(hba->host->host_lock, flags); 6223 /* 6224 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6225 * device fatal error and/or DL NAC & REPLAY timeout errors. 6226 */ 6227 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6228 goto out; 6229 6230 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6231 ((hba->saved_err & UIC_ERROR) && 6232 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6233 goto out; 6234 6235 if ((hba->saved_err & UIC_ERROR) && 6236 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6237 int err; 6238 /* 6239 * wait for 50ms to see if we can get any other errors or not. 6240 */ 6241 spin_unlock_irqrestore(hba->host->host_lock, flags); 6242 msleep(50); 6243 spin_lock_irqsave(hba->host->host_lock, flags); 6244 6245 /* 6246 * now check if we have got any other severe errors other than 6247 * DL NAC error? 6248 */ 6249 if ((hba->saved_err & INT_FATAL_ERRORS) || 6250 ((hba->saved_err & UIC_ERROR) && 6251 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6252 goto out; 6253 6254 /* 6255 * As DL NAC is the only error received so far, send out NOP 6256 * command to confirm if link is still active or not. 6257 * - If we don't get any response then do error recovery. 6258 * - If we get response then clear the DL NAC error bit. 6259 */ 6260 6261 spin_unlock_irqrestore(hba->host->host_lock, flags); 6262 err = ufshcd_verify_dev_init(hba); 6263 spin_lock_irqsave(hba->host->host_lock, flags); 6264 6265 if (err) 6266 goto out; 6267 6268 /* Link seems to be alive hence ignore the DL NAC errors */ 6269 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6270 hba->saved_err &= ~UIC_ERROR; 6271 /* clear NAC error */ 6272 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6273 if (!hba->saved_uic_err) 6274 err_handling = false; 6275 } 6276 out: 6277 spin_unlock_irqrestore(hba->host->host_lock, flags); 6278 return err_handling; 6279 } 6280 6281 /* host lock must be held before calling this func */ 6282 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6283 { 6284 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6285 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6286 } 6287 6288 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6289 { 6290 lockdep_assert_held(hba->host->host_lock); 6291 6292 /* handle fatal errors only when link is not in error state */ 6293 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6294 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6295 ufshcd_is_saved_err_fatal(hba)) 6296 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6297 else 6298 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6299 queue_work(hba->eh_wq, &hba->eh_work); 6300 } 6301 } 6302 6303 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6304 { 6305 spin_lock_irq(hba->host->host_lock); 6306 hba->force_reset = true; 6307 ufshcd_schedule_eh_work(hba); 6308 spin_unlock_irq(hba->host->host_lock); 6309 } 6310 6311 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6312 { 6313 mutex_lock(&hba->wb_mutex); 6314 down_write(&hba->clk_scaling_lock); 6315 hba->clk_scaling.is_allowed = allow; 6316 up_write(&hba->clk_scaling_lock); 6317 mutex_unlock(&hba->wb_mutex); 6318 } 6319 6320 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6321 { 6322 if (suspend) { 6323 if (hba->clk_scaling.is_enabled) 6324 ufshcd_suspend_clkscaling(hba); 6325 ufshcd_clk_scaling_allow(hba, false); 6326 } else { 6327 ufshcd_clk_scaling_allow(hba, true); 6328 if (hba->clk_scaling.is_enabled) 6329 ufshcd_resume_clkscaling(hba); 6330 } 6331 } 6332 6333 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6334 { 6335 ufshcd_rpm_get_sync(hba); 6336 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6337 hba->is_sys_suspended) { 6338 enum ufs_pm_op pm_op; 6339 6340 /* 6341 * Don't assume anything of resume, if 6342 * resume fails, irq and clocks can be OFF, and powers 6343 * can be OFF or in LPM. 6344 */ 6345 ufshcd_setup_hba_vreg(hba, true); 6346 ufshcd_enable_irq(hba); 6347 ufshcd_setup_vreg(hba, true); 6348 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6349 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6350 ufshcd_hold(hba); 6351 if (!ufshcd_is_clkgating_allowed(hba)) 6352 ufshcd_setup_clocks(hba, true); 6353 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6354 ufshcd_vops_resume(hba, pm_op); 6355 } else { 6356 ufshcd_hold(hba); 6357 if (ufshcd_is_clkscaling_supported(hba) && 6358 hba->clk_scaling.is_enabled) 6359 ufshcd_suspend_clkscaling(hba); 6360 ufshcd_clk_scaling_allow(hba, false); 6361 } 6362 ufshcd_scsi_block_requests(hba); 6363 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6364 blk_mq_wait_quiesce_done(&hba->host->tag_set); 6365 cancel_work_sync(&hba->eeh_work); 6366 } 6367 6368 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6369 { 6370 ufshcd_scsi_unblock_requests(hba); 6371 ufshcd_release(hba); 6372 if (ufshcd_is_clkscaling_supported(hba)) 6373 ufshcd_clk_scaling_suspend(hba, false); 6374 ufshcd_rpm_put(hba); 6375 } 6376 6377 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6378 { 6379 return (!hba->is_powered || hba->shutting_down || 6380 !hba->ufs_device_wlun || 6381 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6382 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6383 ufshcd_is_link_broken(hba)))); 6384 } 6385 6386 #ifdef CONFIG_PM 6387 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6388 { 6389 struct Scsi_Host *shost = hba->host; 6390 struct scsi_device *sdev; 6391 struct request_queue *q; 6392 int ret; 6393 6394 hba->is_sys_suspended = false; 6395 /* 6396 * Set RPM status of wlun device to RPM_ACTIVE, 6397 * this also clears its runtime error. 6398 */ 6399 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6400 6401 /* hba device might have a runtime error otherwise */ 6402 if (ret) 6403 ret = pm_runtime_set_active(hba->dev); 6404 /* 6405 * If wlun device had runtime error, we also need to resume those 6406 * consumer scsi devices in case any of them has failed to be 6407 * resumed due to supplier runtime resume failure. This is to unblock 6408 * blk_queue_enter in case there are bios waiting inside it. 6409 */ 6410 if (!ret) { 6411 shost_for_each_device(sdev, shost) { 6412 q = sdev->request_queue; 6413 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6414 q->rpm_status == RPM_SUSPENDING)) 6415 pm_request_resume(q->dev); 6416 } 6417 } 6418 } 6419 #else 6420 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6421 { 6422 } 6423 #endif 6424 6425 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6426 { 6427 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6428 u32 mode; 6429 6430 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6431 6432 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6433 return true; 6434 6435 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6436 return true; 6437 6438 return false; 6439 } 6440 6441 static bool ufshcd_abort_one(struct request *rq, void *priv) 6442 { 6443 int *ret = priv; 6444 u32 tag = rq->tag; 6445 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6446 struct scsi_device *sdev = cmd->device; 6447 struct Scsi_Host *shost = sdev->host; 6448 struct ufs_hba *hba = shost_priv(shost); 6449 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 6450 struct ufs_hw_queue *hwq; 6451 unsigned long flags; 6452 6453 *ret = ufshcd_try_to_abort_task(hba, tag); 6454 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6455 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6456 *ret ? "failed" : "succeeded"); 6457 6458 /* Release cmd in MCQ mode if abort succeeds */ 6459 if (is_mcq_enabled(hba) && (*ret == 0)) { 6460 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 6461 spin_lock_irqsave(&hwq->cq_lock, flags); 6462 if (ufshcd_cmd_inflight(lrbp->cmd)) 6463 ufshcd_release_scsi_cmd(hba, lrbp); 6464 spin_unlock_irqrestore(&hwq->cq_lock, flags); 6465 } 6466 6467 return *ret == 0; 6468 } 6469 6470 /** 6471 * ufshcd_abort_all - Abort all pending commands. 6472 * @hba: Host bus adapter pointer. 6473 * 6474 * Return: true if and only if the host controller needs to be reset. 6475 */ 6476 static bool ufshcd_abort_all(struct ufs_hba *hba) 6477 { 6478 int tag, ret = 0; 6479 6480 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6481 if (ret) 6482 goto out; 6483 6484 /* Clear pending task management requests */ 6485 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6486 ret = ufshcd_clear_tm_cmd(hba, tag); 6487 if (ret) 6488 goto out; 6489 } 6490 6491 out: 6492 /* Complete the requests that are cleared by s/w */ 6493 ufshcd_complete_requests(hba, false); 6494 6495 return ret != 0; 6496 } 6497 6498 /** 6499 * ufshcd_err_handler - handle UFS errors that require s/w attention 6500 * @work: pointer to work structure 6501 */ 6502 static void ufshcd_err_handler(struct work_struct *work) 6503 { 6504 int retries = MAX_ERR_HANDLER_RETRIES; 6505 struct ufs_hba *hba; 6506 unsigned long flags; 6507 bool needs_restore; 6508 bool needs_reset; 6509 int pmc_err; 6510 6511 hba = container_of(work, struct ufs_hba, eh_work); 6512 6513 dev_info(hba->dev, 6514 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6515 __func__, ufshcd_state_name[hba->ufshcd_state], 6516 hba->is_powered, hba->shutting_down, hba->saved_err, 6517 hba->saved_uic_err, hba->force_reset, 6518 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6519 6520 down(&hba->host_sem); 6521 spin_lock_irqsave(hba->host->host_lock, flags); 6522 if (ufshcd_err_handling_should_stop(hba)) { 6523 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6524 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6525 spin_unlock_irqrestore(hba->host->host_lock, flags); 6526 up(&hba->host_sem); 6527 return; 6528 } 6529 ufshcd_set_eh_in_progress(hba); 6530 spin_unlock_irqrestore(hba->host->host_lock, flags); 6531 ufshcd_err_handling_prepare(hba); 6532 /* Complete requests that have door-bell cleared by h/w */ 6533 ufshcd_complete_requests(hba, false); 6534 spin_lock_irqsave(hba->host->host_lock, flags); 6535 again: 6536 needs_restore = false; 6537 needs_reset = false; 6538 6539 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6540 hba->ufshcd_state = UFSHCD_STATE_RESET; 6541 /* 6542 * A full reset and restore might have happened after preparation 6543 * is finished, double check whether we should stop. 6544 */ 6545 if (ufshcd_err_handling_should_stop(hba)) 6546 goto skip_err_handling; 6547 6548 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6549 bool ret; 6550 6551 spin_unlock_irqrestore(hba->host->host_lock, flags); 6552 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6553 ret = ufshcd_quirk_dl_nac_errors(hba); 6554 spin_lock_irqsave(hba->host->host_lock, flags); 6555 if (!ret && ufshcd_err_handling_should_stop(hba)) 6556 goto skip_err_handling; 6557 } 6558 6559 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6560 (hba->saved_uic_err && 6561 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6562 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6563 6564 spin_unlock_irqrestore(hba->host->host_lock, flags); 6565 ufshcd_print_host_state(hba); 6566 ufshcd_print_pwr_info(hba); 6567 ufshcd_print_evt_hist(hba); 6568 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6569 ufshcd_print_trs_all(hba, pr_prdt); 6570 spin_lock_irqsave(hba->host->host_lock, flags); 6571 } 6572 6573 /* 6574 * if host reset is required then skip clearing the pending 6575 * transfers forcefully because they will get cleared during 6576 * host reset and restore 6577 */ 6578 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6579 ufshcd_is_saved_err_fatal(hba) || 6580 ((hba->saved_err & UIC_ERROR) && 6581 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6582 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6583 needs_reset = true; 6584 goto do_reset; 6585 } 6586 6587 /* 6588 * If LINERESET was caught, UFS might have been put to PWM mode, 6589 * check if power mode restore is needed. 6590 */ 6591 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6592 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6593 if (!hba->saved_uic_err) 6594 hba->saved_err &= ~UIC_ERROR; 6595 spin_unlock_irqrestore(hba->host->host_lock, flags); 6596 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6597 needs_restore = true; 6598 spin_lock_irqsave(hba->host->host_lock, flags); 6599 if (!hba->saved_err && !needs_restore) 6600 goto skip_err_handling; 6601 } 6602 6603 hba->silence_err_logs = true; 6604 /* release lock as clear command might sleep */ 6605 spin_unlock_irqrestore(hba->host->host_lock, flags); 6606 6607 needs_reset = ufshcd_abort_all(hba); 6608 6609 spin_lock_irqsave(hba->host->host_lock, flags); 6610 hba->silence_err_logs = false; 6611 if (needs_reset) 6612 goto do_reset; 6613 6614 /* 6615 * After all reqs and tasks are cleared from doorbell, 6616 * now it is safe to retore power mode. 6617 */ 6618 if (needs_restore) { 6619 spin_unlock_irqrestore(hba->host->host_lock, flags); 6620 /* 6621 * Hold the scaling lock just in case dev cmds 6622 * are sent via bsg and/or sysfs. 6623 */ 6624 down_write(&hba->clk_scaling_lock); 6625 hba->force_pmc = true; 6626 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6627 if (pmc_err) { 6628 needs_reset = true; 6629 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6630 __func__, pmc_err); 6631 } 6632 hba->force_pmc = false; 6633 ufshcd_print_pwr_info(hba); 6634 up_write(&hba->clk_scaling_lock); 6635 spin_lock_irqsave(hba->host->host_lock, flags); 6636 } 6637 6638 do_reset: 6639 /* Fatal errors need reset */ 6640 if (needs_reset) { 6641 int err; 6642 6643 hba->force_reset = false; 6644 spin_unlock_irqrestore(hba->host->host_lock, flags); 6645 err = ufshcd_reset_and_restore(hba); 6646 if (err) 6647 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6648 __func__, err); 6649 else 6650 ufshcd_recover_pm_error(hba); 6651 spin_lock_irqsave(hba->host->host_lock, flags); 6652 } 6653 6654 skip_err_handling: 6655 if (!needs_reset) { 6656 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6657 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6658 if (hba->saved_err || hba->saved_uic_err) 6659 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6660 __func__, hba->saved_err, hba->saved_uic_err); 6661 } 6662 /* Exit in an operational state or dead */ 6663 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6664 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6665 if (--retries) 6666 goto again; 6667 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6668 } 6669 ufshcd_clear_eh_in_progress(hba); 6670 spin_unlock_irqrestore(hba->host->host_lock, flags); 6671 ufshcd_err_handling_unprepare(hba); 6672 up(&hba->host_sem); 6673 6674 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6675 ufshcd_state_name[hba->ufshcd_state]); 6676 } 6677 6678 /** 6679 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6680 * @hba: per-adapter instance 6681 * 6682 * Return: 6683 * IRQ_HANDLED - If interrupt is valid 6684 * IRQ_NONE - If invalid interrupt 6685 */ 6686 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6687 { 6688 u32 reg; 6689 irqreturn_t retval = IRQ_NONE; 6690 6691 /* PHY layer error */ 6692 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6693 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6694 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6695 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6696 /* 6697 * To know whether this error is fatal or not, DB timeout 6698 * must be checked but this error is handled separately. 6699 */ 6700 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6701 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6702 __func__); 6703 6704 /* Got a LINERESET indication. */ 6705 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6706 struct uic_command *cmd = NULL; 6707 6708 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6709 if (hba->uic_async_done && hba->active_uic_cmd) 6710 cmd = hba->active_uic_cmd; 6711 /* 6712 * Ignore the LINERESET during power mode change 6713 * operation via DME_SET command. 6714 */ 6715 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6716 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6717 } 6718 retval |= IRQ_HANDLED; 6719 } 6720 6721 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6722 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6723 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6724 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6725 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6726 6727 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6728 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6729 else if (hba->dev_quirks & 6730 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6731 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6732 hba->uic_error |= 6733 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6734 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6735 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6736 } 6737 retval |= IRQ_HANDLED; 6738 } 6739 6740 /* UIC NL/TL/DME errors needs software retry */ 6741 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6742 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6743 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6744 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6745 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6746 retval |= IRQ_HANDLED; 6747 } 6748 6749 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6750 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6751 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6752 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6753 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6754 retval |= IRQ_HANDLED; 6755 } 6756 6757 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6758 if ((reg & UIC_DME_ERROR) && 6759 (reg & UIC_DME_ERROR_CODE_MASK)) { 6760 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6761 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6762 retval |= IRQ_HANDLED; 6763 } 6764 6765 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6766 __func__, hba->uic_error); 6767 return retval; 6768 } 6769 6770 /** 6771 * ufshcd_check_errors - Check for errors that need s/w attention 6772 * @hba: per-adapter instance 6773 * @intr_status: interrupt status generated by the controller 6774 * 6775 * Return: 6776 * IRQ_HANDLED - If interrupt is valid 6777 * IRQ_NONE - If invalid interrupt 6778 */ 6779 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6780 { 6781 bool queue_eh_work = false; 6782 irqreturn_t retval = IRQ_NONE; 6783 6784 spin_lock(hba->host->host_lock); 6785 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6786 6787 if (hba->errors & INT_FATAL_ERRORS) { 6788 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6789 hba->errors); 6790 queue_eh_work = true; 6791 } 6792 6793 if (hba->errors & UIC_ERROR) { 6794 hba->uic_error = 0; 6795 retval = ufshcd_update_uic_error(hba); 6796 if (hba->uic_error) 6797 queue_eh_work = true; 6798 } 6799 6800 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6801 dev_err(hba->dev, 6802 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6803 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6804 "Enter" : "Exit", 6805 hba->errors, ufshcd_get_upmcrs(hba)); 6806 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6807 hba->errors); 6808 ufshcd_set_link_broken(hba); 6809 queue_eh_work = true; 6810 } 6811 6812 if (queue_eh_work) { 6813 /* 6814 * update the transfer error masks to sticky bits, let's do this 6815 * irrespective of current ufshcd_state. 6816 */ 6817 hba->saved_err |= hba->errors; 6818 hba->saved_uic_err |= hba->uic_error; 6819 6820 /* dump controller state before resetting */ 6821 if ((hba->saved_err & 6822 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6823 (hba->saved_uic_err && 6824 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6825 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6826 __func__, hba->saved_err, 6827 hba->saved_uic_err); 6828 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6829 "host_regs: "); 6830 ufshcd_print_pwr_info(hba); 6831 } 6832 ufshcd_schedule_eh_work(hba); 6833 retval |= IRQ_HANDLED; 6834 } 6835 /* 6836 * if (!queue_eh_work) - 6837 * Other errors are either non-fatal where host recovers 6838 * itself without s/w intervention or errors that will be 6839 * handled by the SCSI core layer. 6840 */ 6841 hba->errors = 0; 6842 hba->uic_error = 0; 6843 spin_unlock(hba->host->host_lock); 6844 return retval; 6845 } 6846 6847 /** 6848 * ufshcd_tmc_handler - handle task management function completion 6849 * @hba: per adapter instance 6850 * 6851 * Return: 6852 * IRQ_HANDLED - If interrupt is valid 6853 * IRQ_NONE - If invalid interrupt 6854 */ 6855 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6856 { 6857 unsigned long flags, pending, issued; 6858 irqreturn_t ret = IRQ_NONE; 6859 int tag; 6860 6861 spin_lock_irqsave(hba->host->host_lock, flags); 6862 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6863 issued = hba->outstanding_tasks & ~pending; 6864 for_each_set_bit(tag, &issued, hba->nutmrs) { 6865 struct request *req = hba->tmf_rqs[tag]; 6866 struct completion *c = req->end_io_data; 6867 6868 complete(c); 6869 ret = IRQ_HANDLED; 6870 } 6871 spin_unlock_irqrestore(hba->host->host_lock, flags); 6872 6873 return ret; 6874 } 6875 6876 /** 6877 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6878 * @hba: per adapter instance 6879 * 6880 * Return: IRQ_HANDLED if interrupt is handled. 6881 */ 6882 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6883 { 6884 struct ufs_hw_queue *hwq; 6885 unsigned long outstanding_cqs; 6886 unsigned int nr_queues; 6887 int i, ret; 6888 u32 events; 6889 6890 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6891 if (ret) 6892 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6893 6894 /* Exclude the poll queues */ 6895 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6896 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6897 hwq = &hba->uhq[i]; 6898 6899 events = ufshcd_mcq_read_cqis(hba, i); 6900 if (events) 6901 ufshcd_mcq_write_cqis(hba, events, i); 6902 6903 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6904 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6905 } 6906 6907 return IRQ_HANDLED; 6908 } 6909 6910 /** 6911 * ufshcd_sl_intr - Interrupt service routine 6912 * @hba: per adapter instance 6913 * @intr_status: contains interrupts generated by the controller 6914 * 6915 * Return: 6916 * IRQ_HANDLED - If interrupt is valid 6917 * IRQ_NONE - If invalid interrupt 6918 */ 6919 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6920 { 6921 irqreturn_t retval = IRQ_NONE; 6922 6923 if (intr_status & UFSHCD_UIC_MASK) 6924 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6925 6926 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6927 retval |= ufshcd_check_errors(hba, intr_status); 6928 6929 if (intr_status & UTP_TASK_REQ_COMPL) 6930 retval |= ufshcd_tmc_handler(hba); 6931 6932 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6933 retval |= ufshcd_transfer_req_compl(hba); 6934 6935 if (intr_status & MCQ_CQ_EVENT_STATUS) 6936 retval |= ufshcd_handle_mcq_cq_events(hba); 6937 6938 return retval; 6939 } 6940 6941 /** 6942 * ufshcd_intr - Main interrupt service routine 6943 * @irq: irq number 6944 * @__hba: pointer to adapter instance 6945 * 6946 * Return: 6947 * IRQ_HANDLED - If interrupt is valid 6948 * IRQ_NONE - If invalid interrupt 6949 */ 6950 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6951 { 6952 u32 intr_status, enabled_intr_status = 0; 6953 irqreturn_t retval = IRQ_NONE; 6954 struct ufs_hba *hba = __hba; 6955 int retries = hba->nutrs; 6956 6957 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6958 hba->ufs_stats.last_intr_status = intr_status; 6959 hba->ufs_stats.last_intr_ts = local_clock(); 6960 6961 /* 6962 * There could be max of hba->nutrs reqs in flight and in worst case 6963 * if the reqs get finished 1 by 1 after the interrupt status is 6964 * read, make sure we handle them by checking the interrupt status 6965 * again in a loop until we process all of the reqs before returning. 6966 */ 6967 while (intr_status && retries--) { 6968 enabled_intr_status = 6969 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6970 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6971 if (enabled_intr_status) 6972 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 6973 6974 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6975 } 6976 6977 if (enabled_intr_status && retval == IRQ_NONE && 6978 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 6979 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 6980 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 6981 __func__, 6982 intr_status, 6983 hba->ufs_stats.last_intr_status, 6984 enabled_intr_status); 6985 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 6986 } 6987 6988 return retval; 6989 } 6990 6991 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 6992 { 6993 int err = 0; 6994 u32 mask = 1 << tag; 6995 unsigned long flags; 6996 6997 if (!test_bit(tag, &hba->outstanding_tasks)) 6998 goto out; 6999 7000 spin_lock_irqsave(hba->host->host_lock, flags); 7001 ufshcd_utmrl_clear(hba, tag); 7002 spin_unlock_irqrestore(hba->host->host_lock, flags); 7003 7004 /* poll for max. 1 sec to clear door bell register by h/w */ 7005 err = ufshcd_wait_for_register(hba, 7006 REG_UTP_TASK_REQ_DOOR_BELL, 7007 mask, 0, 1000, 1000); 7008 7009 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 7010 tag, err < 0 ? "failed" : "succeeded"); 7011 7012 out: 7013 return err; 7014 } 7015 7016 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 7017 struct utp_task_req_desc *treq, u8 tm_function) 7018 { 7019 struct request_queue *q = hba->tmf_queue; 7020 struct Scsi_Host *host = hba->host; 7021 DECLARE_COMPLETION_ONSTACK(wait); 7022 struct request *req; 7023 unsigned long flags; 7024 int task_tag, err; 7025 7026 /* 7027 * blk_mq_alloc_request() is used here only to get a free tag. 7028 */ 7029 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 7030 if (IS_ERR(req)) 7031 return PTR_ERR(req); 7032 7033 req->end_io_data = &wait; 7034 ufshcd_hold(hba); 7035 7036 spin_lock_irqsave(host->host_lock, flags); 7037 7038 task_tag = req->tag; 7039 hba->tmf_rqs[req->tag] = req; 7040 treq->upiu_req.req_header.task_tag = task_tag; 7041 7042 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 7043 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 7044 7045 /* send command to the controller */ 7046 __set_bit(task_tag, &hba->outstanding_tasks); 7047 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 7048 7049 spin_unlock_irqrestore(host->host_lock, flags); 7050 7051 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 7052 7053 /* wait until the task management command is completed */ 7054 err = wait_for_completion_io_timeout(&wait, 7055 msecs_to_jiffies(TM_CMD_TIMEOUT)); 7056 if (!err) { 7057 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 7058 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 7059 __func__, tm_function); 7060 if (ufshcd_clear_tm_cmd(hba, task_tag)) 7061 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 7062 __func__, task_tag); 7063 err = -ETIMEDOUT; 7064 } else { 7065 err = 0; 7066 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 7067 7068 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 7069 } 7070 7071 spin_lock_irqsave(hba->host->host_lock, flags); 7072 hba->tmf_rqs[req->tag] = NULL; 7073 __clear_bit(task_tag, &hba->outstanding_tasks); 7074 spin_unlock_irqrestore(hba->host->host_lock, flags); 7075 7076 ufshcd_release(hba); 7077 blk_mq_free_request(req); 7078 7079 return err; 7080 } 7081 7082 /** 7083 * ufshcd_issue_tm_cmd - issues task management commands to controller 7084 * @hba: per adapter instance 7085 * @lun_id: LUN ID to which TM command is sent 7086 * @task_id: task ID to which the TM command is applicable 7087 * @tm_function: task management function opcode 7088 * @tm_response: task management service response return value 7089 * 7090 * Return: non-zero value on error, zero on success. 7091 */ 7092 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7093 u8 tm_function, u8 *tm_response) 7094 { 7095 struct utp_task_req_desc treq = { }; 7096 enum utp_ocs ocs_value; 7097 int err; 7098 7099 /* Configure task request descriptor */ 7100 treq.header.interrupt = 1; 7101 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7102 7103 /* Configure task request UPIU */ 7104 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7105 treq.upiu_req.req_header.lun = lun_id; 7106 treq.upiu_req.req_header.tm_function = tm_function; 7107 7108 /* 7109 * The host shall provide the same value for LUN field in the basic 7110 * header and for Input Parameter. 7111 */ 7112 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7113 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7114 7115 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7116 if (err == -ETIMEDOUT) 7117 return err; 7118 7119 ocs_value = treq.header.ocs & MASK_OCS; 7120 if (ocs_value != OCS_SUCCESS) 7121 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7122 __func__, ocs_value); 7123 else if (tm_response) 7124 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7125 MASK_TM_SERVICE_RESP; 7126 return err; 7127 } 7128 7129 /** 7130 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7131 * @hba: per-adapter instance 7132 * @req_upiu: upiu request 7133 * @rsp_upiu: upiu reply 7134 * @desc_buff: pointer to descriptor buffer, NULL if NA 7135 * @buff_len: descriptor size, 0 if NA 7136 * @cmd_type: specifies the type (NOP, Query...) 7137 * @desc_op: descriptor operation 7138 * 7139 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7140 * Therefore, it "rides" the device management infrastructure: uses its tag and 7141 * tasks work queues. 7142 * 7143 * Since there is only one available tag for device management commands, 7144 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7145 * 7146 * Return: 0 upon success; < 0 upon failure. 7147 */ 7148 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7149 struct utp_upiu_req *req_upiu, 7150 struct utp_upiu_req *rsp_upiu, 7151 u8 *desc_buff, int *buff_len, 7152 enum dev_cmd_type cmd_type, 7153 enum query_opcode desc_op) 7154 { 7155 const u32 tag = hba->reserved_slot; 7156 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7157 int err = 0; 7158 u8 upiu_flags; 7159 7160 /* Protects use of hba->reserved_slot. */ 7161 lockdep_assert_held(&hba->dev_cmd.lock); 7162 7163 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 7164 7165 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 7166 7167 /* update the task tag in the request upiu */ 7168 req_upiu->header.task_tag = tag; 7169 7170 /* just copy the upiu request as it is */ 7171 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7172 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7173 /* The Data Segment Area is optional depending upon the query 7174 * function value. for WRITE DESCRIPTOR, the data segment 7175 * follows right after the tsf. 7176 */ 7177 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7178 *buff_len = 0; 7179 } 7180 7181 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7182 7183 /* 7184 * ignore the returning value here - ufshcd_check_query_response is 7185 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7186 * read the response directly ignoring all errors. 7187 */ 7188 ufshcd_issue_dev_cmd(hba, lrbp, tag, QUERY_REQ_TIMEOUT); 7189 7190 /* just copy the upiu response as it is */ 7191 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7192 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7193 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7194 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7195 .data_segment_length); 7196 7197 if (*buff_len >= resp_len) { 7198 memcpy(desc_buff, descp, resp_len); 7199 *buff_len = resp_len; 7200 } else { 7201 dev_warn(hba->dev, 7202 "%s: rsp size %d is bigger than buffer size %d", 7203 __func__, resp_len, *buff_len); 7204 *buff_len = 0; 7205 err = -EINVAL; 7206 } 7207 } 7208 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7209 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7210 7211 return err; 7212 } 7213 7214 /** 7215 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7216 * @hba: per-adapter instance 7217 * @req_upiu: upiu request 7218 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7219 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7220 * @desc_buff: pointer to descriptor buffer, NULL if NA 7221 * @buff_len: descriptor size, 0 if NA 7222 * @desc_op: descriptor operation 7223 * 7224 * Supports UTP Transfer requests (nop and query), and UTP Task 7225 * Management requests. 7226 * It is up to the caller to fill the upiu conent properly, as it will 7227 * be copied without any further input validations. 7228 * 7229 * Return: 0 upon success; < 0 upon failure. 7230 */ 7231 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7232 struct utp_upiu_req *req_upiu, 7233 struct utp_upiu_req *rsp_upiu, 7234 enum upiu_request_transaction msgcode, 7235 u8 *desc_buff, int *buff_len, 7236 enum query_opcode desc_op) 7237 { 7238 int err; 7239 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7240 struct utp_task_req_desc treq = { }; 7241 enum utp_ocs ocs_value; 7242 u8 tm_f = req_upiu->header.tm_function; 7243 7244 switch (msgcode) { 7245 case UPIU_TRANSACTION_NOP_OUT: 7246 cmd_type = DEV_CMD_TYPE_NOP; 7247 fallthrough; 7248 case UPIU_TRANSACTION_QUERY_REQ: 7249 ufshcd_dev_man_lock(hba); 7250 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7251 desc_buff, buff_len, 7252 cmd_type, desc_op); 7253 ufshcd_dev_man_unlock(hba); 7254 7255 break; 7256 case UPIU_TRANSACTION_TASK_REQ: 7257 treq.header.interrupt = 1; 7258 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7259 7260 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7261 7262 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7263 if (err == -ETIMEDOUT) 7264 break; 7265 7266 ocs_value = treq.header.ocs & MASK_OCS; 7267 if (ocs_value != OCS_SUCCESS) { 7268 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7269 ocs_value); 7270 break; 7271 } 7272 7273 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7274 7275 break; 7276 default: 7277 err = -EINVAL; 7278 7279 break; 7280 } 7281 7282 return err; 7283 } 7284 7285 /** 7286 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7287 * @hba: per adapter instance 7288 * @req_upiu: upiu request 7289 * @rsp_upiu: upiu reply 7290 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7291 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7292 * @sg_cnt: The number of sg lists actually used 7293 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7294 * @dir: DMA direction 7295 * 7296 * Return: zero on success, non-zero on failure. 7297 */ 7298 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7299 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7300 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7301 enum dma_data_direction dir) 7302 { 7303 const u32 tag = hba->reserved_slot; 7304 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7305 int err = 0; 7306 int result; 7307 u8 upiu_flags; 7308 u8 *ehs_data; 7309 u16 ehs_len; 7310 int ehs = (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) ? 2 : 0; 7311 7312 /* Protects use of hba->reserved_slot. */ 7313 ufshcd_dev_man_lock(hba); 7314 7315 ufshcd_setup_dev_cmd(hba, lrbp, DEV_CMD_TYPE_RPMB, UFS_UPIU_RPMB_WLUN, tag); 7316 7317 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, ehs); 7318 7319 /* update the task tag */ 7320 req_upiu->header.task_tag = tag; 7321 7322 /* copy the UPIU(contains CDB) request as it is */ 7323 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7324 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7325 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7326 7327 if (dir != DMA_NONE && sg_list) 7328 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7329 7330 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7331 7332 err = ufshcd_issue_dev_cmd(hba, lrbp, tag, ADVANCED_RPMB_REQ_TIMEOUT); 7333 7334 if (!err) { 7335 /* Just copy the upiu response as it is */ 7336 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7337 /* Get the response UPIU result */ 7338 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7339 lrbp->ucd_rsp_ptr->header.status; 7340 7341 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7342 /* 7343 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7344 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7345 * Message is 02h 7346 */ 7347 if (ehs_len == 2 && rsp_ehs) { 7348 /* 7349 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7350 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7351 */ 7352 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7353 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7354 } 7355 } 7356 7357 ufshcd_dev_man_unlock(hba); 7358 7359 return err ? : result; 7360 } 7361 7362 /** 7363 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7364 * @cmd: SCSI command pointer 7365 * 7366 * Return: SUCCESS or FAILED. 7367 */ 7368 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7369 { 7370 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7371 struct Scsi_Host *host; 7372 struct ufs_hba *hba; 7373 struct ufs_hw_queue *hwq; 7374 struct ufshcd_lrb *lrbp; 7375 u32 pos, not_cleared_mask = 0; 7376 int err; 7377 u8 resp = 0xF, lun; 7378 7379 host = cmd->device->host; 7380 hba = shost_priv(host); 7381 7382 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7383 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7384 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7385 if (!err) 7386 err = resp; 7387 goto out; 7388 } 7389 7390 if (is_mcq_enabled(hba)) { 7391 for (pos = 0; pos < hba->nutrs; pos++) { 7392 lrbp = &hba->lrb[pos]; 7393 if (ufshcd_cmd_inflight(lrbp->cmd) && 7394 lrbp->lun == lun) { 7395 ufshcd_clear_cmd(hba, pos); 7396 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7397 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7398 } 7399 } 7400 err = 0; 7401 goto out; 7402 } 7403 7404 /* clear the commands that were pending for corresponding LUN */ 7405 spin_lock_irqsave(&hba->outstanding_lock, flags); 7406 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7407 if (hba->lrb[pos].lun == lun) 7408 __set_bit(pos, &pending_reqs); 7409 hba->outstanding_reqs &= ~pending_reqs; 7410 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7411 7412 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7413 if (ufshcd_clear_cmd(hba, pos) < 0) { 7414 spin_lock_irqsave(&hba->outstanding_lock, flags); 7415 not_cleared = 1U << pos & 7416 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7417 hba->outstanding_reqs |= not_cleared; 7418 not_cleared_mask |= not_cleared; 7419 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7420 7421 dev_err(hba->dev, "%s: failed to clear request %d\n", 7422 __func__, pos); 7423 } 7424 } 7425 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7426 7427 out: 7428 hba->req_abort_count = 0; 7429 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7430 if (!err) { 7431 err = SUCCESS; 7432 } else { 7433 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7434 err = FAILED; 7435 } 7436 return err; 7437 } 7438 7439 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7440 { 7441 struct ufshcd_lrb *lrbp; 7442 int tag; 7443 7444 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7445 lrbp = &hba->lrb[tag]; 7446 lrbp->req_abort_skip = true; 7447 } 7448 } 7449 7450 /** 7451 * ufshcd_try_to_abort_task - abort a specific task 7452 * @hba: Pointer to adapter instance 7453 * @tag: Task tag/index to be aborted 7454 * 7455 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7456 * command, and in host controller by clearing the door-bell register. There can 7457 * be race between controller sending the command to the device while abort is 7458 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7459 * really issued and then try to abort it. 7460 * 7461 * Return: zero on success, non-zero on failure. 7462 */ 7463 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7464 { 7465 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7466 int err = 0; 7467 int poll_cnt; 7468 u8 resp = 0xF; 7469 u32 reg; 7470 7471 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7472 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7473 UFS_QUERY_TASK, &resp); 7474 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7475 /* cmd pending in the device */ 7476 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7477 __func__, tag); 7478 break; 7479 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7480 /* 7481 * cmd not pending in the device, check if it is 7482 * in transition. 7483 */ 7484 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n", 7485 __func__, tag); 7486 if (is_mcq_enabled(hba)) { 7487 /* MCQ mode */ 7488 if (ufshcd_cmd_inflight(lrbp->cmd)) { 7489 /* sleep for max. 200us same delay as in SDB mode */ 7490 usleep_range(100, 200); 7491 continue; 7492 } 7493 /* command completed already */ 7494 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n", 7495 __func__, tag); 7496 goto out; 7497 } 7498 7499 /* Single Doorbell Mode */ 7500 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7501 if (reg & (1 << tag)) { 7502 /* sleep for max. 200us to stabilize */ 7503 usleep_range(100, 200); 7504 continue; 7505 } 7506 /* command completed already */ 7507 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n", 7508 __func__, tag); 7509 goto out; 7510 } else { 7511 dev_err(hba->dev, 7512 "%s: no response from device. tag = %d, err %d\n", 7513 __func__, tag, err); 7514 if (!err) 7515 err = resp; /* service response error */ 7516 goto out; 7517 } 7518 } 7519 7520 if (!poll_cnt) { 7521 err = -EBUSY; 7522 goto out; 7523 } 7524 7525 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7526 UFS_ABORT_TASK, &resp); 7527 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7528 if (!err) { 7529 err = resp; /* service response error */ 7530 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7531 __func__, tag, err); 7532 } 7533 goto out; 7534 } 7535 7536 err = ufshcd_clear_cmd(hba, tag); 7537 if (err) 7538 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7539 __func__, tag, err); 7540 7541 out: 7542 return err; 7543 } 7544 7545 /** 7546 * ufshcd_abort - scsi host template eh_abort_handler callback 7547 * @cmd: SCSI command pointer 7548 * 7549 * Return: SUCCESS or FAILED. 7550 */ 7551 static int ufshcd_abort(struct scsi_cmnd *cmd) 7552 { 7553 struct Scsi_Host *host = cmd->device->host; 7554 struct ufs_hba *hba = shost_priv(host); 7555 int tag = scsi_cmd_to_rq(cmd)->tag; 7556 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7557 unsigned long flags; 7558 int err = FAILED; 7559 bool outstanding; 7560 u32 reg; 7561 7562 ufshcd_hold(hba); 7563 7564 if (!is_mcq_enabled(hba)) { 7565 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7566 if (!test_bit(tag, &hba->outstanding_reqs)) { 7567 /* If command is already aborted/completed, return FAILED. */ 7568 dev_err(hba->dev, 7569 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7570 __func__, tag, hba->outstanding_reqs, reg); 7571 goto release; 7572 } 7573 } 7574 7575 /* Print Transfer Request of aborted task */ 7576 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7577 7578 /* 7579 * Print detailed info about aborted request. 7580 * As more than one request might get aborted at the same time, 7581 * print full information only for the first aborted request in order 7582 * to reduce repeated printouts. For other aborted requests only print 7583 * basic details. 7584 */ 7585 scsi_print_command(cmd); 7586 if (!hba->req_abort_count) { 7587 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7588 ufshcd_print_evt_hist(hba); 7589 ufshcd_print_host_state(hba); 7590 ufshcd_print_pwr_info(hba); 7591 ufshcd_print_tr(hba, tag, true); 7592 } else { 7593 ufshcd_print_tr(hba, tag, false); 7594 } 7595 hba->req_abort_count++; 7596 7597 if (!is_mcq_enabled(hba) && !(reg & (1 << tag))) { 7598 /* only execute this code in single doorbell mode */ 7599 dev_err(hba->dev, 7600 "%s: cmd was completed, but without a notifying intr, tag = %d", 7601 __func__, tag); 7602 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7603 goto release; 7604 } 7605 7606 /* 7607 * Task abort to the device W-LUN is illegal. When this command 7608 * will fail, due to spec violation, scsi err handling next step 7609 * will be to send LU reset which, again, is a spec violation. 7610 * To avoid these unnecessary/illegal steps, first we clean up 7611 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7612 * then queue the eh_work and bail. 7613 */ 7614 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7615 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7616 7617 spin_lock_irqsave(host->host_lock, flags); 7618 hba->force_reset = true; 7619 ufshcd_schedule_eh_work(hba); 7620 spin_unlock_irqrestore(host->host_lock, flags); 7621 goto release; 7622 } 7623 7624 if (is_mcq_enabled(hba)) { 7625 /* MCQ mode. Branch off to handle abort for mcq mode */ 7626 err = ufshcd_mcq_abort(cmd); 7627 goto release; 7628 } 7629 7630 /* Skip task abort in case previous aborts failed and report failure */ 7631 if (lrbp->req_abort_skip) { 7632 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7633 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7634 goto release; 7635 } 7636 7637 err = ufshcd_try_to_abort_task(hba, tag); 7638 if (err) { 7639 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7640 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7641 err = FAILED; 7642 goto release; 7643 } 7644 7645 /* 7646 * Clear the corresponding bit from outstanding_reqs since the command 7647 * has been aborted successfully. 7648 */ 7649 spin_lock_irqsave(&hba->outstanding_lock, flags); 7650 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7651 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7652 7653 if (outstanding) 7654 ufshcd_release_scsi_cmd(hba, lrbp); 7655 7656 err = SUCCESS; 7657 7658 release: 7659 /* Matches the ufshcd_hold() call at the start of this function. */ 7660 ufshcd_release(hba); 7661 return err; 7662 } 7663 7664 /** 7665 * ufshcd_host_reset_and_restore - reset and restore host controller 7666 * @hba: per-adapter instance 7667 * 7668 * Note that host controller reset may issue DME_RESET to 7669 * local and remote (device) Uni-Pro stack and the attributes 7670 * are reset to default state. 7671 * 7672 * Return: zero on success, non-zero on failure. 7673 */ 7674 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7675 { 7676 int err; 7677 7678 /* 7679 * Stop the host controller and complete the requests 7680 * cleared by h/w 7681 */ 7682 ufshcd_hba_stop(hba); 7683 hba->silence_err_logs = true; 7684 ufshcd_complete_requests(hba, true); 7685 hba->silence_err_logs = false; 7686 7687 /* scale up clocks to max frequency before full reinitialization */ 7688 ufshcd_scale_clks(hba, ULONG_MAX, true); 7689 7690 err = ufshcd_hba_enable(hba); 7691 7692 /* Establish the link again and restore the device */ 7693 if (!err) 7694 err = ufshcd_probe_hba(hba, false); 7695 7696 if (err) 7697 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7698 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7699 return err; 7700 } 7701 7702 /** 7703 * ufshcd_reset_and_restore - reset and re-initialize host/device 7704 * @hba: per-adapter instance 7705 * 7706 * Reset and recover device, host and re-establish link. This 7707 * is helpful to recover the communication in fatal error conditions. 7708 * 7709 * Return: zero on success, non-zero on failure. 7710 */ 7711 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7712 { 7713 u32 saved_err = 0; 7714 u32 saved_uic_err = 0; 7715 int err = 0; 7716 unsigned long flags; 7717 int retries = MAX_HOST_RESET_RETRIES; 7718 7719 spin_lock_irqsave(hba->host->host_lock, flags); 7720 do { 7721 /* 7722 * This is a fresh start, cache and clear saved error first, 7723 * in case new error generated during reset and restore. 7724 */ 7725 saved_err |= hba->saved_err; 7726 saved_uic_err |= hba->saved_uic_err; 7727 hba->saved_err = 0; 7728 hba->saved_uic_err = 0; 7729 hba->force_reset = false; 7730 hba->ufshcd_state = UFSHCD_STATE_RESET; 7731 spin_unlock_irqrestore(hba->host->host_lock, flags); 7732 7733 /* Reset the attached device */ 7734 ufshcd_device_reset(hba); 7735 7736 err = ufshcd_host_reset_and_restore(hba); 7737 7738 spin_lock_irqsave(hba->host->host_lock, flags); 7739 if (err) 7740 continue; 7741 /* Do not exit unless operational or dead */ 7742 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7743 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7744 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7745 err = -EAGAIN; 7746 } while (err && --retries); 7747 7748 /* 7749 * Inform scsi mid-layer that we did reset and allow to handle 7750 * Unit Attention properly. 7751 */ 7752 scsi_report_bus_reset(hba->host, 0); 7753 if (err) { 7754 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7755 hba->saved_err |= saved_err; 7756 hba->saved_uic_err |= saved_uic_err; 7757 } 7758 spin_unlock_irqrestore(hba->host->host_lock, flags); 7759 7760 return err; 7761 } 7762 7763 /** 7764 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7765 * @cmd: SCSI command pointer 7766 * 7767 * Return: SUCCESS or FAILED. 7768 */ 7769 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7770 { 7771 int err = SUCCESS; 7772 unsigned long flags; 7773 struct ufs_hba *hba; 7774 7775 hba = shost_priv(cmd->device->host); 7776 7777 /* 7778 * If runtime PM sent SSU and got a timeout, scsi_error_handler is 7779 * stuck in this function waiting for flush_work(&hba->eh_work). And 7780 * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do 7781 * ufshcd_link_recovery instead of eh_work to prevent deadlock. 7782 */ 7783 if (hba->pm_op_in_progress) { 7784 if (ufshcd_link_recovery(hba)) 7785 err = FAILED; 7786 7787 return err; 7788 } 7789 7790 spin_lock_irqsave(hba->host->host_lock, flags); 7791 hba->force_reset = true; 7792 ufshcd_schedule_eh_work(hba); 7793 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7794 spin_unlock_irqrestore(hba->host->host_lock, flags); 7795 7796 flush_work(&hba->eh_work); 7797 7798 spin_lock_irqsave(hba->host->host_lock, flags); 7799 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7800 err = FAILED; 7801 spin_unlock_irqrestore(hba->host->host_lock, flags); 7802 7803 return err; 7804 } 7805 7806 /** 7807 * ufshcd_get_max_icc_level - calculate the ICC level 7808 * @sup_curr_uA: max. current supported by the regulator 7809 * @start_scan: row at the desc table to start scan from 7810 * @buff: power descriptor buffer 7811 * 7812 * Return: calculated max ICC level for specific regulator. 7813 */ 7814 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7815 const char *buff) 7816 { 7817 int i; 7818 int curr_uA; 7819 u16 data; 7820 u16 unit; 7821 7822 for (i = start_scan; i >= 0; i--) { 7823 data = get_unaligned_be16(&buff[2 * i]); 7824 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7825 ATTR_ICC_LVL_UNIT_OFFSET; 7826 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7827 switch (unit) { 7828 case UFSHCD_NANO_AMP: 7829 curr_uA = curr_uA / 1000; 7830 break; 7831 case UFSHCD_MILI_AMP: 7832 curr_uA = curr_uA * 1000; 7833 break; 7834 case UFSHCD_AMP: 7835 curr_uA = curr_uA * 1000 * 1000; 7836 break; 7837 case UFSHCD_MICRO_AMP: 7838 default: 7839 break; 7840 } 7841 if (sup_curr_uA >= curr_uA) 7842 break; 7843 } 7844 if (i < 0) { 7845 i = 0; 7846 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7847 } 7848 7849 return (u32)i; 7850 } 7851 7852 /** 7853 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7854 * In case regulators are not initialized we'll return 0 7855 * @hba: per-adapter instance 7856 * @desc_buf: power descriptor buffer to extract ICC levels from. 7857 * 7858 * Return: calculated ICC level. 7859 */ 7860 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7861 const u8 *desc_buf) 7862 { 7863 u32 icc_level = 0; 7864 7865 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7866 !hba->vreg_info.vccq2) { 7867 /* 7868 * Using dev_dbg to avoid messages during runtime PM to avoid 7869 * never-ending cycles of messages written back to storage by 7870 * user space causing runtime resume, causing more messages and 7871 * so on. 7872 */ 7873 dev_dbg(hba->dev, 7874 "%s: Regulator capability was not set, actvIccLevel=%d", 7875 __func__, icc_level); 7876 goto out; 7877 } 7878 7879 if (hba->vreg_info.vcc->max_uA) 7880 icc_level = ufshcd_get_max_icc_level( 7881 hba->vreg_info.vcc->max_uA, 7882 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7883 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7884 7885 if (hba->vreg_info.vccq->max_uA) 7886 icc_level = ufshcd_get_max_icc_level( 7887 hba->vreg_info.vccq->max_uA, 7888 icc_level, 7889 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7890 7891 if (hba->vreg_info.vccq2->max_uA) 7892 icc_level = ufshcd_get_max_icc_level( 7893 hba->vreg_info.vccq2->max_uA, 7894 icc_level, 7895 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7896 out: 7897 return icc_level; 7898 } 7899 7900 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7901 { 7902 int ret; 7903 u8 *desc_buf; 7904 u32 icc_level; 7905 7906 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7907 if (!desc_buf) 7908 return; 7909 7910 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7911 desc_buf, QUERY_DESC_MAX_SIZE); 7912 if (ret) { 7913 dev_err(hba->dev, 7914 "%s: Failed reading power descriptor ret = %d", 7915 __func__, ret); 7916 goto out; 7917 } 7918 7919 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7920 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7921 7922 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7923 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7924 7925 if (ret) 7926 dev_err(hba->dev, 7927 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7928 __func__, icc_level, ret); 7929 7930 out: 7931 kfree(desc_buf); 7932 } 7933 7934 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7935 { 7936 struct Scsi_Host *shost = sdev->host; 7937 7938 scsi_autopm_get_device(sdev); 7939 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7940 if (sdev->rpm_autosuspend) 7941 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7942 shost->rpm_autosuspend_delay); 7943 scsi_autopm_put_device(sdev); 7944 } 7945 7946 /** 7947 * ufshcd_scsi_add_wlus - Adds required W-LUs 7948 * @hba: per-adapter instance 7949 * 7950 * UFS device specification requires the UFS devices to support 4 well known 7951 * logical units: 7952 * "REPORT_LUNS" (address: 01h) 7953 * "UFS Device" (address: 50h) 7954 * "RPMB" (address: 44h) 7955 * "BOOT" (address: 30h) 7956 * UFS device's power management needs to be controlled by "POWER CONDITION" 7957 * field of SSU (START STOP UNIT) command. But this "power condition" field 7958 * will take effect only when its sent to "UFS device" well known logical unit 7959 * hence we require the scsi_device instance to represent this logical unit in 7960 * order for the UFS host driver to send the SSU command for power management. 7961 * 7962 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 7963 * Block) LU so user space process can control this LU. User space may also 7964 * want to have access to BOOT LU. 7965 * 7966 * This function adds scsi device instances for each of all well known LUs 7967 * (except "REPORT LUNS" LU). 7968 * 7969 * Return: zero on success (all required W-LUs are added successfully), 7970 * non-zero error value on failure (if failed to add any of the required W-LU). 7971 */ 7972 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 7973 { 7974 int ret = 0; 7975 struct scsi_device *sdev_boot, *sdev_rpmb; 7976 7977 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 7978 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 7979 if (IS_ERR(hba->ufs_device_wlun)) { 7980 ret = PTR_ERR(hba->ufs_device_wlun); 7981 hba->ufs_device_wlun = NULL; 7982 goto out; 7983 } 7984 scsi_device_put(hba->ufs_device_wlun); 7985 7986 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 7987 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 7988 if (IS_ERR(sdev_rpmb)) { 7989 ret = PTR_ERR(sdev_rpmb); 7990 goto remove_ufs_device_wlun; 7991 } 7992 ufshcd_blk_pm_runtime_init(sdev_rpmb); 7993 scsi_device_put(sdev_rpmb); 7994 7995 sdev_boot = __scsi_add_device(hba->host, 0, 0, 7996 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 7997 if (IS_ERR(sdev_boot)) { 7998 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 7999 } else { 8000 ufshcd_blk_pm_runtime_init(sdev_boot); 8001 scsi_device_put(sdev_boot); 8002 } 8003 goto out; 8004 8005 remove_ufs_device_wlun: 8006 scsi_remove_device(hba->ufs_device_wlun); 8007 out: 8008 return ret; 8009 } 8010 8011 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 8012 { 8013 struct ufs_dev_info *dev_info = &hba->dev_info; 8014 u8 lun; 8015 u32 d_lu_wb_buf_alloc; 8016 u32 ext_ufs_feature; 8017 8018 if (!ufshcd_is_wb_allowed(hba)) 8019 return; 8020 8021 /* 8022 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 8023 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 8024 * enabled 8025 */ 8026 if (!(dev_info->wspecversion >= 0x310 || 8027 dev_info->wspecversion == 0x220 || 8028 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 8029 goto wb_disabled; 8030 8031 ext_ufs_feature = get_unaligned_be32(desc_buf + 8032 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8033 8034 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 8035 goto wb_disabled; 8036 8037 /* 8038 * WB may be supported but not configured while provisioning. The spec 8039 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 8040 * buffer configured. 8041 */ 8042 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 8043 8044 dev_info->b_presrv_uspc_en = 8045 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 8046 8047 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 8048 if (!get_unaligned_be32(desc_buf + 8049 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 8050 goto wb_disabled; 8051 } else { 8052 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 8053 d_lu_wb_buf_alloc = 0; 8054 ufshcd_read_unit_desc_param(hba, 8055 lun, 8056 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 8057 (u8 *)&d_lu_wb_buf_alloc, 8058 sizeof(d_lu_wb_buf_alloc)); 8059 if (d_lu_wb_buf_alloc) { 8060 dev_info->wb_dedicated_lu = lun; 8061 break; 8062 } 8063 } 8064 8065 if (!d_lu_wb_buf_alloc) 8066 goto wb_disabled; 8067 } 8068 8069 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8070 goto wb_disabled; 8071 8072 return; 8073 8074 wb_disabled: 8075 hba->caps &= ~UFSHCD_CAP_WB_EN; 8076 } 8077 8078 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8079 { 8080 struct ufs_dev_info *dev_info = &hba->dev_info; 8081 u32 ext_ufs_feature; 8082 u8 mask = 0; 8083 8084 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8085 return; 8086 8087 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8088 8089 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8090 mask |= MASK_EE_TOO_LOW_TEMP; 8091 8092 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8093 mask |= MASK_EE_TOO_HIGH_TEMP; 8094 8095 if (mask) { 8096 ufshcd_enable_ee(hba, mask); 8097 ufs_hwmon_probe(hba, mask); 8098 } 8099 } 8100 8101 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8102 { 8103 struct ufs_dev_info *dev_info = &hba->dev_info; 8104 u32 ext_ufs_feature; 8105 u32 ext_iid_en = 0; 8106 int err; 8107 8108 /* Only UFS-4.0 and above may support EXT_IID */ 8109 if (dev_info->wspecversion < 0x400) 8110 goto out; 8111 8112 ext_ufs_feature = get_unaligned_be32(desc_buf + 8113 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8114 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8115 goto out; 8116 8117 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8118 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8119 if (err) 8120 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8121 8122 out: 8123 dev_info->b_ext_iid_en = ext_iid_en; 8124 } 8125 8126 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8127 const struct ufs_dev_quirk *fixups) 8128 { 8129 const struct ufs_dev_quirk *f; 8130 struct ufs_dev_info *dev_info = &hba->dev_info; 8131 8132 if (!fixups) 8133 return; 8134 8135 for (f = fixups; f->quirk; f++) { 8136 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8137 f->wmanufacturerid == UFS_ANY_VENDOR) && 8138 ((dev_info->model && 8139 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8140 !strcmp(f->model, UFS_ANY_MODEL))) 8141 hba->dev_quirks |= f->quirk; 8142 } 8143 } 8144 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8145 8146 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8147 { 8148 /* fix by general quirk table */ 8149 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8150 8151 /* allow vendors to fix quirks */ 8152 ufshcd_vops_fixup_dev_quirks(hba); 8153 } 8154 8155 static void ufshcd_update_rtc(struct ufs_hba *hba) 8156 { 8157 struct timespec64 ts64; 8158 int err; 8159 u32 val; 8160 8161 ktime_get_real_ts64(&ts64); 8162 8163 if (ts64.tv_sec < hba->dev_info.rtc_time_baseline) { 8164 dev_warn_once(hba->dev, "%s: Current time precedes previous setting!\n", __func__); 8165 return; 8166 } 8167 8168 /* 8169 * The Absolute RTC mode has a 136-year limit, spanning from 2010 to 2146. If a time beyond 8170 * 2146 is required, it is recommended to choose the relative RTC mode. 8171 */ 8172 val = ts64.tv_sec - hba->dev_info.rtc_time_baseline; 8173 8174 ufshcd_rpm_get_sync(hba); 8175 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_SECONDS_PASSED, 8176 0, 0, &val); 8177 ufshcd_rpm_put_sync(hba); 8178 8179 if (err) 8180 dev_err(hba->dev, "%s: Failed to update rtc %d\n", __func__, err); 8181 else if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 8182 hba->dev_info.rtc_time_baseline = ts64.tv_sec; 8183 } 8184 8185 static void ufshcd_rtc_work(struct work_struct *work) 8186 { 8187 struct ufs_hba *hba; 8188 8189 hba = container_of(to_delayed_work(work), struct ufs_hba, ufs_rtc_update_work); 8190 8191 /* Update RTC only when there are no requests in progress and UFSHCI is operational */ 8192 if (!ufshcd_is_ufs_dev_busy(hba) && hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) 8193 ufshcd_update_rtc(hba); 8194 8195 if (ufshcd_is_ufs_dev_active(hba) && hba->dev_info.rtc_update_period) 8196 schedule_delayed_work(&hba->ufs_rtc_update_work, 8197 msecs_to_jiffies(hba->dev_info.rtc_update_period)); 8198 } 8199 8200 static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf) 8201 { 8202 u16 periodic_rtc_update = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_FRQ_RTC]); 8203 struct ufs_dev_info *dev_info = &hba->dev_info; 8204 8205 if (periodic_rtc_update & UFS_RTC_TIME_BASELINE) { 8206 dev_info->rtc_type = UFS_RTC_ABSOLUTE; 8207 8208 /* 8209 * The concept of measuring time in Linux as the number of seconds elapsed since 8210 * 00:00:00 UTC on January 1, 1970, and UFS ABS RTC is elapsed from January 1st 8211 * 2010 00:00, here we need to adjust ABS baseline. 8212 */ 8213 dev_info->rtc_time_baseline = mktime64(2010, 1, 1, 0, 0, 0) - 8214 mktime64(1970, 1, 1, 0, 0, 0); 8215 } else { 8216 dev_info->rtc_type = UFS_RTC_RELATIVE; 8217 dev_info->rtc_time_baseline = 0; 8218 } 8219 8220 /* 8221 * We ignore TIME_PERIOD defined in wPeriodicRTCUpdate because Spec does not clearly state 8222 * how to calculate the specific update period for each time unit. And we disable periodic 8223 * RTC update work, let user configure by sysfs node according to specific circumstance. 8224 */ 8225 dev_info->rtc_update_period = 0; 8226 } 8227 8228 static int ufs_get_device_desc(struct ufs_hba *hba) 8229 { 8230 int err; 8231 u8 model_index; 8232 u8 *desc_buf; 8233 struct ufs_dev_info *dev_info = &hba->dev_info; 8234 8235 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8236 if (!desc_buf) { 8237 err = -ENOMEM; 8238 goto out; 8239 } 8240 8241 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8242 QUERY_DESC_MAX_SIZE); 8243 if (err) { 8244 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8245 __func__, err); 8246 goto out; 8247 } 8248 8249 /* 8250 * getting vendor (manufacturerID) and Bank Index in big endian 8251 * format 8252 */ 8253 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8254 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8255 8256 /* getting Specification Version in big endian format */ 8257 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8258 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8259 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8260 8261 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8262 8263 err = ufshcd_read_string_desc(hba, model_index, 8264 &dev_info->model, SD_ASCII_STD); 8265 if (err < 0) { 8266 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8267 __func__, err); 8268 goto out; 8269 } 8270 8271 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8272 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8273 8274 ufs_fixup_device_setup(hba); 8275 8276 ufshcd_wb_probe(hba, desc_buf); 8277 8278 ufshcd_temp_notif_probe(hba, desc_buf); 8279 8280 ufs_init_rtc(hba, desc_buf); 8281 8282 if (hba->ext_iid_sup) 8283 ufshcd_ext_iid_probe(hba, desc_buf); 8284 8285 /* 8286 * ufshcd_read_string_desc returns size of the string 8287 * reset the error value 8288 */ 8289 err = 0; 8290 8291 out: 8292 kfree(desc_buf); 8293 return err; 8294 } 8295 8296 static void ufs_put_device_desc(struct ufs_hba *hba) 8297 { 8298 struct ufs_dev_info *dev_info = &hba->dev_info; 8299 8300 kfree(dev_info->model); 8301 dev_info->model = NULL; 8302 } 8303 8304 /** 8305 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8306 * less than device PA_TACTIVATE time. 8307 * @hba: per-adapter instance 8308 * 8309 * Some UFS devices require host PA_TACTIVATE to be lower than device 8310 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8311 * for such devices. 8312 * 8313 * Return: zero on success, non-zero error value on failure. 8314 */ 8315 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8316 { 8317 int ret = 0; 8318 u32 granularity, peer_granularity; 8319 u32 pa_tactivate, peer_pa_tactivate; 8320 u32 pa_tactivate_us, peer_pa_tactivate_us; 8321 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8322 8323 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8324 &granularity); 8325 if (ret) 8326 goto out; 8327 8328 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8329 &peer_granularity); 8330 if (ret) 8331 goto out; 8332 8333 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8334 (granularity > PA_GRANULARITY_MAX_VAL)) { 8335 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8336 __func__, granularity); 8337 return -EINVAL; 8338 } 8339 8340 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8341 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8342 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8343 __func__, peer_granularity); 8344 return -EINVAL; 8345 } 8346 8347 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8348 if (ret) 8349 goto out; 8350 8351 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8352 &peer_pa_tactivate); 8353 if (ret) 8354 goto out; 8355 8356 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8357 peer_pa_tactivate_us = peer_pa_tactivate * 8358 gran_to_us_table[peer_granularity - 1]; 8359 8360 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8361 u32 new_peer_pa_tactivate; 8362 8363 new_peer_pa_tactivate = pa_tactivate_us / 8364 gran_to_us_table[peer_granularity - 1]; 8365 new_peer_pa_tactivate++; 8366 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8367 new_peer_pa_tactivate); 8368 } 8369 8370 out: 8371 return ret; 8372 } 8373 8374 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8375 { 8376 ufshcd_vops_apply_dev_quirks(hba); 8377 8378 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8379 /* set 1ms timeout for PA_TACTIVATE */ 8380 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8381 8382 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8383 ufshcd_quirk_tune_host_pa_tactivate(hba); 8384 } 8385 8386 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8387 { 8388 hba->ufs_stats.hibern8_exit_cnt = 0; 8389 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8390 hba->req_abort_count = 0; 8391 } 8392 8393 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8394 { 8395 int err; 8396 u8 *desc_buf; 8397 8398 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8399 if (!desc_buf) { 8400 err = -ENOMEM; 8401 goto out; 8402 } 8403 8404 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8405 desc_buf, QUERY_DESC_MAX_SIZE); 8406 if (err) { 8407 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8408 __func__, err); 8409 goto out; 8410 } 8411 8412 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8413 hba->dev_info.max_lu_supported = 32; 8414 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8415 hba->dev_info.max_lu_supported = 8; 8416 8417 out: 8418 kfree(desc_buf); 8419 return err; 8420 } 8421 8422 struct ufs_ref_clk { 8423 unsigned long freq_hz; 8424 enum ufs_ref_clk_freq val; 8425 }; 8426 8427 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8428 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8429 {26000000, REF_CLK_FREQ_26_MHZ}, 8430 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8431 {52000000, REF_CLK_FREQ_52_MHZ}, 8432 {0, REF_CLK_FREQ_INVAL}, 8433 }; 8434 8435 static enum ufs_ref_clk_freq 8436 ufs_get_bref_clk_from_hz(unsigned long freq) 8437 { 8438 int i; 8439 8440 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8441 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8442 return ufs_ref_clk_freqs[i].val; 8443 8444 return REF_CLK_FREQ_INVAL; 8445 } 8446 8447 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8448 { 8449 unsigned long freq; 8450 8451 freq = clk_get_rate(refclk); 8452 8453 hba->dev_ref_clk_freq = 8454 ufs_get_bref_clk_from_hz(freq); 8455 8456 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8457 dev_err(hba->dev, 8458 "invalid ref_clk setting = %ld\n", freq); 8459 } 8460 8461 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8462 { 8463 int err; 8464 u32 ref_clk; 8465 u32 freq = hba->dev_ref_clk_freq; 8466 8467 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8468 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8469 8470 if (err) { 8471 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8472 err); 8473 goto out; 8474 } 8475 8476 if (ref_clk == freq) 8477 goto out; /* nothing to update */ 8478 8479 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8480 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8481 8482 if (err) { 8483 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8484 ufs_ref_clk_freqs[freq].freq_hz); 8485 goto out; 8486 } 8487 8488 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8489 ufs_ref_clk_freqs[freq].freq_hz); 8490 8491 out: 8492 return err; 8493 } 8494 8495 static int ufshcd_device_params_init(struct ufs_hba *hba) 8496 { 8497 bool flag; 8498 int ret; 8499 8500 /* Init UFS geometry descriptor related parameters */ 8501 ret = ufshcd_device_geo_params_init(hba); 8502 if (ret) 8503 goto out; 8504 8505 /* Check and apply UFS device quirks */ 8506 ret = ufs_get_device_desc(hba); 8507 if (ret) { 8508 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8509 __func__, ret); 8510 goto out; 8511 } 8512 8513 ufshcd_get_ref_clk_gating_wait(hba); 8514 8515 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8516 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8517 hba->dev_info.f_power_on_wp_en = flag; 8518 8519 /* Probe maximum power mode co-supported by both UFS host and device */ 8520 if (ufshcd_get_max_pwr_mode(hba)) 8521 dev_err(hba->dev, 8522 "%s: Failed getting max supported power mode\n", 8523 __func__); 8524 out: 8525 return ret; 8526 } 8527 8528 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8529 { 8530 int err; 8531 struct ufs_query_req *request = NULL; 8532 struct ufs_query_res *response = NULL; 8533 struct ufs_dev_info *dev_info = &hba->dev_info; 8534 struct utp_upiu_query_v4_0 *upiu_data; 8535 8536 if (dev_info->wspecversion < 0x400) 8537 return; 8538 8539 ufshcd_dev_man_lock(hba); 8540 8541 ufshcd_init_query(hba, &request, &response, 8542 UPIU_QUERY_OPCODE_WRITE_ATTR, 8543 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8544 8545 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8546 8547 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8548 8549 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8550 8551 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8552 8553 if (err) 8554 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8555 __func__, err); 8556 8557 ufshcd_dev_man_unlock(hba); 8558 } 8559 8560 /** 8561 * ufshcd_add_lus - probe and add UFS logical units 8562 * @hba: per-adapter instance 8563 * 8564 * Return: 0 upon success; < 0 upon failure. 8565 */ 8566 static int ufshcd_add_lus(struct ufs_hba *hba) 8567 { 8568 int ret; 8569 8570 /* Add required well known logical units to scsi mid layer */ 8571 ret = ufshcd_scsi_add_wlus(hba); 8572 if (ret) 8573 goto out; 8574 8575 /* Initialize devfreq after UFS device is detected */ 8576 if (ufshcd_is_clkscaling_supported(hba)) { 8577 memcpy(&hba->clk_scaling.saved_pwr_info, 8578 &hba->pwr_info, 8579 sizeof(struct ufs_pa_layer_attr)); 8580 hba->clk_scaling.is_allowed = true; 8581 8582 ret = ufshcd_devfreq_init(hba); 8583 if (ret) 8584 goto out; 8585 8586 hba->clk_scaling.is_enabled = true; 8587 ufshcd_init_clk_scaling_sysfs(hba); 8588 } 8589 8590 ufs_bsg_probe(hba); 8591 scsi_scan_host(hba->host); 8592 8593 out: 8594 return ret; 8595 } 8596 8597 /* SDB - Single Doorbell */ 8598 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8599 { 8600 size_t ucdl_size, utrdl_size; 8601 8602 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8603 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8604 hba->ucdl_dma_addr); 8605 8606 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8607 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8608 hba->utrdl_dma_addr); 8609 8610 devm_kfree(hba->dev, hba->lrb); 8611 } 8612 8613 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8614 { 8615 int ret; 8616 int old_nutrs = hba->nutrs; 8617 8618 ret = ufshcd_mcq_decide_queue_depth(hba); 8619 if (ret < 0) 8620 return ret; 8621 8622 hba->nutrs = ret; 8623 ret = ufshcd_mcq_init(hba); 8624 if (ret) 8625 goto err; 8626 8627 /* 8628 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8629 * Number of supported tags in MCQ mode may be larger than SDB mode. 8630 */ 8631 if (hba->nutrs != old_nutrs) { 8632 ufshcd_release_sdb_queue(hba, old_nutrs); 8633 ret = ufshcd_memory_alloc(hba); 8634 if (ret) 8635 goto err; 8636 ufshcd_host_memory_configure(hba); 8637 } 8638 8639 ret = ufshcd_mcq_memory_alloc(hba); 8640 if (ret) 8641 goto err; 8642 8643 return 0; 8644 err: 8645 hba->nutrs = old_nutrs; 8646 return ret; 8647 } 8648 8649 static void ufshcd_config_mcq(struct ufs_hba *hba) 8650 { 8651 int ret; 8652 u32 intrs; 8653 8654 ret = ufshcd_mcq_vops_config_esi(hba); 8655 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8656 8657 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8658 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8659 intrs &= ~MCQ_CQ_EVENT_STATUS; 8660 ufshcd_enable_intr(hba, intrs); 8661 ufshcd_mcq_make_queues_operational(hba); 8662 ufshcd_mcq_config_mac(hba, hba->nutrs); 8663 8664 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8665 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8666 8667 ufshcd_mcq_enable(hba); 8668 hba->mcq_enabled = true; 8669 8670 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8671 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8672 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8673 hba->nutrs); 8674 } 8675 8676 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8677 { 8678 int ret; 8679 struct Scsi_Host *host = hba->host; 8680 8681 hba->ufshcd_state = UFSHCD_STATE_RESET; 8682 8683 ret = ufshcd_link_startup(hba); 8684 if (ret) 8685 return ret; 8686 8687 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8688 return ret; 8689 8690 /* Debug counters initialization */ 8691 ufshcd_clear_dbg_ufs_stats(hba); 8692 8693 /* UniPro link is active now */ 8694 ufshcd_set_link_active(hba); 8695 8696 /* Reconfigure MCQ upon reset */ 8697 if (is_mcq_enabled(hba) && !init_dev_params) 8698 ufshcd_config_mcq(hba); 8699 8700 /* Verify device initialization by sending NOP OUT UPIU */ 8701 ret = ufshcd_verify_dev_init(hba); 8702 if (ret) 8703 return ret; 8704 8705 /* Initiate UFS initialization, and waiting until completion */ 8706 ret = ufshcd_complete_dev_init(hba); 8707 if (ret) 8708 return ret; 8709 8710 /* 8711 * Initialize UFS device parameters used by driver, these 8712 * parameters are associated with UFS descriptors. 8713 */ 8714 if (init_dev_params) { 8715 ret = ufshcd_device_params_init(hba); 8716 if (ret) 8717 return ret; 8718 if (is_mcq_supported(hba) && !hba->scsi_host_added) { 8719 ret = ufshcd_alloc_mcq(hba); 8720 if (!ret) { 8721 ufshcd_config_mcq(hba); 8722 } else { 8723 /* Continue with SDB mode */ 8724 use_mcq_mode = false; 8725 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 8726 ret); 8727 } 8728 ret = scsi_add_host(host, hba->dev); 8729 if (ret) { 8730 dev_err(hba->dev, "scsi_add_host failed\n"); 8731 return ret; 8732 } 8733 hba->scsi_host_added = true; 8734 } else if (is_mcq_supported(hba)) { 8735 /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */ 8736 ufshcd_config_mcq(hba); 8737 } 8738 } 8739 8740 ufshcd_tune_unipro_params(hba); 8741 8742 /* UFS device is also active now */ 8743 ufshcd_set_ufs_dev_active(hba); 8744 ufshcd_force_reset_auto_bkops(hba); 8745 8746 ufshcd_set_timestamp_attr(hba); 8747 schedule_delayed_work(&hba->ufs_rtc_update_work, 8748 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 8749 8750 /* Gear up to HS gear if supported */ 8751 if (hba->max_pwr_info.is_valid) { 8752 /* 8753 * Set the right value to bRefClkFreq before attempting to 8754 * switch to HS gears. 8755 */ 8756 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8757 ufshcd_set_dev_ref_clk(hba); 8758 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8759 if (ret) { 8760 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8761 __func__, ret); 8762 return ret; 8763 } 8764 } 8765 8766 return 0; 8767 } 8768 8769 /** 8770 * ufshcd_probe_hba - probe hba to detect device and initialize it 8771 * @hba: per-adapter instance 8772 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8773 * 8774 * Execute link-startup and verify device initialization 8775 * 8776 * Return: 0 upon success; < 0 upon failure. 8777 */ 8778 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8779 { 8780 ktime_t start = ktime_get(); 8781 unsigned long flags; 8782 int ret; 8783 8784 ret = ufshcd_device_init(hba, init_dev_params); 8785 if (ret) 8786 goto out; 8787 8788 if (!hba->pm_op_in_progress && 8789 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8790 /* Reset the device and controller before doing reinit */ 8791 ufshcd_device_reset(hba); 8792 ufshcd_hba_stop(hba); 8793 ufshcd_vops_reinit_notify(hba); 8794 ret = ufshcd_hba_enable(hba); 8795 if (ret) { 8796 dev_err(hba->dev, "Host controller enable failed\n"); 8797 ufshcd_print_evt_hist(hba); 8798 ufshcd_print_host_state(hba); 8799 goto out; 8800 } 8801 8802 /* Reinit the device */ 8803 ret = ufshcd_device_init(hba, init_dev_params); 8804 if (ret) 8805 goto out; 8806 } 8807 8808 ufshcd_print_pwr_info(hba); 8809 8810 /* 8811 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8812 * and for removable UFS card as well, hence always set the parameter. 8813 * Note: Error handler may issue the device reset hence resetting 8814 * bActiveICCLevel as well so it is always safe to set this here. 8815 */ 8816 ufshcd_set_active_icc_lvl(hba); 8817 8818 /* Enable UFS Write Booster if supported */ 8819 ufshcd_configure_wb(hba); 8820 8821 if (hba->ee_usr_mask) 8822 ufshcd_write_ee_control(hba); 8823 ufshcd_configure_auto_hibern8(hba); 8824 8825 out: 8826 spin_lock_irqsave(hba->host->host_lock, flags); 8827 if (ret) 8828 hba->ufshcd_state = UFSHCD_STATE_ERROR; 8829 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 8830 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 8831 spin_unlock_irqrestore(hba->host->host_lock, flags); 8832 8833 trace_ufshcd_init(dev_name(hba->dev), ret, 8834 ktime_to_us(ktime_sub(ktime_get(), start)), 8835 hba->curr_dev_pwr_mode, hba->uic_link_state); 8836 return ret; 8837 } 8838 8839 /** 8840 * ufshcd_async_scan - asynchronous execution for probing hba 8841 * @data: data pointer to pass to this function 8842 * @cookie: cookie data 8843 */ 8844 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8845 { 8846 struct ufs_hba *hba = (struct ufs_hba *)data; 8847 int ret; 8848 8849 down(&hba->host_sem); 8850 /* Initialize hba, detect and initialize UFS device */ 8851 ret = ufshcd_probe_hba(hba, true); 8852 up(&hba->host_sem); 8853 if (ret) 8854 goto out; 8855 8856 /* Probe and add UFS logical units */ 8857 ret = ufshcd_add_lus(hba); 8858 8859 out: 8860 pm_runtime_put_sync(hba->dev); 8861 8862 if (ret) 8863 dev_err(hba->dev, "%s failed: %d\n", __func__, ret); 8864 } 8865 8866 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8867 { 8868 struct ufs_hba *hba = shost_priv(scmd->device->host); 8869 8870 if (!hba->system_suspending) { 8871 /* Activate the error handler in the SCSI core. */ 8872 return SCSI_EH_NOT_HANDLED; 8873 } 8874 8875 /* 8876 * If we get here we know that no TMFs are outstanding and also that 8877 * the only pending command is a START STOP UNIT command. Handle the 8878 * timeout of that command directly to prevent a deadlock between 8879 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8880 */ 8881 ufshcd_link_recovery(hba); 8882 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8883 __func__, hba->outstanding_tasks); 8884 8885 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8886 } 8887 8888 static const struct attribute_group *ufshcd_driver_groups[] = { 8889 &ufs_sysfs_unit_descriptor_group, 8890 &ufs_sysfs_lun_attributes_group, 8891 NULL, 8892 }; 8893 8894 static struct ufs_hba_variant_params ufs_hba_vps = { 8895 .hba_enable_delay_us = 1000, 8896 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8897 .devfreq_profile.polling_ms = 100, 8898 .devfreq_profile.target = ufshcd_devfreq_target, 8899 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8900 .ondemand_data.upthreshold = 70, 8901 .ondemand_data.downdifferential = 5, 8902 }; 8903 8904 static const struct scsi_host_template ufshcd_driver_template = { 8905 .module = THIS_MODULE, 8906 .name = UFSHCD, 8907 .proc_name = UFSHCD, 8908 .map_queues = ufshcd_map_queues, 8909 .queuecommand = ufshcd_queuecommand, 8910 .mq_poll = ufshcd_poll, 8911 .slave_alloc = ufshcd_slave_alloc, 8912 .device_configure = ufshcd_device_configure, 8913 .slave_destroy = ufshcd_slave_destroy, 8914 .change_queue_depth = ufshcd_change_queue_depth, 8915 .eh_abort_handler = ufshcd_abort, 8916 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8917 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8918 .eh_timed_out = ufshcd_eh_timed_out, 8919 .this_id = -1, 8920 .sg_tablesize = SG_ALL, 8921 .cmd_per_lun = UFSHCD_CMD_PER_LUN, 8922 .can_queue = UFSHCD_CAN_QUEUE, 8923 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8924 .max_sectors = SZ_1M / SECTOR_SIZE, 8925 .max_host_blocked = 1, 8926 .track_queue_depth = 1, 8927 .skip_settle_delay = 1, 8928 .sdev_groups = ufshcd_driver_groups, 8929 }; 8930 8931 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8932 int ua) 8933 { 8934 int ret; 8935 8936 if (!vreg) 8937 return 0; 8938 8939 /* 8940 * "set_load" operation shall be required on those regulators 8941 * which specifically configured current limitation. Otherwise 8942 * zero max_uA may cause unexpected behavior when regulator is 8943 * enabled or set as high power mode. 8944 */ 8945 if (!vreg->max_uA) 8946 return 0; 8947 8948 ret = regulator_set_load(vreg->reg, ua); 8949 if (ret < 0) { 8950 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 8951 __func__, vreg->name, ua, ret); 8952 } 8953 8954 return ret; 8955 } 8956 8957 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 8958 struct ufs_vreg *vreg) 8959 { 8960 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 8961 } 8962 8963 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 8964 struct ufs_vreg *vreg) 8965 { 8966 if (!vreg) 8967 return 0; 8968 8969 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 8970 } 8971 8972 static int ufshcd_config_vreg(struct device *dev, 8973 struct ufs_vreg *vreg, bool on) 8974 { 8975 if (regulator_count_voltages(vreg->reg) <= 0) 8976 return 0; 8977 8978 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 8979 } 8980 8981 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 8982 { 8983 int ret = 0; 8984 8985 if (!vreg || vreg->enabled) 8986 goto out; 8987 8988 ret = ufshcd_config_vreg(dev, vreg, true); 8989 if (!ret) 8990 ret = regulator_enable(vreg->reg); 8991 8992 if (!ret) 8993 vreg->enabled = true; 8994 else 8995 dev_err(dev, "%s: %s enable failed, err=%d\n", 8996 __func__, vreg->name, ret); 8997 out: 8998 return ret; 8999 } 9000 9001 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 9002 { 9003 int ret = 0; 9004 9005 if (!vreg || !vreg->enabled || vreg->always_on) 9006 goto out; 9007 9008 ret = regulator_disable(vreg->reg); 9009 9010 if (!ret) { 9011 /* ignore errors on applying disable config */ 9012 ufshcd_config_vreg(dev, vreg, false); 9013 vreg->enabled = false; 9014 } else { 9015 dev_err(dev, "%s: %s disable failed, err=%d\n", 9016 __func__, vreg->name, ret); 9017 } 9018 out: 9019 return ret; 9020 } 9021 9022 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 9023 { 9024 int ret = 0; 9025 struct device *dev = hba->dev; 9026 struct ufs_vreg_info *info = &hba->vreg_info; 9027 9028 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 9029 if (ret) 9030 goto out; 9031 9032 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 9033 if (ret) 9034 goto out; 9035 9036 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 9037 9038 out: 9039 if (ret) { 9040 ufshcd_toggle_vreg(dev, info->vccq2, false); 9041 ufshcd_toggle_vreg(dev, info->vccq, false); 9042 ufshcd_toggle_vreg(dev, info->vcc, false); 9043 } 9044 return ret; 9045 } 9046 9047 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9048 { 9049 struct ufs_vreg_info *info = &hba->vreg_info; 9050 9051 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9052 } 9053 9054 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9055 { 9056 int ret = 0; 9057 9058 if (!vreg) 9059 goto out; 9060 9061 vreg->reg = devm_regulator_get(dev, vreg->name); 9062 if (IS_ERR(vreg->reg)) { 9063 ret = PTR_ERR(vreg->reg); 9064 dev_err(dev, "%s: %s get failed, err=%d\n", 9065 __func__, vreg->name, ret); 9066 } 9067 out: 9068 return ret; 9069 } 9070 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9071 9072 static int ufshcd_init_vreg(struct ufs_hba *hba) 9073 { 9074 int ret = 0; 9075 struct device *dev = hba->dev; 9076 struct ufs_vreg_info *info = &hba->vreg_info; 9077 9078 ret = ufshcd_get_vreg(dev, info->vcc); 9079 if (ret) 9080 goto out; 9081 9082 ret = ufshcd_get_vreg(dev, info->vccq); 9083 if (!ret) 9084 ret = ufshcd_get_vreg(dev, info->vccq2); 9085 out: 9086 return ret; 9087 } 9088 9089 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9090 { 9091 struct ufs_vreg_info *info = &hba->vreg_info; 9092 9093 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9094 } 9095 9096 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9097 { 9098 int ret = 0; 9099 struct ufs_clk_info *clki; 9100 struct list_head *head = &hba->clk_list_head; 9101 unsigned long flags; 9102 ktime_t start = ktime_get(); 9103 bool clk_state_changed = false; 9104 9105 if (list_empty(head)) 9106 goto out; 9107 9108 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9109 if (ret) 9110 return ret; 9111 9112 list_for_each_entry(clki, head, list) { 9113 if (!IS_ERR_OR_NULL(clki->clk)) { 9114 /* 9115 * Don't disable clocks which are needed 9116 * to keep the link active. 9117 */ 9118 if (ufshcd_is_link_active(hba) && 9119 clki->keep_link_active) 9120 continue; 9121 9122 clk_state_changed = on ^ clki->enabled; 9123 if (on && !clki->enabled) { 9124 ret = clk_prepare_enable(clki->clk); 9125 if (ret) { 9126 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9127 __func__, clki->name, ret); 9128 goto out; 9129 } 9130 } else if (!on && clki->enabled) { 9131 clk_disable_unprepare(clki->clk); 9132 } 9133 clki->enabled = on; 9134 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9135 clki->name, on ? "en" : "dis"); 9136 } 9137 } 9138 9139 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9140 if (ret) 9141 return ret; 9142 9143 if (!ufshcd_is_clkscaling_supported(hba)) 9144 ufshcd_pm_qos_update(hba, on); 9145 out: 9146 if (ret) { 9147 list_for_each_entry(clki, head, list) { 9148 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9149 clk_disable_unprepare(clki->clk); 9150 } 9151 } else if (!ret && on) { 9152 spin_lock_irqsave(hba->host->host_lock, flags); 9153 hba->clk_gating.state = CLKS_ON; 9154 trace_ufshcd_clk_gating(dev_name(hba->dev), 9155 hba->clk_gating.state); 9156 spin_unlock_irqrestore(hba->host->host_lock, flags); 9157 } 9158 9159 if (clk_state_changed) 9160 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9161 (on ? "on" : "off"), 9162 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9163 return ret; 9164 } 9165 9166 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9167 { 9168 u32 freq; 9169 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9170 9171 if (ret) { 9172 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9173 return REF_CLK_FREQ_INVAL; 9174 } 9175 9176 return ufs_get_bref_clk_from_hz(freq); 9177 } 9178 9179 static int ufshcd_init_clocks(struct ufs_hba *hba) 9180 { 9181 int ret = 0; 9182 struct ufs_clk_info *clki; 9183 struct device *dev = hba->dev; 9184 struct list_head *head = &hba->clk_list_head; 9185 9186 if (list_empty(head)) 9187 goto out; 9188 9189 list_for_each_entry(clki, head, list) { 9190 if (!clki->name) 9191 continue; 9192 9193 clki->clk = devm_clk_get(dev, clki->name); 9194 if (IS_ERR(clki->clk)) { 9195 ret = PTR_ERR(clki->clk); 9196 dev_err(dev, "%s: %s clk get failed, %d\n", 9197 __func__, clki->name, ret); 9198 goto out; 9199 } 9200 9201 /* 9202 * Parse device ref clk freq as per device tree "ref_clk". 9203 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9204 * in ufshcd_alloc_host(). 9205 */ 9206 if (!strcmp(clki->name, "ref_clk")) 9207 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9208 9209 if (clki->max_freq) { 9210 ret = clk_set_rate(clki->clk, clki->max_freq); 9211 if (ret) { 9212 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9213 __func__, clki->name, 9214 clki->max_freq, ret); 9215 goto out; 9216 } 9217 clki->curr_freq = clki->max_freq; 9218 } 9219 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9220 clki->name, clk_get_rate(clki->clk)); 9221 } 9222 9223 /* Set Max. frequency for all clocks */ 9224 if (hba->use_pm_opp) { 9225 ret = ufshcd_opp_set_rate(hba, ULONG_MAX); 9226 if (ret) { 9227 dev_err(hba->dev, "%s: failed to set OPP: %d", __func__, 9228 ret); 9229 goto out; 9230 } 9231 } 9232 9233 out: 9234 return ret; 9235 } 9236 9237 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9238 { 9239 int err = 0; 9240 9241 if (!hba->vops) 9242 goto out; 9243 9244 err = ufshcd_vops_init(hba); 9245 if (err) 9246 dev_err_probe(hba->dev, err, 9247 "%s: variant %s init failed with err %d\n", 9248 __func__, ufshcd_get_var_name(hba), err); 9249 out: 9250 return err; 9251 } 9252 9253 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9254 { 9255 if (!hba->vops) 9256 return; 9257 9258 ufshcd_vops_exit(hba); 9259 } 9260 9261 static int ufshcd_hba_init(struct ufs_hba *hba) 9262 { 9263 int err; 9264 9265 /* 9266 * Handle host controller power separately from the UFS device power 9267 * rails as it will help controlling the UFS host controller power 9268 * collapse easily which is different than UFS device power collapse. 9269 * Also, enable the host controller power before we go ahead with rest 9270 * of the initialization here. 9271 */ 9272 err = ufshcd_init_hba_vreg(hba); 9273 if (err) 9274 goto out; 9275 9276 err = ufshcd_setup_hba_vreg(hba, true); 9277 if (err) 9278 goto out; 9279 9280 err = ufshcd_init_clocks(hba); 9281 if (err) 9282 goto out_disable_hba_vreg; 9283 9284 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9285 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9286 9287 err = ufshcd_setup_clocks(hba, true); 9288 if (err) 9289 goto out_disable_hba_vreg; 9290 9291 err = ufshcd_init_vreg(hba); 9292 if (err) 9293 goto out_disable_clks; 9294 9295 err = ufshcd_setup_vreg(hba, true); 9296 if (err) 9297 goto out_disable_clks; 9298 9299 err = ufshcd_variant_hba_init(hba); 9300 if (err) 9301 goto out_disable_vreg; 9302 9303 ufs_debugfs_hba_init(hba); 9304 ufs_fault_inject_hba_init(hba); 9305 9306 hba->is_powered = true; 9307 goto out; 9308 9309 out_disable_vreg: 9310 ufshcd_setup_vreg(hba, false); 9311 out_disable_clks: 9312 ufshcd_setup_clocks(hba, false); 9313 out_disable_hba_vreg: 9314 ufshcd_setup_hba_vreg(hba, false); 9315 out: 9316 return err; 9317 } 9318 9319 static void ufshcd_hba_exit(struct ufs_hba *hba) 9320 { 9321 if (hba->is_powered) { 9322 ufshcd_pm_qos_exit(hba); 9323 ufshcd_exit_clk_scaling(hba); 9324 ufshcd_exit_clk_gating(hba); 9325 if (hba->eh_wq) 9326 destroy_workqueue(hba->eh_wq); 9327 ufs_debugfs_hba_exit(hba); 9328 ufshcd_variant_hba_exit(hba); 9329 ufshcd_setup_vreg(hba, false); 9330 ufshcd_setup_clocks(hba, false); 9331 ufshcd_setup_hba_vreg(hba, false); 9332 hba->is_powered = false; 9333 ufs_put_device_desc(hba); 9334 } 9335 } 9336 9337 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9338 enum ufs_dev_pwr_mode pwr_mode, 9339 struct scsi_sense_hdr *sshdr) 9340 { 9341 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9342 struct scsi_failure failure_defs[] = { 9343 { 9344 .allowed = 2, 9345 .result = SCMD_FAILURE_RESULT_ANY, 9346 }, 9347 }; 9348 struct scsi_failures failures = { 9349 .failure_definitions = failure_defs, 9350 }; 9351 const struct scsi_exec_args args = { 9352 .failures = &failures, 9353 .sshdr = sshdr, 9354 .req_flags = BLK_MQ_REQ_PM, 9355 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9356 }; 9357 9358 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9359 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9360 &args); 9361 } 9362 9363 /** 9364 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9365 * power mode 9366 * @hba: per adapter instance 9367 * @pwr_mode: device power mode to set 9368 * 9369 * Return: 0 if requested power mode is set successfully; 9370 * < 0 if failed to set the requested power mode. 9371 */ 9372 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9373 enum ufs_dev_pwr_mode pwr_mode) 9374 { 9375 struct scsi_sense_hdr sshdr; 9376 struct scsi_device *sdp; 9377 unsigned long flags; 9378 int ret; 9379 9380 spin_lock_irqsave(hba->host->host_lock, flags); 9381 sdp = hba->ufs_device_wlun; 9382 if (sdp && scsi_device_online(sdp)) 9383 ret = scsi_device_get(sdp); 9384 else 9385 ret = -ENODEV; 9386 spin_unlock_irqrestore(hba->host->host_lock, flags); 9387 9388 if (ret) 9389 return ret; 9390 9391 /* 9392 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9393 * handling, which would wait for host to be resumed. Since we know 9394 * we are functional while we are here, skip host resume in error 9395 * handling context. 9396 */ 9397 hba->host->eh_noresume = 1; 9398 9399 /* 9400 * Current function would be generally called from the power management 9401 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9402 * already suspended childs. 9403 */ 9404 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9405 if (ret) { 9406 sdev_printk(KERN_WARNING, sdp, 9407 "START_STOP failed for power mode: %d, result %x\n", 9408 pwr_mode, ret); 9409 if (ret > 0) { 9410 if (scsi_sense_valid(&sshdr)) 9411 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9412 ret = -EIO; 9413 } 9414 } else { 9415 hba->curr_dev_pwr_mode = pwr_mode; 9416 } 9417 9418 scsi_device_put(sdp); 9419 hba->host->eh_noresume = 0; 9420 return ret; 9421 } 9422 9423 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9424 enum uic_link_state req_link_state, 9425 bool check_for_bkops) 9426 { 9427 int ret = 0; 9428 9429 if (req_link_state == hba->uic_link_state) 9430 return 0; 9431 9432 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9433 ret = ufshcd_uic_hibern8_enter(hba); 9434 if (!ret) { 9435 ufshcd_set_link_hibern8(hba); 9436 } else { 9437 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9438 __func__, ret); 9439 goto out; 9440 } 9441 } 9442 /* 9443 * If autobkops is enabled, link can't be turned off because 9444 * turning off the link would also turn off the device, except in the 9445 * case of DeepSleep where the device is expected to remain powered. 9446 */ 9447 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9448 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9449 /* 9450 * Let's make sure that link is in low power mode, we are doing 9451 * this currently by putting the link in Hibern8. Otherway to 9452 * put the link in low power mode is to send the DME end point 9453 * to device and then send the DME reset command to local 9454 * unipro. But putting the link in hibern8 is much faster. 9455 * 9456 * Note also that putting the link in Hibern8 is a requirement 9457 * for entering DeepSleep. 9458 */ 9459 ret = ufshcd_uic_hibern8_enter(hba); 9460 if (ret) { 9461 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9462 __func__, ret); 9463 goto out; 9464 } 9465 /* 9466 * Change controller state to "reset state" which 9467 * should also put the link in off/reset state 9468 */ 9469 ufshcd_hba_stop(hba); 9470 /* 9471 * TODO: Check if we need any delay to make sure that 9472 * controller is reset 9473 */ 9474 ufshcd_set_link_off(hba); 9475 } 9476 9477 out: 9478 return ret; 9479 } 9480 9481 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9482 { 9483 bool vcc_off = false; 9484 9485 /* 9486 * It seems some UFS devices may keep drawing more than sleep current 9487 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9488 * To avoid this situation, add 2ms delay before putting these UFS 9489 * rails in LPM mode. 9490 */ 9491 if (!ufshcd_is_link_active(hba) && 9492 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9493 usleep_range(2000, 2100); 9494 9495 /* 9496 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9497 * power. 9498 * 9499 * If UFS device and link is in OFF state, all power supplies (VCC, 9500 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9501 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9502 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9503 * 9504 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9505 * in low power state which would save some power. 9506 * 9507 * If Write Booster is enabled and the device needs to flush the WB 9508 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9509 */ 9510 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9511 !hba->dev_info.is_lu_power_on_wp) { 9512 ufshcd_setup_vreg(hba, false); 9513 vcc_off = true; 9514 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9515 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9516 vcc_off = true; 9517 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9518 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9519 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9520 } 9521 } 9522 9523 /* 9524 * Some UFS devices require delay after VCC power rail is turned-off. 9525 */ 9526 if (vcc_off && hba->vreg_info.vcc && 9527 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9528 usleep_range(5000, 5100); 9529 } 9530 9531 #ifdef CONFIG_PM 9532 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9533 { 9534 int ret = 0; 9535 9536 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9537 !hba->dev_info.is_lu_power_on_wp) { 9538 ret = ufshcd_setup_vreg(hba, true); 9539 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9540 if (!ufshcd_is_link_active(hba)) { 9541 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9542 if (ret) 9543 goto vcc_disable; 9544 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9545 if (ret) 9546 goto vccq_lpm; 9547 } 9548 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9549 } 9550 goto out; 9551 9552 vccq_lpm: 9553 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9554 vcc_disable: 9555 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9556 out: 9557 return ret; 9558 } 9559 #endif /* CONFIG_PM */ 9560 9561 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9562 { 9563 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9564 ufshcd_setup_hba_vreg(hba, false); 9565 } 9566 9567 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9568 { 9569 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9570 ufshcd_setup_hba_vreg(hba, true); 9571 } 9572 9573 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9574 { 9575 int ret = 0; 9576 bool check_for_bkops; 9577 enum ufs_pm_level pm_lvl; 9578 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9579 enum uic_link_state req_link_state; 9580 9581 hba->pm_op_in_progress = true; 9582 if (pm_op != UFS_SHUTDOWN_PM) { 9583 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9584 hba->rpm_lvl : hba->spm_lvl; 9585 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9586 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9587 } else { 9588 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9589 req_link_state = UIC_LINK_OFF_STATE; 9590 } 9591 9592 /* 9593 * If we can't transition into any of the low power modes 9594 * just gate the clocks. 9595 */ 9596 ufshcd_hold(hba); 9597 hba->clk_gating.is_suspended = true; 9598 9599 if (ufshcd_is_clkscaling_supported(hba)) 9600 ufshcd_clk_scaling_suspend(hba, true); 9601 9602 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9603 req_link_state == UIC_LINK_ACTIVE_STATE) { 9604 goto vops_suspend; 9605 } 9606 9607 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9608 (req_link_state == hba->uic_link_state)) 9609 goto enable_scaling; 9610 9611 /* UFS device & link must be active before we enter in this function */ 9612 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9613 /* Wait err handler finish or trigger err recovery */ 9614 if (!ufshcd_eh_in_progress(hba)) 9615 ufshcd_force_error_recovery(hba); 9616 ret = -EBUSY; 9617 goto enable_scaling; 9618 } 9619 9620 if (pm_op == UFS_RUNTIME_PM) { 9621 if (ufshcd_can_autobkops_during_suspend(hba)) { 9622 /* 9623 * The device is idle with no requests in the queue, 9624 * allow background operations if bkops status shows 9625 * that performance might be impacted. 9626 */ 9627 ret = ufshcd_urgent_bkops(hba); 9628 if (ret) { 9629 /* 9630 * If return err in suspend flow, IO will hang. 9631 * Trigger error handler and break suspend for 9632 * error recovery. 9633 */ 9634 ufshcd_force_error_recovery(hba); 9635 ret = -EBUSY; 9636 goto enable_scaling; 9637 } 9638 } else { 9639 /* make sure that auto bkops is disabled */ 9640 ufshcd_disable_auto_bkops(hba); 9641 } 9642 /* 9643 * If device needs to do BKOP or WB buffer flush during 9644 * Hibern8, keep device power mode as "active power mode" 9645 * and VCC supply. 9646 */ 9647 hba->dev_info.b_rpm_dev_flush_capable = 9648 hba->auto_bkops_enabled || 9649 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9650 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9651 ufshcd_is_auto_hibern8_enabled(hba))) && 9652 ufshcd_wb_need_flush(hba)); 9653 } 9654 9655 flush_work(&hba->eeh_work); 9656 9657 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9658 if (ret) 9659 goto enable_scaling; 9660 9661 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9662 if (pm_op != UFS_RUNTIME_PM) 9663 /* ensure that bkops is disabled */ 9664 ufshcd_disable_auto_bkops(hba); 9665 9666 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9667 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9668 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9669 /* 9670 * If return err in suspend flow, IO will hang. 9671 * Trigger error handler and break suspend for 9672 * error recovery. 9673 */ 9674 ufshcd_force_error_recovery(hba); 9675 ret = -EBUSY; 9676 } 9677 if (ret) 9678 goto enable_scaling; 9679 } 9680 } 9681 9682 /* 9683 * In the case of DeepSleep, the device is expected to remain powered 9684 * with the link off, so do not check for bkops. 9685 */ 9686 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9687 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9688 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9689 /* 9690 * If return err in suspend flow, IO will hang. 9691 * Trigger error handler and break suspend for 9692 * error recovery. 9693 */ 9694 ufshcd_force_error_recovery(hba); 9695 ret = -EBUSY; 9696 } 9697 if (ret) 9698 goto set_dev_active; 9699 9700 vops_suspend: 9701 /* 9702 * Call vendor specific suspend callback. As these callbacks may access 9703 * vendor specific host controller register space call them before the 9704 * host clocks are ON. 9705 */ 9706 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9707 if (ret) 9708 goto set_link_active; 9709 9710 cancel_delayed_work_sync(&hba->ufs_rtc_update_work); 9711 goto out; 9712 9713 set_link_active: 9714 /* 9715 * Device hardware reset is required to exit DeepSleep. Also, for 9716 * DeepSleep, the link is off so host reset and restore will be done 9717 * further below. 9718 */ 9719 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9720 ufshcd_device_reset(hba); 9721 WARN_ON(!ufshcd_is_link_off(hba)); 9722 } 9723 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9724 ufshcd_set_link_active(hba); 9725 else if (ufshcd_is_link_off(hba)) 9726 ufshcd_host_reset_and_restore(hba); 9727 set_dev_active: 9728 /* Can also get here needing to exit DeepSleep */ 9729 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9730 ufshcd_device_reset(hba); 9731 ufshcd_host_reset_and_restore(hba); 9732 } 9733 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9734 ufshcd_disable_auto_bkops(hba); 9735 enable_scaling: 9736 if (ufshcd_is_clkscaling_supported(hba)) 9737 ufshcd_clk_scaling_suspend(hba, false); 9738 9739 hba->dev_info.b_rpm_dev_flush_capable = false; 9740 out: 9741 if (hba->dev_info.b_rpm_dev_flush_capable) { 9742 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9743 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9744 } 9745 9746 if (ret) { 9747 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9748 hba->clk_gating.is_suspended = false; 9749 ufshcd_release(hba); 9750 } 9751 hba->pm_op_in_progress = false; 9752 return ret; 9753 } 9754 9755 #ifdef CONFIG_PM 9756 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9757 { 9758 int ret; 9759 enum uic_link_state old_link_state = hba->uic_link_state; 9760 9761 hba->pm_op_in_progress = true; 9762 9763 /* 9764 * Call vendor specific resume callback. As these callbacks may access 9765 * vendor specific host controller register space call them when the 9766 * host clocks are ON. 9767 */ 9768 ret = ufshcd_vops_resume(hba, pm_op); 9769 if (ret) 9770 goto out; 9771 9772 /* For DeepSleep, the only supported option is to have the link off */ 9773 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9774 9775 if (ufshcd_is_link_hibern8(hba)) { 9776 ret = ufshcd_uic_hibern8_exit(hba); 9777 if (!ret) { 9778 ufshcd_set_link_active(hba); 9779 } else { 9780 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9781 __func__, ret); 9782 goto vendor_suspend; 9783 } 9784 } else if (ufshcd_is_link_off(hba)) { 9785 /* 9786 * A full initialization of the host and the device is 9787 * required since the link was put to off during suspend. 9788 * Note, in the case of DeepSleep, the device will exit 9789 * DeepSleep due to device reset. 9790 */ 9791 ret = ufshcd_reset_and_restore(hba); 9792 /* 9793 * ufshcd_reset_and_restore() should have already 9794 * set the link state as active 9795 */ 9796 if (ret || !ufshcd_is_link_active(hba)) 9797 goto vendor_suspend; 9798 } 9799 9800 if (!ufshcd_is_ufs_dev_active(hba)) { 9801 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9802 if (ret) 9803 goto set_old_link_state; 9804 ufshcd_set_timestamp_attr(hba); 9805 schedule_delayed_work(&hba->ufs_rtc_update_work, 9806 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 9807 } 9808 9809 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9810 ufshcd_enable_auto_bkops(hba); 9811 else 9812 /* 9813 * If BKOPs operations are urgently needed at this moment then 9814 * keep auto-bkops enabled or else disable it. 9815 */ 9816 ufshcd_urgent_bkops(hba); 9817 9818 if (hba->ee_usr_mask) 9819 ufshcd_write_ee_control(hba); 9820 9821 if (ufshcd_is_clkscaling_supported(hba)) 9822 ufshcd_clk_scaling_suspend(hba, false); 9823 9824 if (hba->dev_info.b_rpm_dev_flush_capable) { 9825 hba->dev_info.b_rpm_dev_flush_capable = false; 9826 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9827 } 9828 9829 ufshcd_configure_auto_hibern8(hba); 9830 9831 goto out; 9832 9833 set_old_link_state: 9834 ufshcd_link_state_transition(hba, old_link_state, 0); 9835 vendor_suspend: 9836 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9837 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9838 out: 9839 if (ret) 9840 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9841 hba->clk_gating.is_suspended = false; 9842 ufshcd_release(hba); 9843 hba->pm_op_in_progress = false; 9844 return ret; 9845 } 9846 9847 static int ufshcd_wl_runtime_suspend(struct device *dev) 9848 { 9849 struct scsi_device *sdev = to_scsi_device(dev); 9850 struct ufs_hba *hba; 9851 int ret; 9852 ktime_t start = ktime_get(); 9853 9854 hba = shost_priv(sdev->host); 9855 9856 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9857 if (ret) 9858 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9859 9860 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9861 ktime_to_us(ktime_sub(ktime_get(), start)), 9862 hba->curr_dev_pwr_mode, hba->uic_link_state); 9863 9864 return ret; 9865 } 9866 9867 static int ufshcd_wl_runtime_resume(struct device *dev) 9868 { 9869 struct scsi_device *sdev = to_scsi_device(dev); 9870 struct ufs_hba *hba; 9871 int ret = 0; 9872 ktime_t start = ktime_get(); 9873 9874 hba = shost_priv(sdev->host); 9875 9876 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9877 if (ret) 9878 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9879 9880 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9881 ktime_to_us(ktime_sub(ktime_get(), start)), 9882 hba->curr_dev_pwr_mode, hba->uic_link_state); 9883 9884 return ret; 9885 } 9886 #endif 9887 9888 #ifdef CONFIG_PM_SLEEP 9889 static int ufshcd_wl_suspend(struct device *dev) 9890 { 9891 struct scsi_device *sdev = to_scsi_device(dev); 9892 struct ufs_hba *hba; 9893 int ret = 0; 9894 ktime_t start = ktime_get(); 9895 9896 hba = shost_priv(sdev->host); 9897 down(&hba->host_sem); 9898 hba->system_suspending = true; 9899 9900 if (pm_runtime_suspended(dev)) 9901 goto out; 9902 9903 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9904 if (ret) { 9905 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9906 up(&hba->host_sem); 9907 } 9908 9909 out: 9910 if (!ret) 9911 hba->is_sys_suspended = true; 9912 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9913 ktime_to_us(ktime_sub(ktime_get(), start)), 9914 hba->curr_dev_pwr_mode, hba->uic_link_state); 9915 9916 return ret; 9917 } 9918 9919 static int ufshcd_wl_resume(struct device *dev) 9920 { 9921 struct scsi_device *sdev = to_scsi_device(dev); 9922 struct ufs_hba *hba; 9923 int ret = 0; 9924 ktime_t start = ktime_get(); 9925 9926 hba = shost_priv(sdev->host); 9927 9928 if (pm_runtime_suspended(dev)) 9929 goto out; 9930 9931 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9932 if (ret) 9933 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9934 out: 9935 trace_ufshcd_wl_resume(dev_name(dev), ret, 9936 ktime_to_us(ktime_sub(ktime_get(), start)), 9937 hba->curr_dev_pwr_mode, hba->uic_link_state); 9938 if (!ret) 9939 hba->is_sys_suspended = false; 9940 hba->system_suspending = false; 9941 up(&hba->host_sem); 9942 return ret; 9943 } 9944 #endif 9945 9946 /** 9947 * ufshcd_suspend - helper function for suspend operations 9948 * @hba: per adapter instance 9949 * 9950 * This function will put disable irqs, turn off clocks 9951 * and set vreg and hba-vreg in lpm mode. 9952 * 9953 * Return: 0 upon success; < 0 upon failure. 9954 */ 9955 static int ufshcd_suspend(struct ufs_hba *hba) 9956 { 9957 int ret; 9958 9959 if (!hba->is_powered) 9960 return 0; 9961 /* 9962 * Disable the host irq as host controller as there won't be any 9963 * host controller transaction expected till resume. 9964 */ 9965 ufshcd_disable_irq(hba); 9966 ret = ufshcd_setup_clocks(hba, false); 9967 if (ret) { 9968 ufshcd_enable_irq(hba); 9969 return ret; 9970 } 9971 if (ufshcd_is_clkgating_allowed(hba)) { 9972 hba->clk_gating.state = CLKS_OFF; 9973 trace_ufshcd_clk_gating(dev_name(hba->dev), 9974 hba->clk_gating.state); 9975 } 9976 9977 ufshcd_vreg_set_lpm(hba); 9978 /* Put the host controller in low power mode if possible */ 9979 ufshcd_hba_vreg_set_lpm(hba); 9980 ufshcd_pm_qos_update(hba, false); 9981 return ret; 9982 } 9983 9984 #ifdef CONFIG_PM 9985 /** 9986 * ufshcd_resume - helper function for resume operations 9987 * @hba: per adapter instance 9988 * 9989 * This function basically turns on the regulators, clocks and 9990 * irqs of the hba. 9991 * 9992 * Return: 0 for success and non-zero for failure. 9993 */ 9994 static int ufshcd_resume(struct ufs_hba *hba) 9995 { 9996 int ret; 9997 9998 if (!hba->is_powered) 9999 return 0; 10000 10001 ufshcd_hba_vreg_set_hpm(hba); 10002 ret = ufshcd_vreg_set_hpm(hba); 10003 if (ret) 10004 goto out; 10005 10006 /* Make sure clocks are enabled before accessing controller */ 10007 ret = ufshcd_setup_clocks(hba, true); 10008 if (ret) 10009 goto disable_vreg; 10010 10011 /* enable the host irq as host controller would be active soon */ 10012 ufshcd_enable_irq(hba); 10013 10014 goto out; 10015 10016 disable_vreg: 10017 ufshcd_vreg_set_lpm(hba); 10018 out: 10019 if (ret) 10020 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 10021 return ret; 10022 } 10023 #endif /* CONFIG_PM */ 10024 10025 #ifdef CONFIG_PM_SLEEP 10026 /** 10027 * ufshcd_system_suspend - system suspend callback 10028 * @dev: Device associated with the UFS controller. 10029 * 10030 * Executed before putting the system into a sleep state in which the contents 10031 * of main memory are preserved. 10032 * 10033 * Return: 0 for success and non-zero for failure. 10034 */ 10035 int ufshcd_system_suspend(struct device *dev) 10036 { 10037 struct ufs_hba *hba = dev_get_drvdata(dev); 10038 int ret = 0; 10039 ktime_t start = ktime_get(); 10040 10041 if (pm_runtime_suspended(hba->dev)) 10042 goto out; 10043 10044 ret = ufshcd_suspend(hba); 10045 out: 10046 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 10047 ktime_to_us(ktime_sub(ktime_get(), start)), 10048 hba->curr_dev_pwr_mode, hba->uic_link_state); 10049 return ret; 10050 } 10051 EXPORT_SYMBOL(ufshcd_system_suspend); 10052 10053 /** 10054 * ufshcd_system_resume - system resume callback 10055 * @dev: Device associated with the UFS controller. 10056 * 10057 * Executed after waking the system up from a sleep state in which the contents 10058 * of main memory were preserved. 10059 * 10060 * Return: 0 for success and non-zero for failure. 10061 */ 10062 int ufshcd_system_resume(struct device *dev) 10063 { 10064 struct ufs_hba *hba = dev_get_drvdata(dev); 10065 ktime_t start = ktime_get(); 10066 int ret = 0; 10067 10068 if (pm_runtime_suspended(hba->dev)) 10069 goto out; 10070 10071 ret = ufshcd_resume(hba); 10072 10073 out: 10074 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10075 ktime_to_us(ktime_sub(ktime_get(), start)), 10076 hba->curr_dev_pwr_mode, hba->uic_link_state); 10077 10078 return ret; 10079 } 10080 EXPORT_SYMBOL(ufshcd_system_resume); 10081 #endif /* CONFIG_PM_SLEEP */ 10082 10083 #ifdef CONFIG_PM 10084 /** 10085 * ufshcd_runtime_suspend - runtime suspend callback 10086 * @dev: Device associated with the UFS controller. 10087 * 10088 * Check the description of ufshcd_suspend() function for more details. 10089 * 10090 * Return: 0 for success and non-zero for failure. 10091 */ 10092 int ufshcd_runtime_suspend(struct device *dev) 10093 { 10094 struct ufs_hba *hba = dev_get_drvdata(dev); 10095 int ret; 10096 ktime_t start = ktime_get(); 10097 10098 ret = ufshcd_suspend(hba); 10099 10100 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10101 ktime_to_us(ktime_sub(ktime_get(), start)), 10102 hba->curr_dev_pwr_mode, hba->uic_link_state); 10103 return ret; 10104 } 10105 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10106 10107 /** 10108 * ufshcd_runtime_resume - runtime resume routine 10109 * @dev: Device associated with the UFS controller. 10110 * 10111 * This function basically brings controller 10112 * to active state. Following operations are done in this function: 10113 * 10114 * 1. Turn on all the controller related clocks 10115 * 2. Turn ON VCC rail 10116 * 10117 * Return: 0 upon success; < 0 upon failure. 10118 */ 10119 int ufshcd_runtime_resume(struct device *dev) 10120 { 10121 struct ufs_hba *hba = dev_get_drvdata(dev); 10122 int ret; 10123 ktime_t start = ktime_get(); 10124 10125 ret = ufshcd_resume(hba); 10126 10127 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10128 ktime_to_us(ktime_sub(ktime_get(), start)), 10129 hba->curr_dev_pwr_mode, hba->uic_link_state); 10130 return ret; 10131 } 10132 EXPORT_SYMBOL(ufshcd_runtime_resume); 10133 #endif /* CONFIG_PM */ 10134 10135 static void ufshcd_wl_shutdown(struct device *dev) 10136 { 10137 struct scsi_device *sdev = to_scsi_device(dev); 10138 struct ufs_hba *hba = shost_priv(sdev->host); 10139 10140 down(&hba->host_sem); 10141 hba->shutting_down = true; 10142 up(&hba->host_sem); 10143 10144 /* Turn on everything while shutting down */ 10145 ufshcd_rpm_get_sync(hba); 10146 scsi_device_quiesce(sdev); 10147 shost_for_each_device(sdev, hba->host) { 10148 if (sdev == hba->ufs_device_wlun) 10149 continue; 10150 scsi_device_quiesce(sdev); 10151 } 10152 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10153 10154 /* 10155 * Next, turn off the UFS controller and the UFS regulators. Disable 10156 * clocks. 10157 */ 10158 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10159 ufshcd_suspend(hba); 10160 10161 hba->is_powered = false; 10162 } 10163 10164 /** 10165 * ufshcd_remove - de-allocate SCSI host and host memory space 10166 * data structure memory 10167 * @hba: per adapter instance 10168 */ 10169 void ufshcd_remove(struct ufs_hba *hba) 10170 { 10171 if (hba->ufs_device_wlun) 10172 ufshcd_rpm_get_sync(hba); 10173 ufs_hwmon_remove(hba); 10174 ufs_bsg_remove(hba); 10175 ufs_sysfs_remove_nodes(hba->dev); 10176 blk_mq_destroy_queue(hba->tmf_queue); 10177 blk_put_queue(hba->tmf_queue); 10178 blk_mq_free_tag_set(&hba->tmf_tag_set); 10179 scsi_remove_host(hba->host); 10180 /* disable interrupts */ 10181 ufshcd_disable_intr(hba, hba->intr_mask); 10182 ufshcd_hba_stop(hba); 10183 ufshcd_hba_exit(hba); 10184 } 10185 EXPORT_SYMBOL_GPL(ufshcd_remove); 10186 10187 #ifdef CONFIG_PM_SLEEP 10188 int ufshcd_system_freeze(struct device *dev) 10189 { 10190 10191 return ufshcd_system_suspend(dev); 10192 10193 } 10194 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10195 10196 int ufshcd_system_restore(struct device *dev) 10197 { 10198 10199 struct ufs_hba *hba = dev_get_drvdata(dev); 10200 int ret; 10201 10202 ret = ufshcd_system_resume(dev); 10203 if (ret) 10204 return ret; 10205 10206 /* Configure UTRL and UTMRL base address registers */ 10207 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10208 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10209 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10210 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10211 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10212 REG_UTP_TASK_REQ_LIST_BASE_L); 10213 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10214 REG_UTP_TASK_REQ_LIST_BASE_H); 10215 /* 10216 * Make sure that UTRL and UTMRL base address registers 10217 * are updated with the latest queue addresses. Only after 10218 * updating these addresses, we can queue the new commands. 10219 */ 10220 ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H); 10221 10222 /* Resuming from hibernate, assume that link was OFF */ 10223 ufshcd_set_link_off(hba); 10224 10225 return 0; 10226 10227 } 10228 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10229 10230 int ufshcd_system_thaw(struct device *dev) 10231 { 10232 return ufshcd_system_resume(dev); 10233 } 10234 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10235 #endif /* CONFIG_PM_SLEEP */ 10236 10237 /** 10238 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10239 * @hba: pointer to Host Bus Adapter (HBA) 10240 */ 10241 void ufshcd_dealloc_host(struct ufs_hba *hba) 10242 { 10243 scsi_host_put(hba->host); 10244 } 10245 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10246 10247 /** 10248 * ufshcd_set_dma_mask - Set dma mask based on the controller 10249 * addressing capability 10250 * @hba: per adapter instance 10251 * 10252 * Return: 0 for success, non-zero for failure. 10253 */ 10254 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10255 { 10256 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10257 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10258 return 0; 10259 } 10260 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10261 } 10262 10263 /** 10264 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10265 * @dev: pointer to device handle 10266 * @hba_handle: driver private handle 10267 * 10268 * Return: 0 on success, non-zero value on failure. 10269 */ 10270 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10271 { 10272 struct Scsi_Host *host; 10273 struct ufs_hba *hba; 10274 int err = 0; 10275 10276 if (!dev) { 10277 dev_err(dev, 10278 "Invalid memory reference for dev is NULL\n"); 10279 err = -ENODEV; 10280 goto out_error; 10281 } 10282 10283 host = scsi_host_alloc(&ufshcd_driver_template, 10284 sizeof(struct ufs_hba)); 10285 if (!host) { 10286 dev_err(dev, "scsi_host_alloc failed\n"); 10287 err = -ENOMEM; 10288 goto out_error; 10289 } 10290 host->nr_maps = HCTX_TYPE_POLL + 1; 10291 hba = shost_priv(host); 10292 hba->host = host; 10293 hba->dev = dev; 10294 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10295 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10296 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10297 INIT_LIST_HEAD(&hba->clk_list_head); 10298 spin_lock_init(&hba->outstanding_lock); 10299 10300 *hba_handle = hba; 10301 10302 out_error: 10303 return err; 10304 } 10305 EXPORT_SYMBOL(ufshcd_alloc_host); 10306 10307 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10308 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10309 const struct blk_mq_queue_data *qd) 10310 { 10311 WARN_ON_ONCE(true); 10312 return BLK_STS_NOTSUPP; 10313 } 10314 10315 static const struct blk_mq_ops ufshcd_tmf_ops = { 10316 .queue_rq = ufshcd_queue_tmf, 10317 }; 10318 10319 /** 10320 * ufshcd_init - Driver initialization routine 10321 * @hba: per-adapter instance 10322 * @mmio_base: base register address 10323 * @irq: Interrupt line of device 10324 * 10325 * Return: 0 on success, non-zero value on failure. 10326 */ 10327 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10328 { 10329 int err; 10330 struct Scsi_Host *host = hba->host; 10331 struct device *dev = hba->dev; 10332 char eh_wq_name[sizeof("ufs_eh_wq_00")]; 10333 10334 /* 10335 * dev_set_drvdata() must be called before any callbacks are registered 10336 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10337 * sysfs). 10338 */ 10339 dev_set_drvdata(dev, hba); 10340 10341 if (!mmio_base) { 10342 dev_err(hba->dev, 10343 "Invalid memory reference for mmio_base is NULL\n"); 10344 err = -ENODEV; 10345 goto out_error; 10346 } 10347 10348 hba->mmio_base = mmio_base; 10349 hba->irq = irq; 10350 hba->vps = &ufs_hba_vps; 10351 10352 err = ufshcd_hba_init(hba); 10353 if (err) 10354 goto out_error; 10355 10356 /* Read capabilities registers */ 10357 err = ufshcd_hba_capabilities(hba); 10358 if (err) 10359 goto out_disable; 10360 10361 /* Get UFS version supported by the controller */ 10362 hba->ufs_version = ufshcd_get_ufs_version(hba); 10363 10364 /* Get Interrupt bit mask per version */ 10365 hba->intr_mask = ufshcd_get_intr_mask(hba); 10366 10367 err = ufshcd_set_dma_mask(hba); 10368 if (err) { 10369 dev_err(hba->dev, "set dma mask failed\n"); 10370 goto out_disable; 10371 } 10372 10373 /* Allocate memory for host memory space */ 10374 err = ufshcd_memory_alloc(hba); 10375 if (err) { 10376 dev_err(hba->dev, "Memory allocation failed\n"); 10377 goto out_disable; 10378 } 10379 10380 /* Configure LRB */ 10381 ufshcd_host_memory_configure(hba); 10382 10383 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10384 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10385 host->max_id = UFSHCD_MAX_ID; 10386 host->max_lun = UFS_MAX_LUNS; 10387 host->max_channel = UFSHCD_MAX_CHANNEL; 10388 host->unique_id = host->host_no; 10389 host->max_cmd_len = UFS_CDB_SIZE; 10390 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10391 10392 /* Use default RPM delay if host not set */ 10393 if (host->rpm_autosuspend_delay == 0) 10394 host->rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS; 10395 10396 hba->max_pwr_info.is_valid = false; 10397 10398 /* Initialize work queues */ 10399 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d", 10400 hba->host->host_no); 10401 hba->eh_wq = create_singlethread_workqueue(eh_wq_name); 10402 if (!hba->eh_wq) { 10403 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10404 __func__); 10405 err = -ENOMEM; 10406 goto out_disable; 10407 } 10408 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10409 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10410 10411 sema_init(&hba->host_sem, 1); 10412 10413 /* Initialize UIC command mutex */ 10414 mutex_init(&hba->uic_cmd_mutex); 10415 10416 /* Initialize mutex for device management commands */ 10417 mutex_init(&hba->dev_cmd.lock); 10418 10419 /* Initialize mutex for exception event control */ 10420 mutex_init(&hba->ee_ctrl_mutex); 10421 10422 mutex_init(&hba->wb_mutex); 10423 init_rwsem(&hba->clk_scaling_lock); 10424 10425 ufshcd_init_clk_gating(hba); 10426 10427 ufshcd_init_clk_scaling(hba); 10428 10429 /* 10430 * In order to avoid any spurious interrupt immediately after 10431 * registering UFS controller interrupt handler, clear any pending UFS 10432 * interrupt status and disable all the UFS interrupts. 10433 */ 10434 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10435 REG_INTERRUPT_STATUS); 10436 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10437 /* 10438 * Make sure that UFS interrupts are disabled and any pending interrupt 10439 * status is cleared before registering UFS interrupt handler. 10440 */ 10441 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 10442 10443 /* IRQ registration */ 10444 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10445 if (err) { 10446 dev_err(hba->dev, "request irq failed\n"); 10447 goto out_disable; 10448 } else { 10449 hba->is_irq_enabled = true; 10450 } 10451 10452 if (!is_mcq_supported(hba)) { 10453 err = scsi_add_host(host, hba->dev); 10454 if (err) { 10455 dev_err(hba->dev, "scsi_add_host failed\n"); 10456 goto out_disable; 10457 } 10458 } 10459 10460 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10461 .nr_hw_queues = 1, 10462 .queue_depth = hba->nutmrs, 10463 .ops = &ufshcd_tmf_ops, 10464 .flags = BLK_MQ_F_NO_SCHED, 10465 }; 10466 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10467 if (err < 0) 10468 goto out_remove_scsi_host; 10469 hba->tmf_queue = blk_mq_alloc_queue(&hba->tmf_tag_set, NULL, NULL); 10470 if (IS_ERR(hba->tmf_queue)) { 10471 err = PTR_ERR(hba->tmf_queue); 10472 goto free_tmf_tag_set; 10473 } 10474 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10475 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10476 if (!hba->tmf_rqs) { 10477 err = -ENOMEM; 10478 goto free_tmf_queue; 10479 } 10480 10481 /* Reset the attached device */ 10482 ufshcd_device_reset(hba); 10483 10484 ufshcd_init_crypto(hba); 10485 10486 /* Host controller enable */ 10487 err = ufshcd_hba_enable(hba); 10488 if (err) { 10489 dev_err(hba->dev, "Host controller enable failed\n"); 10490 ufshcd_print_evt_hist(hba); 10491 ufshcd_print_host_state(hba); 10492 goto free_tmf_queue; 10493 } 10494 10495 /* 10496 * Set the default power management level for runtime and system PM. 10497 * Default power saving mode is to keep UFS link in Hibern8 state 10498 * and UFS device in sleep state. 10499 */ 10500 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10501 UFS_SLEEP_PWR_MODE, 10502 UIC_LINK_HIBERN8_STATE); 10503 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10504 UFS_SLEEP_PWR_MODE, 10505 UIC_LINK_HIBERN8_STATE); 10506 10507 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, ufshcd_rpm_dev_flush_recheck_work); 10508 INIT_DELAYED_WORK(&hba->ufs_rtc_update_work, ufshcd_rtc_work); 10509 10510 /* Set the default auto-hiberate idle timer value to 150 ms */ 10511 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10512 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10513 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10514 } 10515 10516 /* Hold auto suspend until async scan completes */ 10517 pm_runtime_get_sync(dev); 10518 atomic_set(&hba->scsi_block_reqs_cnt, 0); 10519 /* 10520 * We are assuming that device wasn't put in sleep/power-down 10521 * state exclusively during the boot stage before kernel. 10522 * This assumption helps avoid doing link startup twice during 10523 * ufshcd_probe_hba(). 10524 */ 10525 ufshcd_set_ufs_dev_active(hba); 10526 10527 async_schedule(ufshcd_async_scan, hba); 10528 ufs_sysfs_add_nodes(hba->dev); 10529 10530 device_enable_async_suspend(dev); 10531 ufshcd_pm_qos_init(hba); 10532 return 0; 10533 10534 free_tmf_queue: 10535 blk_mq_destroy_queue(hba->tmf_queue); 10536 blk_put_queue(hba->tmf_queue); 10537 free_tmf_tag_set: 10538 blk_mq_free_tag_set(&hba->tmf_tag_set); 10539 out_remove_scsi_host: 10540 scsi_remove_host(hba->host); 10541 out_disable: 10542 hba->is_irq_enabled = false; 10543 ufshcd_hba_exit(hba); 10544 out_error: 10545 return err; 10546 } 10547 EXPORT_SYMBOL_GPL(ufshcd_init); 10548 10549 void ufshcd_resume_complete(struct device *dev) 10550 { 10551 struct ufs_hba *hba = dev_get_drvdata(dev); 10552 10553 if (hba->complete_put) { 10554 ufshcd_rpm_put(hba); 10555 hba->complete_put = false; 10556 } 10557 } 10558 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10559 10560 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10561 { 10562 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10563 enum ufs_dev_pwr_mode dev_pwr_mode; 10564 enum uic_link_state link_state; 10565 unsigned long flags; 10566 bool res; 10567 10568 spin_lock_irqsave(&dev->power.lock, flags); 10569 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10570 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10571 res = pm_runtime_suspended(dev) && 10572 hba->curr_dev_pwr_mode == dev_pwr_mode && 10573 hba->uic_link_state == link_state && 10574 !hba->dev_info.b_rpm_dev_flush_capable; 10575 spin_unlock_irqrestore(&dev->power.lock, flags); 10576 10577 return res; 10578 } 10579 10580 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10581 { 10582 struct ufs_hba *hba = dev_get_drvdata(dev); 10583 int ret; 10584 10585 /* 10586 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10587 * are same. And it doesn't wake up the device for system-suspend 10588 * if it's runtime suspended. But ufs doesn't follow that. 10589 * Refer ufshcd_resume_complete() 10590 */ 10591 if (hba->ufs_device_wlun) { 10592 /* Prevent runtime suspend */ 10593 ufshcd_rpm_get_noresume(hba); 10594 /* 10595 * Check if already runtime suspended in same state as system 10596 * suspend would be. 10597 */ 10598 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10599 /* RPM state is not ok for SPM, so runtime resume */ 10600 ret = ufshcd_rpm_resume(hba); 10601 if (ret < 0 && ret != -EACCES) { 10602 ufshcd_rpm_put(hba); 10603 return ret; 10604 } 10605 } 10606 hba->complete_put = true; 10607 } 10608 return 0; 10609 } 10610 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10611 10612 int ufshcd_suspend_prepare(struct device *dev) 10613 { 10614 return __ufshcd_suspend_prepare(dev, true); 10615 } 10616 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10617 10618 #ifdef CONFIG_PM_SLEEP 10619 static int ufshcd_wl_poweroff(struct device *dev) 10620 { 10621 struct scsi_device *sdev = to_scsi_device(dev); 10622 struct ufs_hba *hba = shost_priv(sdev->host); 10623 10624 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10625 return 0; 10626 } 10627 #endif 10628 10629 static int ufshcd_wl_probe(struct device *dev) 10630 { 10631 struct scsi_device *sdev = to_scsi_device(dev); 10632 10633 if (!is_device_wlun(sdev)) 10634 return -ENODEV; 10635 10636 blk_pm_runtime_init(sdev->request_queue, dev); 10637 pm_runtime_set_autosuspend_delay(dev, 0); 10638 pm_runtime_allow(dev); 10639 10640 return 0; 10641 } 10642 10643 static int ufshcd_wl_remove(struct device *dev) 10644 { 10645 pm_runtime_forbid(dev); 10646 return 0; 10647 } 10648 10649 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10650 #ifdef CONFIG_PM_SLEEP 10651 .suspend = ufshcd_wl_suspend, 10652 .resume = ufshcd_wl_resume, 10653 .freeze = ufshcd_wl_suspend, 10654 .thaw = ufshcd_wl_resume, 10655 .poweroff = ufshcd_wl_poweroff, 10656 .restore = ufshcd_wl_resume, 10657 #endif 10658 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10659 }; 10660 10661 static void ufshcd_check_header_layout(void) 10662 { 10663 /* 10664 * gcc compilers before version 10 cannot do constant-folding for 10665 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10666 * before. 10667 */ 10668 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10669 return; 10670 10671 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10672 .cci = 3})[0] != 3); 10673 10674 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10675 .ehs_length = 2})[1] != 2); 10676 10677 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10678 .enable_crypto = 1})[2] 10679 != 0x80); 10680 10681 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10682 .command_type = 5, 10683 .data_direction = 3, 10684 .interrupt = 1, 10685 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10686 10687 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10688 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10689 cpu_to_le32(0xdeadbeef)); 10690 10691 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10692 .ocs = 4})[8] != 4); 10693 10694 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10695 .cds = 5})[9] != 5); 10696 10697 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10698 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10699 cpu_to_le32(0xbadcafe)); 10700 10701 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10702 .iid = 0xf })[4] != 0xf0); 10703 10704 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10705 .command_set_type = 0xf })[4] != 0xf); 10706 } 10707 10708 /* 10709 * ufs_dev_wlun_template - describes ufs device wlun 10710 * ufs-device wlun - used to send pm commands 10711 * All luns are consumers of ufs-device wlun. 10712 * 10713 * Currently, no sd driver is present for wluns. 10714 * Hence the no specific pm operations are performed. 10715 * With ufs design, SSU should be sent to ufs-device wlun. 10716 * Hence register a scsi driver for ufs wluns only. 10717 */ 10718 static struct scsi_driver ufs_dev_wlun_template = { 10719 .gendrv = { 10720 .name = "ufs_device_wlun", 10721 .probe = ufshcd_wl_probe, 10722 .remove = ufshcd_wl_remove, 10723 .pm = &ufshcd_wl_pm_ops, 10724 .shutdown = ufshcd_wl_shutdown, 10725 }, 10726 }; 10727 10728 static int __init ufshcd_core_init(void) 10729 { 10730 int ret; 10731 10732 ufshcd_check_header_layout(); 10733 10734 ufs_debugfs_init(); 10735 10736 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10737 if (ret) 10738 ufs_debugfs_exit(); 10739 return ret; 10740 } 10741 10742 static void __exit ufshcd_core_exit(void) 10743 { 10744 ufs_debugfs_exit(); 10745 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10746 } 10747 10748 module_init(ufshcd_core_init); 10749 module_exit(ufshcd_core_exit); 10750 10751 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10752 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10753 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10754 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10755 MODULE_LICENSE("GPL"); 10756