1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/pm_opp.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/sched/clock.h> 26 #include <linux/iopoll.h> 27 #include <scsi/scsi_cmnd.h> 28 #include <scsi/scsi_dbg.h> 29 #include <scsi/scsi_driver.h> 30 #include <scsi/scsi_eh.h> 31 #include "ufshcd-priv.h" 32 #include <ufs/ufs_quirks.h> 33 #include <ufs/unipro.h> 34 #include "ufs-sysfs.h" 35 #include "ufs-debugfs.h" 36 #include "ufs-fault-injection.h" 37 #include "ufs_bsg.h" 38 #include "ufshcd-crypto.h" 39 #include <linux/unaligned.h> 40 41 #define CREATE_TRACE_POINTS 42 #include "ufs_trace.h" 43 44 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 45 UTP_TASK_REQ_COMPL |\ 46 UFSHCD_ERROR_MASK) 47 48 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 49 UFSHCD_ERROR_MASK |\ 50 MCQ_CQ_EVENT_STATUS) 51 52 53 /* UIC command timeout, unit: ms */ 54 enum { 55 UIC_CMD_TIMEOUT_DEFAULT = 500, 56 UIC_CMD_TIMEOUT_MAX = 2000, 57 }; 58 /* NOP OUT retries waiting for NOP IN response */ 59 #define NOP_OUT_RETRIES 10 60 /* Timeout after 50 msecs if NOP OUT hangs without response */ 61 #define NOP_OUT_TIMEOUT 50 /* msecs */ 62 63 /* Query request retries */ 64 #define QUERY_REQ_RETRIES 3 65 /* Query request timeout */ 66 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 67 68 /* Advanced RPMB request timeout */ 69 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 70 71 /* Task management command timeout */ 72 #define TM_CMD_TIMEOUT 100 /* msecs */ 73 74 /* maximum number of retries for a general UIC command */ 75 #define UFS_UIC_COMMAND_RETRIES 3 76 77 /* maximum number of link-startup retries */ 78 #define DME_LINKSTARTUP_RETRIES 3 79 80 /* maximum number of reset retries before giving up */ 81 #define MAX_HOST_RESET_RETRIES 5 82 83 /* Maximum number of error handler retries before giving up */ 84 #define MAX_ERR_HANDLER_RETRIES 5 85 86 /* Expose the flag value from utp_upiu_query.value */ 87 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 88 89 /* Interrupt aggregation default timeout, unit: 40us */ 90 #define INT_AGGR_DEF_TO 0x02 91 92 /* default delay of autosuspend: 2000 ms */ 93 #define RPM_AUTOSUSPEND_DELAY_MS 2000 94 95 /* Default delay of RPM device flush delayed work */ 96 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 97 98 /* Default value of wait time before gating device ref clock */ 99 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 100 101 /* Polling time to wait for fDeviceInit */ 102 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 103 104 /* Default RTC update every 10 seconds */ 105 #define UFS_RTC_UPDATE_INTERVAL_MS (10 * MSEC_PER_SEC) 106 107 /* bMaxNumOfRTT is equal to two after device manufacturing */ 108 #define DEFAULT_MAX_NUM_RTT 2 109 110 /* UFSHC 4.0 compliant HC support this mode. */ 111 static bool use_mcq_mode = true; 112 113 static bool is_mcq_supported(struct ufs_hba *hba) 114 { 115 return hba->mcq_sup && use_mcq_mode; 116 } 117 118 module_param(use_mcq_mode, bool, 0644); 119 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 120 121 static unsigned int uic_cmd_timeout = UIC_CMD_TIMEOUT_DEFAULT; 122 123 static int uic_cmd_timeout_set(const char *val, const struct kernel_param *kp) 124 { 125 return param_set_uint_minmax(val, kp, UIC_CMD_TIMEOUT_DEFAULT, 126 UIC_CMD_TIMEOUT_MAX); 127 } 128 129 static const struct kernel_param_ops uic_cmd_timeout_ops = { 130 .set = uic_cmd_timeout_set, 131 .get = param_get_uint, 132 }; 133 134 module_param_cb(uic_cmd_timeout, &uic_cmd_timeout_ops, &uic_cmd_timeout, 0644); 135 MODULE_PARM_DESC(uic_cmd_timeout, 136 "UFS UIC command timeout in milliseconds. Defaults to 500ms. Supported values range from 500ms to 2 seconds inclusively"); 137 138 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 139 ({ \ 140 int _ret; \ 141 if (_on) \ 142 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 143 else \ 144 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 145 _ret; \ 146 }) 147 148 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 149 size_t __len = (len); \ 150 print_hex_dump(KERN_ERR, prefix_str, \ 151 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 152 16, 4, buf, __len, false); \ 153 } while (0) 154 155 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 156 const char *prefix) 157 { 158 u32 *regs; 159 size_t pos; 160 161 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 162 return -EINVAL; 163 164 regs = kzalloc(len, GFP_ATOMIC); 165 if (!regs) 166 return -ENOMEM; 167 168 for (pos = 0; pos < len; pos += 4) { 169 if (offset == 0 && 170 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 171 pos <= REG_UIC_ERROR_CODE_DME) 172 continue; 173 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 174 } 175 176 ufshcd_hex_dump(prefix, regs, len); 177 kfree(regs); 178 179 return 0; 180 } 181 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 182 183 enum { 184 UFSHCD_MAX_CHANNEL = 0, 185 UFSHCD_MAX_ID = 1, 186 }; 187 188 static const char *const ufshcd_state_name[] = { 189 [UFSHCD_STATE_RESET] = "reset", 190 [UFSHCD_STATE_OPERATIONAL] = "operational", 191 [UFSHCD_STATE_ERROR] = "error", 192 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 193 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 194 }; 195 196 /* UFSHCD error handling flags */ 197 enum { 198 UFSHCD_EH_IN_PROGRESS = (1 << 0), 199 }; 200 201 /* UFSHCD UIC layer error flags */ 202 enum { 203 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 204 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 205 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 206 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 207 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 208 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 209 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 210 }; 211 212 #define ufshcd_set_eh_in_progress(h) \ 213 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 214 #define ufshcd_eh_in_progress(h) \ 215 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 216 #define ufshcd_clear_eh_in_progress(h) \ 217 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 218 219 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 220 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 221 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 222 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 223 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 224 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 225 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 226 /* 227 * For DeepSleep, the link is first put in hibern8 and then off. 228 * Leaving the link in hibern8 is not supported. 229 */ 230 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 231 }; 232 233 static inline enum ufs_dev_pwr_mode 234 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 235 { 236 return ufs_pm_lvl_states[lvl].dev_state; 237 } 238 239 static inline enum uic_link_state 240 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 241 { 242 return ufs_pm_lvl_states[lvl].link_state; 243 } 244 245 static inline enum ufs_pm_level 246 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 247 enum uic_link_state link_state) 248 { 249 enum ufs_pm_level lvl; 250 251 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 252 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 253 (ufs_pm_lvl_states[lvl].link_state == link_state)) 254 return lvl; 255 } 256 257 /* if no match found, return the level 0 */ 258 return UFS_PM_LVL_0; 259 } 260 261 static bool ufshcd_is_ufs_dev_busy(struct ufs_hba *hba) 262 { 263 return (hba->clk_gating.active_reqs || hba->outstanding_reqs || hba->outstanding_tasks || 264 hba->active_uic_cmd || hba->uic_async_done); 265 } 266 267 static const struct ufs_dev_quirk ufs_fixups[] = { 268 /* UFS cards deviations table */ 269 { .wmanufacturerid = UFS_VENDOR_MICRON, 270 .model = UFS_ANY_MODEL, 271 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 272 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 273 .model = UFS_ANY_MODEL, 274 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 275 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 276 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 277 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 278 .model = UFS_ANY_MODEL, 279 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 280 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 281 .model = "hB8aL1" /*H28U62301AMR*/, 282 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 283 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 284 .model = UFS_ANY_MODEL, 285 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 286 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 287 .model = "THGLF2G9C8KBADG", 288 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 289 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 290 .model = "THGLF2G9D8KBADG", 291 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 292 {} 293 }; 294 295 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 296 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 297 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 298 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 299 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 300 static void ufshcd_hba_exit(struct ufs_hba *hba); 301 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 302 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 303 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 304 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 305 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 306 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 307 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 308 bool scale_up); 309 static irqreturn_t ufshcd_intr(int irq, void *__hba); 310 static int ufshcd_change_power_mode(struct ufs_hba *hba, 311 struct ufs_pa_layer_attr *pwr_mode); 312 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 313 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 314 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 315 struct ufs_vreg *vreg); 316 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 317 bool enable); 318 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 319 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 320 321 void ufshcd_enable_irq(struct ufs_hba *hba) 322 { 323 if (!hba->is_irq_enabled) { 324 enable_irq(hba->irq); 325 hba->is_irq_enabled = true; 326 } 327 } 328 EXPORT_SYMBOL_GPL(ufshcd_enable_irq); 329 330 void ufshcd_disable_irq(struct ufs_hba *hba) 331 { 332 if (hba->is_irq_enabled) { 333 disable_irq(hba->irq); 334 hba->is_irq_enabled = false; 335 } 336 } 337 EXPORT_SYMBOL_GPL(ufshcd_disable_irq); 338 339 static void ufshcd_configure_wb(struct ufs_hba *hba) 340 { 341 if (!ufshcd_is_wb_allowed(hba)) 342 return; 343 344 ufshcd_wb_toggle(hba, true); 345 346 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 347 348 if (ufshcd_is_wb_buf_flush_allowed(hba)) 349 ufshcd_wb_toggle_buf_flush(hba, true); 350 } 351 352 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba) 353 { 354 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt)) 355 scsi_unblock_requests(hba->host); 356 } 357 358 static void ufshcd_scsi_block_requests(struct ufs_hba *hba) 359 { 360 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1) 361 scsi_block_requests(hba->host); 362 } 363 364 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 365 enum ufs_trace_str_t str_t) 366 { 367 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 368 struct utp_upiu_header *header; 369 370 if (!trace_ufshcd_upiu_enabled()) 371 return; 372 373 if (str_t == UFS_CMD_SEND) 374 header = &rq->header; 375 else 376 header = &hba->lrb[tag].ucd_rsp_ptr->header; 377 378 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 379 UFS_TSF_CDB); 380 } 381 382 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 383 enum ufs_trace_str_t str_t, 384 struct utp_upiu_req *rq_rsp) 385 { 386 if (!trace_ufshcd_upiu_enabled()) 387 return; 388 389 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 390 &rq_rsp->qr, UFS_TSF_OSF); 391 } 392 393 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 394 enum ufs_trace_str_t str_t) 395 { 396 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 397 398 if (!trace_ufshcd_upiu_enabled()) 399 return; 400 401 if (str_t == UFS_TM_SEND) 402 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 403 &descp->upiu_req.req_header, 404 &descp->upiu_req.input_param1, 405 UFS_TSF_TM_INPUT); 406 else 407 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 408 &descp->upiu_rsp.rsp_header, 409 &descp->upiu_rsp.output_param1, 410 UFS_TSF_TM_OUTPUT); 411 } 412 413 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 414 const struct uic_command *ucmd, 415 enum ufs_trace_str_t str_t) 416 { 417 u32 cmd; 418 419 if (!trace_ufshcd_uic_command_enabled()) 420 return; 421 422 if (str_t == UFS_CMD_SEND) 423 cmd = ucmd->command; 424 else 425 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 426 427 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 428 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 429 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 430 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 431 } 432 433 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 434 enum ufs_trace_str_t str_t) 435 { 436 u64 lba = 0; 437 u8 opcode = 0, group_id = 0; 438 u32 doorbell = 0; 439 u32 intr; 440 int hwq_id = -1; 441 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 442 struct scsi_cmnd *cmd = lrbp->cmd; 443 struct request *rq = scsi_cmd_to_rq(cmd); 444 int transfer_len = -1; 445 446 if (!cmd) 447 return; 448 449 /* trace UPIU also */ 450 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 451 if (!trace_ufshcd_command_enabled()) 452 return; 453 454 opcode = cmd->cmnd[0]; 455 456 if (opcode == READ_10 || opcode == WRITE_10) { 457 /* 458 * Currently we only fully trace read(10) and write(10) commands 459 */ 460 transfer_len = 461 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 462 lba = scsi_get_lba(cmd); 463 if (opcode == WRITE_10) 464 group_id = lrbp->cmd->cmnd[6]; 465 } else if (opcode == UNMAP) { 466 /* 467 * The number of Bytes to be unmapped beginning with the lba. 468 */ 469 transfer_len = blk_rq_bytes(rq); 470 lba = scsi_get_lba(cmd); 471 } 472 473 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 474 475 if (hba->mcq_enabled) { 476 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 477 478 hwq_id = hwq->id; 479 } else { 480 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 481 } 482 trace_ufshcd_command(cmd->device, str_t, tag, doorbell, hwq_id, 483 transfer_len, intr, lba, opcode, group_id); 484 } 485 486 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 487 { 488 struct ufs_clk_info *clki; 489 struct list_head *head = &hba->clk_list_head; 490 491 if (list_empty(head)) 492 return; 493 494 list_for_each_entry(clki, head, list) { 495 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 496 clki->max_freq) 497 dev_err(hba->dev, "clk: %s, rate: %u\n", 498 clki->name, clki->curr_freq); 499 } 500 } 501 502 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 503 const char *err_name) 504 { 505 int i; 506 bool found = false; 507 const struct ufs_event_hist *e; 508 509 if (id >= UFS_EVT_CNT) 510 return; 511 512 e = &hba->ufs_stats.event[id]; 513 514 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 515 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 516 517 if (e->tstamp[p] == 0) 518 continue; 519 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 520 e->val[p], div_u64(e->tstamp[p], 1000)); 521 found = true; 522 } 523 524 if (!found) 525 dev_err(hba->dev, "No record of %s\n", err_name); 526 else 527 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 528 } 529 530 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 531 { 532 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 533 534 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 535 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 536 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 537 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 538 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 539 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 540 "auto_hibern8_err"); 541 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 542 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 543 "link_startup_fail"); 544 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 545 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 546 "suspend_fail"); 547 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 548 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 549 "wlun suspend_fail"); 550 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 551 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 552 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 553 554 ufshcd_vops_dbg_register_dump(hba); 555 } 556 557 static 558 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 559 { 560 const struct ufshcd_lrb *lrbp; 561 int prdt_length; 562 563 lrbp = &hba->lrb[tag]; 564 565 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 566 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 567 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 568 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 569 dev_err(hba->dev, 570 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 571 tag, (u64)lrbp->utrd_dma_addr); 572 573 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 574 sizeof(struct utp_transfer_req_desc)); 575 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 576 (u64)lrbp->ucd_req_dma_addr); 577 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 578 sizeof(struct utp_upiu_req)); 579 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 580 (u64)lrbp->ucd_rsp_dma_addr); 581 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 582 sizeof(struct utp_upiu_rsp)); 583 584 prdt_length = le16_to_cpu( 585 lrbp->utr_descriptor_ptr->prd_table_length); 586 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 587 prdt_length /= ufshcd_sg_entry_size(hba); 588 589 dev_err(hba->dev, 590 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 591 tag, prdt_length, 592 (u64)lrbp->ucd_prdt_dma_addr); 593 594 if (pr_prdt) 595 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 596 ufshcd_sg_entry_size(hba) * prdt_length); 597 } 598 599 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 600 { 601 struct scsi_device *sdev = req->q->queuedata; 602 struct Scsi_Host *shost = sdev->host; 603 struct ufs_hba *hba = shost_priv(shost); 604 605 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 606 607 return true; 608 } 609 610 /** 611 * ufshcd_print_trs_all - print trs for all started requests. 612 * @hba: per-adapter instance. 613 * @pr_prdt: need to print prdt or not. 614 */ 615 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 616 { 617 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 618 } 619 620 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 621 { 622 int tag; 623 624 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 625 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 626 627 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 628 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 629 } 630 } 631 632 static void ufshcd_print_host_state(struct ufs_hba *hba) 633 { 634 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 635 636 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 637 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 638 hba->outstanding_reqs, hba->outstanding_tasks); 639 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 640 hba->saved_err, hba->saved_uic_err); 641 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 642 hba->curr_dev_pwr_mode, hba->uic_link_state); 643 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 644 hba->pm_op_in_progress, hba->is_sys_suspended); 645 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 646 hba->auto_bkops_enabled, hba->host->host_self_blocked); 647 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 648 dev_err(hba->dev, 649 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 650 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 651 hba->ufs_stats.hibern8_exit_cnt); 652 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 653 div_u64(hba->ufs_stats.last_intr_ts, 1000), 654 hba->ufs_stats.last_intr_status); 655 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 656 hba->eh_flags, hba->req_abort_count); 657 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 658 hba->ufs_version, hba->capabilities, hba->caps); 659 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 660 hba->dev_quirks); 661 if (sdev_ufs) 662 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 663 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 664 665 ufshcd_print_clk_freqs(hba); 666 } 667 668 /** 669 * ufshcd_print_pwr_info - print power params as saved in hba 670 * power info 671 * @hba: per-adapter instance 672 */ 673 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 674 { 675 static const char * const names[] = { 676 "INVALID MODE", 677 "FAST MODE", 678 "SLOW_MODE", 679 "INVALID MODE", 680 "FASTAUTO_MODE", 681 "SLOWAUTO_MODE", 682 "INVALID MODE", 683 }; 684 685 /* 686 * Using dev_dbg to avoid messages during runtime PM to avoid 687 * never-ending cycles of messages written back to storage by user space 688 * causing runtime resume, causing more messages and so on. 689 */ 690 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 691 __func__, 692 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 693 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 694 names[hba->pwr_info.pwr_rx], 695 names[hba->pwr_info.pwr_tx], 696 hba->pwr_info.hs_rate); 697 } 698 699 static void ufshcd_device_reset(struct ufs_hba *hba) 700 { 701 int err; 702 703 err = ufshcd_vops_device_reset(hba); 704 705 if (!err) { 706 ufshcd_set_ufs_dev_active(hba); 707 if (ufshcd_is_wb_allowed(hba)) { 708 hba->dev_info.wb_enabled = false; 709 hba->dev_info.wb_buf_flush_enabled = false; 710 } 711 if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 712 hba->dev_info.rtc_time_baseline = 0; 713 } 714 if (err != -EOPNOTSUPP) 715 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 716 } 717 718 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 719 { 720 if (!us) 721 return; 722 723 if (us < 10) 724 udelay(us); 725 else 726 usleep_range(us, us + tolerance); 727 } 728 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 729 730 /** 731 * ufshcd_wait_for_register - wait for register value to change 732 * @hba: per-adapter interface 733 * @reg: mmio register offset 734 * @mask: mask to apply to the read register value 735 * @val: value to wait for 736 * @interval_us: polling interval in microseconds 737 * @timeout_ms: timeout in milliseconds 738 * 739 * Return: -ETIMEDOUT on error, zero on success. 740 */ 741 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 742 u32 val, unsigned long interval_us, 743 unsigned long timeout_ms) 744 { 745 int err = 0; 746 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 747 748 /* ignore bits that we don't intend to wait on */ 749 val = val & mask; 750 751 while ((ufshcd_readl(hba, reg) & mask) != val) { 752 usleep_range(interval_us, interval_us + 50); 753 if (time_after(jiffies, timeout)) { 754 if ((ufshcd_readl(hba, reg) & mask) != val) 755 err = -ETIMEDOUT; 756 break; 757 } 758 } 759 760 return err; 761 } 762 763 /** 764 * ufshcd_get_intr_mask - Get the interrupt bit mask 765 * @hba: Pointer to adapter instance 766 * 767 * Return: interrupt bit mask per version 768 */ 769 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 770 { 771 if (hba->ufs_version <= ufshci_version(2, 0)) 772 return INTERRUPT_MASK_ALL_VER_11; 773 774 return INTERRUPT_MASK_ALL_VER_21; 775 } 776 777 /** 778 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 779 * @hba: Pointer to adapter instance 780 * 781 * Return: UFSHCI version supported by the controller 782 */ 783 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 784 { 785 u32 ufshci_ver; 786 787 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 788 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 789 else 790 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 791 792 /* 793 * UFSHCI v1.x uses a different version scheme, in order 794 * to allow the use of comparisons with the ufshci_version 795 * function, we convert it to the same scheme as ufs 2.0+. 796 */ 797 if (ufshci_ver & 0x00010000) 798 return ufshci_version(1, ufshci_ver & 0x00000100); 799 800 return ufshci_ver; 801 } 802 803 /** 804 * ufshcd_is_device_present - Check if any device connected to 805 * the host controller 806 * @hba: pointer to adapter instance 807 * 808 * Return: true if device present, false if no device detected 809 */ 810 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 811 { 812 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 813 } 814 815 /** 816 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 817 * @lrbp: pointer to local command reference block 818 * @cqe: pointer to the completion queue entry 819 * 820 * This function is used to get the OCS field from UTRD 821 * 822 * Return: the OCS field in the UTRD. 823 */ 824 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 825 struct cq_entry *cqe) 826 { 827 if (cqe) 828 return le32_to_cpu(cqe->status) & MASK_OCS; 829 830 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 831 } 832 833 /** 834 * ufshcd_utrl_clear() - Clear requests from the controller request list. 835 * @hba: per adapter instance 836 * @mask: mask with one bit set for each request to be cleared 837 */ 838 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 839 { 840 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 841 mask = ~mask; 842 /* 843 * From the UFSHCI specification: "UTP Transfer Request List CLear 844 * Register (UTRLCLR): This field is bit significant. Each bit 845 * corresponds to a slot in the UTP Transfer Request List, where bit 0 846 * corresponds to request slot 0. A bit in this field is set to ‘0’ 847 * by host software to indicate to the host controller that a transfer 848 * request slot is cleared. The host controller 849 * shall free up any resources associated to the request slot 850 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 851 * host software indicates no change to request slots by setting the 852 * associated bits in this field to ‘1’. Bits in this field shall only 853 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 854 */ 855 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 856 } 857 858 /** 859 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 860 * @hba: per adapter instance 861 * @pos: position of the bit to be cleared 862 */ 863 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 864 { 865 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 866 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 867 else 868 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 869 } 870 871 /** 872 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 873 * @reg: Register value of host controller status 874 * 875 * Return: 0 on success; a positive value if failed. 876 */ 877 static inline int ufshcd_get_lists_status(u32 reg) 878 { 879 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 880 } 881 882 /** 883 * ufshcd_get_uic_cmd_result - Get the UIC command result 884 * @hba: Pointer to adapter instance 885 * 886 * This function gets the result of UIC command completion 887 * 888 * Return: 0 on success; non-zero value on error. 889 */ 890 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 891 { 892 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 893 MASK_UIC_COMMAND_RESULT; 894 } 895 896 /** 897 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 898 * @hba: Pointer to adapter instance 899 * 900 * This function gets UIC command argument3 901 * 902 * Return: 0 on success; non-zero value on error. 903 */ 904 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 905 { 906 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 907 } 908 909 /** 910 * ufshcd_get_req_rsp - returns the TR response transaction type 911 * @ucd_rsp_ptr: pointer to response UPIU 912 * 913 * Return: UPIU type. 914 */ 915 static inline enum upiu_response_transaction 916 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 917 { 918 return ucd_rsp_ptr->header.transaction_code; 919 } 920 921 /** 922 * ufshcd_is_exception_event - Check if the device raised an exception event 923 * @ucd_rsp_ptr: pointer to response UPIU 924 * 925 * The function checks if the device raised an exception event indicated in 926 * the Device Information field of response UPIU. 927 * 928 * Return: true if exception is raised, false otherwise. 929 */ 930 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 931 { 932 return ucd_rsp_ptr->header.device_information & 1; 933 } 934 935 /** 936 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 937 * @hba: per adapter instance 938 */ 939 static inline void 940 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 941 { 942 ufshcd_writel(hba, INT_AGGR_ENABLE | 943 INT_AGGR_COUNTER_AND_TIMER_RESET, 944 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 945 } 946 947 /** 948 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 949 * @hba: per adapter instance 950 * @cnt: Interrupt aggregation counter threshold 951 * @tmout: Interrupt aggregation timeout value 952 */ 953 static inline void 954 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 955 { 956 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 957 INT_AGGR_COUNTER_THLD_VAL(cnt) | 958 INT_AGGR_TIMEOUT_VAL(tmout), 959 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 960 } 961 962 /** 963 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 964 * @hba: per adapter instance 965 */ 966 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 967 { 968 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 969 } 970 971 /** 972 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 973 * When run-stop registers are set to 1, it indicates the 974 * host controller that it can process the requests 975 * @hba: per adapter instance 976 */ 977 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 978 { 979 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 980 REG_UTP_TASK_REQ_LIST_RUN_STOP); 981 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 982 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 983 } 984 985 /** 986 * ufshcd_hba_start - Start controller initialization sequence 987 * @hba: per adapter instance 988 */ 989 static inline void ufshcd_hba_start(struct ufs_hba *hba) 990 { 991 u32 val = CONTROLLER_ENABLE; 992 993 if (ufshcd_crypto_enable(hba)) 994 val |= CRYPTO_GENERAL_ENABLE; 995 996 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 997 } 998 999 /** 1000 * ufshcd_is_hba_active - Get controller state 1001 * @hba: per adapter instance 1002 * 1003 * Return: true if and only if the controller is active. 1004 */ 1005 bool ufshcd_is_hba_active(struct ufs_hba *hba) 1006 { 1007 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 1008 } 1009 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 1010 1011 /** 1012 * ufshcd_pm_qos_init - initialize PM QoS request 1013 * @hba: per adapter instance 1014 */ 1015 void ufshcd_pm_qos_init(struct ufs_hba *hba) 1016 { 1017 1018 if (hba->pm_qos_enabled) 1019 return; 1020 1021 cpu_latency_qos_add_request(&hba->pm_qos_req, PM_QOS_DEFAULT_VALUE); 1022 1023 if (cpu_latency_qos_request_active(&hba->pm_qos_req)) 1024 hba->pm_qos_enabled = true; 1025 } 1026 1027 /** 1028 * ufshcd_pm_qos_exit - remove request from PM QoS 1029 * @hba: per adapter instance 1030 */ 1031 void ufshcd_pm_qos_exit(struct ufs_hba *hba) 1032 { 1033 if (!hba->pm_qos_enabled) 1034 return; 1035 1036 cpu_latency_qos_remove_request(&hba->pm_qos_req); 1037 hba->pm_qos_enabled = false; 1038 } 1039 1040 /** 1041 * ufshcd_pm_qos_update - update PM QoS request 1042 * @hba: per adapter instance 1043 * @on: If True, vote for perf PM QoS mode otherwise power save mode 1044 */ 1045 static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) 1046 { 1047 if (!hba->pm_qos_enabled) 1048 return; 1049 1050 cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE); 1051 } 1052 1053 /** 1054 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1055 * @hba: per adapter instance 1056 * @scale_up: If True, set max possible frequency othewise set low frequency 1057 * 1058 * Return: 0 if successful; < 0 upon failure. 1059 */ 1060 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1061 { 1062 int ret = 0; 1063 struct ufs_clk_info *clki; 1064 struct list_head *head = &hba->clk_list_head; 1065 1066 if (list_empty(head)) 1067 goto out; 1068 1069 list_for_each_entry(clki, head, list) { 1070 if (!IS_ERR_OR_NULL(clki->clk)) { 1071 if (scale_up && clki->max_freq) { 1072 if (clki->curr_freq == clki->max_freq) 1073 continue; 1074 1075 ret = clk_set_rate(clki->clk, clki->max_freq); 1076 if (ret) { 1077 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1078 __func__, clki->name, 1079 clki->max_freq, ret); 1080 break; 1081 } 1082 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1083 "scaled up", clki->name, 1084 clki->curr_freq, 1085 clki->max_freq); 1086 1087 clki->curr_freq = clki->max_freq; 1088 1089 } else if (!scale_up && clki->min_freq) { 1090 if (clki->curr_freq == clki->min_freq) 1091 continue; 1092 1093 ret = clk_set_rate(clki->clk, clki->min_freq); 1094 if (ret) { 1095 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1096 __func__, clki->name, 1097 clki->min_freq, ret); 1098 break; 1099 } 1100 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1101 "scaled down", clki->name, 1102 clki->curr_freq, 1103 clki->min_freq); 1104 clki->curr_freq = clki->min_freq; 1105 } 1106 } 1107 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1108 clki->name, clk_get_rate(clki->clk)); 1109 } 1110 1111 out: 1112 return ret; 1113 } 1114 1115 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1116 struct dev_pm_opp *opp, void *data, 1117 bool scaling_down) 1118 { 1119 struct ufs_hba *hba = dev_get_drvdata(dev); 1120 struct list_head *head = &hba->clk_list_head; 1121 struct ufs_clk_info *clki; 1122 unsigned long freq; 1123 u8 idx = 0; 1124 int ret; 1125 1126 list_for_each_entry(clki, head, list) { 1127 if (!IS_ERR_OR_NULL(clki->clk)) { 1128 freq = dev_pm_opp_get_freq_indexed(opp, idx++); 1129 1130 /* Do not set rate for clocks having frequency as 0 */ 1131 if (!freq) 1132 continue; 1133 1134 ret = clk_set_rate(clki->clk, freq); 1135 if (ret) { 1136 dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n", 1137 __func__, clki->name, freq, ret); 1138 return ret; 1139 } 1140 1141 trace_ufshcd_clk_scaling(dev_name(dev), 1142 (scaling_down ? "scaled down" : "scaled up"), 1143 clki->name, hba->clk_scaling.target_freq, freq); 1144 } 1145 } 1146 1147 return 0; 1148 } 1149 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks); 1150 1151 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) 1152 { 1153 struct dev_pm_opp *opp; 1154 int ret; 1155 1156 opp = dev_pm_opp_find_freq_floor_indexed(hba->dev, 1157 &freq, 0); 1158 if (IS_ERR(opp)) 1159 return PTR_ERR(opp); 1160 1161 ret = dev_pm_opp_set_opp(hba->dev, opp); 1162 dev_pm_opp_put(opp); 1163 1164 return ret; 1165 } 1166 1167 /** 1168 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1169 * @hba: per adapter instance 1170 * @freq: frequency to scale 1171 * @scale_up: True if scaling up and false if scaling down 1172 * 1173 * Return: 0 if successful; < 0 upon failure. 1174 */ 1175 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 1176 bool scale_up) 1177 { 1178 int ret = 0; 1179 ktime_t start = ktime_get(); 1180 1181 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1182 if (ret) 1183 goto out; 1184 1185 if (hba->use_pm_opp) 1186 ret = ufshcd_opp_set_rate(hba, freq); 1187 else 1188 ret = ufshcd_set_clk_freq(hba, scale_up); 1189 if (ret) 1190 goto out; 1191 1192 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1193 if (ret) { 1194 if (hba->use_pm_opp) 1195 ufshcd_opp_set_rate(hba, 1196 hba->devfreq->previous_freq); 1197 else 1198 ufshcd_set_clk_freq(hba, !scale_up); 1199 goto out; 1200 } 1201 1202 ufshcd_pm_qos_update(hba, scale_up); 1203 1204 out: 1205 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1206 (scale_up ? "up" : "down"), 1207 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1208 return ret; 1209 } 1210 1211 /** 1212 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1213 * @hba: per adapter instance 1214 * @freq: frequency to scale 1215 * @scale_up: True if scaling up and false if scaling down 1216 * 1217 * Return: true if scaling is required, false otherwise. 1218 */ 1219 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1220 unsigned long freq, bool scale_up) 1221 { 1222 struct ufs_clk_info *clki; 1223 struct list_head *head = &hba->clk_list_head; 1224 1225 if (list_empty(head)) 1226 return false; 1227 1228 if (hba->use_pm_opp) 1229 return freq != hba->clk_scaling.target_freq; 1230 1231 list_for_each_entry(clki, head, list) { 1232 if (!IS_ERR_OR_NULL(clki->clk)) { 1233 if (scale_up && clki->max_freq) { 1234 if (clki->curr_freq == clki->max_freq) 1235 continue; 1236 return true; 1237 } else if (!scale_up && clki->min_freq) { 1238 if (clki->curr_freq == clki->min_freq) 1239 continue; 1240 return true; 1241 } 1242 } 1243 } 1244 1245 return false; 1246 } 1247 1248 /* 1249 * Determine the number of pending commands by counting the bits in the SCSI 1250 * device budget maps. This approach has been selected because a bit is set in 1251 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1252 * flag. The host_self_blocked flag can be modified by calling 1253 * scsi_block_requests() or scsi_unblock_requests(). 1254 */ 1255 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1256 { 1257 const struct scsi_device *sdev; 1258 u32 pending = 0; 1259 1260 lockdep_assert_held(hba->host->host_lock); 1261 __shost_for_each_device(sdev, hba->host) 1262 pending += sbitmap_weight(&sdev->budget_map); 1263 1264 return pending; 1265 } 1266 1267 /* 1268 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1269 * has expired. 1270 * 1271 * Return: 0 upon success; -EBUSY upon timeout. 1272 */ 1273 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1274 u64 wait_timeout_us) 1275 { 1276 unsigned long flags; 1277 int ret = 0; 1278 u32 tm_doorbell; 1279 u32 tr_pending; 1280 bool timeout = false, do_last_check = false; 1281 ktime_t start; 1282 1283 ufshcd_hold(hba); 1284 spin_lock_irqsave(hba->host->host_lock, flags); 1285 /* 1286 * Wait for all the outstanding tasks/transfer requests. 1287 * Verify by checking the doorbell registers are clear. 1288 */ 1289 start = ktime_get(); 1290 do { 1291 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1292 ret = -EBUSY; 1293 goto out; 1294 } 1295 1296 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1297 tr_pending = ufshcd_pending_cmds(hba); 1298 if (!tm_doorbell && !tr_pending) { 1299 timeout = false; 1300 break; 1301 } else if (do_last_check) { 1302 break; 1303 } 1304 1305 spin_unlock_irqrestore(hba->host->host_lock, flags); 1306 io_schedule_timeout(msecs_to_jiffies(20)); 1307 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1308 wait_timeout_us) { 1309 timeout = true; 1310 /* 1311 * We might have scheduled out for long time so make 1312 * sure to check if doorbells are cleared by this time 1313 * or not. 1314 */ 1315 do_last_check = true; 1316 } 1317 spin_lock_irqsave(hba->host->host_lock, flags); 1318 } while (tm_doorbell || tr_pending); 1319 1320 if (timeout) { 1321 dev_err(hba->dev, 1322 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1323 __func__, tm_doorbell, tr_pending); 1324 ret = -EBUSY; 1325 } 1326 out: 1327 spin_unlock_irqrestore(hba->host->host_lock, flags); 1328 ufshcd_release(hba); 1329 return ret; 1330 } 1331 1332 /** 1333 * ufshcd_scale_gear - scale up/down UFS gear 1334 * @hba: per adapter instance 1335 * @scale_up: True for scaling up gear and false for scaling down 1336 * 1337 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1338 * non-zero for any other errors. 1339 */ 1340 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1341 { 1342 int ret = 0; 1343 struct ufs_pa_layer_attr new_pwr_info; 1344 1345 if (scale_up) { 1346 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1347 sizeof(struct ufs_pa_layer_attr)); 1348 } else { 1349 memcpy(&new_pwr_info, &hba->pwr_info, 1350 sizeof(struct ufs_pa_layer_attr)); 1351 1352 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1353 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1354 /* save the current power mode */ 1355 memcpy(&hba->clk_scaling.saved_pwr_info, 1356 &hba->pwr_info, 1357 sizeof(struct ufs_pa_layer_attr)); 1358 1359 /* scale down gear */ 1360 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1361 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1362 } 1363 } 1364 1365 /* check if the power mode needs to be changed or not? */ 1366 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1367 if (ret) 1368 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1369 __func__, ret, 1370 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1371 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1372 1373 return ret; 1374 } 1375 1376 /* 1377 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1378 * has expired. 1379 * 1380 * Return: 0 upon success; -EBUSY upon timeout. 1381 */ 1382 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1383 { 1384 int ret = 0; 1385 /* 1386 * make sure that there are no outstanding requests when 1387 * clock scaling is in progress 1388 */ 1389 blk_mq_quiesce_tagset(&hba->host->tag_set); 1390 mutex_lock(&hba->wb_mutex); 1391 down_write(&hba->clk_scaling_lock); 1392 1393 if (!hba->clk_scaling.is_allowed || 1394 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1395 ret = -EBUSY; 1396 up_write(&hba->clk_scaling_lock); 1397 mutex_unlock(&hba->wb_mutex); 1398 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1399 goto out; 1400 } 1401 1402 /* let's not get into low power until clock scaling is completed */ 1403 ufshcd_hold(hba); 1404 1405 out: 1406 return ret; 1407 } 1408 1409 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1410 { 1411 up_write(&hba->clk_scaling_lock); 1412 1413 /* Enable Write Booster if we have scaled up else disable it */ 1414 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1415 ufshcd_wb_toggle(hba, scale_up); 1416 1417 mutex_unlock(&hba->wb_mutex); 1418 1419 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1420 ufshcd_release(hba); 1421 } 1422 1423 /** 1424 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1425 * @hba: per adapter instance 1426 * @freq: frequency to scale 1427 * @scale_up: True for scaling up and false for scalin down 1428 * 1429 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1430 * for any other errors. 1431 */ 1432 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, 1433 bool scale_up) 1434 { 1435 int ret = 0; 1436 1437 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1438 if (ret) 1439 return ret; 1440 1441 /* scale down the gear before scaling down clocks */ 1442 if (!scale_up) { 1443 ret = ufshcd_scale_gear(hba, false); 1444 if (ret) 1445 goto out_unprepare; 1446 } 1447 1448 ret = ufshcd_scale_clks(hba, freq, scale_up); 1449 if (ret) { 1450 if (!scale_up) 1451 ufshcd_scale_gear(hba, true); 1452 goto out_unprepare; 1453 } 1454 1455 /* scale up the gear after scaling up clocks */ 1456 if (scale_up) { 1457 ret = ufshcd_scale_gear(hba, true); 1458 if (ret) { 1459 ufshcd_scale_clks(hba, hba->devfreq->previous_freq, 1460 false); 1461 goto out_unprepare; 1462 } 1463 } 1464 1465 out_unprepare: 1466 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1467 return ret; 1468 } 1469 1470 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1471 { 1472 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1473 clk_scaling.suspend_work); 1474 unsigned long irq_flags; 1475 1476 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1477 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1478 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1479 return; 1480 } 1481 hba->clk_scaling.is_suspended = true; 1482 hba->clk_scaling.window_start_t = 0; 1483 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1484 1485 devfreq_suspend_device(hba->devfreq); 1486 } 1487 1488 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1489 { 1490 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1491 clk_scaling.resume_work); 1492 unsigned long irq_flags; 1493 1494 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1495 if (!hba->clk_scaling.is_suspended) { 1496 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1497 return; 1498 } 1499 hba->clk_scaling.is_suspended = false; 1500 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1501 1502 devfreq_resume_device(hba->devfreq); 1503 } 1504 1505 static int ufshcd_devfreq_target(struct device *dev, 1506 unsigned long *freq, u32 flags) 1507 { 1508 int ret = 0; 1509 struct ufs_hba *hba = dev_get_drvdata(dev); 1510 ktime_t start; 1511 bool scale_up = false, sched_clk_scaling_suspend_work = false; 1512 struct list_head *clk_list = &hba->clk_list_head; 1513 struct ufs_clk_info *clki; 1514 unsigned long irq_flags; 1515 1516 if (!ufshcd_is_clkscaling_supported(hba)) 1517 return -EINVAL; 1518 1519 if (hba->use_pm_opp) { 1520 struct dev_pm_opp *opp; 1521 1522 /* Get the recommended frequency from OPP framework */ 1523 opp = devfreq_recommended_opp(dev, freq, flags); 1524 if (IS_ERR(opp)) 1525 return PTR_ERR(opp); 1526 1527 dev_pm_opp_put(opp); 1528 } else { 1529 /* Override with the closest supported frequency */ 1530 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, 1531 list); 1532 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1533 } 1534 1535 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1536 if (ufshcd_eh_in_progress(hba)) { 1537 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1538 return 0; 1539 } 1540 1541 /* Skip scaling clock when clock scaling is suspended */ 1542 if (hba->clk_scaling.is_suspended) { 1543 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1544 dev_warn(hba->dev, "clock scaling is suspended, skip"); 1545 return 0; 1546 } 1547 1548 if (!hba->clk_scaling.active_reqs) 1549 sched_clk_scaling_suspend_work = true; 1550 1551 if (list_empty(clk_list)) { 1552 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1553 goto out; 1554 } 1555 1556 /* Decide based on the target or rounded-off frequency and update */ 1557 if (hba->use_pm_opp) 1558 scale_up = *freq > hba->clk_scaling.target_freq; 1559 else 1560 scale_up = *freq == clki->max_freq; 1561 1562 if (!hba->use_pm_opp && !scale_up) 1563 *freq = clki->min_freq; 1564 1565 /* Update the frequency */ 1566 if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) { 1567 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1568 ret = 0; 1569 goto out; /* no state change required */ 1570 } 1571 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1572 1573 start = ktime_get(); 1574 ret = ufshcd_devfreq_scale(hba, *freq, scale_up); 1575 if (!ret) 1576 hba->clk_scaling.target_freq = *freq; 1577 1578 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1579 (scale_up ? "up" : "down"), 1580 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1581 1582 out: 1583 if (sched_clk_scaling_suspend_work && 1584 (!scale_up || hba->clk_scaling.suspend_on_no_request)) 1585 queue_work(hba->clk_scaling.workq, 1586 &hba->clk_scaling.suspend_work); 1587 1588 return ret; 1589 } 1590 1591 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1592 struct devfreq_dev_status *stat) 1593 { 1594 struct ufs_hba *hba = dev_get_drvdata(dev); 1595 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1596 unsigned long flags; 1597 ktime_t curr_t; 1598 1599 if (!ufshcd_is_clkscaling_supported(hba)) 1600 return -EINVAL; 1601 1602 memset(stat, 0, sizeof(*stat)); 1603 1604 spin_lock_irqsave(hba->host->host_lock, flags); 1605 curr_t = ktime_get(); 1606 if (!scaling->window_start_t) 1607 goto start_window; 1608 1609 /* 1610 * If current frequency is 0, then the ondemand governor considers 1611 * there's no initial frequency set. And it always requests to set 1612 * to max. frequency. 1613 */ 1614 if (hba->use_pm_opp) { 1615 stat->current_frequency = hba->clk_scaling.target_freq; 1616 } else { 1617 struct list_head *clk_list = &hba->clk_list_head; 1618 struct ufs_clk_info *clki; 1619 1620 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1621 stat->current_frequency = clki->curr_freq; 1622 } 1623 1624 if (scaling->is_busy_started) 1625 scaling->tot_busy_t += ktime_us_delta(curr_t, 1626 scaling->busy_start_t); 1627 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1628 stat->busy_time = scaling->tot_busy_t; 1629 start_window: 1630 scaling->window_start_t = curr_t; 1631 scaling->tot_busy_t = 0; 1632 1633 if (scaling->active_reqs) { 1634 scaling->busy_start_t = curr_t; 1635 scaling->is_busy_started = true; 1636 } else { 1637 scaling->busy_start_t = 0; 1638 scaling->is_busy_started = false; 1639 } 1640 spin_unlock_irqrestore(hba->host->host_lock, flags); 1641 return 0; 1642 } 1643 1644 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1645 { 1646 struct list_head *clk_list = &hba->clk_list_head; 1647 struct ufs_clk_info *clki; 1648 struct devfreq *devfreq; 1649 int ret; 1650 1651 /* Skip devfreq if we don't have any clocks in the list */ 1652 if (list_empty(clk_list)) 1653 return 0; 1654 1655 if (!hba->use_pm_opp) { 1656 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1657 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1658 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1659 } 1660 1661 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1662 &hba->vps->ondemand_data); 1663 devfreq = devfreq_add_device(hba->dev, 1664 &hba->vps->devfreq_profile, 1665 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1666 &hba->vps->ondemand_data); 1667 if (IS_ERR(devfreq)) { 1668 ret = PTR_ERR(devfreq); 1669 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1670 1671 if (!hba->use_pm_opp) { 1672 dev_pm_opp_remove(hba->dev, clki->min_freq); 1673 dev_pm_opp_remove(hba->dev, clki->max_freq); 1674 } 1675 return ret; 1676 } 1677 1678 hba->devfreq = devfreq; 1679 1680 return 0; 1681 } 1682 1683 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1684 { 1685 struct list_head *clk_list = &hba->clk_list_head; 1686 1687 if (!hba->devfreq) 1688 return; 1689 1690 devfreq_remove_device(hba->devfreq); 1691 hba->devfreq = NULL; 1692 1693 if (!hba->use_pm_opp) { 1694 struct ufs_clk_info *clki; 1695 1696 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1697 dev_pm_opp_remove(hba->dev, clki->min_freq); 1698 dev_pm_opp_remove(hba->dev, clki->max_freq); 1699 } 1700 } 1701 1702 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1703 { 1704 unsigned long flags; 1705 bool suspend = false; 1706 1707 cancel_work_sync(&hba->clk_scaling.suspend_work); 1708 cancel_work_sync(&hba->clk_scaling.resume_work); 1709 1710 spin_lock_irqsave(hba->host->host_lock, flags); 1711 if (!hba->clk_scaling.is_suspended) { 1712 suspend = true; 1713 hba->clk_scaling.is_suspended = true; 1714 hba->clk_scaling.window_start_t = 0; 1715 } 1716 spin_unlock_irqrestore(hba->host->host_lock, flags); 1717 1718 if (suspend) 1719 devfreq_suspend_device(hba->devfreq); 1720 } 1721 1722 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1723 { 1724 unsigned long flags; 1725 bool resume = false; 1726 1727 spin_lock_irqsave(hba->host->host_lock, flags); 1728 if (hba->clk_scaling.is_suspended) { 1729 resume = true; 1730 hba->clk_scaling.is_suspended = false; 1731 } 1732 spin_unlock_irqrestore(hba->host->host_lock, flags); 1733 1734 if (resume) 1735 devfreq_resume_device(hba->devfreq); 1736 } 1737 1738 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1739 struct device_attribute *attr, char *buf) 1740 { 1741 struct ufs_hba *hba = dev_get_drvdata(dev); 1742 1743 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1744 } 1745 1746 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1747 struct device_attribute *attr, const char *buf, size_t count) 1748 { 1749 struct ufs_hba *hba = dev_get_drvdata(dev); 1750 u32 value; 1751 int err = 0; 1752 1753 if (kstrtou32(buf, 0, &value)) 1754 return -EINVAL; 1755 1756 down(&hba->host_sem); 1757 if (!ufshcd_is_user_access_allowed(hba)) { 1758 err = -EBUSY; 1759 goto out; 1760 } 1761 1762 value = !!value; 1763 if (value == hba->clk_scaling.is_enabled) 1764 goto out; 1765 1766 ufshcd_rpm_get_sync(hba); 1767 ufshcd_hold(hba); 1768 1769 hba->clk_scaling.is_enabled = value; 1770 1771 if (value) { 1772 ufshcd_resume_clkscaling(hba); 1773 } else { 1774 ufshcd_suspend_clkscaling(hba); 1775 err = ufshcd_devfreq_scale(hba, ULONG_MAX, true); 1776 if (err) 1777 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1778 __func__, err); 1779 } 1780 1781 ufshcd_release(hba); 1782 ufshcd_rpm_put_sync(hba); 1783 out: 1784 up(&hba->host_sem); 1785 return err ? err : count; 1786 } 1787 1788 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1789 { 1790 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1791 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1792 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1793 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1794 hba->clk_scaling.enable_attr.attr.mode = 0644; 1795 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1796 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1797 } 1798 1799 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1800 { 1801 if (hba->clk_scaling.enable_attr.attr.name) 1802 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1803 } 1804 1805 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1806 { 1807 if (!ufshcd_is_clkscaling_supported(hba)) 1808 return; 1809 1810 if (!hba->clk_scaling.min_gear) 1811 hba->clk_scaling.min_gear = UFS_HS_G1; 1812 1813 INIT_WORK(&hba->clk_scaling.suspend_work, 1814 ufshcd_clk_scaling_suspend_work); 1815 INIT_WORK(&hba->clk_scaling.resume_work, 1816 ufshcd_clk_scaling_resume_work); 1817 1818 hba->clk_scaling.workq = alloc_ordered_workqueue( 1819 "ufs_clkscaling_%d", WQ_MEM_RECLAIM, hba->host->host_no); 1820 1821 hba->clk_scaling.is_initialized = true; 1822 } 1823 1824 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1825 { 1826 if (!hba->clk_scaling.is_initialized) 1827 return; 1828 1829 ufshcd_remove_clk_scaling_sysfs(hba); 1830 destroy_workqueue(hba->clk_scaling.workq); 1831 ufshcd_devfreq_remove(hba); 1832 hba->clk_scaling.is_initialized = false; 1833 } 1834 1835 static void ufshcd_ungate_work(struct work_struct *work) 1836 { 1837 int ret; 1838 unsigned long flags; 1839 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1840 clk_gating.ungate_work); 1841 1842 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1843 1844 spin_lock_irqsave(hba->host->host_lock, flags); 1845 if (hba->clk_gating.state == CLKS_ON) { 1846 spin_unlock_irqrestore(hba->host->host_lock, flags); 1847 return; 1848 } 1849 1850 spin_unlock_irqrestore(hba->host->host_lock, flags); 1851 ufshcd_hba_vreg_set_hpm(hba); 1852 ufshcd_setup_clocks(hba, true); 1853 1854 ufshcd_enable_irq(hba); 1855 1856 /* Exit from hibern8 */ 1857 if (ufshcd_can_hibern8_during_gating(hba)) { 1858 /* Prevent gating in this path */ 1859 hba->clk_gating.is_suspended = true; 1860 if (ufshcd_is_link_hibern8(hba)) { 1861 ret = ufshcd_uic_hibern8_exit(hba); 1862 if (ret) 1863 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1864 __func__, ret); 1865 else 1866 ufshcd_set_link_active(hba); 1867 } 1868 hba->clk_gating.is_suspended = false; 1869 } 1870 } 1871 1872 /** 1873 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1874 * Also, exit from hibern8 mode and set the link as active. 1875 * @hba: per adapter instance 1876 */ 1877 void ufshcd_hold(struct ufs_hba *hba) 1878 { 1879 bool flush_result; 1880 unsigned long flags; 1881 1882 if (!ufshcd_is_clkgating_allowed(hba) || 1883 !hba->clk_gating.is_initialized) 1884 return; 1885 spin_lock_irqsave(hba->host->host_lock, flags); 1886 hba->clk_gating.active_reqs++; 1887 1888 start: 1889 switch (hba->clk_gating.state) { 1890 case CLKS_ON: 1891 /* 1892 * Wait for the ungate work to complete if in progress. 1893 * Though the clocks may be in ON state, the link could 1894 * still be in hibner8 state if hibern8 is allowed 1895 * during clock gating. 1896 * Make sure we exit hibern8 state also in addition to 1897 * clocks being ON. 1898 */ 1899 if (ufshcd_can_hibern8_during_gating(hba) && 1900 ufshcd_is_link_hibern8(hba)) { 1901 spin_unlock_irqrestore(hba->host->host_lock, flags); 1902 flush_result = flush_work(&hba->clk_gating.ungate_work); 1903 if (hba->clk_gating.is_suspended && !flush_result) 1904 return; 1905 spin_lock_irqsave(hba->host->host_lock, flags); 1906 goto start; 1907 } 1908 break; 1909 case REQ_CLKS_OFF: 1910 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1911 hba->clk_gating.state = CLKS_ON; 1912 trace_ufshcd_clk_gating(dev_name(hba->dev), 1913 hba->clk_gating.state); 1914 break; 1915 } 1916 /* 1917 * If we are here, it means gating work is either done or 1918 * currently running. Hence, fall through to cancel gating 1919 * work and to enable clocks. 1920 */ 1921 fallthrough; 1922 case CLKS_OFF: 1923 hba->clk_gating.state = REQ_CLKS_ON; 1924 trace_ufshcd_clk_gating(dev_name(hba->dev), 1925 hba->clk_gating.state); 1926 queue_work(hba->clk_gating.clk_gating_workq, 1927 &hba->clk_gating.ungate_work); 1928 /* 1929 * fall through to check if we should wait for this 1930 * work to be done or not. 1931 */ 1932 fallthrough; 1933 case REQ_CLKS_ON: 1934 spin_unlock_irqrestore(hba->host->host_lock, flags); 1935 flush_work(&hba->clk_gating.ungate_work); 1936 /* Make sure state is CLKS_ON before returning */ 1937 spin_lock_irqsave(hba->host->host_lock, flags); 1938 goto start; 1939 default: 1940 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1941 __func__, hba->clk_gating.state); 1942 break; 1943 } 1944 spin_unlock_irqrestore(hba->host->host_lock, flags); 1945 } 1946 EXPORT_SYMBOL_GPL(ufshcd_hold); 1947 1948 static void ufshcd_gate_work(struct work_struct *work) 1949 { 1950 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1951 clk_gating.gate_work.work); 1952 unsigned long flags; 1953 int ret; 1954 1955 spin_lock_irqsave(hba->host->host_lock, flags); 1956 /* 1957 * In case you are here to cancel this work the gating state 1958 * would be marked as REQ_CLKS_ON. In this case save time by 1959 * skipping the gating work and exit after changing the clock 1960 * state to CLKS_ON. 1961 */ 1962 if (hba->clk_gating.is_suspended || 1963 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1964 hba->clk_gating.state = CLKS_ON; 1965 trace_ufshcd_clk_gating(dev_name(hba->dev), 1966 hba->clk_gating.state); 1967 goto rel_lock; 1968 } 1969 1970 if (ufshcd_is_ufs_dev_busy(hba) || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) 1971 goto rel_lock; 1972 1973 spin_unlock_irqrestore(hba->host->host_lock, flags); 1974 1975 /* put the link into hibern8 mode before turning off clocks */ 1976 if (ufshcd_can_hibern8_during_gating(hba)) { 1977 ret = ufshcd_uic_hibern8_enter(hba); 1978 if (ret) { 1979 hba->clk_gating.state = CLKS_ON; 1980 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1981 __func__, ret); 1982 trace_ufshcd_clk_gating(dev_name(hba->dev), 1983 hba->clk_gating.state); 1984 goto out; 1985 } 1986 ufshcd_set_link_hibern8(hba); 1987 } 1988 1989 ufshcd_disable_irq(hba); 1990 1991 ufshcd_setup_clocks(hba, false); 1992 1993 /* Put the host controller in low power mode if possible */ 1994 ufshcd_hba_vreg_set_lpm(hba); 1995 /* 1996 * In case you are here to cancel this work the gating state 1997 * would be marked as REQ_CLKS_ON. In this case keep the state 1998 * as REQ_CLKS_ON which would anyway imply that clocks are off 1999 * and a request to turn them on is pending. By doing this way, 2000 * we keep the state machine in tact and this would ultimately 2001 * prevent from doing cancel work multiple times when there are 2002 * new requests arriving before the current cancel work is done. 2003 */ 2004 spin_lock_irqsave(hba->host->host_lock, flags); 2005 if (hba->clk_gating.state == REQ_CLKS_OFF) { 2006 hba->clk_gating.state = CLKS_OFF; 2007 trace_ufshcd_clk_gating(dev_name(hba->dev), 2008 hba->clk_gating.state); 2009 } 2010 rel_lock: 2011 spin_unlock_irqrestore(hba->host->host_lock, flags); 2012 out: 2013 return; 2014 } 2015 2016 /* host lock must be held before calling this variant */ 2017 static void __ufshcd_release(struct ufs_hba *hba) 2018 { 2019 if (!ufshcd_is_clkgating_allowed(hba)) 2020 return; 2021 2022 hba->clk_gating.active_reqs--; 2023 2024 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 2025 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 2026 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 2027 hba->active_uic_cmd || hba->uic_async_done || 2028 hba->clk_gating.state == CLKS_OFF) 2029 return; 2030 2031 hba->clk_gating.state = REQ_CLKS_OFF; 2032 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 2033 queue_delayed_work(hba->clk_gating.clk_gating_workq, 2034 &hba->clk_gating.gate_work, 2035 msecs_to_jiffies(hba->clk_gating.delay_ms)); 2036 } 2037 2038 void ufshcd_release(struct ufs_hba *hba) 2039 { 2040 unsigned long flags; 2041 2042 spin_lock_irqsave(hba->host->host_lock, flags); 2043 __ufshcd_release(hba); 2044 spin_unlock_irqrestore(hba->host->host_lock, flags); 2045 } 2046 EXPORT_SYMBOL_GPL(ufshcd_release); 2047 2048 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 2049 struct device_attribute *attr, char *buf) 2050 { 2051 struct ufs_hba *hba = dev_get_drvdata(dev); 2052 2053 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 2054 } 2055 2056 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 2057 { 2058 struct ufs_hba *hba = dev_get_drvdata(dev); 2059 unsigned long flags; 2060 2061 spin_lock_irqsave(hba->host->host_lock, flags); 2062 hba->clk_gating.delay_ms = value; 2063 spin_unlock_irqrestore(hba->host->host_lock, flags); 2064 } 2065 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 2066 2067 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 2068 struct device_attribute *attr, const char *buf, size_t count) 2069 { 2070 unsigned long value; 2071 2072 if (kstrtoul(buf, 0, &value)) 2073 return -EINVAL; 2074 2075 ufshcd_clkgate_delay_set(dev, value); 2076 return count; 2077 } 2078 2079 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 2080 struct device_attribute *attr, char *buf) 2081 { 2082 struct ufs_hba *hba = dev_get_drvdata(dev); 2083 2084 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 2085 } 2086 2087 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 2088 struct device_attribute *attr, const char *buf, size_t count) 2089 { 2090 struct ufs_hba *hba = dev_get_drvdata(dev); 2091 unsigned long flags; 2092 u32 value; 2093 2094 if (kstrtou32(buf, 0, &value)) 2095 return -EINVAL; 2096 2097 value = !!value; 2098 2099 spin_lock_irqsave(hba->host->host_lock, flags); 2100 if (value == hba->clk_gating.is_enabled) 2101 goto out; 2102 2103 if (value) 2104 __ufshcd_release(hba); 2105 else 2106 hba->clk_gating.active_reqs++; 2107 2108 hba->clk_gating.is_enabled = value; 2109 out: 2110 spin_unlock_irqrestore(hba->host->host_lock, flags); 2111 return count; 2112 } 2113 2114 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 2115 { 2116 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 2117 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 2118 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 2119 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 2120 hba->clk_gating.delay_attr.attr.mode = 0644; 2121 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 2122 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 2123 2124 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 2125 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 2126 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 2127 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 2128 hba->clk_gating.enable_attr.attr.mode = 0644; 2129 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 2130 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 2131 } 2132 2133 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 2134 { 2135 if (hba->clk_gating.delay_attr.attr.name) 2136 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 2137 if (hba->clk_gating.enable_attr.attr.name) 2138 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 2139 } 2140 2141 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 2142 { 2143 if (!ufshcd_is_clkgating_allowed(hba)) 2144 return; 2145 2146 hba->clk_gating.state = CLKS_ON; 2147 2148 hba->clk_gating.delay_ms = 150; 2149 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2150 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2151 2152 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue( 2153 "ufs_clk_gating_%d", WQ_MEM_RECLAIM | WQ_HIGHPRI, 2154 hba->host->host_no); 2155 2156 ufshcd_init_clk_gating_sysfs(hba); 2157 2158 hba->clk_gating.is_enabled = true; 2159 hba->clk_gating.is_initialized = true; 2160 } 2161 2162 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2163 { 2164 if (!hba->clk_gating.is_initialized) 2165 return; 2166 2167 ufshcd_remove_clk_gating_sysfs(hba); 2168 2169 /* Ungate the clock if necessary. */ 2170 ufshcd_hold(hba); 2171 hba->clk_gating.is_initialized = false; 2172 ufshcd_release(hba); 2173 2174 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2175 } 2176 2177 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2178 { 2179 bool queue_resume_work = false; 2180 ktime_t curr_t = ktime_get(); 2181 unsigned long flags; 2182 2183 if (!ufshcd_is_clkscaling_supported(hba)) 2184 return; 2185 2186 spin_lock_irqsave(hba->host->host_lock, flags); 2187 if (!hba->clk_scaling.active_reqs++) 2188 queue_resume_work = true; 2189 2190 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2191 spin_unlock_irqrestore(hba->host->host_lock, flags); 2192 return; 2193 } 2194 2195 if (queue_resume_work) 2196 queue_work(hba->clk_scaling.workq, 2197 &hba->clk_scaling.resume_work); 2198 2199 if (!hba->clk_scaling.window_start_t) { 2200 hba->clk_scaling.window_start_t = curr_t; 2201 hba->clk_scaling.tot_busy_t = 0; 2202 hba->clk_scaling.is_busy_started = false; 2203 } 2204 2205 if (!hba->clk_scaling.is_busy_started) { 2206 hba->clk_scaling.busy_start_t = curr_t; 2207 hba->clk_scaling.is_busy_started = true; 2208 } 2209 spin_unlock_irqrestore(hba->host->host_lock, flags); 2210 } 2211 2212 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2213 { 2214 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2215 unsigned long flags; 2216 2217 if (!ufshcd_is_clkscaling_supported(hba)) 2218 return; 2219 2220 spin_lock_irqsave(hba->host->host_lock, flags); 2221 hba->clk_scaling.active_reqs--; 2222 if (!scaling->active_reqs && scaling->is_busy_started) { 2223 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2224 scaling->busy_start_t)); 2225 scaling->busy_start_t = 0; 2226 scaling->is_busy_started = false; 2227 } 2228 spin_unlock_irqrestore(hba->host->host_lock, flags); 2229 } 2230 2231 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2232 { 2233 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2234 return READ; 2235 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2236 return WRITE; 2237 else 2238 return -EINVAL; 2239 } 2240 2241 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2242 struct ufshcd_lrb *lrbp) 2243 { 2244 const struct ufs_hba_monitor *m = &hba->monitor; 2245 2246 return (m->enabled && lrbp && lrbp->cmd && 2247 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2248 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2249 } 2250 2251 static void ufshcd_start_monitor(struct ufs_hba *hba, 2252 const struct ufshcd_lrb *lrbp) 2253 { 2254 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2255 unsigned long flags; 2256 2257 spin_lock_irqsave(hba->host->host_lock, flags); 2258 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2259 hba->monitor.busy_start_ts[dir] = ktime_get(); 2260 spin_unlock_irqrestore(hba->host->host_lock, flags); 2261 } 2262 2263 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2264 { 2265 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2266 unsigned long flags; 2267 2268 spin_lock_irqsave(hba->host->host_lock, flags); 2269 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2270 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2271 struct ufs_hba_monitor *m = &hba->monitor; 2272 ktime_t now, inc, lat; 2273 2274 now = lrbp->compl_time_stamp; 2275 inc = ktime_sub(now, m->busy_start_ts[dir]); 2276 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2277 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2278 2279 /* Update latencies */ 2280 m->nr_req[dir]++; 2281 lat = ktime_sub(now, lrbp->issue_time_stamp); 2282 m->lat_sum[dir] += lat; 2283 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2284 m->lat_max[dir] = lat; 2285 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2286 m->lat_min[dir] = lat; 2287 2288 m->nr_queued[dir]--; 2289 /* Push forward the busy start of monitor */ 2290 m->busy_start_ts[dir] = now; 2291 } 2292 spin_unlock_irqrestore(hba->host->host_lock, flags); 2293 } 2294 2295 /** 2296 * ufshcd_send_command - Send SCSI or device management commands 2297 * @hba: per adapter instance 2298 * @task_tag: Task tag of the command 2299 * @hwq: pointer to hardware queue instance 2300 */ 2301 static inline 2302 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2303 struct ufs_hw_queue *hwq) 2304 { 2305 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2306 unsigned long flags; 2307 2308 lrbp->issue_time_stamp = ktime_get(); 2309 lrbp->issue_time_stamp_local_clock = local_clock(); 2310 lrbp->compl_time_stamp = ktime_set(0, 0); 2311 lrbp->compl_time_stamp_local_clock = 0; 2312 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2313 if (lrbp->cmd) 2314 ufshcd_clk_scaling_start_busy(hba); 2315 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2316 ufshcd_start_monitor(hba, lrbp); 2317 2318 if (hba->mcq_enabled) { 2319 int utrd_size = sizeof(struct utp_transfer_req_desc); 2320 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2321 struct utp_transfer_req_desc *dest; 2322 2323 spin_lock(&hwq->sq_lock); 2324 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2325 memcpy(dest, src, utrd_size); 2326 ufshcd_inc_sq_tail(hwq); 2327 spin_unlock(&hwq->sq_lock); 2328 } else { 2329 spin_lock_irqsave(&hba->outstanding_lock, flags); 2330 if (hba->vops && hba->vops->setup_xfer_req) 2331 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2332 !!lrbp->cmd); 2333 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2334 ufshcd_writel(hba, 1 << lrbp->task_tag, 2335 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2336 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2337 } 2338 } 2339 2340 /** 2341 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2342 * @lrbp: pointer to local reference block 2343 */ 2344 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2345 { 2346 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2347 u16 resp_len; 2348 int len; 2349 2350 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2351 if (sense_buffer && resp_len) { 2352 int len_to_copy; 2353 2354 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2355 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2356 2357 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2358 len_to_copy); 2359 } 2360 } 2361 2362 /** 2363 * ufshcd_copy_query_response() - Copy the Query Response and the data 2364 * descriptor 2365 * @hba: per adapter instance 2366 * @lrbp: pointer to local reference block 2367 * 2368 * Return: 0 upon success; < 0 upon failure. 2369 */ 2370 static 2371 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2372 { 2373 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2374 2375 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2376 2377 /* Get the descriptor */ 2378 if (hba->dev_cmd.query.descriptor && 2379 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2380 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2381 GENERAL_UPIU_REQUEST_SIZE; 2382 u16 resp_len; 2383 u16 buf_len; 2384 2385 /* data segment length */ 2386 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2387 .data_segment_length); 2388 buf_len = be16_to_cpu( 2389 hba->dev_cmd.query.request.upiu_req.length); 2390 if (likely(buf_len >= resp_len)) { 2391 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2392 } else { 2393 dev_warn(hba->dev, 2394 "%s: rsp size %d is bigger than buffer size %d", 2395 __func__, resp_len, buf_len); 2396 return -EINVAL; 2397 } 2398 } 2399 2400 return 0; 2401 } 2402 2403 /** 2404 * ufshcd_hba_capabilities - Read controller capabilities 2405 * @hba: per adapter instance 2406 * 2407 * Return: 0 on success, negative on error. 2408 */ 2409 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2410 { 2411 int err; 2412 2413 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2414 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) 2415 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT; 2416 2417 /* nutrs and nutmrs are 0 based values */ 2418 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS_SDB) + 1; 2419 hba->nutmrs = 2420 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2421 hba->reserved_slot = hba->nutrs - 1; 2422 2423 hba->nortt = FIELD_GET(MASK_NUMBER_OUTSTANDING_RTT, hba->capabilities) + 1; 2424 2425 /* Read crypto capabilities */ 2426 err = ufshcd_hba_init_crypto_capabilities(hba); 2427 if (err) { 2428 dev_err(hba->dev, "crypto setup failed\n"); 2429 return err; 2430 } 2431 2432 /* 2433 * The UFSHCI 3.0 specification does not define MCQ_SUPPORT and 2434 * LSDB_SUPPORT, but [31:29] as reserved bits with reset value 0s, which 2435 * means we can simply read values regardless of version. 2436 */ 2437 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2438 /* 2439 * 0h: legacy single doorbell support is available 2440 * 1h: indicate that legacy single doorbell support has been removed 2441 */ 2442 if (!(hba->quirks & UFSHCD_QUIRK_BROKEN_LSDBS_CAP)) 2443 hba->lsdb_sup = !FIELD_GET(MASK_LSDB_SUPPORT, hba->capabilities); 2444 else 2445 hba->lsdb_sup = true; 2446 2447 if (!hba->mcq_sup) 2448 return 0; 2449 2450 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2451 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2452 hba->mcq_capabilities); 2453 2454 return 0; 2455 } 2456 2457 /** 2458 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2459 * to accept UIC commands 2460 * @hba: per adapter instance 2461 * 2462 * Return: true on success, else false. 2463 */ 2464 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2465 { 2466 u32 val; 2467 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2468 500, uic_cmd_timeout * 1000, false, hba, 2469 REG_CONTROLLER_STATUS); 2470 return ret == 0; 2471 } 2472 2473 /** 2474 * ufshcd_get_upmcrs - Get the power mode change request status 2475 * @hba: Pointer to adapter instance 2476 * 2477 * This function gets the UPMCRS field of HCS register 2478 * 2479 * Return: value of UPMCRS field. 2480 */ 2481 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2482 { 2483 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2484 } 2485 2486 /** 2487 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2488 * @hba: per adapter instance 2489 * @uic_cmd: UIC command 2490 */ 2491 static inline void 2492 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2493 { 2494 lockdep_assert_held(&hba->uic_cmd_mutex); 2495 2496 WARN_ON(hba->active_uic_cmd); 2497 2498 hba->active_uic_cmd = uic_cmd; 2499 2500 /* Write Args */ 2501 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2502 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2503 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2504 2505 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2506 2507 /* Write UIC Cmd */ 2508 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2509 REG_UIC_COMMAND); 2510 } 2511 2512 /** 2513 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2514 * @hba: per adapter instance 2515 * @uic_cmd: UIC command 2516 * 2517 * Return: 0 only if success. 2518 */ 2519 static int 2520 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2521 { 2522 int ret; 2523 unsigned long flags; 2524 2525 lockdep_assert_held(&hba->uic_cmd_mutex); 2526 2527 if (wait_for_completion_timeout(&uic_cmd->done, 2528 msecs_to_jiffies(uic_cmd_timeout))) { 2529 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2530 } else { 2531 ret = -ETIMEDOUT; 2532 dev_err(hba->dev, 2533 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2534 uic_cmd->command, uic_cmd->argument3); 2535 2536 if (!uic_cmd->cmd_active) { 2537 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2538 __func__); 2539 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2540 } 2541 } 2542 2543 spin_lock_irqsave(hba->host->host_lock, flags); 2544 hba->active_uic_cmd = NULL; 2545 spin_unlock_irqrestore(hba->host->host_lock, flags); 2546 2547 return ret; 2548 } 2549 2550 /** 2551 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2552 * @hba: per adapter instance 2553 * @uic_cmd: UIC command 2554 * @completion: initialize the completion only if this is set to true 2555 * 2556 * Return: 0 only if success. 2557 */ 2558 static int 2559 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd, 2560 bool completion) 2561 { 2562 lockdep_assert_held(&hba->uic_cmd_mutex); 2563 2564 if (!ufshcd_ready_for_uic_cmd(hba)) { 2565 dev_err(hba->dev, 2566 "Controller not ready to accept UIC commands\n"); 2567 return -EIO; 2568 } 2569 2570 if (completion) 2571 init_completion(&uic_cmd->done); 2572 2573 uic_cmd->cmd_active = 1; 2574 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2575 2576 return 0; 2577 } 2578 2579 /** 2580 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2581 * @hba: per adapter instance 2582 * @uic_cmd: UIC command 2583 * 2584 * Return: 0 only if success. 2585 */ 2586 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2587 { 2588 int ret; 2589 2590 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2591 return 0; 2592 2593 ufshcd_hold(hba); 2594 mutex_lock(&hba->uic_cmd_mutex); 2595 ufshcd_add_delay_before_dme_cmd(hba); 2596 2597 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true); 2598 if (!ret) 2599 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2600 2601 mutex_unlock(&hba->uic_cmd_mutex); 2602 2603 ufshcd_release(hba); 2604 return ret; 2605 } 2606 2607 /** 2608 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2609 * @hba: per-adapter instance 2610 * @lrbp: pointer to local reference block 2611 * @sg_entries: The number of sg lists actually used 2612 * @sg_list: Pointer to SG list 2613 */ 2614 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2615 struct scatterlist *sg_list) 2616 { 2617 struct ufshcd_sg_entry *prd; 2618 struct scatterlist *sg; 2619 int i; 2620 2621 if (sg_entries) { 2622 2623 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2624 lrbp->utr_descriptor_ptr->prd_table_length = 2625 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2626 else 2627 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2628 2629 prd = lrbp->ucd_prdt_ptr; 2630 2631 for_each_sg(sg_list, sg, sg_entries, i) { 2632 const unsigned int len = sg_dma_len(sg); 2633 2634 /* 2635 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2636 * based value that indicates the length, in bytes, of 2637 * the data block. A maximum of length of 256KB may 2638 * exist for any entry. Bits 1:0 of this field shall be 2639 * 11b to indicate Dword granularity. A value of '3' 2640 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2641 */ 2642 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2643 prd->size = cpu_to_le32(len - 1); 2644 prd->addr = cpu_to_le64(sg->dma_address); 2645 prd->reserved = 0; 2646 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2647 } 2648 } else { 2649 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2650 } 2651 } 2652 2653 /** 2654 * ufshcd_map_sg - Map scatter-gather list to prdt 2655 * @hba: per adapter instance 2656 * @lrbp: pointer to local reference block 2657 * 2658 * Return: 0 in case of success, non-zero value in case of failure. 2659 */ 2660 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2661 { 2662 struct scsi_cmnd *cmd = lrbp->cmd; 2663 int sg_segments = scsi_dma_map(cmd); 2664 2665 if (sg_segments < 0) 2666 return sg_segments; 2667 2668 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2669 2670 return ufshcd_crypto_fill_prdt(hba, lrbp); 2671 } 2672 2673 /** 2674 * ufshcd_enable_intr - enable interrupts 2675 * @hba: per adapter instance 2676 * @intrs: interrupt bits 2677 */ 2678 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2679 { 2680 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2681 2682 set |= intrs; 2683 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2684 } 2685 2686 /** 2687 * ufshcd_disable_intr - disable interrupts 2688 * @hba: per adapter instance 2689 * @intrs: interrupt bits 2690 */ 2691 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2692 { 2693 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2694 2695 set &= ~intrs; 2696 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2697 } 2698 2699 /** 2700 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2701 * descriptor according to request 2702 * @hba: per adapter instance 2703 * @lrbp: pointer to local reference block 2704 * @upiu_flags: flags required in the header 2705 * @cmd_dir: requests data direction 2706 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2707 */ 2708 static void 2709 ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 2710 u8 *upiu_flags, enum dma_data_direction cmd_dir, 2711 int ehs_length) 2712 { 2713 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2714 struct request_desc_header *h = &req_desc->header; 2715 enum utp_data_direction data_direction; 2716 2717 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2718 2719 *h = (typeof(*h)){ }; 2720 2721 if (cmd_dir == DMA_FROM_DEVICE) { 2722 data_direction = UTP_DEVICE_TO_HOST; 2723 *upiu_flags = UPIU_CMD_FLAGS_READ; 2724 } else if (cmd_dir == DMA_TO_DEVICE) { 2725 data_direction = UTP_HOST_TO_DEVICE; 2726 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2727 } else { 2728 data_direction = UTP_NO_DATA_TRANSFER; 2729 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2730 } 2731 2732 h->command_type = lrbp->command_type; 2733 h->data_direction = data_direction; 2734 h->ehs_length = ehs_length; 2735 2736 if (lrbp->intr_cmd) 2737 h->interrupt = 1; 2738 2739 /* Prepare crypto related dwords */ 2740 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2741 2742 /* 2743 * assigning invalid value for command status. Controller 2744 * updates OCS on command completion, with the command 2745 * status 2746 */ 2747 h->ocs = OCS_INVALID_COMMAND_STATUS; 2748 2749 req_desc->prd_table_length = 0; 2750 } 2751 2752 /** 2753 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2754 * for scsi commands 2755 * @lrbp: local reference block pointer 2756 * @upiu_flags: flags 2757 */ 2758 static 2759 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2760 { 2761 struct scsi_cmnd *cmd = lrbp->cmd; 2762 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2763 unsigned short cdb_len; 2764 2765 ucd_req_ptr->header = (struct utp_upiu_header){ 2766 .transaction_code = UPIU_TRANSACTION_COMMAND, 2767 .flags = upiu_flags, 2768 .lun = lrbp->lun, 2769 .task_tag = lrbp->task_tag, 2770 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2771 }; 2772 2773 WARN_ON_ONCE(ucd_req_ptr->header.task_tag != lrbp->task_tag); 2774 2775 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2776 2777 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2778 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 2779 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2780 2781 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2782 } 2783 2784 /** 2785 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2786 * @hba: UFS hba 2787 * @lrbp: local reference block pointer 2788 * @upiu_flags: flags 2789 */ 2790 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2791 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2792 { 2793 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2794 struct ufs_query *query = &hba->dev_cmd.query; 2795 u16 len = be16_to_cpu(query->request.upiu_req.length); 2796 2797 /* Query request header */ 2798 ucd_req_ptr->header = (struct utp_upiu_header){ 2799 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2800 .flags = upiu_flags, 2801 .lun = lrbp->lun, 2802 .task_tag = lrbp->task_tag, 2803 .query_function = query->request.query_func, 2804 /* Data segment length only need for WRITE_DESC */ 2805 .data_segment_length = 2806 query->request.upiu_req.opcode == 2807 UPIU_QUERY_OPCODE_WRITE_DESC ? 2808 cpu_to_be16(len) : 2809 0, 2810 }; 2811 2812 /* Copy the Query Request buffer as is */ 2813 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2814 QUERY_OSF_SIZE); 2815 2816 /* Copy the Descriptor */ 2817 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2818 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2819 2820 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2821 } 2822 2823 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2824 { 2825 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2826 2827 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2828 2829 ucd_req_ptr->header = (struct utp_upiu_header){ 2830 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2831 .task_tag = lrbp->task_tag, 2832 }; 2833 2834 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2835 } 2836 2837 /** 2838 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2839 * for Device Management Purposes 2840 * @hba: per adapter instance 2841 * @lrbp: pointer to local reference block 2842 * 2843 * Return: 0 upon success; < 0 upon failure. 2844 */ 2845 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2846 struct ufshcd_lrb *lrbp) 2847 { 2848 u8 upiu_flags; 2849 int ret = 0; 2850 2851 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 2852 2853 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2854 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2855 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2856 ufshcd_prepare_utp_nop_upiu(lrbp); 2857 else 2858 ret = -EINVAL; 2859 2860 return ret; 2861 } 2862 2863 /** 2864 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2865 * for SCSI Purposes 2866 * @hba: per adapter instance 2867 * @lrbp: pointer to local reference block 2868 */ 2869 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2870 { 2871 struct request *rq = scsi_cmd_to_rq(lrbp->cmd); 2872 unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq)); 2873 u8 upiu_flags; 2874 2875 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0); 2876 if (ioprio_class == IOPRIO_CLASS_RT) 2877 upiu_flags |= UPIU_CMD_FLAGS_CP; 2878 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2879 } 2880 2881 /** 2882 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2883 * @upiu_wlun_id: UPIU W-LUN id 2884 * 2885 * Return: SCSI W-LUN id. 2886 */ 2887 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2888 { 2889 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2890 } 2891 2892 static inline bool is_device_wlun(struct scsi_device *sdev) 2893 { 2894 return sdev->lun == 2895 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2896 } 2897 2898 /* 2899 * Associate the UFS controller queue with the default and poll HCTX types. 2900 * Initialize the mq_map[] arrays. 2901 */ 2902 static void ufshcd_map_queues(struct Scsi_Host *shost) 2903 { 2904 struct ufs_hba *hba = shost_priv(shost); 2905 int i, queue_offset = 0; 2906 2907 if (!is_mcq_supported(hba)) { 2908 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2909 hba->nr_queues[HCTX_TYPE_READ] = 0; 2910 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2911 hba->nr_hw_queues = 1; 2912 } 2913 2914 for (i = 0; i < shost->nr_maps; i++) { 2915 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2916 2917 map->nr_queues = hba->nr_queues[i]; 2918 if (!map->nr_queues) 2919 continue; 2920 map->queue_offset = queue_offset; 2921 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2922 map->queue_offset = 0; 2923 2924 blk_mq_map_queues(map); 2925 queue_offset += map->nr_queues; 2926 } 2927 } 2928 2929 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2930 { 2931 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2932 i * ufshcd_get_ucd_size(hba); 2933 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2934 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2935 i * ufshcd_get_ucd_size(hba); 2936 u16 response_offset = le16_to_cpu(utrdlp[i].response_upiu_offset); 2937 u16 prdt_offset = le16_to_cpu(utrdlp[i].prd_table_offset); 2938 2939 lrb->utr_descriptor_ptr = utrdlp + i; 2940 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2941 i * sizeof(struct utp_transfer_req_desc); 2942 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2943 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2944 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2945 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2946 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2947 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2948 } 2949 2950 /** 2951 * ufshcd_queuecommand - main entry point for SCSI requests 2952 * @host: SCSI host pointer 2953 * @cmd: command from SCSI Midlayer 2954 * 2955 * Return: 0 for success, non-zero in case of failure. 2956 */ 2957 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2958 { 2959 struct ufs_hba *hba = shost_priv(host); 2960 int tag = scsi_cmd_to_rq(cmd)->tag; 2961 struct ufshcd_lrb *lrbp; 2962 int err = 0; 2963 struct ufs_hw_queue *hwq = NULL; 2964 2965 switch (hba->ufshcd_state) { 2966 case UFSHCD_STATE_OPERATIONAL: 2967 break; 2968 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2969 /* 2970 * SCSI error handler can call ->queuecommand() while UFS error 2971 * handler is in progress. Error interrupts could change the 2972 * state from UFSHCD_STATE_RESET to 2973 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2974 * being issued in that case. 2975 */ 2976 if (ufshcd_eh_in_progress(hba)) { 2977 err = SCSI_MLQUEUE_HOST_BUSY; 2978 goto out; 2979 } 2980 break; 2981 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2982 /* 2983 * pm_runtime_get_sync() is used at error handling preparation 2984 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2985 * PM ops, it can never be finished if we let SCSI layer keep 2986 * retrying it, which gets err handler stuck forever. Neither 2987 * can we let the scsi cmd pass through, because UFS is in bad 2988 * state, the scsi cmd may eventually time out, which will get 2989 * err handler blocked for too long. So, just fail the scsi cmd 2990 * sent from PM ops, err handler can recover PM error anyways. 2991 */ 2992 if (hba->pm_op_in_progress) { 2993 hba->force_reset = true; 2994 set_host_byte(cmd, DID_BAD_TARGET); 2995 scsi_done(cmd); 2996 goto out; 2997 } 2998 fallthrough; 2999 case UFSHCD_STATE_RESET: 3000 err = SCSI_MLQUEUE_HOST_BUSY; 3001 goto out; 3002 case UFSHCD_STATE_ERROR: 3003 set_host_byte(cmd, DID_ERROR); 3004 scsi_done(cmd); 3005 goto out; 3006 } 3007 3008 hba->req_abort_count = 0; 3009 3010 ufshcd_hold(hba); 3011 3012 lrbp = &hba->lrb[tag]; 3013 lrbp->cmd = cmd; 3014 lrbp->task_tag = tag; 3015 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 3016 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 3017 3018 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp); 3019 3020 lrbp->req_abort_skip = false; 3021 3022 ufshcd_comp_scsi_upiu(hba, lrbp); 3023 3024 err = ufshcd_map_sg(hba, lrbp); 3025 if (err) { 3026 ufshcd_release(hba); 3027 goto out; 3028 } 3029 3030 if (hba->mcq_enabled) 3031 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 3032 3033 ufshcd_send_command(hba, tag, hwq); 3034 3035 out: 3036 if (ufs_trigger_eh(hba)) { 3037 unsigned long flags; 3038 3039 spin_lock_irqsave(hba->host->host_lock, flags); 3040 ufshcd_schedule_eh_work(hba); 3041 spin_unlock_irqrestore(hba->host->host_lock, flags); 3042 } 3043 3044 return err; 3045 } 3046 3047 static void ufshcd_setup_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3048 enum dev_cmd_type cmd_type, u8 lun, int tag) 3049 { 3050 lrbp->cmd = NULL; 3051 lrbp->task_tag = tag; 3052 lrbp->lun = lun; 3053 lrbp->intr_cmd = true; /* No interrupt aggregation */ 3054 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 3055 hba->dev_cmd.type = cmd_type; 3056 } 3057 3058 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 3059 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 3060 { 3061 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 3062 3063 return ufshcd_compose_devman_upiu(hba, lrbp); 3064 } 3065 3066 /* 3067 * Check with the block layer if the command is inflight 3068 * @cmd: command to check. 3069 * 3070 * Return: true if command is inflight; false if not. 3071 */ 3072 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 3073 { 3074 return cmd && blk_mq_rq_state(scsi_cmd_to_rq(cmd)) == MQ_RQ_IN_FLIGHT; 3075 } 3076 3077 /* 3078 * Clear the pending command in the controller and wait until 3079 * the controller confirms that the command has been cleared. 3080 * @hba: per adapter instance 3081 * @task_tag: The tag number of the command to be cleared. 3082 */ 3083 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 3084 { 3085 u32 mask; 3086 unsigned long flags; 3087 int err; 3088 3089 if (hba->mcq_enabled) { 3090 /* 3091 * MCQ mode. Clean up the MCQ resources similar to 3092 * what the ufshcd_utrl_clear() does for SDB mode. 3093 */ 3094 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 3095 if (err) { 3096 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 3097 __func__, task_tag, err); 3098 return err; 3099 } 3100 return 0; 3101 } 3102 3103 mask = 1U << task_tag; 3104 3105 /* clear outstanding transaction before retry */ 3106 spin_lock_irqsave(hba->host->host_lock, flags); 3107 ufshcd_utrl_clear(hba, mask); 3108 spin_unlock_irqrestore(hba->host->host_lock, flags); 3109 3110 /* 3111 * wait for h/w to clear corresponding bit in door-bell. 3112 * max. wait is 1 sec. 3113 */ 3114 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 3115 mask, ~mask, 1000, 1000); 3116 } 3117 3118 /** 3119 * ufshcd_dev_cmd_completion() - handles device management command responses 3120 * @hba: per adapter instance 3121 * @lrbp: pointer to local reference block 3122 * 3123 * Return: 0 upon success; < 0 upon failure. 3124 */ 3125 static int 3126 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 3127 { 3128 enum upiu_response_transaction resp; 3129 int err = 0; 3130 3131 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 3132 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3133 3134 switch (resp) { 3135 case UPIU_TRANSACTION_NOP_IN: 3136 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3137 err = -EINVAL; 3138 dev_err(hba->dev, "%s: unexpected response %x\n", 3139 __func__, resp); 3140 } 3141 break; 3142 case UPIU_TRANSACTION_QUERY_RSP: { 3143 u8 response = lrbp->ucd_rsp_ptr->header.response; 3144 3145 if (response == 0) 3146 err = ufshcd_copy_query_response(hba, lrbp); 3147 break; 3148 } 3149 case UPIU_TRANSACTION_REJECT_UPIU: 3150 /* TODO: handle Reject UPIU Response */ 3151 err = -EPERM; 3152 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3153 __func__); 3154 break; 3155 case UPIU_TRANSACTION_RESPONSE: 3156 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3157 err = -EINVAL; 3158 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3159 } 3160 break; 3161 default: 3162 err = -EINVAL; 3163 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3164 __func__, resp); 3165 break; 3166 } 3167 3168 return err; 3169 } 3170 3171 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3172 struct ufshcd_lrb *lrbp, int max_timeout) 3173 { 3174 unsigned long time_left = msecs_to_jiffies(max_timeout); 3175 unsigned long flags; 3176 bool pending; 3177 int err; 3178 3179 retry: 3180 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3181 time_left); 3182 3183 if (likely(time_left)) { 3184 /* 3185 * The completion handler called complete() and the caller of 3186 * this function still owns the @lrbp tag so the code below does 3187 * not trigger any race conditions. 3188 */ 3189 hba->dev_cmd.complete = NULL; 3190 err = ufshcd_get_tr_ocs(lrbp, NULL); 3191 if (!err) 3192 err = ufshcd_dev_cmd_completion(hba, lrbp); 3193 } else { 3194 err = -ETIMEDOUT; 3195 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3196 __func__, lrbp->task_tag); 3197 3198 /* MCQ mode */ 3199 if (hba->mcq_enabled) { 3200 /* successfully cleared the command, retry if needed */ 3201 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) 3202 err = -EAGAIN; 3203 hba->dev_cmd.complete = NULL; 3204 return err; 3205 } 3206 3207 /* SDB mode */ 3208 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3209 /* successfully cleared the command, retry if needed */ 3210 err = -EAGAIN; 3211 /* 3212 * Since clearing the command succeeded we also need to 3213 * clear the task tag bit from the outstanding_reqs 3214 * variable. 3215 */ 3216 spin_lock_irqsave(&hba->outstanding_lock, flags); 3217 pending = test_bit(lrbp->task_tag, 3218 &hba->outstanding_reqs); 3219 if (pending) { 3220 hba->dev_cmd.complete = NULL; 3221 __clear_bit(lrbp->task_tag, 3222 &hba->outstanding_reqs); 3223 } 3224 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3225 3226 if (!pending) { 3227 /* 3228 * The completion handler ran while we tried to 3229 * clear the command. 3230 */ 3231 time_left = 1; 3232 goto retry; 3233 } 3234 } else { 3235 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3236 __func__, lrbp->task_tag); 3237 3238 spin_lock_irqsave(&hba->outstanding_lock, flags); 3239 pending = test_bit(lrbp->task_tag, 3240 &hba->outstanding_reqs); 3241 if (pending) 3242 hba->dev_cmd.complete = NULL; 3243 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3244 3245 if (!pending) { 3246 /* 3247 * The completion handler ran while we tried to 3248 * clear the command. 3249 */ 3250 time_left = 1; 3251 goto retry; 3252 } 3253 } 3254 } 3255 3256 return err; 3257 } 3258 3259 static void ufshcd_dev_man_lock(struct ufs_hba *hba) 3260 { 3261 ufshcd_hold(hba); 3262 mutex_lock(&hba->dev_cmd.lock); 3263 down_read(&hba->clk_scaling_lock); 3264 } 3265 3266 static void ufshcd_dev_man_unlock(struct ufs_hba *hba) 3267 { 3268 up_read(&hba->clk_scaling_lock); 3269 mutex_unlock(&hba->dev_cmd.lock); 3270 ufshcd_release(hba); 3271 } 3272 3273 static int ufshcd_issue_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3274 const u32 tag, int timeout) 3275 { 3276 DECLARE_COMPLETION_ONSTACK(wait); 3277 int err; 3278 3279 hba->dev_cmd.complete = &wait; 3280 3281 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3282 3283 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3284 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3285 3286 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3287 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3288 3289 return err; 3290 } 3291 3292 /** 3293 * ufshcd_exec_dev_cmd - API for sending device management requests 3294 * @hba: UFS hba 3295 * @cmd_type: specifies the type (NOP, Query...) 3296 * @timeout: timeout in milliseconds 3297 * 3298 * Return: 0 upon success; < 0 upon failure. 3299 * 3300 * NOTE: Since there is only one available tag for device management commands, 3301 * it is expected you hold the hba->dev_cmd.lock mutex. 3302 */ 3303 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3304 enum dev_cmd_type cmd_type, int timeout) 3305 { 3306 const u32 tag = hba->reserved_slot; 3307 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 3308 int err; 3309 3310 /* Protects use of hba->reserved_slot. */ 3311 lockdep_assert_held(&hba->dev_cmd.lock); 3312 3313 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3314 if (unlikely(err)) 3315 return err; 3316 3317 return ufshcd_issue_dev_cmd(hba, lrbp, tag, timeout); 3318 } 3319 3320 /** 3321 * ufshcd_init_query() - init the query response and request parameters 3322 * @hba: per-adapter instance 3323 * @request: address of the request pointer to be initialized 3324 * @response: address of the response pointer to be initialized 3325 * @opcode: operation to perform 3326 * @idn: flag idn to access 3327 * @index: LU number to access 3328 * @selector: query/flag/descriptor further identification 3329 */ 3330 static inline void ufshcd_init_query(struct ufs_hba *hba, 3331 struct ufs_query_req **request, struct ufs_query_res **response, 3332 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3333 { 3334 *request = &hba->dev_cmd.query.request; 3335 *response = &hba->dev_cmd.query.response; 3336 memset(*request, 0, sizeof(struct ufs_query_req)); 3337 memset(*response, 0, sizeof(struct ufs_query_res)); 3338 (*request)->upiu_req.opcode = opcode; 3339 (*request)->upiu_req.idn = idn; 3340 (*request)->upiu_req.index = index; 3341 (*request)->upiu_req.selector = selector; 3342 } 3343 3344 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3345 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3346 { 3347 int ret; 3348 int retries; 3349 3350 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3351 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3352 if (ret) 3353 dev_dbg(hba->dev, 3354 "%s: failed with error %d, retries %d\n", 3355 __func__, ret, retries); 3356 else 3357 break; 3358 } 3359 3360 if (ret) 3361 dev_err(hba->dev, 3362 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3363 __func__, opcode, idn, ret, retries); 3364 return ret; 3365 } 3366 3367 /** 3368 * ufshcd_query_flag() - API function for sending flag query requests 3369 * @hba: per-adapter instance 3370 * @opcode: flag query to perform 3371 * @idn: flag idn to access 3372 * @index: flag index to access 3373 * @flag_res: the flag value after the query request completes 3374 * 3375 * Return: 0 for success, non-zero in case of failure. 3376 */ 3377 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3378 enum flag_idn idn, u8 index, bool *flag_res) 3379 { 3380 struct ufs_query_req *request = NULL; 3381 struct ufs_query_res *response = NULL; 3382 int err, selector = 0; 3383 int timeout = QUERY_REQ_TIMEOUT; 3384 3385 BUG_ON(!hba); 3386 3387 ufshcd_dev_man_lock(hba); 3388 3389 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3390 selector); 3391 3392 switch (opcode) { 3393 case UPIU_QUERY_OPCODE_SET_FLAG: 3394 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3395 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3396 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3397 break; 3398 case UPIU_QUERY_OPCODE_READ_FLAG: 3399 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3400 if (!flag_res) { 3401 /* No dummy reads */ 3402 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3403 __func__); 3404 err = -EINVAL; 3405 goto out_unlock; 3406 } 3407 break; 3408 default: 3409 dev_err(hba->dev, 3410 "%s: Expected query flag opcode but got = %d\n", 3411 __func__, opcode); 3412 err = -EINVAL; 3413 goto out_unlock; 3414 } 3415 3416 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3417 3418 if (err) { 3419 dev_err(hba->dev, 3420 "%s: Sending flag query for idn %d failed, err = %d\n", 3421 __func__, idn, err); 3422 goto out_unlock; 3423 } 3424 3425 if (flag_res) 3426 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3427 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3428 3429 out_unlock: 3430 ufshcd_dev_man_unlock(hba); 3431 return err; 3432 } 3433 3434 /** 3435 * ufshcd_query_attr - API function for sending attribute requests 3436 * @hba: per-adapter instance 3437 * @opcode: attribute opcode 3438 * @idn: attribute idn to access 3439 * @index: index field 3440 * @selector: selector field 3441 * @attr_val: the attribute value after the query request completes 3442 * 3443 * Return: 0 for success, non-zero in case of failure. 3444 */ 3445 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3446 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3447 { 3448 struct ufs_query_req *request = NULL; 3449 struct ufs_query_res *response = NULL; 3450 int err; 3451 3452 BUG_ON(!hba); 3453 3454 if (!attr_val) { 3455 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3456 __func__, opcode); 3457 return -EINVAL; 3458 } 3459 3460 ufshcd_dev_man_lock(hba); 3461 3462 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3463 selector); 3464 3465 switch (opcode) { 3466 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3467 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3468 request->upiu_req.value = cpu_to_be32(*attr_val); 3469 break; 3470 case UPIU_QUERY_OPCODE_READ_ATTR: 3471 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3472 break; 3473 default: 3474 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3475 __func__, opcode); 3476 err = -EINVAL; 3477 goto out_unlock; 3478 } 3479 3480 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3481 3482 if (err) { 3483 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3484 __func__, opcode, idn, index, err); 3485 goto out_unlock; 3486 } 3487 3488 *attr_val = be32_to_cpu(response->upiu_res.value); 3489 3490 out_unlock: 3491 ufshcd_dev_man_unlock(hba); 3492 return err; 3493 } 3494 3495 /** 3496 * ufshcd_query_attr_retry() - API function for sending query 3497 * attribute with retries 3498 * @hba: per-adapter instance 3499 * @opcode: attribute opcode 3500 * @idn: attribute idn to access 3501 * @index: index field 3502 * @selector: selector field 3503 * @attr_val: the attribute value after the query request 3504 * completes 3505 * 3506 * Return: 0 for success, non-zero in case of failure. 3507 */ 3508 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3509 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3510 u32 *attr_val) 3511 { 3512 int ret = 0; 3513 u32 retries; 3514 3515 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3516 ret = ufshcd_query_attr(hba, opcode, idn, index, 3517 selector, attr_val); 3518 if (ret) 3519 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3520 __func__, ret, retries); 3521 else 3522 break; 3523 } 3524 3525 if (ret) 3526 dev_err(hba->dev, 3527 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3528 __func__, idn, ret, QUERY_REQ_RETRIES); 3529 return ret; 3530 } 3531 3532 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3533 enum query_opcode opcode, enum desc_idn idn, u8 index, 3534 u8 selector, u8 *desc_buf, int *buf_len) 3535 { 3536 struct ufs_query_req *request = NULL; 3537 struct ufs_query_res *response = NULL; 3538 int err; 3539 3540 BUG_ON(!hba); 3541 3542 if (!desc_buf) { 3543 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3544 __func__, opcode); 3545 return -EINVAL; 3546 } 3547 3548 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3549 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3550 __func__, *buf_len); 3551 return -EINVAL; 3552 } 3553 3554 ufshcd_dev_man_lock(hba); 3555 3556 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3557 selector); 3558 hba->dev_cmd.query.descriptor = desc_buf; 3559 request->upiu_req.length = cpu_to_be16(*buf_len); 3560 3561 switch (opcode) { 3562 case UPIU_QUERY_OPCODE_WRITE_DESC: 3563 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3564 break; 3565 case UPIU_QUERY_OPCODE_READ_DESC: 3566 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3567 break; 3568 default: 3569 dev_err(hba->dev, 3570 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3571 __func__, opcode); 3572 err = -EINVAL; 3573 goto out_unlock; 3574 } 3575 3576 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3577 3578 if (err) { 3579 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3580 __func__, opcode, idn, index, err); 3581 goto out_unlock; 3582 } 3583 3584 *buf_len = be16_to_cpu(response->upiu_res.length); 3585 3586 out_unlock: 3587 hba->dev_cmd.query.descriptor = NULL; 3588 ufshcd_dev_man_unlock(hba); 3589 return err; 3590 } 3591 3592 /** 3593 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3594 * @hba: per-adapter instance 3595 * @opcode: attribute opcode 3596 * @idn: attribute idn to access 3597 * @index: index field 3598 * @selector: selector field 3599 * @desc_buf: the buffer that contains the descriptor 3600 * @buf_len: length parameter passed to the device 3601 * 3602 * The buf_len parameter will contain, on return, the length parameter 3603 * received on the response. 3604 * 3605 * Return: 0 for success, non-zero in case of failure. 3606 */ 3607 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3608 enum query_opcode opcode, 3609 enum desc_idn idn, u8 index, 3610 u8 selector, 3611 u8 *desc_buf, int *buf_len) 3612 { 3613 int err; 3614 int retries; 3615 3616 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3617 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3618 selector, desc_buf, buf_len); 3619 if (!err || err == -EINVAL) 3620 break; 3621 } 3622 3623 return err; 3624 } 3625 3626 /** 3627 * ufshcd_read_desc_param - read the specified descriptor parameter 3628 * @hba: Pointer to adapter instance 3629 * @desc_id: descriptor idn value 3630 * @desc_index: descriptor index 3631 * @param_offset: offset of the parameter to read 3632 * @param_read_buf: pointer to buffer where parameter would be read 3633 * @param_size: sizeof(param_read_buf) 3634 * 3635 * Return: 0 in case of success, non-zero otherwise. 3636 */ 3637 int ufshcd_read_desc_param(struct ufs_hba *hba, 3638 enum desc_idn desc_id, 3639 int desc_index, 3640 u8 param_offset, 3641 u8 *param_read_buf, 3642 u8 param_size) 3643 { 3644 int ret; 3645 u8 *desc_buf; 3646 int buff_len = QUERY_DESC_MAX_SIZE; 3647 bool is_kmalloc = true; 3648 3649 /* Safety check */ 3650 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3651 return -EINVAL; 3652 3653 /* Check whether we need temp memory */ 3654 if (param_offset != 0 || param_size < buff_len) { 3655 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3656 if (!desc_buf) 3657 return -ENOMEM; 3658 } else { 3659 desc_buf = param_read_buf; 3660 is_kmalloc = false; 3661 } 3662 3663 /* Request for full descriptor */ 3664 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3665 desc_id, desc_index, 0, 3666 desc_buf, &buff_len); 3667 if (ret) { 3668 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3669 __func__, desc_id, desc_index, param_offset, ret); 3670 goto out; 3671 } 3672 3673 /* Update descriptor length */ 3674 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3675 3676 if (param_offset >= buff_len) { 3677 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3678 __func__, param_offset, desc_id, buff_len); 3679 ret = -EINVAL; 3680 goto out; 3681 } 3682 3683 /* Sanity check */ 3684 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3685 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3686 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3687 ret = -EINVAL; 3688 goto out; 3689 } 3690 3691 if (is_kmalloc) { 3692 /* Make sure we don't copy more data than available */ 3693 if (param_offset >= buff_len) 3694 ret = -EINVAL; 3695 else 3696 memcpy(param_read_buf, &desc_buf[param_offset], 3697 min_t(u32, param_size, buff_len - param_offset)); 3698 } 3699 out: 3700 if (is_kmalloc) 3701 kfree(desc_buf); 3702 return ret; 3703 } 3704 3705 /** 3706 * struct uc_string_id - unicode string 3707 * 3708 * @len: size of this descriptor inclusive 3709 * @type: descriptor type 3710 * @uc: unicode string character 3711 */ 3712 struct uc_string_id { 3713 u8 len; 3714 u8 type; 3715 wchar_t uc[]; 3716 } __packed; 3717 3718 /* replace non-printable or non-ASCII characters with spaces */ 3719 static inline char ufshcd_remove_non_printable(u8 ch) 3720 { 3721 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3722 } 3723 3724 /** 3725 * ufshcd_read_string_desc - read string descriptor 3726 * @hba: pointer to adapter instance 3727 * @desc_index: descriptor index 3728 * @buf: pointer to buffer where descriptor would be read, 3729 * the caller should free the memory. 3730 * @ascii: if true convert from unicode to ascii characters 3731 * null terminated string. 3732 * 3733 * Return: 3734 * * string size on success. 3735 * * -ENOMEM: on allocation failure 3736 * * -EINVAL: on a wrong parameter 3737 */ 3738 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3739 u8 **buf, bool ascii) 3740 { 3741 struct uc_string_id *uc_str; 3742 u8 *str; 3743 int ret; 3744 3745 if (!buf) 3746 return -EINVAL; 3747 3748 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3749 if (!uc_str) 3750 return -ENOMEM; 3751 3752 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3753 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3754 if (ret < 0) { 3755 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3756 QUERY_REQ_RETRIES, ret); 3757 str = NULL; 3758 goto out; 3759 } 3760 3761 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3762 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3763 str = NULL; 3764 ret = 0; 3765 goto out; 3766 } 3767 3768 if (ascii) { 3769 ssize_t ascii_len; 3770 int i; 3771 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3772 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3773 str = kzalloc(ascii_len, GFP_KERNEL); 3774 if (!str) { 3775 ret = -ENOMEM; 3776 goto out; 3777 } 3778 3779 /* 3780 * the descriptor contains string in UTF16 format 3781 * we need to convert to utf-8 so it can be displayed 3782 */ 3783 ret = utf16s_to_utf8s(uc_str->uc, 3784 uc_str->len - QUERY_DESC_HDR_SIZE, 3785 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3786 3787 /* replace non-printable or non-ASCII characters with spaces */ 3788 for (i = 0; i < ret; i++) 3789 str[i] = ufshcd_remove_non_printable(str[i]); 3790 3791 str[ret++] = '\0'; 3792 3793 } else { 3794 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3795 if (!str) { 3796 ret = -ENOMEM; 3797 goto out; 3798 } 3799 ret = uc_str->len; 3800 } 3801 out: 3802 *buf = str; 3803 kfree(uc_str); 3804 return ret; 3805 } 3806 3807 /** 3808 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3809 * @hba: Pointer to adapter instance 3810 * @lun: lun id 3811 * @param_offset: offset of the parameter to read 3812 * @param_read_buf: pointer to buffer where parameter would be read 3813 * @param_size: sizeof(param_read_buf) 3814 * 3815 * Return: 0 in case of success, non-zero otherwise. 3816 */ 3817 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3818 int lun, 3819 enum unit_desc_param param_offset, 3820 u8 *param_read_buf, 3821 u32 param_size) 3822 { 3823 /* 3824 * Unit descriptors are only available for general purpose LUs (LUN id 3825 * from 0 to 7) and RPMB Well known LU. 3826 */ 3827 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3828 return -EOPNOTSUPP; 3829 3830 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3831 param_offset, param_read_buf, param_size); 3832 } 3833 3834 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3835 { 3836 int err = 0; 3837 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3838 3839 if (hba->dev_info.wspecversion >= 0x300) { 3840 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3841 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3842 &gating_wait); 3843 if (err) 3844 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3845 err, gating_wait); 3846 3847 if (gating_wait == 0) { 3848 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3849 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3850 gating_wait); 3851 } 3852 3853 hba->dev_info.clk_gating_wait_us = gating_wait; 3854 } 3855 3856 return err; 3857 } 3858 3859 /** 3860 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3861 * @hba: per adapter instance 3862 * 3863 * 1. Allocate DMA memory for Command Descriptor array 3864 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3865 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3866 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3867 * (UTMRDL) 3868 * 4. Allocate memory for local reference block(lrb). 3869 * 3870 * Return: 0 for success, non-zero in case of failure. 3871 */ 3872 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3873 { 3874 size_t utmrdl_size, utrdl_size, ucdl_size; 3875 3876 /* Allocate memory for UTP command descriptors */ 3877 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3878 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3879 ucdl_size, 3880 &hba->ucdl_dma_addr, 3881 GFP_KERNEL); 3882 3883 /* 3884 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3885 */ 3886 if (!hba->ucdl_base_addr || 3887 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3888 dev_err(hba->dev, 3889 "Command Descriptor Memory allocation failed\n"); 3890 goto out; 3891 } 3892 3893 /* 3894 * Allocate memory for UTP Transfer descriptors 3895 * UFSHCI requires 1KB alignment of UTRD 3896 */ 3897 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3898 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3899 utrdl_size, 3900 &hba->utrdl_dma_addr, 3901 GFP_KERNEL); 3902 if (!hba->utrdl_base_addr || 3903 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3904 dev_err(hba->dev, 3905 "Transfer Descriptor Memory allocation failed\n"); 3906 goto out; 3907 } 3908 3909 /* 3910 * Skip utmrdl allocation; it may have been 3911 * allocated during first pass and not released during 3912 * MCQ memory allocation. 3913 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3914 */ 3915 if (hba->utmrdl_base_addr) 3916 goto skip_utmrdl; 3917 /* 3918 * Allocate memory for UTP Task Management descriptors 3919 * UFSHCI requires 1KB alignment of UTMRD 3920 */ 3921 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3922 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3923 utmrdl_size, 3924 &hba->utmrdl_dma_addr, 3925 GFP_KERNEL); 3926 if (!hba->utmrdl_base_addr || 3927 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3928 dev_err(hba->dev, 3929 "Task Management Descriptor Memory allocation failed\n"); 3930 goto out; 3931 } 3932 3933 skip_utmrdl: 3934 /* Allocate memory for local reference block */ 3935 hba->lrb = devm_kcalloc(hba->dev, 3936 hba->nutrs, sizeof(struct ufshcd_lrb), 3937 GFP_KERNEL); 3938 if (!hba->lrb) { 3939 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3940 goto out; 3941 } 3942 return 0; 3943 out: 3944 return -ENOMEM; 3945 } 3946 3947 /** 3948 * ufshcd_host_memory_configure - configure local reference block with 3949 * memory offsets 3950 * @hba: per adapter instance 3951 * 3952 * Configure Host memory space 3953 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3954 * address. 3955 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3956 * and PRDT offset. 3957 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3958 * into local reference block. 3959 */ 3960 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3961 { 3962 struct utp_transfer_req_desc *utrdlp; 3963 dma_addr_t cmd_desc_dma_addr; 3964 dma_addr_t cmd_desc_element_addr; 3965 u16 response_offset; 3966 u16 prdt_offset; 3967 int cmd_desc_size; 3968 int i; 3969 3970 utrdlp = hba->utrdl_base_addr; 3971 3972 response_offset = 3973 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3974 prdt_offset = 3975 offsetof(struct utp_transfer_cmd_desc, prd_table); 3976 3977 cmd_desc_size = ufshcd_get_ucd_size(hba); 3978 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3979 3980 for (i = 0; i < hba->nutrs; i++) { 3981 /* Configure UTRD with command descriptor base address */ 3982 cmd_desc_element_addr = 3983 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3984 utrdlp[i].command_desc_base_addr = 3985 cpu_to_le64(cmd_desc_element_addr); 3986 3987 /* Response upiu and prdt offset should be in double words */ 3988 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3989 utrdlp[i].response_upiu_offset = 3990 cpu_to_le16(response_offset); 3991 utrdlp[i].prd_table_offset = 3992 cpu_to_le16(prdt_offset); 3993 utrdlp[i].response_upiu_length = 3994 cpu_to_le16(ALIGNED_UPIU_SIZE); 3995 } else { 3996 utrdlp[i].response_upiu_offset = 3997 cpu_to_le16(response_offset >> 2); 3998 utrdlp[i].prd_table_offset = 3999 cpu_to_le16(prdt_offset >> 2); 4000 utrdlp[i].response_upiu_length = 4001 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 4002 } 4003 4004 ufshcd_init_lrb(hba, &hba->lrb[i], i); 4005 } 4006 } 4007 4008 /** 4009 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 4010 * @hba: per adapter instance 4011 * 4012 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 4013 * in order to initialize the Unipro link startup procedure. 4014 * Once the Unipro links are up, the device connected to the controller 4015 * is detected. 4016 * 4017 * Return: 0 on success, non-zero value on failure. 4018 */ 4019 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 4020 { 4021 struct uic_command uic_cmd = { 4022 .command = UIC_CMD_DME_LINK_STARTUP, 4023 }; 4024 int ret; 4025 4026 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4027 if (ret) 4028 dev_dbg(hba->dev, 4029 "dme-link-startup: error code %d\n", ret); 4030 return ret; 4031 } 4032 /** 4033 * ufshcd_dme_reset - UIC command for DME_RESET 4034 * @hba: per adapter instance 4035 * 4036 * DME_RESET command is issued in order to reset UniPro stack. 4037 * This function now deals with cold reset. 4038 * 4039 * Return: 0 on success, non-zero value on failure. 4040 */ 4041 static int ufshcd_dme_reset(struct ufs_hba *hba) 4042 { 4043 struct uic_command uic_cmd = { 4044 .command = UIC_CMD_DME_RESET, 4045 }; 4046 int ret; 4047 4048 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4049 if (ret) 4050 dev_err(hba->dev, 4051 "dme-reset: error code %d\n", ret); 4052 4053 return ret; 4054 } 4055 4056 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 4057 int agreed_gear, 4058 int adapt_val) 4059 { 4060 int ret; 4061 4062 if (agreed_gear < UFS_HS_G4) 4063 adapt_val = PA_NO_ADAPT; 4064 4065 ret = ufshcd_dme_set(hba, 4066 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 4067 adapt_val); 4068 return ret; 4069 } 4070 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 4071 4072 /** 4073 * ufshcd_dme_enable - UIC command for DME_ENABLE 4074 * @hba: per adapter instance 4075 * 4076 * DME_ENABLE command is issued in order to enable UniPro stack. 4077 * 4078 * Return: 0 on success, non-zero value on failure. 4079 */ 4080 static int ufshcd_dme_enable(struct ufs_hba *hba) 4081 { 4082 struct uic_command uic_cmd = { 4083 .command = UIC_CMD_DME_ENABLE, 4084 }; 4085 int ret; 4086 4087 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4088 if (ret) 4089 dev_err(hba->dev, 4090 "dme-enable: error code %d\n", ret); 4091 4092 return ret; 4093 } 4094 4095 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 4096 { 4097 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 4098 unsigned long min_sleep_time_us; 4099 4100 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 4101 return; 4102 4103 /* 4104 * last_dme_cmd_tstamp will be 0 only for 1st call to 4105 * this function 4106 */ 4107 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 4108 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 4109 } else { 4110 unsigned long delta = 4111 (unsigned long) ktime_to_us( 4112 ktime_sub(ktime_get(), 4113 hba->last_dme_cmd_tstamp)); 4114 4115 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 4116 min_sleep_time_us = 4117 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 4118 else 4119 min_sleep_time_us = 0; /* no more delay required */ 4120 } 4121 4122 if (min_sleep_time_us > 0) { 4123 /* allow sleep for extra 50us if needed */ 4124 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 4125 } 4126 4127 /* update the last_dme_cmd_tstamp */ 4128 hba->last_dme_cmd_tstamp = ktime_get(); 4129 } 4130 4131 /** 4132 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 4133 * @hba: per adapter instance 4134 * @attr_sel: uic command argument1 4135 * @attr_set: attribute set type as uic command argument2 4136 * @mib_val: setting value as uic command argument3 4137 * @peer: indicate whether peer or local 4138 * 4139 * Return: 0 on success, non-zero value on failure. 4140 */ 4141 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 4142 u8 attr_set, u32 mib_val, u8 peer) 4143 { 4144 struct uic_command uic_cmd = { 4145 .command = peer ? UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET, 4146 .argument1 = attr_sel, 4147 .argument2 = UIC_ARG_ATTR_TYPE(attr_set), 4148 .argument3 = mib_val, 4149 }; 4150 static const char *const action[] = { 4151 "dme-set", 4152 "dme-peer-set" 4153 }; 4154 const char *set = action[!!peer]; 4155 int ret; 4156 int retries = UFS_UIC_COMMAND_RETRIES; 4157 4158 do { 4159 /* for peer attributes we retry upon failure */ 4160 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4161 if (ret) 4162 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4163 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4164 } while (ret && peer && --retries); 4165 4166 if (ret) 4167 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4168 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4169 UFS_UIC_COMMAND_RETRIES - retries); 4170 4171 return ret; 4172 } 4173 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4174 4175 /** 4176 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4177 * @hba: per adapter instance 4178 * @attr_sel: uic command argument1 4179 * @mib_val: the value of the attribute as returned by the UIC command 4180 * @peer: indicate whether peer or local 4181 * 4182 * Return: 0 on success, non-zero value on failure. 4183 */ 4184 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4185 u32 *mib_val, u8 peer) 4186 { 4187 struct uic_command uic_cmd = { 4188 .command = peer ? UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET, 4189 .argument1 = attr_sel, 4190 }; 4191 static const char *const action[] = { 4192 "dme-get", 4193 "dme-peer-get" 4194 }; 4195 const char *get = action[!!peer]; 4196 int ret; 4197 int retries = UFS_UIC_COMMAND_RETRIES; 4198 struct ufs_pa_layer_attr orig_pwr_info; 4199 struct ufs_pa_layer_attr temp_pwr_info; 4200 bool pwr_mode_change = false; 4201 4202 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4203 orig_pwr_info = hba->pwr_info; 4204 temp_pwr_info = orig_pwr_info; 4205 4206 if (orig_pwr_info.pwr_tx == FAST_MODE || 4207 orig_pwr_info.pwr_rx == FAST_MODE) { 4208 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4209 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4210 pwr_mode_change = true; 4211 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4212 orig_pwr_info.pwr_rx == SLOW_MODE) { 4213 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4214 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4215 pwr_mode_change = true; 4216 } 4217 if (pwr_mode_change) { 4218 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4219 if (ret) 4220 goto out; 4221 } 4222 } 4223 4224 do { 4225 /* for peer attributes we retry upon failure */ 4226 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4227 if (ret) 4228 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4229 get, UIC_GET_ATTR_ID(attr_sel), ret); 4230 } while (ret && peer && --retries); 4231 4232 if (ret) 4233 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4234 get, UIC_GET_ATTR_ID(attr_sel), 4235 UFS_UIC_COMMAND_RETRIES - retries); 4236 4237 if (mib_val && !ret) 4238 *mib_val = uic_cmd.argument3; 4239 4240 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4241 && pwr_mode_change) 4242 ufshcd_change_power_mode(hba, &orig_pwr_info); 4243 out: 4244 return ret; 4245 } 4246 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4247 4248 /** 4249 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4250 * state) and waits for it to take effect. 4251 * 4252 * @hba: per adapter instance 4253 * @cmd: UIC command to execute 4254 * 4255 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4256 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4257 * and device UniPro link and hence it's final completion would be indicated by 4258 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4259 * addition to normal UIC command completion Status (UCCS). This function only 4260 * returns after the relevant status bits indicate the completion. 4261 * 4262 * Return: 0 on success, non-zero value on failure. 4263 */ 4264 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4265 { 4266 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4267 unsigned long flags; 4268 u8 status; 4269 int ret; 4270 bool reenable_intr = false; 4271 4272 mutex_lock(&hba->uic_cmd_mutex); 4273 ufshcd_add_delay_before_dme_cmd(hba); 4274 4275 spin_lock_irqsave(hba->host->host_lock, flags); 4276 if (ufshcd_is_link_broken(hba)) { 4277 ret = -ENOLINK; 4278 goto out_unlock; 4279 } 4280 hba->uic_async_done = &uic_async_done; 4281 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4282 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4283 /* 4284 * Make sure UIC command completion interrupt is disabled before 4285 * issuing UIC command. 4286 */ 4287 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 4288 reenable_intr = true; 4289 } 4290 spin_unlock_irqrestore(hba->host->host_lock, flags); 4291 ret = __ufshcd_send_uic_cmd(hba, cmd, false); 4292 if (ret) { 4293 dev_err(hba->dev, 4294 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4295 cmd->command, cmd->argument3, ret); 4296 goto out; 4297 } 4298 4299 if (!wait_for_completion_timeout(hba->uic_async_done, 4300 msecs_to_jiffies(uic_cmd_timeout))) { 4301 dev_err(hba->dev, 4302 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4303 cmd->command, cmd->argument3); 4304 4305 if (!cmd->cmd_active) { 4306 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4307 __func__); 4308 goto check_upmcrs; 4309 } 4310 4311 ret = -ETIMEDOUT; 4312 goto out; 4313 } 4314 4315 check_upmcrs: 4316 status = ufshcd_get_upmcrs(hba); 4317 if (status != PWR_LOCAL) { 4318 dev_err(hba->dev, 4319 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4320 cmd->command, status); 4321 ret = (status != PWR_OK) ? status : -1; 4322 } 4323 out: 4324 if (ret) { 4325 ufshcd_print_host_state(hba); 4326 ufshcd_print_pwr_info(hba); 4327 ufshcd_print_evt_hist(hba); 4328 } 4329 4330 spin_lock_irqsave(hba->host->host_lock, flags); 4331 hba->active_uic_cmd = NULL; 4332 hba->uic_async_done = NULL; 4333 if (reenable_intr) 4334 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4335 if (ret) { 4336 ufshcd_set_link_broken(hba); 4337 ufshcd_schedule_eh_work(hba); 4338 } 4339 out_unlock: 4340 spin_unlock_irqrestore(hba->host->host_lock, flags); 4341 mutex_unlock(&hba->uic_cmd_mutex); 4342 4343 return ret; 4344 } 4345 4346 /** 4347 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4348 * using DME_SET primitives. 4349 * @hba: per adapter instance 4350 * @mode: powr mode value 4351 * 4352 * Return: 0 on success, non-zero value on failure. 4353 */ 4354 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4355 { 4356 struct uic_command uic_cmd = { 4357 .command = UIC_CMD_DME_SET, 4358 .argument1 = UIC_ARG_MIB(PA_PWRMODE), 4359 .argument3 = mode, 4360 }; 4361 int ret; 4362 4363 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4364 ret = ufshcd_dme_set(hba, 4365 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4366 if (ret) { 4367 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4368 __func__, ret); 4369 goto out; 4370 } 4371 } 4372 4373 ufshcd_hold(hba); 4374 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4375 ufshcd_release(hba); 4376 4377 out: 4378 return ret; 4379 } 4380 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4381 4382 int ufshcd_link_recovery(struct ufs_hba *hba) 4383 { 4384 int ret; 4385 unsigned long flags; 4386 4387 spin_lock_irqsave(hba->host->host_lock, flags); 4388 hba->ufshcd_state = UFSHCD_STATE_RESET; 4389 ufshcd_set_eh_in_progress(hba); 4390 spin_unlock_irqrestore(hba->host->host_lock, flags); 4391 4392 /* Reset the attached device */ 4393 ufshcd_device_reset(hba); 4394 4395 ret = ufshcd_host_reset_and_restore(hba); 4396 4397 spin_lock_irqsave(hba->host->host_lock, flags); 4398 if (ret) 4399 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4400 ufshcd_clear_eh_in_progress(hba); 4401 spin_unlock_irqrestore(hba->host->host_lock, flags); 4402 4403 if (ret) 4404 dev_err(hba->dev, "%s: link recovery failed, err %d", 4405 __func__, ret); 4406 4407 return ret; 4408 } 4409 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4410 4411 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4412 { 4413 struct uic_command uic_cmd = { 4414 .command = UIC_CMD_DME_HIBER_ENTER, 4415 }; 4416 ktime_t start = ktime_get(); 4417 int ret; 4418 4419 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4420 4421 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4422 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4423 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4424 4425 if (ret) 4426 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4427 __func__, ret); 4428 else 4429 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4430 POST_CHANGE); 4431 4432 return ret; 4433 } 4434 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4435 4436 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4437 { 4438 struct uic_command uic_cmd = { 4439 .command = UIC_CMD_DME_HIBER_EXIT, 4440 }; 4441 int ret; 4442 ktime_t start = ktime_get(); 4443 4444 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4445 4446 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4447 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4448 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4449 4450 if (ret) { 4451 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4452 __func__, ret); 4453 } else { 4454 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4455 POST_CHANGE); 4456 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4457 hba->ufs_stats.hibern8_exit_cnt++; 4458 } 4459 4460 return ret; 4461 } 4462 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4463 4464 static void ufshcd_configure_auto_hibern8(struct ufs_hba *hba) 4465 { 4466 if (!ufshcd_is_auto_hibern8_supported(hba)) 4467 return; 4468 4469 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4470 } 4471 4472 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4473 { 4474 const u32 cur_ahit = READ_ONCE(hba->ahit); 4475 4476 if (!ufshcd_is_auto_hibern8_supported(hba) || cur_ahit == ahit) 4477 return; 4478 4479 WRITE_ONCE(hba->ahit, ahit); 4480 if (!pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4481 ufshcd_rpm_get_sync(hba); 4482 ufshcd_hold(hba); 4483 ufshcd_configure_auto_hibern8(hba); 4484 ufshcd_release(hba); 4485 ufshcd_rpm_put_sync(hba); 4486 } 4487 } 4488 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4489 4490 /** 4491 * ufshcd_init_pwr_info - setting the POR (power on reset) 4492 * values in hba power info 4493 * @hba: per-adapter instance 4494 */ 4495 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4496 { 4497 hba->pwr_info.gear_rx = UFS_PWM_G1; 4498 hba->pwr_info.gear_tx = UFS_PWM_G1; 4499 hba->pwr_info.lane_rx = UFS_LANE_1; 4500 hba->pwr_info.lane_tx = UFS_LANE_1; 4501 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4502 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4503 hba->pwr_info.hs_rate = 0; 4504 } 4505 4506 /** 4507 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4508 * @hba: per-adapter instance 4509 * 4510 * Return: 0 upon success; < 0 upon failure. 4511 */ 4512 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4513 { 4514 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4515 4516 if (hba->max_pwr_info.is_valid) 4517 return 0; 4518 4519 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4520 pwr_info->pwr_tx = FASTAUTO_MODE; 4521 pwr_info->pwr_rx = FASTAUTO_MODE; 4522 } else { 4523 pwr_info->pwr_tx = FAST_MODE; 4524 pwr_info->pwr_rx = FAST_MODE; 4525 } 4526 pwr_info->hs_rate = PA_HS_MODE_B; 4527 4528 /* Get the connected lane count */ 4529 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4530 &pwr_info->lane_rx); 4531 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4532 &pwr_info->lane_tx); 4533 4534 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4535 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4536 __func__, 4537 pwr_info->lane_rx, 4538 pwr_info->lane_tx); 4539 return -EINVAL; 4540 } 4541 4542 /* 4543 * First, get the maximum gears of HS speed. 4544 * If a zero value, it means there is no HSGEAR capability. 4545 * Then, get the maximum gears of PWM speed. 4546 */ 4547 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4548 if (!pwr_info->gear_rx) { 4549 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4550 &pwr_info->gear_rx); 4551 if (!pwr_info->gear_rx) { 4552 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4553 __func__, pwr_info->gear_rx); 4554 return -EINVAL; 4555 } 4556 pwr_info->pwr_rx = SLOW_MODE; 4557 } 4558 4559 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4560 &pwr_info->gear_tx); 4561 if (!pwr_info->gear_tx) { 4562 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4563 &pwr_info->gear_tx); 4564 if (!pwr_info->gear_tx) { 4565 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4566 __func__, pwr_info->gear_tx); 4567 return -EINVAL; 4568 } 4569 pwr_info->pwr_tx = SLOW_MODE; 4570 } 4571 4572 hba->max_pwr_info.is_valid = true; 4573 return 0; 4574 } 4575 4576 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4577 struct ufs_pa_layer_attr *pwr_mode) 4578 { 4579 int ret; 4580 4581 /* if already configured to the requested pwr_mode */ 4582 if (!hba->force_pmc && 4583 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4584 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4585 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4586 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4587 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4588 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4589 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4590 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4591 return 0; 4592 } 4593 4594 /* 4595 * Configure attributes for power mode change with below. 4596 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4597 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4598 * - PA_HSSERIES 4599 */ 4600 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4601 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4602 pwr_mode->lane_rx); 4603 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4604 pwr_mode->pwr_rx == FAST_MODE) 4605 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4606 else 4607 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4608 4609 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4610 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4611 pwr_mode->lane_tx); 4612 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4613 pwr_mode->pwr_tx == FAST_MODE) 4614 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4615 else 4616 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4617 4618 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4619 pwr_mode->pwr_tx == FASTAUTO_MODE || 4620 pwr_mode->pwr_rx == FAST_MODE || 4621 pwr_mode->pwr_tx == FAST_MODE) 4622 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4623 pwr_mode->hs_rate); 4624 4625 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4626 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4627 DL_FC0ProtectionTimeOutVal_Default); 4628 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4629 DL_TC0ReplayTimeOutVal_Default); 4630 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4631 DL_AFC0ReqTimeOutVal_Default); 4632 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4633 DL_FC1ProtectionTimeOutVal_Default); 4634 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4635 DL_TC1ReplayTimeOutVal_Default); 4636 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4637 DL_AFC1ReqTimeOutVal_Default); 4638 4639 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4640 DL_FC0ProtectionTimeOutVal_Default); 4641 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4642 DL_TC0ReplayTimeOutVal_Default); 4643 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4644 DL_AFC0ReqTimeOutVal_Default); 4645 } 4646 4647 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4648 | pwr_mode->pwr_tx); 4649 4650 if (ret) { 4651 dev_err(hba->dev, 4652 "%s: power mode change failed %d\n", __func__, ret); 4653 } else { 4654 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4655 pwr_mode); 4656 4657 memcpy(&hba->pwr_info, pwr_mode, 4658 sizeof(struct ufs_pa_layer_attr)); 4659 } 4660 4661 return ret; 4662 } 4663 4664 /** 4665 * ufshcd_config_pwr_mode - configure a new power mode 4666 * @hba: per-adapter instance 4667 * @desired_pwr_mode: desired power configuration 4668 * 4669 * Return: 0 upon success; < 0 upon failure. 4670 */ 4671 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4672 struct ufs_pa_layer_attr *desired_pwr_mode) 4673 { 4674 struct ufs_pa_layer_attr final_params = { 0 }; 4675 int ret; 4676 4677 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4678 desired_pwr_mode, &final_params); 4679 4680 if (ret) 4681 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4682 4683 ret = ufshcd_change_power_mode(hba, &final_params); 4684 4685 return ret; 4686 } 4687 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4688 4689 /** 4690 * ufshcd_complete_dev_init() - checks device readiness 4691 * @hba: per-adapter instance 4692 * 4693 * Set fDeviceInit flag and poll until device toggles it. 4694 * 4695 * Return: 0 upon success; < 0 upon failure. 4696 */ 4697 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4698 { 4699 int err; 4700 bool flag_res = true; 4701 ktime_t timeout; 4702 4703 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4704 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4705 if (err) { 4706 dev_err(hba->dev, 4707 "%s: setting fDeviceInit flag failed with error %d\n", 4708 __func__, err); 4709 goto out; 4710 } 4711 4712 /* Poll fDeviceInit flag to be cleared */ 4713 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4714 do { 4715 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4716 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4717 if (!flag_res) 4718 break; 4719 usleep_range(500, 1000); 4720 } while (ktime_before(ktime_get(), timeout)); 4721 4722 if (err) { 4723 dev_err(hba->dev, 4724 "%s: reading fDeviceInit flag failed with error %d\n", 4725 __func__, err); 4726 } else if (flag_res) { 4727 dev_err(hba->dev, 4728 "%s: fDeviceInit was not cleared by the device\n", 4729 __func__); 4730 err = -EBUSY; 4731 } 4732 out: 4733 return err; 4734 } 4735 4736 /** 4737 * ufshcd_make_hba_operational - Make UFS controller operational 4738 * @hba: per adapter instance 4739 * 4740 * To bring UFS host controller to operational state, 4741 * 1. Enable required interrupts 4742 * 2. Configure interrupt aggregation 4743 * 3. Program UTRL and UTMRL base address 4744 * 4. Configure run-stop-registers 4745 * 4746 * Return: 0 on success, non-zero value on failure. 4747 */ 4748 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4749 { 4750 int err = 0; 4751 u32 reg; 4752 4753 /* Enable required interrupts */ 4754 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4755 4756 /* Configure interrupt aggregation */ 4757 if (ufshcd_is_intr_aggr_allowed(hba)) 4758 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4759 else 4760 ufshcd_disable_intr_aggr(hba); 4761 4762 /* Configure UTRL and UTMRL base address registers */ 4763 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4764 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4765 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4766 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4767 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4768 REG_UTP_TASK_REQ_LIST_BASE_L); 4769 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4770 REG_UTP_TASK_REQ_LIST_BASE_H); 4771 4772 /* 4773 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4774 */ 4775 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4776 if (!(ufshcd_get_lists_status(reg))) { 4777 ufshcd_enable_run_stop_reg(hba); 4778 } else { 4779 dev_err(hba->dev, 4780 "Host controller not ready to process requests"); 4781 err = -EIO; 4782 } 4783 4784 return err; 4785 } 4786 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4787 4788 /** 4789 * ufshcd_hba_stop - Send controller to reset state 4790 * @hba: per adapter instance 4791 */ 4792 void ufshcd_hba_stop(struct ufs_hba *hba) 4793 { 4794 unsigned long flags; 4795 int err; 4796 4797 /* 4798 * Obtain the host lock to prevent that the controller is disabled 4799 * while the UFS interrupt handler is active on another CPU. 4800 */ 4801 spin_lock_irqsave(hba->host->host_lock, flags); 4802 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4803 spin_unlock_irqrestore(hba->host->host_lock, flags); 4804 4805 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4806 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4807 10, 1); 4808 if (err) 4809 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4810 } 4811 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4812 4813 /** 4814 * ufshcd_hba_execute_hce - initialize the controller 4815 * @hba: per adapter instance 4816 * 4817 * The controller resets itself and controller firmware initialization 4818 * sequence kicks off. When controller is ready it will set 4819 * the Host Controller Enable bit to 1. 4820 * 4821 * Return: 0 on success, non-zero value on failure. 4822 */ 4823 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4824 { 4825 int retry_outer = 3; 4826 int retry_inner; 4827 4828 start: 4829 if (ufshcd_is_hba_active(hba)) 4830 /* change controller state to "reset state" */ 4831 ufshcd_hba_stop(hba); 4832 4833 /* UniPro link is disabled at this point */ 4834 ufshcd_set_link_off(hba); 4835 4836 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4837 4838 /* start controller initialization sequence */ 4839 ufshcd_hba_start(hba); 4840 4841 /* 4842 * To initialize a UFS host controller HCE bit must be set to 1. 4843 * During initialization the HCE bit value changes from 1->0->1. 4844 * When the host controller completes initialization sequence 4845 * it sets the value of HCE bit to 1. The same HCE bit is read back 4846 * to check if the controller has completed initialization sequence. 4847 * So without this delay the value HCE = 1, set in the previous 4848 * instruction might be read back. 4849 * This delay can be changed based on the controller. 4850 */ 4851 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4852 4853 /* wait for the host controller to complete initialization */ 4854 retry_inner = 50; 4855 while (!ufshcd_is_hba_active(hba)) { 4856 if (retry_inner) { 4857 retry_inner--; 4858 } else { 4859 dev_err(hba->dev, 4860 "Controller enable failed\n"); 4861 if (retry_outer) { 4862 retry_outer--; 4863 goto start; 4864 } 4865 return -EIO; 4866 } 4867 usleep_range(1000, 1100); 4868 } 4869 4870 /* enable UIC related interrupts */ 4871 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4872 4873 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4874 4875 return 0; 4876 } 4877 4878 int ufshcd_hba_enable(struct ufs_hba *hba) 4879 { 4880 int ret; 4881 4882 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4883 ufshcd_set_link_off(hba); 4884 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4885 4886 /* enable UIC related interrupts */ 4887 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4888 ret = ufshcd_dme_reset(hba); 4889 if (ret) { 4890 dev_err(hba->dev, "DME_RESET failed\n"); 4891 return ret; 4892 } 4893 4894 ret = ufshcd_dme_enable(hba); 4895 if (ret) { 4896 dev_err(hba->dev, "Enabling DME failed\n"); 4897 return ret; 4898 } 4899 4900 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4901 } else { 4902 ret = ufshcd_hba_execute_hce(hba); 4903 } 4904 4905 return ret; 4906 } 4907 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4908 4909 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4910 { 4911 int tx_lanes = 0, i, err = 0; 4912 4913 if (!peer) 4914 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4915 &tx_lanes); 4916 else 4917 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4918 &tx_lanes); 4919 for (i = 0; i < tx_lanes; i++) { 4920 if (!peer) 4921 err = ufshcd_dme_set(hba, 4922 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4923 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4924 0); 4925 else 4926 err = ufshcd_dme_peer_set(hba, 4927 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4928 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4929 0); 4930 if (err) { 4931 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4932 __func__, peer, i, err); 4933 break; 4934 } 4935 } 4936 4937 return err; 4938 } 4939 4940 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4941 { 4942 return ufshcd_disable_tx_lcc(hba, true); 4943 } 4944 4945 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4946 { 4947 struct ufs_event_hist *e; 4948 4949 if (id >= UFS_EVT_CNT) 4950 return; 4951 4952 e = &hba->ufs_stats.event[id]; 4953 e->val[e->pos] = val; 4954 e->tstamp[e->pos] = local_clock(); 4955 e->cnt += 1; 4956 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4957 4958 ufshcd_vops_event_notify(hba, id, &val); 4959 } 4960 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4961 4962 /** 4963 * ufshcd_link_startup - Initialize unipro link startup 4964 * @hba: per adapter instance 4965 * 4966 * Return: 0 for success, non-zero in case of failure. 4967 */ 4968 static int ufshcd_link_startup(struct ufs_hba *hba) 4969 { 4970 int ret; 4971 int retries = DME_LINKSTARTUP_RETRIES; 4972 bool link_startup_again = false; 4973 4974 /* 4975 * If UFS device isn't active then we will have to issue link startup 4976 * 2 times to make sure the device state move to active. 4977 */ 4978 if (!ufshcd_is_ufs_dev_active(hba)) 4979 link_startup_again = true; 4980 4981 link_startup: 4982 do { 4983 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4984 4985 ret = ufshcd_dme_link_startup(hba); 4986 4987 /* check if device is detected by inter-connect layer */ 4988 if (!ret && !ufshcd_is_device_present(hba)) { 4989 ufshcd_update_evt_hist(hba, 4990 UFS_EVT_LINK_STARTUP_FAIL, 4991 0); 4992 dev_err(hba->dev, "%s: Device not present\n", __func__); 4993 ret = -ENXIO; 4994 goto out; 4995 } 4996 4997 /* 4998 * DME link lost indication is only received when link is up, 4999 * but we can't be sure if the link is up until link startup 5000 * succeeds. So reset the local Uni-Pro and try again. 5001 */ 5002 if (ret && retries && ufshcd_hba_enable(hba)) { 5003 ufshcd_update_evt_hist(hba, 5004 UFS_EVT_LINK_STARTUP_FAIL, 5005 (u32)ret); 5006 goto out; 5007 } 5008 } while (ret && retries--); 5009 5010 if (ret) { 5011 /* failed to get the link up... retire */ 5012 ufshcd_update_evt_hist(hba, 5013 UFS_EVT_LINK_STARTUP_FAIL, 5014 (u32)ret); 5015 goto out; 5016 } 5017 5018 if (link_startup_again) { 5019 link_startup_again = false; 5020 retries = DME_LINKSTARTUP_RETRIES; 5021 goto link_startup; 5022 } 5023 5024 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 5025 ufshcd_init_pwr_info(hba); 5026 ufshcd_print_pwr_info(hba); 5027 5028 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 5029 ret = ufshcd_disable_device_tx_lcc(hba); 5030 if (ret) 5031 goto out; 5032 } 5033 5034 /* Include any host controller configuration via UIC commands */ 5035 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 5036 if (ret) 5037 goto out; 5038 5039 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 5040 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 5041 ret = ufshcd_make_hba_operational(hba); 5042 out: 5043 if (ret) { 5044 dev_err(hba->dev, "link startup failed %d\n", ret); 5045 ufshcd_print_host_state(hba); 5046 ufshcd_print_pwr_info(hba); 5047 ufshcd_print_evt_hist(hba); 5048 } 5049 return ret; 5050 } 5051 5052 /** 5053 * ufshcd_verify_dev_init() - Verify device initialization 5054 * @hba: per-adapter instance 5055 * 5056 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 5057 * device Transport Protocol (UTP) layer is ready after a reset. 5058 * If the UTP layer at the device side is not initialized, it may 5059 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 5060 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 5061 * 5062 * Return: 0 upon success; < 0 upon failure. 5063 */ 5064 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 5065 { 5066 int err = 0; 5067 int retries; 5068 5069 ufshcd_dev_man_lock(hba); 5070 5071 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 5072 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 5073 hba->nop_out_timeout); 5074 5075 if (!err || err == -ETIMEDOUT) 5076 break; 5077 5078 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 5079 } 5080 5081 ufshcd_dev_man_unlock(hba); 5082 5083 if (err) 5084 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 5085 return err; 5086 } 5087 5088 /** 5089 * ufshcd_setup_links - associate link b/w device wlun and other luns 5090 * @sdev: pointer to SCSI device 5091 * @hba: pointer to ufs hba 5092 */ 5093 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 5094 { 5095 struct device_link *link; 5096 5097 /* 5098 * Device wlun is the supplier & rest of the luns are consumers. 5099 * This ensures that device wlun suspends after all other luns. 5100 */ 5101 if (hba->ufs_device_wlun) { 5102 link = device_link_add(&sdev->sdev_gendev, 5103 &hba->ufs_device_wlun->sdev_gendev, 5104 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 5105 if (!link) { 5106 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 5107 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 5108 return; 5109 } 5110 hba->luns_avail--; 5111 /* Ignore REPORT_LUN wlun probing */ 5112 if (hba->luns_avail == 1) { 5113 ufshcd_rpm_put(hba); 5114 return; 5115 } 5116 } else { 5117 /* 5118 * Device wlun is probed. The assumption is that WLUNs are 5119 * scanned before other LUNs. 5120 */ 5121 hba->luns_avail--; 5122 } 5123 } 5124 5125 /** 5126 * ufshcd_lu_init - Initialize the relevant parameters of the LU 5127 * @hba: per-adapter instance 5128 * @sdev: pointer to SCSI device 5129 */ 5130 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 5131 { 5132 int len = QUERY_DESC_MAX_SIZE; 5133 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 5134 u8 lun_qdepth = hba->nutrs; 5135 u8 *desc_buf; 5136 int ret; 5137 5138 desc_buf = kzalloc(len, GFP_KERNEL); 5139 if (!desc_buf) 5140 goto set_qdepth; 5141 5142 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5143 if (ret < 0) { 5144 if (ret == -EOPNOTSUPP) 5145 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5146 lun_qdepth = 1; 5147 kfree(desc_buf); 5148 goto set_qdepth; 5149 } 5150 5151 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5152 /* 5153 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5154 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5155 */ 5156 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5157 } 5158 /* 5159 * According to UFS device specification, the write protection mode is only supported by 5160 * normal LU, not supported by WLUN. 5161 */ 5162 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5163 !hba->dev_info.is_lu_power_on_wp && 5164 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5165 hba->dev_info.is_lu_power_on_wp = true; 5166 5167 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5168 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5169 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5170 hba->dev_info.b_advanced_rpmb_en = true; 5171 5172 5173 kfree(desc_buf); 5174 set_qdepth: 5175 /* 5176 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5177 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5178 */ 5179 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5180 scsi_change_queue_depth(sdev, lun_qdepth); 5181 } 5182 5183 /** 5184 * ufshcd_slave_alloc - handle initial SCSI device configurations 5185 * @sdev: pointer to SCSI device 5186 * 5187 * Return: success. 5188 */ 5189 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5190 { 5191 struct ufs_hba *hba; 5192 5193 hba = shost_priv(sdev->host); 5194 5195 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5196 sdev->use_10_for_ms = 1; 5197 5198 /* DBD field should be set to 1 in mode sense(10) */ 5199 sdev->set_dbd_for_ms = 1; 5200 5201 /* allow SCSI layer to restart the device in case of errors */ 5202 sdev->allow_restart = 1; 5203 5204 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5205 sdev->no_report_opcodes = 1; 5206 5207 /* WRITE_SAME command is not supported */ 5208 sdev->no_write_same = 1; 5209 5210 ufshcd_lu_init(hba, sdev); 5211 5212 ufshcd_setup_links(hba, sdev); 5213 5214 return 0; 5215 } 5216 5217 /** 5218 * ufshcd_change_queue_depth - change queue depth 5219 * @sdev: pointer to SCSI device 5220 * @depth: required depth to set 5221 * 5222 * Change queue depth and make sure the max. limits are not crossed. 5223 * 5224 * Return: new queue depth. 5225 */ 5226 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5227 { 5228 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5229 } 5230 5231 /** 5232 * ufshcd_device_configure - adjust SCSI device configurations 5233 * @sdev: pointer to SCSI device 5234 * @lim: queue limits 5235 * 5236 * Return: 0 (success). 5237 */ 5238 static int ufshcd_device_configure(struct scsi_device *sdev, 5239 struct queue_limits *lim) 5240 { 5241 struct ufs_hba *hba = shost_priv(sdev->host); 5242 struct request_queue *q = sdev->request_queue; 5243 5244 lim->dma_pad_mask = PRDT_DATA_BYTE_COUNT_PAD - 1; 5245 5246 /* 5247 * Block runtime-pm until all consumers are added. 5248 * Refer ufshcd_setup_links(). 5249 */ 5250 if (is_device_wlun(sdev)) 5251 pm_runtime_get_noresume(&sdev->sdev_gendev); 5252 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5253 sdev->rpm_autosuspend = 1; 5254 /* 5255 * Do not print messages during runtime PM to avoid never-ending cycles 5256 * of messages written back to storage by user space causing runtime 5257 * resume, causing more messages and so on. 5258 */ 5259 sdev->silence_suspend = 1; 5260 5261 ufshcd_crypto_register(hba, q); 5262 5263 return 0; 5264 } 5265 5266 /** 5267 * ufshcd_slave_destroy - remove SCSI device configurations 5268 * @sdev: pointer to SCSI device 5269 */ 5270 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5271 { 5272 struct ufs_hba *hba; 5273 unsigned long flags; 5274 5275 hba = shost_priv(sdev->host); 5276 5277 /* Drop the reference as it won't be needed anymore */ 5278 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5279 spin_lock_irqsave(hba->host->host_lock, flags); 5280 hba->ufs_device_wlun = NULL; 5281 spin_unlock_irqrestore(hba->host->host_lock, flags); 5282 } else if (hba->ufs_device_wlun) { 5283 struct device *supplier = NULL; 5284 5285 /* Ensure UFS Device WLUN exists and does not disappear */ 5286 spin_lock_irqsave(hba->host->host_lock, flags); 5287 if (hba->ufs_device_wlun) { 5288 supplier = &hba->ufs_device_wlun->sdev_gendev; 5289 get_device(supplier); 5290 } 5291 spin_unlock_irqrestore(hba->host->host_lock, flags); 5292 5293 if (supplier) { 5294 /* 5295 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5296 * device will not have been registered but can still 5297 * have a device link holding a reference to the device. 5298 */ 5299 device_link_remove(&sdev->sdev_gendev, supplier); 5300 put_device(supplier); 5301 } 5302 } 5303 } 5304 5305 /** 5306 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5307 * @lrbp: pointer to local reference block of completed command 5308 * @scsi_status: SCSI command status 5309 * 5310 * Return: value base on SCSI command status. 5311 */ 5312 static inline int 5313 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5314 { 5315 int result = 0; 5316 5317 switch (scsi_status) { 5318 case SAM_STAT_CHECK_CONDITION: 5319 ufshcd_copy_sense_data(lrbp); 5320 fallthrough; 5321 case SAM_STAT_GOOD: 5322 result |= DID_OK << 16 | scsi_status; 5323 break; 5324 case SAM_STAT_TASK_SET_FULL: 5325 case SAM_STAT_BUSY: 5326 case SAM_STAT_TASK_ABORTED: 5327 ufshcd_copy_sense_data(lrbp); 5328 result |= scsi_status; 5329 break; 5330 default: 5331 result |= DID_ERROR << 16; 5332 break; 5333 } /* end of switch */ 5334 5335 return result; 5336 } 5337 5338 /** 5339 * ufshcd_transfer_rsp_status - Get overall status of the response 5340 * @hba: per adapter instance 5341 * @lrbp: pointer to local reference block of completed command 5342 * @cqe: pointer to the completion queue entry 5343 * 5344 * Return: result of the command to notify SCSI midlayer. 5345 */ 5346 static inline int 5347 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5348 struct cq_entry *cqe) 5349 { 5350 int result = 0; 5351 int scsi_status; 5352 enum utp_ocs ocs; 5353 u8 upiu_flags; 5354 u32 resid; 5355 5356 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5357 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5358 /* 5359 * Test !overflow instead of underflow to support UFS devices that do 5360 * not set either flag. 5361 */ 5362 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5363 scsi_set_resid(lrbp->cmd, resid); 5364 5365 /* overall command status of utrd */ 5366 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5367 5368 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5369 if (lrbp->ucd_rsp_ptr->header.response || 5370 lrbp->ucd_rsp_ptr->header.status) 5371 ocs = OCS_SUCCESS; 5372 } 5373 5374 switch (ocs) { 5375 case OCS_SUCCESS: 5376 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5377 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5378 case UPIU_TRANSACTION_RESPONSE: 5379 /* 5380 * get the result based on SCSI status response 5381 * to notify the SCSI midlayer of the command status 5382 */ 5383 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5384 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5385 5386 /* 5387 * Currently we are only supporting BKOPs exception 5388 * events hence we can ignore BKOPs exception event 5389 * during power management callbacks. BKOPs exception 5390 * event is not expected to be raised in runtime suspend 5391 * callback as it allows the urgent bkops. 5392 * During system suspend, we are anyway forcefully 5393 * disabling the bkops and if urgent bkops is needed 5394 * it will be enabled on system resume. Long term 5395 * solution could be to abort the system suspend if 5396 * UFS device needs urgent BKOPs. 5397 */ 5398 if (!hba->pm_op_in_progress && 5399 !ufshcd_eh_in_progress(hba) && 5400 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5401 /* Flushed in suspend */ 5402 schedule_work(&hba->eeh_work); 5403 break; 5404 case UPIU_TRANSACTION_REJECT_UPIU: 5405 /* TODO: handle Reject UPIU Response */ 5406 result = DID_ERROR << 16; 5407 dev_err(hba->dev, 5408 "Reject UPIU not fully implemented\n"); 5409 break; 5410 default: 5411 dev_err(hba->dev, 5412 "Unexpected request response code = %x\n", 5413 result); 5414 result = DID_ERROR << 16; 5415 break; 5416 } 5417 break; 5418 case OCS_ABORTED: 5419 result |= DID_ABORT << 16; 5420 break; 5421 case OCS_INVALID_COMMAND_STATUS: 5422 result |= DID_REQUEUE << 16; 5423 break; 5424 case OCS_INVALID_CMD_TABLE_ATTR: 5425 case OCS_INVALID_PRDT_ATTR: 5426 case OCS_MISMATCH_DATA_BUF_SIZE: 5427 case OCS_MISMATCH_RESP_UPIU_SIZE: 5428 case OCS_PEER_COMM_FAILURE: 5429 case OCS_FATAL_ERROR: 5430 case OCS_DEVICE_FATAL_ERROR: 5431 case OCS_INVALID_CRYPTO_CONFIG: 5432 case OCS_GENERAL_CRYPTO_ERROR: 5433 default: 5434 result |= DID_ERROR << 16; 5435 dev_err(hba->dev, 5436 "OCS error from controller = %x for tag %d\n", 5437 ocs, lrbp->task_tag); 5438 ufshcd_print_evt_hist(hba); 5439 ufshcd_print_host_state(hba); 5440 break; 5441 } /* end of switch */ 5442 5443 if ((host_byte(result) != DID_OK) && 5444 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5445 ufshcd_print_tr(hba, lrbp->task_tag, true); 5446 return result; 5447 } 5448 5449 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5450 u32 intr_mask) 5451 { 5452 if (!ufshcd_is_auto_hibern8_supported(hba) || 5453 !ufshcd_is_auto_hibern8_enabled(hba)) 5454 return false; 5455 5456 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5457 return false; 5458 5459 if (hba->active_uic_cmd && 5460 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5461 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5462 return false; 5463 5464 return true; 5465 } 5466 5467 /** 5468 * ufshcd_uic_cmd_compl - handle completion of uic command 5469 * @hba: per adapter instance 5470 * @intr_status: interrupt status generated by the controller 5471 * 5472 * Return: 5473 * IRQ_HANDLED - If interrupt is valid 5474 * IRQ_NONE - If invalid interrupt 5475 */ 5476 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5477 { 5478 irqreturn_t retval = IRQ_NONE; 5479 5480 spin_lock(hba->host->host_lock); 5481 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5482 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5483 5484 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { 5485 hba->active_uic_cmd->argument2 |= 5486 ufshcd_get_uic_cmd_result(hba); 5487 hba->active_uic_cmd->argument3 = 5488 ufshcd_get_dme_attr_val(hba); 5489 if (!hba->uic_async_done) 5490 hba->active_uic_cmd->cmd_active = 0; 5491 complete(&hba->active_uic_cmd->done); 5492 retval = IRQ_HANDLED; 5493 } 5494 5495 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { 5496 hba->active_uic_cmd->cmd_active = 0; 5497 complete(hba->uic_async_done); 5498 retval = IRQ_HANDLED; 5499 } 5500 5501 if (retval == IRQ_HANDLED) 5502 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd, 5503 UFS_CMD_COMP); 5504 spin_unlock(hba->host->host_lock); 5505 return retval; 5506 } 5507 5508 /* Release the resources allocated for processing a SCSI command. */ 5509 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5510 struct ufshcd_lrb *lrbp) 5511 { 5512 struct scsi_cmnd *cmd = lrbp->cmd; 5513 5514 scsi_dma_unmap(cmd); 5515 ufshcd_crypto_clear_prdt(hba, lrbp); 5516 ufshcd_release(hba); 5517 ufshcd_clk_scaling_update_busy(hba); 5518 } 5519 5520 /** 5521 * ufshcd_compl_one_cqe - handle a completion queue entry 5522 * @hba: per adapter instance 5523 * @task_tag: the task tag of the request to be completed 5524 * @cqe: pointer to the completion queue entry 5525 */ 5526 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5527 struct cq_entry *cqe) 5528 { 5529 struct ufshcd_lrb *lrbp; 5530 struct scsi_cmnd *cmd; 5531 enum utp_ocs ocs; 5532 5533 lrbp = &hba->lrb[task_tag]; 5534 lrbp->compl_time_stamp = ktime_get(); 5535 cmd = lrbp->cmd; 5536 if (cmd) { 5537 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5538 ufshcd_update_monitor(hba, lrbp); 5539 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5540 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5541 ufshcd_release_scsi_cmd(hba, lrbp); 5542 /* Do not touch lrbp after scsi done */ 5543 scsi_done(cmd); 5544 } else if (hba->dev_cmd.complete) { 5545 if (cqe) { 5546 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5547 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5548 } 5549 complete(hba->dev_cmd.complete); 5550 } 5551 } 5552 5553 /** 5554 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5555 * @hba: per adapter instance 5556 * @completed_reqs: bitmask that indicates which requests to complete 5557 */ 5558 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5559 unsigned long completed_reqs) 5560 { 5561 int tag; 5562 5563 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5564 ufshcd_compl_one_cqe(hba, tag, NULL); 5565 } 5566 5567 /* Any value that is not an existing queue number is fine for this constant. */ 5568 enum { 5569 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5570 }; 5571 5572 static void ufshcd_clear_polled(struct ufs_hba *hba, 5573 unsigned long *completed_reqs) 5574 { 5575 int tag; 5576 5577 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5578 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5579 5580 if (!cmd) 5581 continue; 5582 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5583 __clear_bit(tag, completed_reqs); 5584 } 5585 } 5586 5587 /* 5588 * Return: > 0 if one or more commands have been completed or 0 if no 5589 * requests have been completed. 5590 */ 5591 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5592 { 5593 struct ufs_hba *hba = shost_priv(shost); 5594 unsigned long completed_reqs, flags; 5595 u32 tr_doorbell; 5596 struct ufs_hw_queue *hwq; 5597 5598 if (hba->mcq_enabled) { 5599 hwq = &hba->uhq[queue_num]; 5600 5601 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5602 } 5603 5604 spin_lock_irqsave(&hba->outstanding_lock, flags); 5605 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5606 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5607 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5608 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5609 hba->outstanding_reqs); 5610 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5611 /* Do not complete polled requests from interrupt context. */ 5612 ufshcd_clear_polled(hba, &completed_reqs); 5613 } 5614 hba->outstanding_reqs &= ~completed_reqs; 5615 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5616 5617 if (completed_reqs) 5618 __ufshcd_transfer_req_compl(hba, completed_reqs); 5619 5620 return completed_reqs != 0; 5621 } 5622 5623 /** 5624 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5625 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5626 * to complete the pending transfers and free the resources associated with 5627 * the scsi command. 5628 * 5629 * @hba: per adapter instance 5630 * @force_compl: This flag is set to true when invoked 5631 * from ufshcd_host_reset_and_restore() in which case it requires special 5632 * handling because the host controller has been reset by ufshcd_hba_stop(). 5633 */ 5634 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5635 bool force_compl) 5636 { 5637 struct ufs_hw_queue *hwq; 5638 struct ufshcd_lrb *lrbp; 5639 struct scsi_cmnd *cmd; 5640 unsigned long flags; 5641 int tag; 5642 5643 for (tag = 0; tag < hba->nutrs; tag++) { 5644 lrbp = &hba->lrb[tag]; 5645 cmd = lrbp->cmd; 5646 if (!ufshcd_cmd_inflight(cmd) || 5647 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5648 continue; 5649 5650 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 5651 5652 if (force_compl) { 5653 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5654 /* 5655 * For those cmds of which the cqes are not present 5656 * in the cq, complete them explicitly. 5657 */ 5658 spin_lock_irqsave(&hwq->cq_lock, flags); 5659 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5660 set_host_byte(cmd, DID_REQUEUE); 5661 ufshcd_release_scsi_cmd(hba, lrbp); 5662 scsi_done(cmd); 5663 } 5664 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5665 } else { 5666 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5667 } 5668 } 5669 } 5670 5671 /** 5672 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5673 * @hba: per adapter instance 5674 * 5675 * Return: 5676 * IRQ_HANDLED - If interrupt is valid 5677 * IRQ_NONE - If invalid interrupt 5678 */ 5679 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5680 { 5681 /* Resetting interrupt aggregation counters first and reading the 5682 * DOOR_BELL afterward allows us to handle all the completed requests. 5683 * In order to prevent other interrupts starvation the DB is read once 5684 * after reset. The down side of this solution is the possibility of 5685 * false interrupt if device completes another request after resetting 5686 * aggregation and before reading the DB. 5687 */ 5688 if (ufshcd_is_intr_aggr_allowed(hba) && 5689 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5690 ufshcd_reset_intr_aggr(hba); 5691 5692 if (ufs_fail_completion(hba)) 5693 return IRQ_HANDLED; 5694 5695 /* 5696 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5697 * do not want polling to trigger spurious interrupt complaints. 5698 */ 5699 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5700 5701 return IRQ_HANDLED; 5702 } 5703 5704 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5705 { 5706 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5707 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5708 &ee_ctrl_mask); 5709 } 5710 5711 int ufshcd_write_ee_control(struct ufs_hba *hba) 5712 { 5713 int err; 5714 5715 mutex_lock(&hba->ee_ctrl_mutex); 5716 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5717 mutex_unlock(&hba->ee_ctrl_mutex); 5718 if (err) 5719 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5720 __func__, err); 5721 return err; 5722 } 5723 5724 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5725 const u16 *other_mask, u16 set, u16 clr) 5726 { 5727 u16 new_mask, ee_ctrl_mask; 5728 int err = 0; 5729 5730 mutex_lock(&hba->ee_ctrl_mutex); 5731 new_mask = (*mask & ~clr) | set; 5732 ee_ctrl_mask = new_mask | *other_mask; 5733 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5734 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5735 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5736 if (!err) { 5737 hba->ee_ctrl_mask = ee_ctrl_mask; 5738 *mask = new_mask; 5739 } 5740 mutex_unlock(&hba->ee_ctrl_mutex); 5741 return err; 5742 } 5743 5744 /** 5745 * ufshcd_disable_ee - disable exception event 5746 * @hba: per-adapter instance 5747 * @mask: exception event to disable 5748 * 5749 * Disables exception event in the device so that the EVENT_ALERT 5750 * bit is not set. 5751 * 5752 * Return: zero on success, non-zero error value on failure. 5753 */ 5754 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5755 { 5756 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5757 } 5758 5759 /** 5760 * ufshcd_enable_ee - enable exception event 5761 * @hba: per-adapter instance 5762 * @mask: exception event to enable 5763 * 5764 * Enable corresponding exception event in the device to allow 5765 * device to alert host in critical scenarios. 5766 * 5767 * Return: zero on success, non-zero error value on failure. 5768 */ 5769 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5770 { 5771 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5772 } 5773 5774 /** 5775 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5776 * @hba: per-adapter instance 5777 * 5778 * Allow device to manage background operations on its own. Enabling 5779 * this might lead to inconsistent latencies during normal data transfers 5780 * as the device is allowed to manage its own way of handling background 5781 * operations. 5782 * 5783 * Return: zero on success, non-zero on failure. 5784 */ 5785 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5786 { 5787 int err = 0; 5788 5789 if (hba->auto_bkops_enabled) 5790 goto out; 5791 5792 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5793 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5794 if (err) { 5795 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5796 __func__, err); 5797 goto out; 5798 } 5799 5800 hba->auto_bkops_enabled = true; 5801 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5802 5803 /* No need of URGENT_BKOPS exception from the device */ 5804 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5805 if (err) 5806 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5807 __func__, err); 5808 out: 5809 return err; 5810 } 5811 5812 /** 5813 * ufshcd_disable_auto_bkops - block device in doing background operations 5814 * @hba: per-adapter instance 5815 * 5816 * Disabling background operations improves command response latency but 5817 * has drawback of device moving into critical state where the device is 5818 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5819 * host is idle so that BKOPS are managed effectively without any negative 5820 * impacts. 5821 * 5822 * Return: zero on success, non-zero on failure. 5823 */ 5824 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5825 { 5826 int err = 0; 5827 5828 if (!hba->auto_bkops_enabled) 5829 goto out; 5830 5831 /* 5832 * If host assisted BKOPs is to be enabled, make sure 5833 * urgent bkops exception is allowed. 5834 */ 5835 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5836 if (err) { 5837 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5838 __func__, err); 5839 goto out; 5840 } 5841 5842 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5843 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5844 if (err) { 5845 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5846 __func__, err); 5847 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5848 goto out; 5849 } 5850 5851 hba->auto_bkops_enabled = false; 5852 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5853 hba->is_urgent_bkops_lvl_checked = false; 5854 out: 5855 return err; 5856 } 5857 5858 /** 5859 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5860 * @hba: per adapter instance 5861 * 5862 * After a device reset the device may toggle the BKOPS_EN flag 5863 * to default value. The s/w tracking variables should be updated 5864 * as well. This function would change the auto-bkops state based on 5865 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5866 */ 5867 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5868 { 5869 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5870 hba->auto_bkops_enabled = false; 5871 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5872 ufshcd_enable_auto_bkops(hba); 5873 } else { 5874 hba->auto_bkops_enabled = true; 5875 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5876 ufshcd_disable_auto_bkops(hba); 5877 } 5878 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5879 hba->is_urgent_bkops_lvl_checked = false; 5880 } 5881 5882 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5883 { 5884 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5885 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5886 } 5887 5888 /** 5889 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5890 * @hba: per-adapter instance 5891 * 5892 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5893 * flag in the device to permit background operations if the device 5894 * bkops_status is greater than or equal to the "hba->urgent_bkops_lvl", 5895 * disable otherwise. 5896 * 5897 * Return: 0 for success, non-zero in case of failure. 5898 * 5899 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5900 * to know whether auto bkops is enabled or disabled after this function 5901 * returns control to it. 5902 */ 5903 static int ufshcd_bkops_ctrl(struct ufs_hba *hba) 5904 { 5905 enum bkops_status status = hba->urgent_bkops_lvl; 5906 u32 curr_status = 0; 5907 int err; 5908 5909 err = ufshcd_get_bkops_status(hba, &curr_status); 5910 if (err) { 5911 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5912 __func__, err); 5913 goto out; 5914 } else if (curr_status > BKOPS_STATUS_MAX) { 5915 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5916 __func__, curr_status); 5917 err = -EINVAL; 5918 goto out; 5919 } 5920 5921 if (curr_status >= status) 5922 err = ufshcd_enable_auto_bkops(hba); 5923 else 5924 err = ufshcd_disable_auto_bkops(hba); 5925 out: 5926 return err; 5927 } 5928 5929 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5930 { 5931 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5932 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5933 } 5934 5935 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5936 { 5937 int err; 5938 u32 curr_status = 0; 5939 5940 if (hba->is_urgent_bkops_lvl_checked) 5941 goto enable_auto_bkops; 5942 5943 err = ufshcd_get_bkops_status(hba, &curr_status); 5944 if (err) { 5945 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5946 __func__, err); 5947 goto out; 5948 } 5949 5950 /* 5951 * We are seeing that some devices are raising the urgent bkops 5952 * exception events even when BKOPS status doesn't indicate performace 5953 * impacted or critical. Handle these device by determining their urgent 5954 * bkops status at runtime. 5955 */ 5956 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5957 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5958 __func__, curr_status); 5959 /* update the current status as the urgent bkops level */ 5960 hba->urgent_bkops_lvl = curr_status; 5961 hba->is_urgent_bkops_lvl_checked = true; 5962 } 5963 5964 enable_auto_bkops: 5965 err = ufshcd_enable_auto_bkops(hba); 5966 out: 5967 if (err < 0) 5968 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5969 __func__, err); 5970 } 5971 5972 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5973 { 5974 u32 value; 5975 5976 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5977 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 5978 return; 5979 5980 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 5981 5982 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 5983 5984 /* 5985 * A placeholder for the platform vendors to add whatever additional 5986 * steps required 5987 */ 5988 } 5989 5990 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 5991 { 5992 u8 index; 5993 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 5994 UPIU_QUERY_OPCODE_CLEAR_FLAG; 5995 5996 index = ufshcd_wb_get_query_index(hba); 5997 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 5998 } 5999 6000 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 6001 { 6002 int ret; 6003 6004 if (!ufshcd_is_wb_allowed(hba) || 6005 hba->dev_info.wb_enabled == enable) 6006 return 0; 6007 6008 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 6009 if (ret) { 6010 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 6011 __func__, enable ? "enabling" : "disabling", ret); 6012 return ret; 6013 } 6014 6015 hba->dev_info.wb_enabled = enable; 6016 dev_dbg(hba->dev, "%s: Write Booster %s\n", 6017 __func__, enable ? "enabled" : "disabled"); 6018 6019 return ret; 6020 } 6021 6022 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 6023 bool enable) 6024 { 6025 int ret; 6026 6027 ret = __ufshcd_wb_toggle(hba, enable, 6028 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 6029 if (ret) { 6030 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 6031 __func__, enable ? "enabling" : "disabling", ret); 6032 return; 6033 } 6034 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 6035 __func__, enable ? "enabled" : "disabled"); 6036 } 6037 6038 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 6039 { 6040 int ret; 6041 6042 if (!ufshcd_is_wb_allowed(hba) || 6043 hba->dev_info.wb_buf_flush_enabled == enable) 6044 return 0; 6045 6046 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 6047 if (ret) { 6048 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 6049 __func__, enable ? "enabling" : "disabling", ret); 6050 return ret; 6051 } 6052 6053 hba->dev_info.wb_buf_flush_enabled = enable; 6054 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 6055 __func__, enable ? "enabled" : "disabled"); 6056 6057 return ret; 6058 } 6059 6060 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 6061 u32 avail_buf) 6062 { 6063 u32 cur_buf; 6064 int ret; 6065 u8 index; 6066 6067 index = ufshcd_wb_get_query_index(hba); 6068 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6069 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 6070 index, 0, &cur_buf); 6071 if (ret) { 6072 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 6073 __func__, ret); 6074 return false; 6075 } 6076 6077 if (!cur_buf) { 6078 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 6079 cur_buf); 6080 return false; 6081 } 6082 /* Let it continue to flush when available buffer exceeds threshold */ 6083 return avail_buf < hba->vps->wb_flush_threshold; 6084 } 6085 6086 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 6087 { 6088 if (ufshcd_is_wb_buf_flush_allowed(hba)) 6089 ufshcd_wb_toggle_buf_flush(hba, false); 6090 6091 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 6092 ufshcd_wb_toggle(hba, false); 6093 hba->caps &= ~UFSHCD_CAP_WB_EN; 6094 6095 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 6096 } 6097 6098 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 6099 { 6100 u32 lifetime; 6101 int ret; 6102 u8 index; 6103 6104 index = ufshcd_wb_get_query_index(hba); 6105 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6106 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 6107 index, 0, &lifetime); 6108 if (ret) { 6109 dev_err(hba->dev, 6110 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 6111 __func__, ret); 6112 return false; 6113 } 6114 6115 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6116 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6117 __func__, lifetime); 6118 return false; 6119 } 6120 6121 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6122 __func__, lifetime); 6123 6124 return true; 6125 } 6126 6127 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6128 { 6129 int ret; 6130 u32 avail_buf; 6131 u8 index; 6132 6133 if (!ufshcd_is_wb_allowed(hba)) 6134 return false; 6135 6136 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6137 ufshcd_wb_force_disable(hba); 6138 return false; 6139 } 6140 6141 /* 6142 * The ufs device needs the vcc to be ON to flush. 6143 * With user-space reduction enabled, it's enough to enable flush 6144 * by checking only the available buffer. The threshold 6145 * defined here is > 90% full. 6146 * With user-space preserved enabled, the current-buffer 6147 * should be checked too because the wb buffer size can reduce 6148 * when disk tends to be full. This info is provided by current 6149 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6150 * keeping vcc on when current buffer is empty. 6151 */ 6152 index = ufshcd_wb_get_query_index(hba); 6153 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6154 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6155 index, 0, &avail_buf); 6156 if (ret) { 6157 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6158 __func__, ret); 6159 return false; 6160 } 6161 6162 if (!hba->dev_info.b_presrv_uspc_en) 6163 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6164 6165 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6166 } 6167 6168 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6169 { 6170 struct ufs_hba *hba = container_of(to_delayed_work(work), 6171 struct ufs_hba, 6172 rpm_dev_flush_recheck_work); 6173 /* 6174 * To prevent unnecessary VCC power drain after device finishes 6175 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6176 * after a certain delay to recheck the threshold by next runtime 6177 * suspend. 6178 */ 6179 ufshcd_rpm_get_sync(hba); 6180 ufshcd_rpm_put_sync(hba); 6181 } 6182 6183 /** 6184 * ufshcd_exception_event_handler - handle exceptions raised by device 6185 * @work: pointer to work data 6186 * 6187 * Read bExceptionEventStatus attribute from the device and handle the 6188 * exception event accordingly. 6189 */ 6190 static void ufshcd_exception_event_handler(struct work_struct *work) 6191 { 6192 struct ufs_hba *hba; 6193 int err; 6194 u32 status = 0; 6195 hba = container_of(work, struct ufs_hba, eeh_work); 6196 6197 ufshcd_scsi_block_requests(hba); 6198 err = ufshcd_get_ee_status(hba, &status); 6199 if (err) { 6200 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6201 __func__, err); 6202 goto out; 6203 } 6204 6205 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6206 6207 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6208 ufshcd_bkops_exception_event_handler(hba); 6209 6210 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6211 ufshcd_temp_exception_event_handler(hba, status); 6212 6213 ufs_debugfs_exception_event(hba, status); 6214 out: 6215 ufshcd_scsi_unblock_requests(hba); 6216 } 6217 6218 /* Complete requests that have door-bell cleared */ 6219 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6220 { 6221 if (hba->mcq_enabled) 6222 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6223 else 6224 ufshcd_transfer_req_compl(hba); 6225 6226 ufshcd_tmc_handler(hba); 6227 } 6228 6229 /** 6230 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6231 * to recover from the DL NAC errors or not. 6232 * @hba: per-adapter instance 6233 * 6234 * Return: true if error handling is required, false otherwise. 6235 */ 6236 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6237 { 6238 unsigned long flags; 6239 bool err_handling = true; 6240 6241 spin_lock_irqsave(hba->host->host_lock, flags); 6242 /* 6243 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6244 * device fatal error and/or DL NAC & REPLAY timeout errors. 6245 */ 6246 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6247 goto out; 6248 6249 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6250 ((hba->saved_err & UIC_ERROR) && 6251 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6252 goto out; 6253 6254 if ((hba->saved_err & UIC_ERROR) && 6255 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6256 int err; 6257 /* 6258 * wait for 50ms to see if we can get any other errors or not. 6259 */ 6260 spin_unlock_irqrestore(hba->host->host_lock, flags); 6261 msleep(50); 6262 spin_lock_irqsave(hba->host->host_lock, flags); 6263 6264 /* 6265 * now check if we have got any other severe errors other than 6266 * DL NAC error? 6267 */ 6268 if ((hba->saved_err & INT_FATAL_ERRORS) || 6269 ((hba->saved_err & UIC_ERROR) && 6270 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6271 goto out; 6272 6273 /* 6274 * As DL NAC is the only error received so far, send out NOP 6275 * command to confirm if link is still active or not. 6276 * - If we don't get any response then do error recovery. 6277 * - If we get response then clear the DL NAC error bit. 6278 */ 6279 6280 spin_unlock_irqrestore(hba->host->host_lock, flags); 6281 err = ufshcd_verify_dev_init(hba); 6282 spin_lock_irqsave(hba->host->host_lock, flags); 6283 6284 if (err) 6285 goto out; 6286 6287 /* Link seems to be alive hence ignore the DL NAC errors */ 6288 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6289 hba->saved_err &= ~UIC_ERROR; 6290 /* clear NAC error */ 6291 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6292 if (!hba->saved_uic_err) 6293 err_handling = false; 6294 } 6295 out: 6296 spin_unlock_irqrestore(hba->host->host_lock, flags); 6297 return err_handling; 6298 } 6299 6300 /* host lock must be held before calling this func */ 6301 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6302 { 6303 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6304 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6305 } 6306 6307 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6308 { 6309 lockdep_assert_held(hba->host->host_lock); 6310 6311 /* handle fatal errors only when link is not in error state */ 6312 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6313 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6314 ufshcd_is_saved_err_fatal(hba)) 6315 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6316 else 6317 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6318 queue_work(hba->eh_wq, &hba->eh_work); 6319 } 6320 } 6321 6322 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6323 { 6324 spin_lock_irq(hba->host->host_lock); 6325 hba->force_reset = true; 6326 ufshcd_schedule_eh_work(hba); 6327 spin_unlock_irq(hba->host->host_lock); 6328 } 6329 6330 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6331 { 6332 mutex_lock(&hba->wb_mutex); 6333 down_write(&hba->clk_scaling_lock); 6334 hba->clk_scaling.is_allowed = allow; 6335 up_write(&hba->clk_scaling_lock); 6336 mutex_unlock(&hba->wb_mutex); 6337 } 6338 6339 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6340 { 6341 if (suspend) { 6342 if (hba->clk_scaling.is_enabled) 6343 ufshcd_suspend_clkscaling(hba); 6344 ufshcd_clk_scaling_allow(hba, false); 6345 } else { 6346 ufshcd_clk_scaling_allow(hba, true); 6347 if (hba->clk_scaling.is_enabled) 6348 ufshcd_resume_clkscaling(hba); 6349 } 6350 } 6351 6352 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6353 { 6354 ufshcd_rpm_get_sync(hba); 6355 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6356 hba->is_sys_suspended) { 6357 enum ufs_pm_op pm_op; 6358 6359 /* 6360 * Don't assume anything of resume, if 6361 * resume fails, irq and clocks can be OFF, and powers 6362 * can be OFF or in LPM. 6363 */ 6364 ufshcd_setup_hba_vreg(hba, true); 6365 ufshcd_enable_irq(hba); 6366 ufshcd_setup_vreg(hba, true); 6367 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6368 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6369 ufshcd_hold(hba); 6370 if (!ufshcd_is_clkgating_allowed(hba)) 6371 ufshcd_setup_clocks(hba, true); 6372 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6373 ufshcd_vops_resume(hba, pm_op); 6374 } else { 6375 ufshcd_hold(hba); 6376 if (ufshcd_is_clkscaling_supported(hba) && 6377 hba->clk_scaling.is_enabled) 6378 ufshcd_suspend_clkscaling(hba); 6379 ufshcd_clk_scaling_allow(hba, false); 6380 } 6381 ufshcd_scsi_block_requests(hba); 6382 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6383 blk_mq_wait_quiesce_done(&hba->host->tag_set); 6384 cancel_work_sync(&hba->eeh_work); 6385 } 6386 6387 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6388 { 6389 ufshcd_scsi_unblock_requests(hba); 6390 ufshcd_release(hba); 6391 if (ufshcd_is_clkscaling_supported(hba)) 6392 ufshcd_clk_scaling_suspend(hba, false); 6393 ufshcd_rpm_put(hba); 6394 } 6395 6396 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6397 { 6398 return (!hba->is_powered || hba->shutting_down || 6399 !hba->ufs_device_wlun || 6400 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6401 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6402 ufshcd_is_link_broken(hba)))); 6403 } 6404 6405 #ifdef CONFIG_PM 6406 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6407 { 6408 struct Scsi_Host *shost = hba->host; 6409 struct scsi_device *sdev; 6410 struct request_queue *q; 6411 int ret; 6412 6413 hba->is_sys_suspended = false; 6414 /* 6415 * Set RPM status of wlun device to RPM_ACTIVE, 6416 * this also clears its runtime error. 6417 */ 6418 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6419 6420 /* hba device might have a runtime error otherwise */ 6421 if (ret) 6422 ret = pm_runtime_set_active(hba->dev); 6423 /* 6424 * If wlun device had runtime error, we also need to resume those 6425 * consumer scsi devices in case any of them has failed to be 6426 * resumed due to supplier runtime resume failure. This is to unblock 6427 * blk_queue_enter in case there are bios waiting inside it. 6428 */ 6429 if (!ret) { 6430 shost_for_each_device(sdev, shost) { 6431 q = sdev->request_queue; 6432 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6433 q->rpm_status == RPM_SUSPENDING)) 6434 pm_request_resume(q->dev); 6435 } 6436 } 6437 } 6438 #else 6439 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6440 { 6441 } 6442 #endif 6443 6444 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6445 { 6446 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6447 u32 mode; 6448 6449 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6450 6451 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6452 return true; 6453 6454 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6455 return true; 6456 6457 return false; 6458 } 6459 6460 static bool ufshcd_abort_one(struct request *rq, void *priv) 6461 { 6462 int *ret = priv; 6463 u32 tag = rq->tag; 6464 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6465 struct scsi_device *sdev = cmd->device; 6466 struct Scsi_Host *shost = sdev->host; 6467 struct ufs_hba *hba = shost_priv(shost); 6468 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 6469 struct ufs_hw_queue *hwq; 6470 unsigned long flags; 6471 6472 *ret = ufshcd_try_to_abort_task(hba, tag); 6473 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6474 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6475 *ret ? "failed" : "succeeded"); 6476 6477 /* Release cmd in MCQ mode if abort succeeds */ 6478 if (hba->mcq_enabled && (*ret == 0)) { 6479 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 6480 if (!hwq) 6481 return 0; 6482 spin_lock_irqsave(&hwq->cq_lock, flags); 6483 if (ufshcd_cmd_inflight(lrbp->cmd)) 6484 ufshcd_release_scsi_cmd(hba, lrbp); 6485 spin_unlock_irqrestore(&hwq->cq_lock, flags); 6486 } 6487 6488 return *ret == 0; 6489 } 6490 6491 /** 6492 * ufshcd_abort_all - Abort all pending commands. 6493 * @hba: Host bus adapter pointer. 6494 * 6495 * Return: true if and only if the host controller needs to be reset. 6496 */ 6497 static bool ufshcd_abort_all(struct ufs_hba *hba) 6498 { 6499 int tag, ret = 0; 6500 6501 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6502 if (ret) 6503 goto out; 6504 6505 /* Clear pending task management requests */ 6506 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6507 ret = ufshcd_clear_tm_cmd(hba, tag); 6508 if (ret) 6509 goto out; 6510 } 6511 6512 out: 6513 /* Complete the requests that are cleared by s/w */ 6514 ufshcd_complete_requests(hba, false); 6515 6516 return ret != 0; 6517 } 6518 6519 /** 6520 * ufshcd_err_handler - handle UFS errors that require s/w attention 6521 * @work: pointer to work structure 6522 */ 6523 static void ufshcd_err_handler(struct work_struct *work) 6524 { 6525 int retries = MAX_ERR_HANDLER_RETRIES; 6526 struct ufs_hba *hba; 6527 unsigned long flags; 6528 bool needs_restore; 6529 bool needs_reset; 6530 int pmc_err; 6531 6532 hba = container_of(work, struct ufs_hba, eh_work); 6533 6534 dev_info(hba->dev, 6535 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6536 __func__, ufshcd_state_name[hba->ufshcd_state], 6537 hba->is_powered, hba->shutting_down, hba->saved_err, 6538 hba->saved_uic_err, hba->force_reset, 6539 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6540 6541 down(&hba->host_sem); 6542 spin_lock_irqsave(hba->host->host_lock, flags); 6543 if (ufshcd_err_handling_should_stop(hba)) { 6544 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6545 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6546 spin_unlock_irqrestore(hba->host->host_lock, flags); 6547 up(&hba->host_sem); 6548 return; 6549 } 6550 ufshcd_set_eh_in_progress(hba); 6551 spin_unlock_irqrestore(hba->host->host_lock, flags); 6552 ufshcd_err_handling_prepare(hba); 6553 /* Complete requests that have door-bell cleared by h/w */ 6554 ufshcd_complete_requests(hba, false); 6555 spin_lock_irqsave(hba->host->host_lock, flags); 6556 again: 6557 needs_restore = false; 6558 needs_reset = false; 6559 6560 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6561 hba->ufshcd_state = UFSHCD_STATE_RESET; 6562 /* 6563 * A full reset and restore might have happened after preparation 6564 * is finished, double check whether we should stop. 6565 */ 6566 if (ufshcd_err_handling_should_stop(hba)) 6567 goto skip_err_handling; 6568 6569 if ((hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) && 6570 !hba->force_reset) { 6571 bool ret; 6572 6573 spin_unlock_irqrestore(hba->host->host_lock, flags); 6574 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6575 ret = ufshcd_quirk_dl_nac_errors(hba); 6576 spin_lock_irqsave(hba->host->host_lock, flags); 6577 if (!ret && ufshcd_err_handling_should_stop(hba)) 6578 goto skip_err_handling; 6579 } 6580 6581 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6582 (hba->saved_uic_err && 6583 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6584 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6585 6586 spin_unlock_irqrestore(hba->host->host_lock, flags); 6587 ufshcd_print_host_state(hba); 6588 ufshcd_print_pwr_info(hba); 6589 ufshcd_print_evt_hist(hba); 6590 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6591 ufshcd_print_trs_all(hba, pr_prdt); 6592 spin_lock_irqsave(hba->host->host_lock, flags); 6593 } 6594 6595 /* 6596 * if host reset is required then skip clearing the pending 6597 * transfers forcefully because they will get cleared during 6598 * host reset and restore 6599 */ 6600 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6601 ufshcd_is_saved_err_fatal(hba) || 6602 ((hba->saved_err & UIC_ERROR) && 6603 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6604 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6605 needs_reset = true; 6606 goto do_reset; 6607 } 6608 6609 /* 6610 * If LINERESET was caught, UFS might have been put to PWM mode, 6611 * check if power mode restore is needed. 6612 */ 6613 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6614 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6615 if (!hba->saved_uic_err) 6616 hba->saved_err &= ~UIC_ERROR; 6617 spin_unlock_irqrestore(hba->host->host_lock, flags); 6618 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6619 needs_restore = true; 6620 spin_lock_irqsave(hba->host->host_lock, flags); 6621 if (!hba->saved_err && !needs_restore) 6622 goto skip_err_handling; 6623 } 6624 6625 hba->silence_err_logs = true; 6626 /* release lock as clear command might sleep */ 6627 spin_unlock_irqrestore(hba->host->host_lock, flags); 6628 6629 needs_reset = ufshcd_abort_all(hba); 6630 6631 spin_lock_irqsave(hba->host->host_lock, flags); 6632 hba->silence_err_logs = false; 6633 if (needs_reset) 6634 goto do_reset; 6635 6636 /* 6637 * After all reqs and tasks are cleared from doorbell, 6638 * now it is safe to retore power mode. 6639 */ 6640 if (needs_restore) { 6641 spin_unlock_irqrestore(hba->host->host_lock, flags); 6642 /* 6643 * Hold the scaling lock just in case dev cmds 6644 * are sent via bsg and/or sysfs. 6645 */ 6646 down_write(&hba->clk_scaling_lock); 6647 hba->force_pmc = true; 6648 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6649 if (pmc_err) { 6650 needs_reset = true; 6651 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6652 __func__, pmc_err); 6653 } 6654 hba->force_pmc = false; 6655 ufshcd_print_pwr_info(hba); 6656 up_write(&hba->clk_scaling_lock); 6657 spin_lock_irqsave(hba->host->host_lock, flags); 6658 } 6659 6660 do_reset: 6661 /* Fatal errors need reset */ 6662 if (needs_reset) { 6663 int err; 6664 6665 hba->force_reset = false; 6666 spin_unlock_irqrestore(hba->host->host_lock, flags); 6667 err = ufshcd_reset_and_restore(hba); 6668 if (err) 6669 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6670 __func__, err); 6671 else 6672 ufshcd_recover_pm_error(hba); 6673 spin_lock_irqsave(hba->host->host_lock, flags); 6674 } 6675 6676 skip_err_handling: 6677 if (!needs_reset) { 6678 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6679 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6680 if (hba->saved_err || hba->saved_uic_err) 6681 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6682 __func__, hba->saved_err, hba->saved_uic_err); 6683 } 6684 /* Exit in an operational state or dead */ 6685 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6686 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6687 if (--retries) 6688 goto again; 6689 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6690 } 6691 ufshcd_clear_eh_in_progress(hba); 6692 spin_unlock_irqrestore(hba->host->host_lock, flags); 6693 ufshcd_err_handling_unprepare(hba); 6694 up(&hba->host_sem); 6695 6696 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6697 ufshcd_state_name[hba->ufshcd_state]); 6698 } 6699 6700 /** 6701 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6702 * @hba: per-adapter instance 6703 * 6704 * Return: 6705 * IRQ_HANDLED - If interrupt is valid 6706 * IRQ_NONE - If invalid interrupt 6707 */ 6708 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6709 { 6710 u32 reg; 6711 irqreturn_t retval = IRQ_NONE; 6712 6713 /* PHY layer error */ 6714 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6715 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6716 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6717 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6718 /* 6719 * To know whether this error is fatal or not, DB timeout 6720 * must be checked but this error is handled separately. 6721 */ 6722 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6723 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6724 __func__); 6725 6726 /* Got a LINERESET indication. */ 6727 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6728 struct uic_command *cmd = NULL; 6729 6730 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6731 if (hba->uic_async_done && hba->active_uic_cmd) 6732 cmd = hba->active_uic_cmd; 6733 /* 6734 * Ignore the LINERESET during power mode change 6735 * operation via DME_SET command. 6736 */ 6737 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6738 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6739 } 6740 retval |= IRQ_HANDLED; 6741 } 6742 6743 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6744 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6745 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6746 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6747 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6748 6749 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6750 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6751 else if (hba->dev_quirks & 6752 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6753 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6754 hba->uic_error |= 6755 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6756 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6757 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6758 } 6759 retval |= IRQ_HANDLED; 6760 } 6761 6762 /* UIC NL/TL/DME errors needs software retry */ 6763 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6764 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6765 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6766 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6767 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6768 retval |= IRQ_HANDLED; 6769 } 6770 6771 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6772 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6773 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6774 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6775 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6776 retval |= IRQ_HANDLED; 6777 } 6778 6779 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6780 if ((reg & UIC_DME_ERROR) && 6781 (reg & UIC_DME_ERROR_CODE_MASK)) { 6782 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6783 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6784 retval |= IRQ_HANDLED; 6785 } 6786 6787 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6788 __func__, hba->uic_error); 6789 return retval; 6790 } 6791 6792 /** 6793 * ufshcd_check_errors - Check for errors that need s/w attention 6794 * @hba: per-adapter instance 6795 * @intr_status: interrupt status generated by the controller 6796 * 6797 * Return: 6798 * IRQ_HANDLED - If interrupt is valid 6799 * IRQ_NONE - If invalid interrupt 6800 */ 6801 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6802 { 6803 bool queue_eh_work = false; 6804 irqreturn_t retval = IRQ_NONE; 6805 6806 spin_lock(hba->host->host_lock); 6807 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6808 6809 if (hba->errors & INT_FATAL_ERRORS) { 6810 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6811 hba->errors); 6812 queue_eh_work = true; 6813 } 6814 6815 if (hba->errors & UIC_ERROR) { 6816 hba->uic_error = 0; 6817 retval = ufshcd_update_uic_error(hba); 6818 if (hba->uic_error) 6819 queue_eh_work = true; 6820 } 6821 6822 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6823 dev_err(hba->dev, 6824 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6825 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6826 "Enter" : "Exit", 6827 hba->errors, ufshcd_get_upmcrs(hba)); 6828 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6829 hba->errors); 6830 ufshcd_set_link_broken(hba); 6831 queue_eh_work = true; 6832 } 6833 6834 if (queue_eh_work) { 6835 /* 6836 * update the transfer error masks to sticky bits, let's do this 6837 * irrespective of current ufshcd_state. 6838 */ 6839 hba->saved_err |= hba->errors; 6840 hba->saved_uic_err |= hba->uic_error; 6841 6842 /* dump controller state before resetting */ 6843 if ((hba->saved_err & 6844 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6845 (hba->saved_uic_err && 6846 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6847 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6848 __func__, hba->saved_err, 6849 hba->saved_uic_err); 6850 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6851 "host_regs: "); 6852 ufshcd_print_pwr_info(hba); 6853 } 6854 ufshcd_schedule_eh_work(hba); 6855 retval |= IRQ_HANDLED; 6856 } 6857 /* 6858 * if (!queue_eh_work) - 6859 * Other errors are either non-fatal where host recovers 6860 * itself without s/w intervention or errors that will be 6861 * handled by the SCSI core layer. 6862 */ 6863 hba->errors = 0; 6864 hba->uic_error = 0; 6865 spin_unlock(hba->host->host_lock); 6866 return retval; 6867 } 6868 6869 /** 6870 * ufshcd_tmc_handler - handle task management function completion 6871 * @hba: per adapter instance 6872 * 6873 * Return: 6874 * IRQ_HANDLED - If interrupt is valid 6875 * IRQ_NONE - If invalid interrupt 6876 */ 6877 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6878 { 6879 unsigned long flags, pending, issued; 6880 irqreturn_t ret = IRQ_NONE; 6881 int tag; 6882 6883 spin_lock_irqsave(hba->host->host_lock, flags); 6884 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6885 issued = hba->outstanding_tasks & ~pending; 6886 for_each_set_bit(tag, &issued, hba->nutmrs) { 6887 struct request *req = hba->tmf_rqs[tag]; 6888 struct completion *c = req->end_io_data; 6889 6890 complete(c); 6891 ret = IRQ_HANDLED; 6892 } 6893 spin_unlock_irqrestore(hba->host->host_lock, flags); 6894 6895 return ret; 6896 } 6897 6898 /** 6899 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6900 * @hba: per adapter instance 6901 * 6902 * Return: IRQ_HANDLED if interrupt is handled. 6903 */ 6904 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6905 { 6906 struct ufs_hw_queue *hwq; 6907 unsigned long outstanding_cqs; 6908 unsigned int nr_queues; 6909 int i, ret; 6910 u32 events; 6911 6912 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6913 if (ret) 6914 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6915 6916 /* Exclude the poll queues */ 6917 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6918 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6919 hwq = &hba->uhq[i]; 6920 6921 events = ufshcd_mcq_read_cqis(hba, i); 6922 if (events) 6923 ufshcd_mcq_write_cqis(hba, events, i); 6924 6925 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6926 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6927 } 6928 6929 return IRQ_HANDLED; 6930 } 6931 6932 /** 6933 * ufshcd_sl_intr - Interrupt service routine 6934 * @hba: per adapter instance 6935 * @intr_status: contains interrupts generated by the controller 6936 * 6937 * Return: 6938 * IRQ_HANDLED - If interrupt is valid 6939 * IRQ_NONE - If invalid interrupt 6940 */ 6941 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6942 { 6943 irqreturn_t retval = IRQ_NONE; 6944 6945 if (intr_status & UFSHCD_UIC_MASK) 6946 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6947 6948 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6949 retval |= ufshcd_check_errors(hba, intr_status); 6950 6951 if (intr_status & UTP_TASK_REQ_COMPL) 6952 retval |= ufshcd_tmc_handler(hba); 6953 6954 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6955 retval |= ufshcd_transfer_req_compl(hba); 6956 6957 if (intr_status & MCQ_CQ_EVENT_STATUS) 6958 retval |= ufshcd_handle_mcq_cq_events(hba); 6959 6960 return retval; 6961 } 6962 6963 /** 6964 * ufshcd_intr - Main interrupt service routine 6965 * @irq: irq number 6966 * @__hba: pointer to adapter instance 6967 * 6968 * Return: 6969 * IRQ_HANDLED - If interrupt is valid 6970 * IRQ_NONE - If invalid interrupt 6971 */ 6972 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6973 { 6974 u32 intr_status, enabled_intr_status = 0; 6975 irqreturn_t retval = IRQ_NONE; 6976 struct ufs_hba *hba = __hba; 6977 int retries = hba->nutrs; 6978 6979 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6980 hba->ufs_stats.last_intr_status = intr_status; 6981 hba->ufs_stats.last_intr_ts = local_clock(); 6982 6983 /* 6984 * There could be max of hba->nutrs reqs in flight and in worst case 6985 * if the reqs get finished 1 by 1 after the interrupt status is 6986 * read, make sure we handle them by checking the interrupt status 6987 * again in a loop until we process all of the reqs before returning. 6988 */ 6989 while (intr_status && retries--) { 6990 enabled_intr_status = 6991 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6992 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6993 if (enabled_intr_status) 6994 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 6995 6996 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6997 } 6998 6999 if (enabled_intr_status && retval == IRQ_NONE && 7000 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 7001 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 7002 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 7003 __func__, 7004 intr_status, 7005 hba->ufs_stats.last_intr_status, 7006 enabled_intr_status); 7007 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 7008 } 7009 7010 return retval; 7011 } 7012 7013 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 7014 { 7015 int err = 0; 7016 u32 mask = 1 << tag; 7017 unsigned long flags; 7018 7019 if (!test_bit(tag, &hba->outstanding_tasks)) 7020 goto out; 7021 7022 spin_lock_irqsave(hba->host->host_lock, flags); 7023 ufshcd_utmrl_clear(hba, tag); 7024 spin_unlock_irqrestore(hba->host->host_lock, flags); 7025 7026 /* poll for max. 1 sec to clear door bell register by h/w */ 7027 err = ufshcd_wait_for_register(hba, 7028 REG_UTP_TASK_REQ_DOOR_BELL, 7029 mask, 0, 1000, 1000); 7030 7031 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 7032 tag, err < 0 ? "failed" : "succeeded"); 7033 7034 out: 7035 return err; 7036 } 7037 7038 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 7039 struct utp_task_req_desc *treq, u8 tm_function) 7040 { 7041 struct request_queue *q = hba->tmf_queue; 7042 struct Scsi_Host *host = hba->host; 7043 DECLARE_COMPLETION_ONSTACK(wait); 7044 struct request *req; 7045 unsigned long flags; 7046 int task_tag, err; 7047 7048 /* 7049 * blk_mq_alloc_request() is used here only to get a free tag. 7050 */ 7051 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 7052 if (IS_ERR(req)) 7053 return PTR_ERR(req); 7054 7055 req->end_io_data = &wait; 7056 ufshcd_hold(hba); 7057 7058 spin_lock_irqsave(host->host_lock, flags); 7059 7060 task_tag = req->tag; 7061 hba->tmf_rqs[req->tag] = req; 7062 treq->upiu_req.req_header.task_tag = task_tag; 7063 7064 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 7065 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 7066 7067 /* send command to the controller */ 7068 __set_bit(task_tag, &hba->outstanding_tasks); 7069 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 7070 7071 spin_unlock_irqrestore(host->host_lock, flags); 7072 7073 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 7074 7075 /* wait until the task management command is completed */ 7076 err = wait_for_completion_io_timeout(&wait, 7077 msecs_to_jiffies(TM_CMD_TIMEOUT)); 7078 if (!err) { 7079 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 7080 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 7081 __func__, tm_function); 7082 if (ufshcd_clear_tm_cmd(hba, task_tag)) 7083 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 7084 __func__, task_tag); 7085 err = -ETIMEDOUT; 7086 } else { 7087 err = 0; 7088 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 7089 7090 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 7091 } 7092 7093 spin_lock_irqsave(hba->host->host_lock, flags); 7094 hba->tmf_rqs[req->tag] = NULL; 7095 __clear_bit(task_tag, &hba->outstanding_tasks); 7096 spin_unlock_irqrestore(hba->host->host_lock, flags); 7097 7098 ufshcd_release(hba); 7099 blk_mq_free_request(req); 7100 7101 return err; 7102 } 7103 7104 /** 7105 * ufshcd_issue_tm_cmd - issues task management commands to controller 7106 * @hba: per adapter instance 7107 * @lun_id: LUN ID to which TM command is sent 7108 * @task_id: task ID to which the TM command is applicable 7109 * @tm_function: task management function opcode 7110 * @tm_response: task management service response return value 7111 * 7112 * Return: non-zero value on error, zero on success. 7113 */ 7114 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7115 u8 tm_function, u8 *tm_response) 7116 { 7117 struct utp_task_req_desc treq = { }; 7118 enum utp_ocs ocs_value; 7119 int err; 7120 7121 /* Configure task request descriptor */ 7122 treq.header.interrupt = 1; 7123 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7124 7125 /* Configure task request UPIU */ 7126 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7127 treq.upiu_req.req_header.lun = lun_id; 7128 treq.upiu_req.req_header.tm_function = tm_function; 7129 7130 /* 7131 * The host shall provide the same value for LUN field in the basic 7132 * header and for Input Parameter. 7133 */ 7134 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7135 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7136 7137 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7138 if (err == -ETIMEDOUT) 7139 return err; 7140 7141 ocs_value = treq.header.ocs & MASK_OCS; 7142 if (ocs_value != OCS_SUCCESS) 7143 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7144 __func__, ocs_value); 7145 else if (tm_response) 7146 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7147 MASK_TM_SERVICE_RESP; 7148 return err; 7149 } 7150 7151 /** 7152 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7153 * @hba: per-adapter instance 7154 * @req_upiu: upiu request 7155 * @rsp_upiu: upiu reply 7156 * @desc_buff: pointer to descriptor buffer, NULL if NA 7157 * @buff_len: descriptor size, 0 if NA 7158 * @cmd_type: specifies the type (NOP, Query...) 7159 * @desc_op: descriptor operation 7160 * 7161 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7162 * Therefore, it "rides" the device management infrastructure: uses its tag and 7163 * tasks work queues. 7164 * 7165 * Since there is only one available tag for device management commands, 7166 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7167 * 7168 * Return: 0 upon success; < 0 upon failure. 7169 */ 7170 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7171 struct utp_upiu_req *req_upiu, 7172 struct utp_upiu_req *rsp_upiu, 7173 u8 *desc_buff, int *buff_len, 7174 enum dev_cmd_type cmd_type, 7175 enum query_opcode desc_op) 7176 { 7177 const u32 tag = hba->reserved_slot; 7178 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7179 int err = 0; 7180 u8 upiu_flags; 7181 7182 /* Protects use of hba->reserved_slot. */ 7183 lockdep_assert_held(&hba->dev_cmd.lock); 7184 7185 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 7186 7187 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 7188 7189 /* update the task tag in the request upiu */ 7190 req_upiu->header.task_tag = tag; 7191 7192 /* just copy the upiu request as it is */ 7193 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7194 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7195 /* The Data Segment Area is optional depending upon the query 7196 * function value. for WRITE DESCRIPTOR, the data segment 7197 * follows right after the tsf. 7198 */ 7199 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7200 *buff_len = 0; 7201 } 7202 7203 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7204 7205 /* 7206 * ignore the returning value here - ufshcd_check_query_response is 7207 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7208 * read the response directly ignoring all errors. 7209 */ 7210 ufshcd_issue_dev_cmd(hba, lrbp, tag, QUERY_REQ_TIMEOUT); 7211 7212 /* just copy the upiu response as it is */ 7213 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7214 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7215 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7216 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7217 .data_segment_length); 7218 7219 if (*buff_len >= resp_len) { 7220 memcpy(desc_buff, descp, resp_len); 7221 *buff_len = resp_len; 7222 } else { 7223 dev_warn(hba->dev, 7224 "%s: rsp size %d is bigger than buffer size %d", 7225 __func__, resp_len, *buff_len); 7226 *buff_len = 0; 7227 err = -EINVAL; 7228 } 7229 } 7230 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7231 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7232 7233 return err; 7234 } 7235 7236 /** 7237 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7238 * @hba: per-adapter instance 7239 * @req_upiu: upiu request 7240 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7241 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7242 * @desc_buff: pointer to descriptor buffer, NULL if NA 7243 * @buff_len: descriptor size, 0 if NA 7244 * @desc_op: descriptor operation 7245 * 7246 * Supports UTP Transfer requests (nop and query), and UTP Task 7247 * Management requests. 7248 * It is up to the caller to fill the upiu conent properly, as it will 7249 * be copied without any further input validations. 7250 * 7251 * Return: 0 upon success; < 0 upon failure. 7252 */ 7253 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7254 struct utp_upiu_req *req_upiu, 7255 struct utp_upiu_req *rsp_upiu, 7256 enum upiu_request_transaction msgcode, 7257 u8 *desc_buff, int *buff_len, 7258 enum query_opcode desc_op) 7259 { 7260 int err; 7261 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7262 struct utp_task_req_desc treq = { }; 7263 enum utp_ocs ocs_value; 7264 u8 tm_f = req_upiu->header.tm_function; 7265 7266 switch (msgcode) { 7267 case UPIU_TRANSACTION_NOP_OUT: 7268 cmd_type = DEV_CMD_TYPE_NOP; 7269 fallthrough; 7270 case UPIU_TRANSACTION_QUERY_REQ: 7271 ufshcd_dev_man_lock(hba); 7272 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7273 desc_buff, buff_len, 7274 cmd_type, desc_op); 7275 ufshcd_dev_man_unlock(hba); 7276 7277 break; 7278 case UPIU_TRANSACTION_TASK_REQ: 7279 treq.header.interrupt = 1; 7280 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7281 7282 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7283 7284 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7285 if (err == -ETIMEDOUT) 7286 break; 7287 7288 ocs_value = treq.header.ocs & MASK_OCS; 7289 if (ocs_value != OCS_SUCCESS) { 7290 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7291 ocs_value); 7292 break; 7293 } 7294 7295 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7296 7297 break; 7298 default: 7299 err = -EINVAL; 7300 7301 break; 7302 } 7303 7304 return err; 7305 } 7306 7307 /** 7308 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7309 * @hba: per adapter instance 7310 * @req_upiu: upiu request 7311 * @rsp_upiu: upiu reply 7312 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7313 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7314 * @sg_cnt: The number of sg lists actually used 7315 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7316 * @dir: DMA direction 7317 * 7318 * Return: zero on success, non-zero on failure. 7319 */ 7320 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7321 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7322 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7323 enum dma_data_direction dir) 7324 { 7325 const u32 tag = hba->reserved_slot; 7326 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7327 int err = 0; 7328 int result; 7329 u8 upiu_flags; 7330 u8 *ehs_data; 7331 u16 ehs_len; 7332 int ehs = (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) ? 2 : 0; 7333 7334 /* Protects use of hba->reserved_slot. */ 7335 ufshcd_dev_man_lock(hba); 7336 7337 ufshcd_setup_dev_cmd(hba, lrbp, DEV_CMD_TYPE_RPMB, UFS_UPIU_RPMB_WLUN, tag); 7338 7339 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, ehs); 7340 7341 /* update the task tag */ 7342 req_upiu->header.task_tag = tag; 7343 7344 /* copy the UPIU(contains CDB) request as it is */ 7345 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7346 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7347 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7348 7349 if (dir != DMA_NONE && sg_list) 7350 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7351 7352 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7353 7354 err = ufshcd_issue_dev_cmd(hba, lrbp, tag, ADVANCED_RPMB_REQ_TIMEOUT); 7355 7356 if (!err) { 7357 /* Just copy the upiu response as it is */ 7358 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7359 /* Get the response UPIU result */ 7360 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7361 lrbp->ucd_rsp_ptr->header.status; 7362 7363 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7364 /* 7365 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7366 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7367 * Message is 02h 7368 */ 7369 if (ehs_len == 2 && rsp_ehs) { 7370 /* 7371 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7372 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7373 */ 7374 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7375 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7376 } 7377 } 7378 7379 ufshcd_dev_man_unlock(hba); 7380 7381 return err ? : result; 7382 } 7383 7384 /** 7385 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7386 * @cmd: SCSI command pointer 7387 * 7388 * Return: SUCCESS or FAILED. 7389 */ 7390 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7391 { 7392 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7393 struct Scsi_Host *host; 7394 struct ufs_hba *hba; 7395 struct ufs_hw_queue *hwq; 7396 struct ufshcd_lrb *lrbp; 7397 u32 pos, not_cleared_mask = 0; 7398 int err; 7399 u8 resp = 0xF, lun; 7400 7401 host = cmd->device->host; 7402 hba = shost_priv(host); 7403 7404 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7405 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7406 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7407 if (!err) 7408 err = resp; 7409 goto out; 7410 } 7411 7412 if (hba->mcq_enabled) { 7413 for (pos = 0; pos < hba->nutrs; pos++) { 7414 lrbp = &hba->lrb[pos]; 7415 if (ufshcd_cmd_inflight(lrbp->cmd) && 7416 lrbp->lun == lun) { 7417 ufshcd_clear_cmd(hba, pos); 7418 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7419 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7420 } 7421 } 7422 err = 0; 7423 goto out; 7424 } 7425 7426 /* clear the commands that were pending for corresponding LUN */ 7427 spin_lock_irqsave(&hba->outstanding_lock, flags); 7428 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7429 if (hba->lrb[pos].lun == lun) 7430 __set_bit(pos, &pending_reqs); 7431 hba->outstanding_reqs &= ~pending_reqs; 7432 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7433 7434 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7435 if (ufshcd_clear_cmd(hba, pos) < 0) { 7436 spin_lock_irqsave(&hba->outstanding_lock, flags); 7437 not_cleared = 1U << pos & 7438 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7439 hba->outstanding_reqs |= not_cleared; 7440 not_cleared_mask |= not_cleared; 7441 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7442 7443 dev_err(hba->dev, "%s: failed to clear request %d\n", 7444 __func__, pos); 7445 } 7446 } 7447 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7448 7449 out: 7450 hba->req_abort_count = 0; 7451 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7452 if (!err) { 7453 err = SUCCESS; 7454 } else { 7455 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7456 err = FAILED; 7457 } 7458 return err; 7459 } 7460 7461 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7462 { 7463 struct ufshcd_lrb *lrbp; 7464 int tag; 7465 7466 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7467 lrbp = &hba->lrb[tag]; 7468 lrbp->req_abort_skip = true; 7469 } 7470 } 7471 7472 /** 7473 * ufshcd_try_to_abort_task - abort a specific task 7474 * @hba: Pointer to adapter instance 7475 * @tag: Task tag/index to be aborted 7476 * 7477 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7478 * command, and in host controller by clearing the door-bell register. There can 7479 * be race between controller sending the command to the device while abort is 7480 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7481 * really issued and then try to abort it. 7482 * 7483 * Return: zero on success, non-zero on failure. 7484 */ 7485 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7486 { 7487 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7488 int err = 0; 7489 int poll_cnt; 7490 u8 resp = 0xF; 7491 u32 reg; 7492 7493 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7494 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7495 UFS_QUERY_TASK, &resp); 7496 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7497 /* cmd pending in the device */ 7498 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7499 __func__, tag); 7500 break; 7501 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7502 /* 7503 * cmd not pending in the device, check if it is 7504 * in transition. 7505 */ 7506 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n", 7507 __func__, tag); 7508 if (hba->mcq_enabled) { 7509 /* MCQ mode */ 7510 if (ufshcd_cmd_inflight(lrbp->cmd)) { 7511 /* sleep for max. 200us same delay as in SDB mode */ 7512 usleep_range(100, 200); 7513 continue; 7514 } 7515 /* command completed already */ 7516 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n", 7517 __func__, tag); 7518 goto out; 7519 } 7520 7521 /* Single Doorbell Mode */ 7522 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7523 if (reg & (1 << tag)) { 7524 /* sleep for max. 200us to stabilize */ 7525 usleep_range(100, 200); 7526 continue; 7527 } 7528 /* command completed already */ 7529 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n", 7530 __func__, tag); 7531 goto out; 7532 } else { 7533 dev_err(hba->dev, 7534 "%s: no response from device. tag = %d, err %d\n", 7535 __func__, tag, err); 7536 if (!err) 7537 err = resp; /* service response error */ 7538 goto out; 7539 } 7540 } 7541 7542 if (!poll_cnt) { 7543 err = -EBUSY; 7544 goto out; 7545 } 7546 7547 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7548 UFS_ABORT_TASK, &resp); 7549 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7550 if (!err) { 7551 err = resp; /* service response error */ 7552 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7553 __func__, tag, err); 7554 } 7555 goto out; 7556 } 7557 7558 err = ufshcd_clear_cmd(hba, tag); 7559 if (err) 7560 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7561 __func__, tag, err); 7562 7563 out: 7564 return err; 7565 } 7566 7567 /** 7568 * ufshcd_abort - scsi host template eh_abort_handler callback 7569 * @cmd: SCSI command pointer 7570 * 7571 * Return: SUCCESS or FAILED. 7572 */ 7573 static int ufshcd_abort(struct scsi_cmnd *cmd) 7574 { 7575 struct Scsi_Host *host = cmd->device->host; 7576 struct ufs_hba *hba = shost_priv(host); 7577 int tag = scsi_cmd_to_rq(cmd)->tag; 7578 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7579 unsigned long flags; 7580 int err = FAILED; 7581 bool outstanding; 7582 u32 reg; 7583 7584 ufshcd_hold(hba); 7585 7586 if (!hba->mcq_enabled) { 7587 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7588 if (!test_bit(tag, &hba->outstanding_reqs)) { 7589 /* If command is already aborted/completed, return FAILED. */ 7590 dev_err(hba->dev, 7591 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7592 __func__, tag, hba->outstanding_reqs, reg); 7593 goto release; 7594 } 7595 } 7596 7597 /* Print Transfer Request of aborted task */ 7598 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7599 7600 /* 7601 * Print detailed info about aborted request. 7602 * As more than one request might get aborted at the same time, 7603 * print full information only for the first aborted request in order 7604 * to reduce repeated printouts. For other aborted requests only print 7605 * basic details. 7606 */ 7607 scsi_print_command(cmd); 7608 if (!hba->req_abort_count) { 7609 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7610 ufshcd_print_evt_hist(hba); 7611 ufshcd_print_host_state(hba); 7612 ufshcd_print_pwr_info(hba); 7613 ufshcd_print_tr(hba, tag, true); 7614 } else { 7615 ufshcd_print_tr(hba, tag, false); 7616 } 7617 hba->req_abort_count++; 7618 7619 if (!hba->mcq_enabled && !(reg & (1 << tag))) { 7620 /* only execute this code in single doorbell mode */ 7621 dev_err(hba->dev, 7622 "%s: cmd was completed, but without a notifying intr, tag = %d", 7623 __func__, tag); 7624 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7625 goto release; 7626 } 7627 7628 /* 7629 * Task abort to the device W-LUN is illegal. When this command 7630 * will fail, due to spec violation, scsi err handling next step 7631 * will be to send LU reset which, again, is a spec violation. 7632 * To avoid these unnecessary/illegal steps, first we clean up 7633 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7634 * then queue the eh_work and bail. 7635 */ 7636 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7637 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7638 7639 spin_lock_irqsave(host->host_lock, flags); 7640 hba->force_reset = true; 7641 ufshcd_schedule_eh_work(hba); 7642 spin_unlock_irqrestore(host->host_lock, flags); 7643 goto release; 7644 } 7645 7646 if (hba->mcq_enabled) { 7647 /* MCQ mode. Branch off to handle abort for mcq mode */ 7648 err = ufshcd_mcq_abort(cmd); 7649 goto release; 7650 } 7651 7652 /* Skip task abort in case previous aborts failed and report failure */ 7653 if (lrbp->req_abort_skip) { 7654 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7655 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7656 goto release; 7657 } 7658 7659 err = ufshcd_try_to_abort_task(hba, tag); 7660 if (err) { 7661 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7662 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7663 err = FAILED; 7664 goto release; 7665 } 7666 7667 /* 7668 * Clear the corresponding bit from outstanding_reqs since the command 7669 * has been aborted successfully. 7670 */ 7671 spin_lock_irqsave(&hba->outstanding_lock, flags); 7672 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7673 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7674 7675 if (outstanding) 7676 ufshcd_release_scsi_cmd(hba, lrbp); 7677 7678 err = SUCCESS; 7679 7680 release: 7681 /* Matches the ufshcd_hold() call at the start of this function. */ 7682 ufshcd_release(hba); 7683 return err; 7684 } 7685 7686 /** 7687 * ufshcd_host_reset_and_restore - reset and restore host controller 7688 * @hba: per-adapter instance 7689 * 7690 * Note that host controller reset may issue DME_RESET to 7691 * local and remote (device) Uni-Pro stack and the attributes 7692 * are reset to default state. 7693 * 7694 * Return: zero on success, non-zero on failure. 7695 */ 7696 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7697 { 7698 int err; 7699 7700 /* 7701 * Stop the host controller and complete the requests 7702 * cleared by h/w 7703 */ 7704 ufshcd_hba_stop(hba); 7705 hba->silence_err_logs = true; 7706 ufshcd_complete_requests(hba, true); 7707 hba->silence_err_logs = false; 7708 7709 /* scale up clocks to max frequency before full reinitialization */ 7710 ufshcd_scale_clks(hba, ULONG_MAX, true); 7711 7712 err = ufshcd_hba_enable(hba); 7713 7714 /* Establish the link again and restore the device */ 7715 if (!err) 7716 err = ufshcd_probe_hba(hba, false); 7717 7718 if (err) 7719 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7720 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7721 return err; 7722 } 7723 7724 /** 7725 * ufshcd_reset_and_restore - reset and re-initialize host/device 7726 * @hba: per-adapter instance 7727 * 7728 * Reset and recover device, host and re-establish link. This 7729 * is helpful to recover the communication in fatal error conditions. 7730 * 7731 * Return: zero on success, non-zero on failure. 7732 */ 7733 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7734 { 7735 u32 saved_err = 0; 7736 u32 saved_uic_err = 0; 7737 int err = 0; 7738 unsigned long flags; 7739 int retries = MAX_HOST_RESET_RETRIES; 7740 7741 spin_lock_irqsave(hba->host->host_lock, flags); 7742 do { 7743 /* 7744 * This is a fresh start, cache and clear saved error first, 7745 * in case new error generated during reset and restore. 7746 */ 7747 saved_err |= hba->saved_err; 7748 saved_uic_err |= hba->saved_uic_err; 7749 hba->saved_err = 0; 7750 hba->saved_uic_err = 0; 7751 hba->force_reset = false; 7752 hba->ufshcd_state = UFSHCD_STATE_RESET; 7753 spin_unlock_irqrestore(hba->host->host_lock, flags); 7754 7755 /* Reset the attached device */ 7756 ufshcd_device_reset(hba); 7757 7758 err = ufshcd_host_reset_and_restore(hba); 7759 7760 spin_lock_irqsave(hba->host->host_lock, flags); 7761 if (err) 7762 continue; 7763 /* Do not exit unless operational or dead */ 7764 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7765 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7766 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7767 err = -EAGAIN; 7768 } while (err && --retries); 7769 7770 /* 7771 * Inform scsi mid-layer that we did reset and allow to handle 7772 * Unit Attention properly. 7773 */ 7774 scsi_report_bus_reset(hba->host, 0); 7775 if (err) { 7776 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7777 hba->saved_err |= saved_err; 7778 hba->saved_uic_err |= saved_uic_err; 7779 } 7780 spin_unlock_irqrestore(hba->host->host_lock, flags); 7781 7782 return err; 7783 } 7784 7785 /** 7786 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7787 * @cmd: SCSI command pointer 7788 * 7789 * Return: SUCCESS or FAILED. 7790 */ 7791 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7792 { 7793 int err = SUCCESS; 7794 unsigned long flags; 7795 struct ufs_hba *hba; 7796 7797 hba = shost_priv(cmd->device->host); 7798 7799 /* 7800 * If runtime PM sent SSU and got a timeout, scsi_error_handler is 7801 * stuck in this function waiting for flush_work(&hba->eh_work). And 7802 * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do 7803 * ufshcd_link_recovery instead of eh_work to prevent deadlock. 7804 */ 7805 if (hba->pm_op_in_progress) { 7806 if (ufshcd_link_recovery(hba)) 7807 err = FAILED; 7808 7809 return err; 7810 } 7811 7812 spin_lock_irqsave(hba->host->host_lock, flags); 7813 hba->force_reset = true; 7814 ufshcd_schedule_eh_work(hba); 7815 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7816 spin_unlock_irqrestore(hba->host->host_lock, flags); 7817 7818 flush_work(&hba->eh_work); 7819 7820 spin_lock_irqsave(hba->host->host_lock, flags); 7821 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7822 err = FAILED; 7823 spin_unlock_irqrestore(hba->host->host_lock, flags); 7824 7825 return err; 7826 } 7827 7828 /** 7829 * ufshcd_get_max_icc_level - calculate the ICC level 7830 * @sup_curr_uA: max. current supported by the regulator 7831 * @start_scan: row at the desc table to start scan from 7832 * @buff: power descriptor buffer 7833 * 7834 * Return: calculated max ICC level for specific regulator. 7835 */ 7836 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7837 const char *buff) 7838 { 7839 int i; 7840 int curr_uA; 7841 u16 data; 7842 u16 unit; 7843 7844 for (i = start_scan; i >= 0; i--) { 7845 data = get_unaligned_be16(&buff[2 * i]); 7846 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7847 ATTR_ICC_LVL_UNIT_OFFSET; 7848 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7849 switch (unit) { 7850 case UFSHCD_NANO_AMP: 7851 curr_uA = curr_uA / 1000; 7852 break; 7853 case UFSHCD_MILI_AMP: 7854 curr_uA = curr_uA * 1000; 7855 break; 7856 case UFSHCD_AMP: 7857 curr_uA = curr_uA * 1000 * 1000; 7858 break; 7859 case UFSHCD_MICRO_AMP: 7860 default: 7861 break; 7862 } 7863 if (sup_curr_uA >= curr_uA) 7864 break; 7865 } 7866 if (i < 0) { 7867 i = 0; 7868 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7869 } 7870 7871 return (u32)i; 7872 } 7873 7874 /** 7875 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7876 * In case regulators are not initialized we'll return 0 7877 * @hba: per-adapter instance 7878 * @desc_buf: power descriptor buffer to extract ICC levels from. 7879 * 7880 * Return: calculated ICC level. 7881 */ 7882 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7883 const u8 *desc_buf) 7884 { 7885 u32 icc_level = 0; 7886 7887 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7888 !hba->vreg_info.vccq2) { 7889 /* 7890 * Using dev_dbg to avoid messages during runtime PM to avoid 7891 * never-ending cycles of messages written back to storage by 7892 * user space causing runtime resume, causing more messages and 7893 * so on. 7894 */ 7895 dev_dbg(hba->dev, 7896 "%s: Regulator capability was not set, actvIccLevel=%d", 7897 __func__, icc_level); 7898 goto out; 7899 } 7900 7901 if (hba->vreg_info.vcc->max_uA) 7902 icc_level = ufshcd_get_max_icc_level( 7903 hba->vreg_info.vcc->max_uA, 7904 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7905 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7906 7907 if (hba->vreg_info.vccq->max_uA) 7908 icc_level = ufshcd_get_max_icc_level( 7909 hba->vreg_info.vccq->max_uA, 7910 icc_level, 7911 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7912 7913 if (hba->vreg_info.vccq2->max_uA) 7914 icc_level = ufshcd_get_max_icc_level( 7915 hba->vreg_info.vccq2->max_uA, 7916 icc_level, 7917 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7918 out: 7919 return icc_level; 7920 } 7921 7922 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7923 { 7924 int ret; 7925 u8 *desc_buf; 7926 u32 icc_level; 7927 7928 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7929 if (!desc_buf) 7930 return; 7931 7932 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7933 desc_buf, QUERY_DESC_MAX_SIZE); 7934 if (ret) { 7935 dev_err(hba->dev, 7936 "%s: Failed reading power descriptor ret = %d", 7937 __func__, ret); 7938 goto out; 7939 } 7940 7941 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7942 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7943 7944 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7945 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7946 7947 if (ret) 7948 dev_err(hba->dev, 7949 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7950 __func__, icc_level, ret); 7951 7952 out: 7953 kfree(desc_buf); 7954 } 7955 7956 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7957 { 7958 struct Scsi_Host *shost = sdev->host; 7959 7960 scsi_autopm_get_device(sdev); 7961 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7962 if (sdev->rpm_autosuspend) 7963 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7964 shost->rpm_autosuspend_delay); 7965 scsi_autopm_put_device(sdev); 7966 } 7967 7968 /** 7969 * ufshcd_scsi_add_wlus - Adds required W-LUs 7970 * @hba: per-adapter instance 7971 * 7972 * UFS device specification requires the UFS devices to support 4 well known 7973 * logical units: 7974 * "REPORT_LUNS" (address: 01h) 7975 * "UFS Device" (address: 50h) 7976 * "RPMB" (address: 44h) 7977 * "BOOT" (address: 30h) 7978 * UFS device's power management needs to be controlled by "POWER CONDITION" 7979 * field of SSU (START STOP UNIT) command. But this "power condition" field 7980 * will take effect only when its sent to "UFS device" well known logical unit 7981 * hence we require the scsi_device instance to represent this logical unit in 7982 * order for the UFS host driver to send the SSU command for power management. 7983 * 7984 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 7985 * Block) LU so user space process can control this LU. User space may also 7986 * want to have access to BOOT LU. 7987 * 7988 * This function adds scsi device instances for each of all well known LUs 7989 * (except "REPORT LUNS" LU). 7990 * 7991 * Return: zero on success (all required W-LUs are added successfully), 7992 * non-zero error value on failure (if failed to add any of the required W-LU). 7993 */ 7994 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 7995 { 7996 int ret = 0; 7997 struct scsi_device *sdev_boot, *sdev_rpmb; 7998 7999 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 8000 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 8001 if (IS_ERR(hba->ufs_device_wlun)) { 8002 ret = PTR_ERR(hba->ufs_device_wlun); 8003 hba->ufs_device_wlun = NULL; 8004 goto out; 8005 } 8006 scsi_device_put(hba->ufs_device_wlun); 8007 8008 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 8009 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 8010 if (IS_ERR(sdev_rpmb)) { 8011 ret = PTR_ERR(sdev_rpmb); 8012 goto remove_ufs_device_wlun; 8013 } 8014 ufshcd_blk_pm_runtime_init(sdev_rpmb); 8015 scsi_device_put(sdev_rpmb); 8016 8017 sdev_boot = __scsi_add_device(hba->host, 0, 0, 8018 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 8019 if (IS_ERR(sdev_boot)) { 8020 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 8021 } else { 8022 ufshcd_blk_pm_runtime_init(sdev_boot); 8023 scsi_device_put(sdev_boot); 8024 } 8025 goto out; 8026 8027 remove_ufs_device_wlun: 8028 scsi_remove_device(hba->ufs_device_wlun); 8029 out: 8030 return ret; 8031 } 8032 8033 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 8034 { 8035 struct ufs_dev_info *dev_info = &hba->dev_info; 8036 u8 lun; 8037 u32 d_lu_wb_buf_alloc; 8038 u32 ext_ufs_feature; 8039 8040 if (!ufshcd_is_wb_allowed(hba)) 8041 return; 8042 8043 /* 8044 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 8045 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 8046 * enabled 8047 */ 8048 if (!(dev_info->wspecversion >= 0x310 || 8049 dev_info->wspecversion == 0x220 || 8050 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 8051 goto wb_disabled; 8052 8053 ext_ufs_feature = get_unaligned_be32(desc_buf + 8054 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8055 8056 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 8057 goto wb_disabled; 8058 8059 /* 8060 * WB may be supported but not configured while provisioning. The spec 8061 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 8062 * buffer configured. 8063 */ 8064 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 8065 8066 dev_info->b_presrv_uspc_en = 8067 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 8068 8069 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 8070 if (!get_unaligned_be32(desc_buf + 8071 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 8072 goto wb_disabled; 8073 } else { 8074 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 8075 d_lu_wb_buf_alloc = 0; 8076 ufshcd_read_unit_desc_param(hba, 8077 lun, 8078 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 8079 (u8 *)&d_lu_wb_buf_alloc, 8080 sizeof(d_lu_wb_buf_alloc)); 8081 if (d_lu_wb_buf_alloc) { 8082 dev_info->wb_dedicated_lu = lun; 8083 break; 8084 } 8085 } 8086 8087 if (!d_lu_wb_buf_alloc) 8088 goto wb_disabled; 8089 } 8090 8091 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8092 goto wb_disabled; 8093 8094 return; 8095 8096 wb_disabled: 8097 hba->caps &= ~UFSHCD_CAP_WB_EN; 8098 } 8099 8100 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8101 { 8102 struct ufs_dev_info *dev_info = &hba->dev_info; 8103 u32 ext_ufs_feature; 8104 u8 mask = 0; 8105 8106 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8107 return; 8108 8109 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8110 8111 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8112 mask |= MASK_EE_TOO_LOW_TEMP; 8113 8114 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8115 mask |= MASK_EE_TOO_HIGH_TEMP; 8116 8117 if (mask) { 8118 ufshcd_enable_ee(hba, mask); 8119 ufs_hwmon_probe(hba, mask); 8120 } 8121 } 8122 8123 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8124 { 8125 struct ufs_dev_info *dev_info = &hba->dev_info; 8126 u32 ext_ufs_feature; 8127 u32 ext_iid_en = 0; 8128 int err; 8129 8130 /* Only UFS-4.0 and above may support EXT_IID */ 8131 if (dev_info->wspecversion < 0x400) 8132 goto out; 8133 8134 ext_ufs_feature = get_unaligned_be32(desc_buf + 8135 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8136 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8137 goto out; 8138 8139 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8140 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8141 if (err) 8142 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8143 8144 out: 8145 dev_info->b_ext_iid_en = ext_iid_en; 8146 } 8147 8148 static void ufshcd_set_rtt(struct ufs_hba *hba) 8149 { 8150 struct ufs_dev_info *dev_info = &hba->dev_info; 8151 u32 rtt = 0; 8152 u32 dev_rtt = 0; 8153 int host_rtt_cap = hba->vops && hba->vops->max_num_rtt ? 8154 hba->vops->max_num_rtt : hba->nortt; 8155 8156 /* RTT override makes sense only for UFS-4.0 and above */ 8157 if (dev_info->wspecversion < 0x400) 8158 return; 8159 8160 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8161 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &dev_rtt)) { 8162 dev_err(hba->dev, "failed reading bMaxNumOfRTT\n"); 8163 return; 8164 } 8165 8166 /* do not override if it was already written */ 8167 if (dev_rtt != DEFAULT_MAX_NUM_RTT) 8168 return; 8169 8170 rtt = min_t(int, dev_info->rtt_cap, host_rtt_cap); 8171 8172 if (rtt == dev_rtt) 8173 return; 8174 8175 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8176 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &rtt)) 8177 dev_err(hba->dev, "failed writing bMaxNumOfRTT\n"); 8178 } 8179 8180 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8181 const struct ufs_dev_quirk *fixups) 8182 { 8183 const struct ufs_dev_quirk *f; 8184 struct ufs_dev_info *dev_info = &hba->dev_info; 8185 8186 if (!fixups) 8187 return; 8188 8189 for (f = fixups; f->quirk; f++) { 8190 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8191 f->wmanufacturerid == UFS_ANY_VENDOR) && 8192 ((dev_info->model && 8193 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8194 !strcmp(f->model, UFS_ANY_MODEL))) 8195 hba->dev_quirks |= f->quirk; 8196 } 8197 } 8198 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8199 8200 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8201 { 8202 /* fix by general quirk table */ 8203 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8204 8205 /* allow vendors to fix quirks */ 8206 ufshcd_vops_fixup_dev_quirks(hba); 8207 } 8208 8209 static void ufshcd_update_rtc(struct ufs_hba *hba) 8210 { 8211 struct timespec64 ts64; 8212 int err; 8213 u32 val; 8214 8215 ktime_get_real_ts64(&ts64); 8216 8217 if (ts64.tv_sec < hba->dev_info.rtc_time_baseline) { 8218 dev_warn_once(hba->dev, "%s: Current time precedes previous setting!\n", __func__); 8219 return; 8220 } 8221 8222 /* 8223 * The Absolute RTC mode has a 136-year limit, spanning from 2010 to 2146. If a time beyond 8224 * 2146 is required, it is recommended to choose the relative RTC mode. 8225 */ 8226 val = ts64.tv_sec - hba->dev_info.rtc_time_baseline; 8227 8228 /* Skip update RTC if RPM state is not RPM_ACTIVE */ 8229 if (ufshcd_rpm_get_if_active(hba) <= 0) 8230 return; 8231 8232 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_SECONDS_PASSED, 8233 0, 0, &val); 8234 ufshcd_rpm_put_sync(hba); 8235 8236 if (err) 8237 dev_err(hba->dev, "%s: Failed to update rtc %d\n", __func__, err); 8238 else if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 8239 hba->dev_info.rtc_time_baseline = ts64.tv_sec; 8240 } 8241 8242 static void ufshcd_rtc_work(struct work_struct *work) 8243 { 8244 struct ufs_hba *hba; 8245 8246 hba = container_of(to_delayed_work(work), struct ufs_hba, ufs_rtc_update_work); 8247 8248 /* Update RTC only when there are no requests in progress and UFSHCI is operational */ 8249 if (!ufshcd_is_ufs_dev_busy(hba) && hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) 8250 ufshcd_update_rtc(hba); 8251 8252 if (ufshcd_is_ufs_dev_active(hba) && hba->dev_info.rtc_update_period) 8253 schedule_delayed_work(&hba->ufs_rtc_update_work, 8254 msecs_to_jiffies(hba->dev_info.rtc_update_period)); 8255 } 8256 8257 static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf) 8258 { 8259 u16 periodic_rtc_update = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_FRQ_RTC]); 8260 struct ufs_dev_info *dev_info = &hba->dev_info; 8261 8262 if (periodic_rtc_update & UFS_RTC_TIME_BASELINE) { 8263 dev_info->rtc_type = UFS_RTC_ABSOLUTE; 8264 8265 /* 8266 * The concept of measuring time in Linux as the number of seconds elapsed since 8267 * 00:00:00 UTC on January 1, 1970, and UFS ABS RTC is elapsed from January 1st 8268 * 2010 00:00, here we need to adjust ABS baseline. 8269 */ 8270 dev_info->rtc_time_baseline = mktime64(2010, 1, 1, 0, 0, 0) - 8271 mktime64(1970, 1, 1, 0, 0, 0); 8272 } else { 8273 dev_info->rtc_type = UFS_RTC_RELATIVE; 8274 dev_info->rtc_time_baseline = 0; 8275 } 8276 8277 /* 8278 * We ignore TIME_PERIOD defined in wPeriodicRTCUpdate because Spec does not clearly state 8279 * how to calculate the specific update period for each time unit. And we disable periodic 8280 * RTC update work, let user configure by sysfs node according to specific circumstance. 8281 */ 8282 dev_info->rtc_update_period = 0; 8283 } 8284 8285 static int ufs_get_device_desc(struct ufs_hba *hba) 8286 { 8287 int err; 8288 u8 model_index; 8289 u8 *desc_buf; 8290 struct ufs_dev_info *dev_info = &hba->dev_info; 8291 8292 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8293 if (!desc_buf) { 8294 err = -ENOMEM; 8295 goto out; 8296 } 8297 8298 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8299 QUERY_DESC_MAX_SIZE); 8300 if (err) { 8301 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8302 __func__, err); 8303 goto out; 8304 } 8305 8306 /* 8307 * getting vendor (manufacturerID) and Bank Index in big endian 8308 * format 8309 */ 8310 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8311 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8312 8313 /* getting Specification Version in big endian format */ 8314 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8315 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8316 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8317 8318 dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP]; 8319 8320 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8321 8322 err = ufshcd_read_string_desc(hba, model_index, 8323 &dev_info->model, SD_ASCII_STD); 8324 if (err < 0) { 8325 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8326 __func__, err); 8327 goto out; 8328 } 8329 8330 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8331 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8332 8333 ufs_fixup_device_setup(hba); 8334 8335 ufshcd_wb_probe(hba, desc_buf); 8336 8337 ufshcd_temp_notif_probe(hba, desc_buf); 8338 8339 ufs_init_rtc(hba, desc_buf); 8340 8341 if (hba->ext_iid_sup) 8342 ufshcd_ext_iid_probe(hba, desc_buf); 8343 8344 /* 8345 * ufshcd_read_string_desc returns size of the string 8346 * reset the error value 8347 */ 8348 err = 0; 8349 8350 out: 8351 kfree(desc_buf); 8352 return err; 8353 } 8354 8355 static void ufs_put_device_desc(struct ufs_hba *hba) 8356 { 8357 struct ufs_dev_info *dev_info = &hba->dev_info; 8358 8359 kfree(dev_info->model); 8360 dev_info->model = NULL; 8361 } 8362 8363 /** 8364 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8365 * less than device PA_TACTIVATE time. 8366 * @hba: per-adapter instance 8367 * 8368 * Some UFS devices require host PA_TACTIVATE to be lower than device 8369 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8370 * for such devices. 8371 * 8372 * Return: zero on success, non-zero error value on failure. 8373 */ 8374 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8375 { 8376 int ret = 0; 8377 u32 granularity, peer_granularity; 8378 u32 pa_tactivate, peer_pa_tactivate; 8379 u32 pa_tactivate_us, peer_pa_tactivate_us; 8380 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8381 8382 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8383 &granularity); 8384 if (ret) 8385 goto out; 8386 8387 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8388 &peer_granularity); 8389 if (ret) 8390 goto out; 8391 8392 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8393 (granularity > PA_GRANULARITY_MAX_VAL)) { 8394 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8395 __func__, granularity); 8396 return -EINVAL; 8397 } 8398 8399 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8400 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8401 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8402 __func__, peer_granularity); 8403 return -EINVAL; 8404 } 8405 8406 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8407 if (ret) 8408 goto out; 8409 8410 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8411 &peer_pa_tactivate); 8412 if (ret) 8413 goto out; 8414 8415 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8416 peer_pa_tactivate_us = peer_pa_tactivate * 8417 gran_to_us_table[peer_granularity - 1]; 8418 8419 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8420 u32 new_peer_pa_tactivate; 8421 8422 new_peer_pa_tactivate = pa_tactivate_us / 8423 gran_to_us_table[peer_granularity - 1]; 8424 new_peer_pa_tactivate++; 8425 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8426 new_peer_pa_tactivate); 8427 } 8428 8429 out: 8430 return ret; 8431 } 8432 8433 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8434 { 8435 ufshcd_vops_apply_dev_quirks(hba); 8436 8437 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8438 /* set 1ms timeout for PA_TACTIVATE */ 8439 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8440 8441 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8442 ufshcd_quirk_tune_host_pa_tactivate(hba); 8443 } 8444 8445 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8446 { 8447 hba->ufs_stats.hibern8_exit_cnt = 0; 8448 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8449 hba->req_abort_count = 0; 8450 } 8451 8452 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8453 { 8454 int err; 8455 u8 *desc_buf; 8456 8457 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8458 if (!desc_buf) { 8459 err = -ENOMEM; 8460 goto out; 8461 } 8462 8463 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8464 desc_buf, QUERY_DESC_MAX_SIZE); 8465 if (err) { 8466 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8467 __func__, err); 8468 goto out; 8469 } 8470 8471 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8472 hba->dev_info.max_lu_supported = 32; 8473 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8474 hba->dev_info.max_lu_supported = 8; 8475 8476 out: 8477 kfree(desc_buf); 8478 return err; 8479 } 8480 8481 struct ufs_ref_clk { 8482 unsigned long freq_hz; 8483 enum ufs_ref_clk_freq val; 8484 }; 8485 8486 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8487 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8488 {26000000, REF_CLK_FREQ_26_MHZ}, 8489 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8490 {52000000, REF_CLK_FREQ_52_MHZ}, 8491 {0, REF_CLK_FREQ_INVAL}, 8492 }; 8493 8494 static enum ufs_ref_clk_freq 8495 ufs_get_bref_clk_from_hz(unsigned long freq) 8496 { 8497 int i; 8498 8499 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8500 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8501 return ufs_ref_clk_freqs[i].val; 8502 8503 return REF_CLK_FREQ_INVAL; 8504 } 8505 8506 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8507 { 8508 unsigned long freq; 8509 8510 freq = clk_get_rate(refclk); 8511 8512 hba->dev_ref_clk_freq = 8513 ufs_get_bref_clk_from_hz(freq); 8514 8515 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8516 dev_err(hba->dev, 8517 "invalid ref_clk setting = %ld\n", freq); 8518 } 8519 8520 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8521 { 8522 int err; 8523 u32 ref_clk; 8524 u32 freq = hba->dev_ref_clk_freq; 8525 8526 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8527 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8528 8529 if (err) { 8530 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8531 err); 8532 goto out; 8533 } 8534 8535 if (ref_clk == freq) 8536 goto out; /* nothing to update */ 8537 8538 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8539 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8540 8541 if (err) { 8542 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8543 ufs_ref_clk_freqs[freq].freq_hz); 8544 goto out; 8545 } 8546 8547 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8548 ufs_ref_clk_freqs[freq].freq_hz); 8549 8550 out: 8551 return err; 8552 } 8553 8554 static int ufshcd_device_params_init(struct ufs_hba *hba) 8555 { 8556 bool flag; 8557 int ret; 8558 8559 /* Init UFS geometry descriptor related parameters */ 8560 ret = ufshcd_device_geo_params_init(hba); 8561 if (ret) 8562 goto out; 8563 8564 /* Check and apply UFS device quirks */ 8565 ret = ufs_get_device_desc(hba); 8566 if (ret) { 8567 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8568 __func__, ret); 8569 goto out; 8570 } 8571 8572 ufshcd_set_rtt(hba); 8573 8574 ufshcd_get_ref_clk_gating_wait(hba); 8575 8576 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8577 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8578 hba->dev_info.f_power_on_wp_en = flag; 8579 8580 /* Probe maximum power mode co-supported by both UFS host and device */ 8581 if (ufshcd_get_max_pwr_mode(hba)) 8582 dev_err(hba->dev, 8583 "%s: Failed getting max supported power mode\n", 8584 __func__); 8585 out: 8586 return ret; 8587 } 8588 8589 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8590 { 8591 int err; 8592 struct ufs_query_req *request = NULL; 8593 struct ufs_query_res *response = NULL; 8594 struct ufs_dev_info *dev_info = &hba->dev_info; 8595 struct utp_upiu_query_v4_0 *upiu_data; 8596 8597 if (dev_info->wspecversion < 0x400) 8598 return; 8599 8600 ufshcd_dev_man_lock(hba); 8601 8602 ufshcd_init_query(hba, &request, &response, 8603 UPIU_QUERY_OPCODE_WRITE_ATTR, 8604 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8605 8606 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8607 8608 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8609 8610 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8611 8612 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8613 8614 if (err) 8615 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8616 __func__, err); 8617 8618 ufshcd_dev_man_unlock(hba); 8619 } 8620 8621 /** 8622 * ufshcd_add_lus - probe and add UFS logical units 8623 * @hba: per-adapter instance 8624 * 8625 * Return: 0 upon success; < 0 upon failure. 8626 */ 8627 static int ufshcd_add_lus(struct ufs_hba *hba) 8628 { 8629 int ret; 8630 8631 /* Add required well known logical units to scsi mid layer */ 8632 ret = ufshcd_scsi_add_wlus(hba); 8633 if (ret) 8634 goto out; 8635 8636 /* Initialize devfreq after UFS device is detected */ 8637 if (ufshcd_is_clkscaling_supported(hba)) { 8638 memcpy(&hba->clk_scaling.saved_pwr_info, 8639 &hba->pwr_info, 8640 sizeof(struct ufs_pa_layer_attr)); 8641 hba->clk_scaling.is_allowed = true; 8642 8643 ret = ufshcd_devfreq_init(hba); 8644 if (ret) 8645 goto out; 8646 8647 hba->clk_scaling.is_enabled = true; 8648 ufshcd_init_clk_scaling_sysfs(hba); 8649 } 8650 8651 ufs_bsg_probe(hba); 8652 scsi_scan_host(hba->host); 8653 8654 out: 8655 return ret; 8656 } 8657 8658 /* SDB - Single Doorbell */ 8659 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8660 { 8661 size_t ucdl_size, utrdl_size; 8662 8663 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8664 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8665 hba->ucdl_dma_addr); 8666 8667 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8668 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8669 hba->utrdl_dma_addr); 8670 8671 devm_kfree(hba->dev, hba->lrb); 8672 } 8673 8674 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8675 { 8676 int ret; 8677 int old_nutrs = hba->nutrs; 8678 8679 ret = ufshcd_mcq_decide_queue_depth(hba); 8680 if (ret < 0) 8681 return ret; 8682 8683 hba->nutrs = ret; 8684 ret = ufshcd_mcq_init(hba); 8685 if (ret) 8686 goto err; 8687 8688 /* 8689 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8690 * Number of supported tags in MCQ mode may be larger than SDB mode. 8691 */ 8692 if (hba->nutrs != old_nutrs) { 8693 ufshcd_release_sdb_queue(hba, old_nutrs); 8694 ret = ufshcd_memory_alloc(hba); 8695 if (ret) 8696 goto err; 8697 ufshcd_host_memory_configure(hba); 8698 } 8699 8700 ret = ufshcd_mcq_memory_alloc(hba); 8701 if (ret) 8702 goto err; 8703 8704 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8705 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8706 8707 return 0; 8708 err: 8709 hba->nutrs = old_nutrs; 8710 return ret; 8711 } 8712 8713 static void ufshcd_config_mcq(struct ufs_hba *hba) 8714 { 8715 int ret; 8716 u32 intrs; 8717 8718 ret = ufshcd_mcq_vops_config_esi(hba); 8719 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8720 8721 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8722 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8723 intrs &= ~MCQ_CQ_EVENT_STATUS; 8724 ufshcd_enable_intr(hba, intrs); 8725 ufshcd_mcq_make_queues_operational(hba); 8726 ufshcd_mcq_config_mac(hba, hba->nutrs); 8727 8728 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8729 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8730 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8731 hba->nutrs); 8732 } 8733 8734 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8735 { 8736 int ret; 8737 struct Scsi_Host *host = hba->host; 8738 8739 hba->ufshcd_state = UFSHCD_STATE_RESET; 8740 8741 ret = ufshcd_link_startup(hba); 8742 if (ret) 8743 return ret; 8744 8745 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8746 return ret; 8747 8748 /* Debug counters initialization */ 8749 ufshcd_clear_dbg_ufs_stats(hba); 8750 8751 /* UniPro link is active now */ 8752 ufshcd_set_link_active(hba); 8753 8754 /* Reconfigure MCQ upon reset */ 8755 if (hba->mcq_enabled && !init_dev_params) { 8756 ufshcd_config_mcq(hba); 8757 ufshcd_mcq_enable(hba); 8758 } 8759 8760 /* Verify device initialization by sending NOP OUT UPIU */ 8761 ret = ufshcd_verify_dev_init(hba); 8762 if (ret) 8763 return ret; 8764 8765 /* Initiate UFS initialization, and waiting until completion */ 8766 ret = ufshcd_complete_dev_init(hba); 8767 if (ret) 8768 return ret; 8769 8770 /* 8771 * Initialize UFS device parameters used by driver, these 8772 * parameters are associated with UFS descriptors. 8773 */ 8774 if (init_dev_params) { 8775 ret = ufshcd_device_params_init(hba); 8776 if (ret) 8777 return ret; 8778 if (is_mcq_supported(hba) && !hba->scsi_host_added) { 8779 ufshcd_mcq_enable(hba); 8780 ret = ufshcd_alloc_mcq(hba); 8781 if (!ret) { 8782 ufshcd_config_mcq(hba); 8783 } else { 8784 /* Continue with SDB mode */ 8785 ufshcd_mcq_disable(hba); 8786 use_mcq_mode = false; 8787 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 8788 ret); 8789 } 8790 ret = scsi_add_host(host, hba->dev); 8791 if (ret) { 8792 dev_err(hba->dev, "scsi_add_host failed\n"); 8793 return ret; 8794 } 8795 hba->scsi_host_added = true; 8796 } else if (is_mcq_supported(hba)) { 8797 /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */ 8798 ufshcd_config_mcq(hba); 8799 ufshcd_mcq_enable(hba); 8800 } 8801 } 8802 8803 ufshcd_tune_unipro_params(hba); 8804 8805 /* UFS device is also active now */ 8806 ufshcd_set_ufs_dev_active(hba); 8807 ufshcd_force_reset_auto_bkops(hba); 8808 8809 ufshcd_set_timestamp_attr(hba); 8810 schedule_delayed_work(&hba->ufs_rtc_update_work, 8811 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 8812 8813 /* Gear up to HS gear if supported */ 8814 if (hba->max_pwr_info.is_valid) { 8815 /* 8816 * Set the right value to bRefClkFreq before attempting to 8817 * switch to HS gears. 8818 */ 8819 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8820 ufshcd_set_dev_ref_clk(hba); 8821 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8822 if (ret) { 8823 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8824 __func__, ret); 8825 return ret; 8826 } 8827 } 8828 8829 return 0; 8830 } 8831 8832 /** 8833 * ufshcd_probe_hba - probe hba to detect device and initialize it 8834 * @hba: per-adapter instance 8835 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8836 * 8837 * Execute link-startup and verify device initialization 8838 * 8839 * Return: 0 upon success; < 0 upon failure. 8840 */ 8841 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8842 { 8843 ktime_t start = ktime_get(); 8844 unsigned long flags; 8845 int ret; 8846 8847 ret = ufshcd_device_init(hba, init_dev_params); 8848 if (ret) 8849 goto out; 8850 8851 if (!hba->pm_op_in_progress && 8852 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8853 /* Reset the device and controller before doing reinit */ 8854 ufshcd_device_reset(hba); 8855 ufs_put_device_desc(hba); 8856 ufshcd_hba_stop(hba); 8857 ufshcd_vops_reinit_notify(hba); 8858 ret = ufshcd_hba_enable(hba); 8859 if (ret) { 8860 dev_err(hba->dev, "Host controller enable failed\n"); 8861 ufshcd_print_evt_hist(hba); 8862 ufshcd_print_host_state(hba); 8863 goto out; 8864 } 8865 8866 /* Reinit the device */ 8867 ret = ufshcd_device_init(hba, init_dev_params); 8868 if (ret) 8869 goto out; 8870 } 8871 8872 ufshcd_print_pwr_info(hba); 8873 8874 /* 8875 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8876 * and for removable UFS card as well, hence always set the parameter. 8877 * Note: Error handler may issue the device reset hence resetting 8878 * bActiveICCLevel as well so it is always safe to set this here. 8879 */ 8880 ufshcd_set_active_icc_lvl(hba); 8881 8882 /* Enable UFS Write Booster if supported */ 8883 ufshcd_configure_wb(hba); 8884 8885 if (hba->ee_usr_mask) 8886 ufshcd_write_ee_control(hba); 8887 ufshcd_configure_auto_hibern8(hba); 8888 8889 out: 8890 spin_lock_irqsave(hba->host->host_lock, flags); 8891 if (ret) 8892 hba->ufshcd_state = UFSHCD_STATE_ERROR; 8893 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 8894 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 8895 spin_unlock_irqrestore(hba->host->host_lock, flags); 8896 8897 trace_ufshcd_init(dev_name(hba->dev), ret, 8898 ktime_to_us(ktime_sub(ktime_get(), start)), 8899 hba->curr_dev_pwr_mode, hba->uic_link_state); 8900 return ret; 8901 } 8902 8903 /** 8904 * ufshcd_async_scan - asynchronous execution for probing hba 8905 * @data: data pointer to pass to this function 8906 * @cookie: cookie data 8907 */ 8908 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8909 { 8910 struct ufs_hba *hba = (struct ufs_hba *)data; 8911 int ret; 8912 8913 down(&hba->host_sem); 8914 /* Initialize hba, detect and initialize UFS device */ 8915 ret = ufshcd_probe_hba(hba, true); 8916 up(&hba->host_sem); 8917 if (ret) 8918 goto out; 8919 8920 /* Probe and add UFS logical units */ 8921 ret = ufshcd_add_lus(hba); 8922 8923 out: 8924 pm_runtime_put_sync(hba->dev); 8925 8926 if (ret) 8927 dev_err(hba->dev, "%s failed: %d\n", __func__, ret); 8928 } 8929 8930 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8931 { 8932 struct ufs_hba *hba = shost_priv(scmd->device->host); 8933 8934 if (!hba->system_suspending) { 8935 /* Activate the error handler in the SCSI core. */ 8936 return SCSI_EH_NOT_HANDLED; 8937 } 8938 8939 /* 8940 * If we get here we know that no TMFs are outstanding and also that 8941 * the only pending command is a START STOP UNIT command. Handle the 8942 * timeout of that command directly to prevent a deadlock between 8943 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8944 */ 8945 ufshcd_link_recovery(hba); 8946 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8947 __func__, hba->outstanding_tasks); 8948 8949 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8950 } 8951 8952 static const struct attribute_group *ufshcd_driver_groups[] = { 8953 &ufs_sysfs_unit_descriptor_group, 8954 &ufs_sysfs_lun_attributes_group, 8955 NULL, 8956 }; 8957 8958 static struct ufs_hba_variant_params ufs_hba_vps = { 8959 .hba_enable_delay_us = 1000, 8960 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8961 .devfreq_profile.polling_ms = 100, 8962 .devfreq_profile.target = ufshcd_devfreq_target, 8963 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8964 .ondemand_data.upthreshold = 70, 8965 .ondemand_data.downdifferential = 5, 8966 }; 8967 8968 static const struct scsi_host_template ufshcd_driver_template = { 8969 .module = THIS_MODULE, 8970 .name = UFSHCD, 8971 .proc_name = UFSHCD, 8972 .map_queues = ufshcd_map_queues, 8973 .queuecommand = ufshcd_queuecommand, 8974 .mq_poll = ufshcd_poll, 8975 .slave_alloc = ufshcd_slave_alloc, 8976 .device_configure = ufshcd_device_configure, 8977 .slave_destroy = ufshcd_slave_destroy, 8978 .change_queue_depth = ufshcd_change_queue_depth, 8979 .eh_abort_handler = ufshcd_abort, 8980 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8981 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8982 .eh_timed_out = ufshcd_eh_timed_out, 8983 .this_id = -1, 8984 .sg_tablesize = SG_ALL, 8985 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8986 .max_sectors = SZ_1M / SECTOR_SIZE, 8987 .max_host_blocked = 1, 8988 .track_queue_depth = 1, 8989 .skip_settle_delay = 1, 8990 .sdev_groups = ufshcd_driver_groups, 8991 }; 8992 8993 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8994 int ua) 8995 { 8996 int ret; 8997 8998 if (!vreg) 8999 return 0; 9000 9001 /* 9002 * "set_load" operation shall be required on those regulators 9003 * which specifically configured current limitation. Otherwise 9004 * zero max_uA may cause unexpected behavior when regulator is 9005 * enabled or set as high power mode. 9006 */ 9007 if (!vreg->max_uA) 9008 return 0; 9009 9010 ret = regulator_set_load(vreg->reg, ua); 9011 if (ret < 0) { 9012 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 9013 __func__, vreg->name, ua, ret); 9014 } 9015 9016 return ret; 9017 } 9018 9019 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 9020 struct ufs_vreg *vreg) 9021 { 9022 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 9023 } 9024 9025 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 9026 struct ufs_vreg *vreg) 9027 { 9028 if (!vreg) 9029 return 0; 9030 9031 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 9032 } 9033 9034 static int ufshcd_config_vreg(struct device *dev, 9035 struct ufs_vreg *vreg, bool on) 9036 { 9037 if (regulator_count_voltages(vreg->reg) <= 0) 9038 return 0; 9039 9040 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 9041 } 9042 9043 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 9044 { 9045 int ret = 0; 9046 9047 if (!vreg || vreg->enabled) 9048 goto out; 9049 9050 ret = ufshcd_config_vreg(dev, vreg, true); 9051 if (!ret) 9052 ret = regulator_enable(vreg->reg); 9053 9054 if (!ret) 9055 vreg->enabled = true; 9056 else 9057 dev_err(dev, "%s: %s enable failed, err=%d\n", 9058 __func__, vreg->name, ret); 9059 out: 9060 return ret; 9061 } 9062 9063 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 9064 { 9065 int ret = 0; 9066 9067 if (!vreg || !vreg->enabled || vreg->always_on) 9068 goto out; 9069 9070 ret = regulator_disable(vreg->reg); 9071 9072 if (!ret) { 9073 /* ignore errors on applying disable config */ 9074 ufshcd_config_vreg(dev, vreg, false); 9075 vreg->enabled = false; 9076 } else { 9077 dev_err(dev, "%s: %s disable failed, err=%d\n", 9078 __func__, vreg->name, ret); 9079 } 9080 out: 9081 return ret; 9082 } 9083 9084 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 9085 { 9086 int ret = 0; 9087 struct device *dev = hba->dev; 9088 struct ufs_vreg_info *info = &hba->vreg_info; 9089 9090 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 9091 if (ret) 9092 goto out; 9093 9094 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 9095 if (ret) 9096 goto out; 9097 9098 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 9099 9100 out: 9101 if (ret) { 9102 ufshcd_toggle_vreg(dev, info->vccq2, false); 9103 ufshcd_toggle_vreg(dev, info->vccq, false); 9104 ufshcd_toggle_vreg(dev, info->vcc, false); 9105 } 9106 return ret; 9107 } 9108 9109 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9110 { 9111 struct ufs_vreg_info *info = &hba->vreg_info; 9112 9113 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9114 } 9115 9116 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9117 { 9118 int ret = 0; 9119 9120 if (!vreg) 9121 goto out; 9122 9123 vreg->reg = devm_regulator_get(dev, vreg->name); 9124 if (IS_ERR(vreg->reg)) { 9125 ret = PTR_ERR(vreg->reg); 9126 dev_err(dev, "%s: %s get failed, err=%d\n", 9127 __func__, vreg->name, ret); 9128 } 9129 out: 9130 return ret; 9131 } 9132 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9133 9134 static int ufshcd_init_vreg(struct ufs_hba *hba) 9135 { 9136 int ret = 0; 9137 struct device *dev = hba->dev; 9138 struct ufs_vreg_info *info = &hba->vreg_info; 9139 9140 ret = ufshcd_get_vreg(dev, info->vcc); 9141 if (ret) 9142 goto out; 9143 9144 ret = ufshcd_get_vreg(dev, info->vccq); 9145 if (!ret) 9146 ret = ufshcd_get_vreg(dev, info->vccq2); 9147 out: 9148 return ret; 9149 } 9150 9151 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9152 { 9153 struct ufs_vreg_info *info = &hba->vreg_info; 9154 9155 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9156 } 9157 9158 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9159 { 9160 int ret = 0; 9161 struct ufs_clk_info *clki; 9162 struct list_head *head = &hba->clk_list_head; 9163 unsigned long flags; 9164 ktime_t start = ktime_get(); 9165 bool clk_state_changed = false; 9166 9167 if (list_empty(head)) 9168 goto out; 9169 9170 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9171 if (ret) 9172 return ret; 9173 9174 list_for_each_entry(clki, head, list) { 9175 if (!IS_ERR_OR_NULL(clki->clk)) { 9176 /* 9177 * Don't disable clocks which are needed 9178 * to keep the link active. 9179 */ 9180 if (ufshcd_is_link_active(hba) && 9181 clki->keep_link_active) 9182 continue; 9183 9184 clk_state_changed = on ^ clki->enabled; 9185 if (on && !clki->enabled) { 9186 ret = clk_prepare_enable(clki->clk); 9187 if (ret) { 9188 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9189 __func__, clki->name, ret); 9190 goto out; 9191 } 9192 } else if (!on && clki->enabled) { 9193 clk_disable_unprepare(clki->clk); 9194 } 9195 clki->enabled = on; 9196 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9197 clki->name, on ? "en" : "dis"); 9198 } 9199 } 9200 9201 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9202 if (ret) 9203 return ret; 9204 9205 if (!ufshcd_is_clkscaling_supported(hba)) 9206 ufshcd_pm_qos_update(hba, on); 9207 out: 9208 if (ret) { 9209 list_for_each_entry(clki, head, list) { 9210 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9211 clk_disable_unprepare(clki->clk); 9212 } 9213 } else if (!ret && on) { 9214 spin_lock_irqsave(hba->host->host_lock, flags); 9215 hba->clk_gating.state = CLKS_ON; 9216 trace_ufshcd_clk_gating(dev_name(hba->dev), 9217 hba->clk_gating.state); 9218 spin_unlock_irqrestore(hba->host->host_lock, flags); 9219 } 9220 9221 if (clk_state_changed) 9222 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9223 (on ? "on" : "off"), 9224 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9225 return ret; 9226 } 9227 9228 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9229 { 9230 u32 freq; 9231 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9232 9233 if (ret) { 9234 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9235 return REF_CLK_FREQ_INVAL; 9236 } 9237 9238 return ufs_get_bref_clk_from_hz(freq); 9239 } 9240 9241 static int ufshcd_init_clocks(struct ufs_hba *hba) 9242 { 9243 int ret = 0; 9244 struct ufs_clk_info *clki; 9245 struct device *dev = hba->dev; 9246 struct list_head *head = &hba->clk_list_head; 9247 9248 if (list_empty(head)) 9249 goto out; 9250 9251 list_for_each_entry(clki, head, list) { 9252 if (!clki->name) 9253 continue; 9254 9255 clki->clk = devm_clk_get(dev, clki->name); 9256 if (IS_ERR(clki->clk)) { 9257 ret = PTR_ERR(clki->clk); 9258 dev_err(dev, "%s: %s clk get failed, %d\n", 9259 __func__, clki->name, ret); 9260 goto out; 9261 } 9262 9263 /* 9264 * Parse device ref clk freq as per device tree "ref_clk". 9265 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9266 * in ufshcd_alloc_host(). 9267 */ 9268 if (!strcmp(clki->name, "ref_clk")) 9269 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9270 9271 if (clki->max_freq) { 9272 ret = clk_set_rate(clki->clk, clki->max_freq); 9273 if (ret) { 9274 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9275 __func__, clki->name, 9276 clki->max_freq, ret); 9277 goto out; 9278 } 9279 clki->curr_freq = clki->max_freq; 9280 } 9281 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9282 clki->name, clk_get_rate(clki->clk)); 9283 } 9284 9285 /* Set Max. frequency for all clocks */ 9286 if (hba->use_pm_opp) { 9287 ret = ufshcd_opp_set_rate(hba, ULONG_MAX); 9288 if (ret) { 9289 dev_err(hba->dev, "%s: failed to set OPP: %d", __func__, 9290 ret); 9291 goto out; 9292 } 9293 } 9294 9295 out: 9296 return ret; 9297 } 9298 9299 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9300 { 9301 int err = 0; 9302 9303 if (!hba->vops) 9304 goto out; 9305 9306 err = ufshcd_vops_init(hba); 9307 if (err) 9308 dev_err_probe(hba->dev, err, 9309 "%s: variant %s init failed with err %d\n", 9310 __func__, ufshcd_get_var_name(hba), err); 9311 out: 9312 return err; 9313 } 9314 9315 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9316 { 9317 if (!hba->vops) 9318 return; 9319 9320 ufshcd_vops_exit(hba); 9321 } 9322 9323 static int ufshcd_hba_init(struct ufs_hba *hba) 9324 { 9325 int err; 9326 9327 /* 9328 * Handle host controller power separately from the UFS device power 9329 * rails as it will help controlling the UFS host controller power 9330 * collapse easily which is different than UFS device power collapse. 9331 * Also, enable the host controller power before we go ahead with rest 9332 * of the initialization here. 9333 */ 9334 err = ufshcd_init_hba_vreg(hba); 9335 if (err) 9336 goto out; 9337 9338 err = ufshcd_setup_hba_vreg(hba, true); 9339 if (err) 9340 goto out; 9341 9342 err = ufshcd_init_clocks(hba); 9343 if (err) 9344 goto out_disable_hba_vreg; 9345 9346 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9347 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9348 9349 err = ufshcd_setup_clocks(hba, true); 9350 if (err) 9351 goto out_disable_hba_vreg; 9352 9353 err = ufshcd_init_vreg(hba); 9354 if (err) 9355 goto out_disable_clks; 9356 9357 err = ufshcd_setup_vreg(hba, true); 9358 if (err) 9359 goto out_disable_clks; 9360 9361 err = ufshcd_variant_hba_init(hba); 9362 if (err) 9363 goto out_disable_vreg; 9364 9365 ufs_debugfs_hba_init(hba); 9366 ufs_fault_inject_hba_init(hba); 9367 9368 hba->is_powered = true; 9369 goto out; 9370 9371 out_disable_vreg: 9372 ufshcd_setup_vreg(hba, false); 9373 out_disable_clks: 9374 ufshcd_setup_clocks(hba, false); 9375 out_disable_hba_vreg: 9376 ufshcd_setup_hba_vreg(hba, false); 9377 out: 9378 return err; 9379 } 9380 9381 static void ufshcd_hba_exit(struct ufs_hba *hba) 9382 { 9383 if (hba->is_powered) { 9384 ufshcd_pm_qos_exit(hba); 9385 ufshcd_exit_clk_scaling(hba); 9386 ufshcd_exit_clk_gating(hba); 9387 if (hba->eh_wq) 9388 destroy_workqueue(hba->eh_wq); 9389 ufs_debugfs_hba_exit(hba); 9390 ufshcd_variant_hba_exit(hba); 9391 ufshcd_setup_vreg(hba, false); 9392 ufshcd_setup_clocks(hba, false); 9393 ufshcd_setup_hba_vreg(hba, false); 9394 hba->is_powered = false; 9395 ufs_put_device_desc(hba); 9396 } 9397 } 9398 9399 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9400 enum ufs_dev_pwr_mode pwr_mode, 9401 struct scsi_sense_hdr *sshdr) 9402 { 9403 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9404 struct scsi_failure failure_defs[] = { 9405 { 9406 .allowed = 2, 9407 .result = SCMD_FAILURE_RESULT_ANY, 9408 }, 9409 }; 9410 struct scsi_failures failures = { 9411 .failure_definitions = failure_defs, 9412 }; 9413 const struct scsi_exec_args args = { 9414 .failures = &failures, 9415 .sshdr = sshdr, 9416 .req_flags = BLK_MQ_REQ_PM, 9417 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9418 }; 9419 9420 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9421 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9422 &args); 9423 } 9424 9425 /** 9426 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9427 * power mode 9428 * @hba: per adapter instance 9429 * @pwr_mode: device power mode to set 9430 * 9431 * Return: 0 if requested power mode is set successfully; 9432 * < 0 if failed to set the requested power mode. 9433 */ 9434 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9435 enum ufs_dev_pwr_mode pwr_mode) 9436 { 9437 struct scsi_sense_hdr sshdr; 9438 struct scsi_device *sdp; 9439 unsigned long flags; 9440 int ret; 9441 9442 spin_lock_irqsave(hba->host->host_lock, flags); 9443 sdp = hba->ufs_device_wlun; 9444 if (sdp && scsi_device_online(sdp)) 9445 ret = scsi_device_get(sdp); 9446 else 9447 ret = -ENODEV; 9448 spin_unlock_irqrestore(hba->host->host_lock, flags); 9449 9450 if (ret) 9451 return ret; 9452 9453 /* 9454 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9455 * handling, which would wait for host to be resumed. Since we know 9456 * we are functional while we are here, skip host resume in error 9457 * handling context. 9458 */ 9459 hba->host->eh_noresume = 1; 9460 9461 /* 9462 * Current function would be generally called from the power management 9463 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9464 * already suspended childs. 9465 */ 9466 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9467 if (ret) { 9468 sdev_printk(KERN_WARNING, sdp, 9469 "START_STOP failed for power mode: %d, result %x\n", 9470 pwr_mode, ret); 9471 if (ret > 0) { 9472 if (scsi_sense_valid(&sshdr)) 9473 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9474 ret = -EIO; 9475 } 9476 } else { 9477 hba->curr_dev_pwr_mode = pwr_mode; 9478 } 9479 9480 scsi_device_put(sdp); 9481 hba->host->eh_noresume = 0; 9482 return ret; 9483 } 9484 9485 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9486 enum uic_link_state req_link_state, 9487 bool check_for_bkops) 9488 { 9489 int ret = 0; 9490 9491 if (req_link_state == hba->uic_link_state) 9492 return 0; 9493 9494 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9495 ret = ufshcd_uic_hibern8_enter(hba); 9496 if (!ret) { 9497 ufshcd_set_link_hibern8(hba); 9498 } else { 9499 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9500 __func__, ret); 9501 goto out; 9502 } 9503 } 9504 /* 9505 * If autobkops is enabled, link can't be turned off because 9506 * turning off the link would also turn off the device, except in the 9507 * case of DeepSleep where the device is expected to remain powered. 9508 */ 9509 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9510 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9511 /* 9512 * Let's make sure that link is in low power mode, we are doing 9513 * this currently by putting the link in Hibern8. Otherway to 9514 * put the link in low power mode is to send the DME end point 9515 * to device and then send the DME reset command to local 9516 * unipro. But putting the link in hibern8 is much faster. 9517 * 9518 * Note also that putting the link in Hibern8 is a requirement 9519 * for entering DeepSleep. 9520 */ 9521 ret = ufshcd_uic_hibern8_enter(hba); 9522 if (ret) { 9523 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9524 __func__, ret); 9525 goto out; 9526 } 9527 /* 9528 * Change controller state to "reset state" which 9529 * should also put the link in off/reset state 9530 */ 9531 ufshcd_hba_stop(hba); 9532 /* 9533 * TODO: Check if we need any delay to make sure that 9534 * controller is reset 9535 */ 9536 ufshcd_set_link_off(hba); 9537 } 9538 9539 out: 9540 return ret; 9541 } 9542 9543 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9544 { 9545 bool vcc_off = false; 9546 9547 /* 9548 * It seems some UFS devices may keep drawing more than sleep current 9549 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9550 * To avoid this situation, add 2ms delay before putting these UFS 9551 * rails in LPM mode. 9552 */ 9553 if (!ufshcd_is_link_active(hba) && 9554 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9555 usleep_range(2000, 2100); 9556 9557 /* 9558 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9559 * power. 9560 * 9561 * If UFS device and link is in OFF state, all power supplies (VCC, 9562 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9563 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9564 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9565 * 9566 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9567 * in low power state which would save some power. 9568 * 9569 * If Write Booster is enabled and the device needs to flush the WB 9570 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9571 */ 9572 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9573 !hba->dev_info.is_lu_power_on_wp) { 9574 ufshcd_setup_vreg(hba, false); 9575 vcc_off = true; 9576 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9577 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9578 vcc_off = true; 9579 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9580 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9581 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9582 } 9583 } 9584 9585 /* 9586 * Some UFS devices require delay after VCC power rail is turned-off. 9587 */ 9588 if (vcc_off && hba->vreg_info.vcc && 9589 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9590 usleep_range(5000, 5100); 9591 } 9592 9593 #ifdef CONFIG_PM 9594 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9595 { 9596 int ret = 0; 9597 9598 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9599 !hba->dev_info.is_lu_power_on_wp) { 9600 ret = ufshcd_setup_vreg(hba, true); 9601 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9602 if (!ufshcd_is_link_active(hba)) { 9603 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9604 if (ret) 9605 goto vcc_disable; 9606 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9607 if (ret) 9608 goto vccq_lpm; 9609 } 9610 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9611 } 9612 goto out; 9613 9614 vccq_lpm: 9615 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9616 vcc_disable: 9617 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9618 out: 9619 return ret; 9620 } 9621 #endif /* CONFIG_PM */ 9622 9623 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9624 { 9625 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9626 ufshcd_setup_hba_vreg(hba, false); 9627 } 9628 9629 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9630 { 9631 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9632 ufshcd_setup_hba_vreg(hba, true); 9633 } 9634 9635 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9636 { 9637 int ret = 0; 9638 bool check_for_bkops; 9639 enum ufs_pm_level pm_lvl; 9640 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9641 enum uic_link_state req_link_state; 9642 9643 hba->pm_op_in_progress = true; 9644 if (pm_op != UFS_SHUTDOWN_PM) { 9645 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9646 hba->rpm_lvl : hba->spm_lvl; 9647 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9648 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9649 } else { 9650 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9651 req_link_state = UIC_LINK_OFF_STATE; 9652 } 9653 9654 /* 9655 * If we can't transition into any of the low power modes 9656 * just gate the clocks. 9657 */ 9658 ufshcd_hold(hba); 9659 hba->clk_gating.is_suspended = true; 9660 9661 if (ufshcd_is_clkscaling_supported(hba)) 9662 ufshcd_clk_scaling_suspend(hba, true); 9663 9664 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9665 req_link_state == UIC_LINK_ACTIVE_STATE) { 9666 goto vops_suspend; 9667 } 9668 9669 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9670 (req_link_state == hba->uic_link_state)) 9671 goto enable_scaling; 9672 9673 /* UFS device & link must be active before we enter in this function */ 9674 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9675 /* Wait err handler finish or trigger err recovery */ 9676 if (!ufshcd_eh_in_progress(hba)) 9677 ufshcd_force_error_recovery(hba); 9678 ret = -EBUSY; 9679 goto enable_scaling; 9680 } 9681 9682 if (pm_op == UFS_RUNTIME_PM) { 9683 if (ufshcd_can_autobkops_during_suspend(hba)) { 9684 /* 9685 * The device is idle with no requests in the queue, 9686 * allow background operations if bkops status shows 9687 * that performance might be impacted. 9688 */ 9689 ret = ufshcd_bkops_ctrl(hba); 9690 if (ret) { 9691 /* 9692 * If return err in suspend flow, IO will hang. 9693 * Trigger error handler and break suspend for 9694 * error recovery. 9695 */ 9696 ufshcd_force_error_recovery(hba); 9697 ret = -EBUSY; 9698 goto enable_scaling; 9699 } 9700 } else { 9701 /* make sure that auto bkops is disabled */ 9702 ufshcd_disable_auto_bkops(hba); 9703 } 9704 /* 9705 * If device needs to do BKOP or WB buffer flush during 9706 * Hibern8, keep device power mode as "active power mode" 9707 * and VCC supply. 9708 */ 9709 hba->dev_info.b_rpm_dev_flush_capable = 9710 hba->auto_bkops_enabled || 9711 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9712 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9713 ufshcd_is_auto_hibern8_enabled(hba))) && 9714 ufshcd_wb_need_flush(hba)); 9715 } 9716 9717 flush_work(&hba->eeh_work); 9718 9719 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9720 if (ret) 9721 goto enable_scaling; 9722 9723 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9724 if (pm_op != UFS_RUNTIME_PM) 9725 /* ensure that bkops is disabled */ 9726 ufshcd_disable_auto_bkops(hba); 9727 9728 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9729 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9730 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9731 /* 9732 * If return err in suspend flow, IO will hang. 9733 * Trigger error handler and break suspend for 9734 * error recovery. 9735 */ 9736 ufshcd_force_error_recovery(hba); 9737 ret = -EBUSY; 9738 } 9739 if (ret) 9740 goto enable_scaling; 9741 } 9742 } 9743 9744 /* 9745 * In the case of DeepSleep, the device is expected to remain powered 9746 * with the link off, so do not check for bkops. 9747 */ 9748 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9749 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9750 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9751 /* 9752 * If return err in suspend flow, IO will hang. 9753 * Trigger error handler and break suspend for 9754 * error recovery. 9755 */ 9756 ufshcd_force_error_recovery(hba); 9757 ret = -EBUSY; 9758 } 9759 if (ret) 9760 goto set_dev_active; 9761 9762 vops_suspend: 9763 /* 9764 * Call vendor specific suspend callback. As these callbacks may access 9765 * vendor specific host controller register space call them before the 9766 * host clocks are ON. 9767 */ 9768 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9769 if (ret) 9770 goto set_link_active; 9771 9772 cancel_delayed_work_sync(&hba->ufs_rtc_update_work); 9773 goto out; 9774 9775 set_link_active: 9776 /* 9777 * Device hardware reset is required to exit DeepSleep. Also, for 9778 * DeepSleep, the link is off so host reset and restore will be done 9779 * further below. 9780 */ 9781 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9782 ufshcd_device_reset(hba); 9783 WARN_ON(!ufshcd_is_link_off(hba)); 9784 } 9785 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9786 ufshcd_set_link_active(hba); 9787 else if (ufshcd_is_link_off(hba)) 9788 ufshcd_host_reset_and_restore(hba); 9789 set_dev_active: 9790 /* Can also get here needing to exit DeepSleep */ 9791 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9792 ufshcd_device_reset(hba); 9793 ufshcd_host_reset_and_restore(hba); 9794 } 9795 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9796 ufshcd_disable_auto_bkops(hba); 9797 enable_scaling: 9798 if (ufshcd_is_clkscaling_supported(hba)) 9799 ufshcd_clk_scaling_suspend(hba, false); 9800 9801 hba->dev_info.b_rpm_dev_flush_capable = false; 9802 out: 9803 if (hba->dev_info.b_rpm_dev_flush_capable) { 9804 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9805 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9806 } 9807 9808 if (ret) { 9809 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9810 hba->clk_gating.is_suspended = false; 9811 ufshcd_release(hba); 9812 } 9813 hba->pm_op_in_progress = false; 9814 return ret; 9815 } 9816 9817 #ifdef CONFIG_PM 9818 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9819 { 9820 int ret; 9821 enum uic_link_state old_link_state = hba->uic_link_state; 9822 9823 hba->pm_op_in_progress = true; 9824 9825 /* 9826 * Call vendor specific resume callback. As these callbacks may access 9827 * vendor specific host controller register space call them when the 9828 * host clocks are ON. 9829 */ 9830 ret = ufshcd_vops_resume(hba, pm_op); 9831 if (ret) 9832 goto out; 9833 9834 /* For DeepSleep, the only supported option is to have the link off */ 9835 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9836 9837 if (ufshcd_is_link_hibern8(hba)) { 9838 ret = ufshcd_uic_hibern8_exit(hba); 9839 if (!ret) { 9840 ufshcd_set_link_active(hba); 9841 } else { 9842 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9843 __func__, ret); 9844 goto vendor_suspend; 9845 } 9846 } else if (ufshcd_is_link_off(hba)) { 9847 /* 9848 * A full initialization of the host and the device is 9849 * required since the link was put to off during suspend. 9850 * Note, in the case of DeepSleep, the device will exit 9851 * DeepSleep due to device reset. 9852 */ 9853 ret = ufshcd_reset_and_restore(hba); 9854 /* 9855 * ufshcd_reset_and_restore() should have already 9856 * set the link state as active 9857 */ 9858 if (ret || !ufshcd_is_link_active(hba)) 9859 goto vendor_suspend; 9860 } 9861 9862 if (!ufshcd_is_ufs_dev_active(hba)) { 9863 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9864 if (ret) 9865 goto set_old_link_state; 9866 ufshcd_set_timestamp_attr(hba); 9867 schedule_delayed_work(&hba->ufs_rtc_update_work, 9868 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 9869 } 9870 9871 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9872 ufshcd_enable_auto_bkops(hba); 9873 else 9874 /* 9875 * If BKOPs operations are urgently needed at this moment then 9876 * keep auto-bkops enabled or else disable it. 9877 */ 9878 ufshcd_bkops_ctrl(hba); 9879 9880 if (hba->ee_usr_mask) 9881 ufshcd_write_ee_control(hba); 9882 9883 if (ufshcd_is_clkscaling_supported(hba)) 9884 ufshcd_clk_scaling_suspend(hba, false); 9885 9886 if (hba->dev_info.b_rpm_dev_flush_capable) { 9887 hba->dev_info.b_rpm_dev_flush_capable = false; 9888 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9889 } 9890 9891 ufshcd_configure_auto_hibern8(hba); 9892 9893 goto out; 9894 9895 set_old_link_state: 9896 ufshcd_link_state_transition(hba, old_link_state, 0); 9897 vendor_suspend: 9898 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9899 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9900 out: 9901 if (ret) 9902 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9903 hba->clk_gating.is_suspended = false; 9904 ufshcd_release(hba); 9905 hba->pm_op_in_progress = false; 9906 return ret; 9907 } 9908 9909 static int ufshcd_wl_runtime_suspend(struct device *dev) 9910 { 9911 struct scsi_device *sdev = to_scsi_device(dev); 9912 struct ufs_hba *hba; 9913 int ret; 9914 ktime_t start = ktime_get(); 9915 9916 hba = shost_priv(sdev->host); 9917 9918 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9919 if (ret) 9920 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9921 9922 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9923 ktime_to_us(ktime_sub(ktime_get(), start)), 9924 hba->curr_dev_pwr_mode, hba->uic_link_state); 9925 9926 return ret; 9927 } 9928 9929 static int ufshcd_wl_runtime_resume(struct device *dev) 9930 { 9931 struct scsi_device *sdev = to_scsi_device(dev); 9932 struct ufs_hba *hba; 9933 int ret = 0; 9934 ktime_t start = ktime_get(); 9935 9936 hba = shost_priv(sdev->host); 9937 9938 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9939 if (ret) 9940 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9941 9942 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9943 ktime_to_us(ktime_sub(ktime_get(), start)), 9944 hba->curr_dev_pwr_mode, hba->uic_link_state); 9945 9946 return ret; 9947 } 9948 #endif 9949 9950 #ifdef CONFIG_PM_SLEEP 9951 static int ufshcd_wl_suspend(struct device *dev) 9952 { 9953 struct scsi_device *sdev = to_scsi_device(dev); 9954 struct ufs_hba *hba; 9955 int ret = 0; 9956 ktime_t start = ktime_get(); 9957 9958 hba = shost_priv(sdev->host); 9959 down(&hba->host_sem); 9960 hba->system_suspending = true; 9961 9962 if (pm_runtime_suspended(dev)) 9963 goto out; 9964 9965 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9966 if (ret) { 9967 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9968 up(&hba->host_sem); 9969 } 9970 9971 out: 9972 if (!ret) 9973 hba->is_sys_suspended = true; 9974 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9975 ktime_to_us(ktime_sub(ktime_get(), start)), 9976 hba->curr_dev_pwr_mode, hba->uic_link_state); 9977 9978 return ret; 9979 } 9980 9981 static int ufshcd_wl_resume(struct device *dev) 9982 { 9983 struct scsi_device *sdev = to_scsi_device(dev); 9984 struct ufs_hba *hba; 9985 int ret = 0; 9986 ktime_t start = ktime_get(); 9987 9988 hba = shost_priv(sdev->host); 9989 9990 if (pm_runtime_suspended(dev)) 9991 goto out; 9992 9993 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9994 if (ret) 9995 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9996 out: 9997 trace_ufshcd_wl_resume(dev_name(dev), ret, 9998 ktime_to_us(ktime_sub(ktime_get(), start)), 9999 hba->curr_dev_pwr_mode, hba->uic_link_state); 10000 if (!ret) 10001 hba->is_sys_suspended = false; 10002 hba->system_suspending = false; 10003 up(&hba->host_sem); 10004 return ret; 10005 } 10006 #endif 10007 10008 /** 10009 * ufshcd_suspend - helper function for suspend operations 10010 * @hba: per adapter instance 10011 * 10012 * This function will put disable irqs, turn off clocks 10013 * and set vreg and hba-vreg in lpm mode. 10014 * 10015 * Return: 0 upon success; < 0 upon failure. 10016 */ 10017 static int ufshcd_suspend(struct ufs_hba *hba) 10018 { 10019 int ret; 10020 10021 if (!hba->is_powered) 10022 return 0; 10023 /* 10024 * Disable the host irq as host controller as there won't be any 10025 * host controller transaction expected till resume. 10026 */ 10027 ufshcd_disable_irq(hba); 10028 ret = ufshcd_setup_clocks(hba, false); 10029 if (ret) { 10030 ufshcd_enable_irq(hba); 10031 return ret; 10032 } 10033 if (ufshcd_is_clkgating_allowed(hba)) { 10034 hba->clk_gating.state = CLKS_OFF; 10035 trace_ufshcd_clk_gating(dev_name(hba->dev), 10036 hba->clk_gating.state); 10037 } 10038 10039 ufshcd_vreg_set_lpm(hba); 10040 /* Put the host controller in low power mode if possible */ 10041 ufshcd_hba_vreg_set_lpm(hba); 10042 ufshcd_pm_qos_update(hba, false); 10043 return ret; 10044 } 10045 10046 #ifdef CONFIG_PM 10047 /** 10048 * ufshcd_resume - helper function for resume operations 10049 * @hba: per adapter instance 10050 * 10051 * This function basically turns on the regulators, clocks and 10052 * irqs of the hba. 10053 * 10054 * Return: 0 for success and non-zero for failure. 10055 */ 10056 static int ufshcd_resume(struct ufs_hba *hba) 10057 { 10058 int ret; 10059 10060 if (!hba->is_powered) 10061 return 0; 10062 10063 ufshcd_hba_vreg_set_hpm(hba); 10064 ret = ufshcd_vreg_set_hpm(hba); 10065 if (ret) 10066 goto out; 10067 10068 /* Make sure clocks are enabled before accessing controller */ 10069 ret = ufshcd_setup_clocks(hba, true); 10070 if (ret) 10071 goto disable_vreg; 10072 10073 /* enable the host irq as host controller would be active soon */ 10074 ufshcd_enable_irq(hba); 10075 10076 goto out; 10077 10078 disable_vreg: 10079 ufshcd_vreg_set_lpm(hba); 10080 out: 10081 if (ret) 10082 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 10083 return ret; 10084 } 10085 #endif /* CONFIG_PM */ 10086 10087 #ifdef CONFIG_PM_SLEEP 10088 /** 10089 * ufshcd_system_suspend - system suspend callback 10090 * @dev: Device associated with the UFS controller. 10091 * 10092 * Executed before putting the system into a sleep state in which the contents 10093 * of main memory are preserved. 10094 * 10095 * Return: 0 for success and non-zero for failure. 10096 */ 10097 int ufshcd_system_suspend(struct device *dev) 10098 { 10099 struct ufs_hba *hba = dev_get_drvdata(dev); 10100 int ret = 0; 10101 ktime_t start = ktime_get(); 10102 10103 if (pm_runtime_suspended(hba->dev)) 10104 goto out; 10105 10106 ret = ufshcd_suspend(hba); 10107 out: 10108 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 10109 ktime_to_us(ktime_sub(ktime_get(), start)), 10110 hba->curr_dev_pwr_mode, hba->uic_link_state); 10111 return ret; 10112 } 10113 EXPORT_SYMBOL(ufshcd_system_suspend); 10114 10115 /** 10116 * ufshcd_system_resume - system resume callback 10117 * @dev: Device associated with the UFS controller. 10118 * 10119 * Executed after waking the system up from a sleep state in which the contents 10120 * of main memory were preserved. 10121 * 10122 * Return: 0 for success and non-zero for failure. 10123 */ 10124 int ufshcd_system_resume(struct device *dev) 10125 { 10126 struct ufs_hba *hba = dev_get_drvdata(dev); 10127 ktime_t start = ktime_get(); 10128 int ret = 0; 10129 10130 if (pm_runtime_suspended(hba->dev)) 10131 goto out; 10132 10133 ret = ufshcd_resume(hba); 10134 10135 out: 10136 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10137 ktime_to_us(ktime_sub(ktime_get(), start)), 10138 hba->curr_dev_pwr_mode, hba->uic_link_state); 10139 10140 return ret; 10141 } 10142 EXPORT_SYMBOL(ufshcd_system_resume); 10143 #endif /* CONFIG_PM_SLEEP */ 10144 10145 #ifdef CONFIG_PM 10146 /** 10147 * ufshcd_runtime_suspend - runtime suspend callback 10148 * @dev: Device associated with the UFS controller. 10149 * 10150 * Check the description of ufshcd_suspend() function for more details. 10151 * 10152 * Return: 0 for success and non-zero for failure. 10153 */ 10154 int ufshcd_runtime_suspend(struct device *dev) 10155 { 10156 struct ufs_hba *hba = dev_get_drvdata(dev); 10157 int ret; 10158 ktime_t start = ktime_get(); 10159 10160 ret = ufshcd_suspend(hba); 10161 10162 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10163 ktime_to_us(ktime_sub(ktime_get(), start)), 10164 hba->curr_dev_pwr_mode, hba->uic_link_state); 10165 return ret; 10166 } 10167 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10168 10169 /** 10170 * ufshcd_runtime_resume - runtime resume routine 10171 * @dev: Device associated with the UFS controller. 10172 * 10173 * This function basically brings controller 10174 * to active state. Following operations are done in this function: 10175 * 10176 * 1. Turn on all the controller related clocks 10177 * 2. Turn ON VCC rail 10178 * 10179 * Return: 0 upon success; < 0 upon failure. 10180 */ 10181 int ufshcd_runtime_resume(struct device *dev) 10182 { 10183 struct ufs_hba *hba = dev_get_drvdata(dev); 10184 int ret; 10185 ktime_t start = ktime_get(); 10186 10187 ret = ufshcd_resume(hba); 10188 10189 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10190 ktime_to_us(ktime_sub(ktime_get(), start)), 10191 hba->curr_dev_pwr_mode, hba->uic_link_state); 10192 return ret; 10193 } 10194 EXPORT_SYMBOL(ufshcd_runtime_resume); 10195 #endif /* CONFIG_PM */ 10196 10197 static void ufshcd_wl_shutdown(struct device *dev) 10198 { 10199 struct scsi_device *sdev = to_scsi_device(dev); 10200 struct ufs_hba *hba = shost_priv(sdev->host); 10201 10202 down(&hba->host_sem); 10203 hba->shutting_down = true; 10204 up(&hba->host_sem); 10205 10206 /* Turn on everything while shutting down */ 10207 ufshcd_rpm_get_sync(hba); 10208 scsi_device_quiesce(sdev); 10209 shost_for_each_device(sdev, hba->host) { 10210 if (sdev == hba->ufs_device_wlun) 10211 continue; 10212 scsi_device_quiesce(sdev); 10213 } 10214 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10215 10216 /* 10217 * Next, turn off the UFS controller and the UFS regulators. Disable 10218 * clocks. 10219 */ 10220 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10221 ufshcd_suspend(hba); 10222 10223 hba->is_powered = false; 10224 } 10225 10226 /** 10227 * ufshcd_remove - de-allocate SCSI host and host memory space 10228 * data structure memory 10229 * @hba: per adapter instance 10230 */ 10231 void ufshcd_remove(struct ufs_hba *hba) 10232 { 10233 if (hba->ufs_device_wlun) 10234 ufshcd_rpm_get_sync(hba); 10235 ufs_hwmon_remove(hba); 10236 ufs_bsg_remove(hba); 10237 ufs_sysfs_remove_nodes(hba->dev); 10238 blk_mq_destroy_queue(hba->tmf_queue); 10239 blk_put_queue(hba->tmf_queue); 10240 blk_mq_free_tag_set(&hba->tmf_tag_set); 10241 if (hba->scsi_host_added) 10242 scsi_remove_host(hba->host); 10243 /* disable interrupts */ 10244 ufshcd_disable_intr(hba, hba->intr_mask); 10245 ufshcd_hba_stop(hba); 10246 ufshcd_hba_exit(hba); 10247 } 10248 EXPORT_SYMBOL_GPL(ufshcd_remove); 10249 10250 #ifdef CONFIG_PM_SLEEP 10251 int ufshcd_system_freeze(struct device *dev) 10252 { 10253 10254 return ufshcd_system_suspend(dev); 10255 10256 } 10257 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10258 10259 int ufshcd_system_restore(struct device *dev) 10260 { 10261 10262 struct ufs_hba *hba = dev_get_drvdata(dev); 10263 int ret; 10264 10265 ret = ufshcd_system_resume(dev); 10266 if (ret) 10267 return ret; 10268 10269 /* Configure UTRL and UTMRL base address registers */ 10270 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10271 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10272 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10273 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10274 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10275 REG_UTP_TASK_REQ_LIST_BASE_L); 10276 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10277 REG_UTP_TASK_REQ_LIST_BASE_H); 10278 /* 10279 * Make sure that UTRL and UTMRL base address registers 10280 * are updated with the latest queue addresses. Only after 10281 * updating these addresses, we can queue the new commands. 10282 */ 10283 ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H); 10284 10285 return 0; 10286 10287 } 10288 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10289 10290 int ufshcd_system_thaw(struct device *dev) 10291 { 10292 return ufshcd_system_resume(dev); 10293 } 10294 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10295 #endif /* CONFIG_PM_SLEEP */ 10296 10297 /** 10298 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10299 * @hba: pointer to Host Bus Adapter (HBA) 10300 */ 10301 void ufshcd_dealloc_host(struct ufs_hba *hba) 10302 { 10303 scsi_host_put(hba->host); 10304 } 10305 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10306 10307 /** 10308 * ufshcd_set_dma_mask - Set dma mask based on the controller 10309 * addressing capability 10310 * @hba: per adapter instance 10311 * 10312 * Return: 0 for success, non-zero for failure. 10313 */ 10314 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10315 { 10316 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10317 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10318 return 0; 10319 } 10320 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10321 } 10322 10323 /** 10324 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10325 * @dev: pointer to device handle 10326 * @hba_handle: driver private handle 10327 * 10328 * Return: 0 on success, non-zero value on failure. 10329 */ 10330 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10331 { 10332 struct Scsi_Host *host; 10333 struct ufs_hba *hba; 10334 int err = 0; 10335 10336 if (!dev) { 10337 dev_err(dev, 10338 "Invalid memory reference for dev is NULL\n"); 10339 err = -ENODEV; 10340 goto out_error; 10341 } 10342 10343 host = scsi_host_alloc(&ufshcd_driver_template, 10344 sizeof(struct ufs_hba)); 10345 if (!host) { 10346 dev_err(dev, "scsi_host_alloc failed\n"); 10347 err = -ENOMEM; 10348 goto out_error; 10349 } 10350 host->nr_maps = HCTX_TYPE_POLL + 1; 10351 hba = shost_priv(host); 10352 hba->host = host; 10353 hba->dev = dev; 10354 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10355 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10356 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10357 INIT_LIST_HEAD(&hba->clk_list_head); 10358 spin_lock_init(&hba->outstanding_lock); 10359 10360 *hba_handle = hba; 10361 10362 out_error: 10363 return err; 10364 } 10365 EXPORT_SYMBOL(ufshcd_alloc_host); 10366 10367 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10368 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10369 const struct blk_mq_queue_data *qd) 10370 { 10371 WARN_ON_ONCE(true); 10372 return BLK_STS_NOTSUPP; 10373 } 10374 10375 static const struct blk_mq_ops ufshcd_tmf_ops = { 10376 .queue_rq = ufshcd_queue_tmf, 10377 }; 10378 10379 /** 10380 * ufshcd_init - Driver initialization routine 10381 * @hba: per-adapter instance 10382 * @mmio_base: base register address 10383 * @irq: Interrupt line of device 10384 * 10385 * Return: 0 on success, non-zero value on failure. 10386 */ 10387 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10388 { 10389 int err; 10390 struct Scsi_Host *host = hba->host; 10391 struct device *dev = hba->dev; 10392 10393 /* 10394 * dev_set_drvdata() must be called before any callbacks are registered 10395 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10396 * sysfs). 10397 */ 10398 dev_set_drvdata(dev, hba); 10399 10400 if (!mmio_base) { 10401 dev_err(hba->dev, 10402 "Invalid memory reference for mmio_base is NULL\n"); 10403 err = -ENODEV; 10404 goto out_error; 10405 } 10406 10407 hba->mmio_base = mmio_base; 10408 hba->irq = irq; 10409 hba->vps = &ufs_hba_vps; 10410 10411 err = ufshcd_hba_init(hba); 10412 if (err) 10413 goto out_error; 10414 10415 /* Read capabilities registers */ 10416 err = ufshcd_hba_capabilities(hba); 10417 if (err) 10418 goto out_disable; 10419 10420 /* Get UFS version supported by the controller */ 10421 hba->ufs_version = ufshcd_get_ufs_version(hba); 10422 10423 /* Get Interrupt bit mask per version */ 10424 hba->intr_mask = ufshcd_get_intr_mask(hba); 10425 10426 err = ufshcd_set_dma_mask(hba); 10427 if (err) { 10428 dev_err(hba->dev, "set dma mask failed\n"); 10429 goto out_disable; 10430 } 10431 10432 /* Allocate memory for host memory space */ 10433 err = ufshcd_memory_alloc(hba); 10434 if (err) { 10435 dev_err(hba->dev, "Memory allocation failed\n"); 10436 goto out_disable; 10437 } 10438 10439 /* Configure LRB */ 10440 ufshcd_host_memory_configure(hba); 10441 10442 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10443 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10444 host->max_id = UFSHCD_MAX_ID; 10445 host->max_lun = UFS_MAX_LUNS; 10446 host->max_channel = UFSHCD_MAX_CHANNEL; 10447 host->unique_id = host->host_no; 10448 host->max_cmd_len = UFS_CDB_SIZE; 10449 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10450 10451 /* Use default RPM delay if host not set */ 10452 if (host->rpm_autosuspend_delay == 0) 10453 host->rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS; 10454 10455 hba->max_pwr_info.is_valid = false; 10456 10457 /* Initialize work queues */ 10458 hba->eh_wq = alloc_ordered_workqueue("ufs_eh_wq_%d", WQ_MEM_RECLAIM, 10459 hba->host->host_no); 10460 if (!hba->eh_wq) { 10461 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10462 __func__); 10463 err = -ENOMEM; 10464 goto out_disable; 10465 } 10466 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10467 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10468 10469 sema_init(&hba->host_sem, 1); 10470 10471 /* Initialize UIC command mutex */ 10472 mutex_init(&hba->uic_cmd_mutex); 10473 10474 /* Initialize mutex for device management commands */ 10475 mutex_init(&hba->dev_cmd.lock); 10476 10477 /* Initialize mutex for exception event control */ 10478 mutex_init(&hba->ee_ctrl_mutex); 10479 10480 mutex_init(&hba->wb_mutex); 10481 init_rwsem(&hba->clk_scaling_lock); 10482 10483 ufshcd_init_clk_gating(hba); 10484 10485 ufshcd_init_clk_scaling(hba); 10486 10487 /* 10488 * In order to avoid any spurious interrupt immediately after 10489 * registering UFS controller interrupt handler, clear any pending UFS 10490 * interrupt status and disable all the UFS interrupts. 10491 */ 10492 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10493 REG_INTERRUPT_STATUS); 10494 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10495 /* 10496 * Make sure that UFS interrupts are disabled and any pending interrupt 10497 * status is cleared before registering UFS interrupt handler. 10498 */ 10499 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 10500 10501 /* IRQ registration */ 10502 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10503 if (err) { 10504 dev_err(hba->dev, "request irq failed\n"); 10505 goto out_disable; 10506 } else { 10507 hba->is_irq_enabled = true; 10508 } 10509 10510 if (!is_mcq_supported(hba)) { 10511 if (!hba->lsdb_sup) { 10512 dev_err(hba->dev, "%s: failed to initialize (legacy doorbell mode not supported)\n", 10513 __func__); 10514 err = -EINVAL; 10515 goto out_disable; 10516 } 10517 err = scsi_add_host(host, hba->dev); 10518 if (err) { 10519 dev_err(hba->dev, "scsi_add_host failed\n"); 10520 goto out_disable; 10521 } 10522 hba->scsi_host_added = true; 10523 } 10524 10525 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10526 .nr_hw_queues = 1, 10527 .queue_depth = hba->nutmrs, 10528 .ops = &ufshcd_tmf_ops, 10529 .flags = BLK_MQ_F_NO_SCHED, 10530 }; 10531 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10532 if (err < 0) 10533 goto out_remove_scsi_host; 10534 hba->tmf_queue = blk_mq_alloc_queue(&hba->tmf_tag_set, NULL, NULL); 10535 if (IS_ERR(hba->tmf_queue)) { 10536 err = PTR_ERR(hba->tmf_queue); 10537 goto free_tmf_tag_set; 10538 } 10539 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10540 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10541 if (!hba->tmf_rqs) { 10542 err = -ENOMEM; 10543 goto free_tmf_queue; 10544 } 10545 10546 /* Reset the attached device */ 10547 ufshcd_device_reset(hba); 10548 10549 ufshcd_init_crypto(hba); 10550 10551 /* Host controller enable */ 10552 err = ufshcd_hba_enable(hba); 10553 if (err) { 10554 dev_err(hba->dev, "Host controller enable failed\n"); 10555 ufshcd_print_evt_hist(hba); 10556 ufshcd_print_host_state(hba); 10557 goto free_tmf_queue; 10558 } 10559 10560 /* 10561 * Set the default power management level for runtime and system PM. 10562 * Default power saving mode is to keep UFS link in Hibern8 state 10563 * and UFS device in sleep state. 10564 */ 10565 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10566 UFS_SLEEP_PWR_MODE, 10567 UIC_LINK_HIBERN8_STATE); 10568 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10569 UFS_SLEEP_PWR_MODE, 10570 UIC_LINK_HIBERN8_STATE); 10571 10572 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, ufshcd_rpm_dev_flush_recheck_work); 10573 INIT_DELAYED_WORK(&hba->ufs_rtc_update_work, ufshcd_rtc_work); 10574 10575 /* Set the default auto-hiberate idle timer value to 150 ms */ 10576 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10577 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10578 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10579 } 10580 10581 /* Hold auto suspend until async scan completes */ 10582 pm_runtime_get_sync(dev); 10583 atomic_set(&hba->scsi_block_reqs_cnt, 0); 10584 /* 10585 * We are assuming that device wasn't put in sleep/power-down 10586 * state exclusively during the boot stage before kernel. 10587 * This assumption helps avoid doing link startup twice during 10588 * ufshcd_probe_hba(). 10589 */ 10590 ufshcd_set_ufs_dev_active(hba); 10591 10592 async_schedule(ufshcd_async_scan, hba); 10593 ufs_sysfs_add_nodes(hba->dev); 10594 10595 device_enable_async_suspend(dev); 10596 ufshcd_pm_qos_init(hba); 10597 return 0; 10598 10599 free_tmf_queue: 10600 blk_mq_destroy_queue(hba->tmf_queue); 10601 blk_put_queue(hba->tmf_queue); 10602 free_tmf_tag_set: 10603 blk_mq_free_tag_set(&hba->tmf_tag_set); 10604 out_remove_scsi_host: 10605 if (hba->scsi_host_added) 10606 scsi_remove_host(hba->host); 10607 out_disable: 10608 hba->is_irq_enabled = false; 10609 ufshcd_hba_exit(hba); 10610 out_error: 10611 return err; 10612 } 10613 EXPORT_SYMBOL_GPL(ufshcd_init); 10614 10615 void ufshcd_resume_complete(struct device *dev) 10616 { 10617 struct ufs_hba *hba = dev_get_drvdata(dev); 10618 10619 if (hba->complete_put) { 10620 ufshcd_rpm_put(hba); 10621 hba->complete_put = false; 10622 } 10623 } 10624 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10625 10626 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10627 { 10628 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10629 enum ufs_dev_pwr_mode dev_pwr_mode; 10630 enum uic_link_state link_state; 10631 unsigned long flags; 10632 bool res; 10633 10634 spin_lock_irqsave(&dev->power.lock, flags); 10635 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10636 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10637 res = pm_runtime_suspended(dev) && 10638 hba->curr_dev_pwr_mode == dev_pwr_mode && 10639 hba->uic_link_state == link_state && 10640 !hba->dev_info.b_rpm_dev_flush_capable; 10641 spin_unlock_irqrestore(&dev->power.lock, flags); 10642 10643 return res; 10644 } 10645 10646 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10647 { 10648 struct ufs_hba *hba = dev_get_drvdata(dev); 10649 int ret; 10650 10651 /* 10652 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10653 * are same. And it doesn't wake up the device for system-suspend 10654 * if it's runtime suspended. But ufs doesn't follow that. 10655 * Refer ufshcd_resume_complete() 10656 */ 10657 if (hba->ufs_device_wlun) { 10658 /* Prevent runtime suspend */ 10659 ufshcd_rpm_get_noresume(hba); 10660 /* 10661 * Check if already runtime suspended in same state as system 10662 * suspend would be. 10663 */ 10664 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10665 /* RPM state is not ok for SPM, so runtime resume */ 10666 ret = ufshcd_rpm_resume(hba); 10667 if (ret < 0 && ret != -EACCES) { 10668 ufshcd_rpm_put(hba); 10669 return ret; 10670 } 10671 } 10672 hba->complete_put = true; 10673 } 10674 return 0; 10675 } 10676 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10677 10678 int ufshcd_suspend_prepare(struct device *dev) 10679 { 10680 return __ufshcd_suspend_prepare(dev, true); 10681 } 10682 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10683 10684 #ifdef CONFIG_PM_SLEEP 10685 static int ufshcd_wl_poweroff(struct device *dev) 10686 { 10687 struct scsi_device *sdev = to_scsi_device(dev); 10688 struct ufs_hba *hba = shost_priv(sdev->host); 10689 10690 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10691 return 0; 10692 } 10693 #endif 10694 10695 static int ufshcd_wl_probe(struct device *dev) 10696 { 10697 struct scsi_device *sdev = to_scsi_device(dev); 10698 10699 if (!is_device_wlun(sdev)) 10700 return -ENODEV; 10701 10702 blk_pm_runtime_init(sdev->request_queue, dev); 10703 pm_runtime_set_autosuspend_delay(dev, 0); 10704 pm_runtime_allow(dev); 10705 10706 return 0; 10707 } 10708 10709 static int ufshcd_wl_remove(struct device *dev) 10710 { 10711 pm_runtime_forbid(dev); 10712 return 0; 10713 } 10714 10715 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10716 #ifdef CONFIG_PM_SLEEP 10717 .suspend = ufshcd_wl_suspend, 10718 .resume = ufshcd_wl_resume, 10719 .freeze = ufshcd_wl_suspend, 10720 .thaw = ufshcd_wl_resume, 10721 .poweroff = ufshcd_wl_poweroff, 10722 .restore = ufshcd_wl_resume, 10723 #endif 10724 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10725 }; 10726 10727 static void ufshcd_check_header_layout(void) 10728 { 10729 /* 10730 * gcc compilers before version 10 cannot do constant-folding for 10731 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10732 * before. 10733 */ 10734 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10735 return; 10736 10737 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10738 .cci = 3})[0] != 3); 10739 10740 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10741 .ehs_length = 2})[1] != 2); 10742 10743 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10744 .enable_crypto = 1})[2] 10745 != 0x80); 10746 10747 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10748 .command_type = 5, 10749 .data_direction = 3, 10750 .interrupt = 1, 10751 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10752 10753 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10754 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10755 cpu_to_le32(0xdeadbeef)); 10756 10757 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10758 .ocs = 4})[8] != 4); 10759 10760 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10761 .cds = 5})[9] != 5); 10762 10763 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10764 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10765 cpu_to_le32(0xbadcafe)); 10766 10767 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10768 .iid = 0xf })[4] != 0xf0); 10769 10770 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10771 .command_set_type = 0xf })[4] != 0xf); 10772 } 10773 10774 /* 10775 * ufs_dev_wlun_template - describes ufs device wlun 10776 * ufs-device wlun - used to send pm commands 10777 * All luns are consumers of ufs-device wlun. 10778 * 10779 * Currently, no sd driver is present for wluns. 10780 * Hence the no specific pm operations are performed. 10781 * With ufs design, SSU should be sent to ufs-device wlun. 10782 * Hence register a scsi driver for ufs wluns only. 10783 */ 10784 static struct scsi_driver ufs_dev_wlun_template = { 10785 .gendrv = { 10786 .name = "ufs_device_wlun", 10787 .probe = ufshcd_wl_probe, 10788 .remove = ufshcd_wl_remove, 10789 .pm = &ufshcd_wl_pm_ops, 10790 .shutdown = ufshcd_wl_shutdown, 10791 }, 10792 }; 10793 10794 static int __init ufshcd_core_init(void) 10795 { 10796 int ret; 10797 10798 ufshcd_check_header_layout(); 10799 10800 ufs_debugfs_init(); 10801 10802 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10803 if (ret) 10804 ufs_debugfs_exit(); 10805 return ret; 10806 } 10807 10808 static void __exit ufshcd_core_exit(void) 10809 { 10810 ufs_debugfs_exit(); 10811 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10812 } 10813 10814 module_init(ufshcd_core_init); 10815 module_exit(ufshcd_core_exit); 10816 10817 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10818 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10819 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10820 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10821 MODULE_LICENSE("GPL"); 10822