1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/pm_opp.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/sched/clock.h> 26 #include <linux/iopoll.h> 27 #include <scsi/scsi_cmnd.h> 28 #include <scsi/scsi_dbg.h> 29 #include <scsi/scsi_driver.h> 30 #include <scsi/scsi_eh.h> 31 #include "ufshcd-priv.h" 32 #include <ufs/ufs_quirks.h> 33 #include <ufs/unipro.h> 34 #include "ufs-sysfs.h" 35 #include "ufs-debugfs.h" 36 #include "ufs-fault-injection.h" 37 #include "ufs_bsg.h" 38 #include "ufshcd-crypto.h" 39 #include <asm/unaligned.h> 40 41 #define CREATE_TRACE_POINTS 42 #include <trace/events/ufs.h> 43 44 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 45 UTP_TASK_REQ_COMPL |\ 46 UFSHCD_ERROR_MASK) 47 48 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 49 UFSHCD_ERROR_MASK |\ 50 MCQ_CQ_EVENT_STATUS) 51 52 53 /* UIC command timeout, unit: ms */ 54 #define UIC_CMD_TIMEOUT 500 55 56 /* NOP OUT retries waiting for NOP IN response */ 57 #define NOP_OUT_RETRIES 10 58 /* Timeout after 50 msecs if NOP OUT hangs without response */ 59 #define NOP_OUT_TIMEOUT 50 /* msecs */ 60 61 /* Query request retries */ 62 #define QUERY_REQ_RETRIES 3 63 /* Query request timeout */ 64 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 65 66 /* Advanced RPMB request timeout */ 67 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 68 69 /* Task management command timeout */ 70 #define TM_CMD_TIMEOUT 100 /* msecs */ 71 72 /* maximum number of retries for a general UIC command */ 73 #define UFS_UIC_COMMAND_RETRIES 3 74 75 /* maximum number of link-startup retries */ 76 #define DME_LINKSTARTUP_RETRIES 3 77 78 /* maximum number of reset retries before giving up */ 79 #define MAX_HOST_RESET_RETRIES 5 80 81 /* Maximum number of error handler retries before giving up */ 82 #define MAX_ERR_HANDLER_RETRIES 5 83 84 /* Expose the flag value from utp_upiu_query.value */ 85 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 86 87 /* Interrupt aggregation default timeout, unit: 40us */ 88 #define INT_AGGR_DEF_TO 0x02 89 90 /* default delay of autosuspend: 2000 ms */ 91 #define RPM_AUTOSUSPEND_DELAY_MS 2000 92 93 /* Default delay of RPM device flush delayed work */ 94 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 95 96 /* Default value of wait time before gating device ref clock */ 97 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 98 99 /* Polling time to wait for fDeviceInit */ 100 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 101 102 /* Default RTC update every 10 seconds */ 103 #define UFS_RTC_UPDATE_INTERVAL_MS (10 * MSEC_PER_SEC) 104 105 /* bMaxNumOfRTT is equal to two after device manufacturing */ 106 #define DEFAULT_MAX_NUM_RTT 2 107 108 /* UFSHC 4.0 compliant HC support this mode. */ 109 static bool use_mcq_mode = true; 110 111 static bool is_mcq_supported(struct ufs_hba *hba) 112 { 113 return hba->mcq_sup && use_mcq_mode; 114 } 115 116 module_param(use_mcq_mode, bool, 0644); 117 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 118 119 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 120 ({ \ 121 int _ret; \ 122 if (_on) \ 123 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 124 else \ 125 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 126 _ret; \ 127 }) 128 129 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 130 size_t __len = (len); \ 131 print_hex_dump(KERN_ERR, prefix_str, \ 132 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 133 16, 4, buf, __len, false); \ 134 } while (0) 135 136 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 137 const char *prefix) 138 { 139 u32 *regs; 140 size_t pos; 141 142 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 143 return -EINVAL; 144 145 regs = kzalloc(len, GFP_ATOMIC); 146 if (!regs) 147 return -ENOMEM; 148 149 for (pos = 0; pos < len; pos += 4) { 150 if (offset == 0 && 151 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 152 pos <= REG_UIC_ERROR_CODE_DME) 153 continue; 154 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 155 } 156 157 ufshcd_hex_dump(prefix, regs, len); 158 kfree(regs); 159 160 return 0; 161 } 162 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 163 164 enum { 165 UFSHCD_MAX_CHANNEL = 0, 166 UFSHCD_MAX_ID = 1, 167 }; 168 169 static const char *const ufshcd_state_name[] = { 170 [UFSHCD_STATE_RESET] = "reset", 171 [UFSHCD_STATE_OPERATIONAL] = "operational", 172 [UFSHCD_STATE_ERROR] = "error", 173 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 174 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 175 }; 176 177 /* UFSHCD error handling flags */ 178 enum { 179 UFSHCD_EH_IN_PROGRESS = (1 << 0), 180 }; 181 182 /* UFSHCD UIC layer error flags */ 183 enum { 184 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 185 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 186 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 187 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 188 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 189 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 190 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 191 }; 192 193 #define ufshcd_set_eh_in_progress(h) \ 194 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 195 #define ufshcd_eh_in_progress(h) \ 196 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 197 #define ufshcd_clear_eh_in_progress(h) \ 198 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 199 200 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 201 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 202 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 203 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 204 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 205 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 206 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 207 /* 208 * For DeepSleep, the link is first put in hibern8 and then off. 209 * Leaving the link in hibern8 is not supported. 210 */ 211 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 212 }; 213 214 static inline enum ufs_dev_pwr_mode 215 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 216 { 217 return ufs_pm_lvl_states[lvl].dev_state; 218 } 219 220 static inline enum uic_link_state 221 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 222 { 223 return ufs_pm_lvl_states[lvl].link_state; 224 } 225 226 static inline enum ufs_pm_level 227 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 228 enum uic_link_state link_state) 229 { 230 enum ufs_pm_level lvl; 231 232 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 233 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 234 (ufs_pm_lvl_states[lvl].link_state == link_state)) 235 return lvl; 236 } 237 238 /* if no match found, return the level 0 */ 239 return UFS_PM_LVL_0; 240 } 241 242 static bool ufshcd_is_ufs_dev_busy(struct ufs_hba *hba) 243 { 244 return (hba->clk_gating.active_reqs || hba->outstanding_reqs || hba->outstanding_tasks || 245 hba->active_uic_cmd || hba->uic_async_done); 246 } 247 248 static const struct ufs_dev_quirk ufs_fixups[] = { 249 /* UFS cards deviations table */ 250 { .wmanufacturerid = UFS_VENDOR_MICRON, 251 .model = UFS_ANY_MODEL, 252 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 253 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 254 .model = UFS_ANY_MODEL, 255 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 256 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 257 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 258 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 259 .model = UFS_ANY_MODEL, 260 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 261 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 262 .model = "hB8aL1" /*H28U62301AMR*/, 263 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 264 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 265 .model = UFS_ANY_MODEL, 266 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 267 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 268 .model = "THGLF2G9C8KBADG", 269 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 270 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 271 .model = "THGLF2G9D8KBADG", 272 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 273 {} 274 }; 275 276 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 277 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 278 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 279 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 280 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 281 static void ufshcd_hba_exit(struct ufs_hba *hba); 282 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 283 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 284 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 285 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 286 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 287 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 288 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 289 bool scale_up); 290 static irqreturn_t ufshcd_intr(int irq, void *__hba); 291 static int ufshcd_change_power_mode(struct ufs_hba *hba, 292 struct ufs_pa_layer_attr *pwr_mode); 293 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 294 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 295 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 296 struct ufs_vreg *vreg); 297 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 298 bool enable); 299 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 300 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 301 302 void ufshcd_enable_irq(struct ufs_hba *hba) 303 { 304 if (!hba->is_irq_enabled) { 305 enable_irq(hba->irq); 306 hba->is_irq_enabled = true; 307 } 308 } 309 EXPORT_SYMBOL_GPL(ufshcd_enable_irq); 310 311 void ufshcd_disable_irq(struct ufs_hba *hba) 312 { 313 if (hba->is_irq_enabled) { 314 disable_irq(hba->irq); 315 hba->is_irq_enabled = false; 316 } 317 } 318 EXPORT_SYMBOL_GPL(ufshcd_disable_irq); 319 320 static void ufshcd_configure_wb(struct ufs_hba *hba) 321 { 322 if (!ufshcd_is_wb_allowed(hba)) 323 return; 324 325 ufshcd_wb_toggle(hba, true); 326 327 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 328 329 if (ufshcd_is_wb_buf_flush_allowed(hba)) 330 ufshcd_wb_toggle_buf_flush(hba, true); 331 } 332 333 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba) 334 { 335 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt)) 336 scsi_unblock_requests(hba->host); 337 } 338 339 static void ufshcd_scsi_block_requests(struct ufs_hba *hba) 340 { 341 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1) 342 scsi_block_requests(hba->host); 343 } 344 345 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 346 enum ufs_trace_str_t str_t) 347 { 348 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 349 struct utp_upiu_header *header; 350 351 if (!trace_ufshcd_upiu_enabled()) 352 return; 353 354 if (str_t == UFS_CMD_SEND) 355 header = &rq->header; 356 else 357 header = &hba->lrb[tag].ucd_rsp_ptr->header; 358 359 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 360 UFS_TSF_CDB); 361 } 362 363 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 364 enum ufs_trace_str_t str_t, 365 struct utp_upiu_req *rq_rsp) 366 { 367 if (!trace_ufshcd_upiu_enabled()) 368 return; 369 370 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 371 &rq_rsp->qr, UFS_TSF_OSF); 372 } 373 374 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 375 enum ufs_trace_str_t str_t) 376 { 377 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 378 379 if (!trace_ufshcd_upiu_enabled()) 380 return; 381 382 if (str_t == UFS_TM_SEND) 383 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 384 &descp->upiu_req.req_header, 385 &descp->upiu_req.input_param1, 386 UFS_TSF_TM_INPUT); 387 else 388 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 389 &descp->upiu_rsp.rsp_header, 390 &descp->upiu_rsp.output_param1, 391 UFS_TSF_TM_OUTPUT); 392 } 393 394 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 395 const struct uic_command *ucmd, 396 enum ufs_trace_str_t str_t) 397 { 398 u32 cmd; 399 400 if (!trace_ufshcd_uic_command_enabled()) 401 return; 402 403 if (str_t == UFS_CMD_SEND) 404 cmd = ucmd->command; 405 else 406 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 407 408 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 409 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 410 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 411 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 412 } 413 414 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 415 enum ufs_trace_str_t str_t) 416 { 417 u64 lba = 0; 418 u8 opcode = 0, group_id = 0; 419 u32 doorbell = 0; 420 u32 intr; 421 int hwq_id = -1; 422 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 423 struct scsi_cmnd *cmd = lrbp->cmd; 424 struct request *rq = scsi_cmd_to_rq(cmd); 425 int transfer_len = -1; 426 427 if (!cmd) 428 return; 429 430 /* trace UPIU also */ 431 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 432 if (!trace_ufshcd_command_enabled()) 433 return; 434 435 opcode = cmd->cmnd[0]; 436 437 if (opcode == READ_10 || opcode == WRITE_10) { 438 /* 439 * Currently we only fully trace read(10) and write(10) commands 440 */ 441 transfer_len = 442 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 443 lba = scsi_get_lba(cmd); 444 if (opcode == WRITE_10) 445 group_id = lrbp->cmd->cmnd[6]; 446 } else if (opcode == UNMAP) { 447 /* 448 * The number of Bytes to be unmapped beginning with the lba. 449 */ 450 transfer_len = blk_rq_bytes(rq); 451 lba = scsi_get_lba(cmd); 452 } 453 454 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 455 456 if (hba->mcq_enabled) { 457 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 458 459 hwq_id = hwq->id; 460 } else { 461 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 462 } 463 trace_ufshcd_command(cmd->device, str_t, tag, doorbell, hwq_id, 464 transfer_len, intr, lba, opcode, group_id); 465 } 466 467 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 468 { 469 struct ufs_clk_info *clki; 470 struct list_head *head = &hba->clk_list_head; 471 472 if (list_empty(head)) 473 return; 474 475 list_for_each_entry(clki, head, list) { 476 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 477 clki->max_freq) 478 dev_err(hba->dev, "clk: %s, rate: %u\n", 479 clki->name, clki->curr_freq); 480 } 481 } 482 483 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 484 const char *err_name) 485 { 486 int i; 487 bool found = false; 488 const struct ufs_event_hist *e; 489 490 if (id >= UFS_EVT_CNT) 491 return; 492 493 e = &hba->ufs_stats.event[id]; 494 495 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 496 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 497 498 if (e->tstamp[p] == 0) 499 continue; 500 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 501 e->val[p], div_u64(e->tstamp[p], 1000)); 502 found = true; 503 } 504 505 if (!found) 506 dev_err(hba->dev, "No record of %s\n", err_name); 507 else 508 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 509 } 510 511 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 512 { 513 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 514 515 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 516 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 517 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 518 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 519 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 520 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 521 "auto_hibern8_err"); 522 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 523 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 524 "link_startup_fail"); 525 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 526 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 527 "suspend_fail"); 528 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 529 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 530 "wlun suspend_fail"); 531 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 532 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 533 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 534 535 ufshcd_vops_dbg_register_dump(hba); 536 } 537 538 static 539 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 540 { 541 const struct ufshcd_lrb *lrbp; 542 int prdt_length; 543 544 lrbp = &hba->lrb[tag]; 545 546 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 547 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 548 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 549 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 550 dev_err(hba->dev, 551 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 552 tag, (u64)lrbp->utrd_dma_addr); 553 554 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 555 sizeof(struct utp_transfer_req_desc)); 556 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 557 (u64)lrbp->ucd_req_dma_addr); 558 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 559 sizeof(struct utp_upiu_req)); 560 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 561 (u64)lrbp->ucd_rsp_dma_addr); 562 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 563 sizeof(struct utp_upiu_rsp)); 564 565 prdt_length = le16_to_cpu( 566 lrbp->utr_descriptor_ptr->prd_table_length); 567 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 568 prdt_length /= ufshcd_sg_entry_size(hba); 569 570 dev_err(hba->dev, 571 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 572 tag, prdt_length, 573 (u64)lrbp->ucd_prdt_dma_addr); 574 575 if (pr_prdt) 576 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 577 ufshcd_sg_entry_size(hba) * prdt_length); 578 } 579 580 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 581 { 582 struct scsi_device *sdev = req->q->queuedata; 583 struct Scsi_Host *shost = sdev->host; 584 struct ufs_hba *hba = shost_priv(shost); 585 586 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 587 588 return true; 589 } 590 591 /** 592 * ufshcd_print_trs_all - print trs for all started requests. 593 * @hba: per-adapter instance. 594 * @pr_prdt: need to print prdt or not. 595 */ 596 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 597 { 598 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 599 } 600 601 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 602 { 603 int tag; 604 605 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 606 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 607 608 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 609 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 610 } 611 } 612 613 static void ufshcd_print_host_state(struct ufs_hba *hba) 614 { 615 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 616 617 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 618 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 619 hba->outstanding_reqs, hba->outstanding_tasks); 620 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 621 hba->saved_err, hba->saved_uic_err); 622 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 623 hba->curr_dev_pwr_mode, hba->uic_link_state); 624 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 625 hba->pm_op_in_progress, hba->is_sys_suspended); 626 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 627 hba->auto_bkops_enabled, hba->host->host_self_blocked); 628 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 629 dev_err(hba->dev, 630 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 631 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 632 hba->ufs_stats.hibern8_exit_cnt); 633 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 634 div_u64(hba->ufs_stats.last_intr_ts, 1000), 635 hba->ufs_stats.last_intr_status); 636 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 637 hba->eh_flags, hba->req_abort_count); 638 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 639 hba->ufs_version, hba->capabilities, hba->caps); 640 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 641 hba->dev_quirks); 642 if (sdev_ufs) 643 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 644 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 645 646 ufshcd_print_clk_freqs(hba); 647 } 648 649 /** 650 * ufshcd_print_pwr_info - print power params as saved in hba 651 * power info 652 * @hba: per-adapter instance 653 */ 654 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 655 { 656 static const char * const names[] = { 657 "INVALID MODE", 658 "FAST MODE", 659 "SLOW_MODE", 660 "INVALID MODE", 661 "FASTAUTO_MODE", 662 "SLOWAUTO_MODE", 663 "INVALID MODE", 664 }; 665 666 /* 667 * Using dev_dbg to avoid messages during runtime PM to avoid 668 * never-ending cycles of messages written back to storage by user space 669 * causing runtime resume, causing more messages and so on. 670 */ 671 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 672 __func__, 673 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 674 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 675 names[hba->pwr_info.pwr_rx], 676 names[hba->pwr_info.pwr_tx], 677 hba->pwr_info.hs_rate); 678 } 679 680 static void ufshcd_device_reset(struct ufs_hba *hba) 681 { 682 int err; 683 684 err = ufshcd_vops_device_reset(hba); 685 686 if (!err) { 687 ufshcd_set_ufs_dev_active(hba); 688 if (ufshcd_is_wb_allowed(hba)) { 689 hba->dev_info.wb_enabled = false; 690 hba->dev_info.wb_buf_flush_enabled = false; 691 } 692 if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 693 hba->dev_info.rtc_time_baseline = 0; 694 } 695 if (err != -EOPNOTSUPP) 696 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 697 } 698 699 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 700 { 701 if (!us) 702 return; 703 704 if (us < 10) 705 udelay(us); 706 else 707 usleep_range(us, us + tolerance); 708 } 709 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 710 711 /** 712 * ufshcd_wait_for_register - wait for register value to change 713 * @hba: per-adapter interface 714 * @reg: mmio register offset 715 * @mask: mask to apply to the read register value 716 * @val: value to wait for 717 * @interval_us: polling interval in microseconds 718 * @timeout_ms: timeout in milliseconds 719 * 720 * Return: -ETIMEDOUT on error, zero on success. 721 */ 722 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 723 u32 val, unsigned long interval_us, 724 unsigned long timeout_ms) 725 { 726 int err = 0; 727 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 728 729 /* ignore bits that we don't intend to wait on */ 730 val = val & mask; 731 732 while ((ufshcd_readl(hba, reg) & mask) != val) { 733 usleep_range(interval_us, interval_us + 50); 734 if (time_after(jiffies, timeout)) { 735 if ((ufshcd_readl(hba, reg) & mask) != val) 736 err = -ETIMEDOUT; 737 break; 738 } 739 } 740 741 return err; 742 } 743 744 /** 745 * ufshcd_get_intr_mask - Get the interrupt bit mask 746 * @hba: Pointer to adapter instance 747 * 748 * Return: interrupt bit mask per version 749 */ 750 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 751 { 752 if (hba->ufs_version <= ufshci_version(2, 0)) 753 return INTERRUPT_MASK_ALL_VER_11; 754 755 return INTERRUPT_MASK_ALL_VER_21; 756 } 757 758 /** 759 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 760 * @hba: Pointer to adapter instance 761 * 762 * Return: UFSHCI version supported by the controller 763 */ 764 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 765 { 766 u32 ufshci_ver; 767 768 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 769 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 770 else 771 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 772 773 /* 774 * UFSHCI v1.x uses a different version scheme, in order 775 * to allow the use of comparisons with the ufshci_version 776 * function, we convert it to the same scheme as ufs 2.0+. 777 */ 778 if (ufshci_ver & 0x00010000) 779 return ufshci_version(1, ufshci_ver & 0x00000100); 780 781 return ufshci_ver; 782 } 783 784 /** 785 * ufshcd_is_device_present - Check if any device connected to 786 * the host controller 787 * @hba: pointer to adapter instance 788 * 789 * Return: true if device present, false if no device detected 790 */ 791 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 792 { 793 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 794 } 795 796 /** 797 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 798 * @lrbp: pointer to local command reference block 799 * @cqe: pointer to the completion queue entry 800 * 801 * This function is used to get the OCS field from UTRD 802 * 803 * Return: the OCS field in the UTRD. 804 */ 805 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 806 struct cq_entry *cqe) 807 { 808 if (cqe) 809 return le32_to_cpu(cqe->status) & MASK_OCS; 810 811 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 812 } 813 814 /** 815 * ufshcd_utrl_clear() - Clear requests from the controller request list. 816 * @hba: per adapter instance 817 * @mask: mask with one bit set for each request to be cleared 818 */ 819 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 820 { 821 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 822 mask = ~mask; 823 /* 824 * From the UFSHCI specification: "UTP Transfer Request List CLear 825 * Register (UTRLCLR): This field is bit significant. Each bit 826 * corresponds to a slot in the UTP Transfer Request List, where bit 0 827 * corresponds to request slot 0. A bit in this field is set to ‘0’ 828 * by host software to indicate to the host controller that a transfer 829 * request slot is cleared. The host controller 830 * shall free up any resources associated to the request slot 831 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 832 * host software indicates no change to request slots by setting the 833 * associated bits in this field to ‘1’. Bits in this field shall only 834 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 835 */ 836 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 837 } 838 839 /** 840 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 841 * @hba: per adapter instance 842 * @pos: position of the bit to be cleared 843 */ 844 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 845 { 846 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 847 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 848 else 849 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 850 } 851 852 /** 853 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 854 * @reg: Register value of host controller status 855 * 856 * Return: 0 on success; a positive value if failed. 857 */ 858 static inline int ufshcd_get_lists_status(u32 reg) 859 { 860 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 861 } 862 863 /** 864 * ufshcd_get_uic_cmd_result - Get the UIC command result 865 * @hba: Pointer to adapter instance 866 * 867 * This function gets the result of UIC command completion 868 * 869 * Return: 0 on success; non-zero value on error. 870 */ 871 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 872 { 873 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 874 MASK_UIC_COMMAND_RESULT; 875 } 876 877 /** 878 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 879 * @hba: Pointer to adapter instance 880 * 881 * This function gets UIC command argument3 882 * 883 * Return: 0 on success; non-zero value on error. 884 */ 885 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 886 { 887 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 888 } 889 890 /** 891 * ufshcd_get_req_rsp - returns the TR response transaction type 892 * @ucd_rsp_ptr: pointer to response UPIU 893 * 894 * Return: UPIU type. 895 */ 896 static inline enum upiu_response_transaction 897 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 898 { 899 return ucd_rsp_ptr->header.transaction_code; 900 } 901 902 /** 903 * ufshcd_is_exception_event - Check if the device raised an exception event 904 * @ucd_rsp_ptr: pointer to response UPIU 905 * 906 * The function checks if the device raised an exception event indicated in 907 * the Device Information field of response UPIU. 908 * 909 * Return: true if exception is raised, false otherwise. 910 */ 911 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 912 { 913 return ucd_rsp_ptr->header.device_information & 1; 914 } 915 916 /** 917 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 918 * @hba: per adapter instance 919 */ 920 static inline void 921 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 922 { 923 ufshcd_writel(hba, INT_AGGR_ENABLE | 924 INT_AGGR_COUNTER_AND_TIMER_RESET, 925 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 926 } 927 928 /** 929 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 930 * @hba: per adapter instance 931 * @cnt: Interrupt aggregation counter threshold 932 * @tmout: Interrupt aggregation timeout value 933 */ 934 static inline void 935 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 936 { 937 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 938 INT_AGGR_COUNTER_THLD_VAL(cnt) | 939 INT_AGGR_TIMEOUT_VAL(tmout), 940 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 941 } 942 943 /** 944 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 945 * @hba: per adapter instance 946 */ 947 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 948 { 949 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 950 } 951 952 /** 953 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 954 * When run-stop registers are set to 1, it indicates the 955 * host controller that it can process the requests 956 * @hba: per adapter instance 957 */ 958 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 959 { 960 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 961 REG_UTP_TASK_REQ_LIST_RUN_STOP); 962 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 963 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 964 } 965 966 /** 967 * ufshcd_hba_start - Start controller initialization sequence 968 * @hba: per adapter instance 969 */ 970 static inline void ufshcd_hba_start(struct ufs_hba *hba) 971 { 972 u32 val = CONTROLLER_ENABLE; 973 974 if (ufshcd_crypto_enable(hba)) 975 val |= CRYPTO_GENERAL_ENABLE; 976 977 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 978 } 979 980 /** 981 * ufshcd_is_hba_active - Get controller state 982 * @hba: per adapter instance 983 * 984 * Return: true if and only if the controller is active. 985 */ 986 bool ufshcd_is_hba_active(struct ufs_hba *hba) 987 { 988 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 989 } 990 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 991 992 /** 993 * ufshcd_pm_qos_init - initialize PM QoS request 994 * @hba: per adapter instance 995 */ 996 void ufshcd_pm_qos_init(struct ufs_hba *hba) 997 { 998 999 if (hba->pm_qos_enabled) 1000 return; 1001 1002 cpu_latency_qos_add_request(&hba->pm_qos_req, PM_QOS_DEFAULT_VALUE); 1003 1004 if (cpu_latency_qos_request_active(&hba->pm_qos_req)) 1005 hba->pm_qos_enabled = true; 1006 } 1007 1008 /** 1009 * ufshcd_pm_qos_exit - remove request from PM QoS 1010 * @hba: per adapter instance 1011 */ 1012 void ufshcd_pm_qos_exit(struct ufs_hba *hba) 1013 { 1014 if (!hba->pm_qos_enabled) 1015 return; 1016 1017 cpu_latency_qos_remove_request(&hba->pm_qos_req); 1018 hba->pm_qos_enabled = false; 1019 } 1020 1021 /** 1022 * ufshcd_pm_qos_update - update PM QoS request 1023 * @hba: per adapter instance 1024 * @on: If True, vote for perf PM QoS mode otherwise power save mode 1025 */ 1026 static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on) 1027 { 1028 if (!hba->pm_qos_enabled) 1029 return; 1030 1031 cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE); 1032 } 1033 1034 /** 1035 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1036 * @hba: per adapter instance 1037 * @scale_up: If True, set max possible frequency othewise set low frequency 1038 * 1039 * Return: 0 if successful; < 0 upon failure. 1040 */ 1041 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1042 { 1043 int ret = 0; 1044 struct ufs_clk_info *clki; 1045 struct list_head *head = &hba->clk_list_head; 1046 1047 if (list_empty(head)) 1048 goto out; 1049 1050 list_for_each_entry(clki, head, list) { 1051 if (!IS_ERR_OR_NULL(clki->clk)) { 1052 if (scale_up && clki->max_freq) { 1053 if (clki->curr_freq == clki->max_freq) 1054 continue; 1055 1056 ret = clk_set_rate(clki->clk, clki->max_freq); 1057 if (ret) { 1058 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1059 __func__, clki->name, 1060 clki->max_freq, ret); 1061 break; 1062 } 1063 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1064 "scaled up", clki->name, 1065 clki->curr_freq, 1066 clki->max_freq); 1067 1068 clki->curr_freq = clki->max_freq; 1069 1070 } else if (!scale_up && clki->min_freq) { 1071 if (clki->curr_freq == clki->min_freq) 1072 continue; 1073 1074 ret = clk_set_rate(clki->clk, clki->min_freq); 1075 if (ret) { 1076 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1077 __func__, clki->name, 1078 clki->min_freq, ret); 1079 break; 1080 } 1081 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1082 "scaled down", clki->name, 1083 clki->curr_freq, 1084 clki->min_freq); 1085 clki->curr_freq = clki->min_freq; 1086 } 1087 } 1088 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1089 clki->name, clk_get_rate(clki->clk)); 1090 } 1091 1092 out: 1093 return ret; 1094 } 1095 1096 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1097 struct dev_pm_opp *opp, void *data, 1098 bool scaling_down) 1099 { 1100 struct ufs_hba *hba = dev_get_drvdata(dev); 1101 struct list_head *head = &hba->clk_list_head; 1102 struct ufs_clk_info *clki; 1103 unsigned long freq; 1104 u8 idx = 0; 1105 int ret; 1106 1107 list_for_each_entry(clki, head, list) { 1108 if (!IS_ERR_OR_NULL(clki->clk)) { 1109 freq = dev_pm_opp_get_freq_indexed(opp, idx++); 1110 1111 /* Do not set rate for clocks having frequency as 0 */ 1112 if (!freq) 1113 continue; 1114 1115 ret = clk_set_rate(clki->clk, freq); 1116 if (ret) { 1117 dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n", 1118 __func__, clki->name, freq, ret); 1119 return ret; 1120 } 1121 1122 trace_ufshcd_clk_scaling(dev_name(dev), 1123 (scaling_down ? "scaled down" : "scaled up"), 1124 clki->name, hba->clk_scaling.target_freq, freq); 1125 } 1126 } 1127 1128 return 0; 1129 } 1130 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks); 1131 1132 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) 1133 { 1134 struct dev_pm_opp *opp; 1135 int ret; 1136 1137 opp = dev_pm_opp_find_freq_floor_indexed(hba->dev, 1138 &freq, 0); 1139 if (IS_ERR(opp)) 1140 return PTR_ERR(opp); 1141 1142 ret = dev_pm_opp_set_opp(hba->dev, opp); 1143 dev_pm_opp_put(opp); 1144 1145 return ret; 1146 } 1147 1148 /** 1149 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1150 * @hba: per adapter instance 1151 * @freq: frequency to scale 1152 * @scale_up: True if scaling up and false if scaling down 1153 * 1154 * Return: 0 if successful; < 0 upon failure. 1155 */ 1156 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 1157 bool scale_up) 1158 { 1159 int ret = 0; 1160 ktime_t start = ktime_get(); 1161 1162 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1163 if (ret) 1164 goto out; 1165 1166 if (hba->use_pm_opp) 1167 ret = ufshcd_opp_set_rate(hba, freq); 1168 else 1169 ret = ufshcd_set_clk_freq(hba, scale_up); 1170 if (ret) 1171 goto out; 1172 1173 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1174 if (ret) { 1175 if (hba->use_pm_opp) 1176 ufshcd_opp_set_rate(hba, 1177 hba->devfreq->previous_freq); 1178 else 1179 ufshcd_set_clk_freq(hba, !scale_up); 1180 goto out; 1181 } 1182 1183 ufshcd_pm_qos_update(hba, scale_up); 1184 1185 out: 1186 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1187 (scale_up ? "up" : "down"), 1188 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1189 return ret; 1190 } 1191 1192 /** 1193 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1194 * @hba: per adapter instance 1195 * @freq: frequency to scale 1196 * @scale_up: True if scaling up and false if scaling down 1197 * 1198 * Return: true if scaling is required, false otherwise. 1199 */ 1200 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1201 unsigned long freq, bool scale_up) 1202 { 1203 struct ufs_clk_info *clki; 1204 struct list_head *head = &hba->clk_list_head; 1205 1206 if (list_empty(head)) 1207 return false; 1208 1209 if (hba->use_pm_opp) 1210 return freq != hba->clk_scaling.target_freq; 1211 1212 list_for_each_entry(clki, head, list) { 1213 if (!IS_ERR_OR_NULL(clki->clk)) { 1214 if (scale_up && clki->max_freq) { 1215 if (clki->curr_freq == clki->max_freq) 1216 continue; 1217 return true; 1218 } else if (!scale_up && clki->min_freq) { 1219 if (clki->curr_freq == clki->min_freq) 1220 continue; 1221 return true; 1222 } 1223 } 1224 } 1225 1226 return false; 1227 } 1228 1229 /* 1230 * Determine the number of pending commands by counting the bits in the SCSI 1231 * device budget maps. This approach has been selected because a bit is set in 1232 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1233 * flag. The host_self_blocked flag can be modified by calling 1234 * scsi_block_requests() or scsi_unblock_requests(). 1235 */ 1236 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1237 { 1238 const struct scsi_device *sdev; 1239 u32 pending = 0; 1240 1241 lockdep_assert_held(hba->host->host_lock); 1242 __shost_for_each_device(sdev, hba->host) 1243 pending += sbitmap_weight(&sdev->budget_map); 1244 1245 return pending; 1246 } 1247 1248 /* 1249 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1250 * has expired. 1251 * 1252 * Return: 0 upon success; -EBUSY upon timeout. 1253 */ 1254 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1255 u64 wait_timeout_us) 1256 { 1257 unsigned long flags; 1258 int ret = 0; 1259 u32 tm_doorbell; 1260 u32 tr_pending; 1261 bool timeout = false, do_last_check = false; 1262 ktime_t start; 1263 1264 ufshcd_hold(hba); 1265 spin_lock_irqsave(hba->host->host_lock, flags); 1266 /* 1267 * Wait for all the outstanding tasks/transfer requests. 1268 * Verify by checking the doorbell registers are clear. 1269 */ 1270 start = ktime_get(); 1271 do { 1272 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1273 ret = -EBUSY; 1274 goto out; 1275 } 1276 1277 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1278 tr_pending = ufshcd_pending_cmds(hba); 1279 if (!tm_doorbell && !tr_pending) { 1280 timeout = false; 1281 break; 1282 } else if (do_last_check) { 1283 break; 1284 } 1285 1286 spin_unlock_irqrestore(hba->host->host_lock, flags); 1287 io_schedule_timeout(msecs_to_jiffies(20)); 1288 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1289 wait_timeout_us) { 1290 timeout = true; 1291 /* 1292 * We might have scheduled out for long time so make 1293 * sure to check if doorbells are cleared by this time 1294 * or not. 1295 */ 1296 do_last_check = true; 1297 } 1298 spin_lock_irqsave(hba->host->host_lock, flags); 1299 } while (tm_doorbell || tr_pending); 1300 1301 if (timeout) { 1302 dev_err(hba->dev, 1303 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1304 __func__, tm_doorbell, tr_pending); 1305 ret = -EBUSY; 1306 } 1307 out: 1308 spin_unlock_irqrestore(hba->host->host_lock, flags); 1309 ufshcd_release(hba); 1310 return ret; 1311 } 1312 1313 /** 1314 * ufshcd_scale_gear - scale up/down UFS gear 1315 * @hba: per adapter instance 1316 * @scale_up: True for scaling up gear and false for scaling down 1317 * 1318 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1319 * non-zero for any other errors. 1320 */ 1321 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1322 { 1323 int ret = 0; 1324 struct ufs_pa_layer_attr new_pwr_info; 1325 1326 if (scale_up) { 1327 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1328 sizeof(struct ufs_pa_layer_attr)); 1329 } else { 1330 memcpy(&new_pwr_info, &hba->pwr_info, 1331 sizeof(struct ufs_pa_layer_attr)); 1332 1333 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1334 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1335 /* save the current power mode */ 1336 memcpy(&hba->clk_scaling.saved_pwr_info, 1337 &hba->pwr_info, 1338 sizeof(struct ufs_pa_layer_attr)); 1339 1340 /* scale down gear */ 1341 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1342 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1343 } 1344 } 1345 1346 /* check if the power mode needs to be changed or not? */ 1347 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1348 if (ret) 1349 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1350 __func__, ret, 1351 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1352 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1353 1354 return ret; 1355 } 1356 1357 /* 1358 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1359 * has expired. 1360 * 1361 * Return: 0 upon success; -EBUSY upon timeout. 1362 */ 1363 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1364 { 1365 int ret = 0; 1366 /* 1367 * make sure that there are no outstanding requests when 1368 * clock scaling is in progress 1369 */ 1370 blk_mq_quiesce_tagset(&hba->host->tag_set); 1371 mutex_lock(&hba->wb_mutex); 1372 down_write(&hba->clk_scaling_lock); 1373 1374 if (!hba->clk_scaling.is_allowed || 1375 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1376 ret = -EBUSY; 1377 up_write(&hba->clk_scaling_lock); 1378 mutex_unlock(&hba->wb_mutex); 1379 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1380 goto out; 1381 } 1382 1383 /* let's not get into low power until clock scaling is completed */ 1384 ufshcd_hold(hba); 1385 1386 out: 1387 return ret; 1388 } 1389 1390 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1391 { 1392 up_write(&hba->clk_scaling_lock); 1393 1394 /* Enable Write Booster if we have scaled up else disable it */ 1395 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1396 ufshcd_wb_toggle(hba, scale_up); 1397 1398 mutex_unlock(&hba->wb_mutex); 1399 1400 blk_mq_unquiesce_tagset(&hba->host->tag_set); 1401 ufshcd_release(hba); 1402 } 1403 1404 /** 1405 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1406 * @hba: per adapter instance 1407 * @freq: frequency to scale 1408 * @scale_up: True for scaling up and false for scalin down 1409 * 1410 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1411 * for any other errors. 1412 */ 1413 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, 1414 bool scale_up) 1415 { 1416 int ret = 0; 1417 1418 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1419 if (ret) 1420 return ret; 1421 1422 /* scale down the gear before scaling down clocks */ 1423 if (!scale_up) { 1424 ret = ufshcd_scale_gear(hba, false); 1425 if (ret) 1426 goto out_unprepare; 1427 } 1428 1429 ret = ufshcd_scale_clks(hba, freq, scale_up); 1430 if (ret) { 1431 if (!scale_up) 1432 ufshcd_scale_gear(hba, true); 1433 goto out_unprepare; 1434 } 1435 1436 /* scale up the gear after scaling up clocks */ 1437 if (scale_up) { 1438 ret = ufshcd_scale_gear(hba, true); 1439 if (ret) { 1440 ufshcd_scale_clks(hba, hba->devfreq->previous_freq, 1441 false); 1442 goto out_unprepare; 1443 } 1444 } 1445 1446 out_unprepare: 1447 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1448 return ret; 1449 } 1450 1451 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1452 { 1453 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1454 clk_scaling.suspend_work); 1455 unsigned long irq_flags; 1456 1457 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1458 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1459 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1460 return; 1461 } 1462 hba->clk_scaling.is_suspended = true; 1463 hba->clk_scaling.window_start_t = 0; 1464 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1465 1466 devfreq_suspend_device(hba->devfreq); 1467 } 1468 1469 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1470 { 1471 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1472 clk_scaling.resume_work); 1473 unsigned long irq_flags; 1474 1475 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1476 if (!hba->clk_scaling.is_suspended) { 1477 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1478 return; 1479 } 1480 hba->clk_scaling.is_suspended = false; 1481 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1482 1483 devfreq_resume_device(hba->devfreq); 1484 } 1485 1486 static int ufshcd_devfreq_target(struct device *dev, 1487 unsigned long *freq, u32 flags) 1488 { 1489 int ret = 0; 1490 struct ufs_hba *hba = dev_get_drvdata(dev); 1491 ktime_t start; 1492 bool scale_up = false, sched_clk_scaling_suspend_work = false; 1493 struct list_head *clk_list = &hba->clk_list_head; 1494 struct ufs_clk_info *clki; 1495 unsigned long irq_flags; 1496 1497 if (!ufshcd_is_clkscaling_supported(hba)) 1498 return -EINVAL; 1499 1500 if (hba->use_pm_opp) { 1501 struct dev_pm_opp *opp; 1502 1503 /* Get the recommended frequency from OPP framework */ 1504 opp = devfreq_recommended_opp(dev, freq, flags); 1505 if (IS_ERR(opp)) 1506 return PTR_ERR(opp); 1507 1508 dev_pm_opp_put(opp); 1509 } else { 1510 /* Override with the closest supported frequency */ 1511 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, 1512 list); 1513 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1514 } 1515 1516 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1517 if (ufshcd_eh_in_progress(hba)) { 1518 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1519 return 0; 1520 } 1521 1522 /* Skip scaling clock when clock scaling is suspended */ 1523 if (hba->clk_scaling.is_suspended) { 1524 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1525 dev_warn(hba->dev, "clock scaling is suspended, skip"); 1526 return 0; 1527 } 1528 1529 if (!hba->clk_scaling.active_reqs) 1530 sched_clk_scaling_suspend_work = true; 1531 1532 if (list_empty(clk_list)) { 1533 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1534 goto out; 1535 } 1536 1537 /* Decide based on the target or rounded-off frequency and update */ 1538 if (hba->use_pm_opp) 1539 scale_up = *freq > hba->clk_scaling.target_freq; 1540 else 1541 scale_up = *freq == clki->max_freq; 1542 1543 if (!hba->use_pm_opp && !scale_up) 1544 *freq = clki->min_freq; 1545 1546 /* Update the frequency */ 1547 if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) { 1548 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1549 ret = 0; 1550 goto out; /* no state change required */ 1551 } 1552 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1553 1554 start = ktime_get(); 1555 ret = ufshcd_devfreq_scale(hba, *freq, scale_up); 1556 if (!ret) 1557 hba->clk_scaling.target_freq = *freq; 1558 1559 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1560 (scale_up ? "up" : "down"), 1561 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1562 1563 out: 1564 if (sched_clk_scaling_suspend_work && 1565 (!scale_up || hba->clk_scaling.suspend_on_no_request)) 1566 queue_work(hba->clk_scaling.workq, 1567 &hba->clk_scaling.suspend_work); 1568 1569 return ret; 1570 } 1571 1572 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1573 struct devfreq_dev_status *stat) 1574 { 1575 struct ufs_hba *hba = dev_get_drvdata(dev); 1576 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1577 unsigned long flags; 1578 ktime_t curr_t; 1579 1580 if (!ufshcd_is_clkscaling_supported(hba)) 1581 return -EINVAL; 1582 1583 memset(stat, 0, sizeof(*stat)); 1584 1585 spin_lock_irqsave(hba->host->host_lock, flags); 1586 curr_t = ktime_get(); 1587 if (!scaling->window_start_t) 1588 goto start_window; 1589 1590 /* 1591 * If current frequency is 0, then the ondemand governor considers 1592 * there's no initial frequency set. And it always requests to set 1593 * to max. frequency. 1594 */ 1595 if (hba->use_pm_opp) { 1596 stat->current_frequency = hba->clk_scaling.target_freq; 1597 } else { 1598 struct list_head *clk_list = &hba->clk_list_head; 1599 struct ufs_clk_info *clki; 1600 1601 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1602 stat->current_frequency = clki->curr_freq; 1603 } 1604 1605 if (scaling->is_busy_started) 1606 scaling->tot_busy_t += ktime_us_delta(curr_t, 1607 scaling->busy_start_t); 1608 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1609 stat->busy_time = scaling->tot_busy_t; 1610 start_window: 1611 scaling->window_start_t = curr_t; 1612 scaling->tot_busy_t = 0; 1613 1614 if (scaling->active_reqs) { 1615 scaling->busy_start_t = curr_t; 1616 scaling->is_busy_started = true; 1617 } else { 1618 scaling->busy_start_t = 0; 1619 scaling->is_busy_started = false; 1620 } 1621 spin_unlock_irqrestore(hba->host->host_lock, flags); 1622 return 0; 1623 } 1624 1625 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1626 { 1627 struct list_head *clk_list = &hba->clk_list_head; 1628 struct ufs_clk_info *clki; 1629 struct devfreq *devfreq; 1630 int ret; 1631 1632 /* Skip devfreq if we don't have any clocks in the list */ 1633 if (list_empty(clk_list)) 1634 return 0; 1635 1636 if (!hba->use_pm_opp) { 1637 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1638 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1639 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1640 } 1641 1642 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1643 &hba->vps->ondemand_data); 1644 devfreq = devfreq_add_device(hba->dev, 1645 &hba->vps->devfreq_profile, 1646 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1647 &hba->vps->ondemand_data); 1648 if (IS_ERR(devfreq)) { 1649 ret = PTR_ERR(devfreq); 1650 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1651 1652 if (!hba->use_pm_opp) { 1653 dev_pm_opp_remove(hba->dev, clki->min_freq); 1654 dev_pm_opp_remove(hba->dev, clki->max_freq); 1655 } 1656 return ret; 1657 } 1658 1659 hba->devfreq = devfreq; 1660 1661 return 0; 1662 } 1663 1664 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1665 { 1666 struct list_head *clk_list = &hba->clk_list_head; 1667 1668 if (!hba->devfreq) 1669 return; 1670 1671 devfreq_remove_device(hba->devfreq); 1672 hba->devfreq = NULL; 1673 1674 if (!hba->use_pm_opp) { 1675 struct ufs_clk_info *clki; 1676 1677 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1678 dev_pm_opp_remove(hba->dev, clki->min_freq); 1679 dev_pm_opp_remove(hba->dev, clki->max_freq); 1680 } 1681 } 1682 1683 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1684 { 1685 unsigned long flags; 1686 bool suspend = false; 1687 1688 cancel_work_sync(&hba->clk_scaling.suspend_work); 1689 cancel_work_sync(&hba->clk_scaling.resume_work); 1690 1691 spin_lock_irqsave(hba->host->host_lock, flags); 1692 if (!hba->clk_scaling.is_suspended) { 1693 suspend = true; 1694 hba->clk_scaling.is_suspended = true; 1695 hba->clk_scaling.window_start_t = 0; 1696 } 1697 spin_unlock_irqrestore(hba->host->host_lock, flags); 1698 1699 if (suspend) 1700 devfreq_suspend_device(hba->devfreq); 1701 } 1702 1703 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1704 { 1705 unsigned long flags; 1706 bool resume = false; 1707 1708 spin_lock_irqsave(hba->host->host_lock, flags); 1709 if (hba->clk_scaling.is_suspended) { 1710 resume = true; 1711 hba->clk_scaling.is_suspended = false; 1712 } 1713 spin_unlock_irqrestore(hba->host->host_lock, flags); 1714 1715 if (resume) 1716 devfreq_resume_device(hba->devfreq); 1717 } 1718 1719 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1720 struct device_attribute *attr, char *buf) 1721 { 1722 struct ufs_hba *hba = dev_get_drvdata(dev); 1723 1724 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1725 } 1726 1727 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1728 struct device_attribute *attr, const char *buf, size_t count) 1729 { 1730 struct ufs_hba *hba = dev_get_drvdata(dev); 1731 u32 value; 1732 int err = 0; 1733 1734 if (kstrtou32(buf, 0, &value)) 1735 return -EINVAL; 1736 1737 down(&hba->host_sem); 1738 if (!ufshcd_is_user_access_allowed(hba)) { 1739 err = -EBUSY; 1740 goto out; 1741 } 1742 1743 value = !!value; 1744 if (value == hba->clk_scaling.is_enabled) 1745 goto out; 1746 1747 ufshcd_rpm_get_sync(hba); 1748 ufshcd_hold(hba); 1749 1750 hba->clk_scaling.is_enabled = value; 1751 1752 if (value) { 1753 ufshcd_resume_clkscaling(hba); 1754 } else { 1755 ufshcd_suspend_clkscaling(hba); 1756 err = ufshcd_devfreq_scale(hba, ULONG_MAX, true); 1757 if (err) 1758 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1759 __func__, err); 1760 } 1761 1762 ufshcd_release(hba); 1763 ufshcd_rpm_put_sync(hba); 1764 out: 1765 up(&hba->host_sem); 1766 return err ? err : count; 1767 } 1768 1769 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1770 { 1771 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1772 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1773 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1774 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1775 hba->clk_scaling.enable_attr.attr.mode = 0644; 1776 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1777 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1778 } 1779 1780 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1781 { 1782 if (hba->clk_scaling.enable_attr.attr.name) 1783 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1784 } 1785 1786 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1787 { 1788 char wq_name[sizeof("ufs_clkscaling_00")]; 1789 1790 if (!ufshcd_is_clkscaling_supported(hba)) 1791 return; 1792 1793 if (!hba->clk_scaling.min_gear) 1794 hba->clk_scaling.min_gear = UFS_HS_G1; 1795 1796 INIT_WORK(&hba->clk_scaling.suspend_work, 1797 ufshcd_clk_scaling_suspend_work); 1798 INIT_WORK(&hba->clk_scaling.resume_work, 1799 ufshcd_clk_scaling_resume_work); 1800 1801 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d", 1802 hba->host->host_no); 1803 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name); 1804 1805 hba->clk_scaling.is_initialized = true; 1806 } 1807 1808 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1809 { 1810 if (!hba->clk_scaling.is_initialized) 1811 return; 1812 1813 ufshcd_remove_clk_scaling_sysfs(hba); 1814 destroy_workqueue(hba->clk_scaling.workq); 1815 ufshcd_devfreq_remove(hba); 1816 hba->clk_scaling.is_initialized = false; 1817 } 1818 1819 static void ufshcd_ungate_work(struct work_struct *work) 1820 { 1821 int ret; 1822 unsigned long flags; 1823 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1824 clk_gating.ungate_work); 1825 1826 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1827 1828 spin_lock_irqsave(hba->host->host_lock, flags); 1829 if (hba->clk_gating.state == CLKS_ON) { 1830 spin_unlock_irqrestore(hba->host->host_lock, flags); 1831 return; 1832 } 1833 1834 spin_unlock_irqrestore(hba->host->host_lock, flags); 1835 ufshcd_hba_vreg_set_hpm(hba); 1836 ufshcd_setup_clocks(hba, true); 1837 1838 ufshcd_enable_irq(hba); 1839 1840 /* Exit from hibern8 */ 1841 if (ufshcd_can_hibern8_during_gating(hba)) { 1842 /* Prevent gating in this path */ 1843 hba->clk_gating.is_suspended = true; 1844 if (ufshcd_is_link_hibern8(hba)) { 1845 ret = ufshcd_uic_hibern8_exit(hba); 1846 if (ret) 1847 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1848 __func__, ret); 1849 else 1850 ufshcd_set_link_active(hba); 1851 } 1852 hba->clk_gating.is_suspended = false; 1853 } 1854 } 1855 1856 /** 1857 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1858 * Also, exit from hibern8 mode and set the link as active. 1859 * @hba: per adapter instance 1860 */ 1861 void ufshcd_hold(struct ufs_hba *hba) 1862 { 1863 bool flush_result; 1864 unsigned long flags; 1865 1866 if (!ufshcd_is_clkgating_allowed(hba) || 1867 !hba->clk_gating.is_initialized) 1868 return; 1869 spin_lock_irqsave(hba->host->host_lock, flags); 1870 hba->clk_gating.active_reqs++; 1871 1872 start: 1873 switch (hba->clk_gating.state) { 1874 case CLKS_ON: 1875 /* 1876 * Wait for the ungate work to complete if in progress. 1877 * Though the clocks may be in ON state, the link could 1878 * still be in hibner8 state if hibern8 is allowed 1879 * during clock gating. 1880 * Make sure we exit hibern8 state also in addition to 1881 * clocks being ON. 1882 */ 1883 if (ufshcd_can_hibern8_during_gating(hba) && 1884 ufshcd_is_link_hibern8(hba)) { 1885 spin_unlock_irqrestore(hba->host->host_lock, flags); 1886 flush_result = flush_work(&hba->clk_gating.ungate_work); 1887 if (hba->clk_gating.is_suspended && !flush_result) 1888 return; 1889 spin_lock_irqsave(hba->host->host_lock, flags); 1890 goto start; 1891 } 1892 break; 1893 case REQ_CLKS_OFF: 1894 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1895 hba->clk_gating.state = CLKS_ON; 1896 trace_ufshcd_clk_gating(dev_name(hba->dev), 1897 hba->clk_gating.state); 1898 break; 1899 } 1900 /* 1901 * If we are here, it means gating work is either done or 1902 * currently running. Hence, fall through to cancel gating 1903 * work and to enable clocks. 1904 */ 1905 fallthrough; 1906 case CLKS_OFF: 1907 hba->clk_gating.state = REQ_CLKS_ON; 1908 trace_ufshcd_clk_gating(dev_name(hba->dev), 1909 hba->clk_gating.state); 1910 queue_work(hba->clk_gating.clk_gating_workq, 1911 &hba->clk_gating.ungate_work); 1912 /* 1913 * fall through to check if we should wait for this 1914 * work to be done or not. 1915 */ 1916 fallthrough; 1917 case REQ_CLKS_ON: 1918 spin_unlock_irqrestore(hba->host->host_lock, flags); 1919 flush_work(&hba->clk_gating.ungate_work); 1920 /* Make sure state is CLKS_ON before returning */ 1921 spin_lock_irqsave(hba->host->host_lock, flags); 1922 goto start; 1923 default: 1924 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1925 __func__, hba->clk_gating.state); 1926 break; 1927 } 1928 spin_unlock_irqrestore(hba->host->host_lock, flags); 1929 } 1930 EXPORT_SYMBOL_GPL(ufshcd_hold); 1931 1932 static void ufshcd_gate_work(struct work_struct *work) 1933 { 1934 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1935 clk_gating.gate_work.work); 1936 unsigned long flags; 1937 int ret; 1938 1939 spin_lock_irqsave(hba->host->host_lock, flags); 1940 /* 1941 * In case you are here to cancel this work the gating state 1942 * would be marked as REQ_CLKS_ON. In this case save time by 1943 * skipping the gating work and exit after changing the clock 1944 * state to CLKS_ON. 1945 */ 1946 if (hba->clk_gating.is_suspended || 1947 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1948 hba->clk_gating.state = CLKS_ON; 1949 trace_ufshcd_clk_gating(dev_name(hba->dev), 1950 hba->clk_gating.state); 1951 goto rel_lock; 1952 } 1953 1954 if (ufshcd_is_ufs_dev_busy(hba) || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) 1955 goto rel_lock; 1956 1957 spin_unlock_irqrestore(hba->host->host_lock, flags); 1958 1959 /* put the link into hibern8 mode before turning off clocks */ 1960 if (ufshcd_can_hibern8_during_gating(hba)) { 1961 ret = ufshcd_uic_hibern8_enter(hba); 1962 if (ret) { 1963 hba->clk_gating.state = CLKS_ON; 1964 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1965 __func__, ret); 1966 trace_ufshcd_clk_gating(dev_name(hba->dev), 1967 hba->clk_gating.state); 1968 goto out; 1969 } 1970 ufshcd_set_link_hibern8(hba); 1971 } 1972 1973 ufshcd_disable_irq(hba); 1974 1975 ufshcd_setup_clocks(hba, false); 1976 1977 /* Put the host controller in low power mode if possible */ 1978 ufshcd_hba_vreg_set_lpm(hba); 1979 /* 1980 * In case you are here to cancel this work the gating state 1981 * would be marked as REQ_CLKS_ON. In this case keep the state 1982 * as REQ_CLKS_ON which would anyway imply that clocks are off 1983 * and a request to turn them on is pending. By doing this way, 1984 * we keep the state machine in tact and this would ultimately 1985 * prevent from doing cancel work multiple times when there are 1986 * new requests arriving before the current cancel work is done. 1987 */ 1988 spin_lock_irqsave(hba->host->host_lock, flags); 1989 if (hba->clk_gating.state == REQ_CLKS_OFF) { 1990 hba->clk_gating.state = CLKS_OFF; 1991 trace_ufshcd_clk_gating(dev_name(hba->dev), 1992 hba->clk_gating.state); 1993 } 1994 rel_lock: 1995 spin_unlock_irqrestore(hba->host->host_lock, flags); 1996 out: 1997 return; 1998 } 1999 2000 /* host lock must be held before calling this variant */ 2001 static void __ufshcd_release(struct ufs_hba *hba) 2002 { 2003 if (!ufshcd_is_clkgating_allowed(hba)) 2004 return; 2005 2006 hba->clk_gating.active_reqs--; 2007 2008 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 2009 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 2010 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 2011 hba->active_uic_cmd || hba->uic_async_done || 2012 hba->clk_gating.state == CLKS_OFF) 2013 return; 2014 2015 hba->clk_gating.state = REQ_CLKS_OFF; 2016 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 2017 queue_delayed_work(hba->clk_gating.clk_gating_workq, 2018 &hba->clk_gating.gate_work, 2019 msecs_to_jiffies(hba->clk_gating.delay_ms)); 2020 } 2021 2022 void ufshcd_release(struct ufs_hba *hba) 2023 { 2024 unsigned long flags; 2025 2026 spin_lock_irqsave(hba->host->host_lock, flags); 2027 __ufshcd_release(hba); 2028 spin_unlock_irqrestore(hba->host->host_lock, flags); 2029 } 2030 EXPORT_SYMBOL_GPL(ufshcd_release); 2031 2032 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 2033 struct device_attribute *attr, char *buf) 2034 { 2035 struct ufs_hba *hba = dev_get_drvdata(dev); 2036 2037 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 2038 } 2039 2040 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 2041 { 2042 struct ufs_hba *hba = dev_get_drvdata(dev); 2043 unsigned long flags; 2044 2045 spin_lock_irqsave(hba->host->host_lock, flags); 2046 hba->clk_gating.delay_ms = value; 2047 spin_unlock_irqrestore(hba->host->host_lock, flags); 2048 } 2049 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 2050 2051 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 2052 struct device_attribute *attr, const char *buf, size_t count) 2053 { 2054 unsigned long value; 2055 2056 if (kstrtoul(buf, 0, &value)) 2057 return -EINVAL; 2058 2059 ufshcd_clkgate_delay_set(dev, value); 2060 return count; 2061 } 2062 2063 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 2064 struct device_attribute *attr, char *buf) 2065 { 2066 struct ufs_hba *hba = dev_get_drvdata(dev); 2067 2068 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 2069 } 2070 2071 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 2072 struct device_attribute *attr, const char *buf, size_t count) 2073 { 2074 struct ufs_hba *hba = dev_get_drvdata(dev); 2075 unsigned long flags; 2076 u32 value; 2077 2078 if (kstrtou32(buf, 0, &value)) 2079 return -EINVAL; 2080 2081 value = !!value; 2082 2083 spin_lock_irqsave(hba->host->host_lock, flags); 2084 if (value == hba->clk_gating.is_enabled) 2085 goto out; 2086 2087 if (value) 2088 __ufshcd_release(hba); 2089 else 2090 hba->clk_gating.active_reqs++; 2091 2092 hba->clk_gating.is_enabled = value; 2093 out: 2094 spin_unlock_irqrestore(hba->host->host_lock, flags); 2095 return count; 2096 } 2097 2098 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 2099 { 2100 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 2101 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 2102 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 2103 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 2104 hba->clk_gating.delay_attr.attr.mode = 0644; 2105 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 2106 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 2107 2108 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 2109 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 2110 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 2111 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 2112 hba->clk_gating.enable_attr.attr.mode = 0644; 2113 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 2114 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 2115 } 2116 2117 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 2118 { 2119 if (hba->clk_gating.delay_attr.attr.name) 2120 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 2121 if (hba->clk_gating.enable_attr.attr.name) 2122 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 2123 } 2124 2125 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 2126 { 2127 char wq_name[sizeof("ufs_clk_gating_00")]; 2128 2129 if (!ufshcd_is_clkgating_allowed(hba)) 2130 return; 2131 2132 hba->clk_gating.state = CLKS_ON; 2133 2134 hba->clk_gating.delay_ms = 150; 2135 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2136 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2137 2138 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d", 2139 hba->host->host_no); 2140 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name, 2141 WQ_MEM_RECLAIM | WQ_HIGHPRI); 2142 2143 ufshcd_init_clk_gating_sysfs(hba); 2144 2145 hba->clk_gating.is_enabled = true; 2146 hba->clk_gating.is_initialized = true; 2147 } 2148 2149 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2150 { 2151 if (!hba->clk_gating.is_initialized) 2152 return; 2153 2154 ufshcd_remove_clk_gating_sysfs(hba); 2155 2156 /* Ungate the clock if necessary. */ 2157 ufshcd_hold(hba); 2158 hba->clk_gating.is_initialized = false; 2159 ufshcd_release(hba); 2160 2161 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2162 } 2163 2164 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2165 { 2166 bool queue_resume_work = false; 2167 ktime_t curr_t = ktime_get(); 2168 unsigned long flags; 2169 2170 if (!ufshcd_is_clkscaling_supported(hba)) 2171 return; 2172 2173 spin_lock_irqsave(hba->host->host_lock, flags); 2174 if (!hba->clk_scaling.active_reqs++) 2175 queue_resume_work = true; 2176 2177 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2178 spin_unlock_irqrestore(hba->host->host_lock, flags); 2179 return; 2180 } 2181 2182 if (queue_resume_work) 2183 queue_work(hba->clk_scaling.workq, 2184 &hba->clk_scaling.resume_work); 2185 2186 if (!hba->clk_scaling.window_start_t) { 2187 hba->clk_scaling.window_start_t = curr_t; 2188 hba->clk_scaling.tot_busy_t = 0; 2189 hba->clk_scaling.is_busy_started = false; 2190 } 2191 2192 if (!hba->clk_scaling.is_busy_started) { 2193 hba->clk_scaling.busy_start_t = curr_t; 2194 hba->clk_scaling.is_busy_started = true; 2195 } 2196 spin_unlock_irqrestore(hba->host->host_lock, flags); 2197 } 2198 2199 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2200 { 2201 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2202 unsigned long flags; 2203 2204 if (!ufshcd_is_clkscaling_supported(hba)) 2205 return; 2206 2207 spin_lock_irqsave(hba->host->host_lock, flags); 2208 hba->clk_scaling.active_reqs--; 2209 if (!scaling->active_reqs && scaling->is_busy_started) { 2210 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2211 scaling->busy_start_t)); 2212 scaling->busy_start_t = 0; 2213 scaling->is_busy_started = false; 2214 } 2215 spin_unlock_irqrestore(hba->host->host_lock, flags); 2216 } 2217 2218 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2219 { 2220 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2221 return READ; 2222 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2223 return WRITE; 2224 else 2225 return -EINVAL; 2226 } 2227 2228 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2229 struct ufshcd_lrb *lrbp) 2230 { 2231 const struct ufs_hba_monitor *m = &hba->monitor; 2232 2233 return (m->enabled && lrbp && lrbp->cmd && 2234 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2235 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2236 } 2237 2238 static void ufshcd_start_monitor(struct ufs_hba *hba, 2239 const struct ufshcd_lrb *lrbp) 2240 { 2241 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2242 unsigned long flags; 2243 2244 spin_lock_irqsave(hba->host->host_lock, flags); 2245 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2246 hba->monitor.busy_start_ts[dir] = ktime_get(); 2247 spin_unlock_irqrestore(hba->host->host_lock, flags); 2248 } 2249 2250 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2251 { 2252 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2253 unsigned long flags; 2254 2255 spin_lock_irqsave(hba->host->host_lock, flags); 2256 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2257 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2258 struct ufs_hba_monitor *m = &hba->monitor; 2259 ktime_t now, inc, lat; 2260 2261 now = lrbp->compl_time_stamp; 2262 inc = ktime_sub(now, m->busy_start_ts[dir]); 2263 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2264 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2265 2266 /* Update latencies */ 2267 m->nr_req[dir]++; 2268 lat = ktime_sub(now, lrbp->issue_time_stamp); 2269 m->lat_sum[dir] += lat; 2270 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2271 m->lat_max[dir] = lat; 2272 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2273 m->lat_min[dir] = lat; 2274 2275 m->nr_queued[dir]--; 2276 /* Push forward the busy start of monitor */ 2277 m->busy_start_ts[dir] = now; 2278 } 2279 spin_unlock_irqrestore(hba->host->host_lock, flags); 2280 } 2281 2282 /** 2283 * ufshcd_send_command - Send SCSI or device management commands 2284 * @hba: per adapter instance 2285 * @task_tag: Task tag of the command 2286 * @hwq: pointer to hardware queue instance 2287 */ 2288 static inline 2289 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2290 struct ufs_hw_queue *hwq) 2291 { 2292 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2293 unsigned long flags; 2294 2295 lrbp->issue_time_stamp = ktime_get(); 2296 lrbp->issue_time_stamp_local_clock = local_clock(); 2297 lrbp->compl_time_stamp = ktime_set(0, 0); 2298 lrbp->compl_time_stamp_local_clock = 0; 2299 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2300 if (lrbp->cmd) 2301 ufshcd_clk_scaling_start_busy(hba); 2302 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2303 ufshcd_start_monitor(hba, lrbp); 2304 2305 if (hba->mcq_enabled) { 2306 int utrd_size = sizeof(struct utp_transfer_req_desc); 2307 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2308 struct utp_transfer_req_desc *dest; 2309 2310 spin_lock(&hwq->sq_lock); 2311 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2312 memcpy(dest, src, utrd_size); 2313 ufshcd_inc_sq_tail(hwq); 2314 spin_unlock(&hwq->sq_lock); 2315 } else { 2316 spin_lock_irqsave(&hba->outstanding_lock, flags); 2317 if (hba->vops && hba->vops->setup_xfer_req) 2318 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2319 !!lrbp->cmd); 2320 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2321 ufshcd_writel(hba, 1 << lrbp->task_tag, 2322 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2323 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2324 } 2325 } 2326 2327 /** 2328 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2329 * @lrbp: pointer to local reference block 2330 */ 2331 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2332 { 2333 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2334 u16 resp_len; 2335 int len; 2336 2337 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2338 if (sense_buffer && resp_len) { 2339 int len_to_copy; 2340 2341 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2342 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2343 2344 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2345 len_to_copy); 2346 } 2347 } 2348 2349 /** 2350 * ufshcd_copy_query_response() - Copy the Query Response and the data 2351 * descriptor 2352 * @hba: per adapter instance 2353 * @lrbp: pointer to local reference block 2354 * 2355 * Return: 0 upon success; < 0 upon failure. 2356 */ 2357 static 2358 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2359 { 2360 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2361 2362 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2363 2364 /* Get the descriptor */ 2365 if (hba->dev_cmd.query.descriptor && 2366 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2367 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2368 GENERAL_UPIU_REQUEST_SIZE; 2369 u16 resp_len; 2370 u16 buf_len; 2371 2372 /* data segment length */ 2373 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2374 .data_segment_length); 2375 buf_len = be16_to_cpu( 2376 hba->dev_cmd.query.request.upiu_req.length); 2377 if (likely(buf_len >= resp_len)) { 2378 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2379 } else { 2380 dev_warn(hba->dev, 2381 "%s: rsp size %d is bigger than buffer size %d", 2382 __func__, resp_len, buf_len); 2383 return -EINVAL; 2384 } 2385 } 2386 2387 return 0; 2388 } 2389 2390 /** 2391 * ufshcd_hba_capabilities - Read controller capabilities 2392 * @hba: per adapter instance 2393 * 2394 * Return: 0 on success, negative on error. 2395 */ 2396 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2397 { 2398 int err; 2399 2400 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2401 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) 2402 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT; 2403 2404 /* nutrs and nutmrs are 0 based values */ 2405 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS_SDB) + 1; 2406 hba->nutmrs = 2407 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2408 hba->reserved_slot = hba->nutrs - 1; 2409 2410 hba->nortt = FIELD_GET(MASK_NUMBER_OUTSTANDING_RTT, hba->capabilities) + 1; 2411 2412 /* Read crypto capabilities */ 2413 err = ufshcd_hba_init_crypto_capabilities(hba); 2414 if (err) { 2415 dev_err(hba->dev, "crypto setup failed\n"); 2416 return err; 2417 } 2418 2419 /* 2420 * The UFSHCI 3.0 specification does not define MCQ_SUPPORT and 2421 * LSDB_SUPPORT, but [31:29] as reserved bits with reset value 0s, which 2422 * means we can simply read values regardless of version. 2423 */ 2424 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2425 /* 2426 * 0h: legacy single doorbell support is available 2427 * 1h: indicate that legacy single doorbell support has been removed 2428 */ 2429 hba->lsdb_sup = !FIELD_GET(MASK_LSDB_SUPPORT, hba->capabilities); 2430 if (!hba->mcq_sup) 2431 return 0; 2432 2433 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2434 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2435 hba->mcq_capabilities); 2436 2437 return 0; 2438 } 2439 2440 /** 2441 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2442 * to accept UIC commands 2443 * @hba: per adapter instance 2444 * 2445 * Return: true on success, else false. 2446 */ 2447 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2448 { 2449 u32 val; 2450 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2451 500, UIC_CMD_TIMEOUT * 1000, false, hba, 2452 REG_CONTROLLER_STATUS); 2453 return ret == 0; 2454 } 2455 2456 /** 2457 * ufshcd_get_upmcrs - Get the power mode change request status 2458 * @hba: Pointer to adapter instance 2459 * 2460 * This function gets the UPMCRS field of HCS register 2461 * 2462 * Return: value of UPMCRS field. 2463 */ 2464 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2465 { 2466 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2467 } 2468 2469 /** 2470 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2471 * @hba: per adapter instance 2472 * @uic_cmd: UIC command 2473 */ 2474 static inline void 2475 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2476 { 2477 lockdep_assert_held(&hba->uic_cmd_mutex); 2478 2479 WARN_ON(hba->active_uic_cmd); 2480 2481 hba->active_uic_cmd = uic_cmd; 2482 2483 /* Write Args */ 2484 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2485 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2486 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2487 2488 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2489 2490 /* Write UIC Cmd */ 2491 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2492 REG_UIC_COMMAND); 2493 } 2494 2495 /** 2496 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2497 * @hba: per adapter instance 2498 * @uic_cmd: UIC command 2499 * 2500 * Return: 0 only if success. 2501 */ 2502 static int 2503 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2504 { 2505 int ret; 2506 unsigned long flags; 2507 2508 lockdep_assert_held(&hba->uic_cmd_mutex); 2509 2510 if (wait_for_completion_timeout(&uic_cmd->done, 2511 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 2512 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2513 } else { 2514 ret = -ETIMEDOUT; 2515 dev_err(hba->dev, 2516 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2517 uic_cmd->command, uic_cmd->argument3); 2518 2519 if (!uic_cmd->cmd_active) { 2520 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2521 __func__); 2522 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2523 } 2524 } 2525 2526 spin_lock_irqsave(hba->host->host_lock, flags); 2527 hba->active_uic_cmd = NULL; 2528 spin_unlock_irqrestore(hba->host->host_lock, flags); 2529 2530 return ret; 2531 } 2532 2533 /** 2534 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2535 * @hba: per adapter instance 2536 * @uic_cmd: UIC command 2537 * @completion: initialize the completion only if this is set to true 2538 * 2539 * Return: 0 only if success. 2540 */ 2541 static int 2542 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd, 2543 bool completion) 2544 { 2545 lockdep_assert_held(&hba->uic_cmd_mutex); 2546 2547 if (!ufshcd_ready_for_uic_cmd(hba)) { 2548 dev_err(hba->dev, 2549 "Controller not ready to accept UIC commands\n"); 2550 return -EIO; 2551 } 2552 2553 if (completion) 2554 init_completion(&uic_cmd->done); 2555 2556 uic_cmd->cmd_active = 1; 2557 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2558 2559 return 0; 2560 } 2561 2562 /** 2563 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2564 * @hba: per adapter instance 2565 * @uic_cmd: UIC command 2566 * 2567 * Return: 0 only if success. 2568 */ 2569 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2570 { 2571 int ret; 2572 2573 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2574 return 0; 2575 2576 ufshcd_hold(hba); 2577 mutex_lock(&hba->uic_cmd_mutex); 2578 ufshcd_add_delay_before_dme_cmd(hba); 2579 2580 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true); 2581 if (!ret) 2582 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2583 2584 mutex_unlock(&hba->uic_cmd_mutex); 2585 2586 ufshcd_release(hba); 2587 return ret; 2588 } 2589 2590 /** 2591 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2592 * @hba: per-adapter instance 2593 * @lrbp: pointer to local reference block 2594 * @sg_entries: The number of sg lists actually used 2595 * @sg_list: Pointer to SG list 2596 */ 2597 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2598 struct scatterlist *sg_list) 2599 { 2600 struct ufshcd_sg_entry *prd; 2601 struct scatterlist *sg; 2602 int i; 2603 2604 if (sg_entries) { 2605 2606 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2607 lrbp->utr_descriptor_ptr->prd_table_length = 2608 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2609 else 2610 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2611 2612 prd = lrbp->ucd_prdt_ptr; 2613 2614 for_each_sg(sg_list, sg, sg_entries, i) { 2615 const unsigned int len = sg_dma_len(sg); 2616 2617 /* 2618 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2619 * based value that indicates the length, in bytes, of 2620 * the data block. A maximum of length of 256KB may 2621 * exist for any entry. Bits 1:0 of this field shall be 2622 * 11b to indicate Dword granularity. A value of '3' 2623 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2624 */ 2625 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2626 prd->size = cpu_to_le32(len - 1); 2627 prd->addr = cpu_to_le64(sg->dma_address); 2628 prd->reserved = 0; 2629 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2630 } 2631 } else { 2632 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2633 } 2634 } 2635 2636 /** 2637 * ufshcd_map_sg - Map scatter-gather list to prdt 2638 * @hba: per adapter instance 2639 * @lrbp: pointer to local reference block 2640 * 2641 * Return: 0 in case of success, non-zero value in case of failure. 2642 */ 2643 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2644 { 2645 struct scsi_cmnd *cmd = lrbp->cmd; 2646 int sg_segments = scsi_dma_map(cmd); 2647 2648 if (sg_segments < 0) 2649 return sg_segments; 2650 2651 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2652 2653 return ufshcd_crypto_fill_prdt(hba, lrbp); 2654 } 2655 2656 /** 2657 * ufshcd_enable_intr - enable interrupts 2658 * @hba: per adapter instance 2659 * @intrs: interrupt bits 2660 */ 2661 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2662 { 2663 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2664 2665 set |= intrs; 2666 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2667 } 2668 2669 /** 2670 * ufshcd_disable_intr - disable interrupts 2671 * @hba: per adapter instance 2672 * @intrs: interrupt bits 2673 */ 2674 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2675 { 2676 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2677 2678 set &= ~intrs; 2679 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2680 } 2681 2682 /** 2683 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2684 * descriptor according to request 2685 * @hba: per adapter instance 2686 * @lrbp: pointer to local reference block 2687 * @upiu_flags: flags required in the header 2688 * @cmd_dir: requests data direction 2689 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2690 */ 2691 static void 2692 ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 2693 u8 *upiu_flags, enum dma_data_direction cmd_dir, 2694 int ehs_length) 2695 { 2696 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2697 struct request_desc_header *h = &req_desc->header; 2698 enum utp_data_direction data_direction; 2699 2700 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2701 2702 *h = (typeof(*h)){ }; 2703 2704 if (cmd_dir == DMA_FROM_DEVICE) { 2705 data_direction = UTP_DEVICE_TO_HOST; 2706 *upiu_flags = UPIU_CMD_FLAGS_READ; 2707 } else if (cmd_dir == DMA_TO_DEVICE) { 2708 data_direction = UTP_HOST_TO_DEVICE; 2709 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2710 } else { 2711 data_direction = UTP_NO_DATA_TRANSFER; 2712 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2713 } 2714 2715 h->command_type = lrbp->command_type; 2716 h->data_direction = data_direction; 2717 h->ehs_length = ehs_length; 2718 2719 if (lrbp->intr_cmd) 2720 h->interrupt = 1; 2721 2722 /* Prepare crypto related dwords */ 2723 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2724 2725 /* 2726 * assigning invalid value for command status. Controller 2727 * updates OCS on command completion, with the command 2728 * status 2729 */ 2730 h->ocs = OCS_INVALID_COMMAND_STATUS; 2731 2732 req_desc->prd_table_length = 0; 2733 } 2734 2735 /** 2736 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2737 * for scsi commands 2738 * @lrbp: local reference block pointer 2739 * @upiu_flags: flags 2740 */ 2741 static 2742 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2743 { 2744 struct scsi_cmnd *cmd = lrbp->cmd; 2745 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2746 unsigned short cdb_len; 2747 2748 ucd_req_ptr->header = (struct utp_upiu_header){ 2749 .transaction_code = UPIU_TRANSACTION_COMMAND, 2750 .flags = upiu_flags, 2751 .lun = lrbp->lun, 2752 .task_tag = lrbp->task_tag, 2753 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2754 }; 2755 2756 WARN_ON_ONCE(ucd_req_ptr->header.task_tag != lrbp->task_tag); 2757 2758 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2759 2760 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2761 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 2762 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2763 2764 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2765 } 2766 2767 /** 2768 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2769 * @hba: UFS hba 2770 * @lrbp: local reference block pointer 2771 * @upiu_flags: flags 2772 */ 2773 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2774 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2775 { 2776 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2777 struct ufs_query *query = &hba->dev_cmd.query; 2778 u16 len = be16_to_cpu(query->request.upiu_req.length); 2779 2780 /* Query request header */ 2781 ucd_req_ptr->header = (struct utp_upiu_header){ 2782 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2783 .flags = upiu_flags, 2784 .lun = lrbp->lun, 2785 .task_tag = lrbp->task_tag, 2786 .query_function = query->request.query_func, 2787 /* Data segment length only need for WRITE_DESC */ 2788 .data_segment_length = 2789 query->request.upiu_req.opcode == 2790 UPIU_QUERY_OPCODE_WRITE_DESC ? 2791 cpu_to_be16(len) : 2792 0, 2793 }; 2794 2795 /* Copy the Query Request buffer as is */ 2796 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2797 QUERY_OSF_SIZE); 2798 2799 /* Copy the Descriptor */ 2800 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2801 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2802 2803 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2804 } 2805 2806 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2807 { 2808 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2809 2810 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2811 2812 ucd_req_ptr->header = (struct utp_upiu_header){ 2813 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2814 .task_tag = lrbp->task_tag, 2815 }; 2816 2817 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2818 } 2819 2820 /** 2821 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2822 * for Device Management Purposes 2823 * @hba: per adapter instance 2824 * @lrbp: pointer to local reference block 2825 * 2826 * Return: 0 upon success; < 0 upon failure. 2827 */ 2828 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2829 struct ufshcd_lrb *lrbp) 2830 { 2831 u8 upiu_flags; 2832 int ret = 0; 2833 2834 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 2835 2836 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2837 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2838 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2839 ufshcd_prepare_utp_nop_upiu(lrbp); 2840 else 2841 ret = -EINVAL; 2842 2843 return ret; 2844 } 2845 2846 /** 2847 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2848 * for SCSI Purposes 2849 * @hba: per adapter instance 2850 * @lrbp: pointer to local reference block 2851 */ 2852 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2853 { 2854 struct request *rq = scsi_cmd_to_rq(lrbp->cmd); 2855 unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq)); 2856 u8 upiu_flags; 2857 2858 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0); 2859 if (ioprio_class == IOPRIO_CLASS_RT) 2860 upiu_flags |= UPIU_CMD_FLAGS_CP; 2861 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2862 } 2863 2864 /** 2865 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2866 * @upiu_wlun_id: UPIU W-LUN id 2867 * 2868 * Return: SCSI W-LUN id. 2869 */ 2870 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2871 { 2872 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2873 } 2874 2875 static inline bool is_device_wlun(struct scsi_device *sdev) 2876 { 2877 return sdev->lun == 2878 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2879 } 2880 2881 /* 2882 * Associate the UFS controller queue with the default and poll HCTX types. 2883 * Initialize the mq_map[] arrays. 2884 */ 2885 static void ufshcd_map_queues(struct Scsi_Host *shost) 2886 { 2887 struct ufs_hba *hba = shost_priv(shost); 2888 int i, queue_offset = 0; 2889 2890 if (!is_mcq_supported(hba)) { 2891 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2892 hba->nr_queues[HCTX_TYPE_READ] = 0; 2893 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2894 hba->nr_hw_queues = 1; 2895 } 2896 2897 for (i = 0; i < shost->nr_maps; i++) { 2898 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2899 2900 map->nr_queues = hba->nr_queues[i]; 2901 if (!map->nr_queues) 2902 continue; 2903 map->queue_offset = queue_offset; 2904 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2905 map->queue_offset = 0; 2906 2907 blk_mq_map_queues(map); 2908 queue_offset += map->nr_queues; 2909 } 2910 } 2911 2912 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2913 { 2914 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2915 i * ufshcd_get_ucd_size(hba); 2916 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2917 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2918 i * ufshcd_get_ucd_size(hba); 2919 u16 response_offset = offsetof(struct utp_transfer_cmd_desc, 2920 response_upiu); 2921 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 2922 2923 lrb->utr_descriptor_ptr = utrdlp + i; 2924 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2925 i * sizeof(struct utp_transfer_req_desc); 2926 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2927 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2928 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2929 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2930 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2931 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2932 } 2933 2934 /** 2935 * ufshcd_queuecommand - main entry point for SCSI requests 2936 * @host: SCSI host pointer 2937 * @cmd: command from SCSI Midlayer 2938 * 2939 * Return: 0 for success, non-zero in case of failure. 2940 */ 2941 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2942 { 2943 struct ufs_hba *hba = shost_priv(host); 2944 int tag = scsi_cmd_to_rq(cmd)->tag; 2945 struct ufshcd_lrb *lrbp; 2946 int err = 0; 2947 struct ufs_hw_queue *hwq = NULL; 2948 2949 switch (hba->ufshcd_state) { 2950 case UFSHCD_STATE_OPERATIONAL: 2951 break; 2952 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2953 /* 2954 * SCSI error handler can call ->queuecommand() while UFS error 2955 * handler is in progress. Error interrupts could change the 2956 * state from UFSHCD_STATE_RESET to 2957 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2958 * being issued in that case. 2959 */ 2960 if (ufshcd_eh_in_progress(hba)) { 2961 err = SCSI_MLQUEUE_HOST_BUSY; 2962 goto out; 2963 } 2964 break; 2965 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2966 /* 2967 * pm_runtime_get_sync() is used at error handling preparation 2968 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2969 * PM ops, it can never be finished if we let SCSI layer keep 2970 * retrying it, which gets err handler stuck forever. Neither 2971 * can we let the scsi cmd pass through, because UFS is in bad 2972 * state, the scsi cmd may eventually time out, which will get 2973 * err handler blocked for too long. So, just fail the scsi cmd 2974 * sent from PM ops, err handler can recover PM error anyways. 2975 */ 2976 if (hba->pm_op_in_progress) { 2977 hba->force_reset = true; 2978 set_host_byte(cmd, DID_BAD_TARGET); 2979 scsi_done(cmd); 2980 goto out; 2981 } 2982 fallthrough; 2983 case UFSHCD_STATE_RESET: 2984 err = SCSI_MLQUEUE_HOST_BUSY; 2985 goto out; 2986 case UFSHCD_STATE_ERROR: 2987 set_host_byte(cmd, DID_ERROR); 2988 scsi_done(cmd); 2989 goto out; 2990 } 2991 2992 hba->req_abort_count = 0; 2993 2994 ufshcd_hold(hba); 2995 2996 lrbp = &hba->lrb[tag]; 2997 lrbp->cmd = cmd; 2998 lrbp->task_tag = tag; 2999 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 3000 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 3001 3002 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp); 3003 3004 lrbp->req_abort_skip = false; 3005 3006 ufshcd_comp_scsi_upiu(hba, lrbp); 3007 3008 err = ufshcd_map_sg(hba, lrbp); 3009 if (err) { 3010 ufshcd_release(hba); 3011 goto out; 3012 } 3013 3014 if (hba->mcq_enabled) 3015 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 3016 3017 ufshcd_send_command(hba, tag, hwq); 3018 3019 out: 3020 if (ufs_trigger_eh(hba)) { 3021 unsigned long flags; 3022 3023 spin_lock_irqsave(hba->host->host_lock, flags); 3024 ufshcd_schedule_eh_work(hba); 3025 spin_unlock_irqrestore(hba->host->host_lock, flags); 3026 } 3027 3028 return err; 3029 } 3030 3031 static void ufshcd_setup_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3032 enum dev_cmd_type cmd_type, u8 lun, int tag) 3033 { 3034 lrbp->cmd = NULL; 3035 lrbp->task_tag = tag; 3036 lrbp->lun = lun; 3037 lrbp->intr_cmd = true; /* No interrupt aggregation */ 3038 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 3039 hba->dev_cmd.type = cmd_type; 3040 } 3041 3042 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 3043 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 3044 { 3045 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 3046 3047 return ufshcd_compose_devman_upiu(hba, lrbp); 3048 } 3049 3050 /* 3051 * Check with the block layer if the command is inflight 3052 * @cmd: command to check. 3053 * 3054 * Return: true if command is inflight; false if not. 3055 */ 3056 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 3057 { 3058 return cmd && blk_mq_rq_state(scsi_cmd_to_rq(cmd)) == MQ_RQ_IN_FLIGHT; 3059 } 3060 3061 /* 3062 * Clear the pending command in the controller and wait until 3063 * the controller confirms that the command has been cleared. 3064 * @hba: per adapter instance 3065 * @task_tag: The tag number of the command to be cleared. 3066 */ 3067 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 3068 { 3069 u32 mask; 3070 unsigned long flags; 3071 int err; 3072 3073 if (hba->mcq_enabled) { 3074 /* 3075 * MCQ mode. Clean up the MCQ resources similar to 3076 * what the ufshcd_utrl_clear() does for SDB mode. 3077 */ 3078 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 3079 if (err) { 3080 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 3081 __func__, task_tag, err); 3082 return err; 3083 } 3084 return 0; 3085 } 3086 3087 mask = 1U << task_tag; 3088 3089 /* clear outstanding transaction before retry */ 3090 spin_lock_irqsave(hba->host->host_lock, flags); 3091 ufshcd_utrl_clear(hba, mask); 3092 spin_unlock_irqrestore(hba->host->host_lock, flags); 3093 3094 /* 3095 * wait for h/w to clear corresponding bit in door-bell. 3096 * max. wait is 1 sec. 3097 */ 3098 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 3099 mask, ~mask, 1000, 1000); 3100 } 3101 3102 /** 3103 * ufshcd_dev_cmd_completion() - handles device management command responses 3104 * @hba: per adapter instance 3105 * @lrbp: pointer to local reference block 3106 * 3107 * Return: 0 upon success; < 0 upon failure. 3108 */ 3109 static int 3110 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 3111 { 3112 enum upiu_response_transaction resp; 3113 int err = 0; 3114 3115 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 3116 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3117 3118 switch (resp) { 3119 case UPIU_TRANSACTION_NOP_IN: 3120 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3121 err = -EINVAL; 3122 dev_err(hba->dev, "%s: unexpected response %x\n", 3123 __func__, resp); 3124 } 3125 break; 3126 case UPIU_TRANSACTION_QUERY_RSP: { 3127 u8 response = lrbp->ucd_rsp_ptr->header.response; 3128 3129 if (response == 0) 3130 err = ufshcd_copy_query_response(hba, lrbp); 3131 break; 3132 } 3133 case UPIU_TRANSACTION_REJECT_UPIU: 3134 /* TODO: handle Reject UPIU Response */ 3135 err = -EPERM; 3136 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3137 __func__); 3138 break; 3139 case UPIU_TRANSACTION_RESPONSE: 3140 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3141 err = -EINVAL; 3142 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3143 } 3144 break; 3145 default: 3146 err = -EINVAL; 3147 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3148 __func__, resp); 3149 break; 3150 } 3151 3152 return err; 3153 } 3154 3155 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3156 struct ufshcd_lrb *lrbp, int max_timeout) 3157 { 3158 unsigned long time_left = msecs_to_jiffies(max_timeout); 3159 unsigned long flags; 3160 bool pending; 3161 int err; 3162 3163 retry: 3164 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3165 time_left); 3166 3167 if (likely(time_left)) { 3168 /* 3169 * The completion handler called complete() and the caller of 3170 * this function still owns the @lrbp tag so the code below does 3171 * not trigger any race conditions. 3172 */ 3173 hba->dev_cmd.complete = NULL; 3174 err = ufshcd_get_tr_ocs(lrbp, NULL); 3175 if (!err) 3176 err = ufshcd_dev_cmd_completion(hba, lrbp); 3177 } else { 3178 err = -ETIMEDOUT; 3179 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3180 __func__, lrbp->task_tag); 3181 3182 /* MCQ mode */ 3183 if (hba->mcq_enabled) { 3184 /* successfully cleared the command, retry if needed */ 3185 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) 3186 err = -EAGAIN; 3187 hba->dev_cmd.complete = NULL; 3188 return err; 3189 } 3190 3191 /* SDB mode */ 3192 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3193 /* successfully cleared the command, retry if needed */ 3194 err = -EAGAIN; 3195 /* 3196 * Since clearing the command succeeded we also need to 3197 * clear the task tag bit from the outstanding_reqs 3198 * variable. 3199 */ 3200 spin_lock_irqsave(&hba->outstanding_lock, flags); 3201 pending = test_bit(lrbp->task_tag, 3202 &hba->outstanding_reqs); 3203 if (pending) { 3204 hba->dev_cmd.complete = NULL; 3205 __clear_bit(lrbp->task_tag, 3206 &hba->outstanding_reqs); 3207 } 3208 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3209 3210 if (!pending) { 3211 /* 3212 * The completion handler ran while we tried to 3213 * clear the command. 3214 */ 3215 time_left = 1; 3216 goto retry; 3217 } 3218 } else { 3219 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3220 __func__, lrbp->task_tag); 3221 3222 spin_lock_irqsave(&hba->outstanding_lock, flags); 3223 pending = test_bit(lrbp->task_tag, 3224 &hba->outstanding_reqs); 3225 if (pending) 3226 hba->dev_cmd.complete = NULL; 3227 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3228 3229 if (!pending) { 3230 /* 3231 * The completion handler ran while we tried to 3232 * clear the command. 3233 */ 3234 time_left = 1; 3235 goto retry; 3236 } 3237 } 3238 } 3239 3240 return err; 3241 } 3242 3243 static void ufshcd_dev_man_lock(struct ufs_hba *hba) 3244 { 3245 ufshcd_hold(hba); 3246 mutex_lock(&hba->dev_cmd.lock); 3247 down_read(&hba->clk_scaling_lock); 3248 } 3249 3250 static void ufshcd_dev_man_unlock(struct ufs_hba *hba) 3251 { 3252 up_read(&hba->clk_scaling_lock); 3253 mutex_unlock(&hba->dev_cmd.lock); 3254 ufshcd_release(hba); 3255 } 3256 3257 static int ufshcd_issue_dev_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 3258 const u32 tag, int timeout) 3259 { 3260 DECLARE_COMPLETION_ONSTACK(wait); 3261 int err; 3262 3263 hba->dev_cmd.complete = &wait; 3264 3265 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3266 3267 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3268 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3269 3270 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3271 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3272 3273 return err; 3274 } 3275 3276 /** 3277 * ufshcd_exec_dev_cmd - API for sending device management requests 3278 * @hba: UFS hba 3279 * @cmd_type: specifies the type (NOP, Query...) 3280 * @timeout: timeout in milliseconds 3281 * 3282 * Return: 0 upon success; < 0 upon failure. 3283 * 3284 * NOTE: Since there is only one available tag for device management commands, 3285 * it is expected you hold the hba->dev_cmd.lock mutex. 3286 */ 3287 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3288 enum dev_cmd_type cmd_type, int timeout) 3289 { 3290 const u32 tag = hba->reserved_slot; 3291 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 3292 int err; 3293 3294 /* Protects use of hba->reserved_slot. */ 3295 lockdep_assert_held(&hba->dev_cmd.lock); 3296 3297 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3298 if (unlikely(err)) 3299 return err; 3300 3301 return ufshcd_issue_dev_cmd(hba, lrbp, tag, timeout); 3302 } 3303 3304 /** 3305 * ufshcd_init_query() - init the query response and request parameters 3306 * @hba: per-adapter instance 3307 * @request: address of the request pointer to be initialized 3308 * @response: address of the response pointer to be initialized 3309 * @opcode: operation to perform 3310 * @idn: flag idn to access 3311 * @index: LU number to access 3312 * @selector: query/flag/descriptor further identification 3313 */ 3314 static inline void ufshcd_init_query(struct ufs_hba *hba, 3315 struct ufs_query_req **request, struct ufs_query_res **response, 3316 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3317 { 3318 *request = &hba->dev_cmd.query.request; 3319 *response = &hba->dev_cmd.query.response; 3320 memset(*request, 0, sizeof(struct ufs_query_req)); 3321 memset(*response, 0, sizeof(struct ufs_query_res)); 3322 (*request)->upiu_req.opcode = opcode; 3323 (*request)->upiu_req.idn = idn; 3324 (*request)->upiu_req.index = index; 3325 (*request)->upiu_req.selector = selector; 3326 } 3327 3328 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3329 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3330 { 3331 int ret; 3332 int retries; 3333 3334 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3335 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3336 if (ret) 3337 dev_dbg(hba->dev, 3338 "%s: failed with error %d, retries %d\n", 3339 __func__, ret, retries); 3340 else 3341 break; 3342 } 3343 3344 if (ret) 3345 dev_err(hba->dev, 3346 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3347 __func__, opcode, idn, ret, retries); 3348 return ret; 3349 } 3350 3351 /** 3352 * ufshcd_query_flag() - API function for sending flag query requests 3353 * @hba: per-adapter instance 3354 * @opcode: flag query to perform 3355 * @idn: flag idn to access 3356 * @index: flag index to access 3357 * @flag_res: the flag value after the query request completes 3358 * 3359 * Return: 0 for success, non-zero in case of failure. 3360 */ 3361 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3362 enum flag_idn idn, u8 index, bool *flag_res) 3363 { 3364 struct ufs_query_req *request = NULL; 3365 struct ufs_query_res *response = NULL; 3366 int err, selector = 0; 3367 int timeout = QUERY_REQ_TIMEOUT; 3368 3369 BUG_ON(!hba); 3370 3371 ufshcd_dev_man_lock(hba); 3372 3373 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3374 selector); 3375 3376 switch (opcode) { 3377 case UPIU_QUERY_OPCODE_SET_FLAG: 3378 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3379 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3380 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3381 break; 3382 case UPIU_QUERY_OPCODE_READ_FLAG: 3383 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3384 if (!flag_res) { 3385 /* No dummy reads */ 3386 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3387 __func__); 3388 err = -EINVAL; 3389 goto out_unlock; 3390 } 3391 break; 3392 default: 3393 dev_err(hba->dev, 3394 "%s: Expected query flag opcode but got = %d\n", 3395 __func__, opcode); 3396 err = -EINVAL; 3397 goto out_unlock; 3398 } 3399 3400 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3401 3402 if (err) { 3403 dev_err(hba->dev, 3404 "%s: Sending flag query for idn %d failed, err = %d\n", 3405 __func__, idn, err); 3406 goto out_unlock; 3407 } 3408 3409 if (flag_res) 3410 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3411 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3412 3413 out_unlock: 3414 ufshcd_dev_man_unlock(hba); 3415 return err; 3416 } 3417 3418 /** 3419 * ufshcd_query_attr - API function for sending attribute requests 3420 * @hba: per-adapter instance 3421 * @opcode: attribute opcode 3422 * @idn: attribute idn to access 3423 * @index: index field 3424 * @selector: selector field 3425 * @attr_val: the attribute value after the query request completes 3426 * 3427 * Return: 0 for success, non-zero in case of failure. 3428 */ 3429 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3430 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3431 { 3432 struct ufs_query_req *request = NULL; 3433 struct ufs_query_res *response = NULL; 3434 int err; 3435 3436 BUG_ON(!hba); 3437 3438 if (!attr_val) { 3439 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3440 __func__, opcode); 3441 return -EINVAL; 3442 } 3443 3444 ufshcd_dev_man_lock(hba); 3445 3446 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3447 selector); 3448 3449 switch (opcode) { 3450 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3451 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3452 request->upiu_req.value = cpu_to_be32(*attr_val); 3453 break; 3454 case UPIU_QUERY_OPCODE_READ_ATTR: 3455 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3456 break; 3457 default: 3458 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3459 __func__, opcode); 3460 err = -EINVAL; 3461 goto out_unlock; 3462 } 3463 3464 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3465 3466 if (err) { 3467 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3468 __func__, opcode, idn, index, err); 3469 goto out_unlock; 3470 } 3471 3472 *attr_val = be32_to_cpu(response->upiu_res.value); 3473 3474 out_unlock: 3475 ufshcd_dev_man_unlock(hba); 3476 return err; 3477 } 3478 3479 /** 3480 * ufshcd_query_attr_retry() - API function for sending query 3481 * attribute with retries 3482 * @hba: per-adapter instance 3483 * @opcode: attribute opcode 3484 * @idn: attribute idn to access 3485 * @index: index field 3486 * @selector: selector field 3487 * @attr_val: the attribute value after the query request 3488 * completes 3489 * 3490 * Return: 0 for success, non-zero in case of failure. 3491 */ 3492 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3493 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3494 u32 *attr_val) 3495 { 3496 int ret = 0; 3497 u32 retries; 3498 3499 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3500 ret = ufshcd_query_attr(hba, opcode, idn, index, 3501 selector, attr_val); 3502 if (ret) 3503 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3504 __func__, ret, retries); 3505 else 3506 break; 3507 } 3508 3509 if (ret) 3510 dev_err(hba->dev, 3511 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3512 __func__, idn, ret, QUERY_REQ_RETRIES); 3513 return ret; 3514 } 3515 3516 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3517 enum query_opcode opcode, enum desc_idn idn, u8 index, 3518 u8 selector, u8 *desc_buf, int *buf_len) 3519 { 3520 struct ufs_query_req *request = NULL; 3521 struct ufs_query_res *response = NULL; 3522 int err; 3523 3524 BUG_ON(!hba); 3525 3526 if (!desc_buf) { 3527 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3528 __func__, opcode); 3529 return -EINVAL; 3530 } 3531 3532 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3533 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3534 __func__, *buf_len); 3535 return -EINVAL; 3536 } 3537 3538 ufshcd_dev_man_lock(hba); 3539 3540 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3541 selector); 3542 hba->dev_cmd.query.descriptor = desc_buf; 3543 request->upiu_req.length = cpu_to_be16(*buf_len); 3544 3545 switch (opcode) { 3546 case UPIU_QUERY_OPCODE_WRITE_DESC: 3547 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3548 break; 3549 case UPIU_QUERY_OPCODE_READ_DESC: 3550 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3551 break; 3552 default: 3553 dev_err(hba->dev, 3554 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3555 __func__, opcode); 3556 err = -EINVAL; 3557 goto out_unlock; 3558 } 3559 3560 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3561 3562 if (err) { 3563 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3564 __func__, opcode, idn, index, err); 3565 goto out_unlock; 3566 } 3567 3568 *buf_len = be16_to_cpu(response->upiu_res.length); 3569 3570 out_unlock: 3571 hba->dev_cmd.query.descriptor = NULL; 3572 ufshcd_dev_man_unlock(hba); 3573 return err; 3574 } 3575 3576 /** 3577 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3578 * @hba: per-adapter instance 3579 * @opcode: attribute opcode 3580 * @idn: attribute idn to access 3581 * @index: index field 3582 * @selector: selector field 3583 * @desc_buf: the buffer that contains the descriptor 3584 * @buf_len: length parameter passed to the device 3585 * 3586 * The buf_len parameter will contain, on return, the length parameter 3587 * received on the response. 3588 * 3589 * Return: 0 for success, non-zero in case of failure. 3590 */ 3591 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3592 enum query_opcode opcode, 3593 enum desc_idn idn, u8 index, 3594 u8 selector, 3595 u8 *desc_buf, int *buf_len) 3596 { 3597 int err; 3598 int retries; 3599 3600 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3601 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3602 selector, desc_buf, buf_len); 3603 if (!err || err == -EINVAL) 3604 break; 3605 } 3606 3607 return err; 3608 } 3609 3610 /** 3611 * ufshcd_read_desc_param - read the specified descriptor parameter 3612 * @hba: Pointer to adapter instance 3613 * @desc_id: descriptor idn value 3614 * @desc_index: descriptor index 3615 * @param_offset: offset of the parameter to read 3616 * @param_read_buf: pointer to buffer where parameter would be read 3617 * @param_size: sizeof(param_read_buf) 3618 * 3619 * Return: 0 in case of success, non-zero otherwise. 3620 */ 3621 int ufshcd_read_desc_param(struct ufs_hba *hba, 3622 enum desc_idn desc_id, 3623 int desc_index, 3624 u8 param_offset, 3625 u8 *param_read_buf, 3626 u8 param_size) 3627 { 3628 int ret; 3629 u8 *desc_buf; 3630 int buff_len = QUERY_DESC_MAX_SIZE; 3631 bool is_kmalloc = true; 3632 3633 /* Safety check */ 3634 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3635 return -EINVAL; 3636 3637 /* Check whether we need temp memory */ 3638 if (param_offset != 0 || param_size < buff_len) { 3639 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3640 if (!desc_buf) 3641 return -ENOMEM; 3642 } else { 3643 desc_buf = param_read_buf; 3644 is_kmalloc = false; 3645 } 3646 3647 /* Request for full descriptor */ 3648 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3649 desc_id, desc_index, 0, 3650 desc_buf, &buff_len); 3651 if (ret) { 3652 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3653 __func__, desc_id, desc_index, param_offset, ret); 3654 goto out; 3655 } 3656 3657 /* Update descriptor length */ 3658 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3659 3660 if (param_offset >= buff_len) { 3661 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3662 __func__, param_offset, desc_id, buff_len); 3663 ret = -EINVAL; 3664 goto out; 3665 } 3666 3667 /* Sanity check */ 3668 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3669 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3670 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3671 ret = -EINVAL; 3672 goto out; 3673 } 3674 3675 if (is_kmalloc) { 3676 /* Make sure we don't copy more data than available */ 3677 if (param_offset >= buff_len) 3678 ret = -EINVAL; 3679 else 3680 memcpy(param_read_buf, &desc_buf[param_offset], 3681 min_t(u32, param_size, buff_len - param_offset)); 3682 } 3683 out: 3684 if (is_kmalloc) 3685 kfree(desc_buf); 3686 return ret; 3687 } 3688 3689 /** 3690 * struct uc_string_id - unicode string 3691 * 3692 * @len: size of this descriptor inclusive 3693 * @type: descriptor type 3694 * @uc: unicode string character 3695 */ 3696 struct uc_string_id { 3697 u8 len; 3698 u8 type; 3699 wchar_t uc[]; 3700 } __packed; 3701 3702 /* replace non-printable or non-ASCII characters with spaces */ 3703 static inline char ufshcd_remove_non_printable(u8 ch) 3704 { 3705 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3706 } 3707 3708 /** 3709 * ufshcd_read_string_desc - read string descriptor 3710 * @hba: pointer to adapter instance 3711 * @desc_index: descriptor index 3712 * @buf: pointer to buffer where descriptor would be read, 3713 * the caller should free the memory. 3714 * @ascii: if true convert from unicode to ascii characters 3715 * null terminated string. 3716 * 3717 * Return: 3718 * * string size on success. 3719 * * -ENOMEM: on allocation failure 3720 * * -EINVAL: on a wrong parameter 3721 */ 3722 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3723 u8 **buf, bool ascii) 3724 { 3725 struct uc_string_id *uc_str; 3726 u8 *str; 3727 int ret; 3728 3729 if (!buf) 3730 return -EINVAL; 3731 3732 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3733 if (!uc_str) 3734 return -ENOMEM; 3735 3736 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3737 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3738 if (ret < 0) { 3739 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3740 QUERY_REQ_RETRIES, ret); 3741 str = NULL; 3742 goto out; 3743 } 3744 3745 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3746 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3747 str = NULL; 3748 ret = 0; 3749 goto out; 3750 } 3751 3752 if (ascii) { 3753 ssize_t ascii_len; 3754 int i; 3755 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3756 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3757 str = kzalloc(ascii_len, GFP_KERNEL); 3758 if (!str) { 3759 ret = -ENOMEM; 3760 goto out; 3761 } 3762 3763 /* 3764 * the descriptor contains string in UTF16 format 3765 * we need to convert to utf-8 so it can be displayed 3766 */ 3767 ret = utf16s_to_utf8s(uc_str->uc, 3768 uc_str->len - QUERY_DESC_HDR_SIZE, 3769 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3770 3771 /* replace non-printable or non-ASCII characters with spaces */ 3772 for (i = 0; i < ret; i++) 3773 str[i] = ufshcd_remove_non_printable(str[i]); 3774 3775 str[ret++] = '\0'; 3776 3777 } else { 3778 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3779 if (!str) { 3780 ret = -ENOMEM; 3781 goto out; 3782 } 3783 ret = uc_str->len; 3784 } 3785 out: 3786 *buf = str; 3787 kfree(uc_str); 3788 return ret; 3789 } 3790 3791 /** 3792 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3793 * @hba: Pointer to adapter instance 3794 * @lun: lun id 3795 * @param_offset: offset of the parameter to read 3796 * @param_read_buf: pointer to buffer where parameter would be read 3797 * @param_size: sizeof(param_read_buf) 3798 * 3799 * Return: 0 in case of success, non-zero otherwise. 3800 */ 3801 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3802 int lun, 3803 enum unit_desc_param param_offset, 3804 u8 *param_read_buf, 3805 u32 param_size) 3806 { 3807 /* 3808 * Unit descriptors are only available for general purpose LUs (LUN id 3809 * from 0 to 7) and RPMB Well known LU. 3810 */ 3811 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3812 return -EOPNOTSUPP; 3813 3814 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3815 param_offset, param_read_buf, param_size); 3816 } 3817 3818 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3819 { 3820 int err = 0; 3821 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3822 3823 if (hba->dev_info.wspecversion >= 0x300) { 3824 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3825 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3826 &gating_wait); 3827 if (err) 3828 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3829 err, gating_wait); 3830 3831 if (gating_wait == 0) { 3832 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3833 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3834 gating_wait); 3835 } 3836 3837 hba->dev_info.clk_gating_wait_us = gating_wait; 3838 } 3839 3840 return err; 3841 } 3842 3843 /** 3844 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3845 * @hba: per adapter instance 3846 * 3847 * 1. Allocate DMA memory for Command Descriptor array 3848 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3849 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3850 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3851 * (UTMRDL) 3852 * 4. Allocate memory for local reference block(lrb). 3853 * 3854 * Return: 0 for success, non-zero in case of failure. 3855 */ 3856 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3857 { 3858 size_t utmrdl_size, utrdl_size, ucdl_size; 3859 3860 /* Allocate memory for UTP command descriptors */ 3861 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3862 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3863 ucdl_size, 3864 &hba->ucdl_dma_addr, 3865 GFP_KERNEL); 3866 3867 /* 3868 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3869 */ 3870 if (!hba->ucdl_base_addr || 3871 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3872 dev_err(hba->dev, 3873 "Command Descriptor Memory allocation failed\n"); 3874 goto out; 3875 } 3876 3877 /* 3878 * Allocate memory for UTP Transfer descriptors 3879 * UFSHCI requires 1KB alignment of UTRD 3880 */ 3881 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3882 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3883 utrdl_size, 3884 &hba->utrdl_dma_addr, 3885 GFP_KERNEL); 3886 if (!hba->utrdl_base_addr || 3887 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3888 dev_err(hba->dev, 3889 "Transfer Descriptor Memory allocation failed\n"); 3890 goto out; 3891 } 3892 3893 /* 3894 * Skip utmrdl allocation; it may have been 3895 * allocated during first pass and not released during 3896 * MCQ memory allocation. 3897 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3898 */ 3899 if (hba->utmrdl_base_addr) 3900 goto skip_utmrdl; 3901 /* 3902 * Allocate memory for UTP Task Management descriptors 3903 * UFSHCI requires 1KB alignment of UTMRD 3904 */ 3905 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3906 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3907 utmrdl_size, 3908 &hba->utmrdl_dma_addr, 3909 GFP_KERNEL); 3910 if (!hba->utmrdl_base_addr || 3911 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3912 dev_err(hba->dev, 3913 "Task Management Descriptor Memory allocation failed\n"); 3914 goto out; 3915 } 3916 3917 skip_utmrdl: 3918 /* Allocate memory for local reference block */ 3919 hba->lrb = devm_kcalloc(hba->dev, 3920 hba->nutrs, sizeof(struct ufshcd_lrb), 3921 GFP_KERNEL); 3922 if (!hba->lrb) { 3923 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3924 goto out; 3925 } 3926 return 0; 3927 out: 3928 return -ENOMEM; 3929 } 3930 3931 /** 3932 * ufshcd_host_memory_configure - configure local reference block with 3933 * memory offsets 3934 * @hba: per adapter instance 3935 * 3936 * Configure Host memory space 3937 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3938 * address. 3939 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3940 * and PRDT offset. 3941 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3942 * into local reference block. 3943 */ 3944 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3945 { 3946 struct utp_transfer_req_desc *utrdlp; 3947 dma_addr_t cmd_desc_dma_addr; 3948 dma_addr_t cmd_desc_element_addr; 3949 u16 response_offset; 3950 u16 prdt_offset; 3951 int cmd_desc_size; 3952 int i; 3953 3954 utrdlp = hba->utrdl_base_addr; 3955 3956 response_offset = 3957 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3958 prdt_offset = 3959 offsetof(struct utp_transfer_cmd_desc, prd_table); 3960 3961 cmd_desc_size = ufshcd_get_ucd_size(hba); 3962 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3963 3964 for (i = 0; i < hba->nutrs; i++) { 3965 /* Configure UTRD with command descriptor base address */ 3966 cmd_desc_element_addr = 3967 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3968 utrdlp[i].command_desc_base_addr = 3969 cpu_to_le64(cmd_desc_element_addr); 3970 3971 /* Response upiu and prdt offset should be in double words */ 3972 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3973 utrdlp[i].response_upiu_offset = 3974 cpu_to_le16(response_offset); 3975 utrdlp[i].prd_table_offset = 3976 cpu_to_le16(prdt_offset); 3977 utrdlp[i].response_upiu_length = 3978 cpu_to_le16(ALIGNED_UPIU_SIZE); 3979 } else { 3980 utrdlp[i].response_upiu_offset = 3981 cpu_to_le16(response_offset >> 2); 3982 utrdlp[i].prd_table_offset = 3983 cpu_to_le16(prdt_offset >> 2); 3984 utrdlp[i].response_upiu_length = 3985 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 3986 } 3987 3988 ufshcd_init_lrb(hba, &hba->lrb[i], i); 3989 } 3990 } 3991 3992 /** 3993 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 3994 * @hba: per adapter instance 3995 * 3996 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 3997 * in order to initialize the Unipro link startup procedure. 3998 * Once the Unipro links are up, the device connected to the controller 3999 * is detected. 4000 * 4001 * Return: 0 on success, non-zero value on failure. 4002 */ 4003 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 4004 { 4005 struct uic_command uic_cmd = { 4006 .command = UIC_CMD_DME_LINK_STARTUP, 4007 }; 4008 int ret; 4009 4010 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4011 if (ret) 4012 dev_dbg(hba->dev, 4013 "dme-link-startup: error code %d\n", ret); 4014 return ret; 4015 } 4016 /** 4017 * ufshcd_dme_reset - UIC command for DME_RESET 4018 * @hba: per adapter instance 4019 * 4020 * DME_RESET command is issued in order to reset UniPro stack. 4021 * This function now deals with cold reset. 4022 * 4023 * Return: 0 on success, non-zero value on failure. 4024 */ 4025 static int ufshcd_dme_reset(struct ufs_hba *hba) 4026 { 4027 struct uic_command uic_cmd = { 4028 .command = UIC_CMD_DME_RESET, 4029 }; 4030 int ret; 4031 4032 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4033 if (ret) 4034 dev_err(hba->dev, 4035 "dme-reset: error code %d\n", ret); 4036 4037 return ret; 4038 } 4039 4040 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 4041 int agreed_gear, 4042 int adapt_val) 4043 { 4044 int ret; 4045 4046 if (agreed_gear < UFS_HS_G4) 4047 adapt_val = PA_NO_ADAPT; 4048 4049 ret = ufshcd_dme_set(hba, 4050 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 4051 adapt_val); 4052 return ret; 4053 } 4054 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 4055 4056 /** 4057 * ufshcd_dme_enable - UIC command for DME_ENABLE 4058 * @hba: per adapter instance 4059 * 4060 * DME_ENABLE command is issued in order to enable UniPro stack. 4061 * 4062 * Return: 0 on success, non-zero value on failure. 4063 */ 4064 static int ufshcd_dme_enable(struct ufs_hba *hba) 4065 { 4066 struct uic_command uic_cmd = { 4067 .command = UIC_CMD_DME_ENABLE, 4068 }; 4069 int ret; 4070 4071 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4072 if (ret) 4073 dev_err(hba->dev, 4074 "dme-enable: error code %d\n", ret); 4075 4076 return ret; 4077 } 4078 4079 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 4080 { 4081 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 4082 unsigned long min_sleep_time_us; 4083 4084 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 4085 return; 4086 4087 /* 4088 * last_dme_cmd_tstamp will be 0 only for 1st call to 4089 * this function 4090 */ 4091 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 4092 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 4093 } else { 4094 unsigned long delta = 4095 (unsigned long) ktime_to_us( 4096 ktime_sub(ktime_get(), 4097 hba->last_dme_cmd_tstamp)); 4098 4099 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 4100 min_sleep_time_us = 4101 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 4102 else 4103 min_sleep_time_us = 0; /* no more delay required */ 4104 } 4105 4106 if (min_sleep_time_us > 0) { 4107 /* allow sleep for extra 50us if needed */ 4108 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 4109 } 4110 4111 /* update the last_dme_cmd_tstamp */ 4112 hba->last_dme_cmd_tstamp = ktime_get(); 4113 } 4114 4115 /** 4116 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 4117 * @hba: per adapter instance 4118 * @attr_sel: uic command argument1 4119 * @attr_set: attribute set type as uic command argument2 4120 * @mib_val: setting value as uic command argument3 4121 * @peer: indicate whether peer or local 4122 * 4123 * Return: 0 on success, non-zero value on failure. 4124 */ 4125 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 4126 u8 attr_set, u32 mib_val, u8 peer) 4127 { 4128 struct uic_command uic_cmd = { 4129 .command = peer ? UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET, 4130 .argument1 = attr_sel, 4131 .argument2 = UIC_ARG_ATTR_TYPE(attr_set), 4132 .argument3 = mib_val, 4133 }; 4134 static const char *const action[] = { 4135 "dme-set", 4136 "dme-peer-set" 4137 }; 4138 const char *set = action[!!peer]; 4139 int ret; 4140 int retries = UFS_UIC_COMMAND_RETRIES; 4141 4142 do { 4143 /* for peer attributes we retry upon failure */ 4144 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4145 if (ret) 4146 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4147 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4148 } while (ret && peer && --retries); 4149 4150 if (ret) 4151 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4152 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4153 UFS_UIC_COMMAND_RETRIES - retries); 4154 4155 return ret; 4156 } 4157 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4158 4159 /** 4160 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4161 * @hba: per adapter instance 4162 * @attr_sel: uic command argument1 4163 * @mib_val: the value of the attribute as returned by the UIC command 4164 * @peer: indicate whether peer or local 4165 * 4166 * Return: 0 on success, non-zero value on failure. 4167 */ 4168 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4169 u32 *mib_val, u8 peer) 4170 { 4171 struct uic_command uic_cmd = { 4172 .command = peer ? UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET, 4173 .argument1 = attr_sel, 4174 }; 4175 static const char *const action[] = { 4176 "dme-get", 4177 "dme-peer-get" 4178 }; 4179 const char *get = action[!!peer]; 4180 int ret; 4181 int retries = UFS_UIC_COMMAND_RETRIES; 4182 struct ufs_pa_layer_attr orig_pwr_info; 4183 struct ufs_pa_layer_attr temp_pwr_info; 4184 bool pwr_mode_change = false; 4185 4186 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4187 orig_pwr_info = hba->pwr_info; 4188 temp_pwr_info = orig_pwr_info; 4189 4190 if (orig_pwr_info.pwr_tx == FAST_MODE || 4191 orig_pwr_info.pwr_rx == FAST_MODE) { 4192 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4193 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4194 pwr_mode_change = true; 4195 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4196 orig_pwr_info.pwr_rx == SLOW_MODE) { 4197 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4198 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4199 pwr_mode_change = true; 4200 } 4201 if (pwr_mode_change) { 4202 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4203 if (ret) 4204 goto out; 4205 } 4206 } 4207 4208 do { 4209 /* for peer attributes we retry upon failure */ 4210 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4211 if (ret) 4212 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4213 get, UIC_GET_ATTR_ID(attr_sel), ret); 4214 } while (ret && peer && --retries); 4215 4216 if (ret) 4217 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4218 get, UIC_GET_ATTR_ID(attr_sel), 4219 UFS_UIC_COMMAND_RETRIES - retries); 4220 4221 if (mib_val && !ret) 4222 *mib_val = uic_cmd.argument3; 4223 4224 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4225 && pwr_mode_change) 4226 ufshcd_change_power_mode(hba, &orig_pwr_info); 4227 out: 4228 return ret; 4229 } 4230 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4231 4232 /** 4233 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4234 * state) and waits for it to take effect. 4235 * 4236 * @hba: per adapter instance 4237 * @cmd: UIC command to execute 4238 * 4239 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4240 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4241 * and device UniPro link and hence it's final completion would be indicated by 4242 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4243 * addition to normal UIC command completion Status (UCCS). This function only 4244 * returns after the relevant status bits indicate the completion. 4245 * 4246 * Return: 0 on success, non-zero value on failure. 4247 */ 4248 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4249 { 4250 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4251 unsigned long flags; 4252 u8 status; 4253 int ret; 4254 bool reenable_intr = false; 4255 4256 mutex_lock(&hba->uic_cmd_mutex); 4257 ufshcd_add_delay_before_dme_cmd(hba); 4258 4259 spin_lock_irqsave(hba->host->host_lock, flags); 4260 if (ufshcd_is_link_broken(hba)) { 4261 ret = -ENOLINK; 4262 goto out_unlock; 4263 } 4264 hba->uic_async_done = &uic_async_done; 4265 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4266 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4267 /* 4268 * Make sure UIC command completion interrupt is disabled before 4269 * issuing UIC command. 4270 */ 4271 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 4272 reenable_intr = true; 4273 } 4274 spin_unlock_irqrestore(hba->host->host_lock, flags); 4275 ret = __ufshcd_send_uic_cmd(hba, cmd, false); 4276 if (ret) { 4277 dev_err(hba->dev, 4278 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4279 cmd->command, cmd->argument3, ret); 4280 goto out; 4281 } 4282 4283 if (!wait_for_completion_timeout(hba->uic_async_done, 4284 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 4285 dev_err(hba->dev, 4286 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4287 cmd->command, cmd->argument3); 4288 4289 if (!cmd->cmd_active) { 4290 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4291 __func__); 4292 goto check_upmcrs; 4293 } 4294 4295 ret = -ETIMEDOUT; 4296 goto out; 4297 } 4298 4299 check_upmcrs: 4300 status = ufshcd_get_upmcrs(hba); 4301 if (status != PWR_LOCAL) { 4302 dev_err(hba->dev, 4303 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4304 cmd->command, status); 4305 ret = (status != PWR_OK) ? status : -1; 4306 } 4307 out: 4308 if (ret) { 4309 ufshcd_print_host_state(hba); 4310 ufshcd_print_pwr_info(hba); 4311 ufshcd_print_evt_hist(hba); 4312 } 4313 4314 spin_lock_irqsave(hba->host->host_lock, flags); 4315 hba->active_uic_cmd = NULL; 4316 hba->uic_async_done = NULL; 4317 if (reenable_intr) 4318 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4319 if (ret) { 4320 ufshcd_set_link_broken(hba); 4321 ufshcd_schedule_eh_work(hba); 4322 } 4323 out_unlock: 4324 spin_unlock_irqrestore(hba->host->host_lock, flags); 4325 mutex_unlock(&hba->uic_cmd_mutex); 4326 4327 return ret; 4328 } 4329 4330 /** 4331 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4332 * using DME_SET primitives. 4333 * @hba: per adapter instance 4334 * @mode: powr mode value 4335 * 4336 * Return: 0 on success, non-zero value on failure. 4337 */ 4338 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4339 { 4340 struct uic_command uic_cmd = { 4341 .command = UIC_CMD_DME_SET, 4342 .argument1 = UIC_ARG_MIB(PA_PWRMODE), 4343 .argument3 = mode, 4344 }; 4345 int ret; 4346 4347 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4348 ret = ufshcd_dme_set(hba, 4349 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4350 if (ret) { 4351 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4352 __func__, ret); 4353 goto out; 4354 } 4355 } 4356 4357 ufshcd_hold(hba); 4358 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4359 ufshcd_release(hba); 4360 4361 out: 4362 return ret; 4363 } 4364 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4365 4366 int ufshcd_link_recovery(struct ufs_hba *hba) 4367 { 4368 int ret; 4369 unsigned long flags; 4370 4371 spin_lock_irqsave(hba->host->host_lock, flags); 4372 hba->ufshcd_state = UFSHCD_STATE_RESET; 4373 ufshcd_set_eh_in_progress(hba); 4374 spin_unlock_irqrestore(hba->host->host_lock, flags); 4375 4376 /* Reset the attached device */ 4377 ufshcd_device_reset(hba); 4378 4379 ret = ufshcd_host_reset_and_restore(hba); 4380 4381 spin_lock_irqsave(hba->host->host_lock, flags); 4382 if (ret) 4383 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4384 ufshcd_clear_eh_in_progress(hba); 4385 spin_unlock_irqrestore(hba->host->host_lock, flags); 4386 4387 if (ret) 4388 dev_err(hba->dev, "%s: link recovery failed, err %d", 4389 __func__, ret); 4390 4391 return ret; 4392 } 4393 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4394 4395 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4396 { 4397 struct uic_command uic_cmd = { 4398 .command = UIC_CMD_DME_HIBER_ENTER, 4399 }; 4400 ktime_t start = ktime_get(); 4401 int ret; 4402 4403 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4404 4405 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4406 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4407 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4408 4409 if (ret) 4410 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4411 __func__, ret); 4412 else 4413 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4414 POST_CHANGE); 4415 4416 return ret; 4417 } 4418 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4419 4420 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4421 { 4422 struct uic_command uic_cmd = { 4423 .command = UIC_CMD_DME_HIBER_EXIT, 4424 }; 4425 int ret; 4426 ktime_t start = ktime_get(); 4427 4428 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4429 4430 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4431 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4432 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4433 4434 if (ret) { 4435 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4436 __func__, ret); 4437 } else { 4438 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4439 POST_CHANGE); 4440 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4441 hba->ufs_stats.hibern8_exit_cnt++; 4442 } 4443 4444 return ret; 4445 } 4446 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4447 4448 static void ufshcd_configure_auto_hibern8(struct ufs_hba *hba) 4449 { 4450 if (!ufshcd_is_auto_hibern8_supported(hba)) 4451 return; 4452 4453 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4454 } 4455 4456 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4457 { 4458 const u32 cur_ahit = READ_ONCE(hba->ahit); 4459 4460 if (!ufshcd_is_auto_hibern8_supported(hba) || cur_ahit == ahit) 4461 return; 4462 4463 WRITE_ONCE(hba->ahit, ahit); 4464 if (!pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4465 ufshcd_rpm_get_sync(hba); 4466 ufshcd_hold(hba); 4467 ufshcd_configure_auto_hibern8(hba); 4468 ufshcd_release(hba); 4469 ufshcd_rpm_put_sync(hba); 4470 } 4471 } 4472 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4473 4474 /** 4475 * ufshcd_init_pwr_info - setting the POR (power on reset) 4476 * values in hba power info 4477 * @hba: per-adapter instance 4478 */ 4479 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4480 { 4481 hba->pwr_info.gear_rx = UFS_PWM_G1; 4482 hba->pwr_info.gear_tx = UFS_PWM_G1; 4483 hba->pwr_info.lane_rx = UFS_LANE_1; 4484 hba->pwr_info.lane_tx = UFS_LANE_1; 4485 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4486 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4487 hba->pwr_info.hs_rate = 0; 4488 } 4489 4490 /** 4491 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4492 * @hba: per-adapter instance 4493 * 4494 * Return: 0 upon success; < 0 upon failure. 4495 */ 4496 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4497 { 4498 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4499 4500 if (hba->max_pwr_info.is_valid) 4501 return 0; 4502 4503 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4504 pwr_info->pwr_tx = FASTAUTO_MODE; 4505 pwr_info->pwr_rx = FASTAUTO_MODE; 4506 } else { 4507 pwr_info->pwr_tx = FAST_MODE; 4508 pwr_info->pwr_rx = FAST_MODE; 4509 } 4510 pwr_info->hs_rate = PA_HS_MODE_B; 4511 4512 /* Get the connected lane count */ 4513 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4514 &pwr_info->lane_rx); 4515 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4516 &pwr_info->lane_tx); 4517 4518 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4519 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4520 __func__, 4521 pwr_info->lane_rx, 4522 pwr_info->lane_tx); 4523 return -EINVAL; 4524 } 4525 4526 /* 4527 * First, get the maximum gears of HS speed. 4528 * If a zero value, it means there is no HSGEAR capability. 4529 * Then, get the maximum gears of PWM speed. 4530 */ 4531 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4532 if (!pwr_info->gear_rx) { 4533 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4534 &pwr_info->gear_rx); 4535 if (!pwr_info->gear_rx) { 4536 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4537 __func__, pwr_info->gear_rx); 4538 return -EINVAL; 4539 } 4540 pwr_info->pwr_rx = SLOW_MODE; 4541 } 4542 4543 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4544 &pwr_info->gear_tx); 4545 if (!pwr_info->gear_tx) { 4546 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4547 &pwr_info->gear_tx); 4548 if (!pwr_info->gear_tx) { 4549 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4550 __func__, pwr_info->gear_tx); 4551 return -EINVAL; 4552 } 4553 pwr_info->pwr_tx = SLOW_MODE; 4554 } 4555 4556 hba->max_pwr_info.is_valid = true; 4557 return 0; 4558 } 4559 4560 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4561 struct ufs_pa_layer_attr *pwr_mode) 4562 { 4563 int ret; 4564 4565 /* if already configured to the requested pwr_mode */ 4566 if (!hba->force_pmc && 4567 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4568 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4569 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4570 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4571 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4572 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4573 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4574 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4575 return 0; 4576 } 4577 4578 /* 4579 * Configure attributes for power mode change with below. 4580 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4581 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4582 * - PA_HSSERIES 4583 */ 4584 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4585 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4586 pwr_mode->lane_rx); 4587 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4588 pwr_mode->pwr_rx == FAST_MODE) 4589 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4590 else 4591 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4592 4593 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4594 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4595 pwr_mode->lane_tx); 4596 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4597 pwr_mode->pwr_tx == FAST_MODE) 4598 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4599 else 4600 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4601 4602 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4603 pwr_mode->pwr_tx == FASTAUTO_MODE || 4604 pwr_mode->pwr_rx == FAST_MODE || 4605 pwr_mode->pwr_tx == FAST_MODE) 4606 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4607 pwr_mode->hs_rate); 4608 4609 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4610 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4611 DL_FC0ProtectionTimeOutVal_Default); 4612 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4613 DL_TC0ReplayTimeOutVal_Default); 4614 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4615 DL_AFC0ReqTimeOutVal_Default); 4616 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4617 DL_FC1ProtectionTimeOutVal_Default); 4618 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4619 DL_TC1ReplayTimeOutVal_Default); 4620 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4621 DL_AFC1ReqTimeOutVal_Default); 4622 4623 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4624 DL_FC0ProtectionTimeOutVal_Default); 4625 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4626 DL_TC0ReplayTimeOutVal_Default); 4627 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4628 DL_AFC0ReqTimeOutVal_Default); 4629 } 4630 4631 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4632 | pwr_mode->pwr_tx); 4633 4634 if (ret) { 4635 dev_err(hba->dev, 4636 "%s: power mode change failed %d\n", __func__, ret); 4637 } else { 4638 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4639 pwr_mode); 4640 4641 memcpy(&hba->pwr_info, pwr_mode, 4642 sizeof(struct ufs_pa_layer_attr)); 4643 } 4644 4645 return ret; 4646 } 4647 4648 /** 4649 * ufshcd_config_pwr_mode - configure a new power mode 4650 * @hba: per-adapter instance 4651 * @desired_pwr_mode: desired power configuration 4652 * 4653 * Return: 0 upon success; < 0 upon failure. 4654 */ 4655 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4656 struct ufs_pa_layer_attr *desired_pwr_mode) 4657 { 4658 struct ufs_pa_layer_attr final_params = { 0 }; 4659 int ret; 4660 4661 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4662 desired_pwr_mode, &final_params); 4663 4664 if (ret) 4665 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4666 4667 ret = ufshcd_change_power_mode(hba, &final_params); 4668 4669 return ret; 4670 } 4671 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4672 4673 /** 4674 * ufshcd_complete_dev_init() - checks device readiness 4675 * @hba: per-adapter instance 4676 * 4677 * Set fDeviceInit flag and poll until device toggles it. 4678 * 4679 * Return: 0 upon success; < 0 upon failure. 4680 */ 4681 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4682 { 4683 int err; 4684 bool flag_res = true; 4685 ktime_t timeout; 4686 4687 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4688 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4689 if (err) { 4690 dev_err(hba->dev, 4691 "%s: setting fDeviceInit flag failed with error %d\n", 4692 __func__, err); 4693 goto out; 4694 } 4695 4696 /* Poll fDeviceInit flag to be cleared */ 4697 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4698 do { 4699 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4700 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4701 if (!flag_res) 4702 break; 4703 usleep_range(500, 1000); 4704 } while (ktime_before(ktime_get(), timeout)); 4705 4706 if (err) { 4707 dev_err(hba->dev, 4708 "%s: reading fDeviceInit flag failed with error %d\n", 4709 __func__, err); 4710 } else if (flag_res) { 4711 dev_err(hba->dev, 4712 "%s: fDeviceInit was not cleared by the device\n", 4713 __func__); 4714 err = -EBUSY; 4715 } 4716 out: 4717 return err; 4718 } 4719 4720 /** 4721 * ufshcd_make_hba_operational - Make UFS controller operational 4722 * @hba: per adapter instance 4723 * 4724 * To bring UFS host controller to operational state, 4725 * 1. Enable required interrupts 4726 * 2. Configure interrupt aggregation 4727 * 3. Program UTRL and UTMRL base address 4728 * 4. Configure run-stop-registers 4729 * 4730 * Return: 0 on success, non-zero value on failure. 4731 */ 4732 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4733 { 4734 int err = 0; 4735 u32 reg; 4736 4737 /* Enable required interrupts */ 4738 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4739 4740 /* Configure interrupt aggregation */ 4741 if (ufshcd_is_intr_aggr_allowed(hba)) 4742 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4743 else 4744 ufshcd_disable_intr_aggr(hba); 4745 4746 /* Configure UTRL and UTMRL base address registers */ 4747 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4748 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4749 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4750 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4751 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4752 REG_UTP_TASK_REQ_LIST_BASE_L); 4753 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4754 REG_UTP_TASK_REQ_LIST_BASE_H); 4755 4756 /* 4757 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4758 */ 4759 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4760 if (!(ufshcd_get_lists_status(reg))) { 4761 ufshcd_enable_run_stop_reg(hba); 4762 } else { 4763 dev_err(hba->dev, 4764 "Host controller not ready to process requests"); 4765 err = -EIO; 4766 } 4767 4768 return err; 4769 } 4770 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4771 4772 /** 4773 * ufshcd_hba_stop - Send controller to reset state 4774 * @hba: per adapter instance 4775 */ 4776 void ufshcd_hba_stop(struct ufs_hba *hba) 4777 { 4778 unsigned long flags; 4779 int err; 4780 4781 /* 4782 * Obtain the host lock to prevent that the controller is disabled 4783 * while the UFS interrupt handler is active on another CPU. 4784 */ 4785 spin_lock_irqsave(hba->host->host_lock, flags); 4786 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4787 spin_unlock_irqrestore(hba->host->host_lock, flags); 4788 4789 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4790 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4791 10, 1); 4792 if (err) 4793 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4794 } 4795 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4796 4797 /** 4798 * ufshcd_hba_execute_hce - initialize the controller 4799 * @hba: per adapter instance 4800 * 4801 * The controller resets itself and controller firmware initialization 4802 * sequence kicks off. When controller is ready it will set 4803 * the Host Controller Enable bit to 1. 4804 * 4805 * Return: 0 on success, non-zero value on failure. 4806 */ 4807 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4808 { 4809 int retry_outer = 3; 4810 int retry_inner; 4811 4812 start: 4813 if (ufshcd_is_hba_active(hba)) 4814 /* change controller state to "reset state" */ 4815 ufshcd_hba_stop(hba); 4816 4817 /* UniPro link is disabled at this point */ 4818 ufshcd_set_link_off(hba); 4819 4820 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4821 4822 /* start controller initialization sequence */ 4823 ufshcd_hba_start(hba); 4824 4825 /* 4826 * To initialize a UFS host controller HCE bit must be set to 1. 4827 * During initialization the HCE bit value changes from 1->0->1. 4828 * When the host controller completes initialization sequence 4829 * it sets the value of HCE bit to 1. The same HCE bit is read back 4830 * to check if the controller has completed initialization sequence. 4831 * So without this delay the value HCE = 1, set in the previous 4832 * instruction might be read back. 4833 * This delay can be changed based on the controller. 4834 */ 4835 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4836 4837 /* wait for the host controller to complete initialization */ 4838 retry_inner = 50; 4839 while (!ufshcd_is_hba_active(hba)) { 4840 if (retry_inner) { 4841 retry_inner--; 4842 } else { 4843 dev_err(hba->dev, 4844 "Controller enable failed\n"); 4845 if (retry_outer) { 4846 retry_outer--; 4847 goto start; 4848 } 4849 return -EIO; 4850 } 4851 usleep_range(1000, 1100); 4852 } 4853 4854 /* enable UIC related interrupts */ 4855 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4856 4857 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4858 4859 return 0; 4860 } 4861 4862 int ufshcd_hba_enable(struct ufs_hba *hba) 4863 { 4864 int ret; 4865 4866 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4867 ufshcd_set_link_off(hba); 4868 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4869 4870 /* enable UIC related interrupts */ 4871 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4872 ret = ufshcd_dme_reset(hba); 4873 if (ret) { 4874 dev_err(hba->dev, "DME_RESET failed\n"); 4875 return ret; 4876 } 4877 4878 ret = ufshcd_dme_enable(hba); 4879 if (ret) { 4880 dev_err(hba->dev, "Enabling DME failed\n"); 4881 return ret; 4882 } 4883 4884 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4885 } else { 4886 ret = ufshcd_hba_execute_hce(hba); 4887 } 4888 4889 return ret; 4890 } 4891 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4892 4893 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4894 { 4895 int tx_lanes = 0, i, err = 0; 4896 4897 if (!peer) 4898 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4899 &tx_lanes); 4900 else 4901 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4902 &tx_lanes); 4903 for (i = 0; i < tx_lanes; i++) { 4904 if (!peer) 4905 err = ufshcd_dme_set(hba, 4906 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4907 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4908 0); 4909 else 4910 err = ufshcd_dme_peer_set(hba, 4911 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4912 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4913 0); 4914 if (err) { 4915 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4916 __func__, peer, i, err); 4917 break; 4918 } 4919 } 4920 4921 return err; 4922 } 4923 4924 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4925 { 4926 return ufshcd_disable_tx_lcc(hba, true); 4927 } 4928 4929 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4930 { 4931 struct ufs_event_hist *e; 4932 4933 if (id >= UFS_EVT_CNT) 4934 return; 4935 4936 e = &hba->ufs_stats.event[id]; 4937 e->val[e->pos] = val; 4938 e->tstamp[e->pos] = local_clock(); 4939 e->cnt += 1; 4940 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4941 4942 ufshcd_vops_event_notify(hba, id, &val); 4943 } 4944 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4945 4946 /** 4947 * ufshcd_link_startup - Initialize unipro link startup 4948 * @hba: per adapter instance 4949 * 4950 * Return: 0 for success, non-zero in case of failure. 4951 */ 4952 static int ufshcd_link_startup(struct ufs_hba *hba) 4953 { 4954 int ret; 4955 int retries = DME_LINKSTARTUP_RETRIES; 4956 bool link_startup_again = false; 4957 4958 /* 4959 * If UFS device isn't active then we will have to issue link startup 4960 * 2 times to make sure the device state move to active. 4961 */ 4962 if (!ufshcd_is_ufs_dev_active(hba)) 4963 link_startup_again = true; 4964 4965 link_startup: 4966 do { 4967 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4968 4969 ret = ufshcd_dme_link_startup(hba); 4970 4971 /* check if device is detected by inter-connect layer */ 4972 if (!ret && !ufshcd_is_device_present(hba)) { 4973 ufshcd_update_evt_hist(hba, 4974 UFS_EVT_LINK_STARTUP_FAIL, 4975 0); 4976 dev_err(hba->dev, "%s: Device not present\n", __func__); 4977 ret = -ENXIO; 4978 goto out; 4979 } 4980 4981 /* 4982 * DME link lost indication is only received when link is up, 4983 * but we can't be sure if the link is up until link startup 4984 * succeeds. So reset the local Uni-Pro and try again. 4985 */ 4986 if (ret && retries && ufshcd_hba_enable(hba)) { 4987 ufshcd_update_evt_hist(hba, 4988 UFS_EVT_LINK_STARTUP_FAIL, 4989 (u32)ret); 4990 goto out; 4991 } 4992 } while (ret && retries--); 4993 4994 if (ret) { 4995 /* failed to get the link up... retire */ 4996 ufshcd_update_evt_hist(hba, 4997 UFS_EVT_LINK_STARTUP_FAIL, 4998 (u32)ret); 4999 goto out; 5000 } 5001 5002 if (link_startup_again) { 5003 link_startup_again = false; 5004 retries = DME_LINKSTARTUP_RETRIES; 5005 goto link_startup; 5006 } 5007 5008 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 5009 ufshcd_init_pwr_info(hba); 5010 ufshcd_print_pwr_info(hba); 5011 5012 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 5013 ret = ufshcd_disable_device_tx_lcc(hba); 5014 if (ret) 5015 goto out; 5016 } 5017 5018 /* Include any host controller configuration via UIC commands */ 5019 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 5020 if (ret) 5021 goto out; 5022 5023 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 5024 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 5025 ret = ufshcd_make_hba_operational(hba); 5026 out: 5027 if (ret) { 5028 dev_err(hba->dev, "link startup failed %d\n", ret); 5029 ufshcd_print_host_state(hba); 5030 ufshcd_print_pwr_info(hba); 5031 ufshcd_print_evt_hist(hba); 5032 } 5033 return ret; 5034 } 5035 5036 /** 5037 * ufshcd_verify_dev_init() - Verify device initialization 5038 * @hba: per-adapter instance 5039 * 5040 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 5041 * device Transport Protocol (UTP) layer is ready after a reset. 5042 * If the UTP layer at the device side is not initialized, it may 5043 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 5044 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 5045 * 5046 * Return: 0 upon success; < 0 upon failure. 5047 */ 5048 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 5049 { 5050 int err = 0; 5051 int retries; 5052 5053 ufshcd_dev_man_lock(hba); 5054 5055 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 5056 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 5057 hba->nop_out_timeout); 5058 5059 if (!err || err == -ETIMEDOUT) 5060 break; 5061 5062 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 5063 } 5064 5065 ufshcd_dev_man_unlock(hba); 5066 5067 if (err) 5068 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 5069 return err; 5070 } 5071 5072 /** 5073 * ufshcd_setup_links - associate link b/w device wlun and other luns 5074 * @sdev: pointer to SCSI device 5075 * @hba: pointer to ufs hba 5076 */ 5077 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 5078 { 5079 struct device_link *link; 5080 5081 /* 5082 * Device wlun is the supplier & rest of the luns are consumers. 5083 * This ensures that device wlun suspends after all other luns. 5084 */ 5085 if (hba->ufs_device_wlun) { 5086 link = device_link_add(&sdev->sdev_gendev, 5087 &hba->ufs_device_wlun->sdev_gendev, 5088 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 5089 if (!link) { 5090 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 5091 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 5092 return; 5093 } 5094 hba->luns_avail--; 5095 /* Ignore REPORT_LUN wlun probing */ 5096 if (hba->luns_avail == 1) { 5097 ufshcd_rpm_put(hba); 5098 return; 5099 } 5100 } else { 5101 /* 5102 * Device wlun is probed. The assumption is that WLUNs are 5103 * scanned before other LUNs. 5104 */ 5105 hba->luns_avail--; 5106 } 5107 } 5108 5109 /** 5110 * ufshcd_lu_init - Initialize the relevant parameters of the LU 5111 * @hba: per-adapter instance 5112 * @sdev: pointer to SCSI device 5113 */ 5114 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 5115 { 5116 int len = QUERY_DESC_MAX_SIZE; 5117 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 5118 u8 lun_qdepth = hba->nutrs; 5119 u8 *desc_buf; 5120 int ret; 5121 5122 desc_buf = kzalloc(len, GFP_KERNEL); 5123 if (!desc_buf) 5124 goto set_qdepth; 5125 5126 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5127 if (ret < 0) { 5128 if (ret == -EOPNOTSUPP) 5129 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5130 lun_qdepth = 1; 5131 kfree(desc_buf); 5132 goto set_qdepth; 5133 } 5134 5135 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5136 /* 5137 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5138 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5139 */ 5140 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5141 } 5142 /* 5143 * According to UFS device specification, the write protection mode is only supported by 5144 * normal LU, not supported by WLUN. 5145 */ 5146 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5147 !hba->dev_info.is_lu_power_on_wp && 5148 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5149 hba->dev_info.is_lu_power_on_wp = true; 5150 5151 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5152 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5153 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5154 hba->dev_info.b_advanced_rpmb_en = true; 5155 5156 5157 kfree(desc_buf); 5158 set_qdepth: 5159 /* 5160 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5161 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5162 */ 5163 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5164 scsi_change_queue_depth(sdev, lun_qdepth); 5165 } 5166 5167 /** 5168 * ufshcd_slave_alloc - handle initial SCSI device configurations 5169 * @sdev: pointer to SCSI device 5170 * 5171 * Return: success. 5172 */ 5173 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5174 { 5175 struct ufs_hba *hba; 5176 5177 hba = shost_priv(sdev->host); 5178 5179 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5180 sdev->use_10_for_ms = 1; 5181 5182 /* DBD field should be set to 1 in mode sense(10) */ 5183 sdev->set_dbd_for_ms = 1; 5184 5185 /* allow SCSI layer to restart the device in case of errors */ 5186 sdev->allow_restart = 1; 5187 5188 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5189 sdev->no_report_opcodes = 1; 5190 5191 /* WRITE_SAME command is not supported */ 5192 sdev->no_write_same = 1; 5193 5194 ufshcd_lu_init(hba, sdev); 5195 5196 ufshcd_setup_links(hba, sdev); 5197 5198 return 0; 5199 } 5200 5201 /** 5202 * ufshcd_change_queue_depth - change queue depth 5203 * @sdev: pointer to SCSI device 5204 * @depth: required depth to set 5205 * 5206 * Change queue depth and make sure the max. limits are not crossed. 5207 * 5208 * Return: new queue depth. 5209 */ 5210 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5211 { 5212 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5213 } 5214 5215 /** 5216 * ufshcd_device_configure - adjust SCSI device configurations 5217 * @sdev: pointer to SCSI device 5218 * @lim: queue limits 5219 * 5220 * Return: 0 (success). 5221 */ 5222 static int ufshcd_device_configure(struct scsi_device *sdev, 5223 struct queue_limits *lim) 5224 { 5225 struct ufs_hba *hba = shost_priv(sdev->host); 5226 struct request_queue *q = sdev->request_queue; 5227 5228 lim->dma_pad_mask = PRDT_DATA_BYTE_COUNT_PAD - 1; 5229 5230 /* 5231 * Block runtime-pm until all consumers are added. 5232 * Refer ufshcd_setup_links(). 5233 */ 5234 if (is_device_wlun(sdev)) 5235 pm_runtime_get_noresume(&sdev->sdev_gendev); 5236 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5237 sdev->rpm_autosuspend = 1; 5238 /* 5239 * Do not print messages during runtime PM to avoid never-ending cycles 5240 * of messages written back to storage by user space causing runtime 5241 * resume, causing more messages and so on. 5242 */ 5243 sdev->silence_suspend = 1; 5244 5245 ufshcd_crypto_register(hba, q); 5246 5247 return 0; 5248 } 5249 5250 /** 5251 * ufshcd_slave_destroy - remove SCSI device configurations 5252 * @sdev: pointer to SCSI device 5253 */ 5254 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5255 { 5256 struct ufs_hba *hba; 5257 unsigned long flags; 5258 5259 hba = shost_priv(sdev->host); 5260 5261 /* Drop the reference as it won't be needed anymore */ 5262 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5263 spin_lock_irqsave(hba->host->host_lock, flags); 5264 hba->ufs_device_wlun = NULL; 5265 spin_unlock_irqrestore(hba->host->host_lock, flags); 5266 } else if (hba->ufs_device_wlun) { 5267 struct device *supplier = NULL; 5268 5269 /* Ensure UFS Device WLUN exists and does not disappear */ 5270 spin_lock_irqsave(hba->host->host_lock, flags); 5271 if (hba->ufs_device_wlun) { 5272 supplier = &hba->ufs_device_wlun->sdev_gendev; 5273 get_device(supplier); 5274 } 5275 spin_unlock_irqrestore(hba->host->host_lock, flags); 5276 5277 if (supplier) { 5278 /* 5279 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5280 * device will not have been registered but can still 5281 * have a device link holding a reference to the device. 5282 */ 5283 device_link_remove(&sdev->sdev_gendev, supplier); 5284 put_device(supplier); 5285 } 5286 } 5287 } 5288 5289 /** 5290 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5291 * @lrbp: pointer to local reference block of completed command 5292 * @scsi_status: SCSI command status 5293 * 5294 * Return: value base on SCSI command status. 5295 */ 5296 static inline int 5297 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5298 { 5299 int result = 0; 5300 5301 switch (scsi_status) { 5302 case SAM_STAT_CHECK_CONDITION: 5303 ufshcd_copy_sense_data(lrbp); 5304 fallthrough; 5305 case SAM_STAT_GOOD: 5306 result |= DID_OK << 16 | scsi_status; 5307 break; 5308 case SAM_STAT_TASK_SET_FULL: 5309 case SAM_STAT_BUSY: 5310 case SAM_STAT_TASK_ABORTED: 5311 ufshcd_copy_sense_data(lrbp); 5312 result |= scsi_status; 5313 break; 5314 default: 5315 result |= DID_ERROR << 16; 5316 break; 5317 } /* end of switch */ 5318 5319 return result; 5320 } 5321 5322 /** 5323 * ufshcd_transfer_rsp_status - Get overall status of the response 5324 * @hba: per adapter instance 5325 * @lrbp: pointer to local reference block of completed command 5326 * @cqe: pointer to the completion queue entry 5327 * 5328 * Return: result of the command to notify SCSI midlayer. 5329 */ 5330 static inline int 5331 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5332 struct cq_entry *cqe) 5333 { 5334 int result = 0; 5335 int scsi_status; 5336 enum utp_ocs ocs; 5337 u8 upiu_flags; 5338 u32 resid; 5339 5340 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5341 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5342 /* 5343 * Test !overflow instead of underflow to support UFS devices that do 5344 * not set either flag. 5345 */ 5346 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5347 scsi_set_resid(lrbp->cmd, resid); 5348 5349 /* overall command status of utrd */ 5350 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5351 5352 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5353 if (lrbp->ucd_rsp_ptr->header.response || 5354 lrbp->ucd_rsp_ptr->header.status) 5355 ocs = OCS_SUCCESS; 5356 } 5357 5358 switch (ocs) { 5359 case OCS_SUCCESS: 5360 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5361 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5362 case UPIU_TRANSACTION_RESPONSE: 5363 /* 5364 * get the result based on SCSI status response 5365 * to notify the SCSI midlayer of the command status 5366 */ 5367 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5368 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5369 5370 /* 5371 * Currently we are only supporting BKOPs exception 5372 * events hence we can ignore BKOPs exception event 5373 * during power management callbacks. BKOPs exception 5374 * event is not expected to be raised in runtime suspend 5375 * callback as it allows the urgent bkops. 5376 * During system suspend, we are anyway forcefully 5377 * disabling the bkops and if urgent bkops is needed 5378 * it will be enabled on system resume. Long term 5379 * solution could be to abort the system suspend if 5380 * UFS device needs urgent BKOPs. 5381 */ 5382 if (!hba->pm_op_in_progress && 5383 !ufshcd_eh_in_progress(hba) && 5384 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5385 /* Flushed in suspend */ 5386 schedule_work(&hba->eeh_work); 5387 break; 5388 case UPIU_TRANSACTION_REJECT_UPIU: 5389 /* TODO: handle Reject UPIU Response */ 5390 result = DID_ERROR << 16; 5391 dev_err(hba->dev, 5392 "Reject UPIU not fully implemented\n"); 5393 break; 5394 default: 5395 dev_err(hba->dev, 5396 "Unexpected request response code = %x\n", 5397 result); 5398 result = DID_ERROR << 16; 5399 break; 5400 } 5401 break; 5402 case OCS_ABORTED: 5403 result |= DID_ABORT << 16; 5404 break; 5405 case OCS_INVALID_COMMAND_STATUS: 5406 result |= DID_REQUEUE << 16; 5407 break; 5408 case OCS_INVALID_CMD_TABLE_ATTR: 5409 case OCS_INVALID_PRDT_ATTR: 5410 case OCS_MISMATCH_DATA_BUF_SIZE: 5411 case OCS_MISMATCH_RESP_UPIU_SIZE: 5412 case OCS_PEER_COMM_FAILURE: 5413 case OCS_FATAL_ERROR: 5414 case OCS_DEVICE_FATAL_ERROR: 5415 case OCS_INVALID_CRYPTO_CONFIG: 5416 case OCS_GENERAL_CRYPTO_ERROR: 5417 default: 5418 result |= DID_ERROR << 16; 5419 dev_err(hba->dev, 5420 "OCS error from controller = %x for tag %d\n", 5421 ocs, lrbp->task_tag); 5422 ufshcd_print_evt_hist(hba); 5423 ufshcd_print_host_state(hba); 5424 break; 5425 } /* end of switch */ 5426 5427 if ((host_byte(result) != DID_OK) && 5428 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5429 ufshcd_print_tr(hba, lrbp->task_tag, true); 5430 return result; 5431 } 5432 5433 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5434 u32 intr_mask) 5435 { 5436 if (!ufshcd_is_auto_hibern8_supported(hba) || 5437 !ufshcd_is_auto_hibern8_enabled(hba)) 5438 return false; 5439 5440 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5441 return false; 5442 5443 if (hba->active_uic_cmd && 5444 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5445 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5446 return false; 5447 5448 return true; 5449 } 5450 5451 /** 5452 * ufshcd_uic_cmd_compl - handle completion of uic command 5453 * @hba: per adapter instance 5454 * @intr_status: interrupt status generated by the controller 5455 * 5456 * Return: 5457 * IRQ_HANDLED - If interrupt is valid 5458 * IRQ_NONE - If invalid interrupt 5459 */ 5460 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5461 { 5462 irqreturn_t retval = IRQ_NONE; 5463 5464 spin_lock(hba->host->host_lock); 5465 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5466 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5467 5468 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { 5469 hba->active_uic_cmd->argument2 |= 5470 ufshcd_get_uic_cmd_result(hba); 5471 hba->active_uic_cmd->argument3 = 5472 ufshcd_get_dme_attr_val(hba); 5473 if (!hba->uic_async_done) 5474 hba->active_uic_cmd->cmd_active = 0; 5475 complete(&hba->active_uic_cmd->done); 5476 retval = IRQ_HANDLED; 5477 } 5478 5479 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { 5480 hba->active_uic_cmd->cmd_active = 0; 5481 complete(hba->uic_async_done); 5482 retval = IRQ_HANDLED; 5483 } 5484 5485 if (retval == IRQ_HANDLED) 5486 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd, 5487 UFS_CMD_COMP); 5488 spin_unlock(hba->host->host_lock); 5489 return retval; 5490 } 5491 5492 /* Release the resources allocated for processing a SCSI command. */ 5493 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5494 struct ufshcd_lrb *lrbp) 5495 { 5496 struct scsi_cmnd *cmd = lrbp->cmd; 5497 5498 scsi_dma_unmap(cmd); 5499 ufshcd_crypto_clear_prdt(hba, lrbp); 5500 ufshcd_release(hba); 5501 ufshcd_clk_scaling_update_busy(hba); 5502 } 5503 5504 /** 5505 * ufshcd_compl_one_cqe - handle a completion queue entry 5506 * @hba: per adapter instance 5507 * @task_tag: the task tag of the request to be completed 5508 * @cqe: pointer to the completion queue entry 5509 */ 5510 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5511 struct cq_entry *cqe) 5512 { 5513 struct ufshcd_lrb *lrbp; 5514 struct scsi_cmnd *cmd; 5515 enum utp_ocs ocs; 5516 5517 lrbp = &hba->lrb[task_tag]; 5518 lrbp->compl_time_stamp = ktime_get(); 5519 cmd = lrbp->cmd; 5520 if (cmd) { 5521 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5522 ufshcd_update_monitor(hba, lrbp); 5523 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5524 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5525 ufshcd_release_scsi_cmd(hba, lrbp); 5526 /* Do not touch lrbp after scsi done */ 5527 scsi_done(cmd); 5528 } else if (hba->dev_cmd.complete) { 5529 if (cqe) { 5530 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5531 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5532 } 5533 complete(hba->dev_cmd.complete); 5534 } 5535 } 5536 5537 /** 5538 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5539 * @hba: per adapter instance 5540 * @completed_reqs: bitmask that indicates which requests to complete 5541 */ 5542 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5543 unsigned long completed_reqs) 5544 { 5545 int tag; 5546 5547 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5548 ufshcd_compl_one_cqe(hba, tag, NULL); 5549 } 5550 5551 /* Any value that is not an existing queue number is fine for this constant. */ 5552 enum { 5553 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5554 }; 5555 5556 static void ufshcd_clear_polled(struct ufs_hba *hba, 5557 unsigned long *completed_reqs) 5558 { 5559 int tag; 5560 5561 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5562 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5563 5564 if (!cmd) 5565 continue; 5566 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5567 __clear_bit(tag, completed_reqs); 5568 } 5569 } 5570 5571 /* 5572 * Return: > 0 if one or more commands have been completed or 0 if no 5573 * requests have been completed. 5574 */ 5575 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5576 { 5577 struct ufs_hba *hba = shost_priv(shost); 5578 unsigned long completed_reqs, flags; 5579 u32 tr_doorbell; 5580 struct ufs_hw_queue *hwq; 5581 5582 if (hba->mcq_enabled) { 5583 hwq = &hba->uhq[queue_num]; 5584 5585 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5586 } 5587 5588 spin_lock_irqsave(&hba->outstanding_lock, flags); 5589 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5590 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5591 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5592 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5593 hba->outstanding_reqs); 5594 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5595 /* Do not complete polled requests from interrupt context. */ 5596 ufshcd_clear_polled(hba, &completed_reqs); 5597 } 5598 hba->outstanding_reqs &= ~completed_reqs; 5599 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5600 5601 if (completed_reqs) 5602 __ufshcd_transfer_req_compl(hba, completed_reqs); 5603 5604 return completed_reqs != 0; 5605 } 5606 5607 /** 5608 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5609 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5610 * to complete the pending transfers and free the resources associated with 5611 * the scsi command. 5612 * 5613 * @hba: per adapter instance 5614 * @force_compl: This flag is set to true when invoked 5615 * from ufshcd_host_reset_and_restore() in which case it requires special 5616 * handling because the host controller has been reset by ufshcd_hba_stop(). 5617 */ 5618 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5619 bool force_compl) 5620 { 5621 struct ufs_hw_queue *hwq; 5622 struct ufshcd_lrb *lrbp; 5623 struct scsi_cmnd *cmd; 5624 unsigned long flags; 5625 int tag; 5626 5627 for (tag = 0; tag < hba->nutrs; tag++) { 5628 lrbp = &hba->lrb[tag]; 5629 cmd = lrbp->cmd; 5630 if (!ufshcd_cmd_inflight(cmd) || 5631 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5632 continue; 5633 5634 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 5635 5636 if (force_compl) { 5637 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5638 /* 5639 * For those cmds of which the cqes are not present 5640 * in the cq, complete them explicitly. 5641 */ 5642 spin_lock_irqsave(&hwq->cq_lock, flags); 5643 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5644 set_host_byte(cmd, DID_REQUEUE); 5645 ufshcd_release_scsi_cmd(hba, lrbp); 5646 scsi_done(cmd); 5647 } 5648 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5649 } else { 5650 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5651 } 5652 } 5653 } 5654 5655 /** 5656 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5657 * @hba: per adapter instance 5658 * 5659 * Return: 5660 * IRQ_HANDLED - If interrupt is valid 5661 * IRQ_NONE - If invalid interrupt 5662 */ 5663 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5664 { 5665 /* Resetting interrupt aggregation counters first and reading the 5666 * DOOR_BELL afterward allows us to handle all the completed requests. 5667 * In order to prevent other interrupts starvation the DB is read once 5668 * after reset. The down side of this solution is the possibility of 5669 * false interrupt if device completes another request after resetting 5670 * aggregation and before reading the DB. 5671 */ 5672 if (ufshcd_is_intr_aggr_allowed(hba) && 5673 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5674 ufshcd_reset_intr_aggr(hba); 5675 5676 if (ufs_fail_completion(hba)) 5677 return IRQ_HANDLED; 5678 5679 /* 5680 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5681 * do not want polling to trigger spurious interrupt complaints. 5682 */ 5683 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5684 5685 return IRQ_HANDLED; 5686 } 5687 5688 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5689 { 5690 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5691 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5692 &ee_ctrl_mask); 5693 } 5694 5695 int ufshcd_write_ee_control(struct ufs_hba *hba) 5696 { 5697 int err; 5698 5699 mutex_lock(&hba->ee_ctrl_mutex); 5700 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5701 mutex_unlock(&hba->ee_ctrl_mutex); 5702 if (err) 5703 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5704 __func__, err); 5705 return err; 5706 } 5707 5708 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5709 const u16 *other_mask, u16 set, u16 clr) 5710 { 5711 u16 new_mask, ee_ctrl_mask; 5712 int err = 0; 5713 5714 mutex_lock(&hba->ee_ctrl_mutex); 5715 new_mask = (*mask & ~clr) | set; 5716 ee_ctrl_mask = new_mask | *other_mask; 5717 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5718 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5719 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5720 if (!err) { 5721 hba->ee_ctrl_mask = ee_ctrl_mask; 5722 *mask = new_mask; 5723 } 5724 mutex_unlock(&hba->ee_ctrl_mutex); 5725 return err; 5726 } 5727 5728 /** 5729 * ufshcd_disable_ee - disable exception event 5730 * @hba: per-adapter instance 5731 * @mask: exception event to disable 5732 * 5733 * Disables exception event in the device so that the EVENT_ALERT 5734 * bit is not set. 5735 * 5736 * Return: zero on success, non-zero error value on failure. 5737 */ 5738 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5739 { 5740 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5741 } 5742 5743 /** 5744 * ufshcd_enable_ee - enable exception event 5745 * @hba: per-adapter instance 5746 * @mask: exception event to enable 5747 * 5748 * Enable corresponding exception event in the device to allow 5749 * device to alert host in critical scenarios. 5750 * 5751 * Return: zero on success, non-zero error value on failure. 5752 */ 5753 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5754 { 5755 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5756 } 5757 5758 /** 5759 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5760 * @hba: per-adapter instance 5761 * 5762 * Allow device to manage background operations on its own. Enabling 5763 * this might lead to inconsistent latencies during normal data transfers 5764 * as the device is allowed to manage its own way of handling background 5765 * operations. 5766 * 5767 * Return: zero on success, non-zero on failure. 5768 */ 5769 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5770 { 5771 int err = 0; 5772 5773 if (hba->auto_bkops_enabled) 5774 goto out; 5775 5776 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5777 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5778 if (err) { 5779 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5780 __func__, err); 5781 goto out; 5782 } 5783 5784 hba->auto_bkops_enabled = true; 5785 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5786 5787 /* No need of URGENT_BKOPS exception from the device */ 5788 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5789 if (err) 5790 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5791 __func__, err); 5792 out: 5793 return err; 5794 } 5795 5796 /** 5797 * ufshcd_disable_auto_bkops - block device in doing background operations 5798 * @hba: per-adapter instance 5799 * 5800 * Disabling background operations improves command response latency but 5801 * has drawback of device moving into critical state where the device is 5802 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5803 * host is idle so that BKOPS are managed effectively without any negative 5804 * impacts. 5805 * 5806 * Return: zero on success, non-zero on failure. 5807 */ 5808 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5809 { 5810 int err = 0; 5811 5812 if (!hba->auto_bkops_enabled) 5813 goto out; 5814 5815 /* 5816 * If host assisted BKOPs is to be enabled, make sure 5817 * urgent bkops exception is allowed. 5818 */ 5819 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5820 if (err) { 5821 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5822 __func__, err); 5823 goto out; 5824 } 5825 5826 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5827 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5828 if (err) { 5829 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5830 __func__, err); 5831 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5832 goto out; 5833 } 5834 5835 hba->auto_bkops_enabled = false; 5836 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5837 hba->is_urgent_bkops_lvl_checked = false; 5838 out: 5839 return err; 5840 } 5841 5842 /** 5843 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5844 * @hba: per adapter instance 5845 * 5846 * After a device reset the device may toggle the BKOPS_EN flag 5847 * to default value. The s/w tracking variables should be updated 5848 * as well. This function would change the auto-bkops state based on 5849 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5850 */ 5851 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5852 { 5853 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5854 hba->auto_bkops_enabled = false; 5855 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5856 ufshcd_enable_auto_bkops(hba); 5857 } else { 5858 hba->auto_bkops_enabled = true; 5859 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5860 ufshcd_disable_auto_bkops(hba); 5861 } 5862 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5863 hba->is_urgent_bkops_lvl_checked = false; 5864 } 5865 5866 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5867 { 5868 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5869 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5870 } 5871 5872 /** 5873 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5874 * @hba: per-adapter instance 5875 * @status: bkops_status value 5876 * 5877 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5878 * flag in the device to permit background operations if the device 5879 * bkops_status is greater than or equal to "status" argument passed to 5880 * this function, disable otherwise. 5881 * 5882 * Return: 0 for success, non-zero in case of failure. 5883 * 5884 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5885 * to know whether auto bkops is enabled or disabled after this function 5886 * returns control to it. 5887 */ 5888 static int ufshcd_bkops_ctrl(struct ufs_hba *hba, 5889 enum bkops_status status) 5890 { 5891 int err; 5892 u32 curr_status = 0; 5893 5894 err = ufshcd_get_bkops_status(hba, &curr_status); 5895 if (err) { 5896 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5897 __func__, err); 5898 goto out; 5899 } else if (curr_status > BKOPS_STATUS_MAX) { 5900 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5901 __func__, curr_status); 5902 err = -EINVAL; 5903 goto out; 5904 } 5905 5906 if (curr_status >= status) 5907 err = ufshcd_enable_auto_bkops(hba); 5908 else 5909 err = ufshcd_disable_auto_bkops(hba); 5910 out: 5911 return err; 5912 } 5913 5914 /** 5915 * ufshcd_urgent_bkops - handle urgent bkops exception event 5916 * @hba: per-adapter instance 5917 * 5918 * Enable fBackgroundOpsEn flag in the device to permit background 5919 * operations. 5920 * 5921 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled 5922 * and negative error value for any other failure. 5923 * 5924 * Return: 0 upon success; < 0 upon failure. 5925 */ 5926 static int ufshcd_urgent_bkops(struct ufs_hba *hba) 5927 { 5928 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl); 5929 } 5930 5931 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5932 { 5933 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5934 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5935 } 5936 5937 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5938 { 5939 int err; 5940 u32 curr_status = 0; 5941 5942 if (hba->is_urgent_bkops_lvl_checked) 5943 goto enable_auto_bkops; 5944 5945 err = ufshcd_get_bkops_status(hba, &curr_status); 5946 if (err) { 5947 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5948 __func__, err); 5949 goto out; 5950 } 5951 5952 /* 5953 * We are seeing that some devices are raising the urgent bkops 5954 * exception events even when BKOPS status doesn't indicate performace 5955 * impacted or critical. Handle these device by determining their urgent 5956 * bkops status at runtime. 5957 */ 5958 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5959 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5960 __func__, curr_status); 5961 /* update the current status as the urgent bkops level */ 5962 hba->urgent_bkops_lvl = curr_status; 5963 hba->is_urgent_bkops_lvl_checked = true; 5964 } 5965 5966 enable_auto_bkops: 5967 err = ufshcd_enable_auto_bkops(hba); 5968 out: 5969 if (err < 0) 5970 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5971 __func__, err); 5972 } 5973 5974 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5975 { 5976 u32 value; 5977 5978 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5979 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 5980 return; 5981 5982 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 5983 5984 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 5985 5986 /* 5987 * A placeholder for the platform vendors to add whatever additional 5988 * steps required 5989 */ 5990 } 5991 5992 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 5993 { 5994 u8 index; 5995 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 5996 UPIU_QUERY_OPCODE_CLEAR_FLAG; 5997 5998 index = ufshcd_wb_get_query_index(hba); 5999 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 6000 } 6001 6002 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 6003 { 6004 int ret; 6005 6006 if (!ufshcd_is_wb_allowed(hba) || 6007 hba->dev_info.wb_enabled == enable) 6008 return 0; 6009 6010 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 6011 if (ret) { 6012 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 6013 __func__, enable ? "enabling" : "disabling", ret); 6014 return ret; 6015 } 6016 6017 hba->dev_info.wb_enabled = enable; 6018 dev_dbg(hba->dev, "%s: Write Booster %s\n", 6019 __func__, enable ? "enabled" : "disabled"); 6020 6021 return ret; 6022 } 6023 6024 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 6025 bool enable) 6026 { 6027 int ret; 6028 6029 ret = __ufshcd_wb_toggle(hba, enable, 6030 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 6031 if (ret) { 6032 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 6033 __func__, enable ? "enabling" : "disabling", ret); 6034 return; 6035 } 6036 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 6037 __func__, enable ? "enabled" : "disabled"); 6038 } 6039 6040 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 6041 { 6042 int ret; 6043 6044 if (!ufshcd_is_wb_allowed(hba) || 6045 hba->dev_info.wb_buf_flush_enabled == enable) 6046 return 0; 6047 6048 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 6049 if (ret) { 6050 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 6051 __func__, enable ? "enabling" : "disabling", ret); 6052 return ret; 6053 } 6054 6055 hba->dev_info.wb_buf_flush_enabled = enable; 6056 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 6057 __func__, enable ? "enabled" : "disabled"); 6058 6059 return ret; 6060 } 6061 6062 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 6063 u32 avail_buf) 6064 { 6065 u32 cur_buf; 6066 int ret; 6067 u8 index; 6068 6069 index = ufshcd_wb_get_query_index(hba); 6070 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6071 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 6072 index, 0, &cur_buf); 6073 if (ret) { 6074 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 6075 __func__, ret); 6076 return false; 6077 } 6078 6079 if (!cur_buf) { 6080 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 6081 cur_buf); 6082 return false; 6083 } 6084 /* Let it continue to flush when available buffer exceeds threshold */ 6085 return avail_buf < hba->vps->wb_flush_threshold; 6086 } 6087 6088 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 6089 { 6090 if (ufshcd_is_wb_buf_flush_allowed(hba)) 6091 ufshcd_wb_toggle_buf_flush(hba, false); 6092 6093 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 6094 ufshcd_wb_toggle(hba, false); 6095 hba->caps &= ~UFSHCD_CAP_WB_EN; 6096 6097 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 6098 } 6099 6100 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 6101 { 6102 u32 lifetime; 6103 int ret; 6104 u8 index; 6105 6106 index = ufshcd_wb_get_query_index(hba); 6107 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6108 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 6109 index, 0, &lifetime); 6110 if (ret) { 6111 dev_err(hba->dev, 6112 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 6113 __func__, ret); 6114 return false; 6115 } 6116 6117 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6118 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6119 __func__, lifetime); 6120 return false; 6121 } 6122 6123 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6124 __func__, lifetime); 6125 6126 return true; 6127 } 6128 6129 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6130 { 6131 int ret; 6132 u32 avail_buf; 6133 u8 index; 6134 6135 if (!ufshcd_is_wb_allowed(hba)) 6136 return false; 6137 6138 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6139 ufshcd_wb_force_disable(hba); 6140 return false; 6141 } 6142 6143 /* 6144 * The ufs device needs the vcc to be ON to flush. 6145 * With user-space reduction enabled, it's enough to enable flush 6146 * by checking only the available buffer. The threshold 6147 * defined here is > 90% full. 6148 * With user-space preserved enabled, the current-buffer 6149 * should be checked too because the wb buffer size can reduce 6150 * when disk tends to be full. This info is provided by current 6151 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6152 * keeping vcc on when current buffer is empty. 6153 */ 6154 index = ufshcd_wb_get_query_index(hba); 6155 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6156 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6157 index, 0, &avail_buf); 6158 if (ret) { 6159 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6160 __func__, ret); 6161 return false; 6162 } 6163 6164 if (!hba->dev_info.b_presrv_uspc_en) 6165 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6166 6167 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6168 } 6169 6170 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6171 { 6172 struct ufs_hba *hba = container_of(to_delayed_work(work), 6173 struct ufs_hba, 6174 rpm_dev_flush_recheck_work); 6175 /* 6176 * To prevent unnecessary VCC power drain after device finishes 6177 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6178 * after a certain delay to recheck the threshold by next runtime 6179 * suspend. 6180 */ 6181 ufshcd_rpm_get_sync(hba); 6182 ufshcd_rpm_put_sync(hba); 6183 } 6184 6185 /** 6186 * ufshcd_exception_event_handler - handle exceptions raised by device 6187 * @work: pointer to work data 6188 * 6189 * Read bExceptionEventStatus attribute from the device and handle the 6190 * exception event accordingly. 6191 */ 6192 static void ufshcd_exception_event_handler(struct work_struct *work) 6193 { 6194 struct ufs_hba *hba; 6195 int err; 6196 u32 status = 0; 6197 hba = container_of(work, struct ufs_hba, eeh_work); 6198 6199 ufshcd_scsi_block_requests(hba); 6200 err = ufshcd_get_ee_status(hba, &status); 6201 if (err) { 6202 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6203 __func__, err); 6204 goto out; 6205 } 6206 6207 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6208 6209 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6210 ufshcd_bkops_exception_event_handler(hba); 6211 6212 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6213 ufshcd_temp_exception_event_handler(hba, status); 6214 6215 ufs_debugfs_exception_event(hba, status); 6216 out: 6217 ufshcd_scsi_unblock_requests(hba); 6218 } 6219 6220 /* Complete requests that have door-bell cleared */ 6221 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6222 { 6223 if (hba->mcq_enabled) 6224 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6225 else 6226 ufshcd_transfer_req_compl(hba); 6227 6228 ufshcd_tmc_handler(hba); 6229 } 6230 6231 /** 6232 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6233 * to recover from the DL NAC errors or not. 6234 * @hba: per-adapter instance 6235 * 6236 * Return: true if error handling is required, false otherwise. 6237 */ 6238 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6239 { 6240 unsigned long flags; 6241 bool err_handling = true; 6242 6243 spin_lock_irqsave(hba->host->host_lock, flags); 6244 /* 6245 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6246 * device fatal error and/or DL NAC & REPLAY timeout errors. 6247 */ 6248 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6249 goto out; 6250 6251 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6252 ((hba->saved_err & UIC_ERROR) && 6253 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6254 goto out; 6255 6256 if ((hba->saved_err & UIC_ERROR) && 6257 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6258 int err; 6259 /* 6260 * wait for 50ms to see if we can get any other errors or not. 6261 */ 6262 spin_unlock_irqrestore(hba->host->host_lock, flags); 6263 msleep(50); 6264 spin_lock_irqsave(hba->host->host_lock, flags); 6265 6266 /* 6267 * now check if we have got any other severe errors other than 6268 * DL NAC error? 6269 */ 6270 if ((hba->saved_err & INT_FATAL_ERRORS) || 6271 ((hba->saved_err & UIC_ERROR) && 6272 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6273 goto out; 6274 6275 /* 6276 * As DL NAC is the only error received so far, send out NOP 6277 * command to confirm if link is still active or not. 6278 * - If we don't get any response then do error recovery. 6279 * - If we get response then clear the DL NAC error bit. 6280 */ 6281 6282 spin_unlock_irqrestore(hba->host->host_lock, flags); 6283 err = ufshcd_verify_dev_init(hba); 6284 spin_lock_irqsave(hba->host->host_lock, flags); 6285 6286 if (err) 6287 goto out; 6288 6289 /* Link seems to be alive hence ignore the DL NAC errors */ 6290 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6291 hba->saved_err &= ~UIC_ERROR; 6292 /* clear NAC error */ 6293 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6294 if (!hba->saved_uic_err) 6295 err_handling = false; 6296 } 6297 out: 6298 spin_unlock_irqrestore(hba->host->host_lock, flags); 6299 return err_handling; 6300 } 6301 6302 /* host lock must be held before calling this func */ 6303 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6304 { 6305 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6306 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6307 } 6308 6309 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6310 { 6311 lockdep_assert_held(hba->host->host_lock); 6312 6313 /* handle fatal errors only when link is not in error state */ 6314 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6315 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6316 ufshcd_is_saved_err_fatal(hba)) 6317 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6318 else 6319 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6320 queue_work(hba->eh_wq, &hba->eh_work); 6321 } 6322 } 6323 6324 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6325 { 6326 spin_lock_irq(hba->host->host_lock); 6327 hba->force_reset = true; 6328 ufshcd_schedule_eh_work(hba); 6329 spin_unlock_irq(hba->host->host_lock); 6330 } 6331 6332 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6333 { 6334 mutex_lock(&hba->wb_mutex); 6335 down_write(&hba->clk_scaling_lock); 6336 hba->clk_scaling.is_allowed = allow; 6337 up_write(&hba->clk_scaling_lock); 6338 mutex_unlock(&hba->wb_mutex); 6339 } 6340 6341 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6342 { 6343 if (suspend) { 6344 if (hba->clk_scaling.is_enabled) 6345 ufshcd_suspend_clkscaling(hba); 6346 ufshcd_clk_scaling_allow(hba, false); 6347 } else { 6348 ufshcd_clk_scaling_allow(hba, true); 6349 if (hba->clk_scaling.is_enabled) 6350 ufshcd_resume_clkscaling(hba); 6351 } 6352 } 6353 6354 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6355 { 6356 ufshcd_rpm_get_sync(hba); 6357 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6358 hba->is_sys_suspended) { 6359 enum ufs_pm_op pm_op; 6360 6361 /* 6362 * Don't assume anything of resume, if 6363 * resume fails, irq and clocks can be OFF, and powers 6364 * can be OFF or in LPM. 6365 */ 6366 ufshcd_setup_hba_vreg(hba, true); 6367 ufshcd_enable_irq(hba); 6368 ufshcd_setup_vreg(hba, true); 6369 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6370 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6371 ufshcd_hold(hba); 6372 if (!ufshcd_is_clkgating_allowed(hba)) 6373 ufshcd_setup_clocks(hba, true); 6374 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6375 ufshcd_vops_resume(hba, pm_op); 6376 } else { 6377 ufshcd_hold(hba); 6378 if (ufshcd_is_clkscaling_supported(hba) && 6379 hba->clk_scaling.is_enabled) 6380 ufshcd_suspend_clkscaling(hba); 6381 ufshcd_clk_scaling_allow(hba, false); 6382 } 6383 ufshcd_scsi_block_requests(hba); 6384 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6385 blk_mq_wait_quiesce_done(&hba->host->tag_set); 6386 cancel_work_sync(&hba->eeh_work); 6387 } 6388 6389 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6390 { 6391 ufshcd_scsi_unblock_requests(hba); 6392 ufshcd_release(hba); 6393 if (ufshcd_is_clkscaling_supported(hba)) 6394 ufshcd_clk_scaling_suspend(hba, false); 6395 ufshcd_rpm_put(hba); 6396 } 6397 6398 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6399 { 6400 return (!hba->is_powered || hba->shutting_down || 6401 !hba->ufs_device_wlun || 6402 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6403 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6404 ufshcd_is_link_broken(hba)))); 6405 } 6406 6407 #ifdef CONFIG_PM 6408 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6409 { 6410 struct Scsi_Host *shost = hba->host; 6411 struct scsi_device *sdev; 6412 struct request_queue *q; 6413 int ret; 6414 6415 hba->is_sys_suspended = false; 6416 /* 6417 * Set RPM status of wlun device to RPM_ACTIVE, 6418 * this also clears its runtime error. 6419 */ 6420 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6421 6422 /* hba device might have a runtime error otherwise */ 6423 if (ret) 6424 ret = pm_runtime_set_active(hba->dev); 6425 /* 6426 * If wlun device had runtime error, we also need to resume those 6427 * consumer scsi devices in case any of them has failed to be 6428 * resumed due to supplier runtime resume failure. This is to unblock 6429 * blk_queue_enter in case there are bios waiting inside it. 6430 */ 6431 if (!ret) { 6432 shost_for_each_device(sdev, shost) { 6433 q = sdev->request_queue; 6434 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6435 q->rpm_status == RPM_SUSPENDING)) 6436 pm_request_resume(q->dev); 6437 } 6438 } 6439 } 6440 #else 6441 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6442 { 6443 } 6444 #endif 6445 6446 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6447 { 6448 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6449 u32 mode; 6450 6451 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6452 6453 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6454 return true; 6455 6456 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6457 return true; 6458 6459 return false; 6460 } 6461 6462 static bool ufshcd_abort_one(struct request *rq, void *priv) 6463 { 6464 int *ret = priv; 6465 u32 tag = rq->tag; 6466 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6467 struct scsi_device *sdev = cmd->device; 6468 struct Scsi_Host *shost = sdev->host; 6469 struct ufs_hba *hba = shost_priv(shost); 6470 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 6471 struct ufs_hw_queue *hwq; 6472 unsigned long flags; 6473 6474 *ret = ufshcd_try_to_abort_task(hba, tag); 6475 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6476 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6477 *ret ? "failed" : "succeeded"); 6478 6479 /* Release cmd in MCQ mode if abort succeeds */ 6480 if (hba->mcq_enabled && (*ret == 0)) { 6481 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 6482 if (!hwq) 6483 return 0; 6484 spin_lock_irqsave(&hwq->cq_lock, flags); 6485 if (ufshcd_cmd_inflight(lrbp->cmd)) 6486 ufshcd_release_scsi_cmd(hba, lrbp); 6487 spin_unlock_irqrestore(&hwq->cq_lock, flags); 6488 } 6489 6490 return *ret == 0; 6491 } 6492 6493 /** 6494 * ufshcd_abort_all - Abort all pending commands. 6495 * @hba: Host bus adapter pointer. 6496 * 6497 * Return: true if and only if the host controller needs to be reset. 6498 */ 6499 static bool ufshcd_abort_all(struct ufs_hba *hba) 6500 { 6501 int tag, ret = 0; 6502 6503 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6504 if (ret) 6505 goto out; 6506 6507 /* Clear pending task management requests */ 6508 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6509 ret = ufshcd_clear_tm_cmd(hba, tag); 6510 if (ret) 6511 goto out; 6512 } 6513 6514 out: 6515 /* Complete the requests that are cleared by s/w */ 6516 ufshcd_complete_requests(hba, false); 6517 6518 return ret != 0; 6519 } 6520 6521 /** 6522 * ufshcd_err_handler - handle UFS errors that require s/w attention 6523 * @work: pointer to work structure 6524 */ 6525 static void ufshcd_err_handler(struct work_struct *work) 6526 { 6527 int retries = MAX_ERR_HANDLER_RETRIES; 6528 struct ufs_hba *hba; 6529 unsigned long flags; 6530 bool needs_restore; 6531 bool needs_reset; 6532 int pmc_err; 6533 6534 hba = container_of(work, struct ufs_hba, eh_work); 6535 6536 dev_info(hba->dev, 6537 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6538 __func__, ufshcd_state_name[hba->ufshcd_state], 6539 hba->is_powered, hba->shutting_down, hba->saved_err, 6540 hba->saved_uic_err, hba->force_reset, 6541 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6542 6543 down(&hba->host_sem); 6544 spin_lock_irqsave(hba->host->host_lock, flags); 6545 if (ufshcd_err_handling_should_stop(hba)) { 6546 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6547 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6548 spin_unlock_irqrestore(hba->host->host_lock, flags); 6549 up(&hba->host_sem); 6550 return; 6551 } 6552 ufshcd_set_eh_in_progress(hba); 6553 spin_unlock_irqrestore(hba->host->host_lock, flags); 6554 ufshcd_err_handling_prepare(hba); 6555 /* Complete requests that have door-bell cleared by h/w */ 6556 ufshcd_complete_requests(hba, false); 6557 spin_lock_irqsave(hba->host->host_lock, flags); 6558 again: 6559 needs_restore = false; 6560 needs_reset = false; 6561 6562 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6563 hba->ufshcd_state = UFSHCD_STATE_RESET; 6564 /* 6565 * A full reset and restore might have happened after preparation 6566 * is finished, double check whether we should stop. 6567 */ 6568 if (ufshcd_err_handling_should_stop(hba)) 6569 goto skip_err_handling; 6570 6571 if ((hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) && 6572 !hba->force_reset) { 6573 bool ret; 6574 6575 spin_unlock_irqrestore(hba->host->host_lock, flags); 6576 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6577 ret = ufshcd_quirk_dl_nac_errors(hba); 6578 spin_lock_irqsave(hba->host->host_lock, flags); 6579 if (!ret && ufshcd_err_handling_should_stop(hba)) 6580 goto skip_err_handling; 6581 } 6582 6583 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6584 (hba->saved_uic_err && 6585 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6586 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6587 6588 spin_unlock_irqrestore(hba->host->host_lock, flags); 6589 ufshcd_print_host_state(hba); 6590 ufshcd_print_pwr_info(hba); 6591 ufshcd_print_evt_hist(hba); 6592 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6593 ufshcd_print_trs_all(hba, pr_prdt); 6594 spin_lock_irqsave(hba->host->host_lock, flags); 6595 } 6596 6597 /* 6598 * if host reset is required then skip clearing the pending 6599 * transfers forcefully because they will get cleared during 6600 * host reset and restore 6601 */ 6602 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6603 ufshcd_is_saved_err_fatal(hba) || 6604 ((hba->saved_err & UIC_ERROR) && 6605 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6606 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6607 needs_reset = true; 6608 goto do_reset; 6609 } 6610 6611 /* 6612 * If LINERESET was caught, UFS might have been put to PWM mode, 6613 * check if power mode restore is needed. 6614 */ 6615 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6616 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6617 if (!hba->saved_uic_err) 6618 hba->saved_err &= ~UIC_ERROR; 6619 spin_unlock_irqrestore(hba->host->host_lock, flags); 6620 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6621 needs_restore = true; 6622 spin_lock_irqsave(hba->host->host_lock, flags); 6623 if (!hba->saved_err && !needs_restore) 6624 goto skip_err_handling; 6625 } 6626 6627 hba->silence_err_logs = true; 6628 /* release lock as clear command might sleep */ 6629 spin_unlock_irqrestore(hba->host->host_lock, flags); 6630 6631 needs_reset = ufshcd_abort_all(hba); 6632 6633 spin_lock_irqsave(hba->host->host_lock, flags); 6634 hba->silence_err_logs = false; 6635 if (needs_reset) 6636 goto do_reset; 6637 6638 /* 6639 * After all reqs and tasks are cleared from doorbell, 6640 * now it is safe to retore power mode. 6641 */ 6642 if (needs_restore) { 6643 spin_unlock_irqrestore(hba->host->host_lock, flags); 6644 /* 6645 * Hold the scaling lock just in case dev cmds 6646 * are sent via bsg and/or sysfs. 6647 */ 6648 down_write(&hba->clk_scaling_lock); 6649 hba->force_pmc = true; 6650 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6651 if (pmc_err) { 6652 needs_reset = true; 6653 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6654 __func__, pmc_err); 6655 } 6656 hba->force_pmc = false; 6657 ufshcd_print_pwr_info(hba); 6658 up_write(&hba->clk_scaling_lock); 6659 spin_lock_irqsave(hba->host->host_lock, flags); 6660 } 6661 6662 do_reset: 6663 /* Fatal errors need reset */ 6664 if (needs_reset) { 6665 int err; 6666 6667 hba->force_reset = false; 6668 spin_unlock_irqrestore(hba->host->host_lock, flags); 6669 err = ufshcd_reset_and_restore(hba); 6670 if (err) 6671 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6672 __func__, err); 6673 else 6674 ufshcd_recover_pm_error(hba); 6675 spin_lock_irqsave(hba->host->host_lock, flags); 6676 } 6677 6678 skip_err_handling: 6679 if (!needs_reset) { 6680 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6681 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6682 if (hba->saved_err || hba->saved_uic_err) 6683 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6684 __func__, hba->saved_err, hba->saved_uic_err); 6685 } 6686 /* Exit in an operational state or dead */ 6687 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6688 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6689 if (--retries) 6690 goto again; 6691 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6692 } 6693 ufshcd_clear_eh_in_progress(hba); 6694 spin_unlock_irqrestore(hba->host->host_lock, flags); 6695 ufshcd_err_handling_unprepare(hba); 6696 up(&hba->host_sem); 6697 6698 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6699 ufshcd_state_name[hba->ufshcd_state]); 6700 } 6701 6702 /** 6703 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6704 * @hba: per-adapter instance 6705 * 6706 * Return: 6707 * IRQ_HANDLED - If interrupt is valid 6708 * IRQ_NONE - If invalid interrupt 6709 */ 6710 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6711 { 6712 u32 reg; 6713 irqreturn_t retval = IRQ_NONE; 6714 6715 /* PHY layer error */ 6716 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6717 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6718 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6719 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6720 /* 6721 * To know whether this error is fatal or not, DB timeout 6722 * must be checked but this error is handled separately. 6723 */ 6724 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6725 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6726 __func__); 6727 6728 /* Got a LINERESET indication. */ 6729 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6730 struct uic_command *cmd = NULL; 6731 6732 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6733 if (hba->uic_async_done && hba->active_uic_cmd) 6734 cmd = hba->active_uic_cmd; 6735 /* 6736 * Ignore the LINERESET during power mode change 6737 * operation via DME_SET command. 6738 */ 6739 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6740 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6741 } 6742 retval |= IRQ_HANDLED; 6743 } 6744 6745 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6746 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6747 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6748 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6749 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6750 6751 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6752 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6753 else if (hba->dev_quirks & 6754 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6755 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6756 hba->uic_error |= 6757 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6758 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6759 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6760 } 6761 retval |= IRQ_HANDLED; 6762 } 6763 6764 /* UIC NL/TL/DME errors needs software retry */ 6765 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6766 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6767 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6768 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6769 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6770 retval |= IRQ_HANDLED; 6771 } 6772 6773 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6774 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6775 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6776 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6777 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6778 retval |= IRQ_HANDLED; 6779 } 6780 6781 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6782 if ((reg & UIC_DME_ERROR) && 6783 (reg & UIC_DME_ERROR_CODE_MASK)) { 6784 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6785 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6786 retval |= IRQ_HANDLED; 6787 } 6788 6789 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6790 __func__, hba->uic_error); 6791 return retval; 6792 } 6793 6794 /** 6795 * ufshcd_check_errors - Check for errors that need s/w attention 6796 * @hba: per-adapter instance 6797 * @intr_status: interrupt status generated by the controller 6798 * 6799 * Return: 6800 * IRQ_HANDLED - If interrupt is valid 6801 * IRQ_NONE - If invalid interrupt 6802 */ 6803 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6804 { 6805 bool queue_eh_work = false; 6806 irqreturn_t retval = IRQ_NONE; 6807 6808 spin_lock(hba->host->host_lock); 6809 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6810 6811 if (hba->errors & INT_FATAL_ERRORS) { 6812 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6813 hba->errors); 6814 queue_eh_work = true; 6815 } 6816 6817 if (hba->errors & UIC_ERROR) { 6818 hba->uic_error = 0; 6819 retval = ufshcd_update_uic_error(hba); 6820 if (hba->uic_error) 6821 queue_eh_work = true; 6822 } 6823 6824 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6825 dev_err(hba->dev, 6826 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6827 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6828 "Enter" : "Exit", 6829 hba->errors, ufshcd_get_upmcrs(hba)); 6830 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6831 hba->errors); 6832 ufshcd_set_link_broken(hba); 6833 queue_eh_work = true; 6834 } 6835 6836 if (queue_eh_work) { 6837 /* 6838 * update the transfer error masks to sticky bits, let's do this 6839 * irrespective of current ufshcd_state. 6840 */ 6841 hba->saved_err |= hba->errors; 6842 hba->saved_uic_err |= hba->uic_error; 6843 6844 /* dump controller state before resetting */ 6845 if ((hba->saved_err & 6846 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6847 (hba->saved_uic_err && 6848 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6849 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6850 __func__, hba->saved_err, 6851 hba->saved_uic_err); 6852 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6853 "host_regs: "); 6854 ufshcd_print_pwr_info(hba); 6855 } 6856 ufshcd_schedule_eh_work(hba); 6857 retval |= IRQ_HANDLED; 6858 } 6859 /* 6860 * if (!queue_eh_work) - 6861 * Other errors are either non-fatal where host recovers 6862 * itself without s/w intervention or errors that will be 6863 * handled by the SCSI core layer. 6864 */ 6865 hba->errors = 0; 6866 hba->uic_error = 0; 6867 spin_unlock(hba->host->host_lock); 6868 return retval; 6869 } 6870 6871 /** 6872 * ufshcd_tmc_handler - handle task management function completion 6873 * @hba: per adapter instance 6874 * 6875 * Return: 6876 * IRQ_HANDLED - If interrupt is valid 6877 * IRQ_NONE - If invalid interrupt 6878 */ 6879 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6880 { 6881 unsigned long flags, pending, issued; 6882 irqreturn_t ret = IRQ_NONE; 6883 int tag; 6884 6885 spin_lock_irqsave(hba->host->host_lock, flags); 6886 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6887 issued = hba->outstanding_tasks & ~pending; 6888 for_each_set_bit(tag, &issued, hba->nutmrs) { 6889 struct request *req = hba->tmf_rqs[tag]; 6890 struct completion *c = req->end_io_data; 6891 6892 complete(c); 6893 ret = IRQ_HANDLED; 6894 } 6895 spin_unlock_irqrestore(hba->host->host_lock, flags); 6896 6897 return ret; 6898 } 6899 6900 /** 6901 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6902 * @hba: per adapter instance 6903 * 6904 * Return: IRQ_HANDLED if interrupt is handled. 6905 */ 6906 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6907 { 6908 struct ufs_hw_queue *hwq; 6909 unsigned long outstanding_cqs; 6910 unsigned int nr_queues; 6911 int i, ret; 6912 u32 events; 6913 6914 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6915 if (ret) 6916 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6917 6918 /* Exclude the poll queues */ 6919 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6920 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6921 hwq = &hba->uhq[i]; 6922 6923 events = ufshcd_mcq_read_cqis(hba, i); 6924 if (events) 6925 ufshcd_mcq_write_cqis(hba, events, i); 6926 6927 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6928 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6929 } 6930 6931 return IRQ_HANDLED; 6932 } 6933 6934 /** 6935 * ufshcd_sl_intr - Interrupt service routine 6936 * @hba: per adapter instance 6937 * @intr_status: contains interrupts generated by the controller 6938 * 6939 * Return: 6940 * IRQ_HANDLED - If interrupt is valid 6941 * IRQ_NONE - If invalid interrupt 6942 */ 6943 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6944 { 6945 irqreturn_t retval = IRQ_NONE; 6946 6947 if (intr_status & UFSHCD_UIC_MASK) 6948 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6949 6950 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6951 retval |= ufshcd_check_errors(hba, intr_status); 6952 6953 if (intr_status & UTP_TASK_REQ_COMPL) 6954 retval |= ufshcd_tmc_handler(hba); 6955 6956 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6957 retval |= ufshcd_transfer_req_compl(hba); 6958 6959 if (intr_status & MCQ_CQ_EVENT_STATUS) 6960 retval |= ufshcd_handle_mcq_cq_events(hba); 6961 6962 return retval; 6963 } 6964 6965 /** 6966 * ufshcd_intr - Main interrupt service routine 6967 * @irq: irq number 6968 * @__hba: pointer to adapter instance 6969 * 6970 * Return: 6971 * IRQ_HANDLED - If interrupt is valid 6972 * IRQ_NONE - If invalid interrupt 6973 */ 6974 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6975 { 6976 u32 intr_status, enabled_intr_status = 0; 6977 irqreturn_t retval = IRQ_NONE; 6978 struct ufs_hba *hba = __hba; 6979 int retries = hba->nutrs; 6980 6981 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6982 hba->ufs_stats.last_intr_status = intr_status; 6983 hba->ufs_stats.last_intr_ts = local_clock(); 6984 6985 /* 6986 * There could be max of hba->nutrs reqs in flight and in worst case 6987 * if the reqs get finished 1 by 1 after the interrupt status is 6988 * read, make sure we handle them by checking the interrupt status 6989 * again in a loop until we process all of the reqs before returning. 6990 */ 6991 while (intr_status && retries--) { 6992 enabled_intr_status = 6993 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6994 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6995 if (enabled_intr_status) 6996 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 6997 6998 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6999 } 7000 7001 if (enabled_intr_status && retval == IRQ_NONE && 7002 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 7003 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 7004 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 7005 __func__, 7006 intr_status, 7007 hba->ufs_stats.last_intr_status, 7008 enabled_intr_status); 7009 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 7010 } 7011 7012 return retval; 7013 } 7014 7015 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 7016 { 7017 int err = 0; 7018 u32 mask = 1 << tag; 7019 unsigned long flags; 7020 7021 if (!test_bit(tag, &hba->outstanding_tasks)) 7022 goto out; 7023 7024 spin_lock_irqsave(hba->host->host_lock, flags); 7025 ufshcd_utmrl_clear(hba, tag); 7026 spin_unlock_irqrestore(hba->host->host_lock, flags); 7027 7028 /* poll for max. 1 sec to clear door bell register by h/w */ 7029 err = ufshcd_wait_for_register(hba, 7030 REG_UTP_TASK_REQ_DOOR_BELL, 7031 mask, 0, 1000, 1000); 7032 7033 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 7034 tag, err < 0 ? "failed" : "succeeded"); 7035 7036 out: 7037 return err; 7038 } 7039 7040 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 7041 struct utp_task_req_desc *treq, u8 tm_function) 7042 { 7043 struct request_queue *q = hba->tmf_queue; 7044 struct Scsi_Host *host = hba->host; 7045 DECLARE_COMPLETION_ONSTACK(wait); 7046 struct request *req; 7047 unsigned long flags; 7048 int task_tag, err; 7049 7050 /* 7051 * blk_mq_alloc_request() is used here only to get a free tag. 7052 */ 7053 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 7054 if (IS_ERR(req)) 7055 return PTR_ERR(req); 7056 7057 req->end_io_data = &wait; 7058 ufshcd_hold(hba); 7059 7060 spin_lock_irqsave(host->host_lock, flags); 7061 7062 task_tag = req->tag; 7063 hba->tmf_rqs[req->tag] = req; 7064 treq->upiu_req.req_header.task_tag = task_tag; 7065 7066 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 7067 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 7068 7069 /* send command to the controller */ 7070 __set_bit(task_tag, &hba->outstanding_tasks); 7071 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 7072 7073 spin_unlock_irqrestore(host->host_lock, flags); 7074 7075 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 7076 7077 /* wait until the task management command is completed */ 7078 err = wait_for_completion_io_timeout(&wait, 7079 msecs_to_jiffies(TM_CMD_TIMEOUT)); 7080 if (!err) { 7081 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 7082 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 7083 __func__, tm_function); 7084 if (ufshcd_clear_tm_cmd(hba, task_tag)) 7085 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 7086 __func__, task_tag); 7087 err = -ETIMEDOUT; 7088 } else { 7089 err = 0; 7090 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 7091 7092 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 7093 } 7094 7095 spin_lock_irqsave(hba->host->host_lock, flags); 7096 hba->tmf_rqs[req->tag] = NULL; 7097 __clear_bit(task_tag, &hba->outstanding_tasks); 7098 spin_unlock_irqrestore(hba->host->host_lock, flags); 7099 7100 ufshcd_release(hba); 7101 blk_mq_free_request(req); 7102 7103 return err; 7104 } 7105 7106 /** 7107 * ufshcd_issue_tm_cmd - issues task management commands to controller 7108 * @hba: per adapter instance 7109 * @lun_id: LUN ID to which TM command is sent 7110 * @task_id: task ID to which the TM command is applicable 7111 * @tm_function: task management function opcode 7112 * @tm_response: task management service response return value 7113 * 7114 * Return: non-zero value on error, zero on success. 7115 */ 7116 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7117 u8 tm_function, u8 *tm_response) 7118 { 7119 struct utp_task_req_desc treq = { }; 7120 enum utp_ocs ocs_value; 7121 int err; 7122 7123 /* Configure task request descriptor */ 7124 treq.header.interrupt = 1; 7125 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7126 7127 /* Configure task request UPIU */ 7128 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7129 treq.upiu_req.req_header.lun = lun_id; 7130 treq.upiu_req.req_header.tm_function = tm_function; 7131 7132 /* 7133 * The host shall provide the same value for LUN field in the basic 7134 * header and for Input Parameter. 7135 */ 7136 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7137 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7138 7139 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7140 if (err == -ETIMEDOUT) 7141 return err; 7142 7143 ocs_value = treq.header.ocs & MASK_OCS; 7144 if (ocs_value != OCS_SUCCESS) 7145 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7146 __func__, ocs_value); 7147 else if (tm_response) 7148 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7149 MASK_TM_SERVICE_RESP; 7150 return err; 7151 } 7152 7153 /** 7154 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7155 * @hba: per-adapter instance 7156 * @req_upiu: upiu request 7157 * @rsp_upiu: upiu reply 7158 * @desc_buff: pointer to descriptor buffer, NULL if NA 7159 * @buff_len: descriptor size, 0 if NA 7160 * @cmd_type: specifies the type (NOP, Query...) 7161 * @desc_op: descriptor operation 7162 * 7163 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7164 * Therefore, it "rides" the device management infrastructure: uses its tag and 7165 * tasks work queues. 7166 * 7167 * Since there is only one available tag for device management commands, 7168 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7169 * 7170 * Return: 0 upon success; < 0 upon failure. 7171 */ 7172 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7173 struct utp_upiu_req *req_upiu, 7174 struct utp_upiu_req *rsp_upiu, 7175 u8 *desc_buff, int *buff_len, 7176 enum dev_cmd_type cmd_type, 7177 enum query_opcode desc_op) 7178 { 7179 const u32 tag = hba->reserved_slot; 7180 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7181 int err = 0; 7182 u8 upiu_flags; 7183 7184 /* Protects use of hba->reserved_slot. */ 7185 lockdep_assert_held(&hba->dev_cmd.lock); 7186 7187 ufshcd_setup_dev_cmd(hba, lrbp, cmd_type, 0, tag); 7188 7189 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, 0); 7190 7191 /* update the task tag in the request upiu */ 7192 req_upiu->header.task_tag = tag; 7193 7194 /* just copy the upiu request as it is */ 7195 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7196 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7197 /* The Data Segment Area is optional depending upon the query 7198 * function value. for WRITE DESCRIPTOR, the data segment 7199 * follows right after the tsf. 7200 */ 7201 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7202 *buff_len = 0; 7203 } 7204 7205 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7206 7207 /* 7208 * ignore the returning value here - ufshcd_check_query_response is 7209 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7210 * read the response directly ignoring all errors. 7211 */ 7212 ufshcd_issue_dev_cmd(hba, lrbp, tag, QUERY_REQ_TIMEOUT); 7213 7214 /* just copy the upiu response as it is */ 7215 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7216 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7217 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7218 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7219 .data_segment_length); 7220 7221 if (*buff_len >= resp_len) { 7222 memcpy(desc_buff, descp, resp_len); 7223 *buff_len = resp_len; 7224 } else { 7225 dev_warn(hba->dev, 7226 "%s: rsp size %d is bigger than buffer size %d", 7227 __func__, resp_len, *buff_len); 7228 *buff_len = 0; 7229 err = -EINVAL; 7230 } 7231 } 7232 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7233 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7234 7235 return err; 7236 } 7237 7238 /** 7239 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7240 * @hba: per-adapter instance 7241 * @req_upiu: upiu request 7242 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7243 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7244 * @desc_buff: pointer to descriptor buffer, NULL if NA 7245 * @buff_len: descriptor size, 0 if NA 7246 * @desc_op: descriptor operation 7247 * 7248 * Supports UTP Transfer requests (nop and query), and UTP Task 7249 * Management requests. 7250 * It is up to the caller to fill the upiu conent properly, as it will 7251 * be copied without any further input validations. 7252 * 7253 * Return: 0 upon success; < 0 upon failure. 7254 */ 7255 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7256 struct utp_upiu_req *req_upiu, 7257 struct utp_upiu_req *rsp_upiu, 7258 enum upiu_request_transaction msgcode, 7259 u8 *desc_buff, int *buff_len, 7260 enum query_opcode desc_op) 7261 { 7262 int err; 7263 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7264 struct utp_task_req_desc treq = { }; 7265 enum utp_ocs ocs_value; 7266 u8 tm_f = req_upiu->header.tm_function; 7267 7268 switch (msgcode) { 7269 case UPIU_TRANSACTION_NOP_OUT: 7270 cmd_type = DEV_CMD_TYPE_NOP; 7271 fallthrough; 7272 case UPIU_TRANSACTION_QUERY_REQ: 7273 ufshcd_dev_man_lock(hba); 7274 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7275 desc_buff, buff_len, 7276 cmd_type, desc_op); 7277 ufshcd_dev_man_unlock(hba); 7278 7279 break; 7280 case UPIU_TRANSACTION_TASK_REQ: 7281 treq.header.interrupt = 1; 7282 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7283 7284 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7285 7286 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7287 if (err == -ETIMEDOUT) 7288 break; 7289 7290 ocs_value = treq.header.ocs & MASK_OCS; 7291 if (ocs_value != OCS_SUCCESS) { 7292 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7293 ocs_value); 7294 break; 7295 } 7296 7297 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7298 7299 break; 7300 default: 7301 err = -EINVAL; 7302 7303 break; 7304 } 7305 7306 return err; 7307 } 7308 7309 /** 7310 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7311 * @hba: per adapter instance 7312 * @req_upiu: upiu request 7313 * @rsp_upiu: upiu reply 7314 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7315 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7316 * @sg_cnt: The number of sg lists actually used 7317 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7318 * @dir: DMA direction 7319 * 7320 * Return: zero on success, non-zero on failure. 7321 */ 7322 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7323 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7324 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7325 enum dma_data_direction dir) 7326 { 7327 const u32 tag = hba->reserved_slot; 7328 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7329 int err = 0; 7330 int result; 7331 u8 upiu_flags; 7332 u8 *ehs_data; 7333 u16 ehs_len; 7334 int ehs = (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) ? 2 : 0; 7335 7336 /* Protects use of hba->reserved_slot. */ 7337 ufshcd_dev_man_lock(hba); 7338 7339 ufshcd_setup_dev_cmd(hba, lrbp, DEV_CMD_TYPE_RPMB, UFS_UPIU_RPMB_WLUN, tag); 7340 7341 ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, DMA_NONE, ehs); 7342 7343 /* update the task tag */ 7344 req_upiu->header.task_tag = tag; 7345 7346 /* copy the UPIU(contains CDB) request as it is */ 7347 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7348 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7349 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7350 7351 if (dir != DMA_NONE && sg_list) 7352 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7353 7354 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7355 7356 err = ufshcd_issue_dev_cmd(hba, lrbp, tag, ADVANCED_RPMB_REQ_TIMEOUT); 7357 7358 if (!err) { 7359 /* Just copy the upiu response as it is */ 7360 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7361 /* Get the response UPIU result */ 7362 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7363 lrbp->ucd_rsp_ptr->header.status; 7364 7365 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7366 /* 7367 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7368 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7369 * Message is 02h 7370 */ 7371 if (ehs_len == 2 && rsp_ehs) { 7372 /* 7373 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7374 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7375 */ 7376 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7377 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7378 } 7379 } 7380 7381 ufshcd_dev_man_unlock(hba); 7382 7383 return err ? : result; 7384 } 7385 7386 /** 7387 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7388 * @cmd: SCSI command pointer 7389 * 7390 * Return: SUCCESS or FAILED. 7391 */ 7392 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7393 { 7394 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7395 struct Scsi_Host *host; 7396 struct ufs_hba *hba; 7397 struct ufs_hw_queue *hwq; 7398 struct ufshcd_lrb *lrbp; 7399 u32 pos, not_cleared_mask = 0; 7400 int err; 7401 u8 resp = 0xF, lun; 7402 7403 host = cmd->device->host; 7404 hba = shost_priv(host); 7405 7406 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7407 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7408 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7409 if (!err) 7410 err = resp; 7411 goto out; 7412 } 7413 7414 if (hba->mcq_enabled) { 7415 for (pos = 0; pos < hba->nutrs; pos++) { 7416 lrbp = &hba->lrb[pos]; 7417 if (ufshcd_cmd_inflight(lrbp->cmd) && 7418 lrbp->lun == lun) { 7419 ufshcd_clear_cmd(hba, pos); 7420 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7421 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7422 } 7423 } 7424 err = 0; 7425 goto out; 7426 } 7427 7428 /* clear the commands that were pending for corresponding LUN */ 7429 spin_lock_irqsave(&hba->outstanding_lock, flags); 7430 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7431 if (hba->lrb[pos].lun == lun) 7432 __set_bit(pos, &pending_reqs); 7433 hba->outstanding_reqs &= ~pending_reqs; 7434 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7435 7436 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7437 if (ufshcd_clear_cmd(hba, pos) < 0) { 7438 spin_lock_irqsave(&hba->outstanding_lock, flags); 7439 not_cleared = 1U << pos & 7440 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7441 hba->outstanding_reqs |= not_cleared; 7442 not_cleared_mask |= not_cleared; 7443 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7444 7445 dev_err(hba->dev, "%s: failed to clear request %d\n", 7446 __func__, pos); 7447 } 7448 } 7449 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7450 7451 out: 7452 hba->req_abort_count = 0; 7453 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7454 if (!err) { 7455 err = SUCCESS; 7456 } else { 7457 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7458 err = FAILED; 7459 } 7460 return err; 7461 } 7462 7463 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7464 { 7465 struct ufshcd_lrb *lrbp; 7466 int tag; 7467 7468 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7469 lrbp = &hba->lrb[tag]; 7470 lrbp->req_abort_skip = true; 7471 } 7472 } 7473 7474 /** 7475 * ufshcd_try_to_abort_task - abort a specific task 7476 * @hba: Pointer to adapter instance 7477 * @tag: Task tag/index to be aborted 7478 * 7479 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7480 * command, and in host controller by clearing the door-bell register. There can 7481 * be race between controller sending the command to the device while abort is 7482 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7483 * really issued and then try to abort it. 7484 * 7485 * Return: zero on success, non-zero on failure. 7486 */ 7487 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7488 { 7489 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7490 int err = 0; 7491 int poll_cnt; 7492 u8 resp = 0xF; 7493 u32 reg; 7494 7495 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7496 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7497 UFS_QUERY_TASK, &resp); 7498 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7499 /* cmd pending in the device */ 7500 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7501 __func__, tag); 7502 break; 7503 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7504 /* 7505 * cmd not pending in the device, check if it is 7506 * in transition. 7507 */ 7508 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n", 7509 __func__, tag); 7510 if (hba->mcq_enabled) { 7511 /* MCQ mode */ 7512 if (ufshcd_cmd_inflight(lrbp->cmd)) { 7513 /* sleep for max. 200us same delay as in SDB mode */ 7514 usleep_range(100, 200); 7515 continue; 7516 } 7517 /* command completed already */ 7518 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n", 7519 __func__, tag); 7520 goto out; 7521 } 7522 7523 /* Single Doorbell Mode */ 7524 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7525 if (reg & (1 << tag)) { 7526 /* sleep for max. 200us to stabilize */ 7527 usleep_range(100, 200); 7528 continue; 7529 } 7530 /* command completed already */ 7531 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n", 7532 __func__, tag); 7533 goto out; 7534 } else { 7535 dev_err(hba->dev, 7536 "%s: no response from device. tag = %d, err %d\n", 7537 __func__, tag, err); 7538 if (!err) 7539 err = resp; /* service response error */ 7540 goto out; 7541 } 7542 } 7543 7544 if (!poll_cnt) { 7545 err = -EBUSY; 7546 goto out; 7547 } 7548 7549 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7550 UFS_ABORT_TASK, &resp); 7551 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7552 if (!err) { 7553 err = resp; /* service response error */ 7554 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7555 __func__, tag, err); 7556 } 7557 goto out; 7558 } 7559 7560 err = ufshcd_clear_cmd(hba, tag); 7561 if (err) 7562 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7563 __func__, tag, err); 7564 7565 out: 7566 return err; 7567 } 7568 7569 /** 7570 * ufshcd_abort - scsi host template eh_abort_handler callback 7571 * @cmd: SCSI command pointer 7572 * 7573 * Return: SUCCESS or FAILED. 7574 */ 7575 static int ufshcd_abort(struct scsi_cmnd *cmd) 7576 { 7577 struct Scsi_Host *host = cmd->device->host; 7578 struct ufs_hba *hba = shost_priv(host); 7579 int tag = scsi_cmd_to_rq(cmd)->tag; 7580 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7581 unsigned long flags; 7582 int err = FAILED; 7583 bool outstanding; 7584 u32 reg; 7585 7586 ufshcd_hold(hba); 7587 7588 if (!hba->mcq_enabled) { 7589 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7590 if (!test_bit(tag, &hba->outstanding_reqs)) { 7591 /* If command is already aborted/completed, return FAILED. */ 7592 dev_err(hba->dev, 7593 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7594 __func__, tag, hba->outstanding_reqs, reg); 7595 goto release; 7596 } 7597 } 7598 7599 /* Print Transfer Request of aborted task */ 7600 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7601 7602 /* 7603 * Print detailed info about aborted request. 7604 * As more than one request might get aborted at the same time, 7605 * print full information only for the first aborted request in order 7606 * to reduce repeated printouts. For other aborted requests only print 7607 * basic details. 7608 */ 7609 scsi_print_command(cmd); 7610 if (!hba->req_abort_count) { 7611 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7612 ufshcd_print_evt_hist(hba); 7613 ufshcd_print_host_state(hba); 7614 ufshcd_print_pwr_info(hba); 7615 ufshcd_print_tr(hba, tag, true); 7616 } else { 7617 ufshcd_print_tr(hba, tag, false); 7618 } 7619 hba->req_abort_count++; 7620 7621 if (!hba->mcq_enabled && !(reg & (1 << tag))) { 7622 /* only execute this code in single doorbell mode */ 7623 dev_err(hba->dev, 7624 "%s: cmd was completed, but without a notifying intr, tag = %d", 7625 __func__, tag); 7626 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7627 goto release; 7628 } 7629 7630 /* 7631 * Task abort to the device W-LUN is illegal. When this command 7632 * will fail, due to spec violation, scsi err handling next step 7633 * will be to send LU reset which, again, is a spec violation. 7634 * To avoid these unnecessary/illegal steps, first we clean up 7635 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7636 * then queue the eh_work and bail. 7637 */ 7638 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7639 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7640 7641 spin_lock_irqsave(host->host_lock, flags); 7642 hba->force_reset = true; 7643 ufshcd_schedule_eh_work(hba); 7644 spin_unlock_irqrestore(host->host_lock, flags); 7645 goto release; 7646 } 7647 7648 if (hba->mcq_enabled) { 7649 /* MCQ mode. Branch off to handle abort for mcq mode */ 7650 err = ufshcd_mcq_abort(cmd); 7651 goto release; 7652 } 7653 7654 /* Skip task abort in case previous aborts failed and report failure */ 7655 if (lrbp->req_abort_skip) { 7656 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7657 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7658 goto release; 7659 } 7660 7661 err = ufshcd_try_to_abort_task(hba, tag); 7662 if (err) { 7663 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7664 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7665 err = FAILED; 7666 goto release; 7667 } 7668 7669 /* 7670 * Clear the corresponding bit from outstanding_reqs since the command 7671 * has been aborted successfully. 7672 */ 7673 spin_lock_irqsave(&hba->outstanding_lock, flags); 7674 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7675 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7676 7677 if (outstanding) 7678 ufshcd_release_scsi_cmd(hba, lrbp); 7679 7680 err = SUCCESS; 7681 7682 release: 7683 /* Matches the ufshcd_hold() call at the start of this function. */ 7684 ufshcd_release(hba); 7685 return err; 7686 } 7687 7688 /** 7689 * ufshcd_host_reset_and_restore - reset and restore host controller 7690 * @hba: per-adapter instance 7691 * 7692 * Note that host controller reset may issue DME_RESET to 7693 * local and remote (device) Uni-Pro stack and the attributes 7694 * are reset to default state. 7695 * 7696 * Return: zero on success, non-zero on failure. 7697 */ 7698 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7699 { 7700 int err; 7701 7702 /* 7703 * Stop the host controller and complete the requests 7704 * cleared by h/w 7705 */ 7706 ufshcd_hba_stop(hba); 7707 hba->silence_err_logs = true; 7708 ufshcd_complete_requests(hba, true); 7709 hba->silence_err_logs = false; 7710 7711 /* scale up clocks to max frequency before full reinitialization */ 7712 ufshcd_scale_clks(hba, ULONG_MAX, true); 7713 7714 err = ufshcd_hba_enable(hba); 7715 7716 /* Establish the link again and restore the device */ 7717 if (!err) 7718 err = ufshcd_probe_hba(hba, false); 7719 7720 if (err) 7721 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7722 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7723 return err; 7724 } 7725 7726 /** 7727 * ufshcd_reset_and_restore - reset and re-initialize host/device 7728 * @hba: per-adapter instance 7729 * 7730 * Reset and recover device, host and re-establish link. This 7731 * is helpful to recover the communication in fatal error conditions. 7732 * 7733 * Return: zero on success, non-zero on failure. 7734 */ 7735 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7736 { 7737 u32 saved_err = 0; 7738 u32 saved_uic_err = 0; 7739 int err = 0; 7740 unsigned long flags; 7741 int retries = MAX_HOST_RESET_RETRIES; 7742 7743 spin_lock_irqsave(hba->host->host_lock, flags); 7744 do { 7745 /* 7746 * This is a fresh start, cache and clear saved error first, 7747 * in case new error generated during reset and restore. 7748 */ 7749 saved_err |= hba->saved_err; 7750 saved_uic_err |= hba->saved_uic_err; 7751 hba->saved_err = 0; 7752 hba->saved_uic_err = 0; 7753 hba->force_reset = false; 7754 hba->ufshcd_state = UFSHCD_STATE_RESET; 7755 spin_unlock_irqrestore(hba->host->host_lock, flags); 7756 7757 /* Reset the attached device */ 7758 ufshcd_device_reset(hba); 7759 7760 err = ufshcd_host_reset_and_restore(hba); 7761 7762 spin_lock_irqsave(hba->host->host_lock, flags); 7763 if (err) 7764 continue; 7765 /* Do not exit unless operational or dead */ 7766 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7767 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7768 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7769 err = -EAGAIN; 7770 } while (err && --retries); 7771 7772 /* 7773 * Inform scsi mid-layer that we did reset and allow to handle 7774 * Unit Attention properly. 7775 */ 7776 scsi_report_bus_reset(hba->host, 0); 7777 if (err) { 7778 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7779 hba->saved_err |= saved_err; 7780 hba->saved_uic_err |= saved_uic_err; 7781 } 7782 spin_unlock_irqrestore(hba->host->host_lock, flags); 7783 7784 return err; 7785 } 7786 7787 /** 7788 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7789 * @cmd: SCSI command pointer 7790 * 7791 * Return: SUCCESS or FAILED. 7792 */ 7793 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7794 { 7795 int err = SUCCESS; 7796 unsigned long flags; 7797 struct ufs_hba *hba; 7798 7799 hba = shost_priv(cmd->device->host); 7800 7801 /* 7802 * If runtime PM sent SSU and got a timeout, scsi_error_handler is 7803 * stuck in this function waiting for flush_work(&hba->eh_work). And 7804 * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do 7805 * ufshcd_link_recovery instead of eh_work to prevent deadlock. 7806 */ 7807 if (hba->pm_op_in_progress) { 7808 if (ufshcd_link_recovery(hba)) 7809 err = FAILED; 7810 7811 return err; 7812 } 7813 7814 spin_lock_irqsave(hba->host->host_lock, flags); 7815 hba->force_reset = true; 7816 ufshcd_schedule_eh_work(hba); 7817 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7818 spin_unlock_irqrestore(hba->host->host_lock, flags); 7819 7820 flush_work(&hba->eh_work); 7821 7822 spin_lock_irqsave(hba->host->host_lock, flags); 7823 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7824 err = FAILED; 7825 spin_unlock_irqrestore(hba->host->host_lock, flags); 7826 7827 return err; 7828 } 7829 7830 /** 7831 * ufshcd_get_max_icc_level - calculate the ICC level 7832 * @sup_curr_uA: max. current supported by the regulator 7833 * @start_scan: row at the desc table to start scan from 7834 * @buff: power descriptor buffer 7835 * 7836 * Return: calculated max ICC level for specific regulator. 7837 */ 7838 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7839 const char *buff) 7840 { 7841 int i; 7842 int curr_uA; 7843 u16 data; 7844 u16 unit; 7845 7846 for (i = start_scan; i >= 0; i--) { 7847 data = get_unaligned_be16(&buff[2 * i]); 7848 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7849 ATTR_ICC_LVL_UNIT_OFFSET; 7850 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7851 switch (unit) { 7852 case UFSHCD_NANO_AMP: 7853 curr_uA = curr_uA / 1000; 7854 break; 7855 case UFSHCD_MILI_AMP: 7856 curr_uA = curr_uA * 1000; 7857 break; 7858 case UFSHCD_AMP: 7859 curr_uA = curr_uA * 1000 * 1000; 7860 break; 7861 case UFSHCD_MICRO_AMP: 7862 default: 7863 break; 7864 } 7865 if (sup_curr_uA >= curr_uA) 7866 break; 7867 } 7868 if (i < 0) { 7869 i = 0; 7870 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7871 } 7872 7873 return (u32)i; 7874 } 7875 7876 /** 7877 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7878 * In case regulators are not initialized we'll return 0 7879 * @hba: per-adapter instance 7880 * @desc_buf: power descriptor buffer to extract ICC levels from. 7881 * 7882 * Return: calculated ICC level. 7883 */ 7884 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7885 const u8 *desc_buf) 7886 { 7887 u32 icc_level = 0; 7888 7889 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7890 !hba->vreg_info.vccq2) { 7891 /* 7892 * Using dev_dbg to avoid messages during runtime PM to avoid 7893 * never-ending cycles of messages written back to storage by 7894 * user space causing runtime resume, causing more messages and 7895 * so on. 7896 */ 7897 dev_dbg(hba->dev, 7898 "%s: Regulator capability was not set, actvIccLevel=%d", 7899 __func__, icc_level); 7900 goto out; 7901 } 7902 7903 if (hba->vreg_info.vcc->max_uA) 7904 icc_level = ufshcd_get_max_icc_level( 7905 hba->vreg_info.vcc->max_uA, 7906 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7907 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7908 7909 if (hba->vreg_info.vccq->max_uA) 7910 icc_level = ufshcd_get_max_icc_level( 7911 hba->vreg_info.vccq->max_uA, 7912 icc_level, 7913 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7914 7915 if (hba->vreg_info.vccq2->max_uA) 7916 icc_level = ufshcd_get_max_icc_level( 7917 hba->vreg_info.vccq2->max_uA, 7918 icc_level, 7919 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7920 out: 7921 return icc_level; 7922 } 7923 7924 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7925 { 7926 int ret; 7927 u8 *desc_buf; 7928 u32 icc_level; 7929 7930 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7931 if (!desc_buf) 7932 return; 7933 7934 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7935 desc_buf, QUERY_DESC_MAX_SIZE); 7936 if (ret) { 7937 dev_err(hba->dev, 7938 "%s: Failed reading power descriptor ret = %d", 7939 __func__, ret); 7940 goto out; 7941 } 7942 7943 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7944 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7945 7946 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7947 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7948 7949 if (ret) 7950 dev_err(hba->dev, 7951 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7952 __func__, icc_level, ret); 7953 7954 out: 7955 kfree(desc_buf); 7956 } 7957 7958 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7959 { 7960 struct Scsi_Host *shost = sdev->host; 7961 7962 scsi_autopm_get_device(sdev); 7963 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7964 if (sdev->rpm_autosuspend) 7965 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7966 shost->rpm_autosuspend_delay); 7967 scsi_autopm_put_device(sdev); 7968 } 7969 7970 /** 7971 * ufshcd_scsi_add_wlus - Adds required W-LUs 7972 * @hba: per-adapter instance 7973 * 7974 * UFS device specification requires the UFS devices to support 4 well known 7975 * logical units: 7976 * "REPORT_LUNS" (address: 01h) 7977 * "UFS Device" (address: 50h) 7978 * "RPMB" (address: 44h) 7979 * "BOOT" (address: 30h) 7980 * UFS device's power management needs to be controlled by "POWER CONDITION" 7981 * field of SSU (START STOP UNIT) command. But this "power condition" field 7982 * will take effect only when its sent to "UFS device" well known logical unit 7983 * hence we require the scsi_device instance to represent this logical unit in 7984 * order for the UFS host driver to send the SSU command for power management. 7985 * 7986 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 7987 * Block) LU so user space process can control this LU. User space may also 7988 * want to have access to BOOT LU. 7989 * 7990 * This function adds scsi device instances for each of all well known LUs 7991 * (except "REPORT LUNS" LU). 7992 * 7993 * Return: zero on success (all required W-LUs are added successfully), 7994 * non-zero error value on failure (if failed to add any of the required W-LU). 7995 */ 7996 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 7997 { 7998 int ret = 0; 7999 struct scsi_device *sdev_boot, *sdev_rpmb; 8000 8001 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 8002 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 8003 if (IS_ERR(hba->ufs_device_wlun)) { 8004 ret = PTR_ERR(hba->ufs_device_wlun); 8005 hba->ufs_device_wlun = NULL; 8006 goto out; 8007 } 8008 scsi_device_put(hba->ufs_device_wlun); 8009 8010 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 8011 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 8012 if (IS_ERR(sdev_rpmb)) { 8013 ret = PTR_ERR(sdev_rpmb); 8014 goto remove_ufs_device_wlun; 8015 } 8016 ufshcd_blk_pm_runtime_init(sdev_rpmb); 8017 scsi_device_put(sdev_rpmb); 8018 8019 sdev_boot = __scsi_add_device(hba->host, 0, 0, 8020 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 8021 if (IS_ERR(sdev_boot)) { 8022 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 8023 } else { 8024 ufshcd_blk_pm_runtime_init(sdev_boot); 8025 scsi_device_put(sdev_boot); 8026 } 8027 goto out; 8028 8029 remove_ufs_device_wlun: 8030 scsi_remove_device(hba->ufs_device_wlun); 8031 out: 8032 return ret; 8033 } 8034 8035 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 8036 { 8037 struct ufs_dev_info *dev_info = &hba->dev_info; 8038 u8 lun; 8039 u32 d_lu_wb_buf_alloc; 8040 u32 ext_ufs_feature; 8041 8042 if (!ufshcd_is_wb_allowed(hba)) 8043 return; 8044 8045 /* 8046 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 8047 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 8048 * enabled 8049 */ 8050 if (!(dev_info->wspecversion >= 0x310 || 8051 dev_info->wspecversion == 0x220 || 8052 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 8053 goto wb_disabled; 8054 8055 ext_ufs_feature = get_unaligned_be32(desc_buf + 8056 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8057 8058 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 8059 goto wb_disabled; 8060 8061 /* 8062 * WB may be supported but not configured while provisioning. The spec 8063 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 8064 * buffer configured. 8065 */ 8066 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 8067 8068 dev_info->b_presrv_uspc_en = 8069 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 8070 8071 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 8072 if (!get_unaligned_be32(desc_buf + 8073 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 8074 goto wb_disabled; 8075 } else { 8076 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 8077 d_lu_wb_buf_alloc = 0; 8078 ufshcd_read_unit_desc_param(hba, 8079 lun, 8080 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 8081 (u8 *)&d_lu_wb_buf_alloc, 8082 sizeof(d_lu_wb_buf_alloc)); 8083 if (d_lu_wb_buf_alloc) { 8084 dev_info->wb_dedicated_lu = lun; 8085 break; 8086 } 8087 } 8088 8089 if (!d_lu_wb_buf_alloc) 8090 goto wb_disabled; 8091 } 8092 8093 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8094 goto wb_disabled; 8095 8096 return; 8097 8098 wb_disabled: 8099 hba->caps &= ~UFSHCD_CAP_WB_EN; 8100 } 8101 8102 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8103 { 8104 struct ufs_dev_info *dev_info = &hba->dev_info; 8105 u32 ext_ufs_feature; 8106 u8 mask = 0; 8107 8108 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8109 return; 8110 8111 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8112 8113 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8114 mask |= MASK_EE_TOO_LOW_TEMP; 8115 8116 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8117 mask |= MASK_EE_TOO_HIGH_TEMP; 8118 8119 if (mask) { 8120 ufshcd_enable_ee(hba, mask); 8121 ufs_hwmon_probe(hba, mask); 8122 } 8123 } 8124 8125 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8126 { 8127 struct ufs_dev_info *dev_info = &hba->dev_info; 8128 u32 ext_ufs_feature; 8129 u32 ext_iid_en = 0; 8130 int err; 8131 8132 /* Only UFS-4.0 and above may support EXT_IID */ 8133 if (dev_info->wspecversion < 0x400) 8134 goto out; 8135 8136 ext_ufs_feature = get_unaligned_be32(desc_buf + 8137 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8138 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8139 goto out; 8140 8141 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8142 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8143 if (err) 8144 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8145 8146 out: 8147 dev_info->b_ext_iid_en = ext_iid_en; 8148 } 8149 8150 static void ufshcd_set_rtt(struct ufs_hba *hba) 8151 { 8152 struct ufs_dev_info *dev_info = &hba->dev_info; 8153 u32 rtt = 0; 8154 u32 dev_rtt = 0; 8155 int host_rtt_cap = hba->vops && hba->vops->max_num_rtt ? 8156 hba->vops->max_num_rtt : hba->nortt; 8157 8158 /* RTT override makes sense only for UFS-4.0 and above */ 8159 if (dev_info->wspecversion < 0x400) 8160 return; 8161 8162 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8163 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &dev_rtt)) { 8164 dev_err(hba->dev, "failed reading bMaxNumOfRTT\n"); 8165 return; 8166 } 8167 8168 /* do not override if it was already written */ 8169 if (dev_rtt != DEFAULT_MAX_NUM_RTT) 8170 return; 8171 8172 rtt = min_t(int, dev_info->rtt_cap, host_rtt_cap); 8173 8174 if (rtt == dev_rtt) 8175 return; 8176 8177 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8178 QUERY_ATTR_IDN_MAX_NUM_OF_RTT, 0, 0, &rtt)) 8179 dev_err(hba->dev, "failed writing bMaxNumOfRTT\n"); 8180 } 8181 8182 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8183 const struct ufs_dev_quirk *fixups) 8184 { 8185 const struct ufs_dev_quirk *f; 8186 struct ufs_dev_info *dev_info = &hba->dev_info; 8187 8188 if (!fixups) 8189 return; 8190 8191 for (f = fixups; f->quirk; f++) { 8192 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8193 f->wmanufacturerid == UFS_ANY_VENDOR) && 8194 ((dev_info->model && 8195 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8196 !strcmp(f->model, UFS_ANY_MODEL))) 8197 hba->dev_quirks |= f->quirk; 8198 } 8199 } 8200 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8201 8202 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8203 { 8204 /* fix by general quirk table */ 8205 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8206 8207 /* allow vendors to fix quirks */ 8208 ufshcd_vops_fixup_dev_quirks(hba); 8209 } 8210 8211 static void ufshcd_update_rtc(struct ufs_hba *hba) 8212 { 8213 struct timespec64 ts64; 8214 int err; 8215 u32 val; 8216 8217 ktime_get_real_ts64(&ts64); 8218 8219 if (ts64.tv_sec < hba->dev_info.rtc_time_baseline) { 8220 dev_warn_once(hba->dev, "%s: Current time precedes previous setting!\n", __func__); 8221 return; 8222 } 8223 8224 /* 8225 * The Absolute RTC mode has a 136-year limit, spanning from 2010 to 2146. If a time beyond 8226 * 2146 is required, it is recommended to choose the relative RTC mode. 8227 */ 8228 val = ts64.tv_sec - hba->dev_info.rtc_time_baseline; 8229 8230 /* Skip update RTC if RPM state is not RPM_ACTIVE */ 8231 if (ufshcd_rpm_get_if_active(hba) <= 0) 8232 return; 8233 8234 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_SECONDS_PASSED, 8235 0, 0, &val); 8236 ufshcd_rpm_put_sync(hba); 8237 8238 if (err) 8239 dev_err(hba->dev, "%s: Failed to update rtc %d\n", __func__, err); 8240 else if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE) 8241 hba->dev_info.rtc_time_baseline = ts64.tv_sec; 8242 } 8243 8244 static void ufshcd_rtc_work(struct work_struct *work) 8245 { 8246 struct ufs_hba *hba; 8247 8248 hba = container_of(to_delayed_work(work), struct ufs_hba, ufs_rtc_update_work); 8249 8250 /* Update RTC only when there are no requests in progress and UFSHCI is operational */ 8251 if (!ufshcd_is_ufs_dev_busy(hba) && hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) 8252 ufshcd_update_rtc(hba); 8253 8254 if (ufshcd_is_ufs_dev_active(hba) && hba->dev_info.rtc_update_period) 8255 schedule_delayed_work(&hba->ufs_rtc_update_work, 8256 msecs_to_jiffies(hba->dev_info.rtc_update_period)); 8257 } 8258 8259 static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf) 8260 { 8261 u16 periodic_rtc_update = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_FRQ_RTC]); 8262 struct ufs_dev_info *dev_info = &hba->dev_info; 8263 8264 if (periodic_rtc_update & UFS_RTC_TIME_BASELINE) { 8265 dev_info->rtc_type = UFS_RTC_ABSOLUTE; 8266 8267 /* 8268 * The concept of measuring time in Linux as the number of seconds elapsed since 8269 * 00:00:00 UTC on January 1, 1970, and UFS ABS RTC is elapsed from January 1st 8270 * 2010 00:00, here we need to adjust ABS baseline. 8271 */ 8272 dev_info->rtc_time_baseline = mktime64(2010, 1, 1, 0, 0, 0) - 8273 mktime64(1970, 1, 1, 0, 0, 0); 8274 } else { 8275 dev_info->rtc_type = UFS_RTC_RELATIVE; 8276 dev_info->rtc_time_baseline = 0; 8277 } 8278 8279 /* 8280 * We ignore TIME_PERIOD defined in wPeriodicRTCUpdate because Spec does not clearly state 8281 * how to calculate the specific update period for each time unit. And we disable periodic 8282 * RTC update work, let user configure by sysfs node according to specific circumstance. 8283 */ 8284 dev_info->rtc_update_period = 0; 8285 } 8286 8287 static int ufs_get_device_desc(struct ufs_hba *hba) 8288 { 8289 int err; 8290 u8 model_index; 8291 u8 *desc_buf; 8292 struct ufs_dev_info *dev_info = &hba->dev_info; 8293 8294 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8295 if (!desc_buf) { 8296 err = -ENOMEM; 8297 goto out; 8298 } 8299 8300 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8301 QUERY_DESC_MAX_SIZE); 8302 if (err) { 8303 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8304 __func__, err); 8305 goto out; 8306 } 8307 8308 /* 8309 * getting vendor (manufacturerID) and Bank Index in big endian 8310 * format 8311 */ 8312 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8313 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8314 8315 /* getting Specification Version in big endian format */ 8316 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8317 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8318 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8319 8320 dev_info->rtt_cap = desc_buf[DEVICE_DESC_PARAM_RTT_CAP]; 8321 8322 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8323 8324 err = ufshcd_read_string_desc(hba, model_index, 8325 &dev_info->model, SD_ASCII_STD); 8326 if (err < 0) { 8327 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8328 __func__, err); 8329 goto out; 8330 } 8331 8332 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8333 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8334 8335 ufs_fixup_device_setup(hba); 8336 8337 ufshcd_wb_probe(hba, desc_buf); 8338 8339 ufshcd_temp_notif_probe(hba, desc_buf); 8340 8341 ufs_init_rtc(hba, desc_buf); 8342 8343 if (hba->ext_iid_sup) 8344 ufshcd_ext_iid_probe(hba, desc_buf); 8345 8346 /* 8347 * ufshcd_read_string_desc returns size of the string 8348 * reset the error value 8349 */ 8350 err = 0; 8351 8352 out: 8353 kfree(desc_buf); 8354 return err; 8355 } 8356 8357 static void ufs_put_device_desc(struct ufs_hba *hba) 8358 { 8359 struct ufs_dev_info *dev_info = &hba->dev_info; 8360 8361 kfree(dev_info->model); 8362 dev_info->model = NULL; 8363 } 8364 8365 /** 8366 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8367 * less than device PA_TACTIVATE time. 8368 * @hba: per-adapter instance 8369 * 8370 * Some UFS devices require host PA_TACTIVATE to be lower than device 8371 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8372 * for such devices. 8373 * 8374 * Return: zero on success, non-zero error value on failure. 8375 */ 8376 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8377 { 8378 int ret = 0; 8379 u32 granularity, peer_granularity; 8380 u32 pa_tactivate, peer_pa_tactivate; 8381 u32 pa_tactivate_us, peer_pa_tactivate_us; 8382 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8383 8384 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8385 &granularity); 8386 if (ret) 8387 goto out; 8388 8389 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8390 &peer_granularity); 8391 if (ret) 8392 goto out; 8393 8394 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8395 (granularity > PA_GRANULARITY_MAX_VAL)) { 8396 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8397 __func__, granularity); 8398 return -EINVAL; 8399 } 8400 8401 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8402 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8403 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8404 __func__, peer_granularity); 8405 return -EINVAL; 8406 } 8407 8408 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8409 if (ret) 8410 goto out; 8411 8412 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8413 &peer_pa_tactivate); 8414 if (ret) 8415 goto out; 8416 8417 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8418 peer_pa_tactivate_us = peer_pa_tactivate * 8419 gran_to_us_table[peer_granularity - 1]; 8420 8421 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8422 u32 new_peer_pa_tactivate; 8423 8424 new_peer_pa_tactivate = pa_tactivate_us / 8425 gran_to_us_table[peer_granularity - 1]; 8426 new_peer_pa_tactivate++; 8427 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8428 new_peer_pa_tactivate); 8429 } 8430 8431 out: 8432 return ret; 8433 } 8434 8435 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8436 { 8437 ufshcd_vops_apply_dev_quirks(hba); 8438 8439 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8440 /* set 1ms timeout for PA_TACTIVATE */ 8441 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8442 8443 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8444 ufshcd_quirk_tune_host_pa_tactivate(hba); 8445 } 8446 8447 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8448 { 8449 hba->ufs_stats.hibern8_exit_cnt = 0; 8450 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8451 hba->req_abort_count = 0; 8452 } 8453 8454 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8455 { 8456 int err; 8457 u8 *desc_buf; 8458 8459 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8460 if (!desc_buf) { 8461 err = -ENOMEM; 8462 goto out; 8463 } 8464 8465 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8466 desc_buf, QUERY_DESC_MAX_SIZE); 8467 if (err) { 8468 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8469 __func__, err); 8470 goto out; 8471 } 8472 8473 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8474 hba->dev_info.max_lu_supported = 32; 8475 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8476 hba->dev_info.max_lu_supported = 8; 8477 8478 out: 8479 kfree(desc_buf); 8480 return err; 8481 } 8482 8483 struct ufs_ref_clk { 8484 unsigned long freq_hz; 8485 enum ufs_ref_clk_freq val; 8486 }; 8487 8488 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8489 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8490 {26000000, REF_CLK_FREQ_26_MHZ}, 8491 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8492 {52000000, REF_CLK_FREQ_52_MHZ}, 8493 {0, REF_CLK_FREQ_INVAL}, 8494 }; 8495 8496 static enum ufs_ref_clk_freq 8497 ufs_get_bref_clk_from_hz(unsigned long freq) 8498 { 8499 int i; 8500 8501 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8502 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8503 return ufs_ref_clk_freqs[i].val; 8504 8505 return REF_CLK_FREQ_INVAL; 8506 } 8507 8508 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8509 { 8510 unsigned long freq; 8511 8512 freq = clk_get_rate(refclk); 8513 8514 hba->dev_ref_clk_freq = 8515 ufs_get_bref_clk_from_hz(freq); 8516 8517 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8518 dev_err(hba->dev, 8519 "invalid ref_clk setting = %ld\n", freq); 8520 } 8521 8522 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8523 { 8524 int err; 8525 u32 ref_clk; 8526 u32 freq = hba->dev_ref_clk_freq; 8527 8528 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8529 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8530 8531 if (err) { 8532 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8533 err); 8534 goto out; 8535 } 8536 8537 if (ref_clk == freq) 8538 goto out; /* nothing to update */ 8539 8540 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8541 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8542 8543 if (err) { 8544 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8545 ufs_ref_clk_freqs[freq].freq_hz); 8546 goto out; 8547 } 8548 8549 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8550 ufs_ref_clk_freqs[freq].freq_hz); 8551 8552 out: 8553 return err; 8554 } 8555 8556 static int ufshcd_device_params_init(struct ufs_hba *hba) 8557 { 8558 bool flag; 8559 int ret; 8560 8561 /* Init UFS geometry descriptor related parameters */ 8562 ret = ufshcd_device_geo_params_init(hba); 8563 if (ret) 8564 goto out; 8565 8566 /* Check and apply UFS device quirks */ 8567 ret = ufs_get_device_desc(hba); 8568 if (ret) { 8569 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8570 __func__, ret); 8571 goto out; 8572 } 8573 8574 ufshcd_set_rtt(hba); 8575 8576 ufshcd_get_ref_clk_gating_wait(hba); 8577 8578 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8579 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8580 hba->dev_info.f_power_on_wp_en = flag; 8581 8582 /* Probe maximum power mode co-supported by both UFS host and device */ 8583 if (ufshcd_get_max_pwr_mode(hba)) 8584 dev_err(hba->dev, 8585 "%s: Failed getting max supported power mode\n", 8586 __func__); 8587 out: 8588 return ret; 8589 } 8590 8591 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8592 { 8593 int err; 8594 struct ufs_query_req *request = NULL; 8595 struct ufs_query_res *response = NULL; 8596 struct ufs_dev_info *dev_info = &hba->dev_info; 8597 struct utp_upiu_query_v4_0 *upiu_data; 8598 8599 if (dev_info->wspecversion < 0x400) 8600 return; 8601 8602 ufshcd_dev_man_lock(hba); 8603 8604 ufshcd_init_query(hba, &request, &response, 8605 UPIU_QUERY_OPCODE_WRITE_ATTR, 8606 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8607 8608 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8609 8610 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8611 8612 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8613 8614 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8615 8616 if (err) 8617 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8618 __func__, err); 8619 8620 ufshcd_dev_man_unlock(hba); 8621 } 8622 8623 /** 8624 * ufshcd_add_lus - probe and add UFS logical units 8625 * @hba: per-adapter instance 8626 * 8627 * Return: 0 upon success; < 0 upon failure. 8628 */ 8629 static int ufshcd_add_lus(struct ufs_hba *hba) 8630 { 8631 int ret; 8632 8633 /* Add required well known logical units to scsi mid layer */ 8634 ret = ufshcd_scsi_add_wlus(hba); 8635 if (ret) 8636 goto out; 8637 8638 /* Initialize devfreq after UFS device is detected */ 8639 if (ufshcd_is_clkscaling_supported(hba)) { 8640 memcpy(&hba->clk_scaling.saved_pwr_info, 8641 &hba->pwr_info, 8642 sizeof(struct ufs_pa_layer_attr)); 8643 hba->clk_scaling.is_allowed = true; 8644 8645 ret = ufshcd_devfreq_init(hba); 8646 if (ret) 8647 goto out; 8648 8649 hba->clk_scaling.is_enabled = true; 8650 ufshcd_init_clk_scaling_sysfs(hba); 8651 } 8652 8653 ufs_bsg_probe(hba); 8654 scsi_scan_host(hba->host); 8655 8656 out: 8657 return ret; 8658 } 8659 8660 /* SDB - Single Doorbell */ 8661 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8662 { 8663 size_t ucdl_size, utrdl_size; 8664 8665 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8666 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8667 hba->ucdl_dma_addr); 8668 8669 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8670 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8671 hba->utrdl_dma_addr); 8672 8673 devm_kfree(hba->dev, hba->lrb); 8674 } 8675 8676 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8677 { 8678 int ret; 8679 int old_nutrs = hba->nutrs; 8680 8681 ret = ufshcd_mcq_decide_queue_depth(hba); 8682 if (ret < 0) 8683 return ret; 8684 8685 hba->nutrs = ret; 8686 ret = ufshcd_mcq_init(hba); 8687 if (ret) 8688 goto err; 8689 8690 /* 8691 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8692 * Number of supported tags in MCQ mode may be larger than SDB mode. 8693 */ 8694 if (hba->nutrs != old_nutrs) { 8695 ufshcd_release_sdb_queue(hba, old_nutrs); 8696 ret = ufshcd_memory_alloc(hba); 8697 if (ret) 8698 goto err; 8699 ufshcd_host_memory_configure(hba); 8700 } 8701 8702 ret = ufshcd_mcq_memory_alloc(hba); 8703 if (ret) 8704 goto err; 8705 8706 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8707 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8708 8709 return 0; 8710 err: 8711 hba->nutrs = old_nutrs; 8712 return ret; 8713 } 8714 8715 static void ufshcd_config_mcq(struct ufs_hba *hba) 8716 { 8717 int ret; 8718 u32 intrs; 8719 8720 ret = ufshcd_mcq_vops_config_esi(hba); 8721 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8722 8723 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8724 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8725 intrs &= ~MCQ_CQ_EVENT_STATUS; 8726 ufshcd_enable_intr(hba, intrs); 8727 ufshcd_mcq_make_queues_operational(hba); 8728 ufshcd_mcq_config_mac(hba, hba->nutrs); 8729 8730 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8731 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8732 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8733 hba->nutrs); 8734 } 8735 8736 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8737 { 8738 int ret; 8739 struct Scsi_Host *host = hba->host; 8740 8741 hba->ufshcd_state = UFSHCD_STATE_RESET; 8742 8743 ret = ufshcd_link_startup(hba); 8744 if (ret) 8745 return ret; 8746 8747 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8748 return ret; 8749 8750 /* Debug counters initialization */ 8751 ufshcd_clear_dbg_ufs_stats(hba); 8752 8753 /* UniPro link is active now */ 8754 ufshcd_set_link_active(hba); 8755 8756 /* Reconfigure MCQ upon reset */ 8757 if (hba->mcq_enabled && !init_dev_params) { 8758 ufshcd_config_mcq(hba); 8759 ufshcd_mcq_enable(hba); 8760 } 8761 8762 /* Verify device initialization by sending NOP OUT UPIU */ 8763 ret = ufshcd_verify_dev_init(hba); 8764 if (ret) 8765 return ret; 8766 8767 /* Initiate UFS initialization, and waiting until completion */ 8768 ret = ufshcd_complete_dev_init(hba); 8769 if (ret) 8770 return ret; 8771 8772 /* 8773 * Initialize UFS device parameters used by driver, these 8774 * parameters are associated with UFS descriptors. 8775 */ 8776 if (init_dev_params) { 8777 ret = ufshcd_device_params_init(hba); 8778 if (ret) 8779 return ret; 8780 if (is_mcq_supported(hba) && !hba->scsi_host_added) { 8781 ufshcd_mcq_enable(hba); 8782 ret = ufshcd_alloc_mcq(hba); 8783 if (!ret) { 8784 ufshcd_config_mcq(hba); 8785 } else { 8786 /* Continue with SDB mode */ 8787 ufshcd_mcq_disable(hba); 8788 use_mcq_mode = false; 8789 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 8790 ret); 8791 } 8792 ret = scsi_add_host(host, hba->dev); 8793 if (ret) { 8794 dev_err(hba->dev, "scsi_add_host failed\n"); 8795 return ret; 8796 } 8797 hba->scsi_host_added = true; 8798 } else if (is_mcq_supported(hba)) { 8799 /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */ 8800 ufshcd_config_mcq(hba); 8801 ufshcd_mcq_enable(hba); 8802 } 8803 } 8804 8805 ufshcd_tune_unipro_params(hba); 8806 8807 /* UFS device is also active now */ 8808 ufshcd_set_ufs_dev_active(hba); 8809 ufshcd_force_reset_auto_bkops(hba); 8810 8811 ufshcd_set_timestamp_attr(hba); 8812 schedule_delayed_work(&hba->ufs_rtc_update_work, 8813 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 8814 8815 /* Gear up to HS gear if supported */ 8816 if (hba->max_pwr_info.is_valid) { 8817 /* 8818 * Set the right value to bRefClkFreq before attempting to 8819 * switch to HS gears. 8820 */ 8821 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8822 ufshcd_set_dev_ref_clk(hba); 8823 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8824 if (ret) { 8825 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8826 __func__, ret); 8827 return ret; 8828 } 8829 } 8830 8831 return 0; 8832 } 8833 8834 /** 8835 * ufshcd_probe_hba - probe hba to detect device and initialize it 8836 * @hba: per-adapter instance 8837 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8838 * 8839 * Execute link-startup and verify device initialization 8840 * 8841 * Return: 0 upon success; < 0 upon failure. 8842 */ 8843 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8844 { 8845 ktime_t start = ktime_get(); 8846 unsigned long flags; 8847 int ret; 8848 8849 ret = ufshcd_device_init(hba, init_dev_params); 8850 if (ret) 8851 goto out; 8852 8853 if (!hba->pm_op_in_progress && 8854 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8855 /* Reset the device and controller before doing reinit */ 8856 ufshcd_device_reset(hba); 8857 ufs_put_device_desc(hba); 8858 ufshcd_hba_stop(hba); 8859 ufshcd_vops_reinit_notify(hba); 8860 ret = ufshcd_hba_enable(hba); 8861 if (ret) { 8862 dev_err(hba->dev, "Host controller enable failed\n"); 8863 ufshcd_print_evt_hist(hba); 8864 ufshcd_print_host_state(hba); 8865 goto out; 8866 } 8867 8868 /* Reinit the device */ 8869 ret = ufshcd_device_init(hba, init_dev_params); 8870 if (ret) 8871 goto out; 8872 } 8873 8874 ufshcd_print_pwr_info(hba); 8875 8876 /* 8877 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8878 * and for removable UFS card as well, hence always set the parameter. 8879 * Note: Error handler may issue the device reset hence resetting 8880 * bActiveICCLevel as well so it is always safe to set this here. 8881 */ 8882 ufshcd_set_active_icc_lvl(hba); 8883 8884 /* Enable UFS Write Booster if supported */ 8885 ufshcd_configure_wb(hba); 8886 8887 if (hba->ee_usr_mask) 8888 ufshcd_write_ee_control(hba); 8889 ufshcd_configure_auto_hibern8(hba); 8890 8891 out: 8892 spin_lock_irqsave(hba->host->host_lock, flags); 8893 if (ret) 8894 hba->ufshcd_state = UFSHCD_STATE_ERROR; 8895 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 8896 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 8897 spin_unlock_irqrestore(hba->host->host_lock, flags); 8898 8899 trace_ufshcd_init(dev_name(hba->dev), ret, 8900 ktime_to_us(ktime_sub(ktime_get(), start)), 8901 hba->curr_dev_pwr_mode, hba->uic_link_state); 8902 return ret; 8903 } 8904 8905 /** 8906 * ufshcd_async_scan - asynchronous execution for probing hba 8907 * @data: data pointer to pass to this function 8908 * @cookie: cookie data 8909 */ 8910 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8911 { 8912 struct ufs_hba *hba = (struct ufs_hba *)data; 8913 int ret; 8914 8915 down(&hba->host_sem); 8916 /* Initialize hba, detect and initialize UFS device */ 8917 ret = ufshcd_probe_hba(hba, true); 8918 up(&hba->host_sem); 8919 if (ret) 8920 goto out; 8921 8922 /* Probe and add UFS logical units */ 8923 ret = ufshcd_add_lus(hba); 8924 8925 out: 8926 pm_runtime_put_sync(hba->dev); 8927 8928 if (ret) 8929 dev_err(hba->dev, "%s failed: %d\n", __func__, ret); 8930 } 8931 8932 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8933 { 8934 struct ufs_hba *hba = shost_priv(scmd->device->host); 8935 8936 if (!hba->system_suspending) { 8937 /* Activate the error handler in the SCSI core. */ 8938 return SCSI_EH_NOT_HANDLED; 8939 } 8940 8941 /* 8942 * If we get here we know that no TMFs are outstanding and also that 8943 * the only pending command is a START STOP UNIT command. Handle the 8944 * timeout of that command directly to prevent a deadlock between 8945 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8946 */ 8947 ufshcd_link_recovery(hba); 8948 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8949 __func__, hba->outstanding_tasks); 8950 8951 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8952 } 8953 8954 static const struct attribute_group *ufshcd_driver_groups[] = { 8955 &ufs_sysfs_unit_descriptor_group, 8956 &ufs_sysfs_lun_attributes_group, 8957 NULL, 8958 }; 8959 8960 static struct ufs_hba_variant_params ufs_hba_vps = { 8961 .hba_enable_delay_us = 1000, 8962 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8963 .devfreq_profile.polling_ms = 100, 8964 .devfreq_profile.target = ufshcd_devfreq_target, 8965 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8966 .ondemand_data.upthreshold = 70, 8967 .ondemand_data.downdifferential = 5, 8968 }; 8969 8970 static const struct scsi_host_template ufshcd_driver_template = { 8971 .module = THIS_MODULE, 8972 .name = UFSHCD, 8973 .proc_name = UFSHCD, 8974 .map_queues = ufshcd_map_queues, 8975 .queuecommand = ufshcd_queuecommand, 8976 .mq_poll = ufshcd_poll, 8977 .slave_alloc = ufshcd_slave_alloc, 8978 .device_configure = ufshcd_device_configure, 8979 .slave_destroy = ufshcd_slave_destroy, 8980 .change_queue_depth = ufshcd_change_queue_depth, 8981 .eh_abort_handler = ufshcd_abort, 8982 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8983 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8984 .eh_timed_out = ufshcd_eh_timed_out, 8985 .this_id = -1, 8986 .sg_tablesize = SG_ALL, 8987 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8988 .max_sectors = SZ_1M / SECTOR_SIZE, 8989 .max_host_blocked = 1, 8990 .track_queue_depth = 1, 8991 .skip_settle_delay = 1, 8992 .sdev_groups = ufshcd_driver_groups, 8993 }; 8994 8995 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8996 int ua) 8997 { 8998 int ret; 8999 9000 if (!vreg) 9001 return 0; 9002 9003 /* 9004 * "set_load" operation shall be required on those regulators 9005 * which specifically configured current limitation. Otherwise 9006 * zero max_uA may cause unexpected behavior when regulator is 9007 * enabled or set as high power mode. 9008 */ 9009 if (!vreg->max_uA) 9010 return 0; 9011 9012 ret = regulator_set_load(vreg->reg, ua); 9013 if (ret < 0) { 9014 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 9015 __func__, vreg->name, ua, ret); 9016 } 9017 9018 return ret; 9019 } 9020 9021 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 9022 struct ufs_vreg *vreg) 9023 { 9024 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 9025 } 9026 9027 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 9028 struct ufs_vreg *vreg) 9029 { 9030 if (!vreg) 9031 return 0; 9032 9033 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 9034 } 9035 9036 static int ufshcd_config_vreg(struct device *dev, 9037 struct ufs_vreg *vreg, bool on) 9038 { 9039 if (regulator_count_voltages(vreg->reg) <= 0) 9040 return 0; 9041 9042 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 9043 } 9044 9045 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 9046 { 9047 int ret = 0; 9048 9049 if (!vreg || vreg->enabled) 9050 goto out; 9051 9052 ret = ufshcd_config_vreg(dev, vreg, true); 9053 if (!ret) 9054 ret = regulator_enable(vreg->reg); 9055 9056 if (!ret) 9057 vreg->enabled = true; 9058 else 9059 dev_err(dev, "%s: %s enable failed, err=%d\n", 9060 __func__, vreg->name, ret); 9061 out: 9062 return ret; 9063 } 9064 9065 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 9066 { 9067 int ret = 0; 9068 9069 if (!vreg || !vreg->enabled || vreg->always_on) 9070 goto out; 9071 9072 ret = regulator_disable(vreg->reg); 9073 9074 if (!ret) { 9075 /* ignore errors on applying disable config */ 9076 ufshcd_config_vreg(dev, vreg, false); 9077 vreg->enabled = false; 9078 } else { 9079 dev_err(dev, "%s: %s disable failed, err=%d\n", 9080 __func__, vreg->name, ret); 9081 } 9082 out: 9083 return ret; 9084 } 9085 9086 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 9087 { 9088 int ret = 0; 9089 struct device *dev = hba->dev; 9090 struct ufs_vreg_info *info = &hba->vreg_info; 9091 9092 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 9093 if (ret) 9094 goto out; 9095 9096 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 9097 if (ret) 9098 goto out; 9099 9100 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 9101 9102 out: 9103 if (ret) { 9104 ufshcd_toggle_vreg(dev, info->vccq2, false); 9105 ufshcd_toggle_vreg(dev, info->vccq, false); 9106 ufshcd_toggle_vreg(dev, info->vcc, false); 9107 } 9108 return ret; 9109 } 9110 9111 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9112 { 9113 struct ufs_vreg_info *info = &hba->vreg_info; 9114 9115 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9116 } 9117 9118 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9119 { 9120 int ret = 0; 9121 9122 if (!vreg) 9123 goto out; 9124 9125 vreg->reg = devm_regulator_get(dev, vreg->name); 9126 if (IS_ERR(vreg->reg)) { 9127 ret = PTR_ERR(vreg->reg); 9128 dev_err(dev, "%s: %s get failed, err=%d\n", 9129 __func__, vreg->name, ret); 9130 } 9131 out: 9132 return ret; 9133 } 9134 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9135 9136 static int ufshcd_init_vreg(struct ufs_hba *hba) 9137 { 9138 int ret = 0; 9139 struct device *dev = hba->dev; 9140 struct ufs_vreg_info *info = &hba->vreg_info; 9141 9142 ret = ufshcd_get_vreg(dev, info->vcc); 9143 if (ret) 9144 goto out; 9145 9146 ret = ufshcd_get_vreg(dev, info->vccq); 9147 if (!ret) 9148 ret = ufshcd_get_vreg(dev, info->vccq2); 9149 out: 9150 return ret; 9151 } 9152 9153 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9154 { 9155 struct ufs_vreg_info *info = &hba->vreg_info; 9156 9157 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9158 } 9159 9160 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9161 { 9162 int ret = 0; 9163 struct ufs_clk_info *clki; 9164 struct list_head *head = &hba->clk_list_head; 9165 unsigned long flags; 9166 ktime_t start = ktime_get(); 9167 bool clk_state_changed = false; 9168 9169 if (list_empty(head)) 9170 goto out; 9171 9172 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9173 if (ret) 9174 return ret; 9175 9176 list_for_each_entry(clki, head, list) { 9177 if (!IS_ERR_OR_NULL(clki->clk)) { 9178 /* 9179 * Don't disable clocks which are needed 9180 * to keep the link active. 9181 */ 9182 if (ufshcd_is_link_active(hba) && 9183 clki->keep_link_active) 9184 continue; 9185 9186 clk_state_changed = on ^ clki->enabled; 9187 if (on && !clki->enabled) { 9188 ret = clk_prepare_enable(clki->clk); 9189 if (ret) { 9190 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9191 __func__, clki->name, ret); 9192 goto out; 9193 } 9194 } else if (!on && clki->enabled) { 9195 clk_disable_unprepare(clki->clk); 9196 } 9197 clki->enabled = on; 9198 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9199 clki->name, on ? "en" : "dis"); 9200 } 9201 } 9202 9203 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9204 if (ret) 9205 return ret; 9206 9207 if (!ufshcd_is_clkscaling_supported(hba)) 9208 ufshcd_pm_qos_update(hba, on); 9209 out: 9210 if (ret) { 9211 list_for_each_entry(clki, head, list) { 9212 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9213 clk_disable_unprepare(clki->clk); 9214 } 9215 } else if (!ret && on) { 9216 spin_lock_irqsave(hba->host->host_lock, flags); 9217 hba->clk_gating.state = CLKS_ON; 9218 trace_ufshcd_clk_gating(dev_name(hba->dev), 9219 hba->clk_gating.state); 9220 spin_unlock_irqrestore(hba->host->host_lock, flags); 9221 } 9222 9223 if (clk_state_changed) 9224 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9225 (on ? "on" : "off"), 9226 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9227 return ret; 9228 } 9229 9230 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9231 { 9232 u32 freq; 9233 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9234 9235 if (ret) { 9236 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9237 return REF_CLK_FREQ_INVAL; 9238 } 9239 9240 return ufs_get_bref_clk_from_hz(freq); 9241 } 9242 9243 static int ufshcd_init_clocks(struct ufs_hba *hba) 9244 { 9245 int ret = 0; 9246 struct ufs_clk_info *clki; 9247 struct device *dev = hba->dev; 9248 struct list_head *head = &hba->clk_list_head; 9249 9250 if (list_empty(head)) 9251 goto out; 9252 9253 list_for_each_entry(clki, head, list) { 9254 if (!clki->name) 9255 continue; 9256 9257 clki->clk = devm_clk_get(dev, clki->name); 9258 if (IS_ERR(clki->clk)) { 9259 ret = PTR_ERR(clki->clk); 9260 dev_err(dev, "%s: %s clk get failed, %d\n", 9261 __func__, clki->name, ret); 9262 goto out; 9263 } 9264 9265 /* 9266 * Parse device ref clk freq as per device tree "ref_clk". 9267 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9268 * in ufshcd_alloc_host(). 9269 */ 9270 if (!strcmp(clki->name, "ref_clk")) 9271 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9272 9273 if (clki->max_freq) { 9274 ret = clk_set_rate(clki->clk, clki->max_freq); 9275 if (ret) { 9276 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9277 __func__, clki->name, 9278 clki->max_freq, ret); 9279 goto out; 9280 } 9281 clki->curr_freq = clki->max_freq; 9282 } 9283 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9284 clki->name, clk_get_rate(clki->clk)); 9285 } 9286 9287 /* Set Max. frequency for all clocks */ 9288 if (hba->use_pm_opp) { 9289 ret = ufshcd_opp_set_rate(hba, ULONG_MAX); 9290 if (ret) { 9291 dev_err(hba->dev, "%s: failed to set OPP: %d", __func__, 9292 ret); 9293 goto out; 9294 } 9295 } 9296 9297 out: 9298 return ret; 9299 } 9300 9301 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9302 { 9303 int err = 0; 9304 9305 if (!hba->vops) 9306 goto out; 9307 9308 err = ufshcd_vops_init(hba); 9309 if (err) 9310 dev_err_probe(hba->dev, err, 9311 "%s: variant %s init failed with err %d\n", 9312 __func__, ufshcd_get_var_name(hba), err); 9313 out: 9314 return err; 9315 } 9316 9317 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9318 { 9319 if (!hba->vops) 9320 return; 9321 9322 ufshcd_vops_exit(hba); 9323 } 9324 9325 static int ufshcd_hba_init(struct ufs_hba *hba) 9326 { 9327 int err; 9328 9329 /* 9330 * Handle host controller power separately from the UFS device power 9331 * rails as it will help controlling the UFS host controller power 9332 * collapse easily which is different than UFS device power collapse. 9333 * Also, enable the host controller power before we go ahead with rest 9334 * of the initialization here. 9335 */ 9336 err = ufshcd_init_hba_vreg(hba); 9337 if (err) 9338 goto out; 9339 9340 err = ufshcd_setup_hba_vreg(hba, true); 9341 if (err) 9342 goto out; 9343 9344 err = ufshcd_init_clocks(hba); 9345 if (err) 9346 goto out_disable_hba_vreg; 9347 9348 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9349 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9350 9351 err = ufshcd_setup_clocks(hba, true); 9352 if (err) 9353 goto out_disable_hba_vreg; 9354 9355 err = ufshcd_init_vreg(hba); 9356 if (err) 9357 goto out_disable_clks; 9358 9359 err = ufshcd_setup_vreg(hba, true); 9360 if (err) 9361 goto out_disable_clks; 9362 9363 err = ufshcd_variant_hba_init(hba); 9364 if (err) 9365 goto out_disable_vreg; 9366 9367 ufs_debugfs_hba_init(hba); 9368 ufs_fault_inject_hba_init(hba); 9369 9370 hba->is_powered = true; 9371 goto out; 9372 9373 out_disable_vreg: 9374 ufshcd_setup_vreg(hba, false); 9375 out_disable_clks: 9376 ufshcd_setup_clocks(hba, false); 9377 out_disable_hba_vreg: 9378 ufshcd_setup_hba_vreg(hba, false); 9379 out: 9380 return err; 9381 } 9382 9383 static void ufshcd_hba_exit(struct ufs_hba *hba) 9384 { 9385 if (hba->is_powered) { 9386 ufshcd_pm_qos_exit(hba); 9387 ufshcd_exit_clk_scaling(hba); 9388 ufshcd_exit_clk_gating(hba); 9389 if (hba->eh_wq) 9390 destroy_workqueue(hba->eh_wq); 9391 ufs_debugfs_hba_exit(hba); 9392 ufshcd_variant_hba_exit(hba); 9393 ufshcd_setup_vreg(hba, false); 9394 ufshcd_setup_clocks(hba, false); 9395 ufshcd_setup_hba_vreg(hba, false); 9396 hba->is_powered = false; 9397 ufs_put_device_desc(hba); 9398 } 9399 } 9400 9401 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9402 enum ufs_dev_pwr_mode pwr_mode, 9403 struct scsi_sense_hdr *sshdr) 9404 { 9405 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9406 struct scsi_failure failure_defs[] = { 9407 { 9408 .allowed = 2, 9409 .result = SCMD_FAILURE_RESULT_ANY, 9410 }, 9411 }; 9412 struct scsi_failures failures = { 9413 .failure_definitions = failure_defs, 9414 }; 9415 const struct scsi_exec_args args = { 9416 .failures = &failures, 9417 .sshdr = sshdr, 9418 .req_flags = BLK_MQ_REQ_PM, 9419 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9420 }; 9421 9422 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9423 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9424 &args); 9425 } 9426 9427 /** 9428 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9429 * power mode 9430 * @hba: per adapter instance 9431 * @pwr_mode: device power mode to set 9432 * 9433 * Return: 0 if requested power mode is set successfully; 9434 * < 0 if failed to set the requested power mode. 9435 */ 9436 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9437 enum ufs_dev_pwr_mode pwr_mode) 9438 { 9439 struct scsi_sense_hdr sshdr; 9440 struct scsi_device *sdp; 9441 unsigned long flags; 9442 int ret; 9443 9444 spin_lock_irqsave(hba->host->host_lock, flags); 9445 sdp = hba->ufs_device_wlun; 9446 if (sdp && scsi_device_online(sdp)) 9447 ret = scsi_device_get(sdp); 9448 else 9449 ret = -ENODEV; 9450 spin_unlock_irqrestore(hba->host->host_lock, flags); 9451 9452 if (ret) 9453 return ret; 9454 9455 /* 9456 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9457 * handling, which would wait for host to be resumed. Since we know 9458 * we are functional while we are here, skip host resume in error 9459 * handling context. 9460 */ 9461 hba->host->eh_noresume = 1; 9462 9463 /* 9464 * Current function would be generally called from the power management 9465 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9466 * already suspended childs. 9467 */ 9468 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9469 if (ret) { 9470 sdev_printk(KERN_WARNING, sdp, 9471 "START_STOP failed for power mode: %d, result %x\n", 9472 pwr_mode, ret); 9473 if (ret > 0) { 9474 if (scsi_sense_valid(&sshdr)) 9475 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9476 ret = -EIO; 9477 } 9478 } else { 9479 hba->curr_dev_pwr_mode = pwr_mode; 9480 } 9481 9482 scsi_device_put(sdp); 9483 hba->host->eh_noresume = 0; 9484 return ret; 9485 } 9486 9487 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9488 enum uic_link_state req_link_state, 9489 bool check_for_bkops) 9490 { 9491 int ret = 0; 9492 9493 if (req_link_state == hba->uic_link_state) 9494 return 0; 9495 9496 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9497 ret = ufshcd_uic_hibern8_enter(hba); 9498 if (!ret) { 9499 ufshcd_set_link_hibern8(hba); 9500 } else { 9501 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9502 __func__, ret); 9503 goto out; 9504 } 9505 } 9506 /* 9507 * If autobkops is enabled, link can't be turned off because 9508 * turning off the link would also turn off the device, except in the 9509 * case of DeepSleep where the device is expected to remain powered. 9510 */ 9511 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9512 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9513 /* 9514 * Let's make sure that link is in low power mode, we are doing 9515 * this currently by putting the link in Hibern8. Otherway to 9516 * put the link in low power mode is to send the DME end point 9517 * to device and then send the DME reset command to local 9518 * unipro. But putting the link in hibern8 is much faster. 9519 * 9520 * Note also that putting the link in Hibern8 is a requirement 9521 * for entering DeepSleep. 9522 */ 9523 ret = ufshcd_uic_hibern8_enter(hba); 9524 if (ret) { 9525 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9526 __func__, ret); 9527 goto out; 9528 } 9529 /* 9530 * Change controller state to "reset state" which 9531 * should also put the link in off/reset state 9532 */ 9533 ufshcd_hba_stop(hba); 9534 /* 9535 * TODO: Check if we need any delay to make sure that 9536 * controller is reset 9537 */ 9538 ufshcd_set_link_off(hba); 9539 } 9540 9541 out: 9542 return ret; 9543 } 9544 9545 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9546 { 9547 bool vcc_off = false; 9548 9549 /* 9550 * It seems some UFS devices may keep drawing more than sleep current 9551 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9552 * To avoid this situation, add 2ms delay before putting these UFS 9553 * rails in LPM mode. 9554 */ 9555 if (!ufshcd_is_link_active(hba) && 9556 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9557 usleep_range(2000, 2100); 9558 9559 /* 9560 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9561 * power. 9562 * 9563 * If UFS device and link is in OFF state, all power supplies (VCC, 9564 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9565 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9566 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9567 * 9568 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9569 * in low power state which would save some power. 9570 * 9571 * If Write Booster is enabled and the device needs to flush the WB 9572 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9573 */ 9574 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9575 !hba->dev_info.is_lu_power_on_wp) { 9576 ufshcd_setup_vreg(hba, false); 9577 vcc_off = true; 9578 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9579 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9580 vcc_off = true; 9581 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9582 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9583 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9584 } 9585 } 9586 9587 /* 9588 * Some UFS devices require delay after VCC power rail is turned-off. 9589 */ 9590 if (vcc_off && hba->vreg_info.vcc && 9591 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9592 usleep_range(5000, 5100); 9593 } 9594 9595 #ifdef CONFIG_PM 9596 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9597 { 9598 int ret = 0; 9599 9600 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9601 !hba->dev_info.is_lu_power_on_wp) { 9602 ret = ufshcd_setup_vreg(hba, true); 9603 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9604 if (!ufshcd_is_link_active(hba)) { 9605 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9606 if (ret) 9607 goto vcc_disable; 9608 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9609 if (ret) 9610 goto vccq_lpm; 9611 } 9612 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9613 } 9614 goto out; 9615 9616 vccq_lpm: 9617 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9618 vcc_disable: 9619 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9620 out: 9621 return ret; 9622 } 9623 #endif /* CONFIG_PM */ 9624 9625 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9626 { 9627 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9628 ufshcd_setup_hba_vreg(hba, false); 9629 } 9630 9631 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9632 { 9633 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9634 ufshcd_setup_hba_vreg(hba, true); 9635 } 9636 9637 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9638 { 9639 int ret = 0; 9640 bool check_for_bkops; 9641 enum ufs_pm_level pm_lvl; 9642 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9643 enum uic_link_state req_link_state; 9644 9645 hba->pm_op_in_progress = true; 9646 if (pm_op != UFS_SHUTDOWN_PM) { 9647 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9648 hba->rpm_lvl : hba->spm_lvl; 9649 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9650 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9651 } else { 9652 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9653 req_link_state = UIC_LINK_OFF_STATE; 9654 } 9655 9656 /* 9657 * If we can't transition into any of the low power modes 9658 * just gate the clocks. 9659 */ 9660 ufshcd_hold(hba); 9661 hba->clk_gating.is_suspended = true; 9662 9663 if (ufshcd_is_clkscaling_supported(hba)) 9664 ufshcd_clk_scaling_suspend(hba, true); 9665 9666 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9667 req_link_state == UIC_LINK_ACTIVE_STATE) { 9668 goto vops_suspend; 9669 } 9670 9671 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9672 (req_link_state == hba->uic_link_state)) 9673 goto enable_scaling; 9674 9675 /* UFS device & link must be active before we enter in this function */ 9676 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9677 /* Wait err handler finish or trigger err recovery */ 9678 if (!ufshcd_eh_in_progress(hba)) 9679 ufshcd_force_error_recovery(hba); 9680 ret = -EBUSY; 9681 goto enable_scaling; 9682 } 9683 9684 if (pm_op == UFS_RUNTIME_PM) { 9685 if (ufshcd_can_autobkops_during_suspend(hba)) { 9686 /* 9687 * The device is idle with no requests in the queue, 9688 * allow background operations if bkops status shows 9689 * that performance might be impacted. 9690 */ 9691 ret = ufshcd_urgent_bkops(hba); 9692 if (ret) { 9693 /* 9694 * If return err in suspend flow, IO will hang. 9695 * Trigger error handler and break suspend for 9696 * error recovery. 9697 */ 9698 ufshcd_force_error_recovery(hba); 9699 ret = -EBUSY; 9700 goto enable_scaling; 9701 } 9702 } else { 9703 /* make sure that auto bkops is disabled */ 9704 ufshcd_disable_auto_bkops(hba); 9705 } 9706 /* 9707 * If device needs to do BKOP or WB buffer flush during 9708 * Hibern8, keep device power mode as "active power mode" 9709 * and VCC supply. 9710 */ 9711 hba->dev_info.b_rpm_dev_flush_capable = 9712 hba->auto_bkops_enabled || 9713 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9714 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9715 ufshcd_is_auto_hibern8_enabled(hba))) && 9716 ufshcd_wb_need_flush(hba)); 9717 } 9718 9719 flush_work(&hba->eeh_work); 9720 9721 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9722 if (ret) 9723 goto enable_scaling; 9724 9725 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9726 if (pm_op != UFS_RUNTIME_PM) 9727 /* ensure that bkops is disabled */ 9728 ufshcd_disable_auto_bkops(hba); 9729 9730 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9731 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9732 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9733 /* 9734 * If return err in suspend flow, IO will hang. 9735 * Trigger error handler and break suspend for 9736 * error recovery. 9737 */ 9738 ufshcd_force_error_recovery(hba); 9739 ret = -EBUSY; 9740 } 9741 if (ret) 9742 goto enable_scaling; 9743 } 9744 } 9745 9746 /* 9747 * In the case of DeepSleep, the device is expected to remain powered 9748 * with the link off, so do not check for bkops. 9749 */ 9750 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9751 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9752 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9753 /* 9754 * If return err in suspend flow, IO will hang. 9755 * Trigger error handler and break suspend for 9756 * error recovery. 9757 */ 9758 ufshcd_force_error_recovery(hba); 9759 ret = -EBUSY; 9760 } 9761 if (ret) 9762 goto set_dev_active; 9763 9764 vops_suspend: 9765 /* 9766 * Call vendor specific suspend callback. As these callbacks may access 9767 * vendor specific host controller register space call them before the 9768 * host clocks are ON. 9769 */ 9770 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9771 if (ret) 9772 goto set_link_active; 9773 9774 cancel_delayed_work_sync(&hba->ufs_rtc_update_work); 9775 goto out; 9776 9777 set_link_active: 9778 /* 9779 * Device hardware reset is required to exit DeepSleep. Also, for 9780 * DeepSleep, the link is off so host reset and restore will be done 9781 * further below. 9782 */ 9783 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9784 ufshcd_device_reset(hba); 9785 WARN_ON(!ufshcd_is_link_off(hba)); 9786 } 9787 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9788 ufshcd_set_link_active(hba); 9789 else if (ufshcd_is_link_off(hba)) 9790 ufshcd_host_reset_and_restore(hba); 9791 set_dev_active: 9792 /* Can also get here needing to exit DeepSleep */ 9793 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9794 ufshcd_device_reset(hba); 9795 ufshcd_host_reset_and_restore(hba); 9796 } 9797 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9798 ufshcd_disable_auto_bkops(hba); 9799 enable_scaling: 9800 if (ufshcd_is_clkscaling_supported(hba)) 9801 ufshcd_clk_scaling_suspend(hba, false); 9802 9803 hba->dev_info.b_rpm_dev_flush_capable = false; 9804 out: 9805 if (hba->dev_info.b_rpm_dev_flush_capable) { 9806 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9807 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9808 } 9809 9810 if (ret) { 9811 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9812 hba->clk_gating.is_suspended = false; 9813 ufshcd_release(hba); 9814 } 9815 hba->pm_op_in_progress = false; 9816 return ret; 9817 } 9818 9819 #ifdef CONFIG_PM 9820 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9821 { 9822 int ret; 9823 enum uic_link_state old_link_state = hba->uic_link_state; 9824 9825 hba->pm_op_in_progress = true; 9826 9827 /* 9828 * Call vendor specific resume callback. As these callbacks may access 9829 * vendor specific host controller register space call them when the 9830 * host clocks are ON. 9831 */ 9832 ret = ufshcd_vops_resume(hba, pm_op); 9833 if (ret) 9834 goto out; 9835 9836 /* For DeepSleep, the only supported option is to have the link off */ 9837 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9838 9839 if (ufshcd_is_link_hibern8(hba)) { 9840 ret = ufshcd_uic_hibern8_exit(hba); 9841 if (!ret) { 9842 ufshcd_set_link_active(hba); 9843 } else { 9844 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9845 __func__, ret); 9846 goto vendor_suspend; 9847 } 9848 } else if (ufshcd_is_link_off(hba)) { 9849 /* 9850 * A full initialization of the host and the device is 9851 * required since the link was put to off during suspend. 9852 * Note, in the case of DeepSleep, the device will exit 9853 * DeepSleep due to device reset. 9854 */ 9855 ret = ufshcd_reset_and_restore(hba); 9856 /* 9857 * ufshcd_reset_and_restore() should have already 9858 * set the link state as active 9859 */ 9860 if (ret || !ufshcd_is_link_active(hba)) 9861 goto vendor_suspend; 9862 } 9863 9864 if (!ufshcd_is_ufs_dev_active(hba)) { 9865 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9866 if (ret) 9867 goto set_old_link_state; 9868 ufshcd_set_timestamp_attr(hba); 9869 schedule_delayed_work(&hba->ufs_rtc_update_work, 9870 msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS)); 9871 } 9872 9873 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9874 ufshcd_enable_auto_bkops(hba); 9875 else 9876 /* 9877 * If BKOPs operations are urgently needed at this moment then 9878 * keep auto-bkops enabled or else disable it. 9879 */ 9880 ufshcd_urgent_bkops(hba); 9881 9882 if (hba->ee_usr_mask) 9883 ufshcd_write_ee_control(hba); 9884 9885 if (ufshcd_is_clkscaling_supported(hba)) 9886 ufshcd_clk_scaling_suspend(hba, false); 9887 9888 if (hba->dev_info.b_rpm_dev_flush_capable) { 9889 hba->dev_info.b_rpm_dev_flush_capable = false; 9890 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9891 } 9892 9893 ufshcd_configure_auto_hibern8(hba); 9894 9895 goto out; 9896 9897 set_old_link_state: 9898 ufshcd_link_state_transition(hba, old_link_state, 0); 9899 vendor_suspend: 9900 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9901 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9902 out: 9903 if (ret) 9904 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9905 hba->clk_gating.is_suspended = false; 9906 ufshcd_release(hba); 9907 hba->pm_op_in_progress = false; 9908 return ret; 9909 } 9910 9911 static int ufshcd_wl_runtime_suspend(struct device *dev) 9912 { 9913 struct scsi_device *sdev = to_scsi_device(dev); 9914 struct ufs_hba *hba; 9915 int ret; 9916 ktime_t start = ktime_get(); 9917 9918 hba = shost_priv(sdev->host); 9919 9920 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9921 if (ret) 9922 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9923 9924 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9925 ktime_to_us(ktime_sub(ktime_get(), start)), 9926 hba->curr_dev_pwr_mode, hba->uic_link_state); 9927 9928 return ret; 9929 } 9930 9931 static int ufshcd_wl_runtime_resume(struct device *dev) 9932 { 9933 struct scsi_device *sdev = to_scsi_device(dev); 9934 struct ufs_hba *hba; 9935 int ret = 0; 9936 ktime_t start = ktime_get(); 9937 9938 hba = shost_priv(sdev->host); 9939 9940 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9941 if (ret) 9942 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9943 9944 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9945 ktime_to_us(ktime_sub(ktime_get(), start)), 9946 hba->curr_dev_pwr_mode, hba->uic_link_state); 9947 9948 return ret; 9949 } 9950 #endif 9951 9952 #ifdef CONFIG_PM_SLEEP 9953 static int ufshcd_wl_suspend(struct device *dev) 9954 { 9955 struct scsi_device *sdev = to_scsi_device(dev); 9956 struct ufs_hba *hba; 9957 int ret = 0; 9958 ktime_t start = ktime_get(); 9959 9960 hba = shost_priv(sdev->host); 9961 down(&hba->host_sem); 9962 hba->system_suspending = true; 9963 9964 if (pm_runtime_suspended(dev)) 9965 goto out; 9966 9967 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9968 if (ret) { 9969 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9970 up(&hba->host_sem); 9971 } 9972 9973 out: 9974 if (!ret) 9975 hba->is_sys_suspended = true; 9976 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9977 ktime_to_us(ktime_sub(ktime_get(), start)), 9978 hba->curr_dev_pwr_mode, hba->uic_link_state); 9979 9980 return ret; 9981 } 9982 9983 static int ufshcd_wl_resume(struct device *dev) 9984 { 9985 struct scsi_device *sdev = to_scsi_device(dev); 9986 struct ufs_hba *hba; 9987 int ret = 0; 9988 ktime_t start = ktime_get(); 9989 9990 hba = shost_priv(sdev->host); 9991 9992 if (pm_runtime_suspended(dev)) 9993 goto out; 9994 9995 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9996 if (ret) 9997 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9998 out: 9999 trace_ufshcd_wl_resume(dev_name(dev), ret, 10000 ktime_to_us(ktime_sub(ktime_get(), start)), 10001 hba->curr_dev_pwr_mode, hba->uic_link_state); 10002 if (!ret) 10003 hba->is_sys_suspended = false; 10004 hba->system_suspending = false; 10005 up(&hba->host_sem); 10006 return ret; 10007 } 10008 #endif 10009 10010 /** 10011 * ufshcd_suspend - helper function for suspend operations 10012 * @hba: per adapter instance 10013 * 10014 * This function will put disable irqs, turn off clocks 10015 * and set vreg and hba-vreg in lpm mode. 10016 * 10017 * Return: 0 upon success; < 0 upon failure. 10018 */ 10019 static int ufshcd_suspend(struct ufs_hba *hba) 10020 { 10021 int ret; 10022 10023 if (!hba->is_powered) 10024 return 0; 10025 /* 10026 * Disable the host irq as host controller as there won't be any 10027 * host controller transaction expected till resume. 10028 */ 10029 ufshcd_disable_irq(hba); 10030 ret = ufshcd_setup_clocks(hba, false); 10031 if (ret) { 10032 ufshcd_enable_irq(hba); 10033 return ret; 10034 } 10035 if (ufshcd_is_clkgating_allowed(hba)) { 10036 hba->clk_gating.state = CLKS_OFF; 10037 trace_ufshcd_clk_gating(dev_name(hba->dev), 10038 hba->clk_gating.state); 10039 } 10040 10041 ufshcd_vreg_set_lpm(hba); 10042 /* Put the host controller in low power mode if possible */ 10043 ufshcd_hba_vreg_set_lpm(hba); 10044 ufshcd_pm_qos_update(hba, false); 10045 return ret; 10046 } 10047 10048 #ifdef CONFIG_PM 10049 /** 10050 * ufshcd_resume - helper function for resume operations 10051 * @hba: per adapter instance 10052 * 10053 * This function basically turns on the regulators, clocks and 10054 * irqs of the hba. 10055 * 10056 * Return: 0 for success and non-zero for failure. 10057 */ 10058 static int ufshcd_resume(struct ufs_hba *hba) 10059 { 10060 int ret; 10061 10062 if (!hba->is_powered) 10063 return 0; 10064 10065 ufshcd_hba_vreg_set_hpm(hba); 10066 ret = ufshcd_vreg_set_hpm(hba); 10067 if (ret) 10068 goto out; 10069 10070 /* Make sure clocks are enabled before accessing controller */ 10071 ret = ufshcd_setup_clocks(hba, true); 10072 if (ret) 10073 goto disable_vreg; 10074 10075 /* enable the host irq as host controller would be active soon */ 10076 ufshcd_enable_irq(hba); 10077 10078 goto out; 10079 10080 disable_vreg: 10081 ufshcd_vreg_set_lpm(hba); 10082 out: 10083 if (ret) 10084 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 10085 return ret; 10086 } 10087 #endif /* CONFIG_PM */ 10088 10089 #ifdef CONFIG_PM_SLEEP 10090 /** 10091 * ufshcd_system_suspend - system suspend callback 10092 * @dev: Device associated with the UFS controller. 10093 * 10094 * Executed before putting the system into a sleep state in which the contents 10095 * of main memory are preserved. 10096 * 10097 * Return: 0 for success and non-zero for failure. 10098 */ 10099 int ufshcd_system_suspend(struct device *dev) 10100 { 10101 struct ufs_hba *hba = dev_get_drvdata(dev); 10102 int ret = 0; 10103 ktime_t start = ktime_get(); 10104 10105 if (pm_runtime_suspended(hba->dev)) 10106 goto out; 10107 10108 ret = ufshcd_suspend(hba); 10109 out: 10110 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 10111 ktime_to_us(ktime_sub(ktime_get(), start)), 10112 hba->curr_dev_pwr_mode, hba->uic_link_state); 10113 return ret; 10114 } 10115 EXPORT_SYMBOL(ufshcd_system_suspend); 10116 10117 /** 10118 * ufshcd_system_resume - system resume callback 10119 * @dev: Device associated with the UFS controller. 10120 * 10121 * Executed after waking the system up from a sleep state in which the contents 10122 * of main memory were preserved. 10123 * 10124 * Return: 0 for success and non-zero for failure. 10125 */ 10126 int ufshcd_system_resume(struct device *dev) 10127 { 10128 struct ufs_hba *hba = dev_get_drvdata(dev); 10129 ktime_t start = ktime_get(); 10130 int ret = 0; 10131 10132 if (pm_runtime_suspended(hba->dev)) 10133 goto out; 10134 10135 ret = ufshcd_resume(hba); 10136 10137 out: 10138 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10139 ktime_to_us(ktime_sub(ktime_get(), start)), 10140 hba->curr_dev_pwr_mode, hba->uic_link_state); 10141 10142 return ret; 10143 } 10144 EXPORT_SYMBOL(ufshcd_system_resume); 10145 #endif /* CONFIG_PM_SLEEP */ 10146 10147 #ifdef CONFIG_PM 10148 /** 10149 * ufshcd_runtime_suspend - runtime suspend callback 10150 * @dev: Device associated with the UFS controller. 10151 * 10152 * Check the description of ufshcd_suspend() function for more details. 10153 * 10154 * Return: 0 for success and non-zero for failure. 10155 */ 10156 int ufshcd_runtime_suspend(struct device *dev) 10157 { 10158 struct ufs_hba *hba = dev_get_drvdata(dev); 10159 int ret; 10160 ktime_t start = ktime_get(); 10161 10162 ret = ufshcd_suspend(hba); 10163 10164 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10165 ktime_to_us(ktime_sub(ktime_get(), start)), 10166 hba->curr_dev_pwr_mode, hba->uic_link_state); 10167 return ret; 10168 } 10169 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10170 10171 /** 10172 * ufshcd_runtime_resume - runtime resume routine 10173 * @dev: Device associated with the UFS controller. 10174 * 10175 * This function basically brings controller 10176 * to active state. Following operations are done in this function: 10177 * 10178 * 1. Turn on all the controller related clocks 10179 * 2. Turn ON VCC rail 10180 * 10181 * Return: 0 upon success; < 0 upon failure. 10182 */ 10183 int ufshcd_runtime_resume(struct device *dev) 10184 { 10185 struct ufs_hba *hba = dev_get_drvdata(dev); 10186 int ret; 10187 ktime_t start = ktime_get(); 10188 10189 ret = ufshcd_resume(hba); 10190 10191 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10192 ktime_to_us(ktime_sub(ktime_get(), start)), 10193 hba->curr_dev_pwr_mode, hba->uic_link_state); 10194 return ret; 10195 } 10196 EXPORT_SYMBOL(ufshcd_runtime_resume); 10197 #endif /* CONFIG_PM */ 10198 10199 static void ufshcd_wl_shutdown(struct device *dev) 10200 { 10201 struct scsi_device *sdev = to_scsi_device(dev); 10202 struct ufs_hba *hba = shost_priv(sdev->host); 10203 10204 down(&hba->host_sem); 10205 hba->shutting_down = true; 10206 up(&hba->host_sem); 10207 10208 /* Turn on everything while shutting down */ 10209 ufshcd_rpm_get_sync(hba); 10210 scsi_device_quiesce(sdev); 10211 shost_for_each_device(sdev, hba->host) { 10212 if (sdev == hba->ufs_device_wlun) 10213 continue; 10214 scsi_device_quiesce(sdev); 10215 } 10216 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10217 10218 /* 10219 * Next, turn off the UFS controller and the UFS regulators. Disable 10220 * clocks. 10221 */ 10222 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10223 ufshcd_suspend(hba); 10224 10225 hba->is_powered = false; 10226 } 10227 10228 /** 10229 * ufshcd_remove - de-allocate SCSI host and host memory space 10230 * data structure memory 10231 * @hba: per adapter instance 10232 */ 10233 void ufshcd_remove(struct ufs_hba *hba) 10234 { 10235 if (hba->ufs_device_wlun) 10236 ufshcd_rpm_get_sync(hba); 10237 ufs_hwmon_remove(hba); 10238 ufs_bsg_remove(hba); 10239 ufs_sysfs_remove_nodes(hba->dev); 10240 blk_mq_destroy_queue(hba->tmf_queue); 10241 blk_put_queue(hba->tmf_queue); 10242 blk_mq_free_tag_set(&hba->tmf_tag_set); 10243 if (hba->scsi_host_added) 10244 scsi_remove_host(hba->host); 10245 /* disable interrupts */ 10246 ufshcd_disable_intr(hba, hba->intr_mask); 10247 ufshcd_hba_stop(hba); 10248 ufshcd_hba_exit(hba); 10249 } 10250 EXPORT_SYMBOL_GPL(ufshcd_remove); 10251 10252 #ifdef CONFIG_PM_SLEEP 10253 int ufshcd_system_freeze(struct device *dev) 10254 { 10255 10256 return ufshcd_system_suspend(dev); 10257 10258 } 10259 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10260 10261 int ufshcd_system_restore(struct device *dev) 10262 { 10263 10264 struct ufs_hba *hba = dev_get_drvdata(dev); 10265 int ret; 10266 10267 ret = ufshcd_system_resume(dev); 10268 if (ret) 10269 return ret; 10270 10271 /* Configure UTRL and UTMRL base address registers */ 10272 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10273 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10274 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10275 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10276 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10277 REG_UTP_TASK_REQ_LIST_BASE_L); 10278 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10279 REG_UTP_TASK_REQ_LIST_BASE_H); 10280 /* 10281 * Make sure that UTRL and UTMRL base address registers 10282 * are updated with the latest queue addresses. Only after 10283 * updating these addresses, we can queue the new commands. 10284 */ 10285 ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H); 10286 10287 return 0; 10288 10289 } 10290 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10291 10292 int ufshcd_system_thaw(struct device *dev) 10293 { 10294 return ufshcd_system_resume(dev); 10295 } 10296 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10297 #endif /* CONFIG_PM_SLEEP */ 10298 10299 /** 10300 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10301 * @hba: pointer to Host Bus Adapter (HBA) 10302 */ 10303 void ufshcd_dealloc_host(struct ufs_hba *hba) 10304 { 10305 scsi_host_put(hba->host); 10306 } 10307 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10308 10309 /** 10310 * ufshcd_set_dma_mask - Set dma mask based on the controller 10311 * addressing capability 10312 * @hba: per adapter instance 10313 * 10314 * Return: 0 for success, non-zero for failure. 10315 */ 10316 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10317 { 10318 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10319 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10320 return 0; 10321 } 10322 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10323 } 10324 10325 /** 10326 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10327 * @dev: pointer to device handle 10328 * @hba_handle: driver private handle 10329 * 10330 * Return: 0 on success, non-zero value on failure. 10331 */ 10332 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10333 { 10334 struct Scsi_Host *host; 10335 struct ufs_hba *hba; 10336 int err = 0; 10337 10338 if (!dev) { 10339 dev_err(dev, 10340 "Invalid memory reference for dev is NULL\n"); 10341 err = -ENODEV; 10342 goto out_error; 10343 } 10344 10345 host = scsi_host_alloc(&ufshcd_driver_template, 10346 sizeof(struct ufs_hba)); 10347 if (!host) { 10348 dev_err(dev, "scsi_host_alloc failed\n"); 10349 err = -ENOMEM; 10350 goto out_error; 10351 } 10352 host->nr_maps = HCTX_TYPE_POLL + 1; 10353 hba = shost_priv(host); 10354 hba->host = host; 10355 hba->dev = dev; 10356 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10357 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10358 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10359 INIT_LIST_HEAD(&hba->clk_list_head); 10360 spin_lock_init(&hba->outstanding_lock); 10361 10362 *hba_handle = hba; 10363 10364 out_error: 10365 return err; 10366 } 10367 EXPORT_SYMBOL(ufshcd_alloc_host); 10368 10369 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10370 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10371 const struct blk_mq_queue_data *qd) 10372 { 10373 WARN_ON_ONCE(true); 10374 return BLK_STS_NOTSUPP; 10375 } 10376 10377 static const struct blk_mq_ops ufshcd_tmf_ops = { 10378 .queue_rq = ufshcd_queue_tmf, 10379 }; 10380 10381 /** 10382 * ufshcd_init - Driver initialization routine 10383 * @hba: per-adapter instance 10384 * @mmio_base: base register address 10385 * @irq: Interrupt line of device 10386 * 10387 * Return: 0 on success, non-zero value on failure. 10388 */ 10389 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10390 { 10391 int err; 10392 struct Scsi_Host *host = hba->host; 10393 struct device *dev = hba->dev; 10394 char eh_wq_name[sizeof("ufs_eh_wq_00")]; 10395 10396 /* 10397 * dev_set_drvdata() must be called before any callbacks are registered 10398 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10399 * sysfs). 10400 */ 10401 dev_set_drvdata(dev, hba); 10402 10403 if (!mmio_base) { 10404 dev_err(hba->dev, 10405 "Invalid memory reference for mmio_base is NULL\n"); 10406 err = -ENODEV; 10407 goto out_error; 10408 } 10409 10410 hba->mmio_base = mmio_base; 10411 hba->irq = irq; 10412 hba->vps = &ufs_hba_vps; 10413 10414 err = ufshcd_hba_init(hba); 10415 if (err) 10416 goto out_error; 10417 10418 /* Read capabilities registers */ 10419 err = ufshcd_hba_capabilities(hba); 10420 if (err) 10421 goto out_disable; 10422 10423 /* Get UFS version supported by the controller */ 10424 hba->ufs_version = ufshcd_get_ufs_version(hba); 10425 10426 /* Get Interrupt bit mask per version */ 10427 hba->intr_mask = ufshcd_get_intr_mask(hba); 10428 10429 err = ufshcd_set_dma_mask(hba); 10430 if (err) { 10431 dev_err(hba->dev, "set dma mask failed\n"); 10432 goto out_disable; 10433 } 10434 10435 /* Allocate memory for host memory space */ 10436 err = ufshcd_memory_alloc(hba); 10437 if (err) { 10438 dev_err(hba->dev, "Memory allocation failed\n"); 10439 goto out_disable; 10440 } 10441 10442 /* Configure LRB */ 10443 ufshcd_host_memory_configure(hba); 10444 10445 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10446 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10447 host->max_id = UFSHCD_MAX_ID; 10448 host->max_lun = UFS_MAX_LUNS; 10449 host->max_channel = UFSHCD_MAX_CHANNEL; 10450 host->unique_id = host->host_no; 10451 host->max_cmd_len = UFS_CDB_SIZE; 10452 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10453 10454 /* Use default RPM delay if host not set */ 10455 if (host->rpm_autosuspend_delay == 0) 10456 host->rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS; 10457 10458 hba->max_pwr_info.is_valid = false; 10459 10460 /* Initialize work queues */ 10461 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d", 10462 hba->host->host_no); 10463 hba->eh_wq = create_singlethread_workqueue(eh_wq_name); 10464 if (!hba->eh_wq) { 10465 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10466 __func__); 10467 err = -ENOMEM; 10468 goto out_disable; 10469 } 10470 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10471 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10472 10473 sema_init(&hba->host_sem, 1); 10474 10475 /* Initialize UIC command mutex */ 10476 mutex_init(&hba->uic_cmd_mutex); 10477 10478 /* Initialize mutex for device management commands */ 10479 mutex_init(&hba->dev_cmd.lock); 10480 10481 /* Initialize mutex for exception event control */ 10482 mutex_init(&hba->ee_ctrl_mutex); 10483 10484 mutex_init(&hba->wb_mutex); 10485 init_rwsem(&hba->clk_scaling_lock); 10486 10487 ufshcd_init_clk_gating(hba); 10488 10489 ufshcd_init_clk_scaling(hba); 10490 10491 /* 10492 * In order to avoid any spurious interrupt immediately after 10493 * registering UFS controller interrupt handler, clear any pending UFS 10494 * interrupt status and disable all the UFS interrupts. 10495 */ 10496 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10497 REG_INTERRUPT_STATUS); 10498 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10499 /* 10500 * Make sure that UFS interrupts are disabled and any pending interrupt 10501 * status is cleared before registering UFS interrupt handler. 10502 */ 10503 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 10504 10505 /* IRQ registration */ 10506 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10507 if (err) { 10508 dev_err(hba->dev, "request irq failed\n"); 10509 goto out_disable; 10510 } else { 10511 hba->is_irq_enabled = true; 10512 } 10513 10514 if (!is_mcq_supported(hba)) { 10515 if (!hba->lsdb_sup) { 10516 dev_err(hba->dev, "%s: failed to initialize (legacy doorbell mode not supported)\n", 10517 __func__); 10518 err = -EINVAL; 10519 goto out_disable; 10520 } 10521 err = scsi_add_host(host, hba->dev); 10522 if (err) { 10523 dev_err(hba->dev, "scsi_add_host failed\n"); 10524 goto out_disable; 10525 } 10526 hba->scsi_host_added = true; 10527 } 10528 10529 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10530 .nr_hw_queues = 1, 10531 .queue_depth = hba->nutmrs, 10532 .ops = &ufshcd_tmf_ops, 10533 .flags = BLK_MQ_F_NO_SCHED, 10534 }; 10535 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10536 if (err < 0) 10537 goto out_remove_scsi_host; 10538 hba->tmf_queue = blk_mq_alloc_queue(&hba->tmf_tag_set, NULL, NULL); 10539 if (IS_ERR(hba->tmf_queue)) { 10540 err = PTR_ERR(hba->tmf_queue); 10541 goto free_tmf_tag_set; 10542 } 10543 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10544 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10545 if (!hba->tmf_rqs) { 10546 err = -ENOMEM; 10547 goto free_tmf_queue; 10548 } 10549 10550 /* Reset the attached device */ 10551 ufshcd_device_reset(hba); 10552 10553 ufshcd_init_crypto(hba); 10554 10555 /* Host controller enable */ 10556 err = ufshcd_hba_enable(hba); 10557 if (err) { 10558 dev_err(hba->dev, "Host controller enable failed\n"); 10559 ufshcd_print_evt_hist(hba); 10560 ufshcd_print_host_state(hba); 10561 goto free_tmf_queue; 10562 } 10563 10564 /* 10565 * Set the default power management level for runtime and system PM. 10566 * Default power saving mode is to keep UFS link in Hibern8 state 10567 * and UFS device in sleep state. 10568 */ 10569 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10570 UFS_SLEEP_PWR_MODE, 10571 UIC_LINK_HIBERN8_STATE); 10572 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10573 UFS_SLEEP_PWR_MODE, 10574 UIC_LINK_HIBERN8_STATE); 10575 10576 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, ufshcd_rpm_dev_flush_recheck_work); 10577 INIT_DELAYED_WORK(&hba->ufs_rtc_update_work, ufshcd_rtc_work); 10578 10579 /* Set the default auto-hiberate idle timer value to 150 ms */ 10580 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10581 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10582 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10583 } 10584 10585 /* Hold auto suspend until async scan completes */ 10586 pm_runtime_get_sync(dev); 10587 atomic_set(&hba->scsi_block_reqs_cnt, 0); 10588 /* 10589 * We are assuming that device wasn't put in sleep/power-down 10590 * state exclusively during the boot stage before kernel. 10591 * This assumption helps avoid doing link startup twice during 10592 * ufshcd_probe_hba(). 10593 */ 10594 ufshcd_set_ufs_dev_active(hba); 10595 10596 async_schedule(ufshcd_async_scan, hba); 10597 ufs_sysfs_add_nodes(hba->dev); 10598 10599 device_enable_async_suspend(dev); 10600 ufshcd_pm_qos_init(hba); 10601 return 0; 10602 10603 free_tmf_queue: 10604 blk_mq_destroy_queue(hba->tmf_queue); 10605 blk_put_queue(hba->tmf_queue); 10606 free_tmf_tag_set: 10607 blk_mq_free_tag_set(&hba->tmf_tag_set); 10608 out_remove_scsi_host: 10609 if (hba->scsi_host_added) 10610 scsi_remove_host(hba->host); 10611 out_disable: 10612 hba->is_irq_enabled = false; 10613 ufshcd_hba_exit(hba); 10614 out_error: 10615 return err; 10616 } 10617 EXPORT_SYMBOL_GPL(ufshcd_init); 10618 10619 void ufshcd_resume_complete(struct device *dev) 10620 { 10621 struct ufs_hba *hba = dev_get_drvdata(dev); 10622 10623 if (hba->complete_put) { 10624 ufshcd_rpm_put(hba); 10625 hba->complete_put = false; 10626 } 10627 } 10628 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10629 10630 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10631 { 10632 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10633 enum ufs_dev_pwr_mode dev_pwr_mode; 10634 enum uic_link_state link_state; 10635 unsigned long flags; 10636 bool res; 10637 10638 spin_lock_irqsave(&dev->power.lock, flags); 10639 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10640 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10641 res = pm_runtime_suspended(dev) && 10642 hba->curr_dev_pwr_mode == dev_pwr_mode && 10643 hba->uic_link_state == link_state && 10644 !hba->dev_info.b_rpm_dev_flush_capable; 10645 spin_unlock_irqrestore(&dev->power.lock, flags); 10646 10647 return res; 10648 } 10649 10650 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10651 { 10652 struct ufs_hba *hba = dev_get_drvdata(dev); 10653 int ret; 10654 10655 /* 10656 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10657 * are same. And it doesn't wake up the device for system-suspend 10658 * if it's runtime suspended. But ufs doesn't follow that. 10659 * Refer ufshcd_resume_complete() 10660 */ 10661 if (hba->ufs_device_wlun) { 10662 /* Prevent runtime suspend */ 10663 ufshcd_rpm_get_noresume(hba); 10664 /* 10665 * Check if already runtime suspended in same state as system 10666 * suspend would be. 10667 */ 10668 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10669 /* RPM state is not ok for SPM, so runtime resume */ 10670 ret = ufshcd_rpm_resume(hba); 10671 if (ret < 0 && ret != -EACCES) { 10672 ufshcd_rpm_put(hba); 10673 return ret; 10674 } 10675 } 10676 hba->complete_put = true; 10677 } 10678 return 0; 10679 } 10680 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10681 10682 int ufshcd_suspend_prepare(struct device *dev) 10683 { 10684 return __ufshcd_suspend_prepare(dev, true); 10685 } 10686 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10687 10688 #ifdef CONFIG_PM_SLEEP 10689 static int ufshcd_wl_poweroff(struct device *dev) 10690 { 10691 struct scsi_device *sdev = to_scsi_device(dev); 10692 struct ufs_hba *hba = shost_priv(sdev->host); 10693 10694 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10695 return 0; 10696 } 10697 #endif 10698 10699 static int ufshcd_wl_probe(struct device *dev) 10700 { 10701 struct scsi_device *sdev = to_scsi_device(dev); 10702 10703 if (!is_device_wlun(sdev)) 10704 return -ENODEV; 10705 10706 blk_pm_runtime_init(sdev->request_queue, dev); 10707 pm_runtime_set_autosuspend_delay(dev, 0); 10708 pm_runtime_allow(dev); 10709 10710 return 0; 10711 } 10712 10713 static int ufshcd_wl_remove(struct device *dev) 10714 { 10715 pm_runtime_forbid(dev); 10716 return 0; 10717 } 10718 10719 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10720 #ifdef CONFIG_PM_SLEEP 10721 .suspend = ufshcd_wl_suspend, 10722 .resume = ufshcd_wl_resume, 10723 .freeze = ufshcd_wl_suspend, 10724 .thaw = ufshcd_wl_resume, 10725 .poweroff = ufshcd_wl_poweroff, 10726 .restore = ufshcd_wl_resume, 10727 #endif 10728 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10729 }; 10730 10731 static void ufshcd_check_header_layout(void) 10732 { 10733 /* 10734 * gcc compilers before version 10 cannot do constant-folding for 10735 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10736 * before. 10737 */ 10738 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10739 return; 10740 10741 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10742 .cci = 3})[0] != 3); 10743 10744 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10745 .ehs_length = 2})[1] != 2); 10746 10747 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10748 .enable_crypto = 1})[2] 10749 != 0x80); 10750 10751 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10752 .command_type = 5, 10753 .data_direction = 3, 10754 .interrupt = 1, 10755 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10756 10757 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10758 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10759 cpu_to_le32(0xdeadbeef)); 10760 10761 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10762 .ocs = 4})[8] != 4); 10763 10764 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10765 .cds = 5})[9] != 5); 10766 10767 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10768 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10769 cpu_to_le32(0xbadcafe)); 10770 10771 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10772 .iid = 0xf })[4] != 0xf0); 10773 10774 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10775 .command_set_type = 0xf })[4] != 0xf); 10776 } 10777 10778 /* 10779 * ufs_dev_wlun_template - describes ufs device wlun 10780 * ufs-device wlun - used to send pm commands 10781 * All luns are consumers of ufs-device wlun. 10782 * 10783 * Currently, no sd driver is present for wluns. 10784 * Hence the no specific pm operations are performed. 10785 * With ufs design, SSU should be sent to ufs-device wlun. 10786 * Hence register a scsi driver for ufs wluns only. 10787 */ 10788 static struct scsi_driver ufs_dev_wlun_template = { 10789 .gendrv = { 10790 .name = "ufs_device_wlun", 10791 .probe = ufshcd_wl_probe, 10792 .remove = ufshcd_wl_remove, 10793 .pm = &ufshcd_wl_pm_ops, 10794 .shutdown = ufshcd_wl_shutdown, 10795 }, 10796 }; 10797 10798 static int __init ufshcd_core_init(void) 10799 { 10800 int ret; 10801 10802 ufshcd_check_header_layout(); 10803 10804 ufs_debugfs_init(); 10805 10806 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10807 if (ret) 10808 ufs_debugfs_exit(); 10809 return ret; 10810 } 10811 10812 static void __exit ufshcd_core_exit(void) 10813 { 10814 ufs_debugfs_exit(); 10815 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10816 } 10817 10818 module_init(ufshcd_core_init); 10819 module_exit(ufshcd_core_exit); 10820 10821 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10822 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10823 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10824 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10825 MODULE_LICENSE("GPL"); 10826