1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * zs.c: Serial port driver for IOASIC DECstations. 4 * 5 * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras. 6 * Derived from drivers/macintosh/macserial.c by Harald Koerfgen. 7 * 8 * DECstation changes 9 * Copyright (C) 1998-2000 Harald Koerfgen 10 * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 11 * 12 * For the rest of the code the original Copyright applies: 13 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) 14 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 15 * 16 * 17 * Note: for IOASIC systems the wiring is as follows: 18 * 19 * mouse/keyboard: 20 * DIN-7 MJ-4 signal SCC 21 * 2 1 TxD <- A.TxD 22 * 3 4 RxD -> A.RxD 23 * 24 * EIA-232/EIA-423: 25 * DB-25 MMJ-6 signal SCC 26 * 2 2 TxD <- B.TxD 27 * 3 5 RxD -> B.RxD 28 * 4 RTS <- ~A.RTS 29 * 5 CTS -> ~B.CTS 30 * 6 6 DSR -> ~A.SYNC 31 * 8 CD -> ~B.DCD 32 * 12 DSRS(DCE) -> ~A.CTS (*) 33 * 15 TxC -> B.TxC 34 * 17 RxC -> B.RxC 35 * 20 1 DTR <- ~A.DTR 36 * 22 RI -> ~A.DCD 37 * 23 DSRS(DTE) <- ~B.RTS 38 * 39 * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE) 40 * is shared with DSRS(DTE) at pin 23. 41 * 42 * As you can immediately notice the wiring of the RTS, DTR and DSR signals 43 * is a bit odd. This makes the handling of port B unnecessarily 44 * complicated and prevents the use of some automatic modes of operation. 45 */ 46 47 #include <linux/bug.h> 48 #include <linux/console.h> 49 #include <linux/delay.h> 50 #include <linux/errno.h> 51 #include <linux/init.h> 52 #include <linux/interrupt.h> 53 #include <linux/io.h> 54 #include <linux/ioport.h> 55 #include <linux/irqflags.h> 56 #include <linux/kernel.h> 57 #include <linux/module.h> 58 #include <linux/major.h> 59 #include <linux/platform_device.h> 60 #include <linux/serial.h> 61 #include <linux/serial_core.h> 62 #include <linux/spinlock.h> 63 #include <linux/sysrq.h> 64 #include <linux/tty.h> 65 #include <linux/tty_flip.h> 66 #include <linux/types.h> 67 68 #include <linux/atomic.h> 69 70 #include "zs.h" 71 72 73 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>"); 74 MODULE_DESCRIPTION("DECstation Z85C30 serial driver"); 75 MODULE_LICENSE("GPL"); 76 77 78 static char zs_name[] __initdata = "DECstation Z85C30 serial driver version "; 79 static char zs_version[] __initdata = "0.11"; 80 81 /* 82 * It would be nice to dynamically allocate everything that 83 * depends on ZS_NUM_SCCS, so we could support any number of 84 * Z85C30s, but for now... 85 */ 86 #define ZS_NUM_SCCS 2 /* Max # of ZS chips supported. */ 87 #define ZS_NUM_CHAN 2 /* 2 channels per chip. */ 88 #define ZS_CHAN_A 0 /* Index of the channel A. */ 89 #define ZS_CHAN_B 1 /* Index of the channel B. */ 90 #define ZS_CHAN_IO_SIZE 8 /* IOMEM space size. */ 91 #define ZS_CHAN_IO_STRIDE 4 /* Register alignment. */ 92 #define ZS_CHAN_IO_OFFSET 1 /* The SCC resides on the high byte 93 of the 16-bit IOBUS. */ 94 #define ZS_CLOCK 7372800 /* Z85C30 PCLK input clock rate. */ 95 96 #define to_zport(uport) container_of(uport, struct zs_port, port) 97 98 static struct zs_scc zs_sccs[ZS_NUM_SCCS]; 99 static struct uart_driver zs_reg; 100 101 /* 102 * Set parameters in WR5, WR12, WR13 such as not to interfere 103 * with the initial PROM-based console. Otherwise any output 104 * produced before the console handover would cause the system 105 * firmware to hang (TxENAB) or produce rubbish (Tx8, B9600). 106 */ 107 static u8 zs_init_regs[ZS_NUM_REGS] __initdata = { 108 0, /* write 0 */ 109 PAR_SPEC, /* write 1 */ 110 0, /* write 2 */ 111 0, /* write 3 */ 112 X16CLK | SB1, /* write 4 */ 113 Tx8 | TxENAB, /* write 5 */ 114 0, 0, 0, /* write 6, 7, 8 */ 115 MIE | DLC | NV, /* write 9 */ 116 NRZ, /* write 10 */ 117 TCBR | RCBR, /* write 11 */ 118 0x16, 0x00, /* BRG time constant, write 12 + 13 */ 119 BRSRC | BRENABL, /* write 14 */ 120 0, /* write 15 */ 121 }; 122 123 /* 124 * Debugging. 125 */ 126 #undef ZS_DEBUG_REGS 127 128 129 /* 130 * Reading and writing Z85C30 registers. 131 */ 132 static void recovery_delay(void) 133 { 134 udelay(2); 135 } 136 137 static u8 read_zsreg(struct zs_port *zport, int reg) 138 { 139 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; 140 u8 retval; 141 142 if (reg != 0) { 143 writeb(reg & 0xf, control); 144 fast_iob(); 145 recovery_delay(); 146 } 147 retval = readb(control); 148 recovery_delay(); 149 return retval; 150 } 151 152 static void write_zsreg(struct zs_port *zport, int reg, u8 value) 153 { 154 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; 155 156 if (reg != 0) { 157 writeb(reg & 0xf, control); 158 fast_iob(); recovery_delay(); 159 } 160 writeb(value, control); 161 fast_iob(); 162 recovery_delay(); 163 return; 164 } 165 166 static u8 read_zsdata(struct zs_port *zport) 167 { 168 void __iomem *data = zport->port.membase + 169 ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET; 170 u8 retval; 171 172 retval = readb(data); 173 recovery_delay(); 174 return retval; 175 } 176 177 static void write_zsdata(struct zs_port *zport, u8 value) 178 { 179 void __iomem *data = zport->port.membase + 180 ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET; 181 182 writeb(value, data); 183 fast_iob(); 184 recovery_delay(); 185 return; 186 } 187 188 #ifdef ZS_DEBUG_REGS 189 void zs_dump(void) 190 { 191 struct zs_port *zport; 192 int i, j; 193 194 for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) { 195 zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN]; 196 197 if (!zport->scc) 198 continue; 199 200 for (j = 0; j < 16; j++) 201 printk("W%-2d = 0x%02x\t", j, zport->regs[j]); 202 printk("\n"); 203 for (j = 0; j < 16; j++) 204 printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j)); 205 printk("\n\n"); 206 } 207 } 208 #endif 209 210 211 static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq) 212 { 213 if (irq) 214 spin_lock_irq(lock); 215 else 216 spin_lock(lock); 217 } 218 219 static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq) 220 { 221 if (irq) 222 spin_unlock_irq(lock); 223 else 224 spin_unlock(lock); 225 } 226 227 static int zs_receive_drain(struct zs_port *zport) 228 { 229 int loops = 10000; 230 231 while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops) 232 read_zsdata(zport); 233 return loops; 234 } 235 236 static int zs_transmit_drain(struct zs_port *zport, int irq) 237 { 238 struct zs_scc *scc = zport->scc; 239 int loops = 10000; 240 241 while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) { 242 zs_spin_unlock_cond_irq(&scc->zlock, irq); 243 udelay(2); 244 zs_spin_lock_cond_irq(&scc->zlock, irq); 245 } 246 return loops; 247 } 248 249 static int zs_line_drain(struct zs_port *zport, int irq) 250 { 251 struct zs_scc *scc = zport->scc; 252 int loops = 10000; 253 254 while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) { 255 zs_spin_unlock_cond_irq(&scc->zlock, irq); 256 udelay(2); 257 zs_spin_lock_cond_irq(&scc->zlock, irq); 258 } 259 return loops; 260 } 261 262 263 static void load_zsregs(struct zs_port *zport, u8 *regs, int irq) 264 { 265 /* Let the current transmission finish. */ 266 zs_line_drain(zport, irq); 267 /* Load 'em up. */ 268 write_zsreg(zport, R3, regs[3] & ~RxENABLE); 269 write_zsreg(zport, R5, regs[5] & ~TxENAB); 270 write_zsreg(zport, R4, regs[4]); 271 write_zsreg(zport, R9, regs[9]); 272 write_zsreg(zport, R1, regs[1]); 273 write_zsreg(zport, R2, regs[2]); 274 write_zsreg(zport, R10, regs[10]); 275 write_zsreg(zport, R14, regs[14] & ~BRENABL); 276 write_zsreg(zport, R11, regs[11]); 277 write_zsreg(zport, R12, regs[12]); 278 write_zsreg(zport, R13, regs[13]); 279 write_zsreg(zport, R14, regs[14]); 280 write_zsreg(zport, R15, regs[15]); 281 if (regs[3] & RxENABLE) 282 write_zsreg(zport, R3, regs[3]); 283 if (regs[5] & TxENAB) 284 write_zsreg(zport, R5, regs[5]); 285 return; 286 } 287 288 289 /* 290 * Status handling routines. 291 */ 292 293 /* 294 * zs_tx_empty() -- get the transmitter empty status 295 * 296 * Purpose: Let user call ioctl() to get info when the UART physically 297 * is emptied. On bus types like RS485, the transmitter must 298 * release the bus after transmitting. This must be done when 299 * the transmit shift register is empty, not be done when the 300 * transmit holding register is empty. This functionality 301 * allows an RS485 driver to be written in user space. 302 */ 303 static unsigned int zs_tx_empty(struct uart_port *uport) 304 { 305 struct zs_port *zport = to_zport(uport); 306 struct zs_scc *scc = zport->scc; 307 unsigned long flags; 308 u8 status; 309 310 spin_lock_irqsave(&scc->zlock, flags); 311 status = read_zsreg(zport, R1); 312 spin_unlock_irqrestore(&scc->zlock, flags); 313 314 return status & ALL_SNT ? TIOCSER_TEMT : 0; 315 } 316 317 static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a, 318 struct zs_port *zport_b) 319 { 320 u8 status_a, status_b; 321 unsigned int mctrl; 322 323 status_a = read_zsreg(zport_a, R0); 324 status_b = read_zsreg(zport_b, R0); 325 326 mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) | 327 ((status_b & DCD) ? TIOCM_CAR : 0) | 328 ((status_a & DCD) ? TIOCM_RNG : 0) | 329 ((status_a & SYNC_HUNT) ? TIOCM_DSR : 0); 330 331 return mctrl; 332 } 333 334 static unsigned int zs_raw_get_mctrl(struct zs_port *zport) 335 { 336 struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A]; 337 338 return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0; 339 } 340 341 static unsigned int zs_raw_xor_mctrl(struct zs_port *zport) 342 { 343 struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A]; 344 unsigned int mmask, mctrl, delta; 345 u8 mask_a, mask_b; 346 347 if (zport == zport_a) 348 return 0; 349 350 mask_a = zport_a->regs[15]; 351 mask_b = zport->regs[15]; 352 353 mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) | 354 ((mask_b & DCDIE) ? TIOCM_CAR : 0) | 355 ((mask_a & DCDIE) ? TIOCM_RNG : 0) | 356 ((mask_a & SYNCIE) ? TIOCM_DSR : 0); 357 358 mctrl = zport->mctrl; 359 if (mmask) { 360 mctrl &= ~mmask; 361 mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask; 362 } 363 364 delta = mctrl ^ zport->mctrl; 365 if (delta) 366 zport->mctrl = mctrl; 367 368 return delta; 369 } 370 371 static unsigned int zs_get_mctrl(struct uart_port *uport) 372 { 373 struct zs_port *zport = to_zport(uport); 374 struct zs_scc *scc = zport->scc; 375 unsigned int mctrl; 376 377 spin_lock(&scc->zlock); 378 mctrl = zs_raw_get_mctrl(zport); 379 spin_unlock(&scc->zlock); 380 381 return mctrl; 382 } 383 384 static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl) 385 { 386 struct zs_port *zport = to_zport(uport); 387 struct zs_scc *scc = zport->scc; 388 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; 389 u8 oldloop, newloop; 390 391 spin_lock(&scc->zlock); 392 if (zport != zport_a) { 393 if (mctrl & TIOCM_DTR) 394 zport_a->regs[5] |= DTR; 395 else 396 zport_a->regs[5] &= ~DTR; 397 if (mctrl & TIOCM_RTS) 398 zport_a->regs[5] |= RTS; 399 else 400 zport_a->regs[5] &= ~RTS; 401 write_zsreg(zport_a, R5, zport_a->regs[5]); 402 } 403 404 /* Rarely modified, so don't poke at hardware unless necessary. */ 405 oldloop = zport->regs[14]; 406 newloop = oldloop; 407 if (mctrl & TIOCM_LOOP) 408 newloop |= LOOPBAK; 409 else 410 newloop &= ~LOOPBAK; 411 if (newloop != oldloop) { 412 zport->regs[14] = newloop; 413 write_zsreg(zport, R14, zport->regs[14]); 414 } 415 spin_unlock(&scc->zlock); 416 } 417 418 static void zs_raw_stop_tx(struct zs_port *zport) 419 { 420 write_zsreg(zport, R0, RES_Tx_P); 421 zport->tx_stopped = 1; 422 } 423 424 static void zs_stop_tx(struct uart_port *uport) 425 { 426 struct zs_port *zport = to_zport(uport); 427 struct zs_scc *scc = zport->scc; 428 429 spin_lock(&scc->zlock); 430 zs_raw_stop_tx(zport); 431 spin_unlock(&scc->zlock); 432 } 433 434 static void zs_raw_transmit_chars(struct zs_port *); 435 436 static void zs_start_tx(struct uart_port *uport) 437 { 438 struct zs_port *zport = to_zport(uport); 439 struct zs_scc *scc = zport->scc; 440 441 spin_lock(&scc->zlock); 442 if (zport->tx_stopped) { 443 zs_transmit_drain(zport, 0); 444 zport->tx_stopped = 0; 445 zs_raw_transmit_chars(zport); 446 } 447 spin_unlock(&scc->zlock); 448 } 449 450 static void zs_stop_rx(struct uart_port *uport) 451 { 452 struct zs_port *zport = to_zport(uport); 453 struct zs_scc *scc = zport->scc; 454 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; 455 456 spin_lock(&scc->zlock); 457 zport->regs[15] &= ~BRKIE; 458 zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB); 459 zport->regs[1] |= RxINT_DISAB; 460 461 if (zport != zport_a) { 462 /* A-side DCD tracks RI and SYNC tracks DSR. */ 463 zport_a->regs[15] &= ~(DCDIE | SYNCIE); 464 write_zsreg(zport_a, R15, zport_a->regs[15]); 465 if (!(zport_a->regs[15] & BRKIE)) { 466 zport_a->regs[1] &= ~EXT_INT_ENAB; 467 write_zsreg(zport_a, R1, zport_a->regs[1]); 468 } 469 470 /* This-side DCD tracks DCD and CTS tracks CTS. */ 471 zport->regs[15] &= ~(DCDIE | CTSIE); 472 zport->regs[1] &= ~EXT_INT_ENAB; 473 } else { 474 /* DCD tracks RI and SYNC tracks DSR for the B side. */ 475 if (!(zport->regs[15] & (DCDIE | SYNCIE))) 476 zport->regs[1] &= ~EXT_INT_ENAB; 477 } 478 479 write_zsreg(zport, R15, zport->regs[15]); 480 write_zsreg(zport, R1, zport->regs[1]); 481 spin_unlock(&scc->zlock); 482 } 483 484 static void zs_enable_ms(struct uart_port *uport) 485 { 486 struct zs_port *zport = to_zport(uport); 487 struct zs_scc *scc = zport->scc; 488 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; 489 490 if (zport == zport_a) 491 return; 492 493 spin_lock(&scc->zlock); 494 495 /* Clear Ext interrupts if not being handled already. */ 496 if (!(zport_a->regs[1] & EXT_INT_ENAB)) 497 write_zsreg(zport_a, R0, RES_EXT_INT); 498 499 /* A-side DCD tracks RI and SYNC tracks DSR. */ 500 zport_a->regs[1] |= EXT_INT_ENAB; 501 zport_a->regs[15] |= DCDIE | SYNCIE; 502 503 /* This-side DCD tracks DCD and CTS tracks CTS. */ 504 zport->regs[15] |= DCDIE | CTSIE; 505 506 zs_raw_xor_mctrl(zport); 507 508 write_zsreg(zport_a, R1, zport_a->regs[1]); 509 write_zsreg(zport_a, R15, zport_a->regs[15]); 510 write_zsreg(zport, R15, zport->regs[15]); 511 spin_unlock(&scc->zlock); 512 } 513 514 static void zs_break_ctl(struct uart_port *uport, int break_state) 515 { 516 struct zs_port *zport = to_zport(uport); 517 struct zs_scc *scc = zport->scc; 518 unsigned long flags; 519 520 spin_lock_irqsave(&scc->zlock, flags); 521 if (break_state == -1) 522 zport->regs[5] |= SND_BRK; 523 else 524 zport->regs[5] &= ~SND_BRK; 525 write_zsreg(zport, R5, zport->regs[5]); 526 spin_unlock_irqrestore(&scc->zlock, flags); 527 } 528 529 530 /* 531 * Interrupt handling routines. 532 */ 533 #define Rx_BRK 0x0100 /* BREAK event software flag. */ 534 #define Rx_SYS 0x0200 /* SysRq event software flag. */ 535 536 static void zs_receive_chars(struct zs_port *zport) 537 { 538 struct uart_port *uport = &zport->port; 539 struct zs_scc *scc = zport->scc; 540 struct uart_icount *icount; 541 unsigned int avail, status; 542 int count; 543 u8 ch, flag; 544 545 for (count = 16; count; count--) { 546 spin_lock(&scc->zlock); 547 avail = read_zsreg(zport, R0) & Rx_CH_AV; 548 spin_unlock(&scc->zlock); 549 if (!avail) 550 break; 551 552 spin_lock(&scc->zlock); 553 status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR); 554 ch = read_zsdata(zport); 555 spin_unlock(&scc->zlock); 556 557 flag = TTY_NORMAL; 558 559 icount = &uport->icount; 560 icount->rx++; 561 562 /* Handle the null char got when BREAK is removed. */ 563 if (!ch) 564 status |= zport->tty_break; 565 if (unlikely(status & 566 (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) { 567 zport->tty_break = 0; 568 569 /* Reset the error indication. */ 570 if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) { 571 spin_lock(&scc->zlock); 572 write_zsreg(zport, R0, ERR_RES); 573 spin_unlock(&scc->zlock); 574 } 575 576 if (status & (Rx_SYS | Rx_BRK)) { 577 icount->brk++; 578 /* SysRq discards the null char. */ 579 if (status & Rx_SYS) 580 continue; 581 } else if (status & FRM_ERR) 582 icount->frame++; 583 else if (status & PAR_ERR) 584 icount->parity++; 585 if (status & Rx_OVR) 586 icount->overrun++; 587 588 status &= uport->read_status_mask; 589 if (status & Rx_BRK) 590 flag = TTY_BREAK; 591 else if (status & FRM_ERR) 592 flag = TTY_FRAME; 593 else if (status & PAR_ERR) 594 flag = TTY_PARITY; 595 } 596 597 if (uart_handle_sysrq_char(uport, ch)) 598 continue; 599 600 uart_insert_char(uport, status, Rx_OVR, ch, flag); 601 } 602 603 tty_flip_buffer_push(&uport->state->port); 604 } 605 606 static void zs_raw_transmit_chars(struct zs_port *zport) 607 { 608 struct tty_port *tport = &zport->port.state->port; 609 unsigned char ch; 610 611 /* XON/XOFF chars. */ 612 if (zport->port.x_char) { 613 write_zsdata(zport, zport->port.x_char); 614 zport->port.icount.tx++; 615 zport->port.x_char = 0; 616 return; 617 } 618 619 /* If nothing to do or stopped or hardware stopped. */ 620 if (uart_tx_stopped(&zport->port) || 621 !uart_fifo_get(&zport->port, &ch)) { 622 zs_raw_stop_tx(zport); 623 return; 624 } 625 626 /* Send char. */ 627 write_zsdata(zport, ch); 628 629 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 630 uart_write_wakeup(&zport->port); 631 632 /* Are we are done? */ 633 if (kfifo_is_empty(&tport->xmit_fifo)) 634 zs_raw_stop_tx(zport); 635 } 636 637 static void zs_transmit_chars(struct zs_port *zport) 638 { 639 struct zs_scc *scc = zport->scc; 640 641 spin_lock(&scc->zlock); 642 zs_raw_transmit_chars(zport); 643 spin_unlock(&scc->zlock); 644 } 645 646 static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a) 647 { 648 struct uart_port *uport = &zport->port; 649 struct zs_scc *scc = zport->scc; 650 unsigned int delta; 651 u8 status, brk; 652 653 spin_lock(&scc->zlock); 654 655 /* Get status from Read Register 0. */ 656 status = read_zsreg(zport, R0); 657 658 if (zport->regs[15] & BRKIE) { 659 brk = status & BRK_ABRT; 660 if (brk && !zport->brk) { 661 spin_unlock(&scc->zlock); 662 if (uart_handle_break(uport)) 663 zport->tty_break = Rx_SYS; 664 else 665 zport->tty_break = Rx_BRK; 666 spin_lock(&scc->zlock); 667 } 668 zport->brk = brk; 669 } 670 671 if (zport != zport_a) { 672 delta = zs_raw_xor_mctrl(zport); 673 spin_unlock(&scc->zlock); 674 675 if (delta & TIOCM_CTS) 676 uart_handle_cts_change(uport, 677 zport->mctrl & TIOCM_CTS); 678 if (delta & TIOCM_CAR) 679 uart_handle_dcd_change(uport, 680 zport->mctrl & TIOCM_CAR); 681 if (delta & TIOCM_RNG) 682 uport->icount.rng++; 683 if (delta & TIOCM_DSR) 684 uport->icount.dsr++; 685 686 if (delta) 687 wake_up_interruptible(&uport->state->port.delta_msr_wait); 688 689 spin_lock(&scc->zlock); 690 } 691 692 /* Clear the status condition... */ 693 write_zsreg(zport, R0, RES_EXT_INT); 694 695 spin_unlock(&scc->zlock); 696 } 697 698 /* 699 * This is the Z85C30 driver's generic interrupt routine. 700 */ 701 static irqreturn_t zs_interrupt(int irq, void *dev_id) 702 { 703 struct zs_scc *scc = dev_id; 704 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; 705 struct zs_port *zport_b = &scc->zport[ZS_CHAN_B]; 706 irqreturn_t status = IRQ_NONE; 707 u8 zs_intreg; 708 int count; 709 710 /* 711 * NOTE: The read register 3, which holds the irq status, 712 * does so for both channels on each chip. Although 713 * the status value itself must be read from the A 714 * channel and is only valid when read from channel A. 715 * Yes... broken hardware... 716 */ 717 for (count = 16; count; count--) { 718 spin_lock(&scc->zlock); 719 zs_intreg = read_zsreg(zport_a, R3); 720 spin_unlock(&scc->zlock); 721 if (!zs_intreg) 722 break; 723 724 /* 725 * We do not like losing characters, so we prioritise 726 * interrupt sources a little bit differently than 727 * the SCC would, was it allowed to. 728 */ 729 if (zs_intreg & CHBRxIP) 730 zs_receive_chars(zport_b); 731 if (zs_intreg & CHARxIP) 732 zs_receive_chars(zport_a); 733 if (zs_intreg & CHBEXT) 734 zs_status_handle(zport_b, zport_a); 735 if (zs_intreg & CHAEXT) 736 zs_status_handle(zport_a, zport_a); 737 if (zs_intreg & CHBTxIP) 738 zs_transmit_chars(zport_b); 739 if (zs_intreg & CHATxIP) 740 zs_transmit_chars(zport_a); 741 742 status = IRQ_HANDLED; 743 } 744 745 return status; 746 } 747 748 749 /* 750 * Finally, routines used to initialize the serial port. 751 */ 752 static int zs_startup(struct uart_port *uport) 753 { 754 struct zs_port *zport = to_zport(uport); 755 struct zs_scc *scc = zport->scc; 756 unsigned long flags; 757 int irq_guard; 758 int ret; 759 760 irq_guard = atomic_add_return(1, &scc->irq_guard); 761 if (irq_guard == 1) { 762 ret = request_irq(zport->port.irq, zs_interrupt, 763 IRQF_SHARED, "scc", scc); 764 if (ret) { 765 atomic_add(-1, &scc->irq_guard); 766 printk(KERN_ERR "zs: can't get irq %d\n", 767 zport->port.irq); 768 return ret; 769 } 770 } 771 772 spin_lock_irqsave(&scc->zlock, flags); 773 774 /* Clear the receive FIFO. */ 775 zs_receive_drain(zport); 776 777 /* Clear the interrupt registers. */ 778 write_zsreg(zport, R0, ERR_RES); 779 write_zsreg(zport, R0, RES_Tx_P); 780 /* But Ext only if not being handled already. */ 781 if (!(zport->regs[1] & EXT_INT_ENAB)) 782 write_zsreg(zport, R0, RES_EXT_INT); 783 784 /* Finally, enable sequencing and interrupts. */ 785 zport->regs[1] &= ~RxINT_MASK; 786 zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB; 787 zport->regs[3] |= RxENABLE; 788 zport->regs[15] |= BRKIE; 789 write_zsreg(zport, R1, zport->regs[1]); 790 write_zsreg(zport, R3, zport->regs[3]); 791 write_zsreg(zport, R5, zport->regs[5]); 792 write_zsreg(zport, R15, zport->regs[15]); 793 794 /* Record the current state of RR0. */ 795 zport->mctrl = zs_raw_get_mctrl(zport); 796 zport->brk = read_zsreg(zport, R0) & BRK_ABRT; 797 798 zport->tx_stopped = 1; 799 800 spin_unlock_irqrestore(&scc->zlock, flags); 801 802 return 0; 803 } 804 805 static void zs_shutdown(struct uart_port *uport) 806 { 807 struct zs_port *zport = to_zport(uport); 808 struct zs_scc *scc = zport->scc; 809 unsigned long flags; 810 int irq_guard; 811 812 spin_lock_irqsave(&scc->zlock, flags); 813 814 zport->regs[3] &= ~RxENABLE; 815 write_zsreg(zport, R5, zport->regs[5]); 816 write_zsreg(zport, R3, zport->regs[3]); 817 818 spin_unlock_irqrestore(&scc->zlock, flags); 819 820 irq_guard = atomic_add_return(-1, &scc->irq_guard); 821 if (!irq_guard) 822 free_irq(zport->port.irq, scc); 823 } 824 825 826 static void zs_reset(struct zs_port *zport) 827 { 828 struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A]; 829 struct zs_scc *scc = zport->scc; 830 int irq; 831 unsigned long flags; 832 833 spin_lock_irqsave(&scc->zlock, flags); 834 irq = !irqs_disabled_flags(flags); 835 836 /* Reset the pointer first, just in case... */ 837 read_zsreg(zport, R0); 838 /* And let the current transmission finish. */ 839 zs_line_drain(zport, irq); 840 write_zsreg(zport, R9, zport == zport_a ? CHRA : CHRB); 841 udelay(10); 842 write_zsreg(zport, R9, 0); 843 844 load_zsregs(zport, zport->regs, irq); 845 spin_unlock_irqrestore(&scc->zlock, flags); 846 } 847 848 static void zs_set_termios(struct uart_port *uport, struct ktermios *termios, 849 const struct ktermios *old_termios) 850 { 851 struct zs_port *zport = to_zport(uport); 852 struct zs_scc *scc = zport->scc; 853 struct zs_port *zport_a = &scc->zport[ZS_CHAN_A]; 854 int irq; 855 unsigned int baud, brg; 856 unsigned long flags; 857 858 spin_lock_irqsave(&scc->zlock, flags); 859 irq = !irqs_disabled_flags(flags); 860 861 /* Byte size. */ 862 zport->regs[3] &= ~RxNBITS_MASK; 863 zport->regs[5] &= ~TxNBITS_MASK; 864 switch (termios->c_cflag & CSIZE) { 865 case CS5: 866 zport->regs[3] |= Rx5; 867 zport->regs[5] |= Tx5; 868 break; 869 case CS6: 870 zport->regs[3] |= Rx6; 871 zport->regs[5] |= Tx6; 872 break; 873 case CS7: 874 zport->regs[3] |= Rx7; 875 zport->regs[5] |= Tx7; 876 break; 877 case CS8: 878 default: 879 zport->regs[3] |= Rx8; 880 zport->regs[5] |= Tx8; 881 break; 882 } 883 884 /* Parity and stop bits. */ 885 zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN); 886 if (termios->c_cflag & CSTOPB) 887 zport->regs[4] |= SB2; 888 else 889 zport->regs[4] |= SB1; 890 if (termios->c_cflag & PARENB) 891 zport->regs[4] |= PAR_ENA; 892 if (!(termios->c_cflag & PARODD)) 893 zport->regs[4] |= PAR_EVEN; 894 switch (zport->clk_mode) { 895 case 64: 896 zport->regs[4] |= X64CLK; 897 break; 898 case 32: 899 zport->regs[4] |= X32CLK; 900 break; 901 case 16: 902 zport->regs[4] |= X16CLK; 903 break; 904 case 1: 905 zport->regs[4] |= X1CLK; 906 break; 907 default: 908 BUG(); 909 } 910 911 baud = uart_get_baud_rate(uport, termios, old_termios, 0, 912 uport->uartclk / zport->clk_mode / 4); 913 914 brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode); 915 zport->regs[12] = brg & 0xff; 916 zport->regs[13] = (brg >> 8) & 0xff; 917 918 uart_update_timeout(uport, termios->c_cflag, baud); 919 920 uport->read_status_mask = Rx_OVR; 921 if (termios->c_iflag & INPCK) 922 uport->read_status_mask |= FRM_ERR | PAR_ERR; 923 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 924 uport->read_status_mask |= Rx_BRK; 925 926 uport->ignore_status_mask = 0; 927 if (termios->c_iflag & IGNPAR) 928 uport->ignore_status_mask |= FRM_ERR | PAR_ERR; 929 if (termios->c_iflag & IGNBRK) { 930 uport->ignore_status_mask |= Rx_BRK; 931 if (termios->c_iflag & IGNPAR) 932 uport->ignore_status_mask |= Rx_OVR; 933 } 934 935 if (termios->c_cflag & CREAD) 936 zport->regs[3] |= RxENABLE; 937 else 938 zport->regs[3] &= ~RxENABLE; 939 940 if (zport != zport_a) { 941 if (!(termios->c_cflag & CLOCAL)) { 942 zport->regs[15] |= DCDIE; 943 } else 944 zport->regs[15] &= ~DCDIE; 945 if (termios->c_cflag & CRTSCTS) { 946 zport->regs[15] |= CTSIE; 947 } else 948 zport->regs[15] &= ~CTSIE; 949 zs_raw_xor_mctrl(zport); 950 } 951 952 /* Load up the new values. */ 953 load_zsregs(zport, zport->regs, irq); 954 955 spin_unlock_irqrestore(&scc->zlock, flags); 956 } 957 958 959 static const char *zs_type(struct uart_port *uport) 960 { 961 return "Z85C30 SCC"; 962 } 963 964 static void zs_release_port(struct uart_port *uport) 965 { 966 iounmap(uport->membase); 967 uport->membase = NULL; 968 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE); 969 } 970 971 static int zs_map_port(struct uart_port *uport) 972 { 973 if (!uport->membase) 974 uport->membase = ioremap(uport->mapbase, 975 ZS_CHAN_IO_SIZE); 976 if (!uport->membase) { 977 printk(KERN_ERR "zs: Cannot map MMIO\n"); 978 return -ENOMEM; 979 } 980 return 0; 981 } 982 983 static int zs_request_port(struct uart_port *uport) 984 { 985 int ret; 986 987 if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) { 988 printk(KERN_ERR "zs: Unable to reserve MMIO resource\n"); 989 return -EBUSY; 990 } 991 ret = zs_map_port(uport); 992 if (ret) { 993 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE); 994 return ret; 995 } 996 return 0; 997 } 998 999 static void zs_config_port(struct uart_port *uport, int flags) 1000 { 1001 struct zs_port *zport = to_zport(uport); 1002 1003 if (flags & UART_CONFIG_TYPE) { 1004 if (zs_request_port(uport)) 1005 return; 1006 1007 uport->type = PORT_ZS; 1008 1009 zs_reset(zport); 1010 } 1011 } 1012 1013 static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser) 1014 { 1015 struct zs_port *zport = to_zport(uport); 1016 int ret = 0; 1017 1018 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS) 1019 ret = -EINVAL; 1020 if (ser->irq != uport->irq) 1021 ret = -EINVAL; 1022 if (ser->baud_base != uport->uartclk / zport->clk_mode / 4) 1023 ret = -EINVAL; 1024 return ret; 1025 } 1026 1027 1028 static const struct uart_ops zs_ops = { 1029 .tx_empty = zs_tx_empty, 1030 .set_mctrl = zs_set_mctrl, 1031 .get_mctrl = zs_get_mctrl, 1032 .stop_tx = zs_stop_tx, 1033 .start_tx = zs_start_tx, 1034 .stop_rx = zs_stop_rx, 1035 .enable_ms = zs_enable_ms, 1036 .break_ctl = zs_break_ctl, 1037 .startup = zs_startup, 1038 .shutdown = zs_shutdown, 1039 .set_termios = zs_set_termios, 1040 .type = zs_type, 1041 .release_port = zs_release_port, 1042 .request_port = zs_request_port, 1043 .config_port = zs_config_port, 1044 .verify_port = zs_verify_port, 1045 }; 1046 1047 /* 1048 * Initialize Z85C30 port structures. 1049 */ 1050 static int __init zs_probe(struct platform_device *pdev) 1051 { 1052 struct resource *mem_resource, *irq_resource; 1053 int chip, side; 1054 int i; 1055 1056 mem_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1057 irq_resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1058 if (!mem_resource || !irq_resource) 1059 return -ENODEV; 1060 1061 chip = pdev->id; 1062 spin_lock_init(&zs_sccs[chip].zlock); 1063 for (side = 0; side < ZS_NUM_CHAN; side++) { 1064 struct zs_port *zport = &zs_sccs[chip].zport[side]; 1065 struct uart_port *uport = &zport->port; 1066 1067 zport->scc = &zs_sccs[chip]; 1068 zport->clk_mode = 16; 1069 1070 uport->dev = &pdev->dev; 1071 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_ZS_CONSOLE); 1072 uport->irq = irq_resource->start; 1073 uport->uartclk = ZS_CLOCK; 1074 uport->fifosize = 1; 1075 uport->iotype = UPIO_MEM; 1076 uport->flags = UPF_BOOT_AUTOCONF; 1077 uport->ops = &zs_ops; 1078 uport->line = chip * ZS_NUM_CHAN + side; 1079 uport->mapbase = mem_resource->start + 1080 (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE; 1081 1082 for (i = 0; i < ZS_NUM_REGS; i++) 1083 zport->regs[i] = zs_init_regs[i]; 1084 1085 if (uart_add_one_port(&zs_reg, uport)) 1086 uport->dev = NULL; 1087 } 1088 1089 return 0; 1090 } 1091 1092 static void __exit zs_remove(struct platform_device *pdev) 1093 { 1094 int chip, side; 1095 1096 chip = pdev->id; 1097 for (side = ZS_NUM_CHAN - 1; side >= 0; side--) { 1098 struct zs_port *zport = &zs_sccs[chip].zport[side]; 1099 struct uart_port *uport = &zport->port; 1100 1101 if (uport->dev) 1102 uart_remove_one_port(&zs_reg, uport); 1103 } 1104 } 1105 1106 1107 #ifdef CONFIG_SERIAL_ZS_CONSOLE 1108 static void zs_console_putchar(struct uart_port *uport, unsigned char ch) 1109 { 1110 struct zs_port *zport = to_zport(uport); 1111 struct zs_scc *scc = zport->scc; 1112 int irq; 1113 unsigned long flags; 1114 1115 spin_lock_irqsave(&scc->zlock, flags); 1116 irq = !irqs_disabled_flags(flags); 1117 if (zs_transmit_drain(zport, irq)) 1118 write_zsdata(zport, ch); 1119 spin_unlock_irqrestore(&scc->zlock, flags); 1120 } 1121 1122 /* 1123 * Print a string to the serial port trying not to disturb 1124 * any possible real use of the port... 1125 */ 1126 static void zs_console_write(struct console *co, const char *s, 1127 unsigned int count) 1128 { 1129 int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN; 1130 struct zs_port *zport = &zs_sccs[chip].zport[side]; 1131 struct zs_scc *scc = zport->scc; 1132 unsigned long flags; 1133 u8 txint, txenb; 1134 int irq; 1135 1136 /* Disable transmit interrupts and enable the transmitter. */ 1137 spin_lock_irqsave(&scc->zlock, flags); 1138 txint = zport->regs[1]; 1139 txenb = zport->regs[5]; 1140 if (txint & TxINT_ENAB) { 1141 zport->regs[1] = txint & ~TxINT_ENAB; 1142 write_zsreg(zport, R1, zport->regs[1]); 1143 } 1144 if (!(txenb & TxENAB)) { 1145 zport->regs[5] = txenb | TxENAB; 1146 write_zsreg(zport, R5, zport->regs[5]); 1147 } 1148 spin_unlock_irqrestore(&scc->zlock, flags); 1149 1150 uart_console_write(&zport->port, s, count, zs_console_putchar); 1151 1152 /* Restore transmit interrupts and the transmitter enable. */ 1153 spin_lock_irqsave(&scc->zlock, flags); 1154 irq = !irqs_disabled_flags(flags); 1155 zs_line_drain(zport, irq); 1156 if (!(txenb & TxENAB)) { 1157 zport->regs[5] &= ~TxENAB; 1158 write_zsreg(zport, R5, zport->regs[5]); 1159 } 1160 if (txint & TxINT_ENAB) { 1161 zport->regs[1] |= TxINT_ENAB; 1162 write_zsreg(zport, R1, zport->regs[1]); 1163 1164 /* Resume any transmission as the TxIP bit won't be set. */ 1165 if (!zport->tx_stopped) 1166 zs_raw_transmit_chars(zport); 1167 } 1168 spin_unlock_irqrestore(&scc->zlock, flags); 1169 } 1170 1171 /* 1172 * Setup serial console baud/bits/parity. We do two things here: 1173 * - construct a cflag setting for the first uart_open() 1174 * - initialise the serial port 1175 * Return non-zero if we didn't find a serial port. 1176 */ 1177 static int __init zs_console_setup(struct console *co, char *options) 1178 { 1179 int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN; 1180 struct zs_port *zport = &zs_sccs[chip].zport[side]; 1181 struct uart_port *uport = &zport->port; 1182 int baud = 9600; 1183 int bits = 8; 1184 int parity = 'n'; 1185 int flow = 'n'; 1186 1187 if (!zport->scc) 1188 return -ENODEV; 1189 if (options) 1190 uart_parse_options(options, &baud, &parity, &bits, &flow); 1191 return uart_set_options(uport, co, baud, parity, bits, flow); 1192 } 1193 1194 static struct console zs_console = { 1195 .name = "ttyS", 1196 .write = zs_console_write, 1197 .device = uart_console_device, 1198 .setup = zs_console_setup, 1199 .flags = CON_PRINTBUFFER, 1200 .index = -1, 1201 .data = &zs_reg, 1202 }; 1203 1204 #define SERIAL_ZS_CONSOLE &zs_console 1205 #else 1206 #define SERIAL_ZS_CONSOLE NULL 1207 #endif /* CONFIG_SERIAL_ZS_CONSOLE */ 1208 1209 static struct uart_driver zs_reg = { 1210 .owner = THIS_MODULE, 1211 .driver_name = "serial_zs", 1212 .dev_name = "ttyS", 1213 .major = TTY_MAJOR, 1214 .minor = 64, 1215 .nr = ZS_NUM_SCCS * ZS_NUM_CHAN, 1216 .cons = SERIAL_ZS_CONSOLE, 1217 }; 1218 1219 static struct platform_driver zs_driver = { 1220 .remove = __exit_p(zs_remove), 1221 .driver = { .name = "zs" }, 1222 }; 1223 1224 /* zs_init inits the driver. */ 1225 static int __init zs_init(void) 1226 { 1227 int ret; 1228 1229 pr_info("%s%s\n", zs_name, zs_version); 1230 1231 ret = uart_register_driver(&zs_reg); 1232 if (ret) 1233 return ret; 1234 ret = platform_driver_probe(&zs_driver, zs_probe); 1235 if (ret) 1236 uart_unregister_driver(&zs_reg); 1237 1238 return ret; 1239 } 1240 1241 static void __exit zs_exit(void) 1242 { 1243 platform_driver_unregister(&zs_driver); 1244 uart_unregister_driver(&zs_reg); 1245 } 1246 1247 module_init(zs_init); 1248 module_exit(zs_exit); 1249