1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Cadence UART driver (found in Xilinx Zynq) 4 * 5 * 2011 - 2014 (C) Xilinx Inc. 6 * 7 * This program is free software; you can redistribute it 8 * and/or modify it under the terms of the GNU General Public 9 * License as published by the Free Software Foundation; 10 * either version 2 of the License, or (at your option) any 11 * later version. 12 * 13 * This driver has originally been pushed by Xilinx using a Zynq-branding. This 14 * still shows in the naming of this file, the kconfig symbols and some symbols 15 * in the code. 16 */ 17 18 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 #define SUPPORT_SYSRQ 20 #endif 21 22 #include <linux/platform_device.h> 23 #include <linux/serial.h> 24 #include <linux/console.h> 25 #include <linux/serial_core.h> 26 #include <linux/slab.h> 27 #include <linux/tty.h> 28 #include <linux/tty_flip.h> 29 #include <linux/clk.h> 30 #include <linux/irq.h> 31 #include <linux/io.h> 32 #include <linux/of.h> 33 #include <linux/module.h> 34 #include <linux/pm_runtime.h> 35 36 #define CDNS_UART_TTY_NAME "ttyPS" 37 #define CDNS_UART_NAME "xuartps" 38 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ 39 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ 40 #define CDNS_UART_NR_PORTS 2 41 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ 42 #define CDNS_UART_REGISTER_SPACE 0x1000 43 44 /* Rx Trigger level */ 45 static int rx_trigger_level = 56; 46 module_param(rx_trigger_level, uint, S_IRUGO); 47 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); 48 49 /* Rx Timeout */ 50 static int rx_timeout = 10; 51 module_param(rx_timeout, uint, S_IRUGO); 52 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 53 54 /* Register offsets for the UART. */ 55 #define CDNS_UART_CR 0x00 /* Control Register */ 56 #define CDNS_UART_MR 0x04 /* Mode Register */ 57 #define CDNS_UART_IER 0x08 /* Interrupt Enable */ 58 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */ 59 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */ 60 #define CDNS_UART_ISR 0x14 /* Interrupt Status */ 61 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */ 62 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */ 63 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */ 64 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */ 65 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */ 66 #define CDNS_UART_SR 0x2C /* Channel Status */ 67 #define CDNS_UART_FIFO 0x30 /* FIFO */ 68 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */ 69 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */ 70 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */ 71 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */ 72 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */ 73 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */ 74 75 /* Control Register Bit Definitions */ 76 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ 77 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ 78 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ 79 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ 80 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ 81 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ 82 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ 83 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ 84 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 85 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */ 86 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */ 87 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */ 88 89 /* 90 * Mode Register: 91 * The mode register (MR) defines the mode of transfer as well as the data 92 * format. If this register is modified during transmission or reception, 93 * data validity cannot be guaranteed. 94 */ 95 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 96 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 97 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 98 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */ 99 100 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 101 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 102 103 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 104 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 105 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 106 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 107 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 108 109 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 110 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 111 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 112 113 /* 114 * Interrupt Registers: 115 * Interrupt control logic uses the interrupt enable register (IER) and the 116 * interrupt disable register (IDR) to set the value of the bits in the 117 * interrupt mask register (IMR). The IMR determines whether to pass an 118 * interrupt to the interrupt status register (ISR). 119 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 120 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 121 * Reading either IER or IDR returns 0x00. 122 * All four registers have the same bit definitions. 123 */ 124 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 125 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ 126 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 127 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 128 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 129 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 130 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 131 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 132 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 133 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 134 #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */ 135 136 /* 137 * Do not enable parity error interrupt for the following 138 * reason: When parity error interrupt is enabled, each Rx 139 * parity error always results in 2 events. The first one 140 * being parity error interrupt and the second one with a 141 * proper Rx interrupt with the incoming data. Disabling 142 * parity error interrupt ensures better handling of parity 143 * error events. With this change, for a parity error case, we 144 * get a Rx interrupt with parity error set in ISR register 145 * and we still handle parity errors in the desired way. 146 */ 147 148 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \ 149 CDNS_UART_IXR_OVERRUN | \ 150 CDNS_UART_IXR_RXTRIG | \ 151 CDNS_UART_IXR_TOUT) 152 153 /* Goes in read_status_mask for break detection as the HW doesn't do it*/ 154 #define CDNS_UART_IXR_BRK 0x00002000 155 156 #define CDNS_UART_RXBS_SUPPORT BIT(1) 157 /* 158 * Modem Control register: 159 * The read/write Modem Control register controls the interface with the modem 160 * or data set, or a peripheral device emulating a modem. 161 */ 162 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ 163 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ 164 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ 165 166 /* 167 * Channel Status Register: 168 * The channel status register (CSR) is provided to enable the control logic 169 * to monitor the status of bits in the channel interrupt status register, 170 * even if these are masked out by the interrupt mask register. 171 */ 172 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 173 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 174 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 175 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ 176 177 /* baud dividers min/max values */ 178 #define CDNS_UART_BDIV_MIN 4 179 #define CDNS_UART_BDIV_MAX 255 180 #define CDNS_UART_CD_MAX 65535 181 #define UART_AUTOSUSPEND_TIMEOUT 3000 182 183 /** 184 * struct cdns_uart - device data 185 * @port: Pointer to the UART port 186 * @uartclk: Reference clock 187 * @pclk: APB clock 188 * @baud: Current baud rate 189 * @clk_rate_change_nb: Notifier block for clock changes 190 * @quirks: Flags for RXBS support. 191 */ 192 struct cdns_uart { 193 struct uart_port *port; 194 struct clk *uartclk; 195 struct clk *pclk; 196 unsigned int baud; 197 struct notifier_block clk_rate_change_nb; 198 u32 quirks; 199 }; 200 struct cdns_platform_data { 201 u32 quirks; 202 }; 203 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ 204 clk_rate_change_nb); 205 206 /** 207 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors. 208 * @dev_id: Id of the UART port 209 * @isrstatus: The interrupt status register value as read 210 * Return: None 211 */ 212 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus) 213 { 214 struct uart_port *port = (struct uart_port *)dev_id; 215 struct cdns_uart *cdns_uart = port->private_data; 216 unsigned int data; 217 unsigned int rxbs_status = 0; 218 unsigned int status_mask; 219 unsigned int framerrprocessed = 0; 220 char status = TTY_NORMAL; 221 bool is_rxbs_support; 222 223 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 224 225 while ((readl(port->membase + CDNS_UART_SR) & 226 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { 227 if (is_rxbs_support) 228 rxbs_status = readl(port->membase + CDNS_UART_RXBS); 229 data = readl(port->membase + CDNS_UART_FIFO); 230 port->icount.rx++; 231 /* 232 * There is no hardware break detection in Zynq, so we interpret 233 * framing error with all-zeros data as a break sequence. 234 * Most of the time, there's another non-zero byte at the 235 * end of the sequence. 236 */ 237 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) { 238 if (!data) { 239 port->read_status_mask |= CDNS_UART_IXR_BRK; 240 framerrprocessed = 1; 241 continue; 242 } 243 } 244 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) { 245 port->icount.brk++; 246 status = TTY_BREAK; 247 if (uart_handle_break(port)) 248 continue; 249 } 250 251 isrstatus &= port->read_status_mask; 252 isrstatus &= ~port->ignore_status_mask; 253 status_mask = port->read_status_mask; 254 status_mask &= ~port->ignore_status_mask; 255 256 if (data && 257 (port->read_status_mask & CDNS_UART_IXR_BRK)) { 258 port->read_status_mask &= ~CDNS_UART_IXR_BRK; 259 port->icount.brk++; 260 if (uart_handle_break(port)) 261 continue; 262 } 263 264 if (uart_handle_sysrq_char(port, data)) 265 continue; 266 267 if (is_rxbs_support) { 268 if ((rxbs_status & CDNS_UART_RXBS_PARITY) 269 && (status_mask & CDNS_UART_IXR_PARITY)) { 270 port->icount.parity++; 271 status = TTY_PARITY; 272 } 273 if ((rxbs_status & CDNS_UART_RXBS_FRAMING) 274 && (status_mask & CDNS_UART_IXR_PARITY)) { 275 port->icount.frame++; 276 status = TTY_FRAME; 277 } 278 } else { 279 if (isrstatus & CDNS_UART_IXR_PARITY) { 280 port->icount.parity++; 281 status = TTY_PARITY; 282 } 283 if ((isrstatus & CDNS_UART_IXR_FRAMING) && 284 !framerrprocessed) { 285 port->icount.frame++; 286 status = TTY_FRAME; 287 } 288 } 289 if (isrstatus & CDNS_UART_IXR_OVERRUN) { 290 port->icount.overrun++; 291 tty_insert_flip_char(&port->state->port, 0, 292 TTY_OVERRUN); 293 } 294 tty_insert_flip_char(&port->state->port, data, status); 295 isrstatus = 0; 296 } 297 spin_unlock(&port->lock); 298 tty_flip_buffer_push(&port->state->port); 299 spin_lock(&port->lock); 300 } 301 302 /** 303 * cdns_uart_handle_tx - Handle the bytes to be Txed. 304 * @dev_id: Id of the UART port 305 * Return: None 306 */ 307 static void cdns_uart_handle_tx(void *dev_id) 308 { 309 struct uart_port *port = (struct uart_port *)dev_id; 310 unsigned int numbytes; 311 312 if (uart_circ_empty(&port->state->xmit)) { 313 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); 314 } else { 315 numbytes = port->fifosize; 316 while (numbytes && !uart_circ_empty(&port->state->xmit) && 317 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { 318 /* 319 * Get the data from the UART circular buffer 320 * and write it to the cdns_uart's TX_FIFO 321 * register. 322 */ 323 writel( 324 port->state->xmit.buf[port->state->xmit. 325 tail], port->membase + CDNS_UART_FIFO); 326 327 port->icount.tx++; 328 329 /* 330 * Adjust the tail of the UART buffer and wrap 331 * the buffer if it reaches limit. 332 */ 333 port->state->xmit.tail = 334 (port->state->xmit.tail + 1) & 335 (UART_XMIT_SIZE - 1); 336 337 numbytes--; 338 } 339 340 if (uart_circ_chars_pending( 341 &port->state->xmit) < WAKEUP_CHARS) 342 uart_write_wakeup(port); 343 } 344 } 345 346 /** 347 * cdns_uart_isr - Interrupt handler 348 * @irq: Irq number 349 * @dev_id: Id of the port 350 * 351 * Return: IRQHANDLED 352 */ 353 static irqreturn_t cdns_uart_isr(int irq, void *dev_id) 354 { 355 struct uart_port *port = (struct uart_port *)dev_id; 356 unsigned int isrstatus; 357 358 spin_lock(&port->lock); 359 360 /* Read the interrupt status register to determine which 361 * interrupt(s) is/are active and clear them. 362 */ 363 isrstatus = readl(port->membase + CDNS_UART_ISR); 364 writel(isrstatus, port->membase + CDNS_UART_ISR); 365 366 if (isrstatus & CDNS_UART_IXR_TXEMPTY) { 367 cdns_uart_handle_tx(dev_id); 368 isrstatus &= ~CDNS_UART_IXR_TXEMPTY; 369 } 370 if (isrstatus & CDNS_UART_IXR_MASK) 371 cdns_uart_handle_rx(dev_id, isrstatus); 372 373 spin_unlock(&port->lock); 374 return IRQ_HANDLED; 375 } 376 377 /** 378 * cdns_uart_calc_baud_divs - Calculate baud rate divisors 379 * @clk: UART module input clock 380 * @baud: Desired baud rate 381 * @rbdiv: BDIV value (return value) 382 * @rcd: CD value (return value) 383 * @div8: Value for clk_sel bit in mod (return value) 384 * Return: baud rate, requested baud when possible, or actual baud when there 385 * was too much error, zero if no valid divisors are found. 386 * 387 * Formula to obtain baud rate is 388 * baud_tx/rx rate = clk/CD * (BDIV + 1) 389 * input_clk = (Uart User Defined Clock or Apb Clock) 390 * depends on UCLKEN in MR Reg 391 * clk = input_clk or input_clk/8; 392 * depends on CLKS in MR reg 393 * CD and BDIV depends on values in 394 * baud rate generate register 395 * baud rate clock divisor register 396 */ 397 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, 398 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) 399 { 400 u32 cd, bdiv; 401 unsigned int calc_baud; 402 unsigned int bestbaud = 0; 403 unsigned int bauderror; 404 unsigned int besterror = ~0; 405 406 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { 407 *div8 = 1; 408 clk /= 8; 409 } else { 410 *div8 = 0; 411 } 412 413 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { 414 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 415 if (cd < 1 || cd > CDNS_UART_CD_MAX) 416 continue; 417 418 calc_baud = clk / (cd * (bdiv + 1)); 419 420 if (baud > calc_baud) 421 bauderror = baud - calc_baud; 422 else 423 bauderror = calc_baud - baud; 424 425 if (besterror > bauderror) { 426 *rbdiv = bdiv; 427 *rcd = cd; 428 bestbaud = calc_baud; 429 besterror = bauderror; 430 } 431 } 432 /* use the values when percent error is acceptable */ 433 if (((besterror * 100) / baud) < 3) 434 bestbaud = baud; 435 436 return bestbaud; 437 } 438 439 /** 440 * cdns_uart_set_baud_rate - Calculate and set the baud rate 441 * @port: Handle to the uart port structure 442 * @baud: Baud rate to set 443 * Return: baud rate, requested baud when possible, or actual baud when there 444 * was too much error, zero if no valid divisors are found. 445 */ 446 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, 447 unsigned int baud) 448 { 449 unsigned int calc_baud; 450 u32 cd = 0, bdiv = 0; 451 u32 mreg; 452 int div8; 453 struct cdns_uart *cdns_uart = port->private_data; 454 455 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 456 &div8); 457 458 /* Write new divisors to hardware */ 459 mreg = readl(port->membase + CDNS_UART_MR); 460 if (div8) 461 mreg |= CDNS_UART_MR_CLKSEL; 462 else 463 mreg &= ~CDNS_UART_MR_CLKSEL; 464 writel(mreg, port->membase + CDNS_UART_MR); 465 writel(cd, port->membase + CDNS_UART_BAUDGEN); 466 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 467 cdns_uart->baud = baud; 468 469 return calc_baud; 470 } 471 472 #ifdef CONFIG_COMMON_CLK 473 /** 474 * cdns_uart_clk_notitifer_cb - Clock notifier callback 475 * @nb: Notifier block 476 * @event: Notify event 477 * @data: Notifier data 478 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. 479 */ 480 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, 481 unsigned long event, void *data) 482 { 483 u32 ctrl_reg; 484 struct uart_port *port; 485 int locked = 0; 486 struct clk_notifier_data *ndata = data; 487 unsigned long flags = 0; 488 struct cdns_uart *cdns_uart = to_cdns_uart(nb); 489 490 port = cdns_uart->port; 491 if (port->suspended) 492 return NOTIFY_OK; 493 494 switch (event) { 495 case PRE_RATE_CHANGE: 496 { 497 u32 bdiv, cd; 498 int div8; 499 500 /* 501 * Find out if current baud-rate can be achieved with new clock 502 * frequency. 503 */ 504 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, 505 &bdiv, &cd, &div8)) { 506 dev_warn(port->dev, "clock rate change rejected\n"); 507 return NOTIFY_BAD; 508 } 509 510 spin_lock_irqsave(&cdns_uart->port->lock, flags); 511 512 /* Disable the TX and RX to set baud rate */ 513 ctrl_reg = readl(port->membase + CDNS_UART_CR); 514 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 515 writel(ctrl_reg, port->membase + CDNS_UART_CR); 516 517 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 518 519 return NOTIFY_OK; 520 } 521 case POST_RATE_CHANGE: 522 /* 523 * Set clk dividers to generate correct baud with new clock 524 * frequency. 525 */ 526 527 spin_lock_irqsave(&cdns_uart->port->lock, flags); 528 529 locked = 1; 530 port->uartclk = ndata->new_rate; 531 532 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, 533 cdns_uart->baud); 534 /* fall through */ 535 case ABORT_RATE_CHANGE: 536 if (!locked) 537 spin_lock_irqsave(&cdns_uart->port->lock, flags); 538 539 /* Set TX/RX Reset */ 540 ctrl_reg = readl(port->membase + CDNS_UART_CR); 541 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 542 writel(ctrl_reg, port->membase + CDNS_UART_CR); 543 544 while (readl(port->membase + CDNS_UART_CR) & 545 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 546 cpu_relax(); 547 548 /* 549 * Clear the RX disable and TX disable bits and then set the TX 550 * enable bit and RX enable bit to enable the transmitter and 551 * receiver. 552 */ 553 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 554 ctrl_reg = readl(port->membase + CDNS_UART_CR); 555 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 556 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 557 writel(ctrl_reg, port->membase + CDNS_UART_CR); 558 559 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 560 561 return NOTIFY_OK; 562 default: 563 return NOTIFY_DONE; 564 } 565 } 566 #endif 567 568 /** 569 * cdns_uart_start_tx - Start transmitting bytes 570 * @port: Handle to the uart port structure 571 */ 572 static void cdns_uart_start_tx(struct uart_port *port) 573 { 574 unsigned int status; 575 576 if (uart_tx_stopped(port)) 577 return; 578 579 /* 580 * Set the TX enable bit and clear the TX disable bit to enable the 581 * transmitter. 582 */ 583 status = readl(port->membase + CDNS_UART_CR); 584 status &= ~CDNS_UART_CR_TX_DIS; 585 status |= CDNS_UART_CR_TX_EN; 586 writel(status, port->membase + CDNS_UART_CR); 587 588 if (uart_circ_empty(&port->state->xmit)) 589 return; 590 591 cdns_uart_handle_tx(port); 592 593 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR); 594 /* Enable the TX Empty interrupt */ 595 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER); 596 } 597 598 /** 599 * cdns_uart_stop_tx - Stop TX 600 * @port: Handle to the uart port structure 601 */ 602 static void cdns_uart_stop_tx(struct uart_port *port) 603 { 604 unsigned int regval; 605 606 regval = readl(port->membase + CDNS_UART_CR); 607 regval |= CDNS_UART_CR_TX_DIS; 608 /* Disable the transmitter */ 609 writel(regval, port->membase + CDNS_UART_CR); 610 } 611 612 /** 613 * cdns_uart_stop_rx - Stop RX 614 * @port: Handle to the uart port structure 615 */ 616 static void cdns_uart_stop_rx(struct uart_port *port) 617 { 618 unsigned int regval; 619 620 /* Disable RX IRQs */ 621 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR); 622 623 /* Disable the receiver */ 624 regval = readl(port->membase + CDNS_UART_CR); 625 regval |= CDNS_UART_CR_RX_DIS; 626 writel(regval, port->membase + CDNS_UART_CR); 627 } 628 629 /** 630 * cdns_uart_tx_empty - Check whether TX is empty 631 * @port: Handle to the uart port structure 632 * 633 * Return: TIOCSER_TEMT on success, 0 otherwise 634 */ 635 static unsigned int cdns_uart_tx_empty(struct uart_port *port) 636 { 637 unsigned int status; 638 639 status = readl(port->membase + CDNS_UART_SR) & 640 CDNS_UART_SR_TXEMPTY; 641 return status ? TIOCSER_TEMT : 0; 642 } 643 644 /** 645 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop 646 * transmitting char breaks 647 * @port: Handle to the uart port structure 648 * @ctl: Value based on which start or stop decision is taken 649 */ 650 static void cdns_uart_break_ctl(struct uart_port *port, int ctl) 651 { 652 unsigned int status; 653 unsigned long flags; 654 655 spin_lock_irqsave(&port->lock, flags); 656 657 status = readl(port->membase + CDNS_UART_CR); 658 659 if (ctl == -1) 660 writel(CDNS_UART_CR_STARTBRK | status, 661 port->membase + CDNS_UART_CR); 662 else { 663 if ((status & CDNS_UART_CR_STOPBRK) == 0) 664 writel(CDNS_UART_CR_STOPBRK | status, 665 port->membase + CDNS_UART_CR); 666 } 667 spin_unlock_irqrestore(&port->lock, flags); 668 } 669 670 /** 671 * cdns_uart_set_termios - termios operations, handling data length, parity, 672 * stop bits, flow control, baud rate 673 * @port: Handle to the uart port structure 674 * @termios: Handle to the input termios structure 675 * @old: Values of the previously saved termios structure 676 */ 677 static void cdns_uart_set_termios(struct uart_port *port, 678 struct ktermios *termios, struct ktermios *old) 679 { 680 unsigned int cval = 0; 681 unsigned int baud, minbaud, maxbaud; 682 unsigned long flags; 683 unsigned int ctrl_reg, mode_reg; 684 685 spin_lock_irqsave(&port->lock, flags); 686 687 /* Wait for the transmit FIFO to empty before making changes */ 688 if (!(readl(port->membase + CDNS_UART_CR) & 689 CDNS_UART_CR_TX_DIS)) { 690 while (!(readl(port->membase + CDNS_UART_SR) & 691 CDNS_UART_SR_TXEMPTY)) { 692 cpu_relax(); 693 } 694 } 695 696 /* Disable the TX and RX to set baud rate */ 697 ctrl_reg = readl(port->membase + CDNS_UART_CR); 698 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 699 writel(ctrl_reg, port->membase + CDNS_UART_CR); 700 701 /* 702 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 703 * min and max baud should be calculated here based on port->uartclk. 704 * this way we get a valid baud and can safely call set_baud() 705 */ 706 minbaud = port->uartclk / 707 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); 708 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); 709 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 710 baud = cdns_uart_set_baud_rate(port, baud); 711 if (tty_termios_baud_rate(termios)) 712 tty_termios_encode_baud_rate(termios, baud, baud); 713 714 /* Update the per-port timeout. */ 715 uart_update_timeout(port, termios->c_cflag, baud); 716 717 /* Set TX/RX Reset */ 718 ctrl_reg = readl(port->membase + CDNS_UART_CR); 719 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 720 writel(ctrl_reg, port->membase + CDNS_UART_CR); 721 722 while (readl(port->membase + CDNS_UART_CR) & 723 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 724 cpu_relax(); 725 726 /* 727 * Clear the RX disable and TX disable bits and then set the TX enable 728 * bit and RX enable bit to enable the transmitter and receiver. 729 */ 730 ctrl_reg = readl(port->membase + CDNS_UART_CR); 731 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 732 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 733 writel(ctrl_reg, port->membase + CDNS_UART_CR); 734 735 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 736 737 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | 738 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; 739 port->ignore_status_mask = 0; 740 741 if (termios->c_iflag & INPCK) 742 port->read_status_mask |= CDNS_UART_IXR_PARITY | 743 CDNS_UART_IXR_FRAMING; 744 745 if (termios->c_iflag & IGNPAR) 746 port->ignore_status_mask |= CDNS_UART_IXR_PARITY | 747 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 748 749 /* ignore all characters if CREAD is not set */ 750 if ((termios->c_cflag & CREAD) == 0) 751 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | 752 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | 753 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 754 755 mode_reg = readl(port->membase + CDNS_UART_MR); 756 757 /* Handling Data Size */ 758 switch (termios->c_cflag & CSIZE) { 759 case CS6: 760 cval |= CDNS_UART_MR_CHARLEN_6_BIT; 761 break; 762 case CS7: 763 cval |= CDNS_UART_MR_CHARLEN_7_BIT; 764 break; 765 default: 766 case CS8: 767 cval |= CDNS_UART_MR_CHARLEN_8_BIT; 768 termios->c_cflag &= ~CSIZE; 769 termios->c_cflag |= CS8; 770 break; 771 } 772 773 /* Handling Parity and Stop Bits length */ 774 if (termios->c_cflag & CSTOPB) 775 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 776 else 777 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 778 779 if (termios->c_cflag & PARENB) { 780 /* Mark or Space parity */ 781 if (termios->c_cflag & CMSPAR) { 782 if (termios->c_cflag & PARODD) 783 cval |= CDNS_UART_MR_PARITY_MARK; 784 else 785 cval |= CDNS_UART_MR_PARITY_SPACE; 786 } else { 787 if (termios->c_cflag & PARODD) 788 cval |= CDNS_UART_MR_PARITY_ODD; 789 else 790 cval |= CDNS_UART_MR_PARITY_EVEN; 791 } 792 } else { 793 cval |= CDNS_UART_MR_PARITY_NONE; 794 } 795 cval |= mode_reg & 1; 796 writel(cval, port->membase + CDNS_UART_MR); 797 798 spin_unlock_irqrestore(&port->lock, flags); 799 } 800 801 /** 802 * cdns_uart_startup - Called when an application opens a cdns_uart port 803 * @port: Handle to the uart port structure 804 * 805 * Return: 0 on success, negative errno otherwise 806 */ 807 static int cdns_uart_startup(struct uart_port *port) 808 { 809 struct cdns_uart *cdns_uart = port->private_data; 810 bool is_brk_support; 811 int ret; 812 unsigned long flags; 813 unsigned int status = 0; 814 815 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 816 817 spin_lock_irqsave(&port->lock, flags); 818 819 /* Disable the TX and RX */ 820 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 821 port->membase + CDNS_UART_CR); 822 823 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 824 * no break chars. 825 */ 826 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, 827 port->membase + CDNS_UART_CR); 828 829 while (readl(port->membase + CDNS_UART_CR) & 830 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 831 cpu_relax(); 832 833 /* 834 * Clear the RX disable bit and then set the RX enable bit to enable 835 * the receiver. 836 */ 837 status = readl(port->membase + CDNS_UART_CR); 838 status &= CDNS_UART_CR_RX_DIS; 839 status |= CDNS_UART_CR_RX_EN; 840 writel(status, port->membase + CDNS_UART_CR); 841 842 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 843 * no parity. 844 */ 845 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT 846 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, 847 port->membase + CDNS_UART_MR); 848 849 /* 850 * Set the RX FIFO Trigger level to use most of the FIFO, but it 851 * can be tuned with a module parameter 852 */ 853 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 854 855 /* 856 * Receive Timeout register is enabled but it 857 * can be tuned with a module parameter 858 */ 859 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 860 861 /* Clear out any pending interrupts before enabling them */ 862 writel(readl(port->membase + CDNS_UART_ISR), 863 port->membase + CDNS_UART_ISR); 864 865 spin_unlock_irqrestore(&port->lock, flags); 866 867 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); 868 if (ret) { 869 dev_err(port->dev, "request_irq '%d' failed with %d\n", 870 port->irq, ret); 871 return ret; 872 } 873 874 /* Set the Interrupt Registers with desired interrupts */ 875 if (is_brk_support) 876 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK, 877 port->membase + CDNS_UART_IER); 878 else 879 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER); 880 881 return 0; 882 } 883 884 /** 885 * cdns_uart_shutdown - Called when an application closes a cdns_uart port 886 * @port: Handle to the uart port structure 887 */ 888 static void cdns_uart_shutdown(struct uart_port *port) 889 { 890 int status; 891 unsigned long flags; 892 893 spin_lock_irqsave(&port->lock, flags); 894 895 /* Disable interrupts */ 896 status = readl(port->membase + CDNS_UART_IMR); 897 writel(status, port->membase + CDNS_UART_IDR); 898 writel(0xffffffff, port->membase + CDNS_UART_ISR); 899 900 /* Disable the TX and RX */ 901 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 902 port->membase + CDNS_UART_CR); 903 904 spin_unlock_irqrestore(&port->lock, flags); 905 906 free_irq(port->irq, port); 907 } 908 909 /** 910 * cdns_uart_type - Set UART type to cdns_uart port 911 * @port: Handle to the uart port structure 912 * 913 * Return: string on success, NULL otherwise 914 */ 915 static const char *cdns_uart_type(struct uart_port *port) 916 { 917 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; 918 } 919 920 /** 921 * cdns_uart_verify_port - Verify the port params 922 * @port: Handle to the uart port structure 923 * @ser: Handle to the structure whose members are compared 924 * 925 * Return: 0 on success, negative errno otherwise. 926 */ 927 static int cdns_uart_verify_port(struct uart_port *port, 928 struct serial_struct *ser) 929 { 930 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 931 return -EINVAL; 932 if (port->irq != ser->irq) 933 return -EINVAL; 934 if (ser->io_type != UPIO_MEM) 935 return -EINVAL; 936 if (port->iobase != ser->port) 937 return -EINVAL; 938 if (ser->hub6 != 0) 939 return -EINVAL; 940 return 0; 941 } 942 943 /** 944 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, 945 * called when the driver adds a cdns_uart port via 946 * uart_add_one_port() 947 * @port: Handle to the uart port structure 948 * 949 * Return: 0 on success, negative errno otherwise. 950 */ 951 static int cdns_uart_request_port(struct uart_port *port) 952 { 953 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, 954 CDNS_UART_NAME)) { 955 return -ENOMEM; 956 } 957 958 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); 959 if (!port->membase) { 960 dev_err(port->dev, "Unable to map registers\n"); 961 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 962 return -ENOMEM; 963 } 964 return 0; 965 } 966 967 /** 968 * cdns_uart_release_port - Release UART port 969 * @port: Handle to the uart port structure 970 * 971 * Release the memory region attached to a cdns_uart port. Called when the 972 * driver removes a cdns_uart port via uart_remove_one_port(). 973 */ 974 static void cdns_uart_release_port(struct uart_port *port) 975 { 976 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 977 iounmap(port->membase); 978 port->membase = NULL; 979 } 980 981 /** 982 * cdns_uart_config_port - Configure UART port 983 * @port: Handle to the uart port structure 984 * @flags: If any 985 */ 986 static void cdns_uart_config_port(struct uart_port *port, int flags) 987 { 988 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) 989 port->type = PORT_XUARTPS; 990 } 991 992 /** 993 * cdns_uart_get_mctrl - Get the modem control state 994 * @port: Handle to the uart port structure 995 * 996 * Return: the modem control state 997 */ 998 static unsigned int cdns_uart_get_mctrl(struct uart_port *port) 999 { 1000 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 1001 } 1002 1003 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1004 { 1005 u32 val; 1006 u32 mode_reg; 1007 1008 val = readl(port->membase + CDNS_UART_MODEMCR); 1009 mode_reg = readl(port->membase + CDNS_UART_MR); 1010 1011 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); 1012 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; 1013 1014 if (mctrl & TIOCM_RTS) 1015 val |= CDNS_UART_MODEMCR_RTS; 1016 if (mctrl & TIOCM_DTR) 1017 val |= CDNS_UART_MODEMCR_DTR; 1018 if (mctrl & TIOCM_LOOP) 1019 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; 1020 else 1021 mode_reg |= CDNS_UART_MR_CHMODE_NORM; 1022 1023 writel(val, port->membase + CDNS_UART_MODEMCR); 1024 writel(mode_reg, port->membase + CDNS_UART_MR); 1025 } 1026 1027 #ifdef CONFIG_CONSOLE_POLL 1028 static int cdns_uart_poll_get_char(struct uart_port *port) 1029 { 1030 int c; 1031 unsigned long flags; 1032 1033 spin_lock_irqsave(&port->lock, flags); 1034 1035 /* Check if FIFO is empty */ 1036 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) 1037 c = NO_POLL_CHAR; 1038 else /* Read a character */ 1039 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); 1040 1041 spin_unlock_irqrestore(&port->lock, flags); 1042 1043 return c; 1044 } 1045 1046 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) 1047 { 1048 unsigned long flags; 1049 1050 spin_lock_irqsave(&port->lock, flags); 1051 1052 /* Wait until FIFO is empty */ 1053 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1054 cpu_relax(); 1055 1056 /* Write a character */ 1057 writel(c, port->membase + CDNS_UART_FIFO); 1058 1059 /* Wait until FIFO is empty */ 1060 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1061 cpu_relax(); 1062 1063 spin_unlock_irqrestore(&port->lock, flags); 1064 1065 return; 1066 } 1067 #endif 1068 1069 static void cdns_uart_pm(struct uart_port *port, unsigned int state, 1070 unsigned int oldstate) 1071 { 1072 switch (state) { 1073 case UART_PM_STATE_OFF: 1074 pm_runtime_mark_last_busy(port->dev); 1075 pm_runtime_put_autosuspend(port->dev); 1076 break; 1077 default: 1078 pm_runtime_get_sync(port->dev); 1079 break; 1080 } 1081 } 1082 1083 static const struct uart_ops cdns_uart_ops = { 1084 .set_mctrl = cdns_uart_set_mctrl, 1085 .get_mctrl = cdns_uart_get_mctrl, 1086 .start_tx = cdns_uart_start_tx, 1087 .stop_tx = cdns_uart_stop_tx, 1088 .stop_rx = cdns_uart_stop_rx, 1089 .tx_empty = cdns_uart_tx_empty, 1090 .break_ctl = cdns_uart_break_ctl, 1091 .set_termios = cdns_uart_set_termios, 1092 .startup = cdns_uart_startup, 1093 .shutdown = cdns_uart_shutdown, 1094 .pm = cdns_uart_pm, 1095 .type = cdns_uart_type, 1096 .verify_port = cdns_uart_verify_port, 1097 .request_port = cdns_uart_request_port, 1098 .release_port = cdns_uart_release_port, 1099 .config_port = cdns_uart_config_port, 1100 #ifdef CONFIG_CONSOLE_POLL 1101 .poll_get_char = cdns_uart_poll_get_char, 1102 .poll_put_char = cdns_uart_poll_put_char, 1103 #endif 1104 }; 1105 1106 static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS]; 1107 1108 /** 1109 * cdns_uart_get_port - Configure the port from platform device resource info 1110 * @id: Port id 1111 * 1112 * Return: a pointer to a uart_port or NULL for failure 1113 */ 1114 static struct uart_port *cdns_uart_get_port(int id) 1115 { 1116 struct uart_port *port; 1117 1118 /* Try the given port id if failed use default method */ 1119 if (cdns_uart_port[id].mapbase != 0) { 1120 /* Find the next unused port */ 1121 for (id = 0; id < CDNS_UART_NR_PORTS; id++) 1122 if (cdns_uart_port[id].mapbase == 0) 1123 break; 1124 } 1125 1126 if (id >= CDNS_UART_NR_PORTS) 1127 return NULL; 1128 1129 port = &cdns_uart_port[id]; 1130 1131 /* At this point, we've got an empty uart_port struct, initialize it */ 1132 spin_lock_init(&port->lock); 1133 port->membase = NULL; 1134 port->irq = 0; 1135 port->type = PORT_UNKNOWN; 1136 port->iotype = UPIO_MEM32; 1137 port->flags = UPF_BOOT_AUTOCONF; 1138 port->ops = &cdns_uart_ops; 1139 port->fifosize = CDNS_UART_FIFO_SIZE; 1140 port->line = id; 1141 port->dev = NULL; 1142 return port; 1143 } 1144 1145 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1146 /** 1147 * cdns_uart_console_wait_tx - Wait for the TX to be full 1148 * @port: Handle to the uart port structure 1149 */ 1150 static void cdns_uart_console_wait_tx(struct uart_port *port) 1151 { 1152 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1153 barrier(); 1154 } 1155 1156 /** 1157 * cdns_uart_console_putchar - write the character to the FIFO buffer 1158 * @port: Handle to the uart port structure 1159 * @ch: Character to be written 1160 */ 1161 static void cdns_uart_console_putchar(struct uart_port *port, int ch) 1162 { 1163 cdns_uart_console_wait_tx(port); 1164 writel(ch, port->membase + CDNS_UART_FIFO); 1165 } 1166 1167 static void cdns_early_write(struct console *con, const char *s, 1168 unsigned n) 1169 { 1170 struct earlycon_device *dev = con->data; 1171 1172 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); 1173 } 1174 1175 static int __init cdns_early_console_setup(struct earlycon_device *device, 1176 const char *opt) 1177 { 1178 struct uart_port *port = &device->port; 1179 1180 if (!port->membase) 1181 return -ENODEV; 1182 1183 /* initialise control register */ 1184 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST, 1185 port->membase + CDNS_UART_CR); 1186 1187 /* only set baud if specified on command line - otherwise 1188 * assume it has been initialized by a boot loader. 1189 */ 1190 if (device->baud) { 1191 u32 cd = 0, bdiv = 0; 1192 u32 mr; 1193 int div8; 1194 1195 cdns_uart_calc_baud_divs(port->uartclk, device->baud, 1196 &bdiv, &cd, &div8); 1197 mr = CDNS_UART_MR_PARITY_NONE; 1198 if (div8) 1199 mr |= CDNS_UART_MR_CLKSEL; 1200 1201 writel(mr, port->membase + CDNS_UART_MR); 1202 writel(cd, port->membase + CDNS_UART_BAUDGEN); 1203 writel(bdiv, port->membase + CDNS_UART_BAUDDIV); 1204 } 1205 1206 device->con->write = cdns_early_write; 1207 1208 return 0; 1209 } 1210 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); 1211 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); 1212 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); 1213 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); 1214 1215 /** 1216 * cdns_uart_console_write - perform write operation 1217 * @co: Console handle 1218 * @s: Pointer to character array 1219 * @count: No of characters 1220 */ 1221 static void cdns_uart_console_write(struct console *co, const char *s, 1222 unsigned int count) 1223 { 1224 struct uart_port *port = &cdns_uart_port[co->index]; 1225 unsigned long flags; 1226 unsigned int imr, ctrl; 1227 int locked = 1; 1228 1229 if (port->sysrq) 1230 locked = 0; 1231 else if (oops_in_progress) 1232 locked = spin_trylock_irqsave(&port->lock, flags); 1233 else 1234 spin_lock_irqsave(&port->lock, flags); 1235 1236 /* save and disable interrupt */ 1237 imr = readl(port->membase + CDNS_UART_IMR); 1238 writel(imr, port->membase + CDNS_UART_IDR); 1239 1240 /* 1241 * Make sure that the tx part is enabled. Set the TX enable bit and 1242 * clear the TX disable bit to enable the transmitter. 1243 */ 1244 ctrl = readl(port->membase + CDNS_UART_CR); 1245 ctrl &= ~CDNS_UART_CR_TX_DIS; 1246 ctrl |= CDNS_UART_CR_TX_EN; 1247 writel(ctrl, port->membase + CDNS_UART_CR); 1248 1249 uart_console_write(port, s, count, cdns_uart_console_putchar); 1250 cdns_uart_console_wait_tx(port); 1251 1252 writel(ctrl, port->membase + CDNS_UART_CR); 1253 1254 /* restore interrupt state */ 1255 writel(imr, port->membase + CDNS_UART_IER); 1256 1257 if (locked) 1258 spin_unlock_irqrestore(&port->lock, flags); 1259 } 1260 1261 /** 1262 * cdns_uart_console_setup - Initialize the uart to default config 1263 * @co: Console handle 1264 * @options: Initial settings of uart 1265 * 1266 * Return: 0 on success, negative errno otherwise. 1267 */ 1268 static int __init cdns_uart_console_setup(struct console *co, char *options) 1269 { 1270 struct uart_port *port = &cdns_uart_port[co->index]; 1271 int baud = 9600; 1272 int bits = 8; 1273 int parity = 'n'; 1274 int flow = 'n'; 1275 1276 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) 1277 return -EINVAL; 1278 1279 if (!port->membase) { 1280 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", 1281 co->index); 1282 return -ENODEV; 1283 } 1284 1285 if (options) 1286 uart_parse_options(options, &baud, &parity, &bits, &flow); 1287 1288 return uart_set_options(port, co, baud, parity, bits, flow); 1289 } 1290 1291 static struct uart_driver cdns_uart_uart_driver; 1292 1293 static struct console cdns_uart_console = { 1294 .name = CDNS_UART_TTY_NAME, 1295 .write = cdns_uart_console_write, 1296 .device = uart_console_device, 1297 .setup = cdns_uart_console_setup, 1298 .flags = CON_PRINTBUFFER, 1299 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1300 .data = &cdns_uart_uart_driver, 1301 }; 1302 1303 /** 1304 * cdns_uart_console_init - Initialization call 1305 * 1306 * Return: 0 on success, negative errno otherwise 1307 */ 1308 static int __init cdns_uart_console_init(void) 1309 { 1310 register_console(&cdns_uart_console); 1311 return 0; 1312 } 1313 1314 console_initcall(cdns_uart_console_init); 1315 1316 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1317 1318 static struct uart_driver cdns_uart_uart_driver = { 1319 .owner = THIS_MODULE, 1320 .driver_name = CDNS_UART_NAME, 1321 .dev_name = CDNS_UART_TTY_NAME, 1322 .major = CDNS_UART_MAJOR, 1323 .minor = CDNS_UART_MINOR, 1324 .nr = CDNS_UART_NR_PORTS, 1325 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1326 .cons = &cdns_uart_console, 1327 #endif 1328 }; 1329 1330 #ifdef CONFIG_PM_SLEEP 1331 /** 1332 * cdns_uart_suspend - suspend event 1333 * @device: Pointer to the device structure 1334 * 1335 * Return: 0 1336 */ 1337 static int cdns_uart_suspend(struct device *device) 1338 { 1339 struct uart_port *port = dev_get_drvdata(device); 1340 struct tty_struct *tty; 1341 struct device *tty_dev; 1342 int may_wake = 0; 1343 1344 /* Get the tty which could be NULL so don't assume it's valid */ 1345 tty = tty_port_tty_get(&port->state->port); 1346 if (tty) { 1347 tty_dev = tty->dev; 1348 may_wake = device_may_wakeup(tty_dev); 1349 tty_kref_put(tty); 1350 } 1351 1352 /* 1353 * Call the API provided in serial_core.c file which handles 1354 * the suspend. 1355 */ 1356 uart_suspend_port(&cdns_uart_uart_driver, port); 1357 if (!(console_suspend_enabled && !may_wake)) { 1358 unsigned long flags = 0; 1359 1360 spin_lock_irqsave(&port->lock, flags); 1361 /* Empty the receive FIFO 1st before making changes */ 1362 while (!(readl(port->membase + CDNS_UART_SR) & 1363 CDNS_UART_SR_RXEMPTY)) 1364 readl(port->membase + CDNS_UART_FIFO); 1365 /* set RX trigger level to 1 */ 1366 writel(1, port->membase + CDNS_UART_RXWM); 1367 /* disable RX timeout interrups */ 1368 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); 1369 spin_unlock_irqrestore(&port->lock, flags); 1370 } 1371 1372 return 0; 1373 } 1374 1375 /** 1376 * cdns_uart_resume - Resume after a previous suspend 1377 * @device: Pointer to the device structure 1378 * 1379 * Return: 0 1380 */ 1381 static int cdns_uart_resume(struct device *device) 1382 { 1383 struct uart_port *port = dev_get_drvdata(device); 1384 unsigned long flags = 0; 1385 u32 ctrl_reg; 1386 struct tty_struct *tty; 1387 struct device *tty_dev; 1388 int may_wake = 0; 1389 1390 /* Get the tty which could be NULL so don't assume it's valid */ 1391 tty = tty_port_tty_get(&port->state->port); 1392 if (tty) { 1393 tty_dev = tty->dev; 1394 may_wake = device_may_wakeup(tty_dev); 1395 tty_kref_put(tty); 1396 } 1397 1398 if (console_suspend_enabled && !may_wake) { 1399 struct cdns_uart *cdns_uart = port->private_data; 1400 1401 clk_enable(cdns_uart->pclk); 1402 clk_enable(cdns_uart->uartclk); 1403 1404 spin_lock_irqsave(&port->lock, flags); 1405 1406 /* Set TX/RX Reset */ 1407 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1408 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 1409 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1410 while (readl(port->membase + CDNS_UART_CR) & 1411 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 1412 cpu_relax(); 1413 1414 /* restore rx timeout value */ 1415 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); 1416 /* Enable Tx/Rx */ 1417 ctrl_reg = readl(port->membase + CDNS_UART_CR); 1418 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 1419 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 1420 writel(ctrl_reg, port->membase + CDNS_UART_CR); 1421 1422 clk_disable(cdns_uart->uartclk); 1423 clk_disable(cdns_uart->pclk); 1424 spin_unlock_irqrestore(&port->lock, flags); 1425 } else { 1426 spin_lock_irqsave(&port->lock, flags); 1427 /* restore original rx trigger level */ 1428 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 1429 /* enable RX timeout interrupt */ 1430 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); 1431 spin_unlock_irqrestore(&port->lock, flags); 1432 } 1433 1434 return uart_resume_port(&cdns_uart_uart_driver, port); 1435 } 1436 #endif /* ! CONFIG_PM_SLEEP */ 1437 static int __maybe_unused cdns_runtime_suspend(struct device *dev) 1438 { 1439 struct platform_device *pdev = to_platform_device(dev); 1440 struct uart_port *port = platform_get_drvdata(pdev); 1441 struct cdns_uart *cdns_uart = port->private_data; 1442 1443 clk_disable(cdns_uart->uartclk); 1444 clk_disable(cdns_uart->pclk); 1445 return 0; 1446 }; 1447 1448 static int __maybe_unused cdns_runtime_resume(struct device *dev) 1449 { 1450 struct platform_device *pdev = to_platform_device(dev); 1451 struct uart_port *port = platform_get_drvdata(pdev); 1452 struct cdns_uart *cdns_uart = port->private_data; 1453 1454 clk_enable(cdns_uart->pclk); 1455 clk_enable(cdns_uart->uartclk); 1456 return 0; 1457 }; 1458 1459 static const struct dev_pm_ops cdns_uart_dev_pm_ops = { 1460 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume) 1461 SET_RUNTIME_PM_OPS(cdns_runtime_suspend, 1462 cdns_runtime_resume, NULL) 1463 }; 1464 1465 static const struct cdns_platform_data zynqmp_uart_def = { 1466 .quirks = CDNS_UART_RXBS_SUPPORT, }; 1467 1468 /* Match table for of_platform binding */ 1469 static const struct of_device_id cdns_uart_of_match[] = { 1470 { .compatible = "xlnx,xuartps", }, 1471 { .compatible = "cdns,uart-r1p8", }, 1472 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, 1473 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, 1474 {} 1475 }; 1476 MODULE_DEVICE_TABLE(of, cdns_uart_of_match); 1477 1478 /** 1479 * cdns_uart_probe - Platform driver probe 1480 * @pdev: Pointer to the platform device structure 1481 * 1482 * Return: 0 on success, negative errno otherwise 1483 */ 1484 static int cdns_uart_probe(struct platform_device *pdev) 1485 { 1486 int rc, id, irq; 1487 struct uart_port *port; 1488 struct resource *res; 1489 struct cdns_uart *cdns_uart_data; 1490 const struct of_device_id *match; 1491 1492 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), 1493 GFP_KERNEL); 1494 if (!cdns_uart_data) 1495 return -ENOMEM; 1496 1497 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node); 1498 if (match && match->data) { 1499 const struct cdns_platform_data *data = match->data; 1500 1501 cdns_uart_data->quirks = data->quirks; 1502 } 1503 1504 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); 1505 if (IS_ERR(cdns_uart_data->pclk)) { 1506 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); 1507 if (!IS_ERR(cdns_uart_data->pclk)) 1508 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); 1509 } 1510 if (IS_ERR(cdns_uart_data->pclk)) { 1511 dev_err(&pdev->dev, "pclk clock not found.\n"); 1512 return PTR_ERR(cdns_uart_data->pclk); 1513 } 1514 1515 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); 1516 if (IS_ERR(cdns_uart_data->uartclk)) { 1517 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); 1518 if (!IS_ERR(cdns_uart_data->uartclk)) 1519 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); 1520 } 1521 if (IS_ERR(cdns_uart_data->uartclk)) { 1522 dev_err(&pdev->dev, "uart_clk clock not found.\n"); 1523 return PTR_ERR(cdns_uart_data->uartclk); 1524 } 1525 1526 rc = clk_prepare_enable(cdns_uart_data->pclk); 1527 if (rc) { 1528 dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); 1529 return rc; 1530 } 1531 rc = clk_prepare_enable(cdns_uart_data->uartclk); 1532 if (rc) { 1533 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1534 goto err_out_clk_dis_pclk; 1535 } 1536 1537 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1538 if (!res) { 1539 rc = -ENODEV; 1540 goto err_out_clk_disable; 1541 } 1542 1543 irq = platform_get_irq(pdev, 0); 1544 if (irq <= 0) { 1545 rc = -ENXIO; 1546 goto err_out_clk_disable; 1547 } 1548 1549 #ifdef CONFIG_COMMON_CLK 1550 cdns_uart_data->clk_rate_change_nb.notifier_call = 1551 cdns_uart_clk_notifier_cb; 1552 if (clk_notifier_register(cdns_uart_data->uartclk, 1553 &cdns_uart_data->clk_rate_change_nb)) 1554 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1555 #endif 1556 /* Look for a serialN alias */ 1557 id = of_alias_get_id(pdev->dev.of_node, "serial"); 1558 if (id < 0) 1559 id = 0; 1560 1561 /* Initialize the port structure */ 1562 port = cdns_uart_get_port(id); 1563 1564 if (!port) { 1565 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1566 rc = -ENODEV; 1567 goto err_out_notif_unreg; 1568 } 1569 1570 /* 1571 * Register the port. 1572 * This function also registers this device with the tty layer 1573 * and triggers invocation of the config_port() entry point. 1574 */ 1575 port->mapbase = res->start; 1576 port->irq = irq; 1577 port->dev = &pdev->dev; 1578 port->uartclk = clk_get_rate(cdns_uart_data->uartclk); 1579 port->private_data = cdns_uart_data; 1580 cdns_uart_data->port = port; 1581 platform_set_drvdata(pdev, port); 1582 1583 pm_runtime_use_autosuspend(&pdev->dev); 1584 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 1585 pm_runtime_set_active(&pdev->dev); 1586 pm_runtime_enable(&pdev->dev); 1587 1588 rc = uart_add_one_port(&cdns_uart_uart_driver, port); 1589 if (rc) { 1590 dev_err(&pdev->dev, 1591 "uart_add_one_port() failed; err=%i\n", rc); 1592 goto err_out_pm_disable; 1593 } 1594 1595 return 0; 1596 1597 err_out_pm_disable: 1598 pm_runtime_disable(&pdev->dev); 1599 pm_runtime_set_suspended(&pdev->dev); 1600 pm_runtime_dont_use_autosuspend(&pdev->dev); 1601 err_out_notif_unreg: 1602 #ifdef CONFIG_COMMON_CLK 1603 clk_notifier_unregister(cdns_uart_data->uartclk, 1604 &cdns_uart_data->clk_rate_change_nb); 1605 #endif 1606 err_out_clk_disable: 1607 clk_disable_unprepare(cdns_uart_data->uartclk); 1608 err_out_clk_dis_pclk: 1609 clk_disable_unprepare(cdns_uart_data->pclk); 1610 1611 return rc; 1612 } 1613 1614 /** 1615 * cdns_uart_remove - called when the platform driver is unregistered 1616 * @pdev: Pointer to the platform device structure 1617 * 1618 * Return: 0 on success, negative errno otherwise 1619 */ 1620 static int cdns_uart_remove(struct platform_device *pdev) 1621 { 1622 struct uart_port *port = platform_get_drvdata(pdev); 1623 struct cdns_uart *cdns_uart_data = port->private_data; 1624 int rc; 1625 1626 /* Remove the cdns_uart port from the serial core */ 1627 #ifdef CONFIG_COMMON_CLK 1628 clk_notifier_unregister(cdns_uart_data->uartclk, 1629 &cdns_uart_data->clk_rate_change_nb); 1630 #endif 1631 rc = uart_remove_one_port(&cdns_uart_uart_driver, port); 1632 port->mapbase = 0; 1633 clk_disable_unprepare(cdns_uart_data->uartclk); 1634 clk_disable_unprepare(cdns_uart_data->pclk); 1635 pm_runtime_disable(&pdev->dev); 1636 pm_runtime_set_suspended(&pdev->dev); 1637 pm_runtime_dont_use_autosuspend(&pdev->dev); 1638 return rc; 1639 } 1640 1641 static struct platform_driver cdns_uart_platform_driver = { 1642 .probe = cdns_uart_probe, 1643 .remove = cdns_uart_remove, 1644 .driver = { 1645 .name = CDNS_UART_NAME, 1646 .of_match_table = cdns_uart_of_match, 1647 .pm = &cdns_uart_dev_pm_ops, 1648 }, 1649 }; 1650 1651 static int __init cdns_uart_init(void) 1652 { 1653 int retval = 0; 1654 1655 /* Register the cdns_uart driver with the serial core */ 1656 retval = uart_register_driver(&cdns_uart_uart_driver); 1657 if (retval) 1658 return retval; 1659 1660 /* Register the platform driver */ 1661 retval = platform_driver_register(&cdns_uart_platform_driver); 1662 if (retval) 1663 uart_unregister_driver(&cdns_uart_uart_driver); 1664 1665 return retval; 1666 } 1667 1668 static void __exit cdns_uart_exit(void) 1669 { 1670 /* Unregister the platform driver */ 1671 platform_driver_unregister(&cdns_uart_platform_driver); 1672 1673 /* Unregister the cdns_uart driver */ 1674 uart_unregister_driver(&cdns_uart_uart_driver); 1675 } 1676 1677 arch_initcall(cdns_uart_init); 1678 module_exit(cdns_uart_exit); 1679 1680 MODULE_DESCRIPTION("Driver for Cadence UART"); 1681 MODULE_AUTHOR("Xilinx Inc."); 1682 MODULE_LICENSE("GPL"); 1683