1 /* 2 * Xilinx PS UART driver 3 * 4 * 2011 (c) Xilinx Inc. 5 * 6 * This program is free software; you can redistribute it 7 * and/or modify it under the terms of the GNU General Public 8 * License as published by the Free Software Foundation; 9 * either version 2 of the License, or (at your option) any 10 * later version. 11 * 12 */ 13 14 #include <linux/platform_device.h> 15 #include <linux/serial.h> 16 #include <linux/serial_core.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/console.h> 20 #include <linux/clk.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/module.h> 25 26 #define XUARTPS_TTY_NAME "ttyPS" 27 #define XUARTPS_NAME "xuartps" 28 #define XUARTPS_MAJOR 0 /* use dynamic node allocation */ 29 #define XUARTPS_MINOR 0 /* works best with devtmpfs */ 30 #define XUARTPS_NR_PORTS 2 31 #define XUARTPS_FIFO_SIZE 16 /* FIFO size */ 32 #define XUARTPS_REGISTER_SPACE 0xFFF 33 34 #define xuartps_readl(offset) ioread32(port->membase + offset) 35 #define xuartps_writel(val, offset) iowrite32(val, port->membase + offset) 36 37 /********************************Register Map********************************/ 38 /** UART 39 * 40 * Register offsets for the UART. 41 * 42 */ 43 #define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */ 44 #define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */ 45 #define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */ 46 #define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */ 47 #define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */ 48 #define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/ 49 #define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */ 50 #define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */ 51 #define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */ 52 #define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */ 53 #define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */ 54 #define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */ 55 #define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ 56 #define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */ 57 #define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */ 58 #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse 59 Width [15:0] */ 60 #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse 61 Width [7:0] */ 62 #define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */ 63 64 /** Control Register 65 * 66 * The Control register (CR) controls the major functions of the device. 67 * 68 * Control Register Bit Definitions 69 */ 70 #define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */ 71 #define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */ 72 #define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */ 73 #define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */ 74 #define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */ 75 #define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */ 76 #define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */ 77 #define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */ 78 #define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 79 80 /** Mode Register 81 * 82 * The mode register (MR) defines the mode of transfer as well as the data 83 * format. If this register is modified during transmission or reception, 84 * data validity cannot be guaranteed. 85 * 86 * Mode Register Bit Definitions 87 * 88 */ 89 #define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 90 #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 91 #define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 92 93 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 94 #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 95 96 #define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */ 97 #define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 98 #define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 99 #define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 100 #define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 101 102 #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 103 #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 104 #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 105 106 /** Interrupt Registers 107 * 108 * Interrupt control logic uses the interrupt enable register (IER) and the 109 * interrupt disable register (IDR) to set the value of the bits in the 110 * interrupt mask register (IMR). The IMR determines whether to pass an 111 * interrupt to the interrupt status register (ISR). 112 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 113 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 114 * Reading either IER or IDR returns 0x00. 115 * 116 * All four registers have the same bit definitions. 117 */ 118 #define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 119 #define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */ 120 #define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 121 #define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 122 #define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 123 #define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 124 #define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 125 #define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 126 #define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 127 #define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 128 #define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */ 129 130 /** Channel Status Register 131 * 132 * The channel status register (CSR) is provided to enable the control logic 133 * to monitor the status of bits in the channel interrupt status register, 134 * even if these are masked out by the interrupt mask register. 135 */ 136 #define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 137 #define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 138 #define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */ 139 #define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */ 140 141 /** 142 * xuartps_isr - Interrupt handler 143 * @irq: Irq number 144 * @dev_id: Id of the port 145 * 146 * Returns IRQHANDLED 147 **/ 148 static irqreturn_t xuartps_isr(int irq, void *dev_id) 149 { 150 struct uart_port *port = (struct uart_port *)dev_id; 151 unsigned long flags; 152 unsigned int isrstatus, numbytes; 153 unsigned int data; 154 char status = TTY_NORMAL; 155 156 spin_lock_irqsave(&port->lock, flags); 157 158 /* Read the interrupt status register to determine which 159 * interrupt(s) is/are active. 160 */ 161 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET); 162 163 /* drop byte with parity error if IGNPAR specified */ 164 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY) 165 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT); 166 167 isrstatus &= port->read_status_mask; 168 isrstatus &= ~port->ignore_status_mask; 169 170 if ((isrstatus & XUARTPS_IXR_TOUT) || 171 (isrstatus & XUARTPS_IXR_RXTRIG)) { 172 /* Receive Timeout Interrupt */ 173 while ((xuartps_readl(XUARTPS_SR_OFFSET) & 174 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { 175 data = xuartps_readl(XUARTPS_FIFO_OFFSET); 176 port->icount.rx++; 177 178 if (isrstatus & XUARTPS_IXR_PARITY) { 179 port->icount.parity++; 180 status = TTY_PARITY; 181 } else if (isrstatus & XUARTPS_IXR_FRAMING) { 182 port->icount.frame++; 183 status = TTY_FRAME; 184 } else if (isrstatus & XUARTPS_IXR_OVERRUN) 185 port->icount.overrun++; 186 187 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN, 188 data, status); 189 } 190 spin_unlock(&port->lock); 191 tty_flip_buffer_push(&port->state->port); 192 spin_lock(&port->lock); 193 } 194 195 /* Dispatch an appropriate handler */ 196 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) { 197 if (uart_circ_empty(&port->state->xmit)) { 198 xuartps_writel(XUARTPS_IXR_TXEMPTY, 199 XUARTPS_IDR_OFFSET); 200 } else { 201 numbytes = port->fifosize; 202 /* Break if no more data available in the UART buffer */ 203 while (numbytes--) { 204 if (uart_circ_empty(&port->state->xmit)) 205 break; 206 /* Get the data from the UART circular buffer 207 * and write it to the xuartps's TX_FIFO 208 * register. 209 */ 210 xuartps_writel( 211 port->state->xmit.buf[port->state->xmit. 212 tail], XUARTPS_FIFO_OFFSET); 213 214 port->icount.tx++; 215 216 /* Adjust the tail of the UART buffer and wrap 217 * the buffer if it reaches limit. 218 */ 219 port->state->xmit.tail = 220 (port->state->xmit.tail + 1) & \ 221 (UART_XMIT_SIZE - 1); 222 } 223 224 if (uart_circ_chars_pending( 225 &port->state->xmit) < WAKEUP_CHARS) 226 uart_write_wakeup(port); 227 } 228 } 229 230 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET); 231 232 /* be sure to release the lock and tty before leaving */ 233 spin_unlock_irqrestore(&port->lock, flags); 234 235 return IRQ_HANDLED; 236 } 237 238 /** 239 * xuartps_set_baud_rate - Calculate and set the baud rate 240 * @port: Handle to the uart port structure 241 * @baud: Baud rate to set 242 * 243 * Returns baud rate, requested baud when possible, or actual baud when there 244 * was too much error 245 **/ 246 static unsigned int xuartps_set_baud_rate(struct uart_port *port, 247 unsigned int baud) 248 { 249 unsigned int sel_clk; 250 unsigned int calc_baud = 0; 251 unsigned int brgr_val, brdiv_val; 252 unsigned int bauderror; 253 254 /* Formula to obtain baud rate is 255 * baud_tx/rx rate = sel_clk/CD * (BDIV + 1) 256 * input_clk = (Uart User Defined Clock or Apb Clock) 257 * depends on UCLKEN in MR Reg 258 * sel_clk = input_clk or input_clk/8; 259 * depends on CLKS in MR reg 260 * CD and BDIV depends on values in 261 * baud rate generate register 262 * baud rate clock divisor register 263 */ 264 sel_clk = port->uartclk; 265 if (xuartps_readl(XUARTPS_MR_OFFSET) & XUARTPS_MR_CLKSEL) 266 sel_clk = sel_clk / 8; 267 268 /* Find the best values for baud generation */ 269 for (brdiv_val = 4; brdiv_val < 255; brdiv_val++) { 270 271 brgr_val = sel_clk / (baud * (brdiv_val + 1)); 272 if (brgr_val < 2 || brgr_val > 65535) 273 continue; 274 275 calc_baud = sel_clk / (brgr_val * (brdiv_val + 1)); 276 277 if (baud > calc_baud) 278 bauderror = baud - calc_baud; 279 else 280 bauderror = calc_baud - baud; 281 282 /* use the values when percent error is acceptable */ 283 if (((bauderror * 100) / baud) < 3) { 284 calc_baud = baud; 285 break; 286 } 287 } 288 289 /* Set the values for the new baud rate */ 290 xuartps_writel(brgr_val, XUARTPS_BAUDGEN_OFFSET); 291 xuartps_writel(brdiv_val, XUARTPS_BAUDDIV_OFFSET); 292 293 return calc_baud; 294 } 295 296 /*----------------------Uart Operations---------------------------*/ 297 298 /** 299 * xuartps_start_tx - Start transmitting bytes 300 * @port: Handle to the uart port structure 301 * 302 **/ 303 static void xuartps_start_tx(struct uart_port *port) 304 { 305 unsigned int status, numbytes = port->fifosize; 306 307 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) 308 return; 309 310 status = xuartps_readl(XUARTPS_CR_OFFSET); 311 /* Set the TX enable bit and clear the TX disable bit to enable the 312 * transmitter. 313 */ 314 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, 315 XUARTPS_CR_OFFSET); 316 317 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET) 318 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) { 319 320 /* Break if no more data available in the UART buffer */ 321 if (uart_circ_empty(&port->state->xmit)) 322 break; 323 324 /* Get the data from the UART circular buffer and 325 * write it to the xuartps's TX_FIFO register. 326 */ 327 xuartps_writel( 328 port->state->xmit.buf[port->state->xmit.tail], 329 XUARTPS_FIFO_OFFSET); 330 port->icount.tx++; 331 332 /* Adjust the tail of the UART buffer and wrap 333 * the buffer if it reaches limit. 334 */ 335 port->state->xmit.tail = (port->state->xmit.tail + 1) & 336 (UART_XMIT_SIZE - 1); 337 } 338 339 /* Enable the TX Empty interrupt */ 340 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET); 341 342 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) 343 uart_write_wakeup(port); 344 } 345 346 /** 347 * xuartps_stop_tx - Stop TX 348 * @port: Handle to the uart port structure 349 * 350 **/ 351 static void xuartps_stop_tx(struct uart_port *port) 352 { 353 unsigned int regval; 354 355 regval = xuartps_readl(XUARTPS_CR_OFFSET); 356 regval |= XUARTPS_CR_TX_DIS; 357 /* Disable the transmitter */ 358 xuartps_writel(regval, XUARTPS_CR_OFFSET); 359 } 360 361 /** 362 * xuartps_stop_rx - Stop RX 363 * @port: Handle to the uart port structure 364 * 365 **/ 366 static void xuartps_stop_rx(struct uart_port *port) 367 { 368 unsigned int regval; 369 370 regval = xuartps_readl(XUARTPS_CR_OFFSET); 371 regval |= XUARTPS_CR_RX_DIS; 372 /* Disable the receiver */ 373 xuartps_writel(regval, XUARTPS_CR_OFFSET); 374 } 375 376 /** 377 * xuartps_tx_empty - Check whether TX is empty 378 * @port: Handle to the uart port structure 379 * 380 * Returns TIOCSER_TEMT on success, 0 otherwise 381 **/ 382 static unsigned int xuartps_tx_empty(struct uart_port *port) 383 { 384 unsigned int status; 385 386 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY; 387 return status ? TIOCSER_TEMT : 0; 388 } 389 390 /** 391 * xuartps_break_ctl - Based on the input ctl we have to start or stop 392 * transmitting char breaks 393 * @port: Handle to the uart port structure 394 * @ctl: Value based on which start or stop decision is taken 395 * 396 **/ 397 static void xuartps_break_ctl(struct uart_port *port, int ctl) 398 { 399 unsigned int status; 400 unsigned long flags; 401 402 spin_lock_irqsave(&port->lock, flags); 403 404 status = xuartps_readl(XUARTPS_CR_OFFSET); 405 406 if (ctl == -1) 407 xuartps_writel(XUARTPS_CR_STARTBRK | status, 408 XUARTPS_CR_OFFSET); 409 else { 410 if ((status & XUARTPS_CR_STOPBRK) == 0) 411 xuartps_writel(XUARTPS_CR_STOPBRK | status, 412 XUARTPS_CR_OFFSET); 413 } 414 spin_unlock_irqrestore(&port->lock, flags); 415 } 416 417 /** 418 * xuartps_set_termios - termios operations, handling data length, parity, 419 * stop bits, flow control, baud rate 420 * @port: Handle to the uart port structure 421 * @termios: Handle to the input termios structure 422 * @old: Values of the previously saved termios structure 423 * 424 **/ 425 static void xuartps_set_termios(struct uart_port *port, 426 struct ktermios *termios, struct ktermios *old) 427 { 428 unsigned int cval = 0; 429 unsigned int baud; 430 unsigned long flags; 431 unsigned int ctrl_reg, mode_reg; 432 433 spin_lock_irqsave(&port->lock, flags); 434 435 /* Empty the receive FIFO 1st before making changes */ 436 while ((xuartps_readl(XUARTPS_SR_OFFSET) & 437 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { 438 xuartps_readl(XUARTPS_FIFO_OFFSET); 439 } 440 441 /* Disable the TX and RX to set baud rate */ 442 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 443 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), 444 XUARTPS_CR_OFFSET); 445 446 /* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk */ 447 baud = uart_get_baud_rate(port, termios, old, 0, 10000000); 448 baud = xuartps_set_baud_rate(port, baud); 449 if (tty_termios_baud_rate(termios)) 450 tty_termios_encode_baud_rate(termios, baud, baud); 451 452 /* 453 * Update the per-port timeout. 454 */ 455 uart_update_timeout(port, termios->c_cflag, baud); 456 457 /* Set TX/RX Reset */ 458 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 459 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), 460 XUARTPS_CR_OFFSET); 461 462 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); 463 464 /* Clear the RX disable and TX disable bits and then set the TX enable 465 * bit and RX enable bit to enable the transmitter and receiver. 466 */ 467 xuartps_writel( 468 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) 469 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), 470 XUARTPS_CR_OFFSET); 471 472 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET); 473 474 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG | 475 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT; 476 port->ignore_status_mask = 0; 477 478 if (termios->c_iflag & INPCK) 479 port->read_status_mask |= XUARTPS_IXR_PARITY | 480 XUARTPS_IXR_FRAMING; 481 482 if (termios->c_iflag & IGNPAR) 483 port->ignore_status_mask |= XUARTPS_IXR_PARITY | 484 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; 485 486 /* ignore all characters if CREAD is not set */ 487 if ((termios->c_cflag & CREAD) == 0) 488 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG | 489 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY | 490 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; 491 492 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET); 493 494 /* Handling Data Size */ 495 switch (termios->c_cflag & CSIZE) { 496 case CS6: 497 cval |= XUARTPS_MR_CHARLEN_6_BIT; 498 break; 499 case CS7: 500 cval |= XUARTPS_MR_CHARLEN_7_BIT; 501 break; 502 default: 503 case CS8: 504 cval |= XUARTPS_MR_CHARLEN_8_BIT; 505 termios->c_cflag &= ~CSIZE; 506 termios->c_cflag |= CS8; 507 break; 508 } 509 510 /* Handling Parity and Stop Bits length */ 511 if (termios->c_cflag & CSTOPB) 512 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 513 else 514 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 515 516 if (termios->c_cflag & PARENB) { 517 /* Mark or Space parity */ 518 if (termios->c_cflag & CMSPAR) { 519 if (termios->c_cflag & PARODD) 520 cval |= XUARTPS_MR_PARITY_MARK; 521 else 522 cval |= XUARTPS_MR_PARITY_SPACE; 523 } else if (termios->c_cflag & PARODD) 524 cval |= XUARTPS_MR_PARITY_ODD; 525 else 526 cval |= XUARTPS_MR_PARITY_EVEN; 527 } else 528 cval |= XUARTPS_MR_PARITY_NONE; 529 xuartps_writel(cval , XUARTPS_MR_OFFSET); 530 531 spin_unlock_irqrestore(&port->lock, flags); 532 } 533 534 /** 535 * xuartps_startup - Called when an application opens a xuartps port 536 * @port: Handle to the uart port structure 537 * 538 * Returns 0 on success, negative error otherwise 539 **/ 540 static int xuartps_startup(struct uart_port *port) 541 { 542 unsigned int retval = 0, status = 0; 543 544 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME, 545 (void *)port); 546 if (retval) 547 return retval; 548 549 /* Disable the TX and RX */ 550 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, 551 XUARTPS_CR_OFFSET); 552 553 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 554 * no break chars. 555 */ 556 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST, 557 XUARTPS_CR_OFFSET); 558 559 status = xuartps_readl(XUARTPS_CR_OFFSET); 560 561 /* Clear the RX disable and TX disable bits and then set the TX enable 562 * bit and RX enable bit to enable the transmitter and receiver. 563 */ 564 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) 565 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN | 566 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET); 567 568 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 569 * no parity. 570 */ 571 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT 572 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT, 573 XUARTPS_MR_OFFSET); 574 575 /* Set the RX FIFO Trigger level to 14 assuming FIFO size as 16 */ 576 xuartps_writel(14, XUARTPS_RXWM_OFFSET); 577 578 /* Receive Timeout register is enabled with value of 10 */ 579 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET); 580 581 /* Clear out any pending interrupts before enabling them */ 582 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET); 583 584 /* Set the Interrupt Registers with desired interrupts */ 585 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY | 586 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN | 587 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); 588 xuartps_writel(~(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY | 589 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN | 590 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT), XUARTPS_IDR_OFFSET); 591 592 return retval; 593 } 594 595 /** 596 * xuartps_shutdown - Called when an application closes a xuartps port 597 * @port: Handle to the uart port structure 598 * 599 **/ 600 static void xuartps_shutdown(struct uart_port *port) 601 { 602 int status; 603 604 /* Disable interrupts */ 605 status = xuartps_readl(XUARTPS_IMR_OFFSET); 606 xuartps_writel(status, XUARTPS_IDR_OFFSET); 607 608 /* Disable the TX and RX */ 609 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, 610 XUARTPS_CR_OFFSET); 611 free_irq(port->irq, port); 612 } 613 614 /** 615 * xuartps_type - Set UART type to xuartps port 616 * @port: Handle to the uart port structure 617 * 618 * Returns string on success, NULL otherwise 619 **/ 620 static const char *xuartps_type(struct uart_port *port) 621 { 622 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL; 623 } 624 625 /** 626 * xuartps_verify_port - Verify the port params 627 * @port: Handle to the uart port structure 628 * @ser: Handle to the structure whose members are compared 629 * 630 * Returns 0 if success otherwise -EINVAL 631 **/ 632 static int xuartps_verify_port(struct uart_port *port, 633 struct serial_struct *ser) 634 { 635 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 636 return -EINVAL; 637 if (port->irq != ser->irq) 638 return -EINVAL; 639 if (ser->io_type != UPIO_MEM) 640 return -EINVAL; 641 if (port->iobase != ser->port) 642 return -EINVAL; 643 if (ser->hub6 != 0) 644 return -EINVAL; 645 return 0; 646 } 647 648 /** 649 * xuartps_request_port - Claim the memory region attached to xuartps port, 650 * called when the driver adds a xuartps port via 651 * uart_add_one_port() 652 * @port: Handle to the uart port structure 653 * 654 * Returns 0, -ENOMEM if request fails 655 **/ 656 static int xuartps_request_port(struct uart_port *port) 657 { 658 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE, 659 XUARTPS_NAME)) { 660 return -ENOMEM; 661 } 662 663 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE); 664 if (!port->membase) { 665 dev_err(port->dev, "Unable to map registers\n"); 666 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); 667 return -ENOMEM; 668 } 669 return 0; 670 } 671 672 /** 673 * xuartps_release_port - Release the memory region attached to a xuartps 674 * port, called when the driver removes a xuartps 675 * port via uart_remove_one_port(). 676 * @port: Handle to the uart port structure 677 * 678 **/ 679 static void xuartps_release_port(struct uart_port *port) 680 { 681 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); 682 iounmap(port->membase); 683 port->membase = NULL; 684 } 685 686 /** 687 * xuartps_config_port - Configure xuartps, called when the driver adds a 688 * xuartps port 689 * @port: Handle to the uart port structure 690 * @flags: If any 691 * 692 **/ 693 static void xuartps_config_port(struct uart_port *port, int flags) 694 { 695 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0) 696 port->type = PORT_XUARTPS; 697 } 698 699 /** 700 * xuartps_get_mctrl - Get the modem control state 701 * 702 * @port: Handle to the uart port structure 703 * 704 * Returns the modem control state 705 * 706 **/ 707 static unsigned int xuartps_get_mctrl(struct uart_port *port) 708 { 709 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 710 } 711 712 static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl) 713 { 714 /* N/A */ 715 } 716 717 static void xuartps_enable_ms(struct uart_port *port) 718 { 719 /* N/A */ 720 } 721 722 /** The UART operations structure 723 */ 724 static struct uart_ops xuartps_ops = { 725 .set_mctrl = xuartps_set_mctrl, 726 .get_mctrl = xuartps_get_mctrl, 727 .enable_ms = xuartps_enable_ms, 728 729 .start_tx = xuartps_start_tx, /* Start transmitting */ 730 .stop_tx = xuartps_stop_tx, /* Stop transmission */ 731 .stop_rx = xuartps_stop_rx, /* Stop reception */ 732 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */ 733 .break_ctl = xuartps_break_ctl, /* Start/stop 734 * transmitting break 735 */ 736 .set_termios = xuartps_set_termios, /* Set termios */ 737 .startup = xuartps_startup, /* App opens xuartps */ 738 .shutdown = xuartps_shutdown, /* App closes xuartps */ 739 .type = xuartps_type, /* Set UART type */ 740 .verify_port = xuartps_verify_port, /* Verification of port 741 * params 742 */ 743 .request_port = xuartps_request_port, /* Claim resources 744 * associated with a 745 * xuartps port 746 */ 747 .release_port = xuartps_release_port, /* Release resources 748 * associated with a 749 * xuartps port 750 */ 751 .config_port = xuartps_config_port, /* Configure when driver 752 * adds a xuartps port 753 */ 754 }; 755 756 static struct uart_port xuartps_port[2]; 757 758 /** 759 * xuartps_get_port - Configure the port from the platform device resource 760 * info 761 * 762 * Returns a pointer to a uart_port or NULL for failure 763 **/ 764 static struct uart_port *xuartps_get_port(void) 765 { 766 struct uart_port *port; 767 int id; 768 769 /* Find the next unused port */ 770 for (id = 0; id < XUARTPS_NR_PORTS; id++) 771 if (xuartps_port[id].mapbase == 0) 772 break; 773 774 if (id >= XUARTPS_NR_PORTS) 775 return NULL; 776 777 port = &xuartps_port[id]; 778 779 /* At this point, we've got an empty uart_port struct, initialize it */ 780 spin_lock_init(&port->lock); 781 port->membase = NULL; 782 port->iobase = 1; /* mark port in use */ 783 port->irq = 0; 784 port->type = PORT_UNKNOWN; 785 port->iotype = UPIO_MEM32; 786 port->flags = UPF_BOOT_AUTOCONF; 787 port->ops = &xuartps_ops; 788 port->fifosize = XUARTPS_FIFO_SIZE; 789 port->line = id; 790 port->dev = NULL; 791 return port; 792 } 793 794 /*-----------------------Console driver operations--------------------------*/ 795 796 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 797 /** 798 * xuartps_console_wait_tx - Wait for the TX to be full 799 * @port: Handle to the uart port structure 800 * 801 **/ 802 static void xuartps_console_wait_tx(struct uart_port *port) 803 { 804 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY) 805 != XUARTPS_SR_TXEMPTY) 806 barrier(); 807 } 808 809 /** 810 * xuartps_console_putchar - write the character to the FIFO buffer 811 * @port: Handle to the uart port structure 812 * @ch: Character to be written 813 * 814 **/ 815 static void xuartps_console_putchar(struct uart_port *port, int ch) 816 { 817 xuartps_console_wait_tx(port); 818 xuartps_writel(ch, XUARTPS_FIFO_OFFSET); 819 } 820 821 /** 822 * xuartps_console_write - perform write operation 823 * @port: Handle to the uart port structure 824 * @s: Pointer to character array 825 * @count: No of characters 826 **/ 827 static void xuartps_console_write(struct console *co, const char *s, 828 unsigned int count) 829 { 830 struct uart_port *port = &xuartps_port[co->index]; 831 unsigned long flags; 832 unsigned int imr; 833 int locked = 1; 834 835 if (oops_in_progress) 836 locked = spin_trylock_irqsave(&port->lock, flags); 837 else 838 spin_lock_irqsave(&port->lock, flags); 839 840 /* save and disable interrupt */ 841 imr = xuartps_readl(XUARTPS_IMR_OFFSET); 842 xuartps_writel(imr, XUARTPS_IDR_OFFSET); 843 844 uart_console_write(port, s, count, xuartps_console_putchar); 845 xuartps_console_wait_tx(port); 846 847 /* restore interrupt state, it seems like there may be a h/w bug 848 * in that the interrupt enable register should not need to be 849 * written based on the data sheet 850 */ 851 xuartps_writel(~imr, XUARTPS_IDR_OFFSET); 852 xuartps_writel(imr, XUARTPS_IER_OFFSET); 853 854 if (locked) 855 spin_unlock_irqrestore(&port->lock, flags); 856 } 857 858 /** 859 * xuartps_console_setup - Initialize the uart to default config 860 * @co: Console handle 861 * @options: Initial settings of uart 862 * 863 * Returns 0, -ENODEV if no device 864 **/ 865 static int __init xuartps_console_setup(struct console *co, char *options) 866 { 867 struct uart_port *port = &xuartps_port[co->index]; 868 int baud = 9600; 869 int bits = 8; 870 int parity = 'n'; 871 int flow = 'n'; 872 873 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS) 874 return -EINVAL; 875 876 if (!port->mapbase) { 877 pr_debug("console on ttyPS%i not present\n", co->index); 878 return -ENODEV; 879 } 880 881 if (options) 882 uart_parse_options(options, &baud, &parity, &bits, &flow); 883 884 return uart_set_options(port, co, baud, parity, bits, flow); 885 } 886 887 static struct uart_driver xuartps_uart_driver; 888 889 static struct console xuartps_console = { 890 .name = XUARTPS_TTY_NAME, 891 .write = xuartps_console_write, 892 .device = uart_console_device, 893 .setup = xuartps_console_setup, 894 .flags = CON_PRINTBUFFER, 895 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 896 .data = &xuartps_uart_driver, 897 }; 898 899 /** 900 * xuartps_console_init - Initialization call 901 * 902 * Returns 0 on success, negative error otherwise 903 **/ 904 static int __init xuartps_console_init(void) 905 { 906 register_console(&xuartps_console); 907 return 0; 908 } 909 910 console_initcall(xuartps_console_init); 911 912 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 913 914 /** Structure Definitions 915 */ 916 static struct uart_driver xuartps_uart_driver = { 917 .owner = THIS_MODULE, /* Owner */ 918 .driver_name = XUARTPS_NAME, /* Driver name */ 919 .dev_name = XUARTPS_TTY_NAME, /* Node name */ 920 .major = XUARTPS_MAJOR, /* Major number */ 921 .minor = XUARTPS_MINOR, /* Minor number */ 922 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */ 923 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 924 .cons = &xuartps_console, /* Console */ 925 #endif 926 }; 927 928 /* --------------------------------------------------------------------- 929 * Platform bus binding 930 */ 931 /** 932 * xuartps_probe - Platform driver probe 933 * @pdev: Pointer to the platform device structure 934 * 935 * Returns 0 on success, negative error otherwise 936 **/ 937 static int xuartps_probe(struct platform_device *pdev) 938 { 939 int rc; 940 struct uart_port *port; 941 struct resource *res, *res2; 942 struct clk *clk; 943 944 clk = of_clk_get(pdev->dev.of_node, 0); 945 if (IS_ERR(clk)) { 946 dev_err(&pdev->dev, "no clock specified\n"); 947 return PTR_ERR(clk); 948 } 949 950 rc = clk_prepare_enable(clk); 951 if (rc) { 952 dev_err(&pdev->dev, "could not enable clock\n"); 953 return -EBUSY; 954 } 955 956 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 957 if (!res) 958 return -ENODEV; 959 960 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 961 if (!res2) 962 return -ENODEV; 963 964 /* Initialize the port structure */ 965 port = xuartps_get_port(); 966 967 if (!port) { 968 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 969 return -ENODEV; 970 } else { 971 /* Register the port. 972 * This function also registers this device with the tty layer 973 * and triggers invocation of the config_port() entry point. 974 */ 975 port->mapbase = res->start; 976 port->irq = res2->start; 977 port->dev = &pdev->dev; 978 port->uartclk = clk_get_rate(clk); 979 port->private_data = clk; 980 dev_set_drvdata(&pdev->dev, port); 981 rc = uart_add_one_port(&xuartps_uart_driver, port); 982 if (rc) { 983 dev_err(&pdev->dev, 984 "uart_add_one_port() failed; err=%i\n", rc); 985 dev_set_drvdata(&pdev->dev, NULL); 986 return rc; 987 } 988 return 0; 989 } 990 } 991 992 /** 993 * xuartps_remove - called when the platform driver is unregistered 994 * @pdev: Pointer to the platform device structure 995 * 996 * Returns 0 on success, negative error otherwise 997 **/ 998 static int xuartps_remove(struct platform_device *pdev) 999 { 1000 struct uart_port *port = dev_get_drvdata(&pdev->dev); 1001 struct clk *clk = port->private_data; 1002 int rc; 1003 1004 /* Remove the xuartps port from the serial core */ 1005 rc = uart_remove_one_port(&xuartps_uart_driver, port); 1006 dev_set_drvdata(&pdev->dev, NULL); 1007 port->mapbase = 0; 1008 clk_disable_unprepare(clk); 1009 return rc; 1010 } 1011 1012 /** 1013 * xuartps_suspend - suspend event 1014 * @pdev: Pointer to the platform device structure 1015 * @state: State of the device 1016 * 1017 * Returns 0 1018 **/ 1019 static int xuartps_suspend(struct platform_device *pdev, pm_message_t state) 1020 { 1021 /* Call the API provided in serial_core.c file which handles 1022 * the suspend. 1023 */ 1024 uart_suspend_port(&xuartps_uart_driver, &xuartps_port[pdev->id]); 1025 return 0; 1026 } 1027 1028 /** 1029 * xuartps_resume - Resume after a previous suspend 1030 * @pdev: Pointer to the platform device structure 1031 * 1032 * Returns 0 1033 **/ 1034 static int xuartps_resume(struct platform_device *pdev) 1035 { 1036 uart_resume_port(&xuartps_uart_driver, &xuartps_port[pdev->id]); 1037 return 0; 1038 } 1039 1040 /* Match table for of_platform binding */ 1041 static struct of_device_id xuartps_of_match[] = { 1042 { .compatible = "xlnx,xuartps", }, 1043 {} 1044 }; 1045 MODULE_DEVICE_TABLE(of, xuartps_of_match); 1046 1047 static struct platform_driver xuartps_platform_driver = { 1048 .probe = xuartps_probe, /* Probe method */ 1049 .remove = xuartps_remove, /* Detach method */ 1050 .suspend = xuartps_suspend, /* Suspend */ 1051 .resume = xuartps_resume, /* Resume after a suspend */ 1052 .driver = { 1053 .owner = THIS_MODULE, 1054 .name = XUARTPS_NAME, /* Driver name */ 1055 .of_match_table = xuartps_of_match, 1056 }, 1057 }; 1058 1059 /* --------------------------------------------------------------------- 1060 * Module Init and Exit 1061 */ 1062 /** 1063 * xuartps_init - Initial driver registration call 1064 * 1065 * Returns whether the registration was successful or not 1066 **/ 1067 static int __init xuartps_init(void) 1068 { 1069 int retval = 0; 1070 1071 /* Register the xuartps driver with the serial core */ 1072 retval = uart_register_driver(&xuartps_uart_driver); 1073 if (retval) 1074 return retval; 1075 1076 /* Register the platform driver */ 1077 retval = platform_driver_register(&xuartps_platform_driver); 1078 if (retval) 1079 uart_unregister_driver(&xuartps_uart_driver); 1080 1081 return retval; 1082 } 1083 1084 /** 1085 * xuartps_exit - Driver unregistration call 1086 **/ 1087 static void __exit xuartps_exit(void) 1088 { 1089 /* The order of unregistration is important. Unregister the 1090 * UART driver before the platform driver crashes the system. 1091 */ 1092 1093 /* Unregister the platform driver */ 1094 platform_driver_unregister(&xuartps_platform_driver); 1095 1096 /* Unregister the xuartps driver */ 1097 uart_unregister_driver(&xuartps_uart_driver); 1098 } 1099 1100 module_init(xuartps_init); 1101 module_exit(xuartps_exit); 1102 1103 MODULE_DESCRIPTION("Driver for PS UART"); 1104 MODULE_AUTHOR("Xilinx Inc."); 1105 MODULE_LICENSE("GPL"); 1106