xref: /linux/drivers/tty/serial/ucc_uart.c (revision fcb3ad4366b9c810cbb9da34c076a9a52d8aa1e0)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Freescale QUICC Engine UART device driver
4  *
5  * Author: Timur Tabi <timur@freescale.com>
6  *
7  * Copyright 2007 Freescale Semiconductor, Inc.
8  *
9  * This driver adds support for UART devices via Freescale's QUICC Engine
10  * found on some Freescale SOCs.
11  *
12  * If Soft-UART support is needed but not already present, then this driver
13  * will request and upload the "Soft-UART" microcode upon probe.  The
14  * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
15  * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
16  * (e.g. "11" for 1.1).
17  */
18 
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial.h>
22 #include <linux/serial_core.h>
23 #include <linux/slab.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/io.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_irq.h>
30 #include <linux/dma-mapping.h>
31 
32 #include <soc/fsl/qe/ucc_slow.h>
33 
34 #include <linux/firmware.h>
35 #include <soc/fsl/cpm.h>
36 
37 #ifdef CONFIG_PPC32
38 #include <asm/reg.h> /* mfspr, SPRN_SVR */
39 #endif
40 
41 /*
42  * The GUMR flag for Soft UART.  This would normally be defined in qe.h,
43  * but Soft-UART is a hack and we want to keep everything related to it in
44  * this file.
45  */
46 #define UCC_SLOW_GUMR_H_SUART   	0x00004000      /* Soft-UART */
47 
48 /*
49  * soft_uart is 1 if we need to use Soft-UART mode
50  */
51 static int soft_uart;
52 /*
53  * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
54  */
55 static int firmware_loaded;
56 
57 /* Enable this macro to configure all serial ports in internal loopback
58    mode */
59 /* #define LOOPBACK */
60 
61 /* The major and minor device numbers are defined in
62  * Documentation/admin-guide/devices.txt.  For the QE
63  * UART, we have major number 204 and minor numbers 46 - 49, which are the
64  * same as for the CPM2.  This decision was made because no Freescale part
65  * has both a CPM and a QE.
66  */
67 #define SERIAL_QE_MAJOR 204
68 #define SERIAL_QE_MINOR 46
69 
70 /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
71 #define UCC_MAX_UART    4
72 
73 /* The number of buffer descriptors for receiving characters. */
74 #define RX_NUM_FIFO     4
75 
76 /* The number of buffer descriptors for transmitting characters. */
77 #define TX_NUM_FIFO     4
78 
79 /* The maximum size of the character buffer for a single RX BD. */
80 #define RX_BUF_SIZE     32
81 
82 /* The maximum size of the character buffer for a single TX BD. */
83 #define TX_BUF_SIZE     32
84 
85 /*
86  * The number of jiffies to wait after receiving a close command before the
87  * device is actually closed.  This allows the last few characters to be
88  * sent over the wire.
89  */
90 #define UCC_WAIT_CLOSING 100
91 
92 struct ucc_uart_pram {
93 	struct ucc_slow_pram common;
94 	u8 res1[8];     	/* reserved */
95 	__be16 maxidl;  	/* Maximum idle chars */
96 	__be16 idlc;    	/* temp idle counter */
97 	__be16 brkcr;   	/* Break count register */
98 	__be16 parec;   	/* receive parity error counter */
99 	__be16 frmec;   	/* receive framing error counter */
100 	__be16 nosec;   	/* receive noise counter */
101 	__be16 brkec;   	/* receive break condition counter */
102 	__be16 brkln;   	/* last received break length */
103 	__be16 uaddr[2];	/* UART address character 1 & 2 */
104 	__be16 rtemp;   	/* Temp storage */
105 	__be16 toseq;   	/* Transmit out of sequence char */
106 	__be16 cchars[8];       /* control characters 1-8 */
107 	__be16 rccm;    	/* receive control character mask */
108 	__be16 rccr;    	/* receive control character register */
109 	__be16 rlbc;    	/* receive last break character */
110 	__be16 res2;    	/* reserved */
111 	__be32 res3;    	/* reserved, should be cleared */
112 	u8 res4;		/* reserved, should be cleared */
113 	u8 res5[3];     	/* reserved, should be cleared */
114 	__be32 res6;    	/* reserved, should be cleared */
115 	__be32 res7;    	/* reserved, should be cleared */
116 	__be32 res8;    	/* reserved, should be cleared */
117 	__be32 res9;    	/* reserved, should be cleared */
118 	__be32 res10;   	/* reserved, should be cleared */
119 	__be32 res11;   	/* reserved, should be cleared */
120 	__be32 res12;   	/* reserved, should be cleared */
121 	__be32 res13;   	/* reserved, should be cleared */
122 /* The rest is for Soft-UART only */
123 	__be16 supsmr;  	/* 0x90, Shadow UPSMR */
124 	__be16 res92;   	/* 0x92, reserved, initialize to 0 */
125 	__be32 rx_state;	/* 0x94, RX state, initialize to 0 */
126 	__be32 rx_cnt;  	/* 0x98, RX count, initialize to 0 */
127 	u8 rx_length;   	/* 0x9C, Char length, set to 1+CL+PEN+1+SL */
128 	u8 rx_bitmark;  	/* 0x9D, reserved, initialize to 0 */
129 	u8 rx_temp_dlst_qe;     /* 0x9E, reserved, initialize to 0 */
130 	u8 res14[0xBC - 0x9F];  /* reserved */
131 	__be32 dump_ptr;	/* 0xBC, Dump pointer */
132 	__be32 rx_frame_rem;    /* 0xC0, reserved, initialize to 0 */
133 	u8 rx_frame_rem_size;   /* 0xC4, reserved, initialize to 0 */
134 	u8 tx_mode;     	/* 0xC5, mode, 0=AHDLC, 1=UART */
135 	__be16 tx_state;	/* 0xC6, TX state */
136 	u8 res15[0xD0 - 0xC8];  /* reserved */
137 	__be32 resD0;   	/* 0xD0, reserved, initialize to 0 */
138 	u8 resD4;       	/* 0xD4, reserved, initialize to 0 */
139 	__be16 resD5;   	/* 0xD5, reserved, initialize to 0 */
140 } __attribute__ ((packed));
141 
142 /* SUPSMR definitions, for Soft-UART only */
143 #define UCC_UART_SUPSMR_SL      	0x8000
144 #define UCC_UART_SUPSMR_RPM_MASK	0x6000
145 #define UCC_UART_SUPSMR_RPM_ODD 	0x0000
146 #define UCC_UART_SUPSMR_RPM_LOW 	0x2000
147 #define UCC_UART_SUPSMR_RPM_EVEN	0x4000
148 #define UCC_UART_SUPSMR_RPM_HIGH	0x6000
149 #define UCC_UART_SUPSMR_PEN     	0x1000
150 #define UCC_UART_SUPSMR_TPM_MASK	0x0C00
151 #define UCC_UART_SUPSMR_TPM_ODD 	0x0000
152 #define UCC_UART_SUPSMR_TPM_LOW 	0x0400
153 #define UCC_UART_SUPSMR_TPM_EVEN	0x0800
154 #define UCC_UART_SUPSMR_TPM_HIGH	0x0C00
155 #define UCC_UART_SUPSMR_FRZ     	0x0100
156 #define UCC_UART_SUPSMR_UM_MASK 	0x00c0
157 #define UCC_UART_SUPSMR_UM_NORMAL       0x0000
158 #define UCC_UART_SUPSMR_UM_MAN_MULTI    0x0040
159 #define UCC_UART_SUPSMR_UM_AUTO_MULTI   0x00c0
160 #define UCC_UART_SUPSMR_CL_MASK 	0x0030
161 #define UCC_UART_SUPSMR_CL_8    	0x0030
162 #define UCC_UART_SUPSMR_CL_7    	0x0020
163 #define UCC_UART_SUPSMR_CL_6    	0x0010
164 #define UCC_UART_SUPSMR_CL_5    	0x0000
165 
166 #define UCC_UART_TX_STATE_AHDLC 	0x00
167 #define UCC_UART_TX_STATE_UART  	0x01
168 #define UCC_UART_TX_STATE_X1    	0x00
169 #define UCC_UART_TX_STATE_X16   	0x80
170 
171 #define UCC_UART_PRAM_ALIGNMENT 0x100
172 
173 #define UCC_UART_SIZE_OF_BD     UCC_SLOW_SIZE_OF_BD
174 #define NUM_CONTROL_CHARS       8
175 
176 /* Private per-port data structure */
177 struct uart_qe_port {
178 	struct uart_port port;
179 	struct ucc_slow __iomem *uccp;
180 	struct ucc_uart_pram __iomem *uccup;
181 	struct ucc_slow_info us_info;
182 	struct ucc_slow_private *us_private;
183 	struct device_node *np;
184 	unsigned int ucc_num;   /* First ucc is 0, not 1 */
185 
186 	u16 rx_nrfifos;
187 	u16 rx_fifosize;
188 	u16 tx_nrfifos;
189 	u16 tx_fifosize;
190 	int wait_closing;
191 	u32 flags;
192 	struct qe_bd __iomem *rx_bd_base;
193 	struct qe_bd __iomem *rx_cur;
194 	struct qe_bd __iomem *tx_bd_base;
195 	struct qe_bd __iomem *tx_cur;
196 	unsigned char *tx_buf;
197 	unsigned char *rx_buf;
198 	void *bd_virt;  	/* virtual address of the BD buffers */
199 	dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
200 	unsigned int bd_size;   /* size of BD buffer space */
201 };
202 
203 static struct uart_driver ucc_uart_driver = {
204 	.owner  	= THIS_MODULE,
205 	.driver_name    = "ucc_uart",
206 	.dev_name       = "ttyQE",
207 	.major  	= SERIAL_QE_MAJOR,
208 	.minor  	= SERIAL_QE_MINOR,
209 	.nr     	= UCC_MAX_UART,
210 };
211 
212 /*
213  * Virtual to physical address translation.
214  *
215  * Given the virtual address for a character buffer, this function returns
216  * the physical (DMA) equivalent.
217  */
218 static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
219 {
220 	if (likely((addr >= qe_port->bd_virt)) &&
221 	    (addr < (qe_port->bd_virt + qe_port->bd_size)))
222 		return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
223 
224 	/* something nasty happened */
225 	printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
226 	BUG();
227 	return 0;
228 }
229 
230 /*
231  * Physical to virtual address translation.
232  *
233  * Given the physical (DMA) address for a character buffer, this function
234  * returns the virtual equivalent.
235  */
236 static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
237 {
238 	/* sanity check */
239 	if (likely((addr >= qe_port->bd_dma_addr) &&
240 		   (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
241 		return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
242 
243 	/* something nasty happened */
244 	printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr);
245 	BUG();
246 	return NULL;
247 }
248 
249 /*
250  * Return 1 if the QE is done transmitting all buffers for this port
251  *
252  * This function scans each BD in sequence.  If we find a BD that is not
253  * ready (READY=1), then we return 0 indicating that the QE is still sending
254  * data.  If we reach the last BD (WRAP=1), then we know we've scanned
255  * the entire list, and all BDs are done.
256  */
257 static unsigned int qe_uart_tx_empty(struct uart_port *port)
258 {
259 	struct uart_qe_port *qe_port =
260 		container_of(port, struct uart_qe_port, port);
261 	struct qe_bd __iomem *bdp = qe_port->tx_bd_base;
262 
263 	while (1) {
264 		if (ioread16be(&bdp->status) & BD_SC_READY)
265 			/* This BD is not done, so return "not done" */
266 			return 0;
267 
268 		if (ioread16be(&bdp->status) & BD_SC_WRAP)
269 			/*
270 			 * This BD is done and it's the last one, so return
271 			 * "done"
272 			 */
273 			return 1;
274 
275 		bdp++;
276 	}
277 }
278 
279 /*
280  * Set the modem control lines
281  *
282  * Although the QE can control the modem control lines (e.g. CTS), we
283  * don't need that support. This function must exist, however, otherwise
284  * the kernel will panic.
285  */
286 static void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
287 {
288 }
289 
290 /*
291  * Get the current modem control line status
292  *
293  * Although the QE can control the modem control lines (e.g. CTS), this
294  * driver currently doesn't support that, so we always return Carrier
295  * Detect, Data Set Ready, and Clear To Send.
296  */
297 static unsigned int qe_uart_get_mctrl(struct uart_port *port)
298 {
299 	return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
300 }
301 
302 /*
303  * Disable the transmit interrupt.
304  *
305  * Although this function is called "stop_tx", it does not actually stop
306  * transmission of data.  Instead, it tells the QE to not generate an
307  * interrupt when the UCC is finished sending characters.
308  */
309 static void qe_uart_stop_tx(struct uart_port *port)
310 {
311 	struct uart_qe_port *qe_port =
312 		container_of(port, struct uart_qe_port, port);
313 
314 	qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
315 }
316 
317 /*
318  * Transmit as many characters to the HW as possible.
319  *
320  * This function will attempt to stuff of all the characters from the
321  * kernel's transmit buffer into TX BDs.
322  *
323  * A return value of non-zero indicates that it successfully stuffed all
324  * characters from the kernel buffer.
325  *
326  * A return value of zero indicates that there are still characters in the
327  * kernel's buffer that have not been transmitted, but there are no more BDs
328  * available.  This function should be called again after a BD has been made
329  * available.
330  */
331 static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
332 {
333 	struct qe_bd __iomem *bdp;
334 	unsigned char *p;
335 	unsigned int count;
336 	struct uart_port *port = &qe_port->port;
337 	struct tty_port *tport = &port->state->port;
338 
339 	/* Handle xon/xoff */
340 	if (port->x_char) {
341 		/* Pick next descriptor and fill from buffer */
342 		bdp = qe_port->tx_cur;
343 
344 		p = qe2cpu_addr(ioread32be(&bdp->buf), qe_port);
345 
346 		*p++ = port->x_char;
347 		iowrite16be(1, &bdp->length);
348 		qe_setbits_be16(&bdp->status, BD_SC_READY);
349 		/* Get next BD. */
350 		if (ioread16be(&bdp->status) & BD_SC_WRAP)
351 			bdp = qe_port->tx_bd_base;
352 		else
353 			bdp++;
354 		qe_port->tx_cur = bdp;
355 
356 		port->icount.tx++;
357 		port->x_char = 0;
358 		return 1;
359 	}
360 
361 	if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
362 		qe_uart_stop_tx(port);
363 		return 0;
364 	}
365 
366 	/* Pick next descriptor and fill from buffer */
367 	bdp = qe_port->tx_cur;
368 
369 	while (!(ioread16be(&bdp->status) & BD_SC_READY) &&
370 	       !kfifo_is_empty(&tport->xmit_fifo)) {
371 		p = qe2cpu_addr(ioread32be(&bdp->buf), qe_port);
372 		count =	uart_fifo_out(port, p, qe_port->tx_fifosize);
373 
374 		iowrite16be(count, &bdp->length);
375 		qe_setbits_be16(&bdp->status, BD_SC_READY);
376 
377 		/* Get next BD. */
378 		if (ioread16be(&bdp->status) & BD_SC_WRAP)
379 			bdp = qe_port->tx_bd_base;
380 		else
381 			bdp++;
382 	}
383 	qe_port->tx_cur = bdp;
384 
385 	if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
386 		uart_write_wakeup(port);
387 
388 	if (kfifo_is_empty(&tport->xmit_fifo)) {
389 		/* The kernel buffer is empty, so turn off TX interrupts.  We
390 		   don't need to be told when the QE is finished transmitting
391 		   the data. */
392 		qe_uart_stop_tx(port);
393 		return 0;
394 	}
395 
396 	return 1;
397 }
398 
399 /*
400  * Start transmitting data
401  *
402  * This function will start transmitting any available data, if the port
403  * isn't already transmitting data.
404  */
405 static void qe_uart_start_tx(struct uart_port *port)
406 {
407 	struct uart_qe_port *qe_port =
408 		container_of(port, struct uart_qe_port, port);
409 
410 	/* If we currently are transmitting, then just return */
411 	if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
412 		return;
413 
414 	/* Otherwise, pump the port and start transmission */
415 	if (qe_uart_tx_pump(qe_port))
416 		qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
417 }
418 
419 /*
420  * Stop transmitting data
421  */
422 static void qe_uart_stop_rx(struct uart_port *port)
423 {
424 	struct uart_qe_port *qe_port =
425 		container_of(port, struct uart_qe_port, port);
426 
427 	qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
428 }
429 
430 /* Start or stop sending  break signal
431  *
432  * This function controls the sending of a break signal.  If break_state=1,
433  * then we start sending a break signal.  If break_state=0, then we stop
434  * sending the break signal.
435  */
436 static void qe_uart_break_ctl(struct uart_port *port, int break_state)
437 {
438 	struct uart_qe_port *qe_port =
439 		container_of(port, struct uart_qe_port, port);
440 
441 	if (break_state)
442 		ucc_slow_stop_tx(qe_port->us_private);
443 	else
444 		ucc_slow_restart_tx(qe_port->us_private);
445 }
446 
447 /* ISR helper function for receiving character.
448  *
449  * This function is called by the ISR to handling receiving characters
450  */
451 static void qe_uart_int_rx(struct uart_qe_port *qe_port)
452 {
453 	int i;
454 	unsigned char ch, *cp;
455 	struct uart_port *port = &qe_port->port;
456 	struct tty_port *tport = &port->state->port;
457 	struct qe_bd __iomem *bdp;
458 	u16 status;
459 	unsigned int flg;
460 
461 	/* Just loop through the closed BDs and copy the characters into
462 	 * the buffer.
463 	 */
464 	bdp = qe_port->rx_cur;
465 	while (1) {
466 		status = ioread16be(&bdp->status);
467 
468 		/* If this one is empty, then we assume we've read them all */
469 		if (status & BD_SC_EMPTY)
470 			break;
471 
472 		/* get number of characters, and check space in RX buffer */
473 		i = ioread16be(&bdp->length);
474 
475 		/* If we don't have enough room in RX buffer for the entire BD,
476 		 * then we try later, which will be the next RX interrupt.
477 		 */
478 		if (tty_buffer_request_room(tport, i) < i) {
479 			dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
480 			return;
481 		}
482 
483 		/* get pointer */
484 		cp = qe2cpu_addr(ioread32be(&bdp->buf), qe_port);
485 
486 		/* loop through the buffer */
487 		while (i-- > 0) {
488 			ch = *cp++;
489 			port->icount.rx++;
490 			flg = TTY_NORMAL;
491 
492 			if (!i && status &
493 			    (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
494 				goto handle_error;
495 			if (uart_handle_sysrq_char(port, ch))
496 				continue;
497 
498 error_return:
499 			tty_insert_flip_char(tport, ch, flg);
500 
501 		}
502 
503 		/* This BD is ready to be used again. Clear status. get next */
504 		qe_clrsetbits_be16(&bdp->status,
505 				   BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
506 				   BD_SC_EMPTY);
507 		if (ioread16be(&bdp->status) & BD_SC_WRAP)
508 			bdp = qe_port->rx_bd_base;
509 		else
510 			bdp++;
511 
512 	}
513 
514 	/* Write back buffer pointer */
515 	qe_port->rx_cur = bdp;
516 
517 	/* Activate BH processing */
518 	tty_flip_buffer_push(tport);
519 
520 	return;
521 
522 	/* Error processing */
523 
524 handle_error:
525 	/* Statistics */
526 	if (status & BD_SC_BR)
527 		port->icount.brk++;
528 	if (status & BD_SC_PR)
529 		port->icount.parity++;
530 	if (status & BD_SC_FR)
531 		port->icount.frame++;
532 	if (status & BD_SC_OV)
533 		port->icount.overrun++;
534 
535 	/* Mask out ignored conditions */
536 	status &= port->read_status_mask;
537 
538 	/* Handle the remaining ones */
539 	if (status & BD_SC_BR)
540 		flg = TTY_BREAK;
541 	else if (status & BD_SC_PR)
542 		flg = TTY_PARITY;
543 	else if (status & BD_SC_FR)
544 		flg = TTY_FRAME;
545 
546 	/* Overrun does not affect the current character ! */
547 	if (status & BD_SC_OV)
548 		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
549 	port->sysrq = 0;
550 	goto error_return;
551 }
552 
553 /* Interrupt handler
554  *
555  * This interrupt handler is called after a BD is processed.
556  */
557 static irqreturn_t qe_uart_int(int irq, void *data)
558 {
559 	struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
560 	struct ucc_slow __iomem *uccp = qe_port->uccp;
561 	u16 events;
562 
563 	/* Clear the interrupts */
564 	events = ioread16be(&uccp->ucce);
565 	iowrite16be(events, &uccp->ucce);
566 
567 	if (events & UCC_UART_UCCE_BRKE)
568 		uart_handle_break(&qe_port->port);
569 
570 	if (events & UCC_UART_UCCE_RX)
571 		qe_uart_int_rx(qe_port);
572 
573 	if (events & UCC_UART_UCCE_TX)
574 		qe_uart_tx_pump(qe_port);
575 
576 	return events ? IRQ_HANDLED : IRQ_NONE;
577 }
578 
579 /* Initialize buffer descriptors
580  *
581  * This function initializes all of the RX and TX buffer descriptors.
582  */
583 static void qe_uart_initbd(struct uart_qe_port *qe_port)
584 {
585 	int i;
586 	void *bd_virt;
587 	struct qe_bd __iomem *bdp;
588 
589 	/* Set the physical address of the host memory buffers in the buffer
590 	 * descriptors, and the virtual address for us to work with.
591 	 */
592 	bd_virt = qe_port->bd_virt;
593 	bdp = qe_port->rx_bd_base;
594 	qe_port->rx_cur = qe_port->rx_bd_base;
595 	for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
596 		iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
597 		iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
598 		iowrite16be(0, &bdp->length);
599 		bd_virt += qe_port->rx_fifosize;
600 		bdp++;
601 	}
602 
603 	/* */
604 	iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
605 	iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
606 	iowrite16be(0, &bdp->length);
607 
608 	/* Set the physical address of the host memory
609 	 * buffers in the buffer descriptors, and the
610 	 * virtual address for us to work with.
611 	 */
612 	bd_virt = qe_port->bd_virt +
613 		L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
614 	qe_port->tx_cur = qe_port->tx_bd_base;
615 	bdp = qe_port->tx_bd_base;
616 	for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
617 		iowrite16be(BD_SC_INTRPT, &bdp->status);
618 		iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
619 		iowrite16be(0, &bdp->length);
620 		bd_virt += qe_port->tx_fifosize;
621 		bdp++;
622 	}
623 
624 	/* Loopback requires the preamble bit to be set on the first TX BD */
625 #ifdef LOOPBACK
626 	qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
627 #endif
628 
629 	iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
630 	iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
631 	iowrite16be(0, &bdp->length);
632 }
633 
634 /*
635  * Initialize a UCC for UART.
636  *
637  * This function configures a given UCC to be used as a UART device. Basic
638  * UCC initialization is handled in qe_uart_request_port().  This function
639  * does all the UART-specific stuff.
640  */
641 static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
642 {
643 	u32 cecr_subblock;
644 	struct ucc_slow __iomem *uccp = qe_port->uccp;
645 	struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
646 
647 	unsigned int i;
648 
649 	/* First, disable TX and RX in the UCC */
650 	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
651 
652 	/* Program the UCC UART parameter RAM */
653 	iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
654 	iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
655 	iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
656 	iowrite16be(0x10, &uccup->maxidl);
657 	iowrite16be(1, &uccup->brkcr);
658 	iowrite16be(0, &uccup->parec);
659 	iowrite16be(0, &uccup->frmec);
660 	iowrite16be(0, &uccup->nosec);
661 	iowrite16be(0, &uccup->brkec);
662 	iowrite16be(0, &uccup->uaddr[0]);
663 	iowrite16be(0, &uccup->uaddr[1]);
664 	iowrite16be(0, &uccup->toseq);
665 	for (i = 0; i < 8; i++)
666 		iowrite16be(0xC000, &uccup->cchars[i]);
667 	iowrite16be(0xc0ff, &uccup->rccm);
668 
669 	/* Configure the GUMR registers for UART */
670 	if (soft_uart) {
671 		/* Soft-UART requires a 1X multiplier for TX */
672 		qe_clrsetbits_be32(&uccp->gumr_l,
673 				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
674 				   UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16);
675 
676 		qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
677 				   UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
678 	} else {
679 		qe_clrsetbits_be32(&uccp->gumr_l,
680 				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
681 				   UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
682 
683 		qe_clrsetbits_be32(&uccp->gumr_h,
684 				   UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
685 				   UCC_SLOW_GUMR_H_RFW);
686 	}
687 
688 #ifdef LOOPBACK
689 	qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
690 			   UCC_SLOW_GUMR_L_DIAG_LOOP);
691 	qe_clrsetbits_be32(&uccp->gumr_h,
692 			   UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
693 			   UCC_SLOW_GUMR_H_CDS);
694 #endif
695 
696 	/* Disable rx interrupts  and clear all pending events.  */
697 	iowrite16be(0, &uccp->uccm);
698 	iowrite16be(0xffff, &uccp->ucce);
699 	iowrite16be(0x7e7e, &uccp->udsr);
700 
701 	/* Initialize UPSMR */
702 	iowrite16be(0, &uccp->upsmr);
703 
704 	if (soft_uart) {
705 		iowrite16be(0x30, &uccup->supsmr);
706 		iowrite16be(0, &uccup->res92);
707 		iowrite32be(0, &uccup->rx_state);
708 		iowrite32be(0, &uccup->rx_cnt);
709 		iowrite8(0, &uccup->rx_bitmark);
710 		iowrite8(10, &uccup->rx_length);
711 		iowrite32be(0x4000, &uccup->dump_ptr);
712 		iowrite8(0, &uccup->rx_temp_dlst_qe);
713 		iowrite32be(0, &uccup->rx_frame_rem);
714 		iowrite8(0, &uccup->rx_frame_rem_size);
715 		/* Soft-UART requires TX to be 1X */
716 		iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
717 			    &uccup->tx_mode);
718 		iowrite16be(0, &uccup->tx_state);
719 		iowrite8(0, &uccup->resD4);
720 		iowrite16be(0, &uccup->resD5);
721 
722 		/* Set UART mode.
723 		 * Enable receive and transmit.
724 		 */
725 
726 		/* From the microcode errata:
727 		 * 1.GUMR_L register, set mode=0010 (QMC).
728 		 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
729 		 * 3.Set GUMR_H[19:20] (Transparent mode)
730 		 * 4.Clear GUMR_H[26] (RFW)
731 		 * ...
732 		 * 6.Receiver must use 16x over sampling
733 		 */
734 		qe_clrsetbits_be32(&uccp->gumr_l,
735 				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
736 				   UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
737 
738 		qe_clrsetbits_be32(&uccp->gumr_h,
739 				   UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
740 				   UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
741 
742 #ifdef LOOPBACK
743 		qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
744 				   UCC_SLOW_GUMR_L_DIAG_LOOP);
745 		qe_clrbits_be32(&uccp->gumr_h,
746 				UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS);
747 #endif
748 
749 		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
750 		qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
751 			QE_CR_PROTOCOL_UNSPECIFIED, 0);
752 	} else {
753 		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
754 		qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
755 			QE_CR_PROTOCOL_UART, 0);
756 	}
757 }
758 
759 /*
760  * Initialize the port.
761  */
762 static int qe_uart_startup(struct uart_port *port)
763 {
764 	struct uart_qe_port *qe_port =
765 		container_of(port, struct uart_qe_port, port);
766 	int ret;
767 
768 	/*
769 	 * If we're using Soft-UART mode, then we need to make sure the
770 	 * firmware has been uploaded first.
771 	 */
772 	if (soft_uart && !firmware_loaded) {
773 		dev_err(port->dev, "Soft-UART firmware not uploaded\n");
774 		return -ENODEV;
775 	}
776 
777 	qe_uart_initbd(qe_port);
778 	qe_uart_init_ucc(qe_port);
779 
780 	/* Install interrupt handler. */
781 	ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
782 		qe_port);
783 	if (ret) {
784 		dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
785 		return ret;
786 	}
787 
788 	/* Startup rx-int */
789 	qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
790 	ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
791 
792 	return 0;
793 }
794 
795 /*
796  * Shutdown the port.
797  */
798 static void qe_uart_shutdown(struct uart_port *port)
799 {
800 	struct uart_qe_port *qe_port =
801 		container_of(port, struct uart_qe_port, port);
802 	struct ucc_slow __iomem *uccp = qe_port->uccp;
803 	unsigned int timeout = 20;
804 
805 	/* Disable RX and TX */
806 
807 	/* Wait for all the BDs marked sent */
808 	while (!qe_uart_tx_empty(port)) {
809 		if (!--timeout) {
810 			dev_warn(port->dev, "shutdown timeout\n");
811 			break;
812 		}
813 		set_current_state(TASK_UNINTERRUPTIBLE);
814 		schedule_timeout(2);
815 	}
816 
817 	if (qe_port->wait_closing) {
818 		/* Wait a bit longer */
819 		set_current_state(TASK_UNINTERRUPTIBLE);
820 		schedule_timeout(qe_port->wait_closing);
821 	}
822 
823 	/* Stop uarts */
824 	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
825 	qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
826 
827 	/* Shut them really down and reinit buffer descriptors */
828 	ucc_slow_graceful_stop_tx(qe_port->us_private);
829 	qe_uart_initbd(qe_port);
830 
831 	free_irq(port->irq, qe_port);
832 }
833 
834 /*
835  * Set the serial port parameters.
836  */
837 static void qe_uart_set_termios(struct uart_port *port,
838 				struct ktermios *termios,
839 				const struct ktermios *old)
840 {
841 	struct uart_qe_port *qe_port =
842 		container_of(port, struct uart_qe_port, port);
843 	struct ucc_slow __iomem *uccp = qe_port->uccp;
844 	unsigned int baud;
845 	unsigned long flags;
846 	u16 upsmr = ioread16be(&uccp->upsmr);
847 	struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
848 	u16 supsmr = ioread16be(&uccup->supsmr);
849 
850 	/* byte size */
851 	upsmr &= UCC_UART_UPSMR_CL_MASK;
852 	supsmr &= UCC_UART_SUPSMR_CL_MASK;
853 
854 	switch (termios->c_cflag & CSIZE) {
855 	case CS5:
856 		upsmr |= UCC_UART_UPSMR_CL_5;
857 		supsmr |= UCC_UART_SUPSMR_CL_5;
858 		break;
859 	case CS6:
860 		upsmr |= UCC_UART_UPSMR_CL_6;
861 		supsmr |= UCC_UART_SUPSMR_CL_6;
862 		break;
863 	case CS7:
864 		upsmr |= UCC_UART_UPSMR_CL_7;
865 		supsmr |= UCC_UART_SUPSMR_CL_7;
866 		break;
867 	default:	/* case CS8 */
868 		upsmr |= UCC_UART_UPSMR_CL_8;
869 		supsmr |= UCC_UART_SUPSMR_CL_8;
870 		break;
871 	}
872 
873 	/* If CSTOPB is set, we want two stop bits */
874 	if (termios->c_cflag & CSTOPB) {
875 		upsmr |= UCC_UART_UPSMR_SL;
876 		supsmr |= UCC_UART_SUPSMR_SL;
877 	}
878 
879 	if (termios->c_cflag & PARENB) {
880 		upsmr |= UCC_UART_UPSMR_PEN;
881 		supsmr |= UCC_UART_SUPSMR_PEN;
882 
883 		if (!(termios->c_cflag & PARODD)) {
884 			upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
885 				   UCC_UART_UPSMR_TPM_MASK);
886 			upsmr |= UCC_UART_UPSMR_RPM_EVEN |
887 				UCC_UART_UPSMR_TPM_EVEN;
888 			supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
889 				    UCC_UART_SUPSMR_TPM_MASK);
890 			supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
891 				UCC_UART_SUPSMR_TPM_EVEN;
892 		}
893 	}
894 
895 	/*
896 	 * Set up parity check flag
897 	 */
898 	port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
899 	if (termios->c_iflag & INPCK)
900 		port->read_status_mask |= BD_SC_FR | BD_SC_PR;
901 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
902 		port->read_status_mask |= BD_SC_BR;
903 
904 	/*
905 	 * Characters to ignore
906 	 */
907 	port->ignore_status_mask = 0;
908 	if (termios->c_iflag & IGNPAR)
909 		port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
910 	if (termios->c_iflag & IGNBRK) {
911 		port->ignore_status_mask |= BD_SC_BR;
912 		/*
913 		 * If we're ignore parity and break indicators, ignore
914 		 * overruns too.  (For real raw support).
915 		 */
916 		if (termios->c_iflag & IGNPAR)
917 			port->ignore_status_mask |= BD_SC_OV;
918 	}
919 	/*
920 	 * !!! ignore all characters if CREAD is not set
921 	 */
922 	if ((termios->c_cflag & CREAD) == 0)
923 		port->read_status_mask &= ~BD_SC_EMPTY;
924 
925 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
926 
927 	/* Do we really need a spinlock here? */
928 	uart_port_lock_irqsave(port, &flags);
929 
930 	/* Update the per-port timeout. */
931 	uart_update_timeout(port, termios->c_cflag, baud);
932 
933 	iowrite16be(upsmr, &uccp->upsmr);
934 	if (soft_uart) {
935 		iowrite16be(supsmr, &uccup->supsmr);
936 		iowrite8(tty_get_frame_size(termios->c_cflag), &uccup->rx_length);
937 
938 		/* Soft-UART requires a 1X multiplier for TX */
939 		qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
940 		qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
941 	} else {
942 		qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
943 		qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
944 	}
945 
946 	uart_port_unlock_irqrestore(port, flags);
947 }
948 
949 /*
950  * Return a pointer to a string that describes what kind of port this is.
951  */
952 static const char *qe_uart_type(struct uart_port *port)
953 {
954 	return "QE";
955 }
956 
957 /*
958  * Allocate any memory and I/O resources required by the port.
959  */
960 static int qe_uart_request_port(struct uart_port *port)
961 {
962 	int ret;
963 	struct uart_qe_port *qe_port =
964 		container_of(port, struct uart_qe_port, port);
965 	struct ucc_slow_info *us_info = &qe_port->us_info;
966 	struct ucc_slow_private *uccs;
967 	unsigned int rx_size, tx_size;
968 	void *bd_virt;
969 	dma_addr_t bd_dma_addr = 0;
970 
971 	ret = ucc_slow_init(us_info, &uccs);
972 	if (ret) {
973 		dev_err(port->dev, "could not initialize UCC%u\n",
974 		       qe_port->ucc_num);
975 		return ret;
976 	}
977 
978 	qe_port->us_private = uccs;
979 	qe_port->uccp = uccs->us_regs;
980 	qe_port->uccup = (struct ucc_uart_pram __iomem *)uccs->us_pram;
981 	qe_port->rx_bd_base = uccs->rx_bd;
982 	qe_port->tx_bd_base = uccs->tx_bd;
983 
984 	/*
985 	 * Allocate the transmit and receive data buffers.
986 	 */
987 
988 	rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
989 	tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
990 
991 	bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
992 		GFP_KERNEL);
993 	if (!bd_virt) {
994 		dev_err(port->dev, "could not allocate buffer descriptors\n");
995 		return -ENOMEM;
996 	}
997 
998 	qe_port->bd_virt = bd_virt;
999 	qe_port->bd_dma_addr = bd_dma_addr;
1000 	qe_port->bd_size = rx_size + tx_size;
1001 
1002 	qe_port->rx_buf = bd_virt;
1003 	qe_port->tx_buf = qe_port->rx_buf + rx_size;
1004 
1005 	return 0;
1006 }
1007 
1008 /*
1009  * Configure the port.
1010  *
1011  * We say we're a CPM-type port because that's mostly true.  Once the device
1012  * is configured, this driver operates almost identically to the CPM serial
1013  * driver.
1014  */
1015 static void qe_uart_config_port(struct uart_port *port, int flags)
1016 {
1017 	if (flags & UART_CONFIG_TYPE) {
1018 		port->type = PORT_CPM;
1019 		qe_uart_request_port(port);
1020 	}
1021 }
1022 
1023 /*
1024  * Release any memory and I/O resources that were allocated in
1025  * qe_uart_request_port().
1026  */
1027 static void qe_uart_release_port(struct uart_port *port)
1028 {
1029 	struct uart_qe_port *qe_port =
1030 		container_of(port, struct uart_qe_port, port);
1031 	struct ucc_slow_private *uccs = qe_port->us_private;
1032 
1033 	dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
1034 			  qe_port->bd_dma_addr);
1035 
1036 	ucc_slow_free(uccs);
1037 }
1038 
1039 /*
1040  * Verify that the data in serial_struct is suitable for this device.
1041  */
1042 static int qe_uart_verify_port(struct uart_port *port,
1043 			       struct serial_struct *ser)
1044 {
1045 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
1046 		return -EINVAL;
1047 
1048 	if (ser->irq < 0 || ser->irq >= irq_get_nr_irqs())
1049 		return -EINVAL;
1050 
1051 	if (ser->baud_base < 9600)
1052 		return -EINVAL;
1053 
1054 	return 0;
1055 }
1056 /* UART operations
1057  *
1058  * Details on these functions can be found in Documentation/driver-api/serial/driver.rst
1059  */
1060 static const struct uart_ops qe_uart_pops = {
1061 	.tx_empty       = qe_uart_tx_empty,
1062 	.set_mctrl      = qe_uart_set_mctrl,
1063 	.get_mctrl      = qe_uart_get_mctrl,
1064 	.stop_tx	= qe_uart_stop_tx,
1065 	.start_tx       = qe_uart_start_tx,
1066 	.stop_rx	= qe_uart_stop_rx,
1067 	.break_ctl      = qe_uart_break_ctl,
1068 	.startup	= qe_uart_startup,
1069 	.shutdown       = qe_uart_shutdown,
1070 	.set_termios    = qe_uart_set_termios,
1071 	.type   	= qe_uart_type,
1072 	.release_port   = qe_uart_release_port,
1073 	.request_port   = qe_uart_request_port,
1074 	.config_port    = qe_uart_config_port,
1075 	.verify_port    = qe_uart_verify_port,
1076 };
1077 
1078 
1079 #ifdef CONFIG_PPC32
1080 /*
1081  * Obtain the SOC model number and revision level
1082  *
1083  * This function parses the device tree to obtain the SOC model.  It then
1084  * reads the SVR register to the revision.
1085  *
1086  * The device tree stores the SOC model two different ways.
1087  *
1088  * The new way is:
1089  *
1090  *      	cpu@0 {
1091  *      		compatible = "PowerPC,8323";
1092  *      		device_type = "cpu";
1093  *      		...
1094  *
1095  *
1096  * The old way is:
1097  *      	 PowerPC,8323@0 {
1098  *      		device_type = "cpu";
1099  *      		...
1100  *
1101  * This code first checks the new way, and then the old way.
1102  */
1103 static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
1104 {
1105 	struct device_node *np;
1106 	const char *soc_string;
1107 	unsigned int svr;
1108 	unsigned int soc;
1109 
1110 	/* Find the CPU node */
1111 	np = of_find_node_by_type(NULL, "cpu");
1112 	if (!np)
1113 		return 0;
1114 	/* Find the compatible property */
1115 	soc_string = of_get_property(np, "compatible", NULL);
1116 	if (!soc_string)
1117 		/* No compatible property, so try the name. */
1118 		soc_string = np->name;
1119 
1120 	of_node_put(np);
1121 
1122 	/* Extract the SOC number from the "PowerPC," string */
1123 	if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
1124 		return 0;
1125 
1126 	/* Get the revision from the SVR */
1127 	svr = mfspr(SPRN_SVR);
1128 	*rev_h = (svr >> 4) & 0xf;
1129 	*rev_l = svr & 0xf;
1130 
1131 	return soc;
1132 }
1133 
1134 /*
1135  * requst_firmware_nowait() callback function
1136  *
1137  * This function is called by the kernel when a firmware is made available,
1138  * or if it times out waiting for the firmware.
1139  */
1140 static void uart_firmware_cont(const struct firmware *fw, void *context)
1141 {
1142 	struct qe_firmware *firmware;
1143 	struct device *dev = context;
1144 	int ret;
1145 
1146 	if (!fw) {
1147 		dev_err(dev, "firmware not found\n");
1148 		return;
1149 	}
1150 
1151 	firmware = (struct qe_firmware *) fw->data;
1152 
1153 	if (be32_to_cpu(firmware->header.length) != fw->size) {
1154 		dev_err(dev, "invalid firmware\n");
1155 		goto out;
1156 	}
1157 
1158 	ret = qe_upload_firmware(firmware);
1159 	if (ret) {
1160 		dev_err(dev, "could not load firmware\n");
1161 		goto out;
1162 	}
1163 
1164 	firmware_loaded = 1;
1165  out:
1166 	release_firmware(fw);
1167 }
1168 
1169 static int soft_uart_init(struct platform_device *ofdev)
1170 {
1171 	struct device_node *np = ofdev->dev.of_node;
1172 	struct qe_firmware_info *qe_fw_info;
1173 	int ret;
1174 
1175 	if (of_property_read_bool(np, "soft-uart")) {
1176 		dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
1177 		soft_uart = 1;
1178 	} else {
1179 		return 0;
1180 	}
1181 
1182 	qe_fw_info = qe_get_firmware_info();
1183 
1184 	/* Check if the firmware has been uploaded. */
1185 	if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
1186 		firmware_loaded = 1;
1187 	} else {
1188 		char filename[32];
1189 		unsigned int soc;
1190 		unsigned int rev_h;
1191 		unsigned int rev_l;
1192 
1193 		soc = soc_info(&rev_h, &rev_l);
1194 		if (!soc) {
1195 			dev_err(&ofdev->dev, "unknown CPU model\n");
1196 			return -ENXIO;
1197 		}
1198 		sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
1199 			soc, rev_h, rev_l);
1200 
1201 		dev_info(&ofdev->dev, "waiting for firmware %s\n",
1202 			 filename);
1203 
1204 		/*
1205 		 * We call request_firmware_nowait instead of
1206 		 * request_firmware so that the driver can load and
1207 		 * initialize the ports without holding up the rest of
1208 		 * the kernel.  If hotplug support is enabled in the
1209 		 * kernel, then we use it.
1210 		 */
1211 		ret = request_firmware_nowait(THIS_MODULE,
1212 					      FW_ACTION_UEVENT, filename, &ofdev->dev,
1213 					      GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
1214 		if (ret) {
1215 			dev_err(&ofdev->dev,
1216 				"could not load firmware %s\n",
1217 				filename);
1218 			return ret;
1219 		}
1220 	}
1221 	return 0;
1222 }
1223 
1224 #else /* !CONFIG_PPC32 */
1225 
1226 static int soft_uart_init(struct platform_device *ofdev)
1227 {
1228 	return 0;
1229 }
1230 
1231 #endif
1232 
1233 
1234 static int ucc_uart_probe(struct platform_device *ofdev)
1235 {
1236 	struct device_node *np = ofdev->dev.of_node;
1237 	const char *sprop;      /* String OF properties */
1238 	struct uart_qe_port *qe_port = NULL;
1239 	struct resource res;
1240 	u32 val;
1241 	int ret;
1242 
1243 	/*
1244 	 * Determine if we need Soft-UART mode
1245 	 */
1246 	ret = soft_uart_init(ofdev);
1247 	if (ret)
1248 		return ret;
1249 
1250 	qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
1251 	if (!qe_port) {
1252 		dev_err(&ofdev->dev, "can't allocate QE port structure\n");
1253 		return -ENOMEM;
1254 	}
1255 
1256 	/* Search for IRQ and mapbase */
1257 	ret = of_address_to_resource(np, 0, &res);
1258 	if (ret) {
1259 		dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
1260 		goto out_free;
1261 	}
1262 	if (!res.start) {
1263 		dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
1264 		ret = -EINVAL;
1265 		goto out_free;
1266 	}
1267 	qe_port->port.mapbase = res.start;
1268 
1269 	/* Get the UCC number (device ID) */
1270 	/* UCCs are numbered 1-7 */
1271 	if (of_property_read_u32(np, "cell-index", &val)) {
1272 		if (of_property_read_u32(np, "device-id", &val)) {
1273 			dev_err(&ofdev->dev, "UCC is unspecified in device tree\n");
1274 			ret = -EINVAL;
1275 			goto out_free;
1276 		}
1277 	}
1278 
1279 	if (val < 1 || val > UCC_MAX_NUM) {
1280 		dev_err(&ofdev->dev, "no support for UCC%u\n", val);
1281 		ret = -ENODEV;
1282 		goto out_free;
1283 	}
1284 	qe_port->ucc_num = val - 1;
1285 
1286 	/*
1287 	 * In the future, we should not require the BRG to be specified in the
1288 	 * device tree.  If no clock-source is specified, then just pick a BRG
1289 	 * to use.  This requires a new QE library function that manages BRG
1290 	 * assignments.
1291 	 */
1292 
1293 	sprop = of_get_property(np, "rx-clock-name", NULL);
1294 	if (!sprop) {
1295 		dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
1296 		ret = -ENODEV;
1297 		goto out_free;
1298 	}
1299 
1300 	qe_port->us_info.rx_clock = qe_clock_source(sprop);
1301 	if ((qe_port->us_info.rx_clock < QE_BRG1) ||
1302 	    (qe_port->us_info.rx_clock > QE_BRG16)) {
1303 		dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
1304 		ret = -ENODEV;
1305 		goto out_free;
1306 	}
1307 
1308 #ifdef LOOPBACK
1309 	/* In internal loopback mode, TX and RX must use the same clock */
1310 	qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
1311 #else
1312 	sprop = of_get_property(np, "tx-clock-name", NULL);
1313 	if (!sprop) {
1314 		dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
1315 		ret = -ENODEV;
1316 		goto out_free;
1317 	}
1318 	qe_port->us_info.tx_clock = qe_clock_source(sprop);
1319 #endif
1320 	if ((qe_port->us_info.tx_clock < QE_BRG1) ||
1321 	    (qe_port->us_info.tx_clock > QE_BRG16)) {
1322 		dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
1323 		ret = -ENODEV;
1324 		goto out_free;
1325 	}
1326 
1327 	/* Get the port number, numbered 0-3 */
1328 	if (of_property_read_u32(np, "port-number", &val)) {
1329 		dev_err(&ofdev->dev, "missing port-number in device tree\n");
1330 		ret = -EINVAL;
1331 		goto out_free;
1332 	}
1333 	qe_port->port.line = val;
1334 	if (qe_port->port.line >= UCC_MAX_UART) {
1335 		dev_err(&ofdev->dev, "port-number must be 0-%u\n",
1336 			UCC_MAX_UART - 1);
1337 		ret = -EINVAL;
1338 		goto out_free;
1339 	}
1340 
1341 	qe_port->port.irq = irq_of_parse_and_map(np, 0);
1342 	if (qe_port->port.irq == 0) {
1343 		dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
1344 		       qe_port->ucc_num + 1);
1345 		ret = -EINVAL;
1346 		goto out_free;
1347 	}
1348 
1349 	/*
1350 	 * Newer device trees have an "fsl,qe" compatible property for the QE
1351 	 * node, but we still need to support older device trees.
1352 	 */
1353 	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
1354 	if (!np) {
1355 		np = of_find_node_by_type(NULL, "qe");
1356 		if (!np) {
1357 			dev_err(&ofdev->dev, "could not find 'qe' node\n");
1358 			ret = -EINVAL;
1359 			goto out_free;
1360 		}
1361 	}
1362 
1363 	if (of_property_read_u32(np, "brg-frequency", &val)) {
1364 		dev_err(&ofdev->dev,
1365 		       "missing brg-frequency in device tree\n");
1366 		ret = -EINVAL;
1367 		goto out_np;
1368 	}
1369 
1370 	if (val)
1371 		qe_port->port.uartclk = val;
1372 	else {
1373 		if (!IS_ENABLED(CONFIG_PPC32)) {
1374 			dev_err(&ofdev->dev,
1375 				"invalid brg-frequency in device tree\n");
1376 			ret = -EINVAL;
1377 			goto out_np;
1378 		}
1379 
1380 		/*
1381 		 * Older versions of U-Boot do not initialize the brg-frequency
1382 		 * property, so in this case we assume the BRG frequency is
1383 		 * half the QE bus frequency.
1384 		 */
1385 		if (of_property_read_u32(np, "bus-frequency", &val)) {
1386 			dev_err(&ofdev->dev,
1387 				"missing QE bus-frequency in device tree\n");
1388 			ret = -EINVAL;
1389 			goto out_np;
1390 		}
1391 		if (val)
1392 			qe_port->port.uartclk = val / 2;
1393 		else {
1394 			dev_err(&ofdev->dev,
1395 				"invalid QE bus-frequency in device tree\n");
1396 			ret = -EINVAL;
1397 			goto out_np;
1398 		}
1399 	}
1400 
1401 	spin_lock_init(&qe_port->port.lock);
1402 	qe_port->np = np;
1403 	qe_port->port.dev = &ofdev->dev;
1404 	qe_port->port.ops = &qe_uart_pops;
1405 	qe_port->port.iotype = UPIO_MEM;
1406 
1407 	qe_port->tx_nrfifos = TX_NUM_FIFO;
1408 	qe_port->tx_fifosize = TX_BUF_SIZE;
1409 	qe_port->rx_nrfifos = RX_NUM_FIFO;
1410 	qe_port->rx_fifosize = RX_BUF_SIZE;
1411 
1412 	qe_port->wait_closing = UCC_WAIT_CLOSING;
1413 	qe_port->port.fifosize = 512;
1414 	qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
1415 
1416 	qe_port->us_info.ucc_num = qe_port->ucc_num;
1417 	qe_port->us_info.regs = (phys_addr_t) res.start;
1418 	qe_port->us_info.irq = qe_port->port.irq;
1419 
1420 	qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
1421 	qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
1422 
1423 	/* Make sure ucc_slow_init() initializes both TX and RX */
1424 	qe_port->us_info.init_tx = 1;
1425 	qe_port->us_info.init_rx = 1;
1426 
1427 	/* Add the port to the uart sub-system.  This will cause
1428 	 * qe_uart_config_port() to be called, so the us_info structure must
1429 	 * be initialized.
1430 	 */
1431 	ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
1432 	if (ret) {
1433 		dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
1434 		       qe_port->port.line);
1435 		goto out_np;
1436 	}
1437 
1438 	platform_set_drvdata(ofdev, qe_port);
1439 
1440 	dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
1441 		qe_port->ucc_num + 1, qe_port->port.line);
1442 
1443 	/* Display the mknod command for this device */
1444 	dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
1445 	       qe_port->port.line, SERIAL_QE_MAJOR,
1446 	       SERIAL_QE_MINOR + qe_port->port.line);
1447 
1448 	return 0;
1449 out_np:
1450 	of_node_put(np);
1451 out_free:
1452 	kfree(qe_port);
1453 	return ret;
1454 }
1455 
1456 static void ucc_uart_remove(struct platform_device *ofdev)
1457 {
1458 	struct uart_qe_port *qe_port = platform_get_drvdata(ofdev);
1459 
1460 	dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
1461 
1462 	uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
1463 
1464 	of_node_put(qe_port->np);
1465 
1466 	kfree(qe_port);
1467 }
1468 
1469 static const struct of_device_id ucc_uart_match[] = {
1470 	{
1471 		.type = "serial",
1472 		.compatible = "ucc_uart",
1473 	},
1474 	{
1475 		.compatible = "fsl,t1040-ucc-uart",
1476 	},
1477 	{},
1478 };
1479 MODULE_DEVICE_TABLE(of, ucc_uart_match);
1480 
1481 static struct platform_driver ucc_uart_of_driver = {
1482 	.driver = {
1483 		.name = "ucc_uart",
1484 		.of_match_table    = ucc_uart_match,
1485 	},
1486 	.probe  	= ucc_uart_probe,
1487 	.remove_new 	= ucc_uart_remove,
1488 };
1489 
1490 static int __init ucc_uart_init(void)
1491 {
1492 	int ret;
1493 
1494 	printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
1495 #ifdef LOOPBACK
1496 	printk(KERN_INFO "ucc-uart: Using loopback mode\n");
1497 #endif
1498 
1499 	ret = uart_register_driver(&ucc_uart_driver);
1500 	if (ret) {
1501 		printk(KERN_ERR "ucc-uart: could not register UART driver\n");
1502 		return ret;
1503 	}
1504 
1505 	ret = platform_driver_register(&ucc_uart_of_driver);
1506 	if (ret) {
1507 		printk(KERN_ERR
1508 		       "ucc-uart: could not register platform driver\n");
1509 		uart_unregister_driver(&ucc_uart_driver);
1510 	}
1511 
1512 	return ret;
1513 }
1514 
1515 static void __exit ucc_uart_exit(void)
1516 {
1517 	printk(KERN_INFO
1518 	       "Freescale QUICC Engine UART device driver unloading\n");
1519 
1520 	platform_driver_unregister(&ucc_uart_of_driver);
1521 	uart_unregister_driver(&ucc_uart_driver);
1522 }
1523 
1524 module_init(ucc_uart_init);
1525 module_exit(ucc_uart_exit);
1526 
1527 MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
1528 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1529 MODULE_LICENSE("GPL v2");
1530 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);
1531 
1532