1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Freescale QUICC Engine UART device driver 4 * 5 * Author: Timur Tabi <timur@freescale.com> 6 * 7 * Copyright 2007 Freescale Semiconductor, Inc. This file is licensed under 8 * the terms of the GNU General Public License version 2. This program 9 * is licensed "as is" without any warranty of any kind, whether express 10 * or implied. 11 * 12 * This driver adds support for UART devices via Freescale's QUICC Engine 13 * found on some Freescale SOCs. 14 * 15 * If Soft-UART support is needed but not already present, then this driver 16 * will request and upload the "Soft-UART" microcode upon probe. The 17 * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X" 18 * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC, 19 * (e.g. "11" for 1.1). 20 */ 21 22 #include <linux/module.h> 23 #include <linux/serial.h> 24 #include <linux/serial_core.h> 25 #include <linux/slab.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/io.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/of_platform.h> 32 #include <linux/dma-mapping.h> 33 34 #include <linux/fs_uart_pd.h> 35 #include <soc/fsl/qe/ucc_slow.h> 36 37 #include <linux/firmware.h> 38 #include <asm/reg.h> 39 40 /* 41 * The GUMR flag for Soft UART. This would normally be defined in qe.h, 42 * but Soft-UART is a hack and we want to keep everything related to it in 43 * this file. 44 */ 45 #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */ 46 47 /* 48 * soft_uart is 1 if we need to use Soft-UART mode 49 */ 50 static int soft_uart; 51 /* 52 * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise. 53 */ 54 static int firmware_loaded; 55 56 /* Enable this macro to configure all serial ports in internal loopback 57 mode */ 58 /* #define LOOPBACK */ 59 60 /* The major and minor device numbers are defined in 61 * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE 62 * UART, we have major number 204 and minor numbers 46 - 49, which are the 63 * same as for the CPM2. This decision was made because no Freescale part 64 * has both a CPM and a QE. 65 */ 66 #define SERIAL_QE_MAJOR 204 67 #define SERIAL_QE_MINOR 46 68 69 /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */ 70 #define UCC_MAX_UART 4 71 72 /* The number of buffer descriptors for receiving characters. */ 73 #define RX_NUM_FIFO 4 74 75 /* The number of buffer descriptors for transmitting characters. */ 76 #define TX_NUM_FIFO 4 77 78 /* The maximum size of the character buffer for a single RX BD. */ 79 #define RX_BUF_SIZE 32 80 81 /* The maximum size of the character buffer for a single TX BD. */ 82 #define TX_BUF_SIZE 32 83 84 /* 85 * The number of jiffies to wait after receiving a close command before the 86 * device is actually closed. This allows the last few characters to be 87 * sent over the wire. 88 */ 89 #define UCC_WAIT_CLOSING 100 90 91 struct ucc_uart_pram { 92 struct ucc_slow_pram common; 93 u8 res1[8]; /* reserved */ 94 __be16 maxidl; /* Maximum idle chars */ 95 __be16 idlc; /* temp idle counter */ 96 __be16 brkcr; /* Break count register */ 97 __be16 parec; /* receive parity error counter */ 98 __be16 frmec; /* receive framing error counter */ 99 __be16 nosec; /* receive noise counter */ 100 __be16 brkec; /* receive break condition counter */ 101 __be16 brkln; /* last received break length */ 102 __be16 uaddr[2]; /* UART address character 1 & 2 */ 103 __be16 rtemp; /* Temp storage */ 104 __be16 toseq; /* Transmit out of sequence char */ 105 __be16 cchars[8]; /* control characters 1-8 */ 106 __be16 rccm; /* receive control character mask */ 107 __be16 rccr; /* receive control character register */ 108 __be16 rlbc; /* receive last break character */ 109 __be16 res2; /* reserved */ 110 __be32 res3; /* reserved, should be cleared */ 111 u8 res4; /* reserved, should be cleared */ 112 u8 res5[3]; /* reserved, should be cleared */ 113 __be32 res6; /* reserved, should be cleared */ 114 __be32 res7; /* reserved, should be cleared */ 115 __be32 res8; /* reserved, should be cleared */ 116 __be32 res9; /* reserved, should be cleared */ 117 __be32 res10; /* reserved, should be cleared */ 118 __be32 res11; /* reserved, should be cleared */ 119 __be32 res12; /* reserved, should be cleared */ 120 __be32 res13; /* reserved, should be cleared */ 121 /* The rest is for Soft-UART only */ 122 __be16 supsmr; /* 0x90, Shadow UPSMR */ 123 __be16 res92; /* 0x92, reserved, initialize to 0 */ 124 __be32 rx_state; /* 0x94, RX state, initialize to 0 */ 125 __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */ 126 u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */ 127 u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */ 128 u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */ 129 u8 res14[0xBC - 0x9F]; /* reserved */ 130 __be32 dump_ptr; /* 0xBC, Dump pointer */ 131 __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */ 132 u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */ 133 u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */ 134 __be16 tx_state; /* 0xC6, TX state */ 135 u8 res15[0xD0 - 0xC8]; /* reserved */ 136 __be32 resD0; /* 0xD0, reserved, initialize to 0 */ 137 u8 resD4; /* 0xD4, reserved, initialize to 0 */ 138 __be16 resD5; /* 0xD5, reserved, initialize to 0 */ 139 } __attribute__ ((packed)); 140 141 /* SUPSMR definitions, for Soft-UART only */ 142 #define UCC_UART_SUPSMR_SL 0x8000 143 #define UCC_UART_SUPSMR_RPM_MASK 0x6000 144 #define UCC_UART_SUPSMR_RPM_ODD 0x0000 145 #define UCC_UART_SUPSMR_RPM_LOW 0x2000 146 #define UCC_UART_SUPSMR_RPM_EVEN 0x4000 147 #define UCC_UART_SUPSMR_RPM_HIGH 0x6000 148 #define UCC_UART_SUPSMR_PEN 0x1000 149 #define UCC_UART_SUPSMR_TPM_MASK 0x0C00 150 #define UCC_UART_SUPSMR_TPM_ODD 0x0000 151 #define UCC_UART_SUPSMR_TPM_LOW 0x0400 152 #define UCC_UART_SUPSMR_TPM_EVEN 0x0800 153 #define UCC_UART_SUPSMR_TPM_HIGH 0x0C00 154 #define UCC_UART_SUPSMR_FRZ 0x0100 155 #define UCC_UART_SUPSMR_UM_MASK 0x00c0 156 #define UCC_UART_SUPSMR_UM_NORMAL 0x0000 157 #define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040 158 #define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0 159 #define UCC_UART_SUPSMR_CL_MASK 0x0030 160 #define UCC_UART_SUPSMR_CL_8 0x0030 161 #define UCC_UART_SUPSMR_CL_7 0x0020 162 #define UCC_UART_SUPSMR_CL_6 0x0010 163 #define UCC_UART_SUPSMR_CL_5 0x0000 164 165 #define UCC_UART_TX_STATE_AHDLC 0x00 166 #define UCC_UART_TX_STATE_UART 0x01 167 #define UCC_UART_TX_STATE_X1 0x00 168 #define UCC_UART_TX_STATE_X16 0x80 169 170 #define UCC_UART_PRAM_ALIGNMENT 0x100 171 172 #define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD 173 #define NUM_CONTROL_CHARS 8 174 175 /* Private per-port data structure */ 176 struct uart_qe_port { 177 struct uart_port port; 178 struct ucc_slow __iomem *uccp; 179 struct ucc_uart_pram __iomem *uccup; 180 struct ucc_slow_info us_info; 181 struct ucc_slow_private *us_private; 182 struct device_node *np; 183 unsigned int ucc_num; /* First ucc is 0, not 1 */ 184 185 u16 rx_nrfifos; 186 u16 rx_fifosize; 187 u16 tx_nrfifos; 188 u16 tx_fifosize; 189 int wait_closing; 190 u32 flags; 191 struct qe_bd *rx_bd_base; 192 struct qe_bd *rx_cur; 193 struct qe_bd *tx_bd_base; 194 struct qe_bd *tx_cur; 195 unsigned char *tx_buf; 196 unsigned char *rx_buf; 197 void *bd_virt; /* virtual address of the BD buffers */ 198 dma_addr_t bd_dma_addr; /* bus address of the BD buffers */ 199 unsigned int bd_size; /* size of BD buffer space */ 200 }; 201 202 static struct uart_driver ucc_uart_driver = { 203 .owner = THIS_MODULE, 204 .driver_name = "ucc_uart", 205 .dev_name = "ttyQE", 206 .major = SERIAL_QE_MAJOR, 207 .minor = SERIAL_QE_MINOR, 208 .nr = UCC_MAX_UART, 209 }; 210 211 /* 212 * Virtual to physical address translation. 213 * 214 * Given the virtual address for a character buffer, this function returns 215 * the physical (DMA) equivalent. 216 */ 217 static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port) 218 { 219 if (likely((addr >= qe_port->bd_virt)) && 220 (addr < (qe_port->bd_virt + qe_port->bd_size))) 221 return qe_port->bd_dma_addr + (addr - qe_port->bd_virt); 222 223 /* something nasty happened */ 224 printk(KERN_ERR "%s: addr=%p\n", __func__, addr); 225 BUG(); 226 return 0; 227 } 228 229 /* 230 * Physical to virtual address translation. 231 * 232 * Given the physical (DMA) address for a character buffer, this function 233 * returns the virtual equivalent. 234 */ 235 static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port) 236 { 237 /* sanity check */ 238 if (likely((addr >= qe_port->bd_dma_addr) && 239 (addr < (qe_port->bd_dma_addr + qe_port->bd_size)))) 240 return qe_port->bd_virt + (addr - qe_port->bd_dma_addr); 241 242 /* something nasty happened */ 243 printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr); 244 BUG(); 245 return NULL; 246 } 247 248 /* 249 * Return 1 if the QE is done transmitting all buffers for this port 250 * 251 * This function scans each BD in sequence. If we find a BD that is not 252 * ready (READY=1), then we return 0 indicating that the QE is still sending 253 * data. If we reach the last BD (WRAP=1), then we know we've scanned 254 * the entire list, and all BDs are done. 255 */ 256 static unsigned int qe_uart_tx_empty(struct uart_port *port) 257 { 258 struct uart_qe_port *qe_port = 259 container_of(port, struct uart_qe_port, port); 260 struct qe_bd *bdp = qe_port->tx_bd_base; 261 262 while (1) { 263 if (in_be16(&bdp->status) & BD_SC_READY) 264 /* This BD is not done, so return "not done" */ 265 return 0; 266 267 if (in_be16(&bdp->status) & BD_SC_WRAP) 268 /* 269 * This BD is done and it's the last one, so return 270 * "done" 271 */ 272 return 1; 273 274 bdp++; 275 } 276 } 277 278 /* 279 * Set the modem control lines 280 * 281 * Although the QE can control the modem control lines (e.g. CTS), we 282 * don't need that support. This function must exist, however, otherwise 283 * the kernel will panic. 284 */ 285 void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 286 { 287 } 288 289 /* 290 * Get the current modem control line status 291 * 292 * Although the QE can control the modem control lines (e.g. CTS), this 293 * driver currently doesn't support that, so we always return Carrier 294 * Detect, Data Set Ready, and Clear To Send. 295 */ 296 static unsigned int qe_uart_get_mctrl(struct uart_port *port) 297 { 298 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 299 } 300 301 /* 302 * Disable the transmit interrupt. 303 * 304 * Although this function is called "stop_tx", it does not actually stop 305 * transmission of data. Instead, it tells the QE to not generate an 306 * interrupt when the UCC is finished sending characters. 307 */ 308 static void qe_uart_stop_tx(struct uart_port *port) 309 { 310 struct uart_qe_port *qe_port = 311 container_of(port, struct uart_qe_port, port); 312 313 clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); 314 } 315 316 /* 317 * Transmit as many characters to the HW as possible. 318 * 319 * This function will attempt to stuff of all the characters from the 320 * kernel's transmit buffer into TX BDs. 321 * 322 * A return value of non-zero indicates that it successfully stuffed all 323 * characters from the kernel buffer. 324 * 325 * A return value of zero indicates that there are still characters in the 326 * kernel's buffer that have not been transmitted, but there are no more BDs 327 * available. This function should be called again after a BD has been made 328 * available. 329 */ 330 static int qe_uart_tx_pump(struct uart_qe_port *qe_port) 331 { 332 struct qe_bd *bdp; 333 unsigned char *p; 334 unsigned int count; 335 struct uart_port *port = &qe_port->port; 336 struct circ_buf *xmit = &port->state->xmit; 337 338 bdp = qe_port->rx_cur; 339 340 /* Handle xon/xoff */ 341 if (port->x_char) { 342 /* Pick next descriptor and fill from buffer */ 343 bdp = qe_port->tx_cur; 344 345 p = qe2cpu_addr(bdp->buf, qe_port); 346 347 *p++ = port->x_char; 348 out_be16(&bdp->length, 1); 349 setbits16(&bdp->status, BD_SC_READY); 350 /* Get next BD. */ 351 if (in_be16(&bdp->status) & BD_SC_WRAP) 352 bdp = qe_port->tx_bd_base; 353 else 354 bdp++; 355 qe_port->tx_cur = bdp; 356 357 port->icount.tx++; 358 port->x_char = 0; 359 return 1; 360 } 361 362 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 363 qe_uart_stop_tx(port); 364 return 0; 365 } 366 367 /* Pick next descriptor and fill from buffer */ 368 bdp = qe_port->tx_cur; 369 370 while (!(in_be16(&bdp->status) & BD_SC_READY) && 371 (xmit->tail != xmit->head)) { 372 count = 0; 373 p = qe2cpu_addr(bdp->buf, qe_port); 374 while (count < qe_port->tx_fifosize) { 375 *p++ = xmit->buf[xmit->tail]; 376 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 377 port->icount.tx++; 378 count++; 379 if (xmit->head == xmit->tail) 380 break; 381 } 382 383 out_be16(&bdp->length, count); 384 setbits16(&bdp->status, BD_SC_READY); 385 386 /* Get next BD. */ 387 if (in_be16(&bdp->status) & BD_SC_WRAP) 388 bdp = qe_port->tx_bd_base; 389 else 390 bdp++; 391 } 392 qe_port->tx_cur = bdp; 393 394 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 395 uart_write_wakeup(port); 396 397 if (uart_circ_empty(xmit)) { 398 /* The kernel buffer is empty, so turn off TX interrupts. We 399 don't need to be told when the QE is finished transmitting 400 the data. */ 401 qe_uart_stop_tx(port); 402 return 0; 403 } 404 405 return 1; 406 } 407 408 /* 409 * Start transmitting data 410 * 411 * This function will start transmitting any available data, if the port 412 * isn't already transmitting data. 413 */ 414 static void qe_uart_start_tx(struct uart_port *port) 415 { 416 struct uart_qe_port *qe_port = 417 container_of(port, struct uart_qe_port, port); 418 419 /* If we currently are transmitting, then just return */ 420 if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX) 421 return; 422 423 /* Otherwise, pump the port and start transmission */ 424 if (qe_uart_tx_pump(qe_port)) 425 setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); 426 } 427 428 /* 429 * Stop transmitting data 430 */ 431 static void qe_uart_stop_rx(struct uart_port *port) 432 { 433 struct uart_qe_port *qe_port = 434 container_of(port, struct uart_qe_port, port); 435 436 clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); 437 } 438 439 /* Start or stop sending break signal 440 * 441 * This function controls the sending of a break signal. If break_state=1, 442 * then we start sending a break signal. If break_state=0, then we stop 443 * sending the break signal. 444 */ 445 static void qe_uart_break_ctl(struct uart_port *port, int break_state) 446 { 447 struct uart_qe_port *qe_port = 448 container_of(port, struct uart_qe_port, port); 449 450 if (break_state) 451 ucc_slow_stop_tx(qe_port->us_private); 452 else 453 ucc_slow_restart_tx(qe_port->us_private); 454 } 455 456 /* ISR helper function for receiving character. 457 * 458 * This function is called by the ISR to handling receiving characters 459 */ 460 static void qe_uart_int_rx(struct uart_qe_port *qe_port) 461 { 462 int i; 463 unsigned char ch, *cp; 464 struct uart_port *port = &qe_port->port; 465 struct tty_port *tport = &port->state->port; 466 struct qe_bd *bdp; 467 u16 status; 468 unsigned int flg; 469 470 /* Just loop through the closed BDs and copy the characters into 471 * the buffer. 472 */ 473 bdp = qe_port->rx_cur; 474 while (1) { 475 status = in_be16(&bdp->status); 476 477 /* If this one is empty, then we assume we've read them all */ 478 if (status & BD_SC_EMPTY) 479 break; 480 481 /* get number of characters, and check space in RX buffer */ 482 i = in_be16(&bdp->length); 483 484 /* If we don't have enough room in RX buffer for the entire BD, 485 * then we try later, which will be the next RX interrupt. 486 */ 487 if (tty_buffer_request_room(tport, i) < i) { 488 dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n"); 489 return; 490 } 491 492 /* get pointer */ 493 cp = qe2cpu_addr(bdp->buf, qe_port); 494 495 /* loop through the buffer */ 496 while (i-- > 0) { 497 ch = *cp++; 498 port->icount.rx++; 499 flg = TTY_NORMAL; 500 501 if (!i && status & 502 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) 503 goto handle_error; 504 if (uart_handle_sysrq_char(port, ch)) 505 continue; 506 507 error_return: 508 tty_insert_flip_char(tport, ch, flg); 509 510 } 511 512 /* This BD is ready to be used again. Clear status. get next */ 513 clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR | 514 BD_SC_OV | BD_SC_ID, BD_SC_EMPTY); 515 if (in_be16(&bdp->status) & BD_SC_WRAP) 516 bdp = qe_port->rx_bd_base; 517 else 518 bdp++; 519 520 } 521 522 /* Write back buffer pointer */ 523 qe_port->rx_cur = bdp; 524 525 /* Activate BH processing */ 526 tty_flip_buffer_push(tport); 527 528 return; 529 530 /* Error processing */ 531 532 handle_error: 533 /* Statistics */ 534 if (status & BD_SC_BR) 535 port->icount.brk++; 536 if (status & BD_SC_PR) 537 port->icount.parity++; 538 if (status & BD_SC_FR) 539 port->icount.frame++; 540 if (status & BD_SC_OV) 541 port->icount.overrun++; 542 543 /* Mask out ignored conditions */ 544 status &= port->read_status_mask; 545 546 /* Handle the remaining ones */ 547 if (status & BD_SC_BR) 548 flg = TTY_BREAK; 549 else if (status & BD_SC_PR) 550 flg = TTY_PARITY; 551 else if (status & BD_SC_FR) 552 flg = TTY_FRAME; 553 554 /* Overrun does not affect the current character ! */ 555 if (status & BD_SC_OV) 556 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 557 #ifdef SUPPORT_SYSRQ 558 port->sysrq = 0; 559 #endif 560 goto error_return; 561 } 562 563 /* Interrupt handler 564 * 565 * This interrupt handler is called after a BD is processed. 566 */ 567 static irqreturn_t qe_uart_int(int irq, void *data) 568 { 569 struct uart_qe_port *qe_port = (struct uart_qe_port *) data; 570 struct ucc_slow __iomem *uccp = qe_port->uccp; 571 u16 events; 572 573 /* Clear the interrupts */ 574 events = in_be16(&uccp->ucce); 575 out_be16(&uccp->ucce, events); 576 577 if (events & UCC_UART_UCCE_BRKE) 578 uart_handle_break(&qe_port->port); 579 580 if (events & UCC_UART_UCCE_RX) 581 qe_uart_int_rx(qe_port); 582 583 if (events & UCC_UART_UCCE_TX) 584 qe_uart_tx_pump(qe_port); 585 586 return events ? IRQ_HANDLED : IRQ_NONE; 587 } 588 589 /* Initialize buffer descriptors 590 * 591 * This function initializes all of the RX and TX buffer descriptors. 592 */ 593 static void qe_uart_initbd(struct uart_qe_port *qe_port) 594 { 595 int i; 596 void *bd_virt; 597 struct qe_bd *bdp; 598 599 /* Set the physical address of the host memory buffers in the buffer 600 * descriptors, and the virtual address for us to work with. 601 */ 602 bd_virt = qe_port->bd_virt; 603 bdp = qe_port->rx_bd_base; 604 qe_port->rx_cur = qe_port->rx_bd_base; 605 for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) { 606 out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT); 607 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); 608 out_be16(&bdp->length, 0); 609 bd_virt += qe_port->rx_fifosize; 610 bdp++; 611 } 612 613 /* */ 614 out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); 615 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); 616 out_be16(&bdp->length, 0); 617 618 /* Set the physical address of the host memory 619 * buffers in the buffer descriptors, and the 620 * virtual address for us to work with. 621 */ 622 bd_virt = qe_port->bd_virt + 623 L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); 624 qe_port->tx_cur = qe_port->tx_bd_base; 625 bdp = qe_port->tx_bd_base; 626 for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) { 627 out_be16(&bdp->status, BD_SC_INTRPT); 628 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); 629 out_be16(&bdp->length, 0); 630 bd_virt += qe_port->tx_fifosize; 631 bdp++; 632 } 633 634 /* Loopback requires the preamble bit to be set on the first TX BD */ 635 #ifdef LOOPBACK 636 setbits16(&qe_port->tx_cur->status, BD_SC_P); 637 #endif 638 639 out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT); 640 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); 641 out_be16(&bdp->length, 0); 642 } 643 644 /* 645 * Initialize a UCC for UART. 646 * 647 * This function configures a given UCC to be used as a UART device. Basic 648 * UCC initialization is handled in qe_uart_request_port(). This function 649 * does all the UART-specific stuff. 650 */ 651 static void qe_uart_init_ucc(struct uart_qe_port *qe_port) 652 { 653 u32 cecr_subblock; 654 struct ucc_slow __iomem *uccp = qe_port->uccp; 655 struct ucc_uart_pram *uccup = qe_port->uccup; 656 657 unsigned int i; 658 659 /* First, disable TX and RX in the UCC */ 660 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); 661 662 /* Program the UCC UART parameter RAM */ 663 out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE); 664 out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE); 665 out_be16(&uccup->common.mrblr, qe_port->rx_fifosize); 666 out_be16(&uccup->maxidl, 0x10); 667 out_be16(&uccup->brkcr, 1); 668 out_be16(&uccup->parec, 0); 669 out_be16(&uccup->frmec, 0); 670 out_be16(&uccup->nosec, 0); 671 out_be16(&uccup->brkec, 0); 672 out_be16(&uccup->uaddr[0], 0); 673 out_be16(&uccup->uaddr[1], 0); 674 out_be16(&uccup->toseq, 0); 675 for (i = 0; i < 8; i++) 676 out_be16(&uccup->cchars[i], 0xC000); 677 out_be16(&uccup->rccm, 0xc0ff); 678 679 /* Configure the GUMR registers for UART */ 680 if (soft_uart) { 681 /* Soft-UART requires a 1X multiplier for TX */ 682 clrsetbits_be32(&uccp->gumr_l, 683 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | 684 UCC_SLOW_GUMR_L_RDCR_MASK, 685 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | 686 UCC_SLOW_GUMR_L_RDCR_16); 687 688 clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW, 689 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX); 690 } else { 691 clrsetbits_be32(&uccp->gumr_l, 692 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | 693 UCC_SLOW_GUMR_L_RDCR_MASK, 694 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | 695 UCC_SLOW_GUMR_L_RDCR_16); 696 697 clrsetbits_be32(&uccp->gumr_h, 698 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX, 699 UCC_SLOW_GUMR_H_RFW); 700 } 701 702 #ifdef LOOPBACK 703 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, 704 UCC_SLOW_GUMR_L_DIAG_LOOP); 705 clrsetbits_be32(&uccp->gumr_h, 706 UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN, 707 UCC_SLOW_GUMR_H_CDS); 708 #endif 709 710 /* Disable rx interrupts and clear all pending events. */ 711 out_be16(&uccp->uccm, 0); 712 out_be16(&uccp->ucce, 0xffff); 713 out_be16(&uccp->udsr, 0x7e7e); 714 715 /* Initialize UPSMR */ 716 out_be16(&uccp->upsmr, 0); 717 718 if (soft_uart) { 719 out_be16(&uccup->supsmr, 0x30); 720 out_be16(&uccup->res92, 0); 721 out_be32(&uccup->rx_state, 0); 722 out_be32(&uccup->rx_cnt, 0); 723 out_8(&uccup->rx_bitmark, 0); 724 out_8(&uccup->rx_length, 10); 725 out_be32(&uccup->dump_ptr, 0x4000); 726 out_8(&uccup->rx_temp_dlst_qe, 0); 727 out_be32(&uccup->rx_frame_rem, 0); 728 out_8(&uccup->rx_frame_rem_size, 0); 729 /* Soft-UART requires TX to be 1X */ 730 out_8(&uccup->tx_mode, 731 UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1); 732 out_be16(&uccup->tx_state, 0); 733 out_8(&uccup->resD4, 0); 734 out_be16(&uccup->resD5, 0); 735 736 /* Set UART mode. 737 * Enable receive and transmit. 738 */ 739 740 /* From the microcode errata: 741 * 1.GUMR_L register, set mode=0010 (QMC). 742 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode). 743 * 3.Set GUMR_H[19:20] (Transparent mode) 744 * 4.Clear GUMR_H[26] (RFW) 745 * ... 746 * 6.Receiver must use 16x over sampling 747 */ 748 clrsetbits_be32(&uccp->gumr_l, 749 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | 750 UCC_SLOW_GUMR_L_RDCR_MASK, 751 UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | 752 UCC_SLOW_GUMR_L_RDCR_16); 753 754 clrsetbits_be32(&uccp->gumr_h, 755 UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN, 756 UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | 757 UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL); 758 759 #ifdef LOOPBACK 760 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, 761 UCC_SLOW_GUMR_L_DIAG_LOOP); 762 clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP | 763 UCC_SLOW_GUMR_H_CDS); 764 #endif 765 766 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); 767 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, 768 QE_CR_PROTOCOL_UNSPECIFIED, 0); 769 } else { 770 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); 771 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, 772 QE_CR_PROTOCOL_UART, 0); 773 } 774 } 775 776 /* 777 * Initialize the port. 778 */ 779 static int qe_uart_startup(struct uart_port *port) 780 { 781 struct uart_qe_port *qe_port = 782 container_of(port, struct uart_qe_port, port); 783 int ret; 784 785 /* 786 * If we're using Soft-UART mode, then we need to make sure the 787 * firmware has been uploaded first. 788 */ 789 if (soft_uart && !firmware_loaded) { 790 dev_err(port->dev, "Soft-UART firmware not uploaded\n"); 791 return -ENODEV; 792 } 793 794 qe_uart_initbd(qe_port); 795 qe_uart_init_ucc(qe_port); 796 797 /* Install interrupt handler. */ 798 ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart", 799 qe_port); 800 if (ret) { 801 dev_err(port->dev, "could not claim IRQ %u\n", port->irq); 802 return ret; 803 } 804 805 /* Startup rx-int */ 806 setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); 807 ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX); 808 809 return 0; 810 } 811 812 /* 813 * Shutdown the port. 814 */ 815 static void qe_uart_shutdown(struct uart_port *port) 816 { 817 struct uart_qe_port *qe_port = 818 container_of(port, struct uart_qe_port, port); 819 struct ucc_slow __iomem *uccp = qe_port->uccp; 820 unsigned int timeout = 20; 821 822 /* Disable RX and TX */ 823 824 /* Wait for all the BDs marked sent */ 825 while (!qe_uart_tx_empty(port)) { 826 if (!--timeout) { 827 dev_warn(port->dev, "shutdown timeout\n"); 828 break; 829 } 830 set_current_state(TASK_UNINTERRUPTIBLE); 831 schedule_timeout(2); 832 } 833 834 if (qe_port->wait_closing) { 835 /* Wait a bit longer */ 836 set_current_state(TASK_UNINTERRUPTIBLE); 837 schedule_timeout(qe_port->wait_closing); 838 } 839 840 /* Stop uarts */ 841 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); 842 clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX); 843 844 /* Shut them really down and reinit buffer descriptors */ 845 ucc_slow_graceful_stop_tx(qe_port->us_private); 846 qe_uart_initbd(qe_port); 847 848 free_irq(port->irq, qe_port); 849 } 850 851 /* 852 * Set the serial port parameters. 853 */ 854 static void qe_uart_set_termios(struct uart_port *port, 855 struct ktermios *termios, struct ktermios *old) 856 { 857 struct uart_qe_port *qe_port = 858 container_of(port, struct uart_qe_port, port); 859 struct ucc_slow __iomem *uccp = qe_port->uccp; 860 unsigned int baud; 861 unsigned long flags; 862 u16 upsmr = in_be16(&uccp->upsmr); 863 struct ucc_uart_pram __iomem *uccup = qe_port->uccup; 864 u16 supsmr = in_be16(&uccup->supsmr); 865 u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */ 866 867 /* Character length programmed into the mode register is the 868 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, 869 * 1 or 2 stop bits, minus 1. 870 * The value 'bits' counts this for us. 871 */ 872 873 /* byte size */ 874 upsmr &= UCC_UART_UPSMR_CL_MASK; 875 supsmr &= UCC_UART_SUPSMR_CL_MASK; 876 877 switch (termios->c_cflag & CSIZE) { 878 case CS5: 879 upsmr |= UCC_UART_UPSMR_CL_5; 880 supsmr |= UCC_UART_SUPSMR_CL_5; 881 char_length += 5; 882 break; 883 case CS6: 884 upsmr |= UCC_UART_UPSMR_CL_6; 885 supsmr |= UCC_UART_SUPSMR_CL_6; 886 char_length += 6; 887 break; 888 case CS7: 889 upsmr |= UCC_UART_UPSMR_CL_7; 890 supsmr |= UCC_UART_SUPSMR_CL_7; 891 char_length += 7; 892 break; 893 default: /* case CS8 */ 894 upsmr |= UCC_UART_UPSMR_CL_8; 895 supsmr |= UCC_UART_SUPSMR_CL_8; 896 char_length += 8; 897 break; 898 } 899 900 /* If CSTOPB is set, we want two stop bits */ 901 if (termios->c_cflag & CSTOPB) { 902 upsmr |= UCC_UART_UPSMR_SL; 903 supsmr |= UCC_UART_SUPSMR_SL; 904 char_length++; /* + SL */ 905 } 906 907 if (termios->c_cflag & PARENB) { 908 upsmr |= UCC_UART_UPSMR_PEN; 909 supsmr |= UCC_UART_SUPSMR_PEN; 910 char_length++; /* + PEN */ 911 912 if (!(termios->c_cflag & PARODD)) { 913 upsmr &= ~(UCC_UART_UPSMR_RPM_MASK | 914 UCC_UART_UPSMR_TPM_MASK); 915 upsmr |= UCC_UART_UPSMR_RPM_EVEN | 916 UCC_UART_UPSMR_TPM_EVEN; 917 supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK | 918 UCC_UART_SUPSMR_TPM_MASK); 919 supsmr |= UCC_UART_SUPSMR_RPM_EVEN | 920 UCC_UART_SUPSMR_TPM_EVEN; 921 } 922 } 923 924 /* 925 * Set up parity check flag 926 */ 927 port->read_status_mask = BD_SC_EMPTY | BD_SC_OV; 928 if (termios->c_iflag & INPCK) 929 port->read_status_mask |= BD_SC_FR | BD_SC_PR; 930 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 931 port->read_status_mask |= BD_SC_BR; 932 933 /* 934 * Characters to ignore 935 */ 936 port->ignore_status_mask = 0; 937 if (termios->c_iflag & IGNPAR) 938 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; 939 if (termios->c_iflag & IGNBRK) { 940 port->ignore_status_mask |= BD_SC_BR; 941 /* 942 * If we're ignore parity and break indicators, ignore 943 * overruns too. (For real raw support). 944 */ 945 if (termios->c_iflag & IGNPAR) 946 port->ignore_status_mask |= BD_SC_OV; 947 } 948 /* 949 * !!! ignore all characters if CREAD is not set 950 */ 951 if ((termios->c_cflag & CREAD) == 0) 952 port->read_status_mask &= ~BD_SC_EMPTY; 953 954 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 955 956 /* Do we really need a spinlock here? */ 957 spin_lock_irqsave(&port->lock, flags); 958 959 /* Update the per-port timeout. */ 960 uart_update_timeout(port, termios->c_cflag, baud); 961 962 out_be16(&uccp->upsmr, upsmr); 963 if (soft_uart) { 964 out_be16(&uccup->supsmr, supsmr); 965 out_8(&uccup->rx_length, char_length); 966 967 /* Soft-UART requires a 1X multiplier for TX */ 968 qe_setbrg(qe_port->us_info.rx_clock, baud, 16); 969 qe_setbrg(qe_port->us_info.tx_clock, baud, 1); 970 } else { 971 qe_setbrg(qe_port->us_info.rx_clock, baud, 16); 972 qe_setbrg(qe_port->us_info.tx_clock, baud, 16); 973 } 974 975 spin_unlock_irqrestore(&port->lock, flags); 976 } 977 978 /* 979 * Return a pointer to a string that describes what kind of port this is. 980 */ 981 static const char *qe_uart_type(struct uart_port *port) 982 { 983 return "QE"; 984 } 985 986 /* 987 * Allocate any memory and I/O resources required by the port. 988 */ 989 static int qe_uart_request_port(struct uart_port *port) 990 { 991 int ret; 992 struct uart_qe_port *qe_port = 993 container_of(port, struct uart_qe_port, port); 994 struct ucc_slow_info *us_info = &qe_port->us_info; 995 struct ucc_slow_private *uccs; 996 unsigned int rx_size, tx_size; 997 void *bd_virt; 998 dma_addr_t bd_dma_addr = 0; 999 1000 ret = ucc_slow_init(us_info, &uccs); 1001 if (ret) { 1002 dev_err(port->dev, "could not initialize UCC%u\n", 1003 qe_port->ucc_num); 1004 return ret; 1005 } 1006 1007 qe_port->us_private = uccs; 1008 qe_port->uccp = uccs->us_regs; 1009 qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram; 1010 qe_port->rx_bd_base = uccs->rx_bd; 1011 qe_port->tx_bd_base = uccs->tx_bd; 1012 1013 /* 1014 * Allocate the transmit and receive data buffers. 1015 */ 1016 1017 rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); 1018 tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize); 1019 1020 bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr, 1021 GFP_KERNEL); 1022 if (!bd_virt) { 1023 dev_err(port->dev, "could not allocate buffer descriptors\n"); 1024 return -ENOMEM; 1025 } 1026 1027 qe_port->bd_virt = bd_virt; 1028 qe_port->bd_dma_addr = bd_dma_addr; 1029 qe_port->bd_size = rx_size + tx_size; 1030 1031 qe_port->rx_buf = bd_virt; 1032 qe_port->tx_buf = qe_port->rx_buf + rx_size; 1033 1034 return 0; 1035 } 1036 1037 /* 1038 * Configure the port. 1039 * 1040 * We say we're a CPM-type port because that's mostly true. Once the device 1041 * is configured, this driver operates almost identically to the CPM serial 1042 * driver. 1043 */ 1044 static void qe_uart_config_port(struct uart_port *port, int flags) 1045 { 1046 if (flags & UART_CONFIG_TYPE) { 1047 port->type = PORT_CPM; 1048 qe_uart_request_port(port); 1049 } 1050 } 1051 1052 /* 1053 * Release any memory and I/O resources that were allocated in 1054 * qe_uart_request_port(). 1055 */ 1056 static void qe_uart_release_port(struct uart_port *port) 1057 { 1058 struct uart_qe_port *qe_port = 1059 container_of(port, struct uart_qe_port, port); 1060 struct ucc_slow_private *uccs = qe_port->us_private; 1061 1062 dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt, 1063 qe_port->bd_dma_addr); 1064 1065 ucc_slow_free(uccs); 1066 } 1067 1068 /* 1069 * Verify that the data in serial_struct is suitable for this device. 1070 */ 1071 static int qe_uart_verify_port(struct uart_port *port, 1072 struct serial_struct *ser) 1073 { 1074 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) 1075 return -EINVAL; 1076 1077 if (ser->irq < 0 || ser->irq >= nr_irqs) 1078 return -EINVAL; 1079 1080 if (ser->baud_base < 9600) 1081 return -EINVAL; 1082 1083 return 0; 1084 } 1085 /* UART operations 1086 * 1087 * Details on these functions can be found in Documentation/serial/driver 1088 */ 1089 static const struct uart_ops qe_uart_pops = { 1090 .tx_empty = qe_uart_tx_empty, 1091 .set_mctrl = qe_uart_set_mctrl, 1092 .get_mctrl = qe_uart_get_mctrl, 1093 .stop_tx = qe_uart_stop_tx, 1094 .start_tx = qe_uart_start_tx, 1095 .stop_rx = qe_uart_stop_rx, 1096 .break_ctl = qe_uart_break_ctl, 1097 .startup = qe_uart_startup, 1098 .shutdown = qe_uart_shutdown, 1099 .set_termios = qe_uart_set_termios, 1100 .type = qe_uart_type, 1101 .release_port = qe_uart_release_port, 1102 .request_port = qe_uart_request_port, 1103 .config_port = qe_uart_config_port, 1104 .verify_port = qe_uart_verify_port, 1105 }; 1106 1107 /* 1108 * Obtain the SOC model number and revision level 1109 * 1110 * This function parses the device tree to obtain the SOC model. It then 1111 * reads the SVR register to the revision. 1112 * 1113 * The device tree stores the SOC model two different ways. 1114 * 1115 * The new way is: 1116 * 1117 * cpu@0 { 1118 * compatible = "PowerPC,8323"; 1119 * device_type = "cpu"; 1120 * ... 1121 * 1122 * 1123 * The old way is: 1124 * PowerPC,8323@0 { 1125 * device_type = "cpu"; 1126 * ... 1127 * 1128 * This code first checks the new way, and then the old way. 1129 */ 1130 static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l) 1131 { 1132 struct device_node *np; 1133 const char *soc_string; 1134 unsigned int svr; 1135 unsigned int soc; 1136 1137 /* Find the CPU node */ 1138 np = of_find_node_by_type(NULL, "cpu"); 1139 if (!np) 1140 return 0; 1141 /* Find the compatible property */ 1142 soc_string = of_get_property(np, "compatible", NULL); 1143 if (!soc_string) 1144 /* No compatible property, so try the name. */ 1145 soc_string = np->name; 1146 1147 /* Extract the SOC number from the "PowerPC," string */ 1148 if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc) 1149 return 0; 1150 1151 /* Get the revision from the SVR */ 1152 svr = mfspr(SPRN_SVR); 1153 *rev_h = (svr >> 4) & 0xf; 1154 *rev_l = svr & 0xf; 1155 1156 return soc; 1157 } 1158 1159 /* 1160 * requst_firmware_nowait() callback function 1161 * 1162 * This function is called by the kernel when a firmware is made available, 1163 * or if it times out waiting for the firmware. 1164 */ 1165 static void uart_firmware_cont(const struct firmware *fw, void *context) 1166 { 1167 struct qe_firmware *firmware; 1168 struct device *dev = context; 1169 int ret; 1170 1171 if (!fw) { 1172 dev_err(dev, "firmware not found\n"); 1173 return; 1174 } 1175 1176 firmware = (struct qe_firmware *) fw->data; 1177 1178 if (firmware->header.length != fw->size) { 1179 dev_err(dev, "invalid firmware\n"); 1180 goto out; 1181 } 1182 1183 ret = qe_upload_firmware(firmware); 1184 if (ret) { 1185 dev_err(dev, "could not load firmware\n"); 1186 goto out; 1187 } 1188 1189 firmware_loaded = 1; 1190 out: 1191 release_firmware(fw); 1192 } 1193 1194 static int ucc_uart_probe(struct platform_device *ofdev) 1195 { 1196 struct device_node *np = ofdev->dev.of_node; 1197 const unsigned int *iprop; /* Integer OF properties */ 1198 const char *sprop; /* String OF properties */ 1199 struct uart_qe_port *qe_port = NULL; 1200 struct resource res; 1201 int ret; 1202 1203 /* 1204 * Determine if we need Soft-UART mode 1205 */ 1206 if (of_find_property(np, "soft-uart", NULL)) { 1207 dev_dbg(&ofdev->dev, "using Soft-UART mode\n"); 1208 soft_uart = 1; 1209 } 1210 1211 /* 1212 * If we are using Soft-UART, determine if we need to upload the 1213 * firmware, too. 1214 */ 1215 if (soft_uart) { 1216 struct qe_firmware_info *qe_fw_info; 1217 1218 qe_fw_info = qe_get_firmware_info(); 1219 1220 /* Check if the firmware has been uploaded. */ 1221 if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) { 1222 firmware_loaded = 1; 1223 } else { 1224 char filename[32]; 1225 unsigned int soc; 1226 unsigned int rev_h; 1227 unsigned int rev_l; 1228 1229 soc = soc_info(&rev_h, &rev_l); 1230 if (!soc) { 1231 dev_err(&ofdev->dev, "unknown CPU model\n"); 1232 return -ENXIO; 1233 } 1234 sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin", 1235 soc, rev_h, rev_l); 1236 1237 dev_info(&ofdev->dev, "waiting for firmware %s\n", 1238 filename); 1239 1240 /* 1241 * We call request_firmware_nowait instead of 1242 * request_firmware so that the driver can load and 1243 * initialize the ports without holding up the rest of 1244 * the kernel. If hotplug support is enabled in the 1245 * kernel, then we use it. 1246 */ 1247 ret = request_firmware_nowait(THIS_MODULE, 1248 FW_ACTION_HOTPLUG, filename, &ofdev->dev, 1249 GFP_KERNEL, &ofdev->dev, uart_firmware_cont); 1250 if (ret) { 1251 dev_err(&ofdev->dev, 1252 "could not load firmware %s\n", 1253 filename); 1254 return ret; 1255 } 1256 } 1257 } 1258 1259 qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL); 1260 if (!qe_port) { 1261 dev_err(&ofdev->dev, "can't allocate QE port structure\n"); 1262 return -ENOMEM; 1263 } 1264 1265 /* Search for IRQ and mapbase */ 1266 ret = of_address_to_resource(np, 0, &res); 1267 if (ret) { 1268 dev_err(&ofdev->dev, "missing 'reg' property in device tree\n"); 1269 goto out_free; 1270 } 1271 if (!res.start) { 1272 dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n"); 1273 ret = -EINVAL; 1274 goto out_free; 1275 } 1276 qe_port->port.mapbase = res.start; 1277 1278 /* Get the UCC number (device ID) */ 1279 /* UCCs are numbered 1-7 */ 1280 iprop = of_get_property(np, "cell-index", NULL); 1281 if (!iprop) { 1282 iprop = of_get_property(np, "device-id", NULL); 1283 if (!iprop) { 1284 dev_err(&ofdev->dev, "UCC is unspecified in " 1285 "device tree\n"); 1286 ret = -EINVAL; 1287 goto out_free; 1288 } 1289 } 1290 1291 if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) { 1292 dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop); 1293 ret = -ENODEV; 1294 goto out_free; 1295 } 1296 qe_port->ucc_num = *iprop - 1; 1297 1298 /* 1299 * In the future, we should not require the BRG to be specified in the 1300 * device tree. If no clock-source is specified, then just pick a BRG 1301 * to use. This requires a new QE library function that manages BRG 1302 * assignments. 1303 */ 1304 1305 sprop = of_get_property(np, "rx-clock-name", NULL); 1306 if (!sprop) { 1307 dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n"); 1308 ret = -ENODEV; 1309 goto out_free; 1310 } 1311 1312 qe_port->us_info.rx_clock = qe_clock_source(sprop); 1313 if ((qe_port->us_info.rx_clock < QE_BRG1) || 1314 (qe_port->us_info.rx_clock > QE_BRG16)) { 1315 dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n"); 1316 ret = -ENODEV; 1317 goto out_free; 1318 } 1319 1320 #ifdef LOOPBACK 1321 /* In internal loopback mode, TX and RX must use the same clock */ 1322 qe_port->us_info.tx_clock = qe_port->us_info.rx_clock; 1323 #else 1324 sprop = of_get_property(np, "tx-clock-name", NULL); 1325 if (!sprop) { 1326 dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n"); 1327 ret = -ENODEV; 1328 goto out_free; 1329 } 1330 qe_port->us_info.tx_clock = qe_clock_source(sprop); 1331 #endif 1332 if ((qe_port->us_info.tx_clock < QE_BRG1) || 1333 (qe_port->us_info.tx_clock > QE_BRG16)) { 1334 dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n"); 1335 ret = -ENODEV; 1336 goto out_free; 1337 } 1338 1339 /* Get the port number, numbered 0-3 */ 1340 iprop = of_get_property(np, "port-number", NULL); 1341 if (!iprop) { 1342 dev_err(&ofdev->dev, "missing port-number in device tree\n"); 1343 ret = -EINVAL; 1344 goto out_free; 1345 } 1346 qe_port->port.line = *iprop; 1347 if (qe_port->port.line >= UCC_MAX_UART) { 1348 dev_err(&ofdev->dev, "port-number must be 0-%u\n", 1349 UCC_MAX_UART - 1); 1350 ret = -EINVAL; 1351 goto out_free; 1352 } 1353 1354 qe_port->port.irq = irq_of_parse_and_map(np, 0); 1355 if (qe_port->port.irq == 0) { 1356 dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n", 1357 qe_port->ucc_num + 1); 1358 ret = -EINVAL; 1359 goto out_free; 1360 } 1361 1362 /* 1363 * Newer device trees have an "fsl,qe" compatible property for the QE 1364 * node, but we still need to support older device trees. 1365 */ 1366 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 1367 if (!np) { 1368 np = of_find_node_by_type(NULL, "qe"); 1369 if (!np) { 1370 dev_err(&ofdev->dev, "could not find 'qe' node\n"); 1371 ret = -EINVAL; 1372 goto out_free; 1373 } 1374 } 1375 1376 iprop = of_get_property(np, "brg-frequency", NULL); 1377 if (!iprop) { 1378 dev_err(&ofdev->dev, 1379 "missing brg-frequency in device tree\n"); 1380 ret = -EINVAL; 1381 goto out_np; 1382 } 1383 1384 if (*iprop) 1385 qe_port->port.uartclk = *iprop; 1386 else { 1387 /* 1388 * Older versions of U-Boot do not initialize the brg-frequency 1389 * property, so in this case we assume the BRG frequency is 1390 * half the QE bus frequency. 1391 */ 1392 iprop = of_get_property(np, "bus-frequency", NULL); 1393 if (!iprop) { 1394 dev_err(&ofdev->dev, 1395 "missing QE bus-frequency in device tree\n"); 1396 ret = -EINVAL; 1397 goto out_np; 1398 } 1399 if (*iprop) 1400 qe_port->port.uartclk = *iprop / 2; 1401 else { 1402 dev_err(&ofdev->dev, 1403 "invalid QE bus-frequency in device tree\n"); 1404 ret = -EINVAL; 1405 goto out_np; 1406 } 1407 } 1408 1409 spin_lock_init(&qe_port->port.lock); 1410 qe_port->np = np; 1411 qe_port->port.dev = &ofdev->dev; 1412 qe_port->port.ops = &qe_uart_pops; 1413 qe_port->port.iotype = UPIO_MEM; 1414 1415 qe_port->tx_nrfifos = TX_NUM_FIFO; 1416 qe_port->tx_fifosize = TX_BUF_SIZE; 1417 qe_port->rx_nrfifos = RX_NUM_FIFO; 1418 qe_port->rx_fifosize = RX_BUF_SIZE; 1419 1420 qe_port->wait_closing = UCC_WAIT_CLOSING; 1421 qe_port->port.fifosize = 512; 1422 qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 1423 1424 qe_port->us_info.ucc_num = qe_port->ucc_num; 1425 qe_port->us_info.regs = (phys_addr_t) res.start; 1426 qe_port->us_info.irq = qe_port->port.irq; 1427 1428 qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos; 1429 qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos; 1430 1431 /* Make sure ucc_slow_init() initializes both TX and RX */ 1432 qe_port->us_info.init_tx = 1; 1433 qe_port->us_info.init_rx = 1; 1434 1435 /* Add the port to the uart sub-system. This will cause 1436 * qe_uart_config_port() to be called, so the us_info structure must 1437 * be initialized. 1438 */ 1439 ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port); 1440 if (ret) { 1441 dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n", 1442 qe_port->port.line); 1443 goto out_np; 1444 } 1445 1446 platform_set_drvdata(ofdev, qe_port); 1447 1448 dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n", 1449 qe_port->ucc_num + 1, qe_port->port.line); 1450 1451 /* Display the mknod command for this device */ 1452 dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n", 1453 qe_port->port.line, SERIAL_QE_MAJOR, 1454 SERIAL_QE_MINOR + qe_port->port.line); 1455 1456 return 0; 1457 out_np: 1458 of_node_put(np); 1459 out_free: 1460 kfree(qe_port); 1461 return ret; 1462 } 1463 1464 static int ucc_uart_remove(struct platform_device *ofdev) 1465 { 1466 struct uart_qe_port *qe_port = platform_get_drvdata(ofdev); 1467 1468 dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line); 1469 1470 uart_remove_one_port(&ucc_uart_driver, &qe_port->port); 1471 1472 kfree(qe_port); 1473 1474 return 0; 1475 } 1476 1477 static const struct of_device_id ucc_uart_match[] = { 1478 { 1479 .type = "serial", 1480 .compatible = "ucc_uart", 1481 }, 1482 { 1483 .compatible = "fsl,t1040-ucc-uart", 1484 }, 1485 {}, 1486 }; 1487 MODULE_DEVICE_TABLE(of, ucc_uart_match); 1488 1489 static struct platform_driver ucc_uart_of_driver = { 1490 .driver = { 1491 .name = "ucc_uart", 1492 .of_match_table = ucc_uart_match, 1493 }, 1494 .probe = ucc_uart_probe, 1495 .remove = ucc_uart_remove, 1496 }; 1497 1498 static int __init ucc_uart_init(void) 1499 { 1500 int ret; 1501 1502 printk(KERN_INFO "Freescale QUICC Engine UART device driver\n"); 1503 #ifdef LOOPBACK 1504 printk(KERN_INFO "ucc-uart: Using loopback mode\n"); 1505 #endif 1506 1507 ret = uart_register_driver(&ucc_uart_driver); 1508 if (ret) { 1509 printk(KERN_ERR "ucc-uart: could not register UART driver\n"); 1510 return ret; 1511 } 1512 1513 ret = platform_driver_register(&ucc_uart_of_driver); 1514 if (ret) { 1515 printk(KERN_ERR 1516 "ucc-uart: could not register platform driver\n"); 1517 uart_unregister_driver(&ucc_uart_driver); 1518 } 1519 1520 return ret; 1521 } 1522 1523 static void __exit ucc_uart_exit(void) 1524 { 1525 printk(KERN_INFO 1526 "Freescale QUICC Engine UART device driver unloading\n"); 1527 1528 platform_driver_unregister(&ucc_uart_of_driver); 1529 uart_unregister_driver(&ucc_uart_driver); 1530 } 1531 1532 module_init(ucc_uart_init); 1533 module_exit(ucc_uart_exit); 1534 1535 MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART"); 1536 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1537 MODULE_LICENSE("GPL v2"); 1538 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR); 1539 1540