1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Freescale QUICC Engine UART device driver 4 * 5 * Author: Timur Tabi <timur@freescale.com> 6 * 7 * Copyright 2007 Freescale Semiconductor, Inc. 8 * 9 * This driver adds support for UART devices via Freescale's QUICC Engine 10 * found on some Freescale SOCs. 11 * 12 * If Soft-UART support is needed but not already present, then this driver 13 * will request and upload the "Soft-UART" microcode upon probe. The 14 * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X" 15 * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC, 16 * (e.g. "11" for 1.1). 17 */ 18 19 #include <linux/module.h> 20 #include <linux/serial.h> 21 #include <linux/serial_core.h> 22 #include <linux/slab.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/io.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_platform.h> 29 #include <linux/dma-mapping.h> 30 31 #include <linux/fs_uart_pd.h> 32 #include <soc/fsl/qe/ucc_slow.h> 33 34 #include <linux/firmware.h> 35 #include <soc/fsl/cpm.h> 36 37 #ifdef CONFIG_PPC32 38 #include <asm/reg.h> /* mfspr, SPRN_SVR */ 39 #endif 40 41 /* 42 * The GUMR flag for Soft UART. This would normally be defined in qe.h, 43 * but Soft-UART is a hack and we want to keep everything related to it in 44 * this file. 45 */ 46 #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */ 47 48 /* 49 * soft_uart is 1 if we need to use Soft-UART mode 50 */ 51 static int soft_uart; 52 /* 53 * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise. 54 */ 55 static int firmware_loaded; 56 57 /* Enable this macro to configure all serial ports in internal loopback 58 mode */ 59 /* #define LOOPBACK */ 60 61 /* The major and minor device numbers are defined in 62 * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE 63 * UART, we have major number 204 and minor numbers 46 - 49, which are the 64 * same as for the CPM2. This decision was made because no Freescale part 65 * has both a CPM and a QE. 66 */ 67 #define SERIAL_QE_MAJOR 204 68 #define SERIAL_QE_MINOR 46 69 70 /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */ 71 #define UCC_MAX_UART 4 72 73 /* The number of buffer descriptors for receiving characters. */ 74 #define RX_NUM_FIFO 4 75 76 /* The number of buffer descriptors for transmitting characters. */ 77 #define TX_NUM_FIFO 4 78 79 /* The maximum size of the character buffer for a single RX BD. */ 80 #define RX_BUF_SIZE 32 81 82 /* The maximum size of the character buffer for a single TX BD. */ 83 #define TX_BUF_SIZE 32 84 85 /* 86 * The number of jiffies to wait after receiving a close command before the 87 * device is actually closed. This allows the last few characters to be 88 * sent over the wire. 89 */ 90 #define UCC_WAIT_CLOSING 100 91 92 struct ucc_uart_pram { 93 struct ucc_slow_pram common; 94 u8 res1[8]; /* reserved */ 95 __be16 maxidl; /* Maximum idle chars */ 96 __be16 idlc; /* temp idle counter */ 97 __be16 brkcr; /* Break count register */ 98 __be16 parec; /* receive parity error counter */ 99 __be16 frmec; /* receive framing error counter */ 100 __be16 nosec; /* receive noise counter */ 101 __be16 brkec; /* receive break condition counter */ 102 __be16 brkln; /* last received break length */ 103 __be16 uaddr[2]; /* UART address character 1 & 2 */ 104 __be16 rtemp; /* Temp storage */ 105 __be16 toseq; /* Transmit out of sequence char */ 106 __be16 cchars[8]; /* control characters 1-8 */ 107 __be16 rccm; /* receive control character mask */ 108 __be16 rccr; /* receive control character register */ 109 __be16 rlbc; /* receive last break character */ 110 __be16 res2; /* reserved */ 111 __be32 res3; /* reserved, should be cleared */ 112 u8 res4; /* reserved, should be cleared */ 113 u8 res5[3]; /* reserved, should be cleared */ 114 __be32 res6; /* reserved, should be cleared */ 115 __be32 res7; /* reserved, should be cleared */ 116 __be32 res8; /* reserved, should be cleared */ 117 __be32 res9; /* reserved, should be cleared */ 118 __be32 res10; /* reserved, should be cleared */ 119 __be32 res11; /* reserved, should be cleared */ 120 __be32 res12; /* reserved, should be cleared */ 121 __be32 res13; /* reserved, should be cleared */ 122 /* The rest is for Soft-UART only */ 123 __be16 supsmr; /* 0x90, Shadow UPSMR */ 124 __be16 res92; /* 0x92, reserved, initialize to 0 */ 125 __be32 rx_state; /* 0x94, RX state, initialize to 0 */ 126 __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */ 127 u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */ 128 u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */ 129 u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */ 130 u8 res14[0xBC - 0x9F]; /* reserved */ 131 __be32 dump_ptr; /* 0xBC, Dump pointer */ 132 __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */ 133 u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */ 134 u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */ 135 __be16 tx_state; /* 0xC6, TX state */ 136 u8 res15[0xD0 - 0xC8]; /* reserved */ 137 __be32 resD0; /* 0xD0, reserved, initialize to 0 */ 138 u8 resD4; /* 0xD4, reserved, initialize to 0 */ 139 __be16 resD5; /* 0xD5, reserved, initialize to 0 */ 140 } __attribute__ ((packed)); 141 142 /* SUPSMR definitions, for Soft-UART only */ 143 #define UCC_UART_SUPSMR_SL 0x8000 144 #define UCC_UART_SUPSMR_RPM_MASK 0x6000 145 #define UCC_UART_SUPSMR_RPM_ODD 0x0000 146 #define UCC_UART_SUPSMR_RPM_LOW 0x2000 147 #define UCC_UART_SUPSMR_RPM_EVEN 0x4000 148 #define UCC_UART_SUPSMR_RPM_HIGH 0x6000 149 #define UCC_UART_SUPSMR_PEN 0x1000 150 #define UCC_UART_SUPSMR_TPM_MASK 0x0C00 151 #define UCC_UART_SUPSMR_TPM_ODD 0x0000 152 #define UCC_UART_SUPSMR_TPM_LOW 0x0400 153 #define UCC_UART_SUPSMR_TPM_EVEN 0x0800 154 #define UCC_UART_SUPSMR_TPM_HIGH 0x0C00 155 #define UCC_UART_SUPSMR_FRZ 0x0100 156 #define UCC_UART_SUPSMR_UM_MASK 0x00c0 157 #define UCC_UART_SUPSMR_UM_NORMAL 0x0000 158 #define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040 159 #define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0 160 #define UCC_UART_SUPSMR_CL_MASK 0x0030 161 #define UCC_UART_SUPSMR_CL_8 0x0030 162 #define UCC_UART_SUPSMR_CL_7 0x0020 163 #define UCC_UART_SUPSMR_CL_6 0x0010 164 #define UCC_UART_SUPSMR_CL_5 0x0000 165 166 #define UCC_UART_TX_STATE_AHDLC 0x00 167 #define UCC_UART_TX_STATE_UART 0x01 168 #define UCC_UART_TX_STATE_X1 0x00 169 #define UCC_UART_TX_STATE_X16 0x80 170 171 #define UCC_UART_PRAM_ALIGNMENT 0x100 172 173 #define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD 174 #define NUM_CONTROL_CHARS 8 175 176 /* Private per-port data structure */ 177 struct uart_qe_port { 178 struct uart_port port; 179 struct ucc_slow __iomem *uccp; 180 struct ucc_uart_pram __iomem *uccup; 181 struct ucc_slow_info us_info; 182 struct ucc_slow_private *us_private; 183 struct device_node *np; 184 unsigned int ucc_num; /* First ucc is 0, not 1 */ 185 186 u16 rx_nrfifos; 187 u16 rx_fifosize; 188 u16 tx_nrfifos; 189 u16 tx_fifosize; 190 int wait_closing; 191 u32 flags; 192 struct qe_bd *rx_bd_base; 193 struct qe_bd *rx_cur; 194 struct qe_bd *tx_bd_base; 195 struct qe_bd *tx_cur; 196 unsigned char *tx_buf; 197 unsigned char *rx_buf; 198 void *bd_virt; /* virtual address of the BD buffers */ 199 dma_addr_t bd_dma_addr; /* bus address of the BD buffers */ 200 unsigned int bd_size; /* size of BD buffer space */ 201 }; 202 203 static struct uart_driver ucc_uart_driver = { 204 .owner = THIS_MODULE, 205 .driver_name = "ucc_uart", 206 .dev_name = "ttyQE", 207 .major = SERIAL_QE_MAJOR, 208 .minor = SERIAL_QE_MINOR, 209 .nr = UCC_MAX_UART, 210 }; 211 212 /* 213 * Virtual to physical address translation. 214 * 215 * Given the virtual address for a character buffer, this function returns 216 * the physical (DMA) equivalent. 217 */ 218 static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port) 219 { 220 if (likely((addr >= qe_port->bd_virt)) && 221 (addr < (qe_port->bd_virt + qe_port->bd_size))) 222 return qe_port->bd_dma_addr + (addr - qe_port->bd_virt); 223 224 /* something nasty happened */ 225 printk(KERN_ERR "%s: addr=%p\n", __func__, addr); 226 BUG(); 227 return 0; 228 } 229 230 /* 231 * Physical to virtual address translation. 232 * 233 * Given the physical (DMA) address for a character buffer, this function 234 * returns the virtual equivalent. 235 */ 236 static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port) 237 { 238 /* sanity check */ 239 if (likely((addr >= qe_port->bd_dma_addr) && 240 (addr < (qe_port->bd_dma_addr + qe_port->bd_size)))) 241 return qe_port->bd_virt + (addr - qe_port->bd_dma_addr); 242 243 /* something nasty happened */ 244 printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr); 245 BUG(); 246 return NULL; 247 } 248 249 /* 250 * Return 1 if the QE is done transmitting all buffers for this port 251 * 252 * This function scans each BD in sequence. If we find a BD that is not 253 * ready (READY=1), then we return 0 indicating that the QE is still sending 254 * data. If we reach the last BD (WRAP=1), then we know we've scanned 255 * the entire list, and all BDs are done. 256 */ 257 static unsigned int qe_uart_tx_empty(struct uart_port *port) 258 { 259 struct uart_qe_port *qe_port = 260 container_of(port, struct uart_qe_port, port); 261 struct qe_bd *bdp = qe_port->tx_bd_base; 262 263 while (1) { 264 if (ioread16be(&bdp->status) & BD_SC_READY) 265 /* This BD is not done, so return "not done" */ 266 return 0; 267 268 if (ioread16be(&bdp->status) & BD_SC_WRAP) 269 /* 270 * This BD is done and it's the last one, so return 271 * "done" 272 */ 273 return 1; 274 275 bdp++; 276 } 277 } 278 279 /* 280 * Set the modem control lines 281 * 282 * Although the QE can control the modem control lines (e.g. CTS), we 283 * don't need that support. This function must exist, however, otherwise 284 * the kernel will panic. 285 */ 286 static void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 287 { 288 } 289 290 /* 291 * Get the current modem control line status 292 * 293 * Although the QE can control the modem control lines (e.g. CTS), this 294 * driver currently doesn't support that, so we always return Carrier 295 * Detect, Data Set Ready, and Clear To Send. 296 */ 297 static unsigned int qe_uart_get_mctrl(struct uart_port *port) 298 { 299 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 300 } 301 302 /* 303 * Disable the transmit interrupt. 304 * 305 * Although this function is called "stop_tx", it does not actually stop 306 * transmission of data. Instead, it tells the QE to not generate an 307 * interrupt when the UCC is finished sending characters. 308 */ 309 static void qe_uart_stop_tx(struct uart_port *port) 310 { 311 struct uart_qe_port *qe_port = 312 container_of(port, struct uart_qe_port, port); 313 314 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); 315 } 316 317 /* 318 * Transmit as many characters to the HW as possible. 319 * 320 * This function will attempt to stuff of all the characters from the 321 * kernel's transmit buffer into TX BDs. 322 * 323 * A return value of non-zero indicates that it successfully stuffed all 324 * characters from the kernel buffer. 325 * 326 * A return value of zero indicates that there are still characters in the 327 * kernel's buffer that have not been transmitted, but there are no more BDs 328 * available. This function should be called again after a BD has been made 329 * available. 330 */ 331 static int qe_uart_tx_pump(struct uart_qe_port *qe_port) 332 { 333 struct qe_bd *bdp; 334 unsigned char *p; 335 unsigned int count; 336 struct uart_port *port = &qe_port->port; 337 struct circ_buf *xmit = &port->state->xmit; 338 339 /* Handle xon/xoff */ 340 if (port->x_char) { 341 /* Pick next descriptor and fill from buffer */ 342 bdp = qe_port->tx_cur; 343 344 p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port); 345 346 *p++ = port->x_char; 347 iowrite16be(1, &bdp->length); 348 qe_setbits_be16(&bdp->status, BD_SC_READY); 349 /* Get next BD. */ 350 if (ioread16be(&bdp->status) & BD_SC_WRAP) 351 bdp = qe_port->tx_bd_base; 352 else 353 bdp++; 354 qe_port->tx_cur = bdp; 355 356 port->icount.tx++; 357 port->x_char = 0; 358 return 1; 359 } 360 361 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 362 qe_uart_stop_tx(port); 363 return 0; 364 } 365 366 /* Pick next descriptor and fill from buffer */ 367 bdp = qe_port->tx_cur; 368 369 while (!(ioread16be(&bdp->status) & BD_SC_READY) && 370 (xmit->tail != xmit->head)) { 371 count = 0; 372 p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port); 373 while (count < qe_port->tx_fifosize) { 374 *p++ = xmit->buf[xmit->tail]; 375 uart_xmit_advance(port, 1); 376 count++; 377 if (xmit->head == xmit->tail) 378 break; 379 } 380 381 iowrite16be(count, &bdp->length); 382 qe_setbits_be16(&bdp->status, BD_SC_READY); 383 384 /* Get next BD. */ 385 if (ioread16be(&bdp->status) & BD_SC_WRAP) 386 bdp = qe_port->tx_bd_base; 387 else 388 bdp++; 389 } 390 qe_port->tx_cur = bdp; 391 392 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 393 uart_write_wakeup(port); 394 395 if (uart_circ_empty(xmit)) { 396 /* The kernel buffer is empty, so turn off TX interrupts. We 397 don't need to be told when the QE is finished transmitting 398 the data. */ 399 qe_uart_stop_tx(port); 400 return 0; 401 } 402 403 return 1; 404 } 405 406 /* 407 * Start transmitting data 408 * 409 * This function will start transmitting any available data, if the port 410 * isn't already transmitting data. 411 */ 412 static void qe_uart_start_tx(struct uart_port *port) 413 { 414 struct uart_qe_port *qe_port = 415 container_of(port, struct uart_qe_port, port); 416 417 /* If we currently are transmitting, then just return */ 418 if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX) 419 return; 420 421 /* Otherwise, pump the port and start transmission */ 422 if (qe_uart_tx_pump(qe_port)) 423 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); 424 } 425 426 /* 427 * Stop transmitting data 428 */ 429 static void qe_uart_stop_rx(struct uart_port *port) 430 { 431 struct uart_qe_port *qe_port = 432 container_of(port, struct uart_qe_port, port); 433 434 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); 435 } 436 437 /* Start or stop sending break signal 438 * 439 * This function controls the sending of a break signal. If break_state=1, 440 * then we start sending a break signal. If break_state=0, then we stop 441 * sending the break signal. 442 */ 443 static void qe_uart_break_ctl(struct uart_port *port, int break_state) 444 { 445 struct uart_qe_port *qe_port = 446 container_of(port, struct uart_qe_port, port); 447 448 if (break_state) 449 ucc_slow_stop_tx(qe_port->us_private); 450 else 451 ucc_slow_restart_tx(qe_port->us_private); 452 } 453 454 /* ISR helper function for receiving character. 455 * 456 * This function is called by the ISR to handling receiving characters 457 */ 458 static void qe_uart_int_rx(struct uart_qe_port *qe_port) 459 { 460 int i; 461 unsigned char ch, *cp; 462 struct uart_port *port = &qe_port->port; 463 struct tty_port *tport = &port->state->port; 464 struct qe_bd *bdp; 465 u16 status; 466 unsigned int flg; 467 468 /* Just loop through the closed BDs and copy the characters into 469 * the buffer. 470 */ 471 bdp = qe_port->rx_cur; 472 while (1) { 473 status = ioread16be(&bdp->status); 474 475 /* If this one is empty, then we assume we've read them all */ 476 if (status & BD_SC_EMPTY) 477 break; 478 479 /* get number of characters, and check space in RX buffer */ 480 i = ioread16be(&bdp->length); 481 482 /* If we don't have enough room in RX buffer for the entire BD, 483 * then we try later, which will be the next RX interrupt. 484 */ 485 if (tty_buffer_request_room(tport, i) < i) { 486 dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n"); 487 return; 488 } 489 490 /* get pointer */ 491 cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port); 492 493 /* loop through the buffer */ 494 while (i-- > 0) { 495 ch = *cp++; 496 port->icount.rx++; 497 flg = TTY_NORMAL; 498 499 if (!i && status & 500 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) 501 goto handle_error; 502 if (uart_handle_sysrq_char(port, ch)) 503 continue; 504 505 error_return: 506 tty_insert_flip_char(tport, ch, flg); 507 508 } 509 510 /* This BD is ready to be used again. Clear status. get next */ 511 qe_clrsetbits_be16(&bdp->status, 512 BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID, 513 BD_SC_EMPTY); 514 if (ioread16be(&bdp->status) & BD_SC_WRAP) 515 bdp = qe_port->rx_bd_base; 516 else 517 bdp++; 518 519 } 520 521 /* Write back buffer pointer */ 522 qe_port->rx_cur = bdp; 523 524 /* Activate BH processing */ 525 tty_flip_buffer_push(tport); 526 527 return; 528 529 /* Error processing */ 530 531 handle_error: 532 /* Statistics */ 533 if (status & BD_SC_BR) 534 port->icount.brk++; 535 if (status & BD_SC_PR) 536 port->icount.parity++; 537 if (status & BD_SC_FR) 538 port->icount.frame++; 539 if (status & BD_SC_OV) 540 port->icount.overrun++; 541 542 /* Mask out ignored conditions */ 543 status &= port->read_status_mask; 544 545 /* Handle the remaining ones */ 546 if (status & BD_SC_BR) 547 flg = TTY_BREAK; 548 else if (status & BD_SC_PR) 549 flg = TTY_PARITY; 550 else if (status & BD_SC_FR) 551 flg = TTY_FRAME; 552 553 /* Overrun does not affect the current character ! */ 554 if (status & BD_SC_OV) 555 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 556 port->sysrq = 0; 557 goto error_return; 558 } 559 560 /* Interrupt handler 561 * 562 * This interrupt handler is called after a BD is processed. 563 */ 564 static irqreturn_t qe_uart_int(int irq, void *data) 565 { 566 struct uart_qe_port *qe_port = (struct uart_qe_port *) data; 567 struct ucc_slow __iomem *uccp = qe_port->uccp; 568 u16 events; 569 570 /* Clear the interrupts */ 571 events = ioread16be(&uccp->ucce); 572 iowrite16be(events, &uccp->ucce); 573 574 if (events & UCC_UART_UCCE_BRKE) 575 uart_handle_break(&qe_port->port); 576 577 if (events & UCC_UART_UCCE_RX) 578 qe_uart_int_rx(qe_port); 579 580 if (events & UCC_UART_UCCE_TX) 581 qe_uart_tx_pump(qe_port); 582 583 return events ? IRQ_HANDLED : IRQ_NONE; 584 } 585 586 /* Initialize buffer descriptors 587 * 588 * This function initializes all of the RX and TX buffer descriptors. 589 */ 590 static void qe_uart_initbd(struct uart_qe_port *qe_port) 591 { 592 int i; 593 void *bd_virt; 594 struct qe_bd *bdp; 595 596 /* Set the physical address of the host memory buffers in the buffer 597 * descriptors, and the virtual address for us to work with. 598 */ 599 bd_virt = qe_port->bd_virt; 600 bdp = qe_port->rx_bd_base; 601 qe_port->rx_cur = qe_port->rx_bd_base; 602 for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) { 603 iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status); 604 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); 605 iowrite16be(0, &bdp->length); 606 bd_virt += qe_port->rx_fifosize; 607 bdp++; 608 } 609 610 /* */ 611 iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status); 612 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); 613 iowrite16be(0, &bdp->length); 614 615 /* Set the physical address of the host memory 616 * buffers in the buffer descriptors, and the 617 * virtual address for us to work with. 618 */ 619 bd_virt = qe_port->bd_virt + 620 L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); 621 qe_port->tx_cur = qe_port->tx_bd_base; 622 bdp = qe_port->tx_bd_base; 623 for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) { 624 iowrite16be(BD_SC_INTRPT, &bdp->status); 625 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); 626 iowrite16be(0, &bdp->length); 627 bd_virt += qe_port->tx_fifosize; 628 bdp++; 629 } 630 631 /* Loopback requires the preamble bit to be set on the first TX BD */ 632 #ifdef LOOPBACK 633 qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P); 634 #endif 635 636 iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status); 637 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); 638 iowrite16be(0, &bdp->length); 639 } 640 641 /* 642 * Initialize a UCC for UART. 643 * 644 * This function configures a given UCC to be used as a UART device. Basic 645 * UCC initialization is handled in qe_uart_request_port(). This function 646 * does all the UART-specific stuff. 647 */ 648 static void qe_uart_init_ucc(struct uart_qe_port *qe_port) 649 { 650 u32 cecr_subblock; 651 struct ucc_slow __iomem *uccp = qe_port->uccp; 652 struct ucc_uart_pram *uccup = qe_port->uccup; 653 654 unsigned int i; 655 656 /* First, disable TX and RX in the UCC */ 657 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); 658 659 /* Program the UCC UART parameter RAM */ 660 iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr); 661 iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr); 662 iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr); 663 iowrite16be(0x10, &uccup->maxidl); 664 iowrite16be(1, &uccup->brkcr); 665 iowrite16be(0, &uccup->parec); 666 iowrite16be(0, &uccup->frmec); 667 iowrite16be(0, &uccup->nosec); 668 iowrite16be(0, &uccup->brkec); 669 iowrite16be(0, &uccup->uaddr[0]); 670 iowrite16be(0, &uccup->uaddr[1]); 671 iowrite16be(0, &uccup->toseq); 672 for (i = 0; i < 8; i++) 673 iowrite16be(0xC000, &uccup->cchars[i]); 674 iowrite16be(0xc0ff, &uccup->rccm); 675 676 /* Configure the GUMR registers for UART */ 677 if (soft_uart) { 678 /* Soft-UART requires a 1X multiplier for TX */ 679 qe_clrsetbits_be32(&uccp->gumr_l, 680 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK, 681 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16); 682 683 qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW, 684 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX); 685 } else { 686 qe_clrsetbits_be32(&uccp->gumr_l, 687 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK, 688 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16); 689 690 qe_clrsetbits_be32(&uccp->gumr_h, 691 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX, 692 UCC_SLOW_GUMR_H_RFW); 693 } 694 695 #ifdef LOOPBACK 696 qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, 697 UCC_SLOW_GUMR_L_DIAG_LOOP); 698 qe_clrsetbits_be32(&uccp->gumr_h, 699 UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN, 700 UCC_SLOW_GUMR_H_CDS); 701 #endif 702 703 /* Disable rx interrupts and clear all pending events. */ 704 iowrite16be(0, &uccp->uccm); 705 iowrite16be(0xffff, &uccp->ucce); 706 iowrite16be(0x7e7e, &uccp->udsr); 707 708 /* Initialize UPSMR */ 709 iowrite16be(0, &uccp->upsmr); 710 711 if (soft_uart) { 712 iowrite16be(0x30, &uccup->supsmr); 713 iowrite16be(0, &uccup->res92); 714 iowrite32be(0, &uccup->rx_state); 715 iowrite32be(0, &uccup->rx_cnt); 716 iowrite8(0, &uccup->rx_bitmark); 717 iowrite8(10, &uccup->rx_length); 718 iowrite32be(0x4000, &uccup->dump_ptr); 719 iowrite8(0, &uccup->rx_temp_dlst_qe); 720 iowrite32be(0, &uccup->rx_frame_rem); 721 iowrite8(0, &uccup->rx_frame_rem_size); 722 /* Soft-UART requires TX to be 1X */ 723 iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1, 724 &uccup->tx_mode); 725 iowrite16be(0, &uccup->tx_state); 726 iowrite8(0, &uccup->resD4); 727 iowrite16be(0, &uccup->resD5); 728 729 /* Set UART mode. 730 * Enable receive and transmit. 731 */ 732 733 /* From the microcode errata: 734 * 1.GUMR_L register, set mode=0010 (QMC). 735 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode). 736 * 3.Set GUMR_H[19:20] (Transparent mode) 737 * 4.Clear GUMR_H[26] (RFW) 738 * ... 739 * 6.Receiver must use 16x over sampling 740 */ 741 qe_clrsetbits_be32(&uccp->gumr_l, 742 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK, 743 UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16); 744 745 qe_clrsetbits_be32(&uccp->gumr_h, 746 UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN, 747 UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL); 748 749 #ifdef LOOPBACK 750 qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, 751 UCC_SLOW_GUMR_L_DIAG_LOOP); 752 qe_clrbits_be32(&uccp->gumr_h, 753 UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS); 754 #endif 755 756 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); 757 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, 758 QE_CR_PROTOCOL_UNSPECIFIED, 0); 759 } else { 760 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); 761 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, 762 QE_CR_PROTOCOL_UART, 0); 763 } 764 } 765 766 /* 767 * Initialize the port. 768 */ 769 static int qe_uart_startup(struct uart_port *port) 770 { 771 struct uart_qe_port *qe_port = 772 container_of(port, struct uart_qe_port, port); 773 int ret; 774 775 /* 776 * If we're using Soft-UART mode, then we need to make sure the 777 * firmware has been uploaded first. 778 */ 779 if (soft_uart && !firmware_loaded) { 780 dev_err(port->dev, "Soft-UART firmware not uploaded\n"); 781 return -ENODEV; 782 } 783 784 qe_uart_initbd(qe_port); 785 qe_uart_init_ucc(qe_port); 786 787 /* Install interrupt handler. */ 788 ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart", 789 qe_port); 790 if (ret) { 791 dev_err(port->dev, "could not claim IRQ %u\n", port->irq); 792 return ret; 793 } 794 795 /* Startup rx-int */ 796 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); 797 ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX); 798 799 return 0; 800 } 801 802 /* 803 * Shutdown the port. 804 */ 805 static void qe_uart_shutdown(struct uart_port *port) 806 { 807 struct uart_qe_port *qe_port = 808 container_of(port, struct uart_qe_port, port); 809 struct ucc_slow __iomem *uccp = qe_port->uccp; 810 unsigned int timeout = 20; 811 812 /* Disable RX and TX */ 813 814 /* Wait for all the BDs marked sent */ 815 while (!qe_uart_tx_empty(port)) { 816 if (!--timeout) { 817 dev_warn(port->dev, "shutdown timeout\n"); 818 break; 819 } 820 set_current_state(TASK_UNINTERRUPTIBLE); 821 schedule_timeout(2); 822 } 823 824 if (qe_port->wait_closing) { 825 /* Wait a bit longer */ 826 set_current_state(TASK_UNINTERRUPTIBLE); 827 schedule_timeout(qe_port->wait_closing); 828 } 829 830 /* Stop uarts */ 831 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); 832 qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX); 833 834 /* Shut them really down and reinit buffer descriptors */ 835 ucc_slow_graceful_stop_tx(qe_port->us_private); 836 qe_uart_initbd(qe_port); 837 838 free_irq(port->irq, qe_port); 839 } 840 841 /* 842 * Set the serial port parameters. 843 */ 844 static void qe_uart_set_termios(struct uart_port *port, 845 struct ktermios *termios, 846 const struct ktermios *old) 847 { 848 struct uart_qe_port *qe_port = 849 container_of(port, struct uart_qe_port, port); 850 struct ucc_slow __iomem *uccp = qe_port->uccp; 851 unsigned int baud; 852 unsigned long flags; 853 u16 upsmr = ioread16be(&uccp->upsmr); 854 struct ucc_uart_pram __iomem *uccup = qe_port->uccup; 855 u16 supsmr = ioread16be(&uccup->supsmr); 856 857 /* byte size */ 858 upsmr &= UCC_UART_UPSMR_CL_MASK; 859 supsmr &= UCC_UART_SUPSMR_CL_MASK; 860 861 switch (termios->c_cflag & CSIZE) { 862 case CS5: 863 upsmr |= UCC_UART_UPSMR_CL_5; 864 supsmr |= UCC_UART_SUPSMR_CL_5; 865 break; 866 case CS6: 867 upsmr |= UCC_UART_UPSMR_CL_6; 868 supsmr |= UCC_UART_SUPSMR_CL_6; 869 break; 870 case CS7: 871 upsmr |= UCC_UART_UPSMR_CL_7; 872 supsmr |= UCC_UART_SUPSMR_CL_7; 873 break; 874 default: /* case CS8 */ 875 upsmr |= UCC_UART_UPSMR_CL_8; 876 supsmr |= UCC_UART_SUPSMR_CL_8; 877 break; 878 } 879 880 /* If CSTOPB is set, we want two stop bits */ 881 if (termios->c_cflag & CSTOPB) { 882 upsmr |= UCC_UART_UPSMR_SL; 883 supsmr |= UCC_UART_SUPSMR_SL; 884 } 885 886 if (termios->c_cflag & PARENB) { 887 upsmr |= UCC_UART_UPSMR_PEN; 888 supsmr |= UCC_UART_SUPSMR_PEN; 889 890 if (!(termios->c_cflag & PARODD)) { 891 upsmr &= ~(UCC_UART_UPSMR_RPM_MASK | 892 UCC_UART_UPSMR_TPM_MASK); 893 upsmr |= UCC_UART_UPSMR_RPM_EVEN | 894 UCC_UART_UPSMR_TPM_EVEN; 895 supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK | 896 UCC_UART_SUPSMR_TPM_MASK); 897 supsmr |= UCC_UART_SUPSMR_RPM_EVEN | 898 UCC_UART_SUPSMR_TPM_EVEN; 899 } 900 } 901 902 /* 903 * Set up parity check flag 904 */ 905 port->read_status_mask = BD_SC_EMPTY | BD_SC_OV; 906 if (termios->c_iflag & INPCK) 907 port->read_status_mask |= BD_SC_FR | BD_SC_PR; 908 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 909 port->read_status_mask |= BD_SC_BR; 910 911 /* 912 * Characters to ignore 913 */ 914 port->ignore_status_mask = 0; 915 if (termios->c_iflag & IGNPAR) 916 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; 917 if (termios->c_iflag & IGNBRK) { 918 port->ignore_status_mask |= BD_SC_BR; 919 /* 920 * If we're ignore parity and break indicators, ignore 921 * overruns too. (For real raw support). 922 */ 923 if (termios->c_iflag & IGNPAR) 924 port->ignore_status_mask |= BD_SC_OV; 925 } 926 /* 927 * !!! ignore all characters if CREAD is not set 928 */ 929 if ((termios->c_cflag & CREAD) == 0) 930 port->read_status_mask &= ~BD_SC_EMPTY; 931 932 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 933 934 /* Do we really need a spinlock here? */ 935 spin_lock_irqsave(&port->lock, flags); 936 937 /* Update the per-port timeout. */ 938 uart_update_timeout(port, termios->c_cflag, baud); 939 940 iowrite16be(upsmr, &uccp->upsmr); 941 if (soft_uart) { 942 iowrite16be(supsmr, &uccup->supsmr); 943 iowrite8(tty_get_frame_size(termios->c_cflag), &uccup->rx_length); 944 945 /* Soft-UART requires a 1X multiplier for TX */ 946 qe_setbrg(qe_port->us_info.rx_clock, baud, 16); 947 qe_setbrg(qe_port->us_info.tx_clock, baud, 1); 948 } else { 949 qe_setbrg(qe_port->us_info.rx_clock, baud, 16); 950 qe_setbrg(qe_port->us_info.tx_clock, baud, 16); 951 } 952 953 spin_unlock_irqrestore(&port->lock, flags); 954 } 955 956 /* 957 * Return a pointer to a string that describes what kind of port this is. 958 */ 959 static const char *qe_uart_type(struct uart_port *port) 960 { 961 return "QE"; 962 } 963 964 /* 965 * Allocate any memory and I/O resources required by the port. 966 */ 967 static int qe_uart_request_port(struct uart_port *port) 968 { 969 int ret; 970 struct uart_qe_port *qe_port = 971 container_of(port, struct uart_qe_port, port); 972 struct ucc_slow_info *us_info = &qe_port->us_info; 973 struct ucc_slow_private *uccs; 974 unsigned int rx_size, tx_size; 975 void *bd_virt; 976 dma_addr_t bd_dma_addr = 0; 977 978 ret = ucc_slow_init(us_info, &uccs); 979 if (ret) { 980 dev_err(port->dev, "could not initialize UCC%u\n", 981 qe_port->ucc_num); 982 return ret; 983 } 984 985 qe_port->us_private = uccs; 986 qe_port->uccp = uccs->us_regs; 987 qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram; 988 qe_port->rx_bd_base = uccs->rx_bd; 989 qe_port->tx_bd_base = uccs->tx_bd; 990 991 /* 992 * Allocate the transmit and receive data buffers. 993 */ 994 995 rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); 996 tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize); 997 998 bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr, 999 GFP_KERNEL); 1000 if (!bd_virt) { 1001 dev_err(port->dev, "could not allocate buffer descriptors\n"); 1002 return -ENOMEM; 1003 } 1004 1005 qe_port->bd_virt = bd_virt; 1006 qe_port->bd_dma_addr = bd_dma_addr; 1007 qe_port->bd_size = rx_size + tx_size; 1008 1009 qe_port->rx_buf = bd_virt; 1010 qe_port->tx_buf = qe_port->rx_buf + rx_size; 1011 1012 return 0; 1013 } 1014 1015 /* 1016 * Configure the port. 1017 * 1018 * We say we're a CPM-type port because that's mostly true. Once the device 1019 * is configured, this driver operates almost identically to the CPM serial 1020 * driver. 1021 */ 1022 static void qe_uart_config_port(struct uart_port *port, int flags) 1023 { 1024 if (flags & UART_CONFIG_TYPE) { 1025 port->type = PORT_CPM; 1026 qe_uart_request_port(port); 1027 } 1028 } 1029 1030 /* 1031 * Release any memory and I/O resources that were allocated in 1032 * qe_uart_request_port(). 1033 */ 1034 static void qe_uart_release_port(struct uart_port *port) 1035 { 1036 struct uart_qe_port *qe_port = 1037 container_of(port, struct uart_qe_port, port); 1038 struct ucc_slow_private *uccs = qe_port->us_private; 1039 1040 dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt, 1041 qe_port->bd_dma_addr); 1042 1043 ucc_slow_free(uccs); 1044 } 1045 1046 /* 1047 * Verify that the data in serial_struct is suitable for this device. 1048 */ 1049 static int qe_uart_verify_port(struct uart_port *port, 1050 struct serial_struct *ser) 1051 { 1052 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) 1053 return -EINVAL; 1054 1055 if (ser->irq < 0 || ser->irq >= nr_irqs) 1056 return -EINVAL; 1057 1058 if (ser->baud_base < 9600) 1059 return -EINVAL; 1060 1061 return 0; 1062 } 1063 /* UART operations 1064 * 1065 * Details on these functions can be found in Documentation/driver-api/serial/driver.rst 1066 */ 1067 static const struct uart_ops qe_uart_pops = { 1068 .tx_empty = qe_uart_tx_empty, 1069 .set_mctrl = qe_uart_set_mctrl, 1070 .get_mctrl = qe_uart_get_mctrl, 1071 .stop_tx = qe_uart_stop_tx, 1072 .start_tx = qe_uart_start_tx, 1073 .stop_rx = qe_uart_stop_rx, 1074 .break_ctl = qe_uart_break_ctl, 1075 .startup = qe_uart_startup, 1076 .shutdown = qe_uart_shutdown, 1077 .set_termios = qe_uart_set_termios, 1078 .type = qe_uart_type, 1079 .release_port = qe_uart_release_port, 1080 .request_port = qe_uart_request_port, 1081 .config_port = qe_uart_config_port, 1082 .verify_port = qe_uart_verify_port, 1083 }; 1084 1085 1086 #ifdef CONFIG_PPC32 1087 /* 1088 * Obtain the SOC model number and revision level 1089 * 1090 * This function parses the device tree to obtain the SOC model. It then 1091 * reads the SVR register to the revision. 1092 * 1093 * The device tree stores the SOC model two different ways. 1094 * 1095 * The new way is: 1096 * 1097 * cpu@0 { 1098 * compatible = "PowerPC,8323"; 1099 * device_type = "cpu"; 1100 * ... 1101 * 1102 * 1103 * The old way is: 1104 * PowerPC,8323@0 { 1105 * device_type = "cpu"; 1106 * ... 1107 * 1108 * This code first checks the new way, and then the old way. 1109 */ 1110 static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l) 1111 { 1112 struct device_node *np; 1113 const char *soc_string; 1114 unsigned int svr; 1115 unsigned int soc; 1116 1117 /* Find the CPU node */ 1118 np = of_find_node_by_type(NULL, "cpu"); 1119 if (!np) 1120 return 0; 1121 /* Find the compatible property */ 1122 soc_string = of_get_property(np, "compatible", NULL); 1123 if (!soc_string) 1124 /* No compatible property, so try the name. */ 1125 soc_string = np->name; 1126 1127 of_node_put(np); 1128 1129 /* Extract the SOC number from the "PowerPC," string */ 1130 if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc) 1131 return 0; 1132 1133 /* Get the revision from the SVR */ 1134 svr = mfspr(SPRN_SVR); 1135 *rev_h = (svr >> 4) & 0xf; 1136 *rev_l = svr & 0xf; 1137 1138 return soc; 1139 } 1140 1141 /* 1142 * requst_firmware_nowait() callback function 1143 * 1144 * This function is called by the kernel when a firmware is made available, 1145 * or if it times out waiting for the firmware. 1146 */ 1147 static void uart_firmware_cont(const struct firmware *fw, void *context) 1148 { 1149 struct qe_firmware *firmware; 1150 struct device *dev = context; 1151 int ret; 1152 1153 if (!fw) { 1154 dev_err(dev, "firmware not found\n"); 1155 return; 1156 } 1157 1158 firmware = (struct qe_firmware *) fw->data; 1159 1160 if (firmware->header.length != fw->size) { 1161 dev_err(dev, "invalid firmware\n"); 1162 goto out; 1163 } 1164 1165 ret = qe_upload_firmware(firmware); 1166 if (ret) { 1167 dev_err(dev, "could not load firmware\n"); 1168 goto out; 1169 } 1170 1171 firmware_loaded = 1; 1172 out: 1173 release_firmware(fw); 1174 } 1175 1176 static int soft_uart_init(struct platform_device *ofdev) 1177 { 1178 struct device_node *np = ofdev->dev.of_node; 1179 struct qe_firmware_info *qe_fw_info; 1180 int ret; 1181 1182 if (of_find_property(np, "soft-uart", NULL)) { 1183 dev_dbg(&ofdev->dev, "using Soft-UART mode\n"); 1184 soft_uart = 1; 1185 } else { 1186 return 0; 1187 } 1188 1189 qe_fw_info = qe_get_firmware_info(); 1190 1191 /* Check if the firmware has been uploaded. */ 1192 if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) { 1193 firmware_loaded = 1; 1194 } else { 1195 char filename[32]; 1196 unsigned int soc; 1197 unsigned int rev_h; 1198 unsigned int rev_l; 1199 1200 soc = soc_info(&rev_h, &rev_l); 1201 if (!soc) { 1202 dev_err(&ofdev->dev, "unknown CPU model\n"); 1203 return -ENXIO; 1204 } 1205 sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin", 1206 soc, rev_h, rev_l); 1207 1208 dev_info(&ofdev->dev, "waiting for firmware %s\n", 1209 filename); 1210 1211 /* 1212 * We call request_firmware_nowait instead of 1213 * request_firmware so that the driver can load and 1214 * initialize the ports without holding up the rest of 1215 * the kernel. If hotplug support is enabled in the 1216 * kernel, then we use it. 1217 */ 1218 ret = request_firmware_nowait(THIS_MODULE, 1219 FW_ACTION_UEVENT, filename, &ofdev->dev, 1220 GFP_KERNEL, &ofdev->dev, uart_firmware_cont); 1221 if (ret) { 1222 dev_err(&ofdev->dev, 1223 "could not load firmware %s\n", 1224 filename); 1225 return ret; 1226 } 1227 } 1228 return 0; 1229 } 1230 1231 #else /* !CONFIG_PPC32 */ 1232 1233 static int soft_uart_init(struct platform_device *ofdev) 1234 { 1235 return 0; 1236 } 1237 1238 #endif 1239 1240 1241 static int ucc_uart_probe(struct platform_device *ofdev) 1242 { 1243 struct device_node *np = ofdev->dev.of_node; 1244 const char *sprop; /* String OF properties */ 1245 struct uart_qe_port *qe_port = NULL; 1246 struct resource res; 1247 u32 val; 1248 int ret; 1249 1250 /* 1251 * Determine if we need Soft-UART mode 1252 */ 1253 ret = soft_uart_init(ofdev); 1254 if (ret) 1255 return ret; 1256 1257 qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL); 1258 if (!qe_port) { 1259 dev_err(&ofdev->dev, "can't allocate QE port structure\n"); 1260 return -ENOMEM; 1261 } 1262 1263 /* Search for IRQ and mapbase */ 1264 ret = of_address_to_resource(np, 0, &res); 1265 if (ret) { 1266 dev_err(&ofdev->dev, "missing 'reg' property in device tree\n"); 1267 goto out_free; 1268 } 1269 if (!res.start) { 1270 dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n"); 1271 ret = -EINVAL; 1272 goto out_free; 1273 } 1274 qe_port->port.mapbase = res.start; 1275 1276 /* Get the UCC number (device ID) */ 1277 /* UCCs are numbered 1-7 */ 1278 if (of_property_read_u32(np, "cell-index", &val)) { 1279 if (of_property_read_u32(np, "device-id", &val)) { 1280 dev_err(&ofdev->dev, "UCC is unspecified in device tree\n"); 1281 ret = -EINVAL; 1282 goto out_free; 1283 } 1284 } 1285 1286 if (val < 1 || val > UCC_MAX_NUM) { 1287 dev_err(&ofdev->dev, "no support for UCC%u\n", val); 1288 ret = -ENODEV; 1289 goto out_free; 1290 } 1291 qe_port->ucc_num = val - 1; 1292 1293 /* 1294 * In the future, we should not require the BRG to be specified in the 1295 * device tree. If no clock-source is specified, then just pick a BRG 1296 * to use. This requires a new QE library function that manages BRG 1297 * assignments. 1298 */ 1299 1300 sprop = of_get_property(np, "rx-clock-name", NULL); 1301 if (!sprop) { 1302 dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n"); 1303 ret = -ENODEV; 1304 goto out_free; 1305 } 1306 1307 qe_port->us_info.rx_clock = qe_clock_source(sprop); 1308 if ((qe_port->us_info.rx_clock < QE_BRG1) || 1309 (qe_port->us_info.rx_clock > QE_BRG16)) { 1310 dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n"); 1311 ret = -ENODEV; 1312 goto out_free; 1313 } 1314 1315 #ifdef LOOPBACK 1316 /* In internal loopback mode, TX and RX must use the same clock */ 1317 qe_port->us_info.tx_clock = qe_port->us_info.rx_clock; 1318 #else 1319 sprop = of_get_property(np, "tx-clock-name", NULL); 1320 if (!sprop) { 1321 dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n"); 1322 ret = -ENODEV; 1323 goto out_free; 1324 } 1325 qe_port->us_info.tx_clock = qe_clock_source(sprop); 1326 #endif 1327 if ((qe_port->us_info.tx_clock < QE_BRG1) || 1328 (qe_port->us_info.tx_clock > QE_BRG16)) { 1329 dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n"); 1330 ret = -ENODEV; 1331 goto out_free; 1332 } 1333 1334 /* Get the port number, numbered 0-3 */ 1335 if (of_property_read_u32(np, "port-number", &val)) { 1336 dev_err(&ofdev->dev, "missing port-number in device tree\n"); 1337 ret = -EINVAL; 1338 goto out_free; 1339 } 1340 qe_port->port.line = val; 1341 if (qe_port->port.line >= UCC_MAX_UART) { 1342 dev_err(&ofdev->dev, "port-number must be 0-%u\n", 1343 UCC_MAX_UART - 1); 1344 ret = -EINVAL; 1345 goto out_free; 1346 } 1347 1348 qe_port->port.irq = irq_of_parse_and_map(np, 0); 1349 if (qe_port->port.irq == 0) { 1350 dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n", 1351 qe_port->ucc_num + 1); 1352 ret = -EINVAL; 1353 goto out_free; 1354 } 1355 1356 /* 1357 * Newer device trees have an "fsl,qe" compatible property for the QE 1358 * node, but we still need to support older device trees. 1359 */ 1360 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 1361 if (!np) { 1362 np = of_find_node_by_type(NULL, "qe"); 1363 if (!np) { 1364 dev_err(&ofdev->dev, "could not find 'qe' node\n"); 1365 ret = -EINVAL; 1366 goto out_free; 1367 } 1368 } 1369 1370 if (of_property_read_u32(np, "brg-frequency", &val)) { 1371 dev_err(&ofdev->dev, 1372 "missing brg-frequency in device tree\n"); 1373 ret = -EINVAL; 1374 goto out_np; 1375 } 1376 1377 if (val) 1378 qe_port->port.uartclk = val; 1379 else { 1380 if (!IS_ENABLED(CONFIG_PPC32)) { 1381 dev_err(&ofdev->dev, 1382 "invalid brg-frequency in device tree\n"); 1383 ret = -EINVAL; 1384 goto out_np; 1385 } 1386 1387 /* 1388 * Older versions of U-Boot do not initialize the brg-frequency 1389 * property, so in this case we assume the BRG frequency is 1390 * half the QE bus frequency. 1391 */ 1392 if (of_property_read_u32(np, "bus-frequency", &val)) { 1393 dev_err(&ofdev->dev, 1394 "missing QE bus-frequency in device tree\n"); 1395 ret = -EINVAL; 1396 goto out_np; 1397 } 1398 if (val) 1399 qe_port->port.uartclk = val / 2; 1400 else { 1401 dev_err(&ofdev->dev, 1402 "invalid QE bus-frequency in device tree\n"); 1403 ret = -EINVAL; 1404 goto out_np; 1405 } 1406 } 1407 1408 spin_lock_init(&qe_port->port.lock); 1409 qe_port->np = np; 1410 qe_port->port.dev = &ofdev->dev; 1411 qe_port->port.ops = &qe_uart_pops; 1412 qe_port->port.iotype = UPIO_MEM; 1413 1414 qe_port->tx_nrfifos = TX_NUM_FIFO; 1415 qe_port->tx_fifosize = TX_BUF_SIZE; 1416 qe_port->rx_nrfifos = RX_NUM_FIFO; 1417 qe_port->rx_fifosize = RX_BUF_SIZE; 1418 1419 qe_port->wait_closing = UCC_WAIT_CLOSING; 1420 qe_port->port.fifosize = 512; 1421 qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 1422 1423 qe_port->us_info.ucc_num = qe_port->ucc_num; 1424 qe_port->us_info.regs = (phys_addr_t) res.start; 1425 qe_port->us_info.irq = qe_port->port.irq; 1426 1427 qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos; 1428 qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos; 1429 1430 /* Make sure ucc_slow_init() initializes both TX and RX */ 1431 qe_port->us_info.init_tx = 1; 1432 qe_port->us_info.init_rx = 1; 1433 1434 /* Add the port to the uart sub-system. This will cause 1435 * qe_uart_config_port() to be called, so the us_info structure must 1436 * be initialized. 1437 */ 1438 ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port); 1439 if (ret) { 1440 dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n", 1441 qe_port->port.line); 1442 goto out_np; 1443 } 1444 1445 platform_set_drvdata(ofdev, qe_port); 1446 1447 dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n", 1448 qe_port->ucc_num + 1, qe_port->port.line); 1449 1450 /* Display the mknod command for this device */ 1451 dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n", 1452 qe_port->port.line, SERIAL_QE_MAJOR, 1453 SERIAL_QE_MINOR + qe_port->port.line); 1454 1455 return 0; 1456 out_np: 1457 of_node_put(np); 1458 out_free: 1459 kfree(qe_port); 1460 return ret; 1461 } 1462 1463 static int ucc_uart_remove(struct platform_device *ofdev) 1464 { 1465 struct uart_qe_port *qe_port = platform_get_drvdata(ofdev); 1466 1467 dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line); 1468 1469 uart_remove_one_port(&ucc_uart_driver, &qe_port->port); 1470 1471 of_node_put(qe_port->np); 1472 1473 kfree(qe_port); 1474 1475 return 0; 1476 } 1477 1478 static const struct of_device_id ucc_uart_match[] = { 1479 { 1480 .type = "serial", 1481 .compatible = "ucc_uart", 1482 }, 1483 { 1484 .compatible = "fsl,t1040-ucc-uart", 1485 }, 1486 {}, 1487 }; 1488 MODULE_DEVICE_TABLE(of, ucc_uart_match); 1489 1490 static struct platform_driver ucc_uart_of_driver = { 1491 .driver = { 1492 .name = "ucc_uart", 1493 .of_match_table = ucc_uart_match, 1494 }, 1495 .probe = ucc_uart_probe, 1496 .remove = ucc_uart_remove, 1497 }; 1498 1499 static int __init ucc_uart_init(void) 1500 { 1501 int ret; 1502 1503 printk(KERN_INFO "Freescale QUICC Engine UART device driver\n"); 1504 #ifdef LOOPBACK 1505 printk(KERN_INFO "ucc-uart: Using loopback mode\n"); 1506 #endif 1507 1508 ret = uart_register_driver(&ucc_uart_driver); 1509 if (ret) { 1510 printk(KERN_ERR "ucc-uart: could not register UART driver\n"); 1511 return ret; 1512 } 1513 1514 ret = platform_driver_register(&ucc_uart_of_driver); 1515 if (ret) { 1516 printk(KERN_ERR 1517 "ucc-uart: could not register platform driver\n"); 1518 uart_unregister_driver(&ucc_uart_driver); 1519 } 1520 1521 return ret; 1522 } 1523 1524 static void __exit ucc_uart_exit(void) 1525 { 1526 printk(KERN_INFO 1527 "Freescale QUICC Engine UART device driver unloading\n"); 1528 1529 platform_driver_unregister(&ucc_uart_of_driver); 1530 uart_unregister_driver(&ucc_uart_driver); 1531 } 1532 1533 module_init(ucc_uart_init); 1534 module_exit(ucc_uart_exit); 1535 1536 MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART"); 1537 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1538 MODULE_LICENSE("GPL v2"); 1539 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR); 1540 1541