1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * uartlite.c: Serial driver for Xilinx uartlite serial controller 4 * 5 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk> 6 * Copyright (C) 2007 Secret Lab Technologies Ltd. 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/console.h> 12 #include <linux/serial.h> 13 #include <linux/serial_core.h> 14 #include <linux/tty.h> 15 #include <linux/tty_flip.h> 16 #include <linux/delay.h> 17 #include <linux/interrupt.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_platform.h> 24 #include <linux/clk.h> 25 26 #define ULITE_NAME "ttyUL" 27 #define ULITE_MAJOR 204 28 #define ULITE_MINOR 187 29 #define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS 30 31 /* --------------------------------------------------------------------- 32 * Register definitions 33 * 34 * For register details see datasheet: 35 * http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf 36 */ 37 38 #define ULITE_RX 0x00 39 #define ULITE_TX 0x04 40 #define ULITE_STATUS 0x08 41 #define ULITE_CONTROL 0x0c 42 43 #define ULITE_REGION 16 44 45 #define ULITE_STATUS_RXVALID 0x01 46 #define ULITE_STATUS_RXFULL 0x02 47 #define ULITE_STATUS_TXEMPTY 0x04 48 #define ULITE_STATUS_TXFULL 0x08 49 #define ULITE_STATUS_IE 0x10 50 #define ULITE_STATUS_OVERRUN 0x20 51 #define ULITE_STATUS_FRAME 0x40 52 #define ULITE_STATUS_PARITY 0x80 53 54 #define ULITE_CONTROL_RST_TX 0x01 55 #define ULITE_CONTROL_RST_RX 0x02 56 #define ULITE_CONTROL_IE 0x10 57 58 struct uartlite_data { 59 const struct uartlite_reg_ops *reg_ops; 60 struct clk *clk; 61 }; 62 63 struct uartlite_reg_ops { 64 u32 (*in)(void __iomem *addr); 65 void (*out)(u32 val, void __iomem *addr); 66 }; 67 68 static u32 uartlite_inbe32(void __iomem *addr) 69 { 70 return ioread32be(addr); 71 } 72 73 static void uartlite_outbe32(u32 val, void __iomem *addr) 74 { 75 iowrite32be(val, addr); 76 } 77 78 static const struct uartlite_reg_ops uartlite_be = { 79 .in = uartlite_inbe32, 80 .out = uartlite_outbe32, 81 }; 82 83 static u32 uartlite_inle32(void __iomem *addr) 84 { 85 return ioread32(addr); 86 } 87 88 static void uartlite_outle32(u32 val, void __iomem *addr) 89 { 90 iowrite32(val, addr); 91 } 92 93 static const struct uartlite_reg_ops uartlite_le = { 94 .in = uartlite_inle32, 95 .out = uartlite_outle32, 96 }; 97 98 static inline u32 uart_in32(u32 offset, struct uart_port *port) 99 { 100 struct uartlite_data *pdata = port->private_data; 101 102 return pdata->reg_ops->in(port->membase + offset); 103 } 104 105 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port) 106 { 107 struct uartlite_data *pdata = port->private_data; 108 109 pdata->reg_ops->out(val, port->membase + offset); 110 } 111 112 static struct uart_port ulite_ports[ULITE_NR_UARTS]; 113 114 /* --------------------------------------------------------------------- 115 * Core UART driver operations 116 */ 117 118 static int ulite_receive(struct uart_port *port, int stat) 119 { 120 struct tty_port *tport = &port->state->port; 121 unsigned char ch = 0; 122 char flag = TTY_NORMAL; 123 124 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 125 | ULITE_STATUS_FRAME)) == 0) 126 return 0; 127 128 /* stats */ 129 if (stat & ULITE_STATUS_RXVALID) { 130 port->icount.rx++; 131 ch = uart_in32(ULITE_RX, port); 132 133 if (stat & ULITE_STATUS_PARITY) 134 port->icount.parity++; 135 } 136 137 if (stat & ULITE_STATUS_OVERRUN) 138 port->icount.overrun++; 139 140 if (stat & ULITE_STATUS_FRAME) 141 port->icount.frame++; 142 143 144 /* drop byte with parity error if IGNPAR specificed */ 145 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) 146 stat &= ~ULITE_STATUS_RXVALID; 147 148 stat &= port->read_status_mask; 149 150 if (stat & ULITE_STATUS_PARITY) 151 flag = TTY_PARITY; 152 153 154 stat &= ~port->ignore_status_mask; 155 156 if (stat & ULITE_STATUS_RXVALID) 157 tty_insert_flip_char(tport, ch, flag); 158 159 if (stat & ULITE_STATUS_FRAME) 160 tty_insert_flip_char(tport, 0, TTY_FRAME); 161 162 if (stat & ULITE_STATUS_OVERRUN) 163 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 164 165 return 1; 166 } 167 168 static int ulite_transmit(struct uart_port *port, int stat) 169 { 170 struct circ_buf *xmit = &port->state->xmit; 171 172 if (stat & ULITE_STATUS_TXFULL) 173 return 0; 174 175 if (port->x_char) { 176 uart_out32(port->x_char, ULITE_TX, port); 177 port->x_char = 0; 178 port->icount.tx++; 179 return 1; 180 } 181 182 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 183 return 0; 184 185 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port); 186 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1); 187 port->icount.tx++; 188 189 /* wake up */ 190 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 191 uart_write_wakeup(port); 192 193 return 1; 194 } 195 196 static irqreturn_t ulite_isr(int irq, void *dev_id) 197 { 198 struct uart_port *port = dev_id; 199 int stat, busy, n = 0; 200 unsigned long flags; 201 202 do { 203 spin_lock_irqsave(&port->lock, flags); 204 stat = uart_in32(ULITE_STATUS, port); 205 busy = ulite_receive(port, stat); 206 busy |= ulite_transmit(port, stat); 207 spin_unlock_irqrestore(&port->lock, flags); 208 n++; 209 } while (busy); 210 211 /* work done? */ 212 if (n > 1) { 213 tty_flip_buffer_push(&port->state->port); 214 return IRQ_HANDLED; 215 } else { 216 return IRQ_NONE; 217 } 218 } 219 220 static unsigned int ulite_tx_empty(struct uart_port *port) 221 { 222 unsigned long flags; 223 unsigned int ret; 224 225 spin_lock_irqsave(&port->lock, flags); 226 ret = uart_in32(ULITE_STATUS, port); 227 spin_unlock_irqrestore(&port->lock, flags); 228 229 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0; 230 } 231 232 static unsigned int ulite_get_mctrl(struct uart_port *port) 233 { 234 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 235 } 236 237 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl) 238 { 239 /* N/A */ 240 } 241 242 static void ulite_stop_tx(struct uart_port *port) 243 { 244 /* N/A */ 245 } 246 247 static void ulite_start_tx(struct uart_port *port) 248 { 249 ulite_transmit(port, uart_in32(ULITE_STATUS, port)); 250 } 251 252 static void ulite_stop_rx(struct uart_port *port) 253 { 254 /* don't forward any more data (like !CREAD) */ 255 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 256 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 257 } 258 259 static void ulite_break_ctl(struct uart_port *port, int ctl) 260 { 261 /* N/A */ 262 } 263 264 static int ulite_startup(struct uart_port *port) 265 { 266 struct uartlite_data *pdata = port->private_data; 267 int ret; 268 269 ret = clk_enable(pdata->clk); 270 if (ret) { 271 dev_err(port->dev, "Failed to enable clock\n"); 272 return ret; 273 } 274 275 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING, 276 "uartlite", port); 277 if (ret) 278 return ret; 279 280 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX, 281 ULITE_CONTROL, port); 282 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 283 284 return 0; 285 } 286 287 static void ulite_shutdown(struct uart_port *port) 288 { 289 struct uartlite_data *pdata = port->private_data; 290 291 uart_out32(0, ULITE_CONTROL, port); 292 uart_in32(ULITE_CONTROL, port); /* dummy */ 293 free_irq(port->irq, port); 294 clk_disable(pdata->clk); 295 } 296 297 static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, 298 struct ktermios *old) 299 { 300 unsigned long flags; 301 unsigned int baud; 302 303 spin_lock_irqsave(&port->lock, flags); 304 305 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 306 | ULITE_STATUS_TXFULL; 307 308 if (termios->c_iflag & INPCK) 309 port->read_status_mask |= 310 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME; 311 312 port->ignore_status_mask = 0; 313 if (termios->c_iflag & IGNPAR) 314 port->ignore_status_mask |= ULITE_STATUS_PARITY 315 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 316 317 /* ignore all characters if CREAD is not set */ 318 if ((termios->c_cflag & CREAD) == 0) 319 port->ignore_status_mask |= 320 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 321 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 322 323 /* update timeout */ 324 baud = uart_get_baud_rate(port, termios, old, 0, 460800); 325 uart_update_timeout(port, termios->c_cflag, baud); 326 327 spin_unlock_irqrestore(&port->lock, flags); 328 } 329 330 static const char *ulite_type(struct uart_port *port) 331 { 332 return port->type == PORT_UARTLITE ? "uartlite" : NULL; 333 } 334 335 static void ulite_release_port(struct uart_port *port) 336 { 337 release_mem_region(port->mapbase, ULITE_REGION); 338 iounmap(port->membase); 339 port->membase = NULL; 340 } 341 342 static int ulite_request_port(struct uart_port *port) 343 { 344 struct uartlite_data *pdata = port->private_data; 345 int ret; 346 347 pr_debug("ulite console: port=%p; port->mapbase=%llx\n", 348 port, (unsigned long long) port->mapbase); 349 350 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { 351 dev_err(port->dev, "Memory region busy\n"); 352 return -EBUSY; 353 } 354 355 port->membase = ioremap(port->mapbase, ULITE_REGION); 356 if (!port->membase) { 357 dev_err(port->dev, "Unable to map registers\n"); 358 release_mem_region(port->mapbase, ULITE_REGION); 359 return -EBUSY; 360 } 361 362 pdata->reg_ops = &uartlite_be; 363 ret = uart_in32(ULITE_CONTROL, port); 364 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); 365 ret = uart_in32(ULITE_STATUS, port); 366 /* Endianess detection */ 367 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY) 368 pdata->reg_ops = &uartlite_le; 369 370 return 0; 371 } 372 373 static void ulite_config_port(struct uart_port *port, int flags) 374 { 375 if (!ulite_request_port(port)) 376 port->type = PORT_UARTLITE; 377 } 378 379 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser) 380 { 381 /* we don't want the core code to modify any port params */ 382 return -EINVAL; 383 } 384 385 static void ulite_pm(struct uart_port *port, unsigned int state, 386 unsigned int oldstate) 387 { 388 struct uartlite_data *pdata = port->private_data; 389 390 if (!state) 391 clk_enable(pdata->clk); 392 else 393 clk_disable(pdata->clk); 394 } 395 396 #ifdef CONFIG_CONSOLE_POLL 397 static int ulite_get_poll_char(struct uart_port *port) 398 { 399 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID)) 400 return NO_POLL_CHAR; 401 402 return uart_in32(ULITE_RX, port); 403 } 404 405 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch) 406 { 407 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL) 408 cpu_relax(); 409 410 /* write char to device */ 411 uart_out32(ch, ULITE_TX, port); 412 } 413 #endif 414 415 static const struct uart_ops ulite_ops = { 416 .tx_empty = ulite_tx_empty, 417 .set_mctrl = ulite_set_mctrl, 418 .get_mctrl = ulite_get_mctrl, 419 .stop_tx = ulite_stop_tx, 420 .start_tx = ulite_start_tx, 421 .stop_rx = ulite_stop_rx, 422 .break_ctl = ulite_break_ctl, 423 .startup = ulite_startup, 424 .shutdown = ulite_shutdown, 425 .set_termios = ulite_set_termios, 426 .type = ulite_type, 427 .release_port = ulite_release_port, 428 .request_port = ulite_request_port, 429 .config_port = ulite_config_port, 430 .verify_port = ulite_verify_port, 431 .pm = ulite_pm, 432 #ifdef CONFIG_CONSOLE_POLL 433 .poll_get_char = ulite_get_poll_char, 434 .poll_put_char = ulite_put_poll_char, 435 #endif 436 }; 437 438 /* --------------------------------------------------------------------- 439 * Console driver operations 440 */ 441 442 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 443 static void ulite_console_wait_tx(struct uart_port *port) 444 { 445 u8 val; 446 unsigned long timeout; 447 448 /* 449 * Spin waiting for TX fifo to have space available. 450 * When using the Microblaze Debug Module this can take up to 1s 451 */ 452 timeout = jiffies + msecs_to_jiffies(1000); 453 while (1) { 454 val = uart_in32(ULITE_STATUS, port); 455 if ((val & ULITE_STATUS_TXFULL) == 0) 456 break; 457 if (time_after(jiffies, timeout)) { 458 dev_warn(port->dev, 459 "timeout waiting for TX buffer empty\n"); 460 break; 461 } 462 cpu_relax(); 463 } 464 } 465 466 static void ulite_console_putchar(struct uart_port *port, int ch) 467 { 468 ulite_console_wait_tx(port); 469 uart_out32(ch, ULITE_TX, port); 470 } 471 472 static void ulite_console_write(struct console *co, const char *s, 473 unsigned int count) 474 { 475 struct uart_port *port = &ulite_ports[co->index]; 476 unsigned long flags; 477 unsigned int ier; 478 int locked = 1; 479 480 if (oops_in_progress) { 481 locked = spin_trylock_irqsave(&port->lock, flags); 482 } else 483 spin_lock_irqsave(&port->lock, flags); 484 485 /* save and disable interrupt */ 486 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE; 487 uart_out32(0, ULITE_CONTROL, port); 488 489 uart_console_write(port, s, count, ulite_console_putchar); 490 491 ulite_console_wait_tx(port); 492 493 /* restore interrupt state */ 494 if (ier) 495 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 496 497 if (locked) 498 spin_unlock_irqrestore(&port->lock, flags); 499 } 500 501 static int ulite_console_setup(struct console *co, char *options) 502 { 503 struct uart_port *port; 504 int baud = 9600; 505 int bits = 8; 506 int parity = 'n'; 507 int flow = 'n'; 508 509 if (co->index < 0 || co->index >= ULITE_NR_UARTS) 510 return -EINVAL; 511 512 port = &ulite_ports[co->index]; 513 514 /* Has the device been initialized yet? */ 515 if (!port->mapbase) { 516 pr_debug("console on ttyUL%i not present\n", co->index); 517 return -ENODEV; 518 } 519 520 /* not initialized yet? */ 521 if (!port->membase) { 522 if (ulite_request_port(port)) 523 return -ENODEV; 524 } 525 526 if (options) 527 uart_parse_options(options, &baud, &parity, &bits, &flow); 528 529 return uart_set_options(port, co, baud, parity, bits, flow); 530 } 531 532 static struct uart_driver ulite_uart_driver; 533 534 static struct console ulite_console = { 535 .name = ULITE_NAME, 536 .write = ulite_console_write, 537 .device = uart_console_device, 538 .setup = ulite_console_setup, 539 .flags = CON_PRINTBUFFER, 540 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */ 541 .data = &ulite_uart_driver, 542 }; 543 544 static int __init ulite_console_init(void) 545 { 546 register_console(&ulite_console); 547 return 0; 548 } 549 550 console_initcall(ulite_console_init); 551 552 static void early_uartlite_putc(struct uart_port *port, int c) 553 { 554 /* 555 * Limit how many times we'll spin waiting for TX FIFO status. 556 * This will prevent lockups if the base address is incorrectly 557 * set, or any other issue on the UARTLITE. 558 * This limit is pretty arbitrary, unless we are at about 10 baud 559 * we'll never timeout on a working UART. 560 */ 561 562 unsigned retries = 1000000; 563 /* read status bit - 0x8 offset */ 564 while (--retries && (readl(port->membase + 8) & (1 << 3))) 565 ; 566 567 /* Only attempt the iowrite if we didn't timeout */ 568 /* write to TX_FIFO - 0x4 offset */ 569 if (retries) 570 writel(c & 0xff, port->membase + 4); 571 } 572 573 static void early_uartlite_write(struct console *console, 574 const char *s, unsigned n) 575 { 576 struct earlycon_device *device = console->data; 577 uart_console_write(&device->port, s, n, early_uartlite_putc); 578 } 579 580 static int __init early_uartlite_setup(struct earlycon_device *device, 581 const char *options) 582 { 583 if (!device->port.membase) 584 return -ENODEV; 585 586 device->con->write = early_uartlite_write; 587 return 0; 588 } 589 EARLYCON_DECLARE(uartlite, early_uartlite_setup); 590 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup); 591 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup); 592 593 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */ 594 595 static struct uart_driver ulite_uart_driver = { 596 .owner = THIS_MODULE, 597 .driver_name = "uartlite", 598 .dev_name = ULITE_NAME, 599 .major = ULITE_MAJOR, 600 .minor = ULITE_MINOR, 601 .nr = ULITE_NR_UARTS, 602 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 603 .cons = &ulite_console, 604 #endif 605 }; 606 607 /* --------------------------------------------------------------------- 608 * Port assignment functions (mapping devices to uart_port structures) 609 */ 610 611 /** ulite_assign: register a uartlite device with the driver 612 * 613 * @dev: pointer to device structure 614 * @id: requested id number. Pass -1 for automatic port assignment 615 * @base: base address of uartlite registers 616 * @irq: irq number for uartlite 617 * @pdata: private data for uartlite 618 * 619 * Returns: 0 on success, <0 otherwise 620 */ 621 static int ulite_assign(struct device *dev, int id, u32 base, int irq, 622 struct uartlite_data *pdata) 623 { 624 struct uart_port *port; 625 int rc; 626 627 /* if id = -1; then scan for a free id and use that */ 628 if (id < 0) { 629 for (id = 0; id < ULITE_NR_UARTS; id++) 630 if (ulite_ports[id].mapbase == 0) 631 break; 632 } 633 if (id < 0 || id >= ULITE_NR_UARTS) { 634 dev_err(dev, "%s%i too large\n", ULITE_NAME, id); 635 return -EINVAL; 636 } 637 638 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) { 639 dev_err(dev, "cannot assign to %s%i; it is already in use\n", 640 ULITE_NAME, id); 641 return -EBUSY; 642 } 643 644 port = &ulite_ports[id]; 645 646 spin_lock_init(&port->lock); 647 port->fifosize = 16; 648 port->regshift = 2; 649 port->iotype = UPIO_MEM; 650 port->iobase = 1; /* mark port in use */ 651 port->mapbase = base; 652 port->membase = NULL; 653 port->ops = &ulite_ops; 654 port->irq = irq; 655 port->flags = UPF_BOOT_AUTOCONF; 656 port->dev = dev; 657 port->type = PORT_UNKNOWN; 658 port->line = id; 659 port->private_data = pdata; 660 661 dev_set_drvdata(dev, port); 662 663 /* Register the port */ 664 rc = uart_add_one_port(&ulite_uart_driver, port); 665 if (rc) { 666 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc); 667 port->mapbase = 0; 668 dev_set_drvdata(dev, NULL); 669 return rc; 670 } 671 672 return 0; 673 } 674 675 /** ulite_release: register a uartlite device with the driver 676 * 677 * @dev: pointer to device structure 678 */ 679 static int ulite_release(struct device *dev) 680 { 681 struct uart_port *port = dev_get_drvdata(dev); 682 int rc = 0; 683 684 if (port) { 685 rc = uart_remove_one_port(&ulite_uart_driver, port); 686 dev_set_drvdata(dev, NULL); 687 port->mapbase = 0; 688 } 689 690 return rc; 691 } 692 693 /** 694 * ulite_suspend - Stop the device. 695 * 696 * @dev: handle to the device structure. 697 * Return: 0 always. 698 */ 699 static int __maybe_unused ulite_suspend(struct device *dev) 700 { 701 struct uart_port *port = dev_get_drvdata(dev); 702 703 if (port) 704 uart_suspend_port(&ulite_uart_driver, port); 705 706 return 0; 707 } 708 709 /** 710 * ulite_resume - Resume the device. 711 * 712 * @dev: handle to the device structure. 713 * Return: 0 on success, errno otherwise. 714 */ 715 static int __maybe_unused ulite_resume(struct device *dev) 716 { 717 struct uart_port *port = dev_get_drvdata(dev); 718 719 if (port) 720 uart_resume_port(&ulite_uart_driver, port); 721 722 return 0; 723 } 724 725 /* --------------------------------------------------------------------- 726 * Platform bus binding 727 */ 728 729 static SIMPLE_DEV_PM_OPS(ulite_pm_ops, ulite_suspend, ulite_resume); 730 731 #if defined(CONFIG_OF) 732 /* Match table for of_platform binding */ 733 static const struct of_device_id ulite_of_match[] = { 734 { .compatible = "xlnx,opb-uartlite-1.00.b", }, 735 { .compatible = "xlnx,xps-uartlite-1.00.a", }, 736 {} 737 }; 738 MODULE_DEVICE_TABLE(of, ulite_of_match); 739 #endif /* CONFIG_OF */ 740 741 static int ulite_probe(struct platform_device *pdev) 742 { 743 struct resource *res; 744 struct uartlite_data *pdata; 745 int irq, ret; 746 int id = pdev->id; 747 #ifdef CONFIG_OF 748 const __be32 *prop; 749 750 prop = of_get_property(pdev->dev.of_node, "port-number", NULL); 751 if (prop) 752 id = be32_to_cpup(prop); 753 #endif 754 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data), 755 GFP_KERNEL); 756 if (!pdata) 757 return -ENOMEM; 758 759 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 760 if (!res) 761 return -ENODEV; 762 763 irq = platform_get_irq(pdev, 0); 764 if (irq <= 0) 765 return -ENXIO; 766 767 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 768 if (IS_ERR(pdata->clk)) { 769 if (PTR_ERR(pdata->clk) != -ENOENT) 770 return PTR_ERR(pdata->clk); 771 772 /* 773 * Clock framework support is optional, continue on 774 * anyways if we don't find a matching clock. 775 */ 776 pdata->clk = NULL; 777 } 778 779 ret = clk_prepare(pdata->clk); 780 if (ret) { 781 dev_err(&pdev->dev, "Failed to prepare clock\n"); 782 return ret; 783 } 784 785 return ulite_assign(&pdev->dev, id, res->start, irq, pdata); 786 } 787 788 static int ulite_remove(struct platform_device *pdev) 789 { 790 struct uart_port *port = dev_get_drvdata(&pdev->dev); 791 struct uartlite_data *pdata = port->private_data; 792 793 clk_disable_unprepare(pdata->clk); 794 return ulite_release(&pdev->dev); 795 } 796 797 /* work with hotplug and coldplug */ 798 MODULE_ALIAS("platform:uartlite"); 799 800 static struct platform_driver ulite_platform_driver = { 801 .probe = ulite_probe, 802 .remove = ulite_remove, 803 .driver = { 804 .name = "uartlite", 805 .of_match_table = of_match_ptr(ulite_of_match), 806 .pm = &ulite_pm_ops, 807 }, 808 }; 809 810 /* --------------------------------------------------------------------- 811 * Module setup/teardown 812 */ 813 814 static int __init ulite_init(void) 815 { 816 int ret; 817 818 pr_debug("uartlite: calling uart_register_driver()\n"); 819 ret = uart_register_driver(&ulite_uart_driver); 820 if (ret) 821 goto err_uart; 822 823 pr_debug("uartlite: calling platform_driver_register()\n"); 824 ret = platform_driver_register(&ulite_platform_driver); 825 if (ret) 826 goto err_plat; 827 828 return 0; 829 830 err_plat: 831 uart_unregister_driver(&ulite_uart_driver); 832 err_uart: 833 pr_err("registering uartlite driver failed: err=%i\n", ret); 834 return ret; 835 } 836 837 static void __exit ulite_exit(void) 838 { 839 platform_driver_unregister(&ulite_platform_driver); 840 uart_unregister_driver(&ulite_uart_driver); 841 } 842 843 module_init(ulite_init); 844 module_exit(ulite_exit); 845 846 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); 847 MODULE_DESCRIPTION("Xilinx uartlite serial driver"); 848 MODULE_LICENSE("GPL"); 849