1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * uartlite.c: Serial driver for Xilinx uartlite serial controller 4 * 5 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk> 6 * Copyright (C) 2007 Secret Lab Technologies Ltd. 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/console.h> 12 #include <linux/serial.h> 13 #include <linux/serial_core.h> 14 #include <linux/tty.h> 15 #include <linux/tty_flip.h> 16 #include <linux/delay.h> 17 #include <linux/interrupt.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_platform.h> 24 #include <linux/clk.h> 25 26 #define ULITE_NAME "ttyUL" 27 #define ULITE_MAJOR 204 28 #define ULITE_MINOR 187 29 #define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS 30 31 /* --------------------------------------------------------------------- 32 * Register definitions 33 * 34 * For register details see datasheet: 35 * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf 36 */ 37 38 #define ULITE_RX 0x00 39 #define ULITE_TX 0x04 40 #define ULITE_STATUS 0x08 41 #define ULITE_CONTROL 0x0c 42 43 #define ULITE_REGION 16 44 45 #define ULITE_STATUS_RXVALID 0x01 46 #define ULITE_STATUS_RXFULL 0x02 47 #define ULITE_STATUS_TXEMPTY 0x04 48 #define ULITE_STATUS_TXFULL 0x08 49 #define ULITE_STATUS_IE 0x10 50 #define ULITE_STATUS_OVERRUN 0x20 51 #define ULITE_STATUS_FRAME 0x40 52 #define ULITE_STATUS_PARITY 0x80 53 54 #define ULITE_CONTROL_RST_TX 0x01 55 #define ULITE_CONTROL_RST_RX 0x02 56 #define ULITE_CONTROL_IE 0x10 57 58 /* Static pointer to console port */ 59 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 60 static struct uart_port *console_port; 61 #endif 62 63 struct uartlite_data { 64 const struct uartlite_reg_ops *reg_ops; 65 struct clk *clk; 66 }; 67 68 struct uartlite_reg_ops { 69 u32 (*in)(void __iomem *addr); 70 void (*out)(u32 val, void __iomem *addr); 71 }; 72 73 static u32 uartlite_inbe32(void __iomem *addr) 74 { 75 return ioread32be(addr); 76 } 77 78 static void uartlite_outbe32(u32 val, void __iomem *addr) 79 { 80 iowrite32be(val, addr); 81 } 82 83 static const struct uartlite_reg_ops uartlite_be = { 84 .in = uartlite_inbe32, 85 .out = uartlite_outbe32, 86 }; 87 88 static u32 uartlite_inle32(void __iomem *addr) 89 { 90 return ioread32(addr); 91 } 92 93 static void uartlite_outle32(u32 val, void __iomem *addr) 94 { 95 iowrite32(val, addr); 96 } 97 98 static const struct uartlite_reg_ops uartlite_le = { 99 .in = uartlite_inle32, 100 .out = uartlite_outle32, 101 }; 102 103 static inline u32 uart_in32(u32 offset, struct uart_port *port) 104 { 105 struct uartlite_data *pdata = port->private_data; 106 107 return pdata->reg_ops->in(port->membase + offset); 108 } 109 110 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port) 111 { 112 struct uartlite_data *pdata = port->private_data; 113 114 pdata->reg_ops->out(val, port->membase + offset); 115 } 116 117 static struct uart_port ulite_ports[ULITE_NR_UARTS]; 118 119 /* --------------------------------------------------------------------- 120 * Core UART driver operations 121 */ 122 123 static int ulite_receive(struct uart_port *port, int stat) 124 { 125 struct tty_port *tport = &port->state->port; 126 unsigned char ch = 0; 127 char flag = TTY_NORMAL; 128 129 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 130 | ULITE_STATUS_FRAME)) == 0) 131 return 0; 132 133 /* stats */ 134 if (stat & ULITE_STATUS_RXVALID) { 135 port->icount.rx++; 136 ch = uart_in32(ULITE_RX, port); 137 138 if (stat & ULITE_STATUS_PARITY) 139 port->icount.parity++; 140 } 141 142 if (stat & ULITE_STATUS_OVERRUN) 143 port->icount.overrun++; 144 145 if (stat & ULITE_STATUS_FRAME) 146 port->icount.frame++; 147 148 149 /* drop byte with parity error if IGNPAR specificed */ 150 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) 151 stat &= ~ULITE_STATUS_RXVALID; 152 153 stat &= port->read_status_mask; 154 155 if (stat & ULITE_STATUS_PARITY) 156 flag = TTY_PARITY; 157 158 159 stat &= ~port->ignore_status_mask; 160 161 if (stat & ULITE_STATUS_RXVALID) 162 tty_insert_flip_char(tport, ch, flag); 163 164 if (stat & ULITE_STATUS_FRAME) 165 tty_insert_flip_char(tport, 0, TTY_FRAME); 166 167 if (stat & ULITE_STATUS_OVERRUN) 168 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 169 170 return 1; 171 } 172 173 static int ulite_transmit(struct uart_port *port, int stat) 174 { 175 struct circ_buf *xmit = &port->state->xmit; 176 177 if (stat & ULITE_STATUS_TXFULL) 178 return 0; 179 180 if (port->x_char) { 181 uart_out32(port->x_char, ULITE_TX, port); 182 port->x_char = 0; 183 port->icount.tx++; 184 return 1; 185 } 186 187 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 188 return 0; 189 190 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port); 191 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1); 192 port->icount.tx++; 193 194 /* wake up */ 195 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 196 uart_write_wakeup(port); 197 198 return 1; 199 } 200 201 static irqreturn_t ulite_isr(int irq, void *dev_id) 202 { 203 struct uart_port *port = dev_id; 204 int stat, busy, n = 0; 205 unsigned long flags; 206 207 do { 208 spin_lock_irqsave(&port->lock, flags); 209 stat = uart_in32(ULITE_STATUS, port); 210 busy = ulite_receive(port, stat); 211 busy |= ulite_transmit(port, stat); 212 spin_unlock_irqrestore(&port->lock, flags); 213 n++; 214 } while (busy); 215 216 /* work done? */ 217 if (n > 1) { 218 tty_flip_buffer_push(&port->state->port); 219 return IRQ_HANDLED; 220 } else { 221 return IRQ_NONE; 222 } 223 } 224 225 static unsigned int ulite_tx_empty(struct uart_port *port) 226 { 227 unsigned long flags; 228 unsigned int ret; 229 230 spin_lock_irqsave(&port->lock, flags); 231 ret = uart_in32(ULITE_STATUS, port); 232 spin_unlock_irqrestore(&port->lock, flags); 233 234 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0; 235 } 236 237 static unsigned int ulite_get_mctrl(struct uart_port *port) 238 { 239 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 240 } 241 242 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl) 243 { 244 /* N/A */ 245 } 246 247 static void ulite_stop_tx(struct uart_port *port) 248 { 249 /* N/A */ 250 } 251 252 static void ulite_start_tx(struct uart_port *port) 253 { 254 ulite_transmit(port, uart_in32(ULITE_STATUS, port)); 255 } 256 257 static void ulite_stop_rx(struct uart_port *port) 258 { 259 /* don't forward any more data (like !CREAD) */ 260 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 261 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 262 } 263 264 static void ulite_break_ctl(struct uart_port *port, int ctl) 265 { 266 /* N/A */ 267 } 268 269 static int ulite_startup(struct uart_port *port) 270 { 271 struct uartlite_data *pdata = port->private_data; 272 int ret; 273 274 ret = clk_enable(pdata->clk); 275 if (ret) { 276 dev_err(port->dev, "Failed to enable clock\n"); 277 return ret; 278 } 279 280 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING, 281 "uartlite", port); 282 if (ret) 283 return ret; 284 285 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX, 286 ULITE_CONTROL, port); 287 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 288 289 return 0; 290 } 291 292 static void ulite_shutdown(struct uart_port *port) 293 { 294 struct uartlite_data *pdata = port->private_data; 295 296 uart_out32(0, ULITE_CONTROL, port); 297 uart_in32(ULITE_CONTROL, port); /* dummy */ 298 free_irq(port->irq, port); 299 clk_disable(pdata->clk); 300 } 301 302 static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, 303 struct ktermios *old) 304 { 305 unsigned long flags; 306 unsigned int baud; 307 308 spin_lock_irqsave(&port->lock, flags); 309 310 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 311 | ULITE_STATUS_TXFULL; 312 313 if (termios->c_iflag & INPCK) 314 port->read_status_mask |= 315 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME; 316 317 port->ignore_status_mask = 0; 318 if (termios->c_iflag & IGNPAR) 319 port->ignore_status_mask |= ULITE_STATUS_PARITY 320 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 321 322 /* ignore all characters if CREAD is not set */ 323 if ((termios->c_cflag & CREAD) == 0) 324 port->ignore_status_mask |= 325 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 326 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 327 328 /* update timeout */ 329 baud = uart_get_baud_rate(port, termios, old, 0, 460800); 330 uart_update_timeout(port, termios->c_cflag, baud); 331 332 spin_unlock_irqrestore(&port->lock, flags); 333 } 334 335 static const char *ulite_type(struct uart_port *port) 336 { 337 return port->type == PORT_UARTLITE ? "uartlite" : NULL; 338 } 339 340 static void ulite_release_port(struct uart_port *port) 341 { 342 release_mem_region(port->mapbase, ULITE_REGION); 343 iounmap(port->membase); 344 port->membase = NULL; 345 } 346 347 static int ulite_request_port(struct uart_port *port) 348 { 349 struct uartlite_data *pdata = port->private_data; 350 int ret; 351 352 pr_debug("ulite console: port=%p; port->mapbase=%llx\n", 353 port, (unsigned long long) port->mapbase); 354 355 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { 356 dev_err(port->dev, "Memory region busy\n"); 357 return -EBUSY; 358 } 359 360 port->membase = ioremap(port->mapbase, ULITE_REGION); 361 if (!port->membase) { 362 dev_err(port->dev, "Unable to map registers\n"); 363 release_mem_region(port->mapbase, ULITE_REGION); 364 return -EBUSY; 365 } 366 367 pdata->reg_ops = &uartlite_be; 368 ret = uart_in32(ULITE_CONTROL, port); 369 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); 370 ret = uart_in32(ULITE_STATUS, port); 371 /* Endianess detection */ 372 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY) 373 pdata->reg_ops = &uartlite_le; 374 375 return 0; 376 } 377 378 static void ulite_config_port(struct uart_port *port, int flags) 379 { 380 if (!ulite_request_port(port)) 381 port->type = PORT_UARTLITE; 382 } 383 384 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser) 385 { 386 /* we don't want the core code to modify any port params */ 387 return -EINVAL; 388 } 389 390 static void ulite_pm(struct uart_port *port, unsigned int state, 391 unsigned int oldstate) 392 { 393 struct uartlite_data *pdata = port->private_data; 394 395 if (!state) 396 clk_enable(pdata->clk); 397 else 398 clk_disable(pdata->clk); 399 } 400 401 #ifdef CONFIG_CONSOLE_POLL 402 static int ulite_get_poll_char(struct uart_port *port) 403 { 404 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID)) 405 return NO_POLL_CHAR; 406 407 return uart_in32(ULITE_RX, port); 408 } 409 410 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch) 411 { 412 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL) 413 cpu_relax(); 414 415 /* write char to device */ 416 uart_out32(ch, ULITE_TX, port); 417 } 418 #endif 419 420 static const struct uart_ops ulite_ops = { 421 .tx_empty = ulite_tx_empty, 422 .set_mctrl = ulite_set_mctrl, 423 .get_mctrl = ulite_get_mctrl, 424 .stop_tx = ulite_stop_tx, 425 .start_tx = ulite_start_tx, 426 .stop_rx = ulite_stop_rx, 427 .break_ctl = ulite_break_ctl, 428 .startup = ulite_startup, 429 .shutdown = ulite_shutdown, 430 .set_termios = ulite_set_termios, 431 .type = ulite_type, 432 .release_port = ulite_release_port, 433 .request_port = ulite_request_port, 434 .config_port = ulite_config_port, 435 .verify_port = ulite_verify_port, 436 .pm = ulite_pm, 437 #ifdef CONFIG_CONSOLE_POLL 438 .poll_get_char = ulite_get_poll_char, 439 .poll_put_char = ulite_put_poll_char, 440 #endif 441 }; 442 443 /* --------------------------------------------------------------------- 444 * Console driver operations 445 */ 446 447 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 448 static void ulite_console_wait_tx(struct uart_port *port) 449 { 450 u8 val; 451 unsigned long timeout; 452 453 /* 454 * Spin waiting for TX fifo to have space available. 455 * When using the Microblaze Debug Module this can take up to 1s 456 */ 457 timeout = jiffies + msecs_to_jiffies(1000); 458 while (1) { 459 val = uart_in32(ULITE_STATUS, port); 460 if ((val & ULITE_STATUS_TXFULL) == 0) 461 break; 462 if (time_after(jiffies, timeout)) { 463 dev_warn(port->dev, 464 "timeout waiting for TX buffer empty\n"); 465 break; 466 } 467 cpu_relax(); 468 } 469 } 470 471 static void ulite_console_putchar(struct uart_port *port, int ch) 472 { 473 ulite_console_wait_tx(port); 474 uart_out32(ch, ULITE_TX, port); 475 } 476 477 static void ulite_console_write(struct console *co, const char *s, 478 unsigned int count) 479 { 480 struct uart_port *port = console_port; 481 unsigned long flags; 482 unsigned int ier; 483 int locked = 1; 484 485 if (oops_in_progress) { 486 locked = spin_trylock_irqsave(&port->lock, flags); 487 } else 488 spin_lock_irqsave(&port->lock, flags); 489 490 /* save and disable interrupt */ 491 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE; 492 uart_out32(0, ULITE_CONTROL, port); 493 494 uart_console_write(port, s, count, ulite_console_putchar); 495 496 ulite_console_wait_tx(port); 497 498 /* restore interrupt state */ 499 if (ier) 500 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 501 502 if (locked) 503 spin_unlock_irqrestore(&port->lock, flags); 504 } 505 506 static int ulite_console_setup(struct console *co, char *options) 507 { 508 struct uart_port *port; 509 int baud = 9600; 510 int bits = 8; 511 int parity = 'n'; 512 int flow = 'n'; 513 514 515 port = console_port; 516 517 /* Has the device been initialized yet? */ 518 if (!port->mapbase) { 519 pr_debug("console on ttyUL%i not present\n", co->index); 520 return -ENODEV; 521 } 522 523 /* not initialized yet? */ 524 if (!port->membase) { 525 if (ulite_request_port(port)) 526 return -ENODEV; 527 } 528 529 if (options) 530 uart_parse_options(options, &baud, &parity, &bits, &flow); 531 532 return uart_set_options(port, co, baud, parity, bits, flow); 533 } 534 535 static struct uart_driver ulite_uart_driver; 536 537 static struct console ulite_console = { 538 .name = ULITE_NAME, 539 .write = ulite_console_write, 540 .device = uart_console_device, 541 .setup = ulite_console_setup, 542 .flags = CON_PRINTBUFFER, 543 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */ 544 .data = &ulite_uart_driver, 545 }; 546 547 static void early_uartlite_putc(struct uart_port *port, int c) 548 { 549 /* 550 * Limit how many times we'll spin waiting for TX FIFO status. 551 * This will prevent lockups if the base address is incorrectly 552 * set, or any other issue on the UARTLITE. 553 * This limit is pretty arbitrary, unless we are at about 10 baud 554 * we'll never timeout on a working UART. 555 */ 556 557 unsigned retries = 1000000; 558 /* read status bit - 0x8 offset */ 559 while (--retries && (readl(port->membase + 8) & (1 << 3))) 560 ; 561 562 /* Only attempt the iowrite if we didn't timeout */ 563 /* write to TX_FIFO - 0x4 offset */ 564 if (retries) 565 writel(c & 0xff, port->membase + 4); 566 } 567 568 static void early_uartlite_write(struct console *console, 569 const char *s, unsigned n) 570 { 571 struct earlycon_device *device = console->data; 572 uart_console_write(&device->port, s, n, early_uartlite_putc); 573 } 574 575 static int __init early_uartlite_setup(struct earlycon_device *device, 576 const char *options) 577 { 578 if (!device->port.membase) 579 return -ENODEV; 580 581 device->con->write = early_uartlite_write; 582 return 0; 583 } 584 EARLYCON_DECLARE(uartlite, early_uartlite_setup); 585 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup); 586 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup); 587 588 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */ 589 590 static struct uart_driver ulite_uart_driver = { 591 .owner = THIS_MODULE, 592 .driver_name = "uartlite", 593 .dev_name = ULITE_NAME, 594 .major = ULITE_MAJOR, 595 .minor = ULITE_MINOR, 596 .nr = ULITE_NR_UARTS, 597 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 598 .cons = &ulite_console, 599 #endif 600 }; 601 602 /* --------------------------------------------------------------------- 603 * Port assignment functions (mapping devices to uart_port structures) 604 */ 605 606 /** ulite_assign: register a uartlite device with the driver 607 * 608 * @dev: pointer to device structure 609 * @id: requested id number. Pass -1 for automatic port assignment 610 * @base: base address of uartlite registers 611 * @irq: irq number for uartlite 612 * @pdata: private data for uartlite 613 * 614 * Returns: 0 on success, <0 otherwise 615 */ 616 static int ulite_assign(struct device *dev, int id, u32 base, int irq, 617 struct uartlite_data *pdata) 618 { 619 struct uart_port *port; 620 int rc; 621 622 /* if id = -1; then scan for a free id and use that */ 623 if (id < 0) { 624 for (id = 0; id < ULITE_NR_UARTS; id++) 625 if (ulite_ports[id].mapbase == 0) 626 break; 627 } 628 if (id < 0 || id >= ULITE_NR_UARTS) { 629 dev_err(dev, "%s%i too large\n", ULITE_NAME, id); 630 return -EINVAL; 631 } 632 633 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) { 634 dev_err(dev, "cannot assign to %s%i; it is already in use\n", 635 ULITE_NAME, id); 636 return -EBUSY; 637 } 638 639 port = &ulite_ports[id]; 640 641 spin_lock_init(&port->lock); 642 port->fifosize = 16; 643 port->regshift = 2; 644 port->iotype = UPIO_MEM; 645 port->iobase = 1; /* mark port in use */ 646 port->mapbase = base; 647 port->membase = NULL; 648 port->ops = &ulite_ops; 649 port->irq = irq; 650 port->flags = UPF_BOOT_AUTOCONF; 651 port->dev = dev; 652 port->type = PORT_UNKNOWN; 653 port->line = id; 654 port->private_data = pdata; 655 656 dev_set_drvdata(dev, port); 657 658 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 659 /* 660 * If console hasn't been found yet try to assign this port 661 * because it is required to be assigned for console setup function. 662 * If register_console() don't assign value, then console_port pointer 663 * is cleanup. 664 */ 665 if (ulite_uart_driver.cons->index == -1) 666 console_port = port; 667 #endif 668 669 /* Register the port */ 670 rc = uart_add_one_port(&ulite_uart_driver, port); 671 if (rc) { 672 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc); 673 port->mapbase = 0; 674 dev_set_drvdata(dev, NULL); 675 return rc; 676 } 677 678 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 679 /* This is not port which is used for console that's why clean it up */ 680 if (ulite_uart_driver.cons->index == -1) 681 console_port = NULL; 682 #endif 683 684 return 0; 685 } 686 687 /** ulite_release: register a uartlite device with the driver 688 * 689 * @dev: pointer to device structure 690 */ 691 static int ulite_release(struct device *dev) 692 { 693 struct uart_port *port = dev_get_drvdata(dev); 694 int rc = 0; 695 696 if (port) { 697 rc = uart_remove_one_port(&ulite_uart_driver, port); 698 dev_set_drvdata(dev, NULL); 699 port->mapbase = 0; 700 } 701 702 return rc; 703 } 704 705 /** 706 * ulite_suspend - Stop the device. 707 * 708 * @dev: handle to the device structure. 709 * Return: 0 always. 710 */ 711 static int __maybe_unused ulite_suspend(struct device *dev) 712 { 713 struct uart_port *port = dev_get_drvdata(dev); 714 715 if (port) 716 uart_suspend_port(&ulite_uart_driver, port); 717 718 return 0; 719 } 720 721 /** 722 * ulite_resume - Resume the device. 723 * 724 * @dev: handle to the device structure. 725 * Return: 0 on success, errno otherwise. 726 */ 727 static int __maybe_unused ulite_resume(struct device *dev) 728 { 729 struct uart_port *port = dev_get_drvdata(dev); 730 731 if (port) 732 uart_resume_port(&ulite_uart_driver, port); 733 734 return 0; 735 } 736 737 /* --------------------------------------------------------------------- 738 * Platform bus binding 739 */ 740 741 static SIMPLE_DEV_PM_OPS(ulite_pm_ops, ulite_suspend, ulite_resume); 742 743 #if defined(CONFIG_OF) 744 /* Match table for of_platform binding */ 745 static const struct of_device_id ulite_of_match[] = { 746 { .compatible = "xlnx,opb-uartlite-1.00.b", }, 747 { .compatible = "xlnx,xps-uartlite-1.00.a", }, 748 {} 749 }; 750 MODULE_DEVICE_TABLE(of, ulite_of_match); 751 #endif /* CONFIG_OF */ 752 753 static int ulite_probe(struct platform_device *pdev) 754 { 755 struct resource *res; 756 struct uartlite_data *pdata; 757 int irq, ret; 758 int id = pdev->id; 759 #ifdef CONFIG_OF 760 const __be32 *prop; 761 762 prop = of_get_property(pdev->dev.of_node, "port-number", NULL); 763 if (prop) 764 id = be32_to_cpup(prop); 765 #endif 766 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data), 767 GFP_KERNEL); 768 if (!pdata) 769 return -ENOMEM; 770 771 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 772 if (!res) 773 return -ENODEV; 774 775 irq = platform_get_irq(pdev, 0); 776 if (irq < 0) 777 return irq; 778 779 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 780 if (IS_ERR(pdata->clk)) { 781 if (PTR_ERR(pdata->clk) != -ENOENT) 782 return PTR_ERR(pdata->clk); 783 784 /* 785 * Clock framework support is optional, continue on 786 * anyways if we don't find a matching clock. 787 */ 788 pdata->clk = NULL; 789 } 790 791 ret = clk_prepare_enable(pdata->clk); 792 if (ret) { 793 dev_err(&pdev->dev, "Failed to prepare clock\n"); 794 return ret; 795 } 796 797 if (!ulite_uart_driver.state) { 798 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n"); 799 ret = uart_register_driver(&ulite_uart_driver); 800 if (ret < 0) { 801 dev_err(&pdev->dev, "Failed to register driver\n"); 802 return ret; 803 } 804 } 805 806 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata); 807 808 clk_disable(pdata->clk); 809 810 return ret; 811 } 812 813 static int ulite_remove(struct platform_device *pdev) 814 { 815 struct uart_port *port = dev_get_drvdata(&pdev->dev); 816 struct uartlite_data *pdata = port->private_data; 817 818 clk_disable_unprepare(pdata->clk); 819 return ulite_release(&pdev->dev); 820 } 821 822 /* work with hotplug and coldplug */ 823 MODULE_ALIAS("platform:uartlite"); 824 825 static struct platform_driver ulite_platform_driver = { 826 .probe = ulite_probe, 827 .remove = ulite_remove, 828 .driver = { 829 .name = "uartlite", 830 .of_match_table = of_match_ptr(ulite_of_match), 831 .pm = &ulite_pm_ops, 832 }, 833 }; 834 835 /* --------------------------------------------------------------------- 836 * Module setup/teardown 837 */ 838 839 static int __init ulite_init(void) 840 { 841 842 pr_debug("uartlite: calling platform_driver_register()\n"); 843 return platform_driver_register(&ulite_platform_driver); 844 } 845 846 static void __exit ulite_exit(void) 847 { 848 platform_driver_unregister(&ulite_platform_driver); 849 if (ulite_uart_driver.state) 850 uart_unregister_driver(&ulite_uart_driver); 851 } 852 853 module_init(ulite_init); 854 module_exit(ulite_exit); 855 856 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); 857 MODULE_DESCRIPTION("Xilinx uartlite serial driver"); 858 MODULE_LICENSE("GPL"); 859