1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * uartlite.c: Serial driver for Xilinx uartlite serial controller 4 * 5 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk> 6 * Copyright (C) 2007 Secret Lab Technologies Ltd. 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/console.h> 12 #include <linux/serial.h> 13 #include <linux/serial_core.h> 14 #include <linux/tty.h> 15 #include <linux/tty_flip.h> 16 #include <linux/delay.h> 17 #include <linux/interrupt.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_platform.h> 24 #include <linux/clk.h> 25 #include <linux/pm_runtime.h> 26 27 #define ULITE_NAME "ttyUL" 28 #define ULITE_MAJOR 204 29 #define ULITE_MINOR 187 30 #define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS 31 32 /* --------------------------------------------------------------------- 33 * Register definitions 34 * 35 * For register details see datasheet: 36 * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf 37 */ 38 39 #define ULITE_RX 0x00 40 #define ULITE_TX 0x04 41 #define ULITE_STATUS 0x08 42 #define ULITE_CONTROL 0x0c 43 44 #define ULITE_REGION 16 45 46 #define ULITE_STATUS_RXVALID 0x01 47 #define ULITE_STATUS_RXFULL 0x02 48 #define ULITE_STATUS_TXEMPTY 0x04 49 #define ULITE_STATUS_TXFULL 0x08 50 #define ULITE_STATUS_IE 0x10 51 #define ULITE_STATUS_OVERRUN 0x20 52 #define ULITE_STATUS_FRAME 0x40 53 #define ULITE_STATUS_PARITY 0x80 54 55 #define ULITE_CONTROL_RST_TX 0x01 56 #define ULITE_CONTROL_RST_RX 0x02 57 #define ULITE_CONTROL_IE 0x10 58 #define UART_AUTOSUSPEND_TIMEOUT 3000 /* ms */ 59 60 /* Static pointer to console port */ 61 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 62 static struct uart_port *console_port; 63 #endif 64 65 struct uartlite_data { 66 const struct uartlite_reg_ops *reg_ops; 67 struct clk *clk; 68 }; 69 70 struct uartlite_reg_ops { 71 u32 (*in)(void __iomem *addr); 72 void (*out)(u32 val, void __iomem *addr); 73 }; 74 75 static u32 uartlite_inbe32(void __iomem *addr) 76 { 77 return ioread32be(addr); 78 } 79 80 static void uartlite_outbe32(u32 val, void __iomem *addr) 81 { 82 iowrite32be(val, addr); 83 } 84 85 static const struct uartlite_reg_ops uartlite_be = { 86 .in = uartlite_inbe32, 87 .out = uartlite_outbe32, 88 }; 89 90 static u32 uartlite_inle32(void __iomem *addr) 91 { 92 return ioread32(addr); 93 } 94 95 static void uartlite_outle32(u32 val, void __iomem *addr) 96 { 97 iowrite32(val, addr); 98 } 99 100 static const struct uartlite_reg_ops uartlite_le = { 101 .in = uartlite_inle32, 102 .out = uartlite_outle32, 103 }; 104 105 static inline u32 uart_in32(u32 offset, struct uart_port *port) 106 { 107 struct uartlite_data *pdata = port->private_data; 108 109 return pdata->reg_ops->in(port->membase + offset); 110 } 111 112 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port) 113 { 114 struct uartlite_data *pdata = port->private_data; 115 116 pdata->reg_ops->out(val, port->membase + offset); 117 } 118 119 static struct uart_port ulite_ports[ULITE_NR_UARTS]; 120 121 /* --------------------------------------------------------------------- 122 * Core UART driver operations 123 */ 124 125 static int ulite_receive(struct uart_port *port, int stat) 126 { 127 struct tty_port *tport = &port->state->port; 128 unsigned char ch = 0; 129 char flag = TTY_NORMAL; 130 131 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 132 | ULITE_STATUS_FRAME)) == 0) 133 return 0; 134 135 /* stats */ 136 if (stat & ULITE_STATUS_RXVALID) { 137 port->icount.rx++; 138 ch = uart_in32(ULITE_RX, port); 139 140 if (stat & ULITE_STATUS_PARITY) 141 port->icount.parity++; 142 } 143 144 if (stat & ULITE_STATUS_OVERRUN) 145 port->icount.overrun++; 146 147 if (stat & ULITE_STATUS_FRAME) 148 port->icount.frame++; 149 150 151 /* drop byte with parity error if IGNPAR specificed */ 152 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) 153 stat &= ~ULITE_STATUS_RXVALID; 154 155 stat &= port->read_status_mask; 156 157 if (stat & ULITE_STATUS_PARITY) 158 flag = TTY_PARITY; 159 160 161 stat &= ~port->ignore_status_mask; 162 163 if (stat & ULITE_STATUS_RXVALID) 164 tty_insert_flip_char(tport, ch, flag); 165 166 if (stat & ULITE_STATUS_FRAME) 167 tty_insert_flip_char(tport, 0, TTY_FRAME); 168 169 if (stat & ULITE_STATUS_OVERRUN) 170 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 171 172 return 1; 173 } 174 175 static int ulite_transmit(struct uart_port *port, int stat) 176 { 177 struct circ_buf *xmit = &port->state->xmit; 178 179 if (stat & ULITE_STATUS_TXFULL) 180 return 0; 181 182 if (port->x_char) { 183 uart_out32(port->x_char, ULITE_TX, port); 184 port->x_char = 0; 185 port->icount.tx++; 186 return 1; 187 } 188 189 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 190 return 0; 191 192 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port); 193 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1); 194 port->icount.tx++; 195 196 /* wake up */ 197 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 198 uart_write_wakeup(port); 199 200 return 1; 201 } 202 203 static irqreturn_t ulite_isr(int irq, void *dev_id) 204 { 205 struct uart_port *port = dev_id; 206 int stat, busy, n = 0; 207 unsigned long flags; 208 209 do { 210 spin_lock_irqsave(&port->lock, flags); 211 stat = uart_in32(ULITE_STATUS, port); 212 busy = ulite_receive(port, stat); 213 busy |= ulite_transmit(port, stat); 214 spin_unlock_irqrestore(&port->lock, flags); 215 n++; 216 } while (busy); 217 218 /* work done? */ 219 if (n > 1) { 220 tty_flip_buffer_push(&port->state->port); 221 return IRQ_HANDLED; 222 } else { 223 return IRQ_NONE; 224 } 225 } 226 227 static unsigned int ulite_tx_empty(struct uart_port *port) 228 { 229 unsigned long flags; 230 unsigned int ret; 231 232 spin_lock_irqsave(&port->lock, flags); 233 ret = uart_in32(ULITE_STATUS, port); 234 spin_unlock_irqrestore(&port->lock, flags); 235 236 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0; 237 } 238 239 static unsigned int ulite_get_mctrl(struct uart_port *port) 240 { 241 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 242 } 243 244 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl) 245 { 246 /* N/A */ 247 } 248 249 static void ulite_stop_tx(struct uart_port *port) 250 { 251 /* N/A */ 252 } 253 254 static void ulite_start_tx(struct uart_port *port) 255 { 256 ulite_transmit(port, uart_in32(ULITE_STATUS, port)); 257 } 258 259 static void ulite_stop_rx(struct uart_port *port) 260 { 261 /* don't forward any more data (like !CREAD) */ 262 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 263 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 264 } 265 266 static void ulite_break_ctl(struct uart_port *port, int ctl) 267 { 268 /* N/A */ 269 } 270 271 static int ulite_startup(struct uart_port *port) 272 { 273 struct uartlite_data *pdata = port->private_data; 274 int ret; 275 276 ret = clk_enable(pdata->clk); 277 if (ret) { 278 dev_err(port->dev, "Failed to enable clock\n"); 279 return ret; 280 } 281 282 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING, 283 "uartlite", port); 284 if (ret) 285 return ret; 286 287 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX, 288 ULITE_CONTROL, port); 289 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 290 291 return 0; 292 } 293 294 static void ulite_shutdown(struct uart_port *port) 295 { 296 struct uartlite_data *pdata = port->private_data; 297 298 uart_out32(0, ULITE_CONTROL, port); 299 uart_in32(ULITE_CONTROL, port); /* dummy */ 300 free_irq(port->irq, port); 301 clk_disable(pdata->clk); 302 } 303 304 static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, 305 struct ktermios *old) 306 { 307 unsigned long flags; 308 unsigned int baud; 309 310 spin_lock_irqsave(&port->lock, flags); 311 312 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 313 | ULITE_STATUS_TXFULL; 314 315 if (termios->c_iflag & INPCK) 316 port->read_status_mask |= 317 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME; 318 319 port->ignore_status_mask = 0; 320 if (termios->c_iflag & IGNPAR) 321 port->ignore_status_mask |= ULITE_STATUS_PARITY 322 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 323 324 /* ignore all characters if CREAD is not set */ 325 if ((termios->c_cflag & CREAD) == 0) 326 port->ignore_status_mask |= 327 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 328 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 329 330 /* update timeout */ 331 baud = uart_get_baud_rate(port, termios, old, 0, 460800); 332 uart_update_timeout(port, termios->c_cflag, baud); 333 334 spin_unlock_irqrestore(&port->lock, flags); 335 } 336 337 static const char *ulite_type(struct uart_port *port) 338 { 339 return port->type == PORT_UARTLITE ? "uartlite" : NULL; 340 } 341 342 static void ulite_release_port(struct uart_port *port) 343 { 344 release_mem_region(port->mapbase, ULITE_REGION); 345 iounmap(port->membase); 346 port->membase = NULL; 347 } 348 349 static int ulite_request_port(struct uart_port *port) 350 { 351 struct uartlite_data *pdata = port->private_data; 352 int ret; 353 354 pr_debug("ulite console: port=%p; port->mapbase=%llx\n", 355 port, (unsigned long long) port->mapbase); 356 357 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { 358 dev_err(port->dev, "Memory region busy\n"); 359 return -EBUSY; 360 } 361 362 port->membase = ioremap(port->mapbase, ULITE_REGION); 363 if (!port->membase) { 364 dev_err(port->dev, "Unable to map registers\n"); 365 release_mem_region(port->mapbase, ULITE_REGION); 366 return -EBUSY; 367 } 368 369 pdata->reg_ops = &uartlite_be; 370 ret = uart_in32(ULITE_CONTROL, port); 371 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); 372 ret = uart_in32(ULITE_STATUS, port); 373 /* Endianess detection */ 374 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY) 375 pdata->reg_ops = &uartlite_le; 376 377 return 0; 378 } 379 380 static void ulite_config_port(struct uart_port *port, int flags) 381 { 382 if (!ulite_request_port(port)) 383 port->type = PORT_UARTLITE; 384 } 385 386 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser) 387 { 388 /* we don't want the core code to modify any port params */ 389 return -EINVAL; 390 } 391 392 static void ulite_pm(struct uart_port *port, unsigned int state, 393 unsigned int oldstate) 394 { 395 int ret; 396 397 if (!state) { 398 ret = pm_runtime_get_sync(port->dev); 399 if (ret < 0) 400 dev_err(port->dev, "Failed to enable clocks\n"); 401 } else { 402 pm_runtime_mark_last_busy(port->dev); 403 pm_runtime_put_autosuspend(port->dev); 404 } 405 } 406 407 #ifdef CONFIG_CONSOLE_POLL 408 static int ulite_get_poll_char(struct uart_port *port) 409 { 410 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID)) 411 return NO_POLL_CHAR; 412 413 return uart_in32(ULITE_RX, port); 414 } 415 416 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch) 417 { 418 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL) 419 cpu_relax(); 420 421 /* write char to device */ 422 uart_out32(ch, ULITE_TX, port); 423 } 424 #endif 425 426 static const struct uart_ops ulite_ops = { 427 .tx_empty = ulite_tx_empty, 428 .set_mctrl = ulite_set_mctrl, 429 .get_mctrl = ulite_get_mctrl, 430 .stop_tx = ulite_stop_tx, 431 .start_tx = ulite_start_tx, 432 .stop_rx = ulite_stop_rx, 433 .break_ctl = ulite_break_ctl, 434 .startup = ulite_startup, 435 .shutdown = ulite_shutdown, 436 .set_termios = ulite_set_termios, 437 .type = ulite_type, 438 .release_port = ulite_release_port, 439 .request_port = ulite_request_port, 440 .config_port = ulite_config_port, 441 .verify_port = ulite_verify_port, 442 .pm = ulite_pm, 443 #ifdef CONFIG_CONSOLE_POLL 444 .poll_get_char = ulite_get_poll_char, 445 .poll_put_char = ulite_put_poll_char, 446 #endif 447 }; 448 449 /* --------------------------------------------------------------------- 450 * Console driver operations 451 */ 452 453 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 454 static void ulite_console_wait_tx(struct uart_port *port) 455 { 456 u8 val; 457 unsigned long timeout; 458 459 /* 460 * Spin waiting for TX fifo to have space available. 461 * When using the Microblaze Debug Module this can take up to 1s 462 */ 463 timeout = jiffies + msecs_to_jiffies(1000); 464 while (1) { 465 val = uart_in32(ULITE_STATUS, port); 466 if ((val & ULITE_STATUS_TXFULL) == 0) 467 break; 468 if (time_after(jiffies, timeout)) { 469 dev_warn(port->dev, 470 "timeout waiting for TX buffer empty\n"); 471 break; 472 } 473 cpu_relax(); 474 } 475 } 476 477 static void ulite_console_putchar(struct uart_port *port, int ch) 478 { 479 ulite_console_wait_tx(port); 480 uart_out32(ch, ULITE_TX, port); 481 } 482 483 static void ulite_console_write(struct console *co, const char *s, 484 unsigned int count) 485 { 486 struct uart_port *port = console_port; 487 unsigned long flags; 488 unsigned int ier; 489 int locked = 1; 490 491 if (oops_in_progress) { 492 locked = spin_trylock_irqsave(&port->lock, flags); 493 } else 494 spin_lock_irqsave(&port->lock, flags); 495 496 /* save and disable interrupt */ 497 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE; 498 uart_out32(0, ULITE_CONTROL, port); 499 500 uart_console_write(port, s, count, ulite_console_putchar); 501 502 ulite_console_wait_tx(port); 503 504 /* restore interrupt state */ 505 if (ier) 506 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 507 508 if (locked) 509 spin_unlock_irqrestore(&port->lock, flags); 510 } 511 512 static int ulite_console_setup(struct console *co, char *options) 513 { 514 struct uart_port *port = NULL; 515 int baud = 9600; 516 int bits = 8; 517 int parity = 'n'; 518 int flow = 'n'; 519 520 if (co->index >= 0 && co->index < ULITE_NR_UARTS) 521 port = ulite_ports + co->index; 522 523 /* Has the device been initialized yet? */ 524 if (!port || !port->mapbase) { 525 pr_debug("console on ttyUL%i not present\n", co->index); 526 return -ENODEV; 527 } 528 529 console_port = port; 530 531 /* not initialized yet? */ 532 if (!port->membase) { 533 if (ulite_request_port(port)) 534 return -ENODEV; 535 } 536 537 if (options) 538 uart_parse_options(options, &baud, &parity, &bits, &flow); 539 540 return uart_set_options(port, co, baud, parity, bits, flow); 541 } 542 543 static struct uart_driver ulite_uart_driver; 544 545 static struct console ulite_console = { 546 .name = ULITE_NAME, 547 .write = ulite_console_write, 548 .device = uart_console_device, 549 .setup = ulite_console_setup, 550 .flags = CON_PRINTBUFFER, 551 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */ 552 .data = &ulite_uart_driver, 553 }; 554 555 static void early_uartlite_putc(struct uart_port *port, int c) 556 { 557 /* 558 * Limit how many times we'll spin waiting for TX FIFO status. 559 * This will prevent lockups if the base address is incorrectly 560 * set, or any other issue on the UARTLITE. 561 * This limit is pretty arbitrary, unless we are at about 10 baud 562 * we'll never timeout on a working UART. 563 */ 564 565 unsigned retries = 1000000; 566 /* read status bit - 0x8 offset */ 567 while (--retries && (readl(port->membase + 8) & (1 << 3))) 568 ; 569 570 /* Only attempt the iowrite if we didn't timeout */ 571 /* write to TX_FIFO - 0x4 offset */ 572 if (retries) 573 writel(c & 0xff, port->membase + 4); 574 } 575 576 static void early_uartlite_write(struct console *console, 577 const char *s, unsigned n) 578 { 579 struct earlycon_device *device = console->data; 580 uart_console_write(&device->port, s, n, early_uartlite_putc); 581 } 582 583 static int __init early_uartlite_setup(struct earlycon_device *device, 584 const char *options) 585 { 586 if (!device->port.membase) 587 return -ENODEV; 588 589 device->con->write = early_uartlite_write; 590 return 0; 591 } 592 EARLYCON_DECLARE(uartlite, early_uartlite_setup); 593 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup); 594 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup); 595 596 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */ 597 598 static struct uart_driver ulite_uart_driver = { 599 .owner = THIS_MODULE, 600 .driver_name = "uartlite", 601 .dev_name = ULITE_NAME, 602 .major = ULITE_MAJOR, 603 .minor = ULITE_MINOR, 604 .nr = ULITE_NR_UARTS, 605 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 606 .cons = &ulite_console, 607 #endif 608 }; 609 610 /* --------------------------------------------------------------------- 611 * Port assignment functions (mapping devices to uart_port structures) 612 */ 613 614 /** ulite_assign: register a uartlite device with the driver 615 * 616 * @dev: pointer to device structure 617 * @id: requested id number. Pass -1 for automatic port assignment 618 * @base: base address of uartlite registers 619 * @irq: irq number for uartlite 620 * @pdata: private data for uartlite 621 * 622 * Returns: 0 on success, <0 otherwise 623 */ 624 static int ulite_assign(struct device *dev, int id, u32 base, int irq, 625 struct uartlite_data *pdata) 626 { 627 struct uart_port *port; 628 int rc; 629 630 /* if id = -1; then scan for a free id and use that */ 631 if (id < 0) { 632 for (id = 0; id < ULITE_NR_UARTS; id++) 633 if (ulite_ports[id].mapbase == 0) 634 break; 635 } 636 if (id < 0 || id >= ULITE_NR_UARTS) { 637 dev_err(dev, "%s%i too large\n", ULITE_NAME, id); 638 return -EINVAL; 639 } 640 641 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) { 642 dev_err(dev, "cannot assign to %s%i; it is already in use\n", 643 ULITE_NAME, id); 644 return -EBUSY; 645 } 646 647 port = &ulite_ports[id]; 648 649 spin_lock_init(&port->lock); 650 port->fifosize = 16; 651 port->regshift = 2; 652 port->iotype = UPIO_MEM; 653 port->iobase = 1; /* mark port in use */ 654 port->mapbase = base; 655 port->membase = NULL; 656 port->ops = &ulite_ops; 657 port->irq = irq; 658 port->flags = UPF_BOOT_AUTOCONF; 659 port->dev = dev; 660 port->type = PORT_UNKNOWN; 661 port->line = id; 662 port->private_data = pdata; 663 664 dev_set_drvdata(dev, port); 665 666 /* Register the port */ 667 rc = uart_add_one_port(&ulite_uart_driver, port); 668 if (rc) { 669 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc); 670 port->mapbase = 0; 671 dev_set_drvdata(dev, NULL); 672 return rc; 673 } 674 675 return 0; 676 } 677 678 /** ulite_release: register a uartlite device with the driver 679 * 680 * @dev: pointer to device structure 681 */ 682 static int ulite_release(struct device *dev) 683 { 684 struct uart_port *port = dev_get_drvdata(dev); 685 int rc = 0; 686 687 if (port) { 688 rc = uart_remove_one_port(&ulite_uart_driver, port); 689 dev_set_drvdata(dev, NULL); 690 port->mapbase = 0; 691 } 692 693 return rc; 694 } 695 696 /** 697 * ulite_suspend - Stop the device. 698 * 699 * @dev: handle to the device structure. 700 * Return: 0 always. 701 */ 702 static int __maybe_unused ulite_suspend(struct device *dev) 703 { 704 struct uart_port *port = dev_get_drvdata(dev); 705 706 if (port) 707 uart_suspend_port(&ulite_uart_driver, port); 708 709 return 0; 710 } 711 712 /** 713 * ulite_resume - Resume the device. 714 * 715 * @dev: handle to the device structure. 716 * Return: 0 on success, errno otherwise. 717 */ 718 static int __maybe_unused ulite_resume(struct device *dev) 719 { 720 struct uart_port *port = dev_get_drvdata(dev); 721 722 if (port) 723 uart_resume_port(&ulite_uart_driver, port); 724 725 return 0; 726 } 727 728 static int __maybe_unused ulite_runtime_suspend(struct device *dev) 729 { 730 struct uart_port *port = dev_get_drvdata(dev); 731 struct uartlite_data *pdata = port->private_data; 732 733 clk_disable(pdata->clk); 734 return 0; 735 }; 736 737 static int __maybe_unused ulite_runtime_resume(struct device *dev) 738 { 739 struct uart_port *port = dev_get_drvdata(dev); 740 struct uartlite_data *pdata = port->private_data; 741 int ret; 742 743 ret = clk_enable(pdata->clk); 744 if (ret) { 745 dev_err(dev, "Cannot enable clock.\n"); 746 return ret; 747 } 748 return 0; 749 } 750 751 /* --------------------------------------------------------------------- 752 * Platform bus binding 753 */ 754 755 static const struct dev_pm_ops ulite_pm_ops = { 756 SET_SYSTEM_SLEEP_PM_OPS(ulite_suspend, ulite_resume) 757 SET_RUNTIME_PM_OPS(ulite_runtime_suspend, 758 ulite_runtime_resume, NULL) 759 }; 760 761 #if defined(CONFIG_OF) 762 /* Match table for of_platform binding */ 763 static const struct of_device_id ulite_of_match[] = { 764 { .compatible = "xlnx,opb-uartlite-1.00.b", }, 765 { .compatible = "xlnx,xps-uartlite-1.00.a", }, 766 {} 767 }; 768 MODULE_DEVICE_TABLE(of, ulite_of_match); 769 #endif /* CONFIG_OF */ 770 771 static int ulite_probe(struct platform_device *pdev) 772 { 773 struct resource *res; 774 struct uartlite_data *pdata; 775 int irq, ret; 776 int id = pdev->id; 777 #ifdef CONFIG_OF 778 const __be32 *prop; 779 780 prop = of_get_property(pdev->dev.of_node, "port-number", NULL); 781 if (prop) 782 id = be32_to_cpup(prop); 783 #endif 784 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data), 785 GFP_KERNEL); 786 if (!pdata) 787 return -ENOMEM; 788 789 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 790 if (!res) 791 return -ENODEV; 792 793 irq = platform_get_irq(pdev, 0); 794 if (irq < 0) 795 return irq; 796 797 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 798 if (IS_ERR(pdata->clk)) { 799 if (PTR_ERR(pdata->clk) != -ENOENT) 800 return PTR_ERR(pdata->clk); 801 802 /* 803 * Clock framework support is optional, continue on 804 * anyways if we don't find a matching clock. 805 */ 806 pdata->clk = NULL; 807 } 808 809 ret = clk_prepare_enable(pdata->clk); 810 if (ret) { 811 dev_err(&pdev->dev, "Failed to prepare clock\n"); 812 return ret; 813 } 814 815 pm_runtime_use_autosuspend(&pdev->dev); 816 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 817 pm_runtime_set_active(&pdev->dev); 818 pm_runtime_enable(&pdev->dev); 819 820 if (!ulite_uart_driver.state) { 821 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n"); 822 ret = uart_register_driver(&ulite_uart_driver); 823 if (ret < 0) { 824 dev_err(&pdev->dev, "Failed to register driver\n"); 825 clk_disable_unprepare(pdata->clk); 826 return ret; 827 } 828 } 829 830 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata); 831 832 pm_runtime_mark_last_busy(&pdev->dev); 833 pm_runtime_put_autosuspend(&pdev->dev); 834 835 return ret; 836 } 837 838 static int ulite_remove(struct platform_device *pdev) 839 { 840 struct uart_port *port = dev_get_drvdata(&pdev->dev); 841 struct uartlite_data *pdata = port->private_data; 842 int rc; 843 844 clk_disable_unprepare(pdata->clk); 845 rc = ulite_release(&pdev->dev); 846 pm_runtime_disable(&pdev->dev); 847 pm_runtime_set_suspended(&pdev->dev); 848 pm_runtime_dont_use_autosuspend(&pdev->dev); 849 return rc; 850 } 851 852 /* work with hotplug and coldplug */ 853 MODULE_ALIAS("platform:uartlite"); 854 855 static struct platform_driver ulite_platform_driver = { 856 .probe = ulite_probe, 857 .remove = ulite_remove, 858 .driver = { 859 .name = "uartlite", 860 .of_match_table = of_match_ptr(ulite_of_match), 861 .pm = &ulite_pm_ops, 862 }, 863 }; 864 865 /* --------------------------------------------------------------------- 866 * Module setup/teardown 867 */ 868 869 static int __init ulite_init(void) 870 { 871 872 pr_debug("uartlite: calling platform_driver_register()\n"); 873 return platform_driver_register(&ulite_platform_driver); 874 } 875 876 static void __exit ulite_exit(void) 877 { 878 platform_driver_unregister(&ulite_platform_driver); 879 if (ulite_uart_driver.state) 880 uart_unregister_driver(&ulite_uart_driver); 881 } 882 883 module_init(ulite_init); 884 module_exit(ulite_exit); 885 886 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); 887 MODULE_DESCRIPTION("Xilinx uartlite serial driver"); 888 MODULE_LICENSE("GPL"); 889