1 /* 2 * Copyright (C) Maxime Coquelin 2015 3 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 4 * Gerald Baeza <gerald.baeza@st.com> 5 * License terms: GNU General Public License (GPL), version 2 6 * 7 * Inspired by st-asc.c from STMicroelectronics (c) 8 */ 9 10 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 11 #define SUPPORT_SYSRQ 12 #endif 13 14 #include <linux/clk.h> 15 #include <linux/console.h> 16 #include <linux/delay.h> 17 #include <linux/dma-direction.h> 18 #include <linux/dmaengine.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/irq.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "stm32-usart.h" 36 37 static void stm32_stop_tx(struct uart_port *port); 38 static void stm32_transmit_chars(struct uart_port *port); 39 40 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 41 { 42 return container_of(port, struct stm32_port, port); 43 } 44 45 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) 46 { 47 u32 val; 48 49 val = readl_relaxed(port->membase + reg); 50 val |= bits; 51 writel_relaxed(val, port->membase + reg); 52 } 53 54 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) 55 { 56 u32 val; 57 58 val = readl_relaxed(port->membase + reg); 59 val &= ~bits; 60 writel_relaxed(val, port->membase + reg); 61 } 62 63 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, 64 bool threaded) 65 { 66 struct stm32_port *stm32_port = to_stm32_port(port); 67 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 68 enum dma_status status; 69 struct dma_tx_state state; 70 71 *sr = readl_relaxed(port->membase + ofs->isr); 72 73 if (threaded && stm32_port->rx_ch) { 74 status = dmaengine_tx_status(stm32_port->rx_ch, 75 stm32_port->rx_ch->cookie, 76 &state); 77 if ((status == DMA_IN_PROGRESS) && 78 (*last_res != state.residue)) 79 return 1; 80 else 81 return 0; 82 } else if (*sr & USART_SR_RXNE) { 83 return 1; 84 } 85 return 0; 86 } 87 88 static unsigned long 89 stm32_get_char(struct uart_port *port, u32 *sr, int *last_res) 90 { 91 struct stm32_port *stm32_port = to_stm32_port(port); 92 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 93 unsigned long c; 94 95 if (stm32_port->rx_ch) { 96 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 97 if ((*last_res) == 0) 98 *last_res = RX_BUF_L; 99 return c; 100 } else { 101 return readl_relaxed(port->membase + ofs->rdr); 102 } 103 } 104 105 static void stm32_receive_chars(struct uart_port *port, bool threaded) 106 { 107 struct tty_port *tport = &port->state->port; 108 struct stm32_port *stm32_port = to_stm32_port(port); 109 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 110 unsigned long c; 111 u32 sr; 112 char flag; 113 static int last_res = RX_BUF_L; 114 115 if (port->irq_wake) 116 pm_wakeup_event(tport->tty->dev, 0); 117 118 while (stm32_pending_rx(port, &sr, &last_res, threaded)) { 119 sr |= USART_SR_DUMMY_RX; 120 c = stm32_get_char(port, &sr, &last_res); 121 flag = TTY_NORMAL; 122 port->icount.rx++; 123 124 if (sr & USART_SR_ERR_MASK) { 125 if (sr & USART_SR_LBD) { 126 port->icount.brk++; 127 if (uart_handle_break(port)) 128 continue; 129 } else if (sr & USART_SR_ORE) { 130 if (ofs->icr != UNDEF_REG) 131 writel_relaxed(USART_ICR_ORECF, 132 port->membase + 133 ofs->icr); 134 port->icount.overrun++; 135 } else if (sr & USART_SR_PE) { 136 port->icount.parity++; 137 } else if (sr & USART_SR_FE) { 138 port->icount.frame++; 139 } 140 141 sr &= port->read_status_mask; 142 143 if (sr & USART_SR_LBD) 144 flag = TTY_BREAK; 145 else if (sr & USART_SR_PE) 146 flag = TTY_PARITY; 147 else if (sr & USART_SR_FE) 148 flag = TTY_FRAME; 149 } 150 151 if (uart_handle_sysrq_char(port, c)) 152 continue; 153 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 154 } 155 156 spin_unlock(&port->lock); 157 tty_flip_buffer_push(tport); 158 spin_lock(&port->lock); 159 } 160 161 static void stm32_tx_dma_complete(void *arg) 162 { 163 struct uart_port *port = arg; 164 struct stm32_port *stm32port = to_stm32_port(port); 165 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 166 unsigned int isr; 167 int ret; 168 169 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 170 isr, 171 (isr & USART_SR_TC), 172 10, 100000); 173 174 if (ret) 175 dev_err(port->dev, "terminal count not set\n"); 176 177 if (ofs->icr == UNDEF_REG) 178 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 179 else 180 stm32_set_bits(port, ofs->icr, USART_CR_TC); 181 182 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 183 stm32port->tx_dma_busy = false; 184 185 /* Let's see if we have pending data to send */ 186 stm32_transmit_chars(port); 187 } 188 189 static void stm32_transmit_chars_pio(struct uart_port *port) 190 { 191 struct stm32_port *stm32_port = to_stm32_port(port); 192 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 193 struct circ_buf *xmit = &port->state->xmit; 194 unsigned int isr; 195 int ret; 196 197 if (stm32_port->tx_dma_busy) { 198 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 199 stm32_port->tx_dma_busy = false; 200 } 201 202 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 203 isr, 204 (isr & USART_SR_TXE), 205 10, 100); 206 207 if (ret) 208 dev_err(port->dev, "tx empty not set\n"); 209 210 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 211 212 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 213 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 214 port->icount.tx++; 215 } 216 217 static void stm32_transmit_chars_dma(struct uart_port *port) 218 { 219 struct stm32_port *stm32port = to_stm32_port(port); 220 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 221 struct circ_buf *xmit = &port->state->xmit; 222 struct dma_async_tx_descriptor *desc = NULL; 223 dma_cookie_t cookie; 224 unsigned int count, i; 225 226 if (stm32port->tx_dma_busy) 227 return; 228 229 stm32port->tx_dma_busy = true; 230 231 count = uart_circ_chars_pending(xmit); 232 233 if (count > TX_BUF_L) 234 count = TX_BUF_L; 235 236 if (xmit->tail < xmit->head) { 237 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 238 } else { 239 size_t one = UART_XMIT_SIZE - xmit->tail; 240 size_t two; 241 242 if (one > count) 243 one = count; 244 two = count - one; 245 246 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 247 if (two) 248 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 249 } 250 251 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 252 stm32port->tx_dma_buf, 253 count, 254 DMA_MEM_TO_DEV, 255 DMA_PREP_INTERRUPT); 256 257 if (!desc) { 258 for (i = count; i > 0; i--) 259 stm32_transmit_chars_pio(port); 260 return; 261 } 262 263 desc->callback = stm32_tx_dma_complete; 264 desc->callback_param = port; 265 266 /* Push current DMA TX transaction in the pending queue */ 267 cookie = dmaengine_submit(desc); 268 269 /* Issue pending DMA TX requests */ 270 dma_async_issue_pending(stm32port->tx_ch); 271 272 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 273 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 274 275 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 276 port->icount.tx += count; 277 } 278 279 static void stm32_transmit_chars(struct uart_port *port) 280 { 281 struct stm32_port *stm32_port = to_stm32_port(port); 282 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 283 struct circ_buf *xmit = &port->state->xmit; 284 285 if (port->x_char) { 286 if (stm32_port->tx_dma_busy) 287 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 288 writel_relaxed(port->x_char, port->membase + ofs->tdr); 289 port->x_char = 0; 290 port->icount.tx++; 291 if (stm32_port->tx_dma_busy) 292 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 293 return; 294 } 295 296 if (uart_tx_stopped(port)) { 297 stm32_stop_tx(port); 298 return; 299 } 300 301 if (uart_circ_empty(xmit)) { 302 stm32_stop_tx(port); 303 return; 304 } 305 306 if (stm32_port->tx_ch) 307 stm32_transmit_chars_dma(port); 308 else 309 stm32_transmit_chars_pio(port); 310 311 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 312 uart_write_wakeup(port); 313 314 if (uart_circ_empty(xmit)) 315 stm32_stop_tx(port); 316 } 317 318 static irqreturn_t stm32_interrupt(int irq, void *ptr) 319 { 320 struct uart_port *port = ptr; 321 struct stm32_port *stm32_port = to_stm32_port(port); 322 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 323 u32 sr; 324 325 spin_lock(&port->lock); 326 327 sr = readl_relaxed(port->membase + ofs->isr); 328 329 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 330 stm32_receive_chars(port, false); 331 332 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 333 stm32_transmit_chars(port); 334 335 spin_unlock(&port->lock); 336 337 if (stm32_port->rx_ch) 338 return IRQ_WAKE_THREAD; 339 else 340 return IRQ_HANDLED; 341 } 342 343 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr) 344 { 345 struct uart_port *port = ptr; 346 struct stm32_port *stm32_port = to_stm32_port(port); 347 348 spin_lock(&port->lock); 349 350 if (stm32_port->rx_ch) 351 stm32_receive_chars(port, true); 352 353 spin_unlock(&port->lock); 354 355 return IRQ_HANDLED; 356 } 357 358 static unsigned int stm32_tx_empty(struct uart_port *port) 359 { 360 struct stm32_port *stm32_port = to_stm32_port(port); 361 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 362 363 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 364 } 365 366 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) 367 { 368 struct stm32_port *stm32_port = to_stm32_port(port); 369 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 370 371 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 372 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); 373 else 374 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 375 } 376 377 static unsigned int stm32_get_mctrl(struct uart_port *port) 378 { 379 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 380 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 381 } 382 383 /* Transmit stop */ 384 static void stm32_stop_tx(struct uart_port *port) 385 { 386 struct stm32_port *stm32_port = to_stm32_port(port); 387 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 388 389 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 390 } 391 392 /* There are probably characters waiting to be transmitted. */ 393 static void stm32_start_tx(struct uart_port *port) 394 { 395 struct circ_buf *xmit = &port->state->xmit; 396 397 if (uart_circ_empty(xmit)) 398 return; 399 400 stm32_transmit_chars(port); 401 } 402 403 /* Throttle the remote when input buffer is about to overflow. */ 404 static void stm32_throttle(struct uart_port *port) 405 { 406 struct stm32_port *stm32_port = to_stm32_port(port); 407 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 408 unsigned long flags; 409 410 spin_lock_irqsave(&port->lock, flags); 411 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 412 spin_unlock_irqrestore(&port->lock, flags); 413 } 414 415 /* Unthrottle the remote, the input buffer can now accept data. */ 416 static void stm32_unthrottle(struct uart_port *port) 417 { 418 struct stm32_port *stm32_port = to_stm32_port(port); 419 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 420 unsigned long flags; 421 422 spin_lock_irqsave(&port->lock, flags); 423 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE); 424 spin_unlock_irqrestore(&port->lock, flags); 425 } 426 427 /* Receive stop */ 428 static void stm32_stop_rx(struct uart_port *port) 429 { 430 struct stm32_port *stm32_port = to_stm32_port(port); 431 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 432 433 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE); 434 } 435 436 /* Handle breaks - ignored by us */ 437 static void stm32_break_ctl(struct uart_port *port, int break_state) 438 { 439 } 440 441 static int stm32_startup(struct uart_port *port) 442 { 443 struct stm32_port *stm32_port = to_stm32_port(port); 444 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 445 const char *name = to_platform_device(port->dev)->name; 446 u32 val; 447 int ret; 448 449 ret = request_threaded_irq(port->irq, stm32_interrupt, 450 stm32_threaded_interrupt, 451 IRQF_NO_SUSPEND, name, port); 452 if (ret) 453 return ret; 454 455 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 456 stm32_set_bits(port, ofs->cr1, val); 457 458 return 0; 459 } 460 461 static void stm32_shutdown(struct uart_port *port) 462 { 463 struct stm32_port *stm32_port = to_stm32_port(port); 464 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 465 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 466 u32 val; 467 468 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; 469 val |= BIT(cfg->uart_enable_bit); 470 stm32_clr_bits(port, ofs->cr1, val); 471 472 free_irq(port->irq, port); 473 } 474 475 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, 476 struct ktermios *old) 477 { 478 struct stm32_port *stm32_port = to_stm32_port(port); 479 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 480 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 481 unsigned int baud; 482 u32 usartdiv, mantissa, fraction, oversampling; 483 tcflag_t cflag = termios->c_cflag; 484 u32 cr1, cr2, cr3; 485 unsigned long flags; 486 487 if (!stm32_port->hw_flow_control) 488 cflag &= ~CRTSCTS; 489 490 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 491 492 spin_lock_irqsave(&port->lock, flags); 493 494 /* Stop serial port and reset value */ 495 writel_relaxed(0, port->membase + ofs->cr1); 496 497 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE; 498 cr1 |= BIT(cfg->uart_enable_bit); 499 cr2 = 0; 500 cr3 = 0; 501 502 if (cflag & CSTOPB) 503 cr2 |= USART_CR2_STOP_2B; 504 505 if (cflag & PARENB) { 506 cr1 |= USART_CR1_PCE; 507 if ((cflag & CSIZE) == CS8) { 508 if (cfg->has_7bits_data) 509 cr1 |= USART_CR1_M0; 510 else 511 cr1 |= USART_CR1_M; 512 } 513 } 514 515 if (cflag & PARODD) 516 cr1 |= USART_CR1_PS; 517 518 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 519 if (cflag & CRTSCTS) { 520 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 521 cr3 |= USART_CR3_CTSE; 522 } 523 524 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 525 526 /* 527 * The USART supports 16 or 8 times oversampling. 528 * By default we prefer 16 times oversampling, so that the receiver 529 * has a better tolerance to clock deviations. 530 * 8 times oversampling is only used to achieve higher speeds. 531 */ 532 if (usartdiv < 16) { 533 oversampling = 8; 534 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); 535 } else { 536 oversampling = 16; 537 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 538 } 539 540 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 541 fraction = usartdiv % oversampling; 542 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 543 544 uart_update_timeout(port, cflag, baud); 545 546 port->read_status_mask = USART_SR_ORE; 547 if (termios->c_iflag & INPCK) 548 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 549 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 550 port->read_status_mask |= USART_SR_LBD; 551 552 /* Characters to ignore */ 553 port->ignore_status_mask = 0; 554 if (termios->c_iflag & IGNPAR) 555 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 556 if (termios->c_iflag & IGNBRK) { 557 port->ignore_status_mask |= USART_SR_LBD; 558 /* 559 * If we're ignoring parity and break indicators, 560 * ignore overruns too (for real raw support). 561 */ 562 if (termios->c_iflag & IGNPAR) 563 port->ignore_status_mask |= USART_SR_ORE; 564 } 565 566 /* Ignore all characters if CREAD is not set */ 567 if ((termios->c_cflag & CREAD) == 0) 568 port->ignore_status_mask |= USART_SR_DUMMY_RX; 569 570 if (stm32_port->rx_ch) 571 cr3 |= USART_CR3_DMAR; 572 573 writel_relaxed(cr3, port->membase + ofs->cr3); 574 writel_relaxed(cr2, port->membase + ofs->cr2); 575 writel_relaxed(cr1, port->membase + ofs->cr1); 576 577 spin_unlock_irqrestore(&port->lock, flags); 578 } 579 580 static const char *stm32_type(struct uart_port *port) 581 { 582 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 583 } 584 585 static void stm32_release_port(struct uart_port *port) 586 { 587 } 588 589 static int stm32_request_port(struct uart_port *port) 590 { 591 return 0; 592 } 593 594 static void stm32_config_port(struct uart_port *port, int flags) 595 { 596 if (flags & UART_CONFIG_TYPE) 597 port->type = PORT_STM32; 598 } 599 600 static int 601 stm32_verify_port(struct uart_port *port, struct serial_struct *ser) 602 { 603 /* No user changeable parameters */ 604 return -EINVAL; 605 } 606 607 static void stm32_pm(struct uart_port *port, unsigned int state, 608 unsigned int oldstate) 609 { 610 struct stm32_port *stm32port = container_of(port, 611 struct stm32_port, port); 612 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 613 struct stm32_usart_config *cfg = &stm32port->info->cfg; 614 unsigned long flags = 0; 615 616 switch (state) { 617 case UART_PM_STATE_ON: 618 clk_prepare_enable(stm32port->clk); 619 break; 620 case UART_PM_STATE_OFF: 621 spin_lock_irqsave(&port->lock, flags); 622 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 623 spin_unlock_irqrestore(&port->lock, flags); 624 clk_disable_unprepare(stm32port->clk); 625 break; 626 } 627 } 628 629 static const struct uart_ops stm32_uart_ops = { 630 .tx_empty = stm32_tx_empty, 631 .set_mctrl = stm32_set_mctrl, 632 .get_mctrl = stm32_get_mctrl, 633 .stop_tx = stm32_stop_tx, 634 .start_tx = stm32_start_tx, 635 .throttle = stm32_throttle, 636 .unthrottle = stm32_unthrottle, 637 .stop_rx = stm32_stop_rx, 638 .break_ctl = stm32_break_ctl, 639 .startup = stm32_startup, 640 .shutdown = stm32_shutdown, 641 .set_termios = stm32_set_termios, 642 .pm = stm32_pm, 643 .type = stm32_type, 644 .release_port = stm32_release_port, 645 .request_port = stm32_request_port, 646 .config_port = stm32_config_port, 647 .verify_port = stm32_verify_port, 648 }; 649 650 static int stm32_init_port(struct stm32_port *stm32port, 651 struct platform_device *pdev) 652 { 653 struct uart_port *port = &stm32port->port; 654 struct resource *res; 655 int ret; 656 657 port->iotype = UPIO_MEM; 658 port->flags = UPF_BOOT_AUTOCONF; 659 port->ops = &stm32_uart_ops; 660 port->dev = &pdev->dev; 661 port->irq = platform_get_irq(pdev, 0); 662 663 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 664 port->membase = devm_ioremap_resource(&pdev->dev, res); 665 if (IS_ERR(port->membase)) 666 return PTR_ERR(port->membase); 667 port->mapbase = res->start; 668 669 spin_lock_init(&port->lock); 670 671 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 672 if (IS_ERR(stm32port->clk)) 673 return PTR_ERR(stm32port->clk); 674 675 /* Ensure that clk rate is correct by enabling the clk */ 676 ret = clk_prepare_enable(stm32port->clk); 677 if (ret) 678 return ret; 679 680 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 681 if (!stm32port->port.uartclk) 682 ret = -EINVAL; 683 684 return ret; 685 } 686 687 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) 688 { 689 struct device_node *np = pdev->dev.of_node; 690 int id; 691 692 if (!np) 693 return NULL; 694 695 id = of_alias_get_id(np, "serial"); 696 if (id < 0) 697 id = 0; 698 699 if (WARN_ON(id >= STM32_MAX_PORTS)) 700 return NULL; 701 702 stm32_ports[id].hw_flow_control = of_property_read_bool(np, 703 "st,hw-flow-ctrl"); 704 stm32_ports[id].port.line = id; 705 return &stm32_ports[id]; 706 } 707 708 #ifdef CONFIG_OF 709 static const struct of_device_id stm32_match[] = { 710 { .compatible = "st,stm32-usart", .data = &stm32f4_info}, 711 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 712 { .compatible = "st,stm32f7-usart", .data = &stm32f7_info}, 713 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 714 {}, 715 }; 716 717 MODULE_DEVICE_TABLE(of, stm32_match); 718 #endif 719 720 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port, 721 struct platform_device *pdev) 722 { 723 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 724 struct uart_port *port = &stm32port->port; 725 struct device *dev = &pdev->dev; 726 struct dma_slave_config config; 727 struct dma_async_tx_descriptor *desc = NULL; 728 dma_cookie_t cookie; 729 int ret; 730 731 /* Request DMA RX channel */ 732 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 733 if (!stm32port->rx_ch) { 734 dev_info(dev, "rx dma alloc failed\n"); 735 return -ENODEV; 736 } 737 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 738 &stm32port->rx_dma_buf, 739 GFP_KERNEL); 740 if (!stm32port->rx_buf) { 741 ret = -ENOMEM; 742 goto alloc_err; 743 } 744 745 /* Configure DMA channel */ 746 memset(&config, 0, sizeof(config)); 747 config.src_addr = port->mapbase + ofs->rdr; 748 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 749 750 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 751 if (ret < 0) { 752 dev_err(dev, "rx dma channel config failed\n"); 753 ret = -ENODEV; 754 goto config_err; 755 } 756 757 /* Prepare a DMA cyclic transaction */ 758 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 759 stm32port->rx_dma_buf, 760 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 761 DMA_PREP_INTERRUPT); 762 if (!desc) { 763 dev_err(dev, "rx dma prep cyclic failed\n"); 764 ret = -ENODEV; 765 goto config_err; 766 } 767 768 /* No callback as dma buffer is drained on usart interrupt */ 769 desc->callback = NULL; 770 desc->callback_param = NULL; 771 772 /* Push current DMA transaction in the pending queue */ 773 cookie = dmaengine_submit(desc); 774 775 /* Issue pending DMA requests */ 776 dma_async_issue_pending(stm32port->rx_ch); 777 778 return 0; 779 780 config_err: 781 dma_free_coherent(&pdev->dev, 782 RX_BUF_L, stm32port->rx_buf, 783 stm32port->rx_dma_buf); 784 785 alloc_err: 786 dma_release_channel(stm32port->rx_ch); 787 stm32port->rx_ch = NULL; 788 789 return ret; 790 } 791 792 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port, 793 struct platform_device *pdev) 794 { 795 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 796 struct uart_port *port = &stm32port->port; 797 struct device *dev = &pdev->dev; 798 struct dma_slave_config config; 799 int ret; 800 801 stm32port->tx_dma_busy = false; 802 803 /* Request DMA TX channel */ 804 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 805 if (!stm32port->tx_ch) { 806 dev_info(dev, "tx dma alloc failed\n"); 807 return -ENODEV; 808 } 809 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 810 &stm32port->tx_dma_buf, 811 GFP_KERNEL); 812 if (!stm32port->tx_buf) { 813 ret = -ENOMEM; 814 goto alloc_err; 815 } 816 817 /* Configure DMA channel */ 818 memset(&config, 0, sizeof(config)); 819 config.dst_addr = port->mapbase + ofs->tdr; 820 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 821 822 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 823 if (ret < 0) { 824 dev_err(dev, "tx dma channel config failed\n"); 825 ret = -ENODEV; 826 goto config_err; 827 } 828 829 return 0; 830 831 config_err: 832 dma_free_coherent(&pdev->dev, 833 TX_BUF_L, stm32port->tx_buf, 834 stm32port->tx_dma_buf); 835 836 alloc_err: 837 dma_release_channel(stm32port->tx_ch); 838 stm32port->tx_ch = NULL; 839 840 return ret; 841 } 842 843 static int stm32_serial_probe(struct platform_device *pdev) 844 { 845 const struct of_device_id *match; 846 struct stm32_port *stm32port; 847 int ret; 848 849 stm32port = stm32_of_get_stm32_port(pdev); 850 if (!stm32port) 851 return -ENODEV; 852 853 match = of_match_device(stm32_match, &pdev->dev); 854 if (match && match->data) 855 stm32port->info = (struct stm32_usart_info *)match->data; 856 else 857 return -EINVAL; 858 859 ret = stm32_init_port(stm32port, pdev); 860 if (ret) 861 return ret; 862 863 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 864 if (ret) 865 return ret; 866 867 ret = stm32_of_dma_rx_probe(stm32port, pdev); 868 if (ret) 869 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 870 871 ret = stm32_of_dma_tx_probe(stm32port, pdev); 872 if (ret) 873 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 874 875 platform_set_drvdata(pdev, &stm32port->port); 876 877 return 0; 878 } 879 880 static int stm32_serial_remove(struct platform_device *pdev) 881 { 882 struct uart_port *port = platform_get_drvdata(pdev); 883 struct stm32_port *stm32_port = to_stm32_port(port); 884 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 885 886 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 887 888 if (stm32_port->rx_ch) 889 dma_release_channel(stm32_port->rx_ch); 890 891 if (stm32_port->rx_dma_buf) 892 dma_free_coherent(&pdev->dev, 893 RX_BUF_L, stm32_port->rx_buf, 894 stm32_port->rx_dma_buf); 895 896 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 897 898 if (stm32_port->tx_ch) 899 dma_release_channel(stm32_port->tx_ch); 900 901 if (stm32_port->tx_dma_buf) 902 dma_free_coherent(&pdev->dev, 903 TX_BUF_L, stm32_port->tx_buf, 904 stm32_port->tx_dma_buf); 905 906 clk_disable_unprepare(stm32_port->clk); 907 908 return uart_remove_one_port(&stm32_usart_driver, port); 909 } 910 911 912 #ifdef CONFIG_SERIAL_STM32_CONSOLE 913 static void stm32_console_putchar(struct uart_port *port, int ch) 914 { 915 struct stm32_port *stm32_port = to_stm32_port(port); 916 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 917 918 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 919 cpu_relax(); 920 921 writel_relaxed(ch, port->membase + ofs->tdr); 922 } 923 924 static void stm32_console_write(struct console *co, const char *s, unsigned cnt) 925 { 926 struct uart_port *port = &stm32_ports[co->index].port; 927 struct stm32_port *stm32_port = to_stm32_port(port); 928 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 929 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 930 unsigned long flags; 931 u32 old_cr1, new_cr1; 932 int locked = 1; 933 934 local_irq_save(flags); 935 if (port->sysrq) 936 locked = 0; 937 else if (oops_in_progress) 938 locked = spin_trylock(&port->lock); 939 else 940 spin_lock(&port->lock); 941 942 /* Save and disable interrupts, enable the transmitter */ 943 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 944 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 945 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 946 writel_relaxed(new_cr1, port->membase + ofs->cr1); 947 948 uart_console_write(port, s, cnt, stm32_console_putchar); 949 950 /* Restore interrupt state */ 951 writel_relaxed(old_cr1, port->membase + ofs->cr1); 952 953 if (locked) 954 spin_unlock(&port->lock); 955 local_irq_restore(flags); 956 } 957 958 static int stm32_console_setup(struct console *co, char *options) 959 { 960 struct stm32_port *stm32port; 961 int baud = 9600; 962 int bits = 8; 963 int parity = 'n'; 964 int flow = 'n'; 965 966 if (co->index >= STM32_MAX_PORTS) 967 return -ENODEV; 968 969 stm32port = &stm32_ports[co->index]; 970 971 /* 972 * This driver does not support early console initialization 973 * (use ARM early printk support instead), so we only expect 974 * this to be called during the uart port registration when the 975 * driver gets probed and the port should be mapped at that point. 976 */ 977 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) 978 return -ENXIO; 979 980 if (options) 981 uart_parse_options(options, &baud, &parity, &bits, &flow); 982 983 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 984 } 985 986 static struct console stm32_console = { 987 .name = STM32_SERIAL_NAME, 988 .device = uart_console_device, 989 .write = stm32_console_write, 990 .setup = stm32_console_setup, 991 .flags = CON_PRINTBUFFER, 992 .index = -1, 993 .data = &stm32_usart_driver, 994 }; 995 996 #define STM32_SERIAL_CONSOLE (&stm32_console) 997 998 #else 999 #define STM32_SERIAL_CONSOLE NULL 1000 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1001 1002 static struct uart_driver stm32_usart_driver = { 1003 .driver_name = DRIVER_NAME, 1004 .dev_name = STM32_SERIAL_NAME, 1005 .major = 0, 1006 .minor = 0, 1007 .nr = STM32_MAX_PORTS, 1008 .cons = STM32_SERIAL_CONSOLE, 1009 }; 1010 1011 static struct platform_driver stm32_serial_driver = { 1012 .probe = stm32_serial_probe, 1013 .remove = stm32_serial_remove, 1014 .driver = { 1015 .name = DRIVER_NAME, 1016 .of_match_table = of_match_ptr(stm32_match), 1017 }, 1018 }; 1019 1020 static int __init usart_init(void) 1021 { 1022 static char banner[] __initdata = "STM32 USART driver initialized"; 1023 int ret; 1024 1025 pr_info("%s\n", banner); 1026 1027 ret = uart_register_driver(&stm32_usart_driver); 1028 if (ret) 1029 return ret; 1030 1031 ret = platform_driver_register(&stm32_serial_driver); 1032 if (ret) 1033 uart_unregister_driver(&stm32_usart_driver); 1034 1035 return ret; 1036 } 1037 1038 static void __exit usart_exit(void) 1039 { 1040 platform_driver_unregister(&stm32_serial_driver); 1041 uart_unregister_driver(&stm32_usart_driver); 1042 } 1043 1044 module_init(usart_init); 1045 module_exit(usart_exit); 1046 1047 MODULE_ALIAS("platform:" DRIVER_NAME); 1048 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1049 MODULE_LICENSE("GPL v2"); 1050