1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/console.h> 15 #include <linux/delay.h> 16 #include <linux/dma-direction.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/irq.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/of_platform.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/pm_wakeirq.h> 29 #include <linux/serial_core.h> 30 #include <linux/serial.h> 31 #include <linux/spinlock.h> 32 #include <linux/sysrq.h> 33 #include <linux/tty_flip.h> 34 #include <linux/tty.h> 35 36 #include "serial_mctrl_gpio.h" 37 #include "stm32-usart.h" 38 39 40 /* Register offsets */ 41 static struct stm32_usart_info __maybe_unused stm32f4_info = { 42 .ofs = { 43 .isr = 0x00, 44 .rdr = 0x04, 45 .tdr = 0x04, 46 .brr = 0x08, 47 .cr1 = 0x0c, 48 .cr2 = 0x10, 49 .cr3 = 0x14, 50 .gtpr = 0x18, 51 .rtor = UNDEF_REG, 52 .rqr = UNDEF_REG, 53 .icr = UNDEF_REG, 54 .presc = UNDEF_REG, 55 .hwcfgr1 = UNDEF_REG, 56 }, 57 .cfg = { 58 .uart_enable_bit = 13, 59 .has_7bits_data = false, 60 } 61 }; 62 63 static struct stm32_usart_info __maybe_unused stm32f7_info = { 64 .ofs = { 65 .cr1 = 0x00, 66 .cr2 = 0x04, 67 .cr3 = 0x08, 68 .brr = 0x0c, 69 .gtpr = 0x10, 70 .rtor = 0x14, 71 .rqr = 0x18, 72 .isr = 0x1c, 73 .icr = 0x20, 74 .rdr = 0x24, 75 .tdr = 0x28, 76 .presc = UNDEF_REG, 77 .hwcfgr1 = UNDEF_REG, 78 }, 79 .cfg = { 80 .uart_enable_bit = 0, 81 .has_7bits_data = true, 82 .has_swap = true, 83 } 84 }; 85 86 static struct stm32_usart_info __maybe_unused stm32h7_info = { 87 .ofs = { 88 .cr1 = 0x00, 89 .cr2 = 0x04, 90 .cr3 = 0x08, 91 .brr = 0x0c, 92 .gtpr = 0x10, 93 .rtor = 0x14, 94 .rqr = 0x18, 95 .isr = 0x1c, 96 .icr = 0x20, 97 .rdr = 0x24, 98 .tdr = 0x28, 99 .presc = 0x2c, 100 .hwcfgr1 = 0x3f0, 101 }, 102 .cfg = { 103 .uart_enable_bit = 0, 104 .has_7bits_data = true, 105 .has_swap = true, 106 .has_wakeup = true, 107 .has_fifo = true, 108 } 109 }; 110 111 static void stm32_usart_stop_tx(struct uart_port *port); 112 static void stm32_usart_transmit_chars(struct uart_port *port); 113 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch); 114 115 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 116 { 117 return container_of(port, struct stm32_port, port); 118 } 119 120 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 121 { 122 u32 val; 123 124 val = readl_relaxed(port->membase + reg); 125 val |= bits; 126 writel_relaxed(val, port->membase + reg); 127 } 128 129 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 130 { 131 u32 val; 132 133 val = readl_relaxed(port->membase + reg); 134 val &= ~bits; 135 writel_relaxed(val, port->membase + reg); 136 } 137 138 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 139 { 140 struct stm32_port *stm32_port = to_stm32_port(port); 141 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 142 143 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) 144 return TIOCSER_TEMT; 145 146 return 0; 147 } 148 149 static void stm32_usart_rs485_rts_enable(struct uart_port *port) 150 { 151 struct stm32_port *stm32_port = to_stm32_port(port); 152 struct serial_rs485 *rs485conf = &port->rs485; 153 154 if (stm32_port->hw_flow_control || 155 !(rs485conf->flags & SER_RS485_ENABLED)) 156 return; 157 158 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 159 mctrl_gpio_set(stm32_port->gpios, 160 stm32_port->port.mctrl | TIOCM_RTS); 161 } else { 162 mctrl_gpio_set(stm32_port->gpios, 163 stm32_port->port.mctrl & ~TIOCM_RTS); 164 } 165 } 166 167 static void stm32_usart_rs485_rts_disable(struct uart_port *port) 168 { 169 struct stm32_port *stm32_port = to_stm32_port(port); 170 struct serial_rs485 *rs485conf = &port->rs485; 171 172 if (stm32_port->hw_flow_control || 173 !(rs485conf->flags & SER_RS485_ENABLED)) 174 return; 175 176 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 177 mctrl_gpio_set(stm32_port->gpios, 178 stm32_port->port.mctrl & ~TIOCM_RTS); 179 } else { 180 mctrl_gpio_set(stm32_port->gpios, 181 stm32_port->port.mctrl | TIOCM_RTS); 182 } 183 } 184 185 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 186 u32 delay_DDE, u32 baud) 187 { 188 u32 rs485_deat_dedt; 189 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 190 bool over8; 191 192 *cr3 |= USART_CR3_DEM; 193 over8 = *cr1 & USART_CR1_OVER8; 194 195 *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 196 197 if (over8) 198 rs485_deat_dedt = delay_ADE * baud * 8; 199 else 200 rs485_deat_dedt = delay_ADE * baud * 16; 201 202 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 203 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 204 rs485_deat_dedt_max : rs485_deat_dedt; 205 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 206 USART_CR1_DEAT_MASK; 207 *cr1 |= rs485_deat_dedt; 208 209 if (over8) 210 rs485_deat_dedt = delay_DDE * baud * 8; 211 else 212 rs485_deat_dedt = delay_DDE * baud * 16; 213 214 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 215 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 216 rs485_deat_dedt_max : rs485_deat_dedt; 217 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 218 USART_CR1_DEDT_MASK; 219 *cr1 |= rs485_deat_dedt; 220 } 221 222 static int stm32_usart_config_rs485(struct uart_port *port, struct ktermios *termios, 223 struct serial_rs485 *rs485conf) 224 { 225 struct stm32_port *stm32_port = to_stm32_port(port); 226 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 227 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 228 u32 usartdiv, baud, cr1, cr3; 229 bool over8; 230 231 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 232 233 if (rs485conf->flags & SER_RS485_ENABLED) { 234 cr1 = readl_relaxed(port->membase + ofs->cr1); 235 cr3 = readl_relaxed(port->membase + ofs->cr3); 236 usartdiv = readl_relaxed(port->membase + ofs->brr); 237 usartdiv = usartdiv & GENMASK(15, 0); 238 over8 = cr1 & USART_CR1_OVER8; 239 240 if (over8) 241 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 242 << USART_BRR_04_R_SHIFT; 243 244 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 245 stm32_usart_config_reg_rs485(&cr1, &cr3, 246 rs485conf->delay_rts_before_send, 247 rs485conf->delay_rts_after_send, 248 baud); 249 250 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) 251 cr3 &= ~USART_CR3_DEP; 252 else 253 cr3 |= USART_CR3_DEP; 254 255 writel_relaxed(cr3, port->membase + ofs->cr3); 256 writel_relaxed(cr1, port->membase + ofs->cr1); 257 258 if (!port->rs485_rx_during_tx_gpio) 259 rs485conf->flags |= SER_RS485_RX_DURING_TX; 260 261 } else { 262 stm32_usart_clr_bits(port, ofs->cr3, 263 USART_CR3_DEM | USART_CR3_DEP); 264 stm32_usart_clr_bits(port, ofs->cr1, 265 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 266 } 267 268 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 269 270 /* Adjust RTS polarity in case it's driven in software */ 271 if (stm32_usart_tx_empty(port)) 272 stm32_usart_rs485_rts_disable(port); 273 else 274 stm32_usart_rs485_rts_enable(port); 275 276 return 0; 277 } 278 279 static int stm32_usart_init_rs485(struct uart_port *port, 280 struct platform_device *pdev) 281 { 282 struct serial_rs485 *rs485conf = &port->rs485; 283 284 rs485conf->flags = 0; 285 rs485conf->delay_rts_before_send = 0; 286 rs485conf->delay_rts_after_send = 0; 287 288 if (!pdev->dev.of_node) 289 return -ENODEV; 290 291 return uart_get_rs485_mode(port); 292 } 293 294 static bool stm32_usart_rx_dma_started(struct stm32_port *stm32_port) 295 { 296 return stm32_port->rx_ch ? stm32_port->rx_dma_busy : false; 297 } 298 299 static void stm32_usart_rx_dma_terminate(struct stm32_port *stm32_port) 300 { 301 dmaengine_terminate_async(stm32_port->rx_ch); 302 stm32_port->rx_dma_busy = false; 303 } 304 305 static int stm32_usart_dma_pause_resume(struct stm32_port *stm32_port, 306 struct dma_chan *chan, 307 enum dma_status expected_status, 308 int dmaengine_pause_or_resume(struct dma_chan *), 309 bool stm32_usart_xx_dma_started(struct stm32_port *), 310 void stm32_usart_xx_dma_terminate(struct stm32_port *)) 311 { 312 struct uart_port *port = &stm32_port->port; 313 enum dma_status dma_status; 314 int ret; 315 316 if (!stm32_usart_xx_dma_started(stm32_port)) 317 return -EPERM; 318 319 dma_status = dmaengine_tx_status(chan, chan->cookie, NULL); 320 if (dma_status != expected_status) 321 return -EAGAIN; 322 323 ret = dmaengine_pause_or_resume(chan); 324 if (ret) { 325 dev_err(port->dev, "DMA failed with error code: %d\n", ret); 326 stm32_usart_xx_dma_terminate(stm32_port); 327 } 328 return ret; 329 } 330 331 static int stm32_usart_rx_dma_pause(struct stm32_port *stm32_port) 332 { 333 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch, 334 DMA_IN_PROGRESS, dmaengine_pause, 335 stm32_usart_rx_dma_started, 336 stm32_usart_rx_dma_terminate); 337 } 338 339 static int stm32_usart_rx_dma_resume(struct stm32_port *stm32_port) 340 { 341 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch, 342 DMA_PAUSED, dmaengine_resume, 343 stm32_usart_rx_dma_started, 344 stm32_usart_rx_dma_terminate); 345 } 346 347 /* Return true when data is pending (in pio mode), and false when no data is pending. */ 348 static bool stm32_usart_pending_rx_pio(struct uart_port *port, u32 *sr) 349 { 350 struct stm32_port *stm32_port = to_stm32_port(port); 351 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 352 353 *sr = readl_relaxed(port->membase + ofs->isr); 354 /* Get pending characters in RDR or FIFO */ 355 if (*sr & USART_SR_RXNE) { 356 /* Get all pending characters from the RDR or the FIFO when using interrupts */ 357 if (!stm32_usart_rx_dma_started(stm32_port)) 358 return true; 359 360 /* Handle only RX data errors when using DMA */ 361 if (*sr & USART_SR_ERR_MASK) 362 return true; 363 } 364 365 return false; 366 } 367 368 static u8 stm32_usart_get_char_pio(struct uart_port *port) 369 { 370 struct stm32_port *stm32_port = to_stm32_port(port); 371 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 372 unsigned long c; 373 374 c = readl_relaxed(port->membase + ofs->rdr); 375 /* Apply RDR data mask */ 376 c &= stm32_port->rdr_mask; 377 378 return c; 379 } 380 381 static unsigned int stm32_usart_receive_chars_pio(struct uart_port *port) 382 { 383 struct stm32_port *stm32_port = to_stm32_port(port); 384 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 385 unsigned int size = 0; 386 u32 sr; 387 u8 c, flag; 388 389 while (stm32_usart_pending_rx_pio(port, &sr)) { 390 sr |= USART_SR_DUMMY_RX; 391 flag = TTY_NORMAL; 392 393 /* 394 * Status bits has to be cleared before reading the RDR: 395 * In FIFO mode, reading the RDR will pop the next data 396 * (if any) along with its status bits into the SR. 397 * Not doing so leads to misalignement between RDR and SR, 398 * and clear status bits of the next rx data. 399 * 400 * Clear errors flags for stm32f7 and stm32h7 compatible 401 * devices. On stm32f4 compatible devices, the error bit is 402 * cleared by the sequence [read SR - read DR]. 403 */ 404 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 405 writel_relaxed(sr & USART_SR_ERR_MASK, 406 port->membase + ofs->icr); 407 408 c = stm32_usart_get_char_pio(port); 409 port->icount.rx++; 410 size++; 411 if (sr & USART_SR_ERR_MASK) { 412 if (sr & USART_SR_ORE) { 413 port->icount.overrun++; 414 } else if (sr & USART_SR_PE) { 415 port->icount.parity++; 416 } else if (sr & USART_SR_FE) { 417 /* Break detection if character is null */ 418 if (!c) { 419 port->icount.brk++; 420 if (uart_handle_break(port)) 421 continue; 422 } else { 423 port->icount.frame++; 424 } 425 } 426 427 sr &= port->read_status_mask; 428 429 if (sr & USART_SR_PE) { 430 flag = TTY_PARITY; 431 } else if (sr & USART_SR_FE) { 432 if (!c) 433 flag = TTY_BREAK; 434 else 435 flag = TTY_FRAME; 436 } 437 } 438 439 if (uart_prepare_sysrq_char(port, c)) 440 continue; 441 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 442 } 443 444 return size; 445 } 446 447 static void stm32_usart_push_buffer_dma(struct uart_port *port, unsigned int dma_size) 448 { 449 struct stm32_port *stm32_port = to_stm32_port(port); 450 struct tty_port *ttyport = &stm32_port->port.state->port; 451 unsigned char *dma_start; 452 int dma_count, i; 453 454 dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res); 455 456 /* 457 * Apply rdr_mask on buffer in order to mask parity bit. 458 * This loop is useless in cs8 mode because DMA copies only 459 * 8 bits and already ignores parity bit. 460 */ 461 if (!(stm32_port->rdr_mask == (BIT(8) - 1))) 462 for (i = 0; i < dma_size; i++) 463 *(dma_start + i) &= stm32_port->rdr_mask; 464 465 dma_count = tty_insert_flip_string(ttyport, dma_start, dma_size); 466 port->icount.rx += dma_count; 467 if (dma_count != dma_size) 468 port->icount.buf_overrun++; 469 stm32_port->last_res -= dma_count; 470 if (stm32_port->last_res == 0) 471 stm32_port->last_res = RX_BUF_L; 472 } 473 474 static unsigned int stm32_usart_receive_chars_dma(struct uart_port *port) 475 { 476 struct stm32_port *stm32_port = to_stm32_port(port); 477 unsigned int dma_size, size = 0; 478 479 /* DMA buffer is configured in cyclic mode and handles the rollback of the buffer. */ 480 if (stm32_port->rx_dma_state.residue > stm32_port->last_res) { 481 /* Conditional first part: from last_res to end of DMA buffer */ 482 dma_size = stm32_port->last_res; 483 stm32_usart_push_buffer_dma(port, dma_size); 484 size = dma_size; 485 } 486 487 dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue; 488 stm32_usart_push_buffer_dma(port, dma_size); 489 size += dma_size; 490 491 return size; 492 } 493 494 static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force_dma_flush) 495 { 496 struct stm32_port *stm32_port = to_stm32_port(port); 497 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 498 enum dma_status rx_dma_status; 499 u32 sr; 500 unsigned int size = 0; 501 502 if (stm32_usart_rx_dma_started(stm32_port) || force_dma_flush) { 503 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, 504 stm32_port->rx_ch->cookie, 505 &stm32_port->rx_dma_state); 506 if (rx_dma_status == DMA_IN_PROGRESS || 507 rx_dma_status == DMA_PAUSED) { 508 /* Empty DMA buffer */ 509 size = stm32_usart_receive_chars_dma(port); 510 sr = readl_relaxed(port->membase + ofs->isr); 511 if (sr & USART_SR_ERR_MASK) { 512 /* Disable DMA request line */ 513 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 514 515 /* Switch to PIO mode to handle the errors */ 516 size += stm32_usart_receive_chars_pio(port); 517 518 /* Switch back to DMA mode */ 519 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); 520 } 521 } else { 522 /* Disable RX DMA */ 523 stm32_usart_rx_dma_terminate(stm32_port); 524 /* Fall back to interrupt mode */ 525 dev_dbg(port->dev, "DMA error, fallback to irq mode\n"); 526 size = stm32_usart_receive_chars_pio(port); 527 } 528 } else { 529 size = stm32_usart_receive_chars_pio(port); 530 } 531 532 return size; 533 } 534 535 static void stm32_usart_rx_dma_complete(void *arg) 536 { 537 struct uart_port *port = arg; 538 struct tty_port *tport = &port->state->port; 539 unsigned int size; 540 unsigned long flags; 541 542 uart_port_lock_irqsave(port, &flags); 543 size = stm32_usart_receive_chars(port, false); 544 uart_unlock_and_check_sysrq_irqrestore(port, flags); 545 if (size) 546 tty_flip_buffer_push(tport); 547 } 548 549 static int stm32_usart_rx_dma_start_or_resume(struct uart_port *port) 550 { 551 struct stm32_port *stm32_port = to_stm32_port(port); 552 struct dma_async_tx_descriptor *desc; 553 enum dma_status rx_dma_status; 554 int ret; 555 556 if (stm32_port->throttled) 557 return 0; 558 559 if (stm32_port->rx_dma_busy) { 560 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, 561 stm32_port->rx_ch->cookie, 562 NULL); 563 if (rx_dma_status == DMA_IN_PROGRESS) 564 return 0; 565 566 if (rx_dma_status == DMA_PAUSED && !stm32_usart_rx_dma_resume(stm32_port)) 567 return 0; 568 569 dev_err(port->dev, "DMA failed : status error.\n"); 570 stm32_usart_rx_dma_terminate(stm32_port); 571 } 572 573 stm32_port->rx_dma_busy = true; 574 575 stm32_port->last_res = RX_BUF_L; 576 /* Prepare a DMA cyclic transaction */ 577 desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch, 578 stm32_port->rx_dma_buf, 579 RX_BUF_L, RX_BUF_P, 580 DMA_DEV_TO_MEM, 581 DMA_PREP_INTERRUPT); 582 if (!desc) { 583 dev_err(port->dev, "rx dma prep cyclic failed\n"); 584 stm32_port->rx_dma_busy = false; 585 return -ENODEV; 586 } 587 588 desc->callback = stm32_usart_rx_dma_complete; 589 desc->callback_param = port; 590 591 /* Push current DMA transaction in the pending queue */ 592 ret = dma_submit_error(dmaengine_submit(desc)); 593 if (ret) { 594 dmaengine_terminate_sync(stm32_port->rx_ch); 595 stm32_port->rx_dma_busy = false; 596 return ret; 597 } 598 599 /* Issue pending DMA requests */ 600 dma_async_issue_pending(stm32_port->rx_ch); 601 602 return 0; 603 } 604 605 static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port) 606 { 607 dmaengine_terminate_async(stm32_port->tx_ch); 608 stm32_port->tx_dma_busy = false; 609 } 610 611 static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port) 612 { 613 /* 614 * We cannot use the function "dmaengine_tx_status" to know the 615 * status of DMA. This function does not show if the "dma complete" 616 * callback of the DMA transaction has been called. So we prefer 617 * to use "tx_dma_busy" flag to prevent dual DMA transaction at the 618 * same time. 619 */ 620 return stm32_port->tx_dma_busy; 621 } 622 623 static int stm32_usart_tx_dma_pause(struct stm32_port *stm32_port) 624 { 625 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch, 626 DMA_IN_PROGRESS, dmaengine_pause, 627 stm32_usart_tx_dma_started, 628 stm32_usart_tx_dma_terminate); 629 } 630 631 static int stm32_usart_tx_dma_resume(struct stm32_port *stm32_port) 632 { 633 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch, 634 DMA_PAUSED, dmaengine_resume, 635 stm32_usart_tx_dma_started, 636 stm32_usart_tx_dma_terminate); 637 } 638 639 static void stm32_usart_tx_dma_complete(void *arg) 640 { 641 struct uart_port *port = arg; 642 struct stm32_port *stm32port = to_stm32_port(port); 643 unsigned long flags; 644 645 stm32_usart_tx_dma_terminate(stm32port); 646 647 /* Let's see if we have pending data to send */ 648 uart_port_lock_irqsave(port, &flags); 649 stm32_usart_transmit_chars(port); 650 uart_port_unlock_irqrestore(port, flags); 651 } 652 653 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 654 { 655 struct stm32_port *stm32_port = to_stm32_port(port); 656 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 657 658 /* 659 * Enables TX FIFO threashold irq when FIFO is enabled, 660 * or TX empty irq when FIFO is disabled 661 */ 662 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) 663 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 664 else 665 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 666 } 667 668 static void stm32_usart_tc_interrupt_enable(struct uart_port *port) 669 { 670 struct stm32_port *stm32_port = to_stm32_port(port); 671 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 672 673 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE); 674 } 675 676 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 677 { 678 struct stm32_port *stm32_port = to_stm32_port(port); 679 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 680 681 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) 682 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 683 else 684 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 685 } 686 687 static void stm32_usart_tc_interrupt_disable(struct uart_port *port) 688 { 689 struct stm32_port *stm32_port = to_stm32_port(port); 690 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 691 692 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE); 693 } 694 695 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 696 { 697 struct stm32_port *stm32_port = to_stm32_port(port); 698 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 699 struct tty_port *tport = &port->state->port; 700 701 while (1) { 702 unsigned char ch; 703 704 /* Check that TDR is empty before filling FIFO */ 705 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 706 break; 707 708 if (!uart_fifo_get(port, &ch)) 709 break; 710 711 writel_relaxed(ch, port->membase + ofs->tdr); 712 } 713 714 /* rely on TXE irq (mask or unmask) for sending remaining data */ 715 if (kfifo_is_empty(&tport->xmit_fifo)) 716 stm32_usart_tx_interrupt_disable(port); 717 else 718 stm32_usart_tx_interrupt_enable(port); 719 } 720 721 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 722 { 723 struct stm32_port *stm32port = to_stm32_port(port); 724 struct tty_port *tport = &port->state->port; 725 struct dma_async_tx_descriptor *desc = NULL; 726 unsigned int count; 727 int ret; 728 729 if (stm32_usart_tx_dma_started(stm32port)) { 730 ret = stm32_usart_tx_dma_resume(stm32port); 731 if (ret < 0 && ret != -EAGAIN) 732 goto fallback_err; 733 return; 734 } 735 736 count = kfifo_out_peek(&tport->xmit_fifo, &stm32port->tx_buf[0], 737 TX_BUF_L); 738 739 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 740 stm32port->tx_dma_buf, 741 count, 742 DMA_MEM_TO_DEV, 743 DMA_PREP_INTERRUPT); 744 745 if (!desc) 746 goto fallback_err; 747 748 /* 749 * Set "tx_dma_busy" flag. This flag will be released when 750 * dmaengine_terminate_async will be called. This flag helps 751 * transmit_chars_dma not to start another DMA transaction 752 * if the callback of the previous is not yet called. 753 */ 754 stm32port->tx_dma_busy = true; 755 756 desc->callback = stm32_usart_tx_dma_complete; 757 desc->callback_param = port; 758 759 /* Push current DMA TX transaction in the pending queue */ 760 /* DMA no yet started, safe to free resources */ 761 ret = dma_submit_error(dmaengine_submit(desc)); 762 if (ret) { 763 dev_err(port->dev, "DMA failed with error code: %d\n", ret); 764 stm32_usart_tx_dma_terminate(stm32port); 765 goto fallback_err; 766 } 767 768 /* Issue pending DMA TX requests */ 769 dma_async_issue_pending(stm32port->tx_ch); 770 771 uart_xmit_advance(port, count); 772 773 return; 774 775 fallback_err: 776 stm32_usart_transmit_chars_pio(port); 777 } 778 779 static void stm32_usart_transmit_chars(struct uart_port *port) 780 { 781 struct stm32_port *stm32_port = to_stm32_port(port); 782 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 783 struct tty_port *tport = &port->state->port; 784 u32 isr; 785 int ret; 786 787 if (!stm32_port->hw_flow_control && 788 port->rs485.flags & SER_RS485_ENABLED && 789 (port->x_char || 790 !(kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)))) { 791 stm32_usart_tc_interrupt_disable(port); 792 stm32_usart_rs485_rts_enable(port); 793 } 794 795 if (port->x_char) { 796 /* dma terminate may have been called in case of dma pause failure */ 797 stm32_usart_tx_dma_pause(stm32_port); 798 799 /* Check that TDR is empty before filling FIFO */ 800 ret = 801 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 802 isr, 803 (isr & USART_SR_TXE), 804 10, 1000); 805 if (ret) 806 dev_warn(port->dev, "1 character may be erased\n"); 807 808 writel_relaxed(port->x_char, port->membase + ofs->tdr); 809 port->x_char = 0; 810 port->icount.tx++; 811 812 /* dma terminate may have been called in case of dma resume failure */ 813 stm32_usart_tx_dma_resume(stm32_port); 814 return; 815 } 816 817 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { 818 stm32_usart_tx_interrupt_disable(port); 819 return; 820 } 821 822 if (ofs->icr == UNDEF_REG) 823 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 824 else 825 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 826 827 if (stm32_port->tx_ch) 828 stm32_usart_transmit_chars_dma(port); 829 else 830 stm32_usart_transmit_chars_pio(port); 831 832 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 833 uart_write_wakeup(port); 834 835 if (kfifo_is_empty(&tport->xmit_fifo)) { 836 stm32_usart_tx_interrupt_disable(port); 837 if (!stm32_port->hw_flow_control && 838 port->rs485.flags & SER_RS485_ENABLED) { 839 stm32_usart_tc_interrupt_enable(port); 840 } 841 } 842 } 843 844 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 845 { 846 struct uart_port *port = ptr; 847 struct tty_port *tport = &port->state->port; 848 struct stm32_port *stm32_port = to_stm32_port(port); 849 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 850 u32 sr; 851 unsigned int size; 852 irqreturn_t ret = IRQ_NONE; 853 854 sr = readl_relaxed(port->membase + ofs->isr); 855 856 if (!stm32_port->hw_flow_control && 857 port->rs485.flags & SER_RS485_ENABLED && 858 (sr & USART_SR_TC)) { 859 stm32_usart_tc_interrupt_disable(port); 860 stm32_usart_rs485_rts_disable(port); 861 ret = IRQ_HANDLED; 862 } 863 864 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) { 865 writel_relaxed(USART_ICR_RTOCF, 866 port->membase + ofs->icr); 867 ret = IRQ_HANDLED; 868 } 869 870 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { 871 /* Clear wake up flag and disable wake up interrupt */ 872 writel_relaxed(USART_ICR_WUCF, 873 port->membase + ofs->icr); 874 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 875 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 876 pm_wakeup_event(tport->tty->dev, 0); 877 ret = IRQ_HANDLED; 878 } 879 880 /* 881 * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request 882 * line has been masked by HW and rx data are stacking in FIFO. 883 */ 884 if (!stm32_port->throttled) { 885 if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_started(stm32_port)) || 886 ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_started(stm32_port))) { 887 uart_port_lock(port); 888 size = stm32_usart_receive_chars(port, false); 889 uart_unlock_and_check_sysrq(port); 890 if (size) 891 tty_flip_buffer_push(tport); 892 ret = IRQ_HANDLED; 893 } 894 } 895 896 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { 897 uart_port_lock(port); 898 stm32_usart_transmit_chars(port); 899 uart_port_unlock(port); 900 ret = IRQ_HANDLED; 901 } 902 903 /* Receiver timeout irq for DMA RX */ 904 if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) { 905 uart_port_lock(port); 906 size = stm32_usart_receive_chars(port, false); 907 uart_unlock_and_check_sysrq(port); 908 if (size) 909 tty_flip_buffer_push(tport); 910 ret = IRQ_HANDLED; 911 } 912 913 return ret; 914 } 915 916 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 917 { 918 struct stm32_port *stm32_port = to_stm32_port(port); 919 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 920 921 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 922 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 923 else 924 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 925 926 mctrl_gpio_set(stm32_port->gpios, mctrl); 927 } 928 929 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 930 { 931 struct stm32_port *stm32_port = to_stm32_port(port); 932 unsigned int ret; 933 934 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 935 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 936 937 return mctrl_gpio_get(stm32_port->gpios, &ret); 938 } 939 940 static void stm32_usart_enable_ms(struct uart_port *port) 941 { 942 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 943 } 944 945 static void stm32_usart_disable_ms(struct uart_port *port) 946 { 947 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 948 } 949 950 /* Transmit stop */ 951 static void stm32_usart_stop_tx(struct uart_port *port) 952 { 953 struct stm32_port *stm32_port = to_stm32_port(port); 954 955 stm32_usart_tx_interrupt_disable(port); 956 957 /* dma terminate may have been called in case of dma pause failure */ 958 stm32_usart_tx_dma_pause(stm32_port); 959 960 stm32_usart_rs485_rts_disable(port); 961 } 962 963 /* There are probably characters waiting to be transmitted. */ 964 static void stm32_usart_start_tx(struct uart_port *port) 965 { 966 struct tty_port *tport = &port->state->port; 967 968 if (kfifo_is_empty(&tport->xmit_fifo) && !port->x_char) { 969 stm32_usart_rs485_rts_disable(port); 970 return; 971 } 972 973 stm32_usart_rs485_rts_enable(port); 974 975 stm32_usart_transmit_chars(port); 976 } 977 978 /* Flush the transmit buffer. */ 979 static void stm32_usart_flush_buffer(struct uart_port *port) 980 { 981 struct stm32_port *stm32_port = to_stm32_port(port); 982 983 if (stm32_port->tx_ch) 984 stm32_usart_tx_dma_terminate(stm32_port); 985 } 986 987 /* Throttle the remote when input buffer is about to overflow. */ 988 static void stm32_usart_throttle(struct uart_port *port) 989 { 990 struct stm32_port *stm32_port = to_stm32_port(port); 991 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 992 unsigned long flags; 993 994 uart_port_lock_irqsave(port, &flags); 995 996 /* 997 * Pause DMA transfer, so the RX data gets queued into the FIFO. 998 * Hardware flow control is triggered when RX FIFO is full. 999 */ 1000 stm32_usart_rx_dma_pause(stm32_port); 1001 1002 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 1003 if (stm32_port->cr3_irq) 1004 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 1005 1006 stm32_port->throttled = true; 1007 uart_port_unlock_irqrestore(port, flags); 1008 } 1009 1010 /* Unthrottle the remote, the input buffer can now accept data. */ 1011 static void stm32_usart_unthrottle(struct uart_port *port) 1012 { 1013 struct stm32_port *stm32_port = to_stm32_port(port); 1014 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1015 unsigned long flags; 1016 1017 uart_port_lock_irqsave(port, &flags); 1018 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 1019 if (stm32_port->cr3_irq) 1020 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 1021 1022 stm32_port->throttled = false; 1023 1024 /* 1025 * Switch back to DMA mode (resume DMA). 1026 * Hardware flow control is stopped when FIFO is not full any more. 1027 */ 1028 if (stm32_port->rx_ch) 1029 stm32_usart_rx_dma_start_or_resume(port); 1030 1031 uart_port_unlock_irqrestore(port, flags); 1032 } 1033 1034 /* Receive stop */ 1035 static void stm32_usart_stop_rx(struct uart_port *port) 1036 { 1037 struct stm32_port *stm32_port = to_stm32_port(port); 1038 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1039 1040 /* Disable DMA request line. */ 1041 stm32_usart_rx_dma_pause(stm32_port); 1042 1043 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 1044 if (stm32_port->cr3_irq) 1045 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 1046 } 1047 1048 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 1049 { 1050 struct stm32_port *stm32_port = to_stm32_port(port); 1051 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1052 unsigned long flags; 1053 1054 spin_lock_irqsave(&port->lock, flags); 1055 1056 if (break_state) 1057 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_SBKRQ); 1058 else 1059 stm32_usart_clr_bits(port, ofs->rqr, USART_RQR_SBKRQ); 1060 1061 spin_unlock_irqrestore(&port->lock, flags); 1062 } 1063 1064 static int stm32_usart_startup(struct uart_port *port) 1065 { 1066 struct stm32_port *stm32_port = to_stm32_port(port); 1067 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1068 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1069 const char *name = to_platform_device(port->dev)->name; 1070 u32 val; 1071 int ret; 1072 1073 ret = request_irq(port->irq, stm32_usart_interrupt, 1074 IRQF_NO_SUSPEND, name, port); 1075 if (ret) 1076 return ret; 1077 1078 if (stm32_port->swap) { 1079 val = readl_relaxed(port->membase + ofs->cr2); 1080 val |= USART_CR2_SWAP; 1081 writel_relaxed(val, port->membase + ofs->cr2); 1082 } 1083 stm32_port->throttled = false; 1084 1085 /* RX FIFO Flush */ 1086 if (ofs->rqr != UNDEF_REG) 1087 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); 1088 1089 if (stm32_port->rx_ch) { 1090 ret = stm32_usart_rx_dma_start_or_resume(port); 1091 if (ret) { 1092 free_irq(port->irq, port); 1093 return ret; 1094 } 1095 } 1096 1097 /* RX enabling */ 1098 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 1099 stm32_usart_set_bits(port, ofs->cr1, val); 1100 1101 return 0; 1102 } 1103 1104 static void stm32_usart_shutdown(struct uart_port *port) 1105 { 1106 struct stm32_port *stm32_port = to_stm32_port(port); 1107 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1108 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1109 u32 val, isr; 1110 int ret; 1111 1112 if (stm32_usart_tx_dma_started(stm32_port)) 1113 stm32_usart_tx_dma_terminate(stm32_port); 1114 1115 if (stm32_port->tx_ch) 1116 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1117 1118 /* Disable modem control interrupts */ 1119 stm32_usart_disable_ms(port); 1120 1121 val = USART_CR1_TXEIE | USART_CR1_TE; 1122 val |= stm32_port->cr1_irq | USART_CR1_RE; 1123 val |= BIT(cfg->uart_enable_bit); 1124 if (stm32_port->fifoen) 1125 val |= USART_CR1_FIFOEN; 1126 1127 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 1128 isr, (isr & USART_SR_TC), 1129 10, 100000); 1130 1131 /* Send the TC error message only when ISR_TC is not set */ 1132 if (ret) 1133 dev_err(port->dev, "Transmission is not complete\n"); 1134 1135 /* Disable RX DMA. */ 1136 if (stm32_port->rx_ch) { 1137 stm32_usart_rx_dma_terminate(stm32_port); 1138 dmaengine_synchronize(stm32_port->rx_ch); 1139 } 1140 1141 /* flush RX & TX FIFO */ 1142 if (ofs->rqr != UNDEF_REG) 1143 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 1144 port->membase + ofs->rqr); 1145 1146 stm32_usart_clr_bits(port, ofs->cr1, val); 1147 1148 free_irq(port->irq, port); 1149 } 1150 1151 static const unsigned int stm32_usart_presc_val[] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; 1152 1153 static void stm32_usart_set_termios(struct uart_port *port, 1154 struct ktermios *termios, 1155 const struct ktermios *old) 1156 { 1157 struct stm32_port *stm32_port = to_stm32_port(port); 1158 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1159 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1160 struct serial_rs485 *rs485conf = &port->rs485; 1161 unsigned int baud, bits, uart_clk, uart_clk_pres; 1162 u32 usartdiv, mantissa, fraction, oversampling; 1163 tcflag_t cflag = termios->c_cflag; 1164 u32 cr1, cr2, cr3, isr, brr, presc; 1165 unsigned long flags; 1166 int ret; 1167 1168 if (!stm32_port->hw_flow_control) 1169 cflag &= ~CRTSCTS; 1170 1171 uart_clk = clk_get_rate(stm32_port->clk); 1172 1173 baud = uart_get_baud_rate(port, termios, old, 0, uart_clk / 8); 1174 1175 uart_port_lock_irqsave(port, &flags); 1176 1177 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 1178 isr, 1179 (isr & USART_SR_TC), 1180 10, 100000); 1181 1182 /* Send the TC error message only when ISR_TC is not set. */ 1183 if (ret) 1184 dev_err(port->dev, "Transmission is not complete\n"); 1185 1186 /* Stop serial port and reset value */ 1187 writel_relaxed(0, port->membase + ofs->cr1); 1188 1189 /* flush RX & TX FIFO */ 1190 if (ofs->rqr != UNDEF_REG) 1191 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, 1192 port->membase + ofs->rqr); 1193 1194 cr1 = USART_CR1_TE | USART_CR1_RE; 1195 if (stm32_port->fifoen) 1196 cr1 |= USART_CR1_FIFOEN; 1197 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; 1198 1199 /* Tx and RX FIFO configuration */ 1200 cr3 = readl_relaxed(port->membase + ofs->cr3); 1201 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; 1202 if (stm32_port->fifoen) { 1203 if (stm32_port->txftcfg >= 0) 1204 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; 1205 if (stm32_port->rxftcfg >= 0) 1206 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; 1207 } 1208 1209 if (cflag & CSTOPB) 1210 cr2 |= USART_CR2_STOP_2B; 1211 1212 bits = tty_get_char_size(cflag); 1213 stm32_port->rdr_mask = (BIT(bits) - 1); 1214 1215 if (cflag & PARENB) { 1216 bits++; 1217 cr1 |= USART_CR1_PCE; 1218 } 1219 1220 /* 1221 * Word length configuration: 1222 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 1223 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 1224 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 1225 * M0 and M1 already cleared by cr1 initialization. 1226 */ 1227 if (bits == 9) { 1228 cr1 |= USART_CR1_M0; 1229 } else if ((bits == 7) && cfg->has_7bits_data) { 1230 cr1 |= USART_CR1_M1; 1231 } else if (bits != 8) { 1232 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 1233 , bits); 1234 cflag &= ~CSIZE; 1235 cflag |= CS8; 1236 termios->c_cflag = cflag; 1237 bits = 8; 1238 if (cflag & PARENB) { 1239 bits++; 1240 cr1 |= USART_CR1_M0; 1241 } 1242 } 1243 1244 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 1245 (stm32_port->fifoen && 1246 stm32_port->rxftcfg >= 0))) { 1247 if (cflag & CSTOPB) 1248 bits = bits + 3; /* 1 start bit + 2 stop bits */ 1249 else 1250 bits = bits + 2; /* 1 start bit + 1 stop bit */ 1251 1252 /* RX timeout irq to occur after last stop bit + bits */ 1253 stm32_port->cr1_irq = USART_CR1_RTOIE; 1254 writel_relaxed(bits, port->membase + ofs->rtor); 1255 cr2 |= USART_CR2_RTOEN; 1256 /* 1257 * Enable fifo threshold irq in two cases, either when there is no DMA, or when 1258 * wake up over usart, from low power until the DMA gets re-enabled by resume. 1259 */ 1260 stm32_port->cr3_irq = USART_CR3_RXFTIE; 1261 } 1262 1263 cr1 |= stm32_port->cr1_irq; 1264 cr3 |= stm32_port->cr3_irq; 1265 1266 if (cflag & PARODD) 1267 cr1 |= USART_CR1_PS; 1268 1269 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1270 if (cflag & CRTSCTS) { 1271 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1272 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 1273 } 1274 1275 for (presc = 0; presc <= USART_PRESC_MAX; presc++) { 1276 uart_clk_pres = DIV_ROUND_CLOSEST(uart_clk, stm32_usart_presc_val[presc]); 1277 usartdiv = DIV_ROUND_CLOSEST(uart_clk_pres, baud); 1278 1279 /* 1280 * The USART supports 16 or 8 times oversampling. 1281 * By default we prefer 16 times oversampling, so that the receiver 1282 * has a better tolerance to clock deviations. 1283 * 8 times oversampling is only used to achieve higher speeds. 1284 */ 1285 if (usartdiv < 16) { 1286 oversampling = 8; 1287 cr1 |= USART_CR1_OVER8; 1288 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 1289 } else { 1290 oversampling = 16; 1291 cr1 &= ~USART_CR1_OVER8; 1292 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 1293 } 1294 1295 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 1296 fraction = usartdiv % oversampling; 1297 brr = mantissa | fraction; 1298 1299 if (FIELD_FIT(USART_BRR_MASK, brr)) { 1300 if (ofs->presc != UNDEF_REG) { 1301 port->uartclk = uart_clk_pres; 1302 writel_relaxed(presc, port->membase + ofs->presc); 1303 } else if (presc) { 1304 /* We need a prescaler but we don't have it (STM32F4, STM32F7) */ 1305 dev_err(port->dev, 1306 "unable to set baudrate, input clock is too high"); 1307 } 1308 break; 1309 } else if (presc == USART_PRESC_MAX) { 1310 /* Even with prescaler and brr at max value we can't set baudrate */ 1311 dev_err(port->dev, "unable to set baudrate, input clock is too high"); 1312 break; 1313 } 1314 } 1315 1316 writel_relaxed(brr, port->membase + ofs->brr); 1317 1318 uart_update_timeout(port, cflag, baud); 1319 1320 port->read_status_mask = USART_SR_ORE; 1321 if (termios->c_iflag & INPCK) 1322 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 1323 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1324 port->read_status_mask |= USART_SR_FE; 1325 1326 /* Characters to ignore */ 1327 port->ignore_status_mask = 0; 1328 if (termios->c_iflag & IGNPAR) 1329 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 1330 if (termios->c_iflag & IGNBRK) { 1331 port->ignore_status_mask |= USART_SR_FE; 1332 /* 1333 * If we're ignoring parity and break indicators, 1334 * ignore overruns too (for real raw support). 1335 */ 1336 if (termios->c_iflag & IGNPAR) 1337 port->ignore_status_mask |= USART_SR_ORE; 1338 } 1339 1340 /* Ignore all characters if CREAD is not set */ 1341 if ((termios->c_cflag & CREAD) == 0) 1342 port->ignore_status_mask |= USART_SR_DUMMY_RX; 1343 1344 if (stm32_port->rx_ch) { 1345 /* 1346 * Setup DMA to collect only valid data and enable error irqs. 1347 * This also enables break reception when using DMA. 1348 */ 1349 cr1 |= USART_CR1_PEIE; 1350 cr3 |= USART_CR3_EIE; 1351 cr3 |= USART_CR3_DMAR; 1352 cr3 |= USART_CR3_DDRE; 1353 } 1354 1355 if (stm32_port->tx_ch) 1356 cr3 |= USART_CR3_DMAT; 1357 1358 if (rs485conf->flags & SER_RS485_ENABLED) { 1359 stm32_usart_config_reg_rs485(&cr1, &cr3, 1360 rs485conf->delay_rts_before_send, 1361 rs485conf->delay_rts_after_send, 1362 baud); 1363 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 1364 cr3 &= ~USART_CR3_DEP; 1365 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 1366 } else { 1367 cr3 |= USART_CR3_DEP; 1368 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 1369 } 1370 1371 } else { 1372 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 1373 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 1374 } 1375 1376 /* Configure wake up from low power on start bit detection */ 1377 if (stm32_port->wakeup_src) { 1378 cr3 &= ~USART_CR3_WUS_MASK; 1379 cr3 |= USART_CR3_WUS_START_BIT; 1380 } 1381 1382 writel_relaxed(cr3, port->membase + ofs->cr3); 1383 writel_relaxed(cr2, port->membase + ofs->cr2); 1384 writel_relaxed(cr1, port->membase + ofs->cr1); 1385 1386 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1387 uart_port_unlock_irqrestore(port, flags); 1388 1389 /* Handle modem control interrupts */ 1390 if (UART_ENABLE_MS(port, termios->c_cflag)) 1391 stm32_usart_enable_ms(port); 1392 else 1393 stm32_usart_disable_ms(port); 1394 } 1395 1396 static const char *stm32_usart_type(struct uart_port *port) 1397 { 1398 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 1399 } 1400 1401 static void stm32_usart_release_port(struct uart_port *port) 1402 { 1403 } 1404 1405 static int stm32_usart_request_port(struct uart_port *port) 1406 { 1407 return 0; 1408 } 1409 1410 static void stm32_usart_config_port(struct uart_port *port, int flags) 1411 { 1412 if (flags & UART_CONFIG_TYPE) 1413 port->type = PORT_STM32; 1414 } 1415 1416 static int 1417 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 1418 { 1419 /* No user changeable parameters */ 1420 return -EINVAL; 1421 } 1422 1423 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 1424 unsigned int oldstate) 1425 { 1426 struct stm32_port *stm32port = container_of(port, 1427 struct stm32_port, port); 1428 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1429 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 1430 unsigned long flags; 1431 1432 switch (state) { 1433 case UART_PM_STATE_ON: 1434 pm_runtime_get_sync(port->dev); 1435 break; 1436 case UART_PM_STATE_OFF: 1437 uart_port_lock_irqsave(port, &flags); 1438 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1439 uart_port_unlock_irqrestore(port, flags); 1440 pm_runtime_put_sync(port->dev); 1441 break; 1442 } 1443 } 1444 1445 #if defined(CONFIG_CONSOLE_POLL) 1446 1447 /* Callbacks for characters polling in debug context (i.e. KGDB). */ 1448 static int stm32_usart_poll_init(struct uart_port *port) 1449 { 1450 struct stm32_port *stm32_port = to_stm32_port(port); 1451 1452 return clk_prepare_enable(stm32_port->clk); 1453 } 1454 1455 static int stm32_usart_poll_get_char(struct uart_port *port) 1456 { 1457 struct stm32_port *stm32_port = to_stm32_port(port); 1458 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1459 1460 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE)) 1461 return NO_POLL_CHAR; 1462 1463 return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask; 1464 } 1465 1466 static void stm32_usart_poll_put_char(struct uart_port *port, unsigned char ch) 1467 { 1468 stm32_usart_console_putchar(port, ch); 1469 } 1470 #endif /* CONFIG_CONSOLE_POLL */ 1471 1472 static const struct uart_ops stm32_uart_ops = { 1473 .tx_empty = stm32_usart_tx_empty, 1474 .set_mctrl = stm32_usart_set_mctrl, 1475 .get_mctrl = stm32_usart_get_mctrl, 1476 .stop_tx = stm32_usart_stop_tx, 1477 .start_tx = stm32_usart_start_tx, 1478 .throttle = stm32_usart_throttle, 1479 .unthrottle = stm32_usart_unthrottle, 1480 .stop_rx = stm32_usart_stop_rx, 1481 .enable_ms = stm32_usart_enable_ms, 1482 .break_ctl = stm32_usart_break_ctl, 1483 .startup = stm32_usart_startup, 1484 .shutdown = stm32_usart_shutdown, 1485 .flush_buffer = stm32_usart_flush_buffer, 1486 .set_termios = stm32_usart_set_termios, 1487 .pm = stm32_usart_pm, 1488 .type = stm32_usart_type, 1489 .release_port = stm32_usart_release_port, 1490 .request_port = stm32_usart_request_port, 1491 .config_port = stm32_usart_config_port, 1492 .verify_port = stm32_usart_verify_port, 1493 #if defined(CONFIG_CONSOLE_POLL) 1494 .poll_init = stm32_usart_poll_init, 1495 .poll_get_char = stm32_usart_poll_get_char, 1496 .poll_put_char = stm32_usart_poll_put_char, 1497 #endif /* CONFIG_CONSOLE_POLL */ 1498 }; 1499 1500 struct stm32_usart_thresh_ratio { 1501 int mul; 1502 int div; 1503 }; 1504 1505 static const struct stm32_usart_thresh_ratio stm32h7_usart_fifo_thresh_cfg[] = { 1506 {1, 8}, {1, 4}, {1, 2}, {3, 4}, {7, 8}, {1, 1} }; 1507 1508 static int stm32_usart_get_thresh_value(u32 fifo_size, int index) 1509 { 1510 return fifo_size * stm32h7_usart_fifo_thresh_cfg[index].mul / 1511 stm32h7_usart_fifo_thresh_cfg[index].div; 1512 } 1513 1514 static int stm32_usart_get_ftcfg(struct platform_device *pdev, struct stm32_port *stm32port, 1515 const char *p, int *ftcfg) 1516 { 1517 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1518 u32 bytes, i, cfg8; 1519 int fifo_size; 1520 1521 if (WARN_ON(ofs->hwcfgr1 == UNDEF_REG)) 1522 return 1; 1523 1524 cfg8 = FIELD_GET(USART_HWCFGR1_CFG8, 1525 readl_relaxed(stm32port->port.membase + ofs->hwcfgr1)); 1526 1527 /* On STM32H7, hwcfgr is not present, so returned value will be 0 */ 1528 fifo_size = cfg8 ? 1 << cfg8 : STM32H7_USART_FIFO_SIZE; 1529 1530 /* DT option to get RX & TX FIFO threshold (default to half fifo size) */ 1531 if (of_property_read_u32(pdev->dev.of_node, p, &bytes)) 1532 bytes = fifo_size / 2; 1533 1534 if (bytes < stm32_usart_get_thresh_value(fifo_size, 0)) { 1535 *ftcfg = -EINVAL; 1536 return fifo_size; 1537 } 1538 1539 for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++) { 1540 if (stm32_usart_get_thresh_value(fifo_size, i) >= bytes) 1541 break; 1542 } 1543 if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg)) 1544 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1; 1545 1546 dev_dbg(&pdev->dev, "%s set to %d/%d bytes\n", p, 1547 stm32_usart_get_thresh_value(fifo_size, i), fifo_size); 1548 1549 *ftcfg = i; 1550 return fifo_size; 1551 } 1552 1553 static void stm32_usart_deinit_port(struct stm32_port *stm32port) 1554 { 1555 clk_disable_unprepare(stm32port->clk); 1556 } 1557 1558 static const struct serial_rs485 stm32_rs485_supported = { 1559 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 1560 SER_RS485_RX_DURING_TX, 1561 .delay_rts_before_send = 1, 1562 .delay_rts_after_send = 1, 1563 }; 1564 1565 static int stm32_usart_init_port(struct stm32_port *stm32port, 1566 struct platform_device *pdev) 1567 { 1568 struct uart_port *port = &stm32port->port; 1569 struct resource *res; 1570 int ret, irq; 1571 1572 irq = platform_get_irq(pdev, 0); 1573 if (irq < 0) 1574 return irq; 1575 1576 port->iotype = UPIO_MEM; 1577 port->flags = UPF_BOOT_AUTOCONF; 1578 port->ops = &stm32_uart_ops; 1579 port->dev = &pdev->dev; 1580 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1581 port->irq = irq; 1582 port->rs485_config = stm32_usart_config_rs485; 1583 port->rs485_supported = stm32_rs485_supported; 1584 1585 ret = stm32_usart_init_rs485(port, pdev); 1586 if (ret) 1587 return ret; 1588 1589 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && 1590 of_property_read_bool(pdev->dev.of_node, "wakeup-source"); 1591 1592 stm32port->swap = stm32port->info->cfg.has_swap && 1593 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); 1594 1595 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1596 if (IS_ERR(port->membase)) 1597 return PTR_ERR(port->membase); 1598 port->mapbase = res->start; 1599 1600 spin_lock_init(&port->lock); 1601 1602 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1603 if (IS_ERR(stm32port->clk)) 1604 return PTR_ERR(stm32port->clk); 1605 1606 /* Ensure that clk rate is correct by enabling the clk */ 1607 ret = clk_prepare_enable(stm32port->clk); 1608 if (ret) 1609 return ret; 1610 1611 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1612 if (!stm32port->port.uartclk) { 1613 ret = -EINVAL; 1614 goto err_clk; 1615 } 1616 1617 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1618 if (stm32port->fifoen) { 1619 stm32_usart_get_ftcfg(pdev, stm32port, "rx-threshold", &stm32port->rxftcfg); 1620 port->fifosize = stm32_usart_get_ftcfg(pdev, stm32port, "tx-threshold", 1621 &stm32port->txftcfg); 1622 } else { 1623 port->fifosize = 1; 1624 } 1625 1626 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1627 if (IS_ERR(stm32port->gpios)) { 1628 ret = PTR_ERR(stm32port->gpios); 1629 goto err_clk; 1630 } 1631 1632 /* 1633 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 1634 * properties should not be specified. 1635 */ 1636 if (stm32port->hw_flow_control) { 1637 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1638 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1639 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1640 ret = -EINVAL; 1641 goto err_clk; 1642 } 1643 } 1644 1645 return ret; 1646 1647 err_clk: 1648 clk_disable_unprepare(stm32port->clk); 1649 1650 return ret; 1651 } 1652 1653 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1654 { 1655 struct device_node *np = pdev->dev.of_node; 1656 int id; 1657 1658 if (!np) 1659 return NULL; 1660 1661 id = of_alias_get_id(np, "serial"); 1662 if (id < 0) { 1663 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1664 return NULL; 1665 } 1666 1667 if (WARN_ON(id >= STM32_MAX_PORTS)) 1668 return NULL; 1669 1670 stm32_ports[id].hw_flow_control = 1671 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1672 of_property_read_bool (np, "uart-has-rtscts"); 1673 stm32_ports[id].port.line = id; 1674 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1675 stm32_ports[id].cr3_irq = 0; 1676 stm32_ports[id].last_res = RX_BUF_L; 1677 return &stm32_ports[id]; 1678 } 1679 1680 #ifdef CONFIG_OF 1681 static const struct of_device_id stm32_match[] = { 1682 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1683 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1684 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1685 {}, 1686 }; 1687 1688 MODULE_DEVICE_TABLE(of, stm32_match); 1689 #endif 1690 1691 static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port, 1692 struct platform_device *pdev) 1693 { 1694 if (stm32port->rx_buf) 1695 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf, 1696 stm32port->rx_dma_buf); 1697 } 1698 1699 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1700 struct platform_device *pdev) 1701 { 1702 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1703 struct uart_port *port = &stm32port->port; 1704 struct device *dev = &pdev->dev; 1705 struct dma_slave_config config; 1706 int ret; 1707 1708 stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L, 1709 &stm32port->rx_dma_buf, 1710 GFP_KERNEL); 1711 if (!stm32port->rx_buf) 1712 return -ENOMEM; 1713 1714 /* Configure DMA channel */ 1715 memset(&config, 0, sizeof(config)); 1716 config.src_addr = port->mapbase + ofs->rdr; 1717 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1718 1719 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1720 if (ret < 0) { 1721 dev_err(dev, "rx dma channel config failed\n"); 1722 stm32_usart_of_dma_rx_remove(stm32port, pdev); 1723 return ret; 1724 } 1725 1726 return 0; 1727 } 1728 1729 static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port, 1730 struct platform_device *pdev) 1731 { 1732 if (stm32port->tx_buf) 1733 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf, 1734 stm32port->tx_dma_buf); 1735 } 1736 1737 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1738 struct platform_device *pdev) 1739 { 1740 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1741 struct uart_port *port = &stm32port->port; 1742 struct device *dev = &pdev->dev; 1743 struct dma_slave_config config; 1744 int ret; 1745 1746 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L, 1747 &stm32port->tx_dma_buf, 1748 GFP_KERNEL); 1749 if (!stm32port->tx_buf) 1750 return -ENOMEM; 1751 1752 /* Configure DMA channel */ 1753 memset(&config, 0, sizeof(config)); 1754 config.dst_addr = port->mapbase + ofs->tdr; 1755 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1756 1757 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1758 if (ret < 0) { 1759 dev_err(dev, "tx dma channel config failed\n"); 1760 stm32_usart_of_dma_tx_remove(stm32port, pdev); 1761 return ret; 1762 } 1763 1764 return 0; 1765 } 1766 1767 static int stm32_usart_serial_probe(struct platform_device *pdev) 1768 { 1769 struct stm32_port *stm32port; 1770 int ret; 1771 1772 stm32port = stm32_usart_of_get_port(pdev); 1773 if (!stm32port) 1774 return -ENODEV; 1775 1776 stm32port->info = of_device_get_match_data(&pdev->dev); 1777 if (!stm32port->info) 1778 return -EINVAL; 1779 1780 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx"); 1781 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) 1782 return -EPROBE_DEFER; 1783 1784 /* Fall back in interrupt mode for any non-deferral error */ 1785 if (IS_ERR(stm32port->rx_ch)) 1786 stm32port->rx_ch = NULL; 1787 1788 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx"); 1789 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) { 1790 ret = -EPROBE_DEFER; 1791 goto err_dma_rx; 1792 } 1793 /* Fall back in interrupt mode for any non-deferral error */ 1794 if (IS_ERR(stm32port->tx_ch)) 1795 stm32port->tx_ch = NULL; 1796 1797 ret = stm32_usart_init_port(stm32port, pdev); 1798 if (ret) 1799 goto err_dma_tx; 1800 1801 if (stm32port->wakeup_src) { 1802 device_set_wakeup_capable(&pdev->dev, true); 1803 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); 1804 if (ret) 1805 goto err_deinit_port; 1806 } 1807 1808 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) { 1809 /* Fall back in interrupt mode */ 1810 dma_release_channel(stm32port->rx_ch); 1811 stm32port->rx_ch = NULL; 1812 } 1813 1814 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) { 1815 /* Fall back in interrupt mode */ 1816 dma_release_channel(stm32port->tx_ch); 1817 stm32port->tx_ch = NULL; 1818 } 1819 1820 if (!stm32port->rx_ch) 1821 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n"); 1822 if (!stm32port->tx_ch) 1823 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n"); 1824 1825 platform_set_drvdata(pdev, &stm32port->port); 1826 1827 pm_runtime_get_noresume(&pdev->dev); 1828 pm_runtime_set_active(&pdev->dev); 1829 pm_runtime_enable(&pdev->dev); 1830 1831 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1832 if (ret) 1833 goto err_port; 1834 1835 pm_runtime_put_sync(&pdev->dev); 1836 1837 return 0; 1838 1839 err_port: 1840 pm_runtime_disable(&pdev->dev); 1841 pm_runtime_set_suspended(&pdev->dev); 1842 pm_runtime_put_noidle(&pdev->dev); 1843 1844 if (stm32port->tx_ch) 1845 stm32_usart_of_dma_tx_remove(stm32port, pdev); 1846 if (stm32port->rx_ch) 1847 stm32_usart_of_dma_rx_remove(stm32port, pdev); 1848 1849 if (stm32port->wakeup_src) 1850 dev_pm_clear_wake_irq(&pdev->dev); 1851 1852 err_deinit_port: 1853 if (stm32port->wakeup_src) 1854 device_set_wakeup_capable(&pdev->dev, false); 1855 1856 stm32_usart_deinit_port(stm32port); 1857 1858 err_dma_tx: 1859 if (stm32port->tx_ch) 1860 dma_release_channel(stm32port->tx_ch); 1861 1862 err_dma_rx: 1863 if (stm32port->rx_ch) 1864 dma_release_channel(stm32port->rx_ch); 1865 1866 return ret; 1867 } 1868 1869 static void stm32_usart_serial_remove(struct platform_device *pdev) 1870 { 1871 struct uart_port *port = platform_get_drvdata(pdev); 1872 struct stm32_port *stm32_port = to_stm32_port(port); 1873 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1874 u32 cr3; 1875 1876 pm_runtime_get_sync(&pdev->dev); 1877 uart_remove_one_port(&stm32_usart_driver, port); 1878 1879 pm_runtime_disable(&pdev->dev); 1880 pm_runtime_set_suspended(&pdev->dev); 1881 pm_runtime_put_noidle(&pdev->dev); 1882 1883 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE); 1884 1885 if (stm32_port->tx_ch) { 1886 stm32_usart_of_dma_tx_remove(stm32_port, pdev); 1887 dma_release_channel(stm32_port->tx_ch); 1888 } 1889 1890 if (stm32_port->rx_ch) { 1891 stm32_usart_of_dma_rx_remove(stm32_port, pdev); 1892 dma_release_channel(stm32_port->rx_ch); 1893 } 1894 1895 cr3 = readl_relaxed(port->membase + ofs->cr3); 1896 cr3 &= ~USART_CR3_EIE; 1897 cr3 &= ~USART_CR3_DMAR; 1898 cr3 &= ~USART_CR3_DMAT; 1899 cr3 &= ~USART_CR3_DDRE; 1900 writel_relaxed(cr3, port->membase + ofs->cr3); 1901 1902 if (stm32_port->wakeup_src) { 1903 dev_pm_clear_wake_irq(&pdev->dev); 1904 device_init_wakeup(&pdev->dev, false); 1905 } 1906 1907 stm32_usart_deinit_port(stm32_port); 1908 } 1909 1910 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch) 1911 { 1912 struct stm32_port *stm32_port = to_stm32_port(port); 1913 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1914 u32 isr; 1915 int ret; 1916 1917 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr, 1918 (isr & USART_SR_TXE), 100, 1919 STM32_USART_TIMEOUT_USEC); 1920 if (ret != 0) { 1921 dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret); 1922 return; 1923 } 1924 writel_relaxed(ch, port->membase + ofs->tdr); 1925 } 1926 1927 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1928 static void stm32_usart_console_write(struct console *co, const char *s, 1929 unsigned int cnt) 1930 { 1931 struct uart_port *port = &stm32_ports[co->index].port; 1932 struct stm32_port *stm32_port = to_stm32_port(port); 1933 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1934 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1935 unsigned long flags; 1936 u32 old_cr1, new_cr1; 1937 int locked = 1; 1938 1939 if (oops_in_progress) 1940 locked = uart_port_trylock_irqsave(port, &flags); 1941 else 1942 uart_port_lock_irqsave(port, &flags); 1943 1944 /* Save and disable interrupts, enable the transmitter */ 1945 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1946 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1947 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1948 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1949 1950 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1951 1952 /* Restore interrupt state */ 1953 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1954 1955 if (locked) 1956 uart_port_unlock_irqrestore(port, flags); 1957 } 1958 1959 static int stm32_usart_console_setup(struct console *co, char *options) 1960 { 1961 struct stm32_port *stm32port; 1962 int baud = 9600; 1963 int bits = 8; 1964 int parity = 'n'; 1965 int flow = 'n'; 1966 1967 if (co->index >= STM32_MAX_PORTS) 1968 return -ENODEV; 1969 1970 stm32port = &stm32_ports[co->index]; 1971 1972 /* 1973 * This driver does not support early console initialization 1974 * (use ARM early printk support instead), so we only expect 1975 * this to be called during the uart port registration when the 1976 * driver gets probed and the port should be mapped at that point. 1977 */ 1978 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1979 return -ENXIO; 1980 1981 if (options) 1982 uart_parse_options(options, &baud, &parity, &bits, &flow); 1983 1984 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1985 } 1986 1987 static struct console stm32_console = { 1988 .name = STM32_SERIAL_NAME, 1989 .device = uart_console_device, 1990 .write = stm32_usart_console_write, 1991 .setup = stm32_usart_console_setup, 1992 .flags = CON_PRINTBUFFER, 1993 .index = -1, 1994 .data = &stm32_usart_driver, 1995 }; 1996 1997 #define STM32_SERIAL_CONSOLE (&stm32_console) 1998 1999 #else 2000 #define STM32_SERIAL_CONSOLE NULL 2001 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 2002 2003 #ifdef CONFIG_SERIAL_EARLYCON 2004 static void early_stm32_usart_console_putchar(struct uart_port *port, unsigned char ch) 2005 { 2006 struct stm32_usart_info *info = port->private_data; 2007 2008 while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE)) 2009 cpu_relax(); 2010 2011 writel_relaxed(ch, port->membase + info->ofs.tdr); 2012 } 2013 2014 static void early_stm32_serial_write(struct console *console, const char *s, unsigned int count) 2015 { 2016 struct earlycon_device *device = console->data; 2017 struct uart_port *port = &device->port; 2018 2019 uart_console_write(port, s, count, early_stm32_usart_console_putchar); 2020 } 2021 2022 static int __init early_stm32_h7_serial_setup(struct earlycon_device *device, const char *options) 2023 { 2024 if (!(device->port.membase || device->port.iobase)) 2025 return -ENODEV; 2026 device->port.private_data = &stm32h7_info; 2027 device->con->write = early_stm32_serial_write; 2028 return 0; 2029 } 2030 2031 static int __init early_stm32_f7_serial_setup(struct earlycon_device *device, const char *options) 2032 { 2033 if (!(device->port.membase || device->port.iobase)) 2034 return -ENODEV; 2035 device->port.private_data = &stm32f7_info; 2036 device->con->write = early_stm32_serial_write; 2037 return 0; 2038 } 2039 2040 static int __init early_stm32_f4_serial_setup(struct earlycon_device *device, const char *options) 2041 { 2042 if (!(device->port.membase || device->port.iobase)) 2043 return -ENODEV; 2044 device->port.private_data = &stm32f4_info; 2045 device->con->write = early_stm32_serial_write; 2046 return 0; 2047 } 2048 2049 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup); 2050 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup); 2051 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup); 2052 #endif /* CONFIG_SERIAL_EARLYCON */ 2053 2054 static struct uart_driver stm32_usart_driver = { 2055 .driver_name = DRIVER_NAME, 2056 .dev_name = STM32_SERIAL_NAME, 2057 .major = 0, 2058 .minor = 0, 2059 .nr = STM32_MAX_PORTS, 2060 .cons = STM32_SERIAL_CONSOLE, 2061 }; 2062 2063 static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 2064 bool enable) 2065 { 2066 struct stm32_port *stm32_port = to_stm32_port(port); 2067 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 2068 struct tty_port *tport = &port->state->port; 2069 int ret; 2070 unsigned int size = 0; 2071 unsigned long flags; 2072 2073 if (!stm32_port->wakeup_src || !tty_port_initialized(tport)) 2074 return 0; 2075 2076 /* 2077 * Enable low-power wake-up and wake-up irq if argument is set to 2078 * "enable", disable low-power wake-up and wake-up irq otherwise 2079 */ 2080 if (enable) { 2081 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 2082 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); 2083 mctrl_gpio_enable_irq_wake(stm32_port->gpios); 2084 2085 /* 2086 * When DMA is used for reception, it must be disabled before 2087 * entering low-power mode and re-enabled when exiting from 2088 * low-power mode. 2089 */ 2090 if (stm32_port->rx_ch) { 2091 uart_port_lock_irqsave(port, &flags); 2092 /* Poll data from DMA RX buffer if any */ 2093 if (!stm32_usart_rx_dma_pause(stm32_port)) 2094 size += stm32_usart_receive_chars(port, true); 2095 stm32_usart_rx_dma_terminate(stm32_port); 2096 uart_unlock_and_check_sysrq_irqrestore(port, flags); 2097 if (size) 2098 tty_flip_buffer_push(tport); 2099 } 2100 2101 /* Poll data from RX FIFO if any */ 2102 stm32_usart_receive_chars(port, false); 2103 } else { 2104 if (stm32_port->rx_ch) { 2105 ret = stm32_usart_rx_dma_start_or_resume(port); 2106 if (ret) 2107 return ret; 2108 } 2109 mctrl_gpio_disable_irq_wake(stm32_port->gpios); 2110 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 2111 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); 2112 } 2113 2114 return 0; 2115 } 2116 2117 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 2118 { 2119 struct uart_port *port = dev_get_drvdata(dev); 2120 int ret; 2121 2122 uart_suspend_port(&stm32_usart_driver, port); 2123 2124 if (device_may_wakeup(dev) || device_wakeup_path(dev)) { 2125 ret = stm32_usart_serial_en_wakeup(port, true); 2126 if (ret) 2127 return ret; 2128 } 2129 2130 /* 2131 * When "no_console_suspend" is enabled, keep the pinctrl default state 2132 * and rely on bootloader stage to restore this state upon resume. 2133 * Otherwise, apply the idle or sleep states depending on wakeup 2134 * capabilities. 2135 */ 2136 if (console_suspend_enabled || !uart_console(port)) { 2137 if (device_may_wakeup(dev) || device_wakeup_path(dev)) 2138 pinctrl_pm_select_idle_state(dev); 2139 else 2140 pinctrl_pm_select_sleep_state(dev); 2141 } 2142 2143 return 0; 2144 } 2145 2146 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 2147 { 2148 struct uart_port *port = dev_get_drvdata(dev); 2149 int ret; 2150 2151 pinctrl_pm_select_default_state(dev); 2152 2153 if (device_may_wakeup(dev) || device_wakeup_path(dev)) { 2154 ret = stm32_usart_serial_en_wakeup(port, false); 2155 if (ret) 2156 return ret; 2157 } 2158 2159 return uart_resume_port(&stm32_usart_driver, port); 2160 } 2161 2162 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 2163 { 2164 struct uart_port *port = dev_get_drvdata(dev); 2165 struct stm32_port *stm32port = container_of(port, 2166 struct stm32_port, port); 2167 2168 clk_disable_unprepare(stm32port->clk); 2169 2170 return 0; 2171 } 2172 2173 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 2174 { 2175 struct uart_port *port = dev_get_drvdata(dev); 2176 struct stm32_port *stm32port = container_of(port, 2177 struct stm32_port, port); 2178 2179 return clk_prepare_enable(stm32port->clk); 2180 } 2181 2182 static const struct dev_pm_ops stm32_serial_pm_ops = { 2183 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 2184 stm32_usart_runtime_resume, NULL) 2185 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 2186 stm32_usart_serial_resume) 2187 }; 2188 2189 static struct platform_driver stm32_serial_driver = { 2190 .probe = stm32_usart_serial_probe, 2191 .remove = stm32_usart_serial_remove, 2192 .driver = { 2193 .name = DRIVER_NAME, 2194 .pm = &stm32_serial_pm_ops, 2195 .of_match_table = of_match_ptr(stm32_match), 2196 }, 2197 }; 2198 2199 static int __init stm32_usart_init(void) 2200 { 2201 static char banner[] __initdata = "STM32 USART driver initialized"; 2202 int ret; 2203 2204 pr_info("%s\n", banner); 2205 2206 ret = uart_register_driver(&stm32_usart_driver); 2207 if (ret) 2208 return ret; 2209 2210 ret = platform_driver_register(&stm32_serial_driver); 2211 if (ret) 2212 uart_unregister_driver(&stm32_usart_driver); 2213 2214 return ret; 2215 } 2216 2217 static void __exit stm32_usart_exit(void) 2218 { 2219 platform_driver_unregister(&stm32_serial_driver); 2220 uart_unregister_driver(&stm32_usart_driver); 2221 } 2222 2223 module_init(stm32_usart_init); 2224 module_exit(stm32_usart_exit); 2225 2226 MODULE_ALIAS("platform:" DRIVER_NAME); 2227 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 2228 MODULE_LICENSE("GPL v2"); 2229