1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@st.com> 7 * 8 * Inspired by st-asc.c from STMicroelectronics (c) 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/console.h> 13 #include <linux/delay.h> 14 #include <linux/dma-direction.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/pm_wakeirq.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial.h> 29 #include <linux/spinlock.h> 30 #include <linux/sysrq.h> 31 #include <linux/tty_flip.h> 32 #include <linux/tty.h> 33 34 #include "serial_mctrl_gpio.h" 35 #include "stm32-usart.h" 36 37 static void stm32_stop_tx(struct uart_port *port); 38 static void stm32_transmit_chars(struct uart_port *port); 39 40 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 41 { 42 return container_of(port, struct stm32_port, port); 43 } 44 45 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) 46 { 47 u32 val; 48 49 val = readl_relaxed(port->membase + reg); 50 val |= bits; 51 writel_relaxed(val, port->membase + reg); 52 } 53 54 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) 55 { 56 u32 val; 57 58 val = readl_relaxed(port->membase + reg); 59 val &= ~bits; 60 writel_relaxed(val, port->membase + reg); 61 } 62 63 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 64 u32 delay_DDE, u32 baud) 65 { 66 u32 rs485_deat_dedt; 67 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 68 bool over8; 69 70 *cr3 |= USART_CR3_DEM; 71 over8 = *cr1 & USART_CR1_OVER8; 72 73 if (over8) 74 rs485_deat_dedt = delay_ADE * baud * 8; 75 else 76 rs485_deat_dedt = delay_ADE * baud * 16; 77 78 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 79 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 80 rs485_deat_dedt_max : rs485_deat_dedt; 81 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 82 USART_CR1_DEAT_MASK; 83 *cr1 |= rs485_deat_dedt; 84 85 if (over8) 86 rs485_deat_dedt = delay_DDE * baud * 8; 87 else 88 rs485_deat_dedt = delay_DDE * baud * 16; 89 90 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 91 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 92 rs485_deat_dedt_max : rs485_deat_dedt; 93 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 94 USART_CR1_DEDT_MASK; 95 *cr1 |= rs485_deat_dedt; 96 } 97 98 static int stm32_config_rs485(struct uart_port *port, 99 struct serial_rs485 *rs485conf) 100 { 101 struct stm32_port *stm32_port = to_stm32_port(port); 102 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 103 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 104 u32 usartdiv, baud, cr1, cr3; 105 bool over8; 106 107 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 108 109 port->rs485 = *rs485conf; 110 111 rs485conf->flags |= SER_RS485_RX_DURING_TX; 112 113 if (rs485conf->flags & SER_RS485_ENABLED) { 114 cr1 = readl_relaxed(port->membase + ofs->cr1); 115 cr3 = readl_relaxed(port->membase + ofs->cr3); 116 usartdiv = readl_relaxed(port->membase + ofs->brr); 117 usartdiv = usartdiv & GENMASK(15, 0); 118 over8 = cr1 & USART_CR1_OVER8; 119 120 if (over8) 121 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 122 << USART_BRR_04_R_SHIFT; 123 124 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 125 stm32_config_reg_rs485(&cr1, &cr3, 126 rs485conf->delay_rts_before_send, 127 rs485conf->delay_rts_after_send, baud); 128 129 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 130 cr3 &= ~USART_CR3_DEP; 131 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 132 } else { 133 cr3 |= USART_CR3_DEP; 134 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 135 } 136 137 writel_relaxed(cr3, port->membase + ofs->cr3); 138 writel_relaxed(cr1, port->membase + ofs->cr1); 139 } else { 140 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP); 141 stm32_clr_bits(port, ofs->cr1, 142 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 143 } 144 145 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 146 147 return 0; 148 } 149 150 static int stm32_init_rs485(struct uart_port *port, 151 struct platform_device *pdev) 152 { 153 struct serial_rs485 *rs485conf = &port->rs485; 154 155 rs485conf->flags = 0; 156 rs485conf->delay_rts_before_send = 0; 157 rs485conf->delay_rts_after_send = 0; 158 159 if (!pdev->dev.of_node) 160 return -ENODEV; 161 162 return uart_get_rs485_mode(port); 163 } 164 165 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res, 166 bool threaded) 167 { 168 struct stm32_port *stm32_port = to_stm32_port(port); 169 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 170 enum dma_status status; 171 struct dma_tx_state state; 172 173 *sr = readl_relaxed(port->membase + ofs->isr); 174 175 if (threaded && stm32_port->rx_ch) { 176 status = dmaengine_tx_status(stm32_port->rx_ch, 177 stm32_port->rx_ch->cookie, 178 &state); 179 if ((status == DMA_IN_PROGRESS) && 180 (*last_res != state.residue)) 181 return 1; 182 else 183 return 0; 184 } else if (*sr & USART_SR_RXNE) { 185 return 1; 186 } 187 return 0; 188 } 189 190 static unsigned long stm32_get_char(struct uart_port *port, u32 *sr, 191 int *last_res) 192 { 193 struct stm32_port *stm32_port = to_stm32_port(port); 194 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 195 unsigned long c; 196 197 if (stm32_port->rx_ch) { 198 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 199 if ((*last_res) == 0) 200 *last_res = RX_BUF_L; 201 } else { 202 c = readl_relaxed(port->membase + ofs->rdr); 203 /* apply RDR data mask */ 204 c &= stm32_port->rdr_mask; 205 } 206 207 return c; 208 } 209 210 static void stm32_receive_chars(struct uart_port *port, bool threaded) 211 { 212 struct tty_port *tport = &port->state->port; 213 struct stm32_port *stm32_port = to_stm32_port(port); 214 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 215 unsigned long c; 216 u32 sr; 217 char flag; 218 219 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 220 pm_wakeup_event(tport->tty->dev, 0); 221 222 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) { 223 sr |= USART_SR_DUMMY_RX; 224 flag = TTY_NORMAL; 225 226 /* 227 * Status bits has to be cleared before reading the RDR: 228 * In FIFO mode, reading the RDR will pop the next data 229 * (if any) along with its status bits into the SR. 230 * Not doing so leads to misalignement between RDR and SR, 231 * and clear status bits of the next rx data. 232 * 233 * Clear errors flags for stm32f7 and stm32h7 compatible 234 * devices. On stm32f4 compatible devices, the error bit is 235 * cleared by the sequence [read SR - read DR]. 236 */ 237 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 238 writel_relaxed(sr & USART_SR_ERR_MASK, 239 port->membase + ofs->icr); 240 241 c = stm32_get_char(port, &sr, &stm32_port->last_res); 242 port->icount.rx++; 243 if (sr & USART_SR_ERR_MASK) { 244 if (sr & USART_SR_ORE) { 245 port->icount.overrun++; 246 } else if (sr & USART_SR_PE) { 247 port->icount.parity++; 248 } else if (sr & USART_SR_FE) { 249 /* Break detection if character is null */ 250 if (!c) { 251 port->icount.brk++; 252 if (uart_handle_break(port)) 253 continue; 254 } else { 255 port->icount.frame++; 256 } 257 } 258 259 sr &= port->read_status_mask; 260 261 if (sr & USART_SR_PE) { 262 flag = TTY_PARITY; 263 } else if (sr & USART_SR_FE) { 264 if (!c) 265 flag = TTY_BREAK; 266 else 267 flag = TTY_FRAME; 268 } 269 } 270 271 if (uart_handle_sysrq_char(port, c)) 272 continue; 273 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 274 } 275 276 spin_unlock(&port->lock); 277 tty_flip_buffer_push(tport); 278 spin_lock(&port->lock); 279 } 280 281 static void stm32_tx_dma_complete(void *arg) 282 { 283 struct uart_port *port = arg; 284 struct stm32_port *stm32port = to_stm32_port(port); 285 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 286 287 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 288 stm32port->tx_dma_busy = false; 289 290 /* Let's see if we have pending data to send */ 291 stm32_transmit_chars(port); 292 } 293 294 static void stm32_tx_interrupt_enable(struct uart_port *port) 295 { 296 struct stm32_port *stm32_port = to_stm32_port(port); 297 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 298 299 /* 300 * Enables TX FIFO threashold irq when FIFO is enabled, 301 * or TX empty irq when FIFO is disabled 302 */ 303 if (stm32_port->fifoen) 304 stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 305 else 306 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 307 } 308 309 static void stm32_tx_interrupt_disable(struct uart_port *port) 310 { 311 struct stm32_port *stm32_port = to_stm32_port(port); 312 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 313 314 if (stm32_port->fifoen) 315 stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 316 else 317 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 318 } 319 320 static void stm32_transmit_chars_pio(struct uart_port *port) 321 { 322 struct stm32_port *stm32_port = to_stm32_port(port); 323 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 324 struct circ_buf *xmit = &port->state->xmit; 325 326 if (stm32_port->tx_dma_busy) { 327 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 328 stm32_port->tx_dma_busy = false; 329 } 330 331 while (!uart_circ_empty(xmit)) { 332 /* Check that TDR is empty before filling FIFO */ 333 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 334 break; 335 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 336 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 337 port->icount.tx++; 338 } 339 340 /* rely on TXE irq (mask or unmask) for sending remaining data */ 341 if (uart_circ_empty(xmit)) 342 stm32_tx_interrupt_disable(port); 343 else 344 stm32_tx_interrupt_enable(port); 345 } 346 347 static void stm32_transmit_chars_dma(struct uart_port *port) 348 { 349 struct stm32_port *stm32port = to_stm32_port(port); 350 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 351 struct circ_buf *xmit = &port->state->xmit; 352 struct dma_async_tx_descriptor *desc = NULL; 353 unsigned int count, i; 354 355 if (stm32port->tx_dma_busy) 356 return; 357 358 stm32port->tx_dma_busy = true; 359 360 count = uart_circ_chars_pending(xmit); 361 362 if (count > TX_BUF_L) 363 count = TX_BUF_L; 364 365 if (xmit->tail < xmit->head) { 366 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 367 } else { 368 size_t one = UART_XMIT_SIZE - xmit->tail; 369 size_t two; 370 371 if (one > count) 372 one = count; 373 two = count - one; 374 375 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 376 if (two) 377 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 378 } 379 380 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 381 stm32port->tx_dma_buf, 382 count, 383 DMA_MEM_TO_DEV, 384 DMA_PREP_INTERRUPT); 385 386 if (!desc) { 387 for (i = count; i > 0; i--) 388 stm32_transmit_chars_pio(port); 389 return; 390 } 391 392 desc->callback = stm32_tx_dma_complete; 393 desc->callback_param = port; 394 395 /* Push current DMA TX transaction in the pending queue */ 396 dmaengine_submit(desc); 397 398 /* Issue pending DMA TX requests */ 399 dma_async_issue_pending(stm32port->tx_ch); 400 401 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 402 403 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 404 port->icount.tx += count; 405 } 406 407 static void stm32_transmit_chars(struct uart_port *port) 408 { 409 struct stm32_port *stm32_port = to_stm32_port(port); 410 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 411 struct circ_buf *xmit = &port->state->xmit; 412 413 if (port->x_char) { 414 if (stm32_port->tx_dma_busy) 415 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 416 writel_relaxed(port->x_char, port->membase + ofs->tdr); 417 port->x_char = 0; 418 port->icount.tx++; 419 if (stm32_port->tx_dma_busy) 420 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); 421 return; 422 } 423 424 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 425 stm32_tx_interrupt_disable(port); 426 return; 427 } 428 429 if (ofs->icr == UNDEF_REG) 430 stm32_clr_bits(port, ofs->isr, USART_SR_TC); 431 else 432 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 433 434 if (stm32_port->tx_ch) 435 stm32_transmit_chars_dma(port); 436 else 437 stm32_transmit_chars_pio(port); 438 439 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 440 uart_write_wakeup(port); 441 442 if (uart_circ_empty(xmit)) 443 stm32_tx_interrupt_disable(port); 444 } 445 446 static irqreturn_t stm32_interrupt(int irq, void *ptr) 447 { 448 struct uart_port *port = ptr; 449 struct stm32_port *stm32_port = to_stm32_port(port); 450 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 451 u32 sr; 452 453 spin_lock(&port->lock); 454 455 sr = readl_relaxed(port->membase + ofs->isr); 456 457 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 458 writel_relaxed(USART_ICR_RTOCF, 459 port->membase + ofs->icr); 460 461 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG)) 462 writel_relaxed(USART_ICR_WUCF, 463 port->membase + ofs->icr); 464 465 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 466 stm32_receive_chars(port, false); 467 468 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 469 stm32_transmit_chars(port); 470 471 spin_unlock(&port->lock); 472 473 if (stm32_port->rx_ch) 474 return IRQ_WAKE_THREAD; 475 else 476 return IRQ_HANDLED; 477 } 478 479 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr) 480 { 481 struct uart_port *port = ptr; 482 struct stm32_port *stm32_port = to_stm32_port(port); 483 484 spin_lock(&port->lock); 485 486 if (stm32_port->rx_ch) 487 stm32_receive_chars(port, true); 488 489 spin_unlock(&port->lock); 490 491 return IRQ_HANDLED; 492 } 493 494 static unsigned int stm32_tx_empty(struct uart_port *port) 495 { 496 struct stm32_port *stm32_port = to_stm32_port(port); 497 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 498 499 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 500 } 501 502 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) 503 { 504 struct stm32_port *stm32_port = to_stm32_port(port); 505 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 506 507 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 508 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); 509 else 510 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 511 512 mctrl_gpio_set(stm32_port->gpios, mctrl); 513 } 514 515 static unsigned int stm32_get_mctrl(struct uart_port *port) 516 { 517 struct stm32_port *stm32_port = to_stm32_port(port); 518 unsigned int ret; 519 520 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 521 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 522 523 return mctrl_gpio_get(stm32_port->gpios, &ret); 524 } 525 526 static void stm32_enable_ms(struct uart_port *port) 527 { 528 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 529 } 530 531 static void stm32_disable_ms(struct uart_port *port) 532 { 533 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 534 } 535 536 /* Transmit stop */ 537 static void stm32_stop_tx(struct uart_port *port) 538 { 539 struct stm32_port *stm32_port = to_stm32_port(port); 540 struct serial_rs485 *rs485conf = &port->rs485; 541 542 stm32_tx_interrupt_disable(port); 543 544 if (rs485conf->flags & SER_RS485_ENABLED) { 545 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 546 mctrl_gpio_set(stm32_port->gpios, 547 stm32_port->port.mctrl & ~TIOCM_RTS); 548 } else { 549 mctrl_gpio_set(stm32_port->gpios, 550 stm32_port->port.mctrl | TIOCM_RTS); 551 } 552 } 553 } 554 555 /* There are probably characters waiting to be transmitted. */ 556 static void stm32_start_tx(struct uart_port *port) 557 { 558 struct stm32_port *stm32_port = to_stm32_port(port); 559 struct serial_rs485 *rs485conf = &port->rs485; 560 struct circ_buf *xmit = &port->state->xmit; 561 562 if (uart_circ_empty(xmit)) 563 return; 564 565 if (rs485conf->flags & SER_RS485_ENABLED) { 566 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 567 mctrl_gpio_set(stm32_port->gpios, 568 stm32_port->port.mctrl | TIOCM_RTS); 569 } else { 570 mctrl_gpio_set(stm32_port->gpios, 571 stm32_port->port.mctrl & ~TIOCM_RTS); 572 } 573 } 574 575 stm32_transmit_chars(port); 576 } 577 578 /* Throttle the remote when input buffer is about to overflow. */ 579 static void stm32_throttle(struct uart_port *port) 580 { 581 struct stm32_port *stm32_port = to_stm32_port(port); 582 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 583 unsigned long flags; 584 585 spin_lock_irqsave(&port->lock, flags); 586 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 587 if (stm32_port->cr3_irq) 588 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 589 590 spin_unlock_irqrestore(&port->lock, flags); 591 } 592 593 /* Unthrottle the remote, the input buffer can now accept data. */ 594 static void stm32_unthrottle(struct uart_port *port) 595 { 596 struct stm32_port *stm32_port = to_stm32_port(port); 597 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 598 unsigned long flags; 599 600 spin_lock_irqsave(&port->lock, flags); 601 stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 602 if (stm32_port->cr3_irq) 603 stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 604 605 spin_unlock_irqrestore(&port->lock, flags); 606 } 607 608 /* Receive stop */ 609 static void stm32_stop_rx(struct uart_port *port) 610 { 611 struct stm32_port *stm32_port = to_stm32_port(port); 612 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 613 614 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 615 if (stm32_port->cr3_irq) 616 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 617 618 } 619 620 /* Handle breaks - ignored by us */ 621 static void stm32_break_ctl(struct uart_port *port, int break_state) 622 { 623 } 624 625 static int stm32_startup(struct uart_port *port) 626 { 627 struct stm32_port *stm32_port = to_stm32_port(port); 628 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 629 const char *name = to_platform_device(port->dev)->name; 630 u32 val; 631 int ret; 632 633 ret = request_threaded_irq(port->irq, stm32_interrupt, 634 stm32_threaded_interrupt, 635 IRQF_NO_SUSPEND, name, port); 636 if (ret) 637 return ret; 638 639 /* RX FIFO Flush */ 640 if (ofs->rqr != UNDEF_REG) 641 stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); 642 643 /* Tx and RX FIFO configuration */ 644 if (stm32_port->fifoen) { 645 val = readl_relaxed(port->membase + ofs->cr3); 646 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 647 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 648 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 649 writel_relaxed(val, port->membase + ofs->cr3); 650 } 651 652 /* RX FIFO enabling */ 653 val = stm32_port->cr1_irq | USART_CR1_RE; 654 if (stm32_port->fifoen) 655 val |= USART_CR1_FIFOEN; 656 stm32_set_bits(port, ofs->cr1, val); 657 658 return 0; 659 } 660 661 static void stm32_shutdown(struct uart_port *port) 662 { 663 struct stm32_port *stm32_port = to_stm32_port(port); 664 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 665 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 666 u32 val, isr; 667 int ret; 668 669 /* Disable modem control interrupts */ 670 stm32_disable_ms(port); 671 672 val = USART_CR1_TXEIE | USART_CR1_TE; 673 val |= stm32_port->cr1_irq | USART_CR1_RE; 674 val |= BIT(cfg->uart_enable_bit); 675 if (stm32_port->fifoen) 676 val |= USART_CR1_FIFOEN; 677 678 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 679 isr, (isr & USART_SR_TC), 680 10, 100000); 681 682 if (ret) 683 dev_err(port->dev, "transmission complete not set\n"); 684 685 stm32_clr_bits(port, ofs->cr1, val); 686 687 free_irq(port->irq, port); 688 } 689 690 static unsigned int stm32_get_databits(struct ktermios *termios) 691 { 692 unsigned int bits; 693 694 tcflag_t cflag = termios->c_cflag; 695 696 switch (cflag & CSIZE) { 697 /* 698 * CSIZE settings are not necessarily supported in hardware. 699 * CSIZE unsupported configurations are handled here to set word length 700 * to 8 bits word as default configuration and to print debug message. 701 */ 702 case CS5: 703 bits = 5; 704 break; 705 case CS6: 706 bits = 6; 707 break; 708 case CS7: 709 bits = 7; 710 break; 711 /* default including CS8 */ 712 default: 713 bits = 8; 714 break; 715 } 716 717 return bits; 718 } 719 720 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, 721 struct ktermios *old) 722 { 723 struct stm32_port *stm32_port = to_stm32_port(port); 724 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 725 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 726 struct serial_rs485 *rs485conf = &port->rs485; 727 unsigned int baud, bits; 728 u32 usartdiv, mantissa, fraction, oversampling; 729 tcflag_t cflag = termios->c_cflag; 730 u32 cr1, cr2, cr3; 731 unsigned long flags; 732 733 if (!stm32_port->hw_flow_control) 734 cflag &= ~CRTSCTS; 735 736 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 737 738 spin_lock_irqsave(&port->lock, flags); 739 740 /* Stop serial port and reset value */ 741 writel_relaxed(0, port->membase + ofs->cr1); 742 743 /* flush RX & TX FIFO */ 744 if (ofs->rqr != UNDEF_REG) 745 stm32_set_bits(port, ofs->rqr, 746 USART_RQR_TXFRQ | USART_RQR_RXFRQ); 747 748 cr1 = USART_CR1_TE | USART_CR1_RE; 749 if (stm32_port->fifoen) 750 cr1 |= USART_CR1_FIFOEN; 751 cr2 = 0; 752 cr3 = readl_relaxed(port->membase + ofs->cr3); 753 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE 754 | USART_CR3_TXFTCFG_MASK; 755 756 if (cflag & CSTOPB) 757 cr2 |= USART_CR2_STOP_2B; 758 759 bits = stm32_get_databits(termios); 760 stm32_port->rdr_mask = (BIT(bits) - 1); 761 762 if (cflag & PARENB) { 763 bits++; 764 cr1 |= USART_CR1_PCE; 765 } 766 767 /* 768 * Word length configuration: 769 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 770 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 771 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 772 * M0 and M1 already cleared by cr1 initialization. 773 */ 774 if (bits == 9) 775 cr1 |= USART_CR1_M0; 776 else if ((bits == 7) && cfg->has_7bits_data) 777 cr1 |= USART_CR1_M1; 778 else if (bits != 8) 779 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 780 , bits); 781 782 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 783 stm32_port->fifoen)) { 784 if (cflag & CSTOPB) 785 bits = bits + 3; /* 1 start bit + 2 stop bits */ 786 else 787 bits = bits + 2; /* 1 start bit + 1 stop bit */ 788 789 /* RX timeout irq to occur after last stop bit + bits */ 790 stm32_port->cr1_irq = USART_CR1_RTOIE; 791 writel_relaxed(bits, port->membase + ofs->rtor); 792 cr2 |= USART_CR2_RTOEN; 793 /* Not using dma, enable fifo threshold irq */ 794 if (!stm32_port->rx_ch) 795 stm32_port->cr3_irq = USART_CR3_RXFTIE; 796 } 797 798 cr1 |= stm32_port->cr1_irq; 799 cr3 |= stm32_port->cr3_irq; 800 801 if (cflag & PARODD) 802 cr1 |= USART_CR1_PS; 803 804 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 805 if (cflag & CRTSCTS) { 806 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 807 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 808 } 809 810 /* Handle modem control interrupts */ 811 if (UART_ENABLE_MS(port, termios->c_cflag)) 812 stm32_enable_ms(port); 813 else 814 stm32_disable_ms(port); 815 816 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 817 818 /* 819 * The USART supports 16 or 8 times oversampling. 820 * By default we prefer 16 times oversampling, so that the receiver 821 * has a better tolerance to clock deviations. 822 * 8 times oversampling is only used to achieve higher speeds. 823 */ 824 if (usartdiv < 16) { 825 oversampling = 8; 826 cr1 |= USART_CR1_OVER8; 827 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); 828 } else { 829 oversampling = 16; 830 cr1 &= ~USART_CR1_OVER8; 831 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 832 } 833 834 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 835 fraction = usartdiv % oversampling; 836 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 837 838 uart_update_timeout(port, cflag, baud); 839 840 port->read_status_mask = USART_SR_ORE; 841 if (termios->c_iflag & INPCK) 842 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 843 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 844 port->read_status_mask |= USART_SR_FE; 845 846 /* Characters to ignore */ 847 port->ignore_status_mask = 0; 848 if (termios->c_iflag & IGNPAR) 849 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 850 if (termios->c_iflag & IGNBRK) { 851 port->ignore_status_mask |= USART_SR_FE; 852 /* 853 * If we're ignoring parity and break indicators, 854 * ignore overruns too (for real raw support). 855 */ 856 if (termios->c_iflag & IGNPAR) 857 port->ignore_status_mask |= USART_SR_ORE; 858 } 859 860 /* Ignore all characters if CREAD is not set */ 861 if ((termios->c_cflag & CREAD) == 0) 862 port->ignore_status_mask |= USART_SR_DUMMY_RX; 863 864 if (stm32_port->rx_ch) 865 cr3 |= USART_CR3_DMAR; 866 867 if (rs485conf->flags & SER_RS485_ENABLED) { 868 stm32_config_reg_rs485(&cr1, &cr3, 869 rs485conf->delay_rts_before_send, 870 rs485conf->delay_rts_after_send, baud); 871 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 872 cr3 &= ~USART_CR3_DEP; 873 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 874 } else { 875 cr3 |= USART_CR3_DEP; 876 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 877 } 878 879 } else { 880 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 881 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 882 } 883 884 writel_relaxed(cr3, port->membase + ofs->cr3); 885 writel_relaxed(cr2, port->membase + ofs->cr2); 886 writel_relaxed(cr1, port->membase + ofs->cr1); 887 888 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 889 spin_unlock_irqrestore(&port->lock, flags); 890 } 891 892 static const char *stm32_type(struct uart_port *port) 893 { 894 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 895 } 896 897 static void stm32_release_port(struct uart_port *port) 898 { 899 } 900 901 static int stm32_request_port(struct uart_port *port) 902 { 903 return 0; 904 } 905 906 static void stm32_config_port(struct uart_port *port, int flags) 907 { 908 if (flags & UART_CONFIG_TYPE) 909 port->type = PORT_STM32; 910 } 911 912 static int 913 stm32_verify_port(struct uart_port *port, struct serial_struct *ser) 914 { 915 /* No user changeable parameters */ 916 return -EINVAL; 917 } 918 919 static void stm32_pm(struct uart_port *port, unsigned int state, 920 unsigned int oldstate) 921 { 922 struct stm32_port *stm32port = container_of(port, 923 struct stm32_port, port); 924 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 925 struct stm32_usart_config *cfg = &stm32port->info->cfg; 926 unsigned long flags = 0; 927 928 switch (state) { 929 case UART_PM_STATE_ON: 930 pm_runtime_get_sync(port->dev); 931 break; 932 case UART_PM_STATE_OFF: 933 spin_lock_irqsave(&port->lock, flags); 934 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 935 spin_unlock_irqrestore(&port->lock, flags); 936 pm_runtime_put_sync(port->dev); 937 break; 938 } 939 } 940 941 static const struct uart_ops stm32_uart_ops = { 942 .tx_empty = stm32_tx_empty, 943 .set_mctrl = stm32_set_mctrl, 944 .get_mctrl = stm32_get_mctrl, 945 .stop_tx = stm32_stop_tx, 946 .start_tx = stm32_start_tx, 947 .throttle = stm32_throttle, 948 .unthrottle = stm32_unthrottle, 949 .stop_rx = stm32_stop_rx, 950 .enable_ms = stm32_enable_ms, 951 .break_ctl = stm32_break_ctl, 952 .startup = stm32_startup, 953 .shutdown = stm32_shutdown, 954 .set_termios = stm32_set_termios, 955 .pm = stm32_pm, 956 .type = stm32_type, 957 .release_port = stm32_release_port, 958 .request_port = stm32_request_port, 959 .config_port = stm32_config_port, 960 .verify_port = stm32_verify_port, 961 }; 962 963 static int stm32_init_port(struct stm32_port *stm32port, 964 struct platform_device *pdev) 965 { 966 struct uart_port *port = &stm32port->port; 967 struct resource *res; 968 int ret; 969 970 port->iotype = UPIO_MEM; 971 port->flags = UPF_BOOT_AUTOCONF; 972 port->ops = &stm32_uart_ops; 973 port->dev = &pdev->dev; 974 port->fifosize = stm32port->info->cfg.fifosize; 975 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 976 977 ret = platform_get_irq(pdev, 0); 978 if (ret <= 0) 979 return ret ? : -ENODEV; 980 port->irq = ret; 981 982 port->rs485_config = stm32_config_rs485; 983 984 ret = stm32_init_rs485(port, pdev); 985 if (ret) 986 return ret; 987 988 if (stm32port->info->cfg.has_wakeup) { 989 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); 990 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 991 return stm32port->wakeirq ? : -ENODEV; 992 } 993 994 stm32port->fifoen = stm32port->info->cfg.has_fifo; 995 996 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 997 port->membase = devm_ioremap_resource(&pdev->dev, res); 998 if (IS_ERR(port->membase)) 999 return PTR_ERR(port->membase); 1000 port->mapbase = res->start; 1001 1002 spin_lock_init(&port->lock); 1003 1004 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1005 if (IS_ERR(stm32port->clk)) 1006 return PTR_ERR(stm32port->clk); 1007 1008 /* Ensure that clk rate is correct by enabling the clk */ 1009 ret = clk_prepare_enable(stm32port->clk); 1010 if (ret) 1011 return ret; 1012 1013 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1014 if (!stm32port->port.uartclk) { 1015 ret = -EINVAL; 1016 goto err_clk; 1017 } 1018 1019 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1020 if (IS_ERR(stm32port->gpios)) { 1021 ret = PTR_ERR(stm32port->gpios); 1022 goto err_clk; 1023 } 1024 1025 /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */ 1026 if (stm32port->hw_flow_control) { 1027 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1028 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1029 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1030 ret = -EINVAL; 1031 goto err_clk; 1032 } 1033 } 1034 1035 return ret; 1036 1037 err_clk: 1038 clk_disable_unprepare(stm32port->clk); 1039 1040 return ret; 1041 } 1042 1043 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) 1044 { 1045 struct device_node *np = pdev->dev.of_node; 1046 int id; 1047 1048 if (!np) 1049 return NULL; 1050 1051 id = of_alias_get_id(np, "serial"); 1052 if (id < 0) { 1053 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1054 return NULL; 1055 } 1056 1057 if (WARN_ON(id >= STM32_MAX_PORTS)) 1058 return NULL; 1059 1060 stm32_ports[id].hw_flow_control = 1061 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1062 of_property_read_bool (np, "uart-has-rtscts"); 1063 stm32_ports[id].port.line = id; 1064 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1065 stm32_ports[id].cr3_irq = 0; 1066 stm32_ports[id].last_res = RX_BUF_L; 1067 return &stm32_ports[id]; 1068 } 1069 1070 #ifdef CONFIG_OF 1071 static const struct of_device_id stm32_match[] = { 1072 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1073 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1074 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1075 {}, 1076 }; 1077 1078 MODULE_DEVICE_TABLE(of, stm32_match); 1079 #endif 1080 1081 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port, 1082 struct platform_device *pdev) 1083 { 1084 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1085 struct uart_port *port = &stm32port->port; 1086 struct device *dev = &pdev->dev; 1087 struct dma_slave_config config; 1088 struct dma_async_tx_descriptor *desc = NULL; 1089 int ret; 1090 1091 /* Request DMA RX channel */ 1092 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1093 if (!stm32port->rx_ch) { 1094 dev_info(dev, "rx dma alloc failed\n"); 1095 return -ENODEV; 1096 } 1097 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1098 &stm32port->rx_dma_buf, 1099 GFP_KERNEL); 1100 if (!stm32port->rx_buf) { 1101 ret = -ENOMEM; 1102 goto alloc_err; 1103 } 1104 1105 /* Configure DMA channel */ 1106 memset(&config, 0, sizeof(config)); 1107 config.src_addr = port->mapbase + ofs->rdr; 1108 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1109 1110 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1111 if (ret < 0) { 1112 dev_err(dev, "rx dma channel config failed\n"); 1113 ret = -ENODEV; 1114 goto config_err; 1115 } 1116 1117 /* Prepare a DMA cyclic transaction */ 1118 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1119 stm32port->rx_dma_buf, 1120 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1121 DMA_PREP_INTERRUPT); 1122 if (!desc) { 1123 dev_err(dev, "rx dma prep cyclic failed\n"); 1124 ret = -ENODEV; 1125 goto config_err; 1126 } 1127 1128 /* No callback as dma buffer is drained on usart interrupt */ 1129 desc->callback = NULL; 1130 desc->callback_param = NULL; 1131 1132 /* Push current DMA transaction in the pending queue */ 1133 dmaengine_submit(desc); 1134 1135 /* Issue pending DMA requests */ 1136 dma_async_issue_pending(stm32port->rx_ch); 1137 1138 return 0; 1139 1140 config_err: 1141 dma_free_coherent(&pdev->dev, 1142 RX_BUF_L, stm32port->rx_buf, 1143 stm32port->rx_dma_buf); 1144 1145 alloc_err: 1146 dma_release_channel(stm32port->rx_ch); 1147 stm32port->rx_ch = NULL; 1148 1149 return ret; 1150 } 1151 1152 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port, 1153 struct platform_device *pdev) 1154 { 1155 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1156 struct uart_port *port = &stm32port->port; 1157 struct device *dev = &pdev->dev; 1158 struct dma_slave_config config; 1159 int ret; 1160 1161 stm32port->tx_dma_busy = false; 1162 1163 /* Request DMA TX channel */ 1164 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1165 if (!stm32port->tx_ch) { 1166 dev_info(dev, "tx dma alloc failed\n"); 1167 return -ENODEV; 1168 } 1169 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1170 &stm32port->tx_dma_buf, 1171 GFP_KERNEL); 1172 if (!stm32port->tx_buf) { 1173 ret = -ENOMEM; 1174 goto alloc_err; 1175 } 1176 1177 /* Configure DMA channel */ 1178 memset(&config, 0, sizeof(config)); 1179 config.dst_addr = port->mapbase + ofs->tdr; 1180 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1181 1182 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1183 if (ret < 0) { 1184 dev_err(dev, "tx dma channel config failed\n"); 1185 ret = -ENODEV; 1186 goto config_err; 1187 } 1188 1189 return 0; 1190 1191 config_err: 1192 dma_free_coherent(&pdev->dev, 1193 TX_BUF_L, stm32port->tx_buf, 1194 stm32port->tx_dma_buf); 1195 1196 alloc_err: 1197 dma_release_channel(stm32port->tx_ch); 1198 stm32port->tx_ch = NULL; 1199 1200 return ret; 1201 } 1202 1203 static int stm32_serial_probe(struct platform_device *pdev) 1204 { 1205 const struct of_device_id *match; 1206 struct stm32_port *stm32port; 1207 int ret; 1208 1209 stm32port = stm32_of_get_stm32_port(pdev); 1210 if (!stm32port) 1211 return -ENODEV; 1212 1213 match = of_match_device(stm32_match, &pdev->dev); 1214 if (match && match->data) 1215 stm32port->info = (struct stm32_usart_info *)match->data; 1216 else 1217 return -EINVAL; 1218 1219 ret = stm32_init_port(stm32port, pdev); 1220 if (ret) 1221 return ret; 1222 1223 if (stm32port->wakeirq > 0) { 1224 ret = device_init_wakeup(&pdev->dev, true); 1225 if (ret) 1226 goto err_uninit; 1227 1228 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1229 stm32port->wakeirq); 1230 if (ret) 1231 goto err_nowup; 1232 1233 device_set_wakeup_enable(&pdev->dev, false); 1234 } 1235 1236 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1237 if (ret) 1238 goto err_wirq; 1239 1240 ret = stm32_of_dma_rx_probe(stm32port, pdev); 1241 if (ret) 1242 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1243 1244 ret = stm32_of_dma_tx_probe(stm32port, pdev); 1245 if (ret) 1246 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1247 1248 platform_set_drvdata(pdev, &stm32port->port); 1249 1250 pm_runtime_get_noresume(&pdev->dev); 1251 pm_runtime_set_active(&pdev->dev); 1252 pm_runtime_enable(&pdev->dev); 1253 pm_runtime_put_sync(&pdev->dev); 1254 1255 return 0; 1256 1257 err_wirq: 1258 if (stm32port->wakeirq > 0) 1259 dev_pm_clear_wake_irq(&pdev->dev); 1260 1261 err_nowup: 1262 if (stm32port->wakeirq > 0) 1263 device_init_wakeup(&pdev->dev, false); 1264 1265 err_uninit: 1266 clk_disable_unprepare(stm32port->clk); 1267 1268 return ret; 1269 } 1270 1271 static int stm32_serial_remove(struct platform_device *pdev) 1272 { 1273 struct uart_port *port = platform_get_drvdata(pdev); 1274 struct stm32_port *stm32_port = to_stm32_port(port); 1275 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1276 int err; 1277 1278 pm_runtime_get_sync(&pdev->dev); 1279 1280 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1281 1282 if (stm32_port->rx_ch) 1283 dma_release_channel(stm32_port->rx_ch); 1284 1285 if (stm32_port->rx_dma_buf) 1286 dma_free_coherent(&pdev->dev, 1287 RX_BUF_L, stm32_port->rx_buf, 1288 stm32_port->rx_dma_buf); 1289 1290 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1291 1292 if (stm32_port->tx_ch) 1293 dma_release_channel(stm32_port->tx_ch); 1294 1295 if (stm32_port->tx_dma_buf) 1296 dma_free_coherent(&pdev->dev, 1297 TX_BUF_L, stm32_port->tx_buf, 1298 stm32_port->tx_dma_buf); 1299 1300 if (stm32_port->wakeirq > 0) { 1301 dev_pm_clear_wake_irq(&pdev->dev); 1302 device_init_wakeup(&pdev->dev, false); 1303 } 1304 1305 clk_disable_unprepare(stm32_port->clk); 1306 1307 err = uart_remove_one_port(&stm32_usart_driver, port); 1308 1309 pm_runtime_disable(&pdev->dev); 1310 pm_runtime_put_noidle(&pdev->dev); 1311 1312 return err; 1313 } 1314 1315 1316 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1317 static void stm32_console_putchar(struct uart_port *port, int ch) 1318 { 1319 struct stm32_port *stm32_port = to_stm32_port(port); 1320 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1321 1322 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1323 cpu_relax(); 1324 1325 writel_relaxed(ch, port->membase + ofs->tdr); 1326 } 1327 1328 static void stm32_console_write(struct console *co, const char *s, unsigned cnt) 1329 { 1330 struct uart_port *port = &stm32_ports[co->index].port; 1331 struct stm32_port *stm32_port = to_stm32_port(port); 1332 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1333 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1334 unsigned long flags; 1335 u32 old_cr1, new_cr1; 1336 int locked = 1; 1337 1338 local_irq_save(flags); 1339 if (port->sysrq) 1340 locked = 0; 1341 else if (oops_in_progress) 1342 locked = spin_trylock(&port->lock); 1343 else 1344 spin_lock(&port->lock); 1345 1346 /* Save and disable interrupts, enable the transmitter */ 1347 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1348 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1349 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1350 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1351 1352 uart_console_write(port, s, cnt, stm32_console_putchar); 1353 1354 /* Restore interrupt state */ 1355 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1356 1357 if (locked) 1358 spin_unlock(&port->lock); 1359 local_irq_restore(flags); 1360 } 1361 1362 static int stm32_console_setup(struct console *co, char *options) 1363 { 1364 struct stm32_port *stm32port; 1365 int baud = 9600; 1366 int bits = 8; 1367 int parity = 'n'; 1368 int flow = 'n'; 1369 1370 if (co->index >= STM32_MAX_PORTS) 1371 return -ENODEV; 1372 1373 stm32port = &stm32_ports[co->index]; 1374 1375 /* 1376 * This driver does not support early console initialization 1377 * (use ARM early printk support instead), so we only expect 1378 * this to be called during the uart port registration when the 1379 * driver gets probed and the port should be mapped at that point. 1380 */ 1381 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) 1382 return -ENXIO; 1383 1384 if (options) 1385 uart_parse_options(options, &baud, &parity, &bits, &flow); 1386 1387 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1388 } 1389 1390 static struct console stm32_console = { 1391 .name = STM32_SERIAL_NAME, 1392 .device = uart_console_device, 1393 .write = stm32_console_write, 1394 .setup = stm32_console_setup, 1395 .flags = CON_PRINTBUFFER, 1396 .index = -1, 1397 .data = &stm32_usart_driver, 1398 }; 1399 1400 #define STM32_SERIAL_CONSOLE (&stm32_console) 1401 1402 #else 1403 #define STM32_SERIAL_CONSOLE NULL 1404 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1405 1406 static struct uart_driver stm32_usart_driver = { 1407 .driver_name = DRIVER_NAME, 1408 .dev_name = STM32_SERIAL_NAME, 1409 .major = 0, 1410 .minor = 0, 1411 .nr = STM32_MAX_PORTS, 1412 .cons = STM32_SERIAL_CONSOLE, 1413 }; 1414 1415 static void __maybe_unused stm32_serial_enable_wakeup(struct uart_port *port, 1416 bool enable) 1417 { 1418 struct stm32_port *stm32_port = to_stm32_port(port); 1419 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1420 struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1421 u32 val; 1422 1423 if (stm32_port->wakeirq <= 0) 1424 return; 1425 1426 if (enable) { 1427 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1428 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM); 1429 val = readl_relaxed(port->membase + ofs->cr3); 1430 val &= ~USART_CR3_WUS_MASK; 1431 /* Enable Wake up interrupt from low power on start bit */ 1432 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1433 writel_relaxed(val, port->membase + ofs->cr3); 1434 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1435 } else { 1436 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1437 } 1438 } 1439 1440 static int __maybe_unused stm32_serial_suspend(struct device *dev) 1441 { 1442 struct uart_port *port = dev_get_drvdata(dev); 1443 1444 uart_suspend_port(&stm32_usart_driver, port); 1445 1446 if (device_may_wakeup(dev)) 1447 stm32_serial_enable_wakeup(port, true); 1448 else 1449 stm32_serial_enable_wakeup(port, false); 1450 1451 /* 1452 * When "no_console_suspend" is enabled, keep the pinctrl default state 1453 * and rely on bootloader stage to restore this state upon resume. 1454 * Otherwise, apply the idle or sleep states depending on wakeup 1455 * capabilities. 1456 */ 1457 if (console_suspend_enabled || !uart_console(port)) { 1458 if (device_may_wakeup(dev)) 1459 pinctrl_pm_select_idle_state(dev); 1460 else 1461 pinctrl_pm_select_sleep_state(dev); 1462 } 1463 1464 return 0; 1465 } 1466 1467 static int __maybe_unused stm32_serial_resume(struct device *dev) 1468 { 1469 struct uart_port *port = dev_get_drvdata(dev); 1470 1471 pinctrl_pm_select_default_state(dev); 1472 1473 if (device_may_wakeup(dev)) 1474 stm32_serial_enable_wakeup(port, false); 1475 1476 return uart_resume_port(&stm32_usart_driver, port); 1477 } 1478 1479 static int __maybe_unused stm32_serial_runtime_suspend(struct device *dev) 1480 { 1481 struct uart_port *port = dev_get_drvdata(dev); 1482 struct stm32_port *stm32port = container_of(port, 1483 struct stm32_port, port); 1484 1485 clk_disable_unprepare(stm32port->clk); 1486 1487 return 0; 1488 } 1489 1490 static int __maybe_unused stm32_serial_runtime_resume(struct device *dev) 1491 { 1492 struct uart_port *port = dev_get_drvdata(dev); 1493 struct stm32_port *stm32port = container_of(port, 1494 struct stm32_port, port); 1495 1496 return clk_prepare_enable(stm32port->clk); 1497 } 1498 1499 static const struct dev_pm_ops stm32_serial_pm_ops = { 1500 SET_RUNTIME_PM_OPS(stm32_serial_runtime_suspend, 1501 stm32_serial_runtime_resume, NULL) 1502 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume) 1503 }; 1504 1505 static struct platform_driver stm32_serial_driver = { 1506 .probe = stm32_serial_probe, 1507 .remove = stm32_serial_remove, 1508 .driver = { 1509 .name = DRIVER_NAME, 1510 .pm = &stm32_serial_pm_ops, 1511 .of_match_table = of_match_ptr(stm32_match), 1512 }, 1513 }; 1514 1515 static int __init usart_init(void) 1516 { 1517 static char banner[] __initdata = "STM32 USART driver initialized"; 1518 int ret; 1519 1520 pr_info("%s\n", banner); 1521 1522 ret = uart_register_driver(&stm32_usart_driver); 1523 if (ret) 1524 return ret; 1525 1526 ret = platform_driver_register(&stm32_serial_driver); 1527 if (ret) 1528 uart_unregister_driver(&stm32_usart_driver); 1529 1530 return ret; 1531 } 1532 1533 static void __exit usart_exit(void) 1534 { 1535 platform_driver_unregister(&stm32_serial_driver); 1536 uart_unregister_driver(&stm32_usart_driver); 1537 } 1538 1539 module_init(usart_init); 1540 module_exit(usart_exit); 1541 1542 MODULE_ALIAS("platform:" DRIVER_NAME); 1543 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1544 MODULE_LICENSE("GPL v2"); 1545