1 #include <linux/bitops.h> 2 #include <linux/serial_core.h> 3 #include <linux/io.h> 4 #include <linux/gpio.h> 5 6 #define SCI_MAJOR 204 7 #define SCI_MINOR_START 8 8 9 10 /* 11 * SCI register subset common for all port types. 12 * Not all registers will exist on all parts. 13 */ 14 enum { 15 SCSMR, /* Serial Mode Register */ 16 SCBRR, /* Bit Rate Register */ 17 SCSCR, /* Serial Control Register */ 18 SCxSR, /* Serial Status Register */ 19 SCFCR, /* FIFO Control Register */ 20 SCFDR, /* FIFO Data Count Register */ 21 SCxTDR, /* Transmit (FIFO) Data Register */ 22 SCxRDR, /* Receive (FIFO) Data Register */ 23 SCLSR, /* Line Status Register */ 24 SCTFDR, /* Transmit FIFO Data Count Register */ 25 SCRFDR, /* Receive FIFO Data Count Register */ 26 SCSPTR, /* Serial Port Register */ 27 HSSRR, /* Sampling Rate Register */ 28 SCPCR, /* Serial Port Control Register */ 29 SCPDR, /* Serial Port Data Register */ 30 SCDL, /* BRG Frequency Division Register */ 31 SCCKS, /* BRG Clock Select Register */ 32 33 SCIx_NR_REGS, 34 }; 35 36 37 /* SCSMR (Serial Mode Register) */ 38 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */ 39 #define SCSMR_PE BIT(5) /* Parity Enable */ 40 #define SCSMR_ODD BIT(4) /* Odd Parity */ 41 #define SCSMR_STOP BIT(3) /* Stop Bit Length */ 42 #define SCSMR_CKS 0x0003 /* Clock Select */ 43 44 /* Serial Control Register, SCIFA/SCIFB only bits */ 45 #define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */ 46 #define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */ 47 48 /* SCxSR (Serial Status Register) on SCI */ 49 #define SCI_TDRE BIT(7) /* Transmit Data Register Empty */ 50 #define SCI_RDRF BIT(6) /* Receive Data Register Full */ 51 #define SCI_ORER BIT(5) /* Overrun Error */ 52 #define SCI_FER BIT(4) /* Framing Error */ 53 #define SCI_PER BIT(3) /* Parity Error */ 54 #define SCI_TEND BIT(2) /* Transmit End */ 55 #define SCI_RESERVED 0x03 /* All reserved bits */ 56 57 #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER) 58 59 #define SCI_RDxF_CLEAR (u32)(~(SCI_RESERVED | SCI_RDRF)) 60 #define SCI_ERROR_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)) 61 #define SCI_TDxE_CLEAR (u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE)) 62 #define SCI_BREAK_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)) 63 64 /* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */ 65 #define SCIF_ER BIT(7) /* Receive Error */ 66 #define SCIF_TEND BIT(6) /* Transmission End */ 67 #define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */ 68 #define SCIF_BRK BIT(4) /* Break Detect */ 69 #define SCIF_FER BIT(3) /* Framing Error */ 70 #define SCIF_PER BIT(2) /* Parity Error */ 71 #define SCIF_RDF BIT(1) /* Receive FIFO Data Full */ 72 #define SCIF_DR BIT(0) /* Receive Data Ready */ 73 /* SCIF only (optional) */ 74 #define SCIF_PERC 0xf000 /* Number of Parity Errors */ 75 #define SCIF_FERC 0x0f00 /* Number of Framing Errors */ 76 /*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */ 77 #define SCIFA_ORER BIT(9) /* Overrun Error */ 78 79 #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER) 80 81 #define SCIF_RDxF_CLEAR (u32)(~(SCIF_DR | SCIF_RDF)) 82 #define SCIF_ERROR_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_ER)) 83 #define SCIF_TDxE_CLEAR (u32)(~(SCIF_TDFE)) 84 #define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK)) 85 86 /* SCFCR (FIFO Control Register) */ 87 #define SCFCR_MCE BIT(3) /* Modem Control Enable */ 88 #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */ 89 #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */ 90 #define SCFCR_LOOP BIT(0) /* Loopback Test */ 91 92 /* SCLSR (Line Status Register) on (H)SCIF */ 93 #define SCLSR_ORER BIT(0) /* Overrun Error */ 94 95 /* SCSPTR (Serial Port Register), optional */ 96 #define SCSPTR_RTSIO BIT(7) /* Serial Port RTS Pin Input/Output */ 97 #define SCSPTR_RTSDT BIT(6) /* Serial Port RTS Pin Data */ 98 #define SCSPTR_CTSIO BIT(5) /* Serial Port CTS Pin Input/Output */ 99 #define SCSPTR_CTSDT BIT(4) /* Serial Port CTS Pin Data */ 100 #define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */ 101 #define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */ 102 103 /* HSSRR HSCIF */ 104 #define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */ 105 106 /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */ 107 #define SCPCR_RTSC BIT(4) /* Serial Port RTS Pin / Output Pin */ 108 #define SCPCR_CTSC BIT(3) /* Serial Port CTS Pin / Input Pin */ 109 110 /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */ 111 #define SCPDR_RTSD BIT(4) /* Serial Port RTS Output Pin Data */ 112 #define SCPDR_CTSD BIT(3) /* Serial Port CTS Input Pin Data */ 113 114 /* 115 * BRG Clock Select Register (Some SCIF and HSCIF) 116 * The Baud Rate Generator for external clock can provide a clock source for 117 * the sampling clock. It outputs either its frequency divided clock, or the 118 * (undivided) (H)SCK external clock. 119 */ 120 #define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */ 121 #define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */ 122 123 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 124 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 125 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 126 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 127 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 128 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 129 130 #define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask) 131 132 #define SCxSR_RDxF_CLEAR(port) \ 133 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR) 134 #define SCxSR_ERROR_CLEAR(port) \ 135 (to_sci_port(port)->error_clear) 136 #define SCxSR_TDxE_CLEAR(port) \ 137 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR) 138 #define SCxSR_BREAK_CLEAR(port) \ 139 (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR) 140