1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 * 18 * This file is subject to the terms and conditions of the GNU General Public 19 * License. See the file "COPYING" in the main directory of this archive 20 * for more details. 21 */ 22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 23 #define SUPPORT_SYSRQ 24 #endif 25 26 #undef DEBUG 27 28 #include <linux/clk.h> 29 #include <linux/console.h> 30 #include <linux/ctype.h> 31 #include <linux/cpufreq.h> 32 #include <linux/delay.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/err.h> 36 #include <linux/errno.h> 37 #include <linux/init.h> 38 #include <linux/interrupt.h> 39 #include <linux/ioport.h> 40 #include <linux/major.h> 41 #include <linux/module.h> 42 #include <linux/mm.h> 43 #include <linux/of.h> 44 #include <linux/of_device.h> 45 #include <linux/platform_device.h> 46 #include <linux/pm_runtime.h> 47 #include <linux/scatterlist.h> 48 #include <linux/serial.h> 49 #include <linux/serial_sci.h> 50 #include <linux/sh_dma.h> 51 #include <linux/slab.h> 52 #include <linux/string.h> 53 #include <linux/sysrq.h> 54 #include <linux/timer.h> 55 #include <linux/tty.h> 56 #include <linux/tty_flip.h> 57 58 #ifdef CONFIG_SUPERH 59 #include <asm/sh_bios.h> 60 #endif 61 62 #include "serial_mctrl_gpio.h" 63 #include "sh-sci.h" 64 65 /* Offsets into the sci_port->irqs array */ 66 enum { 67 SCIx_ERI_IRQ, 68 SCIx_RXI_IRQ, 69 SCIx_TXI_IRQ, 70 SCIx_BRI_IRQ, 71 SCIx_NR_IRQS, 72 73 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 74 }; 75 76 #define SCIx_IRQ_IS_MUXED(port) \ 77 ((port)->irqs[SCIx_ERI_IRQ] == \ 78 (port)->irqs[SCIx_RXI_IRQ]) || \ 79 ((port)->irqs[SCIx_ERI_IRQ] && \ 80 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 81 82 enum SCI_CLKS { 83 SCI_FCK, /* Functional Clock */ 84 SCI_SCK, /* Optional External Clock */ 85 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 86 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 87 SCI_NUM_CLKS 88 }; 89 90 /* Bit x set means sampling rate x + 1 is supported */ 91 #define SCI_SR(x) BIT((x) - 1) 92 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 93 94 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 95 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 96 SCI_SR(19) | SCI_SR(27) 97 98 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 99 #define max_sr(_port) fls((_port)->sampling_rate_mask) 100 101 /* Iterate over all supported sampling rates, from high to low */ 102 #define for_each_sr(_sr, _port) \ 103 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 104 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 105 106 struct plat_sci_reg { 107 u8 offset, size; 108 }; 109 110 struct sci_port_params { 111 const struct plat_sci_reg regs[SCIx_NR_REGS]; 112 unsigned int fifosize; 113 unsigned int overrun_reg; 114 unsigned int overrun_mask; 115 unsigned int sampling_rate_mask; 116 unsigned int error_mask; 117 unsigned int error_clear; 118 }; 119 120 struct sci_port { 121 struct uart_port port; 122 123 /* Platform configuration */ 124 const struct sci_port_params *params; 125 const struct plat_sci_port *cfg; 126 unsigned int sampling_rate_mask; 127 resource_size_t reg_size; 128 struct mctrl_gpios *gpios; 129 130 /* Clocks */ 131 struct clk *clks[SCI_NUM_CLKS]; 132 unsigned long clk_rates[SCI_NUM_CLKS]; 133 134 int irqs[SCIx_NR_IRQS]; 135 char *irqstr[SCIx_NR_IRQS]; 136 137 struct dma_chan *chan_tx; 138 struct dma_chan *chan_rx; 139 140 #ifdef CONFIG_SERIAL_SH_SCI_DMA 141 dma_cookie_t cookie_tx; 142 dma_cookie_t cookie_rx[2]; 143 dma_cookie_t active_rx; 144 dma_addr_t tx_dma_addr; 145 unsigned int tx_dma_len; 146 struct scatterlist sg_rx[2]; 147 void *rx_buf[2]; 148 size_t buf_len_rx; 149 struct work_struct work_tx; 150 struct timer_list rx_timer; 151 unsigned int rx_timeout; 152 #endif 153 unsigned int rx_frame; 154 int rx_trigger; 155 struct timer_list rx_fifo_timer; 156 int rx_fifo_timeout; 157 u16 hscif_tot; 158 159 bool has_rtscts; 160 bool autorts; 161 }; 162 163 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 164 165 static struct sci_port sci_ports[SCI_NPORTS]; 166 static struct uart_driver sci_uart_driver; 167 168 static inline struct sci_port * 169 to_sci_port(struct uart_port *uart) 170 { 171 return container_of(uart, struct sci_port, port); 172 } 173 174 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 175 /* 176 * Common SCI definitions, dependent on the port's regshift 177 * value. 178 */ 179 [SCIx_SCI_REGTYPE] = { 180 .regs = { 181 [SCSMR] = { 0x00, 8 }, 182 [SCBRR] = { 0x01, 8 }, 183 [SCSCR] = { 0x02, 8 }, 184 [SCxTDR] = { 0x03, 8 }, 185 [SCxSR] = { 0x04, 8 }, 186 [SCxRDR] = { 0x05, 8 }, 187 }, 188 .fifosize = 1, 189 .overrun_reg = SCxSR, 190 .overrun_mask = SCI_ORER, 191 .sampling_rate_mask = SCI_SR(32), 192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 194 }, 195 196 /* 197 * Common definitions for legacy IrDA ports. 198 */ 199 [SCIx_IRDA_REGTYPE] = { 200 .regs = { 201 [SCSMR] = { 0x00, 8 }, 202 [SCBRR] = { 0x02, 8 }, 203 [SCSCR] = { 0x04, 8 }, 204 [SCxTDR] = { 0x06, 8 }, 205 [SCxSR] = { 0x08, 16 }, 206 [SCxRDR] = { 0x0a, 8 }, 207 [SCFCR] = { 0x0c, 8 }, 208 [SCFDR] = { 0x0e, 16 }, 209 }, 210 .fifosize = 1, 211 .overrun_reg = SCxSR, 212 .overrun_mask = SCI_ORER, 213 .sampling_rate_mask = SCI_SR(32), 214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 216 }, 217 218 /* 219 * Common SCIFA definitions. 220 */ 221 [SCIx_SCIFA_REGTYPE] = { 222 .regs = { 223 [SCSMR] = { 0x00, 16 }, 224 [SCBRR] = { 0x04, 8 }, 225 [SCSCR] = { 0x08, 16 }, 226 [SCxTDR] = { 0x20, 8 }, 227 [SCxSR] = { 0x14, 16 }, 228 [SCxRDR] = { 0x24, 8 }, 229 [SCFCR] = { 0x18, 16 }, 230 [SCFDR] = { 0x1c, 16 }, 231 [SCPCR] = { 0x30, 16 }, 232 [SCPDR] = { 0x34, 16 }, 233 }, 234 .fifosize = 64, 235 .overrun_reg = SCxSR, 236 .overrun_mask = SCIFA_ORER, 237 .sampling_rate_mask = SCI_SR_SCIFAB, 238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 240 }, 241 242 /* 243 * Common SCIFB definitions. 244 */ 245 [SCIx_SCIFB_REGTYPE] = { 246 .regs = { 247 [SCSMR] = { 0x00, 16 }, 248 [SCBRR] = { 0x04, 8 }, 249 [SCSCR] = { 0x08, 16 }, 250 [SCxTDR] = { 0x40, 8 }, 251 [SCxSR] = { 0x14, 16 }, 252 [SCxRDR] = { 0x60, 8 }, 253 [SCFCR] = { 0x18, 16 }, 254 [SCTFDR] = { 0x38, 16 }, 255 [SCRFDR] = { 0x3c, 16 }, 256 [SCPCR] = { 0x30, 16 }, 257 [SCPDR] = { 0x34, 16 }, 258 }, 259 .fifosize = 256, 260 .overrun_reg = SCxSR, 261 .overrun_mask = SCIFA_ORER, 262 .sampling_rate_mask = SCI_SR_SCIFAB, 263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 265 }, 266 267 /* 268 * Common SH-2(A) SCIF definitions for ports with FIFO data 269 * count registers. 270 */ 271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 272 .regs = { 273 [SCSMR] = { 0x00, 16 }, 274 [SCBRR] = { 0x04, 8 }, 275 [SCSCR] = { 0x08, 16 }, 276 [SCxTDR] = { 0x0c, 8 }, 277 [SCxSR] = { 0x10, 16 }, 278 [SCxRDR] = { 0x14, 8 }, 279 [SCFCR] = { 0x18, 16 }, 280 [SCFDR] = { 0x1c, 16 }, 281 [SCSPTR] = { 0x20, 16 }, 282 [SCLSR] = { 0x24, 16 }, 283 }, 284 .fifosize = 16, 285 .overrun_reg = SCLSR, 286 .overrun_mask = SCLSR_ORER, 287 .sampling_rate_mask = SCI_SR(32), 288 .error_mask = SCIF_DEFAULT_ERROR_MASK, 289 .error_clear = SCIF_ERROR_CLEAR, 290 }, 291 292 /* 293 * Common SH-3 SCIF definitions. 294 */ 295 [SCIx_SH3_SCIF_REGTYPE] = { 296 .regs = { 297 [SCSMR] = { 0x00, 8 }, 298 [SCBRR] = { 0x02, 8 }, 299 [SCSCR] = { 0x04, 8 }, 300 [SCxTDR] = { 0x06, 8 }, 301 [SCxSR] = { 0x08, 16 }, 302 [SCxRDR] = { 0x0a, 8 }, 303 [SCFCR] = { 0x0c, 8 }, 304 [SCFDR] = { 0x0e, 16 }, 305 }, 306 .fifosize = 16, 307 .overrun_reg = SCLSR, 308 .overrun_mask = SCLSR_ORER, 309 .sampling_rate_mask = SCI_SR(32), 310 .error_mask = SCIF_DEFAULT_ERROR_MASK, 311 .error_clear = SCIF_ERROR_CLEAR, 312 }, 313 314 /* 315 * Common SH-4(A) SCIF(B) definitions. 316 */ 317 [SCIx_SH4_SCIF_REGTYPE] = { 318 .regs = { 319 [SCSMR] = { 0x00, 16 }, 320 [SCBRR] = { 0x04, 8 }, 321 [SCSCR] = { 0x08, 16 }, 322 [SCxTDR] = { 0x0c, 8 }, 323 [SCxSR] = { 0x10, 16 }, 324 [SCxRDR] = { 0x14, 8 }, 325 [SCFCR] = { 0x18, 16 }, 326 [SCFDR] = { 0x1c, 16 }, 327 [SCSPTR] = { 0x20, 16 }, 328 [SCLSR] = { 0x24, 16 }, 329 }, 330 .fifosize = 16, 331 .overrun_reg = SCLSR, 332 .overrun_mask = SCLSR_ORER, 333 .sampling_rate_mask = SCI_SR(32), 334 .error_mask = SCIF_DEFAULT_ERROR_MASK, 335 .error_clear = SCIF_ERROR_CLEAR, 336 }, 337 338 /* 339 * Common SCIF definitions for ports with a Baud Rate Generator for 340 * External Clock (BRG). 341 */ 342 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 343 .regs = { 344 [SCSMR] = { 0x00, 16 }, 345 [SCBRR] = { 0x04, 8 }, 346 [SCSCR] = { 0x08, 16 }, 347 [SCxTDR] = { 0x0c, 8 }, 348 [SCxSR] = { 0x10, 16 }, 349 [SCxRDR] = { 0x14, 8 }, 350 [SCFCR] = { 0x18, 16 }, 351 [SCFDR] = { 0x1c, 16 }, 352 [SCSPTR] = { 0x20, 16 }, 353 [SCLSR] = { 0x24, 16 }, 354 [SCDL] = { 0x30, 16 }, 355 [SCCKS] = { 0x34, 16 }, 356 }, 357 .fifosize = 16, 358 .overrun_reg = SCLSR, 359 .overrun_mask = SCLSR_ORER, 360 .sampling_rate_mask = SCI_SR(32), 361 .error_mask = SCIF_DEFAULT_ERROR_MASK, 362 .error_clear = SCIF_ERROR_CLEAR, 363 }, 364 365 /* 366 * Common HSCIF definitions. 367 */ 368 [SCIx_HSCIF_REGTYPE] = { 369 .regs = { 370 [SCSMR] = { 0x00, 16 }, 371 [SCBRR] = { 0x04, 8 }, 372 [SCSCR] = { 0x08, 16 }, 373 [SCxTDR] = { 0x0c, 8 }, 374 [SCxSR] = { 0x10, 16 }, 375 [SCxRDR] = { 0x14, 8 }, 376 [SCFCR] = { 0x18, 16 }, 377 [SCFDR] = { 0x1c, 16 }, 378 [SCSPTR] = { 0x20, 16 }, 379 [SCLSR] = { 0x24, 16 }, 380 [HSSRR] = { 0x40, 16 }, 381 [SCDL] = { 0x30, 16 }, 382 [SCCKS] = { 0x34, 16 }, 383 [HSRTRGR] = { 0x54, 16 }, 384 [HSTTRGR] = { 0x58, 16 }, 385 }, 386 .fifosize = 128, 387 .overrun_reg = SCLSR, 388 .overrun_mask = SCLSR_ORER, 389 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 390 .error_mask = SCIF_DEFAULT_ERROR_MASK, 391 .error_clear = SCIF_ERROR_CLEAR, 392 }, 393 394 /* 395 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 396 * register. 397 */ 398 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 399 .regs = { 400 [SCSMR] = { 0x00, 16 }, 401 [SCBRR] = { 0x04, 8 }, 402 [SCSCR] = { 0x08, 16 }, 403 [SCxTDR] = { 0x0c, 8 }, 404 [SCxSR] = { 0x10, 16 }, 405 [SCxRDR] = { 0x14, 8 }, 406 [SCFCR] = { 0x18, 16 }, 407 [SCFDR] = { 0x1c, 16 }, 408 [SCLSR] = { 0x24, 16 }, 409 }, 410 .fifosize = 16, 411 .overrun_reg = SCLSR, 412 .overrun_mask = SCLSR_ORER, 413 .sampling_rate_mask = SCI_SR(32), 414 .error_mask = SCIF_DEFAULT_ERROR_MASK, 415 .error_clear = SCIF_ERROR_CLEAR, 416 }, 417 418 /* 419 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 420 * count registers. 421 */ 422 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 423 .regs = { 424 [SCSMR] = { 0x00, 16 }, 425 [SCBRR] = { 0x04, 8 }, 426 [SCSCR] = { 0x08, 16 }, 427 [SCxTDR] = { 0x0c, 8 }, 428 [SCxSR] = { 0x10, 16 }, 429 [SCxRDR] = { 0x14, 8 }, 430 [SCFCR] = { 0x18, 16 }, 431 [SCFDR] = { 0x1c, 16 }, 432 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 433 [SCRFDR] = { 0x20, 16 }, 434 [SCSPTR] = { 0x24, 16 }, 435 [SCLSR] = { 0x28, 16 }, 436 }, 437 .fifosize = 16, 438 .overrun_reg = SCLSR, 439 .overrun_mask = SCLSR_ORER, 440 .sampling_rate_mask = SCI_SR(32), 441 .error_mask = SCIF_DEFAULT_ERROR_MASK, 442 .error_clear = SCIF_ERROR_CLEAR, 443 }, 444 445 /* 446 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 447 * registers. 448 */ 449 [SCIx_SH7705_SCIF_REGTYPE] = { 450 .regs = { 451 [SCSMR] = { 0x00, 16 }, 452 [SCBRR] = { 0x04, 8 }, 453 [SCSCR] = { 0x08, 16 }, 454 [SCxTDR] = { 0x20, 8 }, 455 [SCxSR] = { 0x14, 16 }, 456 [SCxRDR] = { 0x24, 8 }, 457 [SCFCR] = { 0x18, 16 }, 458 [SCFDR] = { 0x1c, 16 }, 459 }, 460 .fifosize = 64, 461 .overrun_reg = SCxSR, 462 .overrun_mask = SCIFA_ORER, 463 .sampling_rate_mask = SCI_SR(16), 464 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 465 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 466 }, 467 }; 468 469 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 470 471 /* 472 * The "offset" here is rather misleading, in that it refers to an enum 473 * value relative to the port mapping rather than the fixed offset 474 * itself, which needs to be manually retrieved from the platform's 475 * register map for the given port. 476 */ 477 static unsigned int sci_serial_in(struct uart_port *p, int offset) 478 { 479 const struct plat_sci_reg *reg = sci_getreg(p, offset); 480 481 if (reg->size == 8) 482 return ioread8(p->membase + (reg->offset << p->regshift)); 483 else if (reg->size == 16) 484 return ioread16(p->membase + (reg->offset << p->regshift)); 485 else 486 WARN(1, "Invalid register access\n"); 487 488 return 0; 489 } 490 491 static void sci_serial_out(struct uart_port *p, int offset, int value) 492 { 493 const struct plat_sci_reg *reg = sci_getreg(p, offset); 494 495 if (reg->size == 8) 496 iowrite8(value, p->membase + (reg->offset << p->regshift)); 497 else if (reg->size == 16) 498 iowrite16(value, p->membase + (reg->offset << p->regshift)); 499 else 500 WARN(1, "Invalid register access\n"); 501 } 502 503 static void sci_port_enable(struct sci_port *sci_port) 504 { 505 unsigned int i; 506 507 if (!sci_port->port.dev) 508 return; 509 510 pm_runtime_get_sync(sci_port->port.dev); 511 512 for (i = 0; i < SCI_NUM_CLKS; i++) { 513 clk_prepare_enable(sci_port->clks[i]); 514 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 515 } 516 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 517 } 518 519 static void sci_port_disable(struct sci_port *sci_port) 520 { 521 unsigned int i; 522 523 if (!sci_port->port.dev) 524 return; 525 526 for (i = SCI_NUM_CLKS; i-- > 0; ) 527 clk_disable_unprepare(sci_port->clks[i]); 528 529 pm_runtime_put_sync(sci_port->port.dev); 530 } 531 532 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 533 { 534 /* 535 * Not all ports (such as SCIFA) will support REIE. Rather than 536 * special-casing the port type, we check the port initialization 537 * IRQ enable mask to see whether the IRQ is desired at all. If 538 * it's unset, it's logically inferred that there's no point in 539 * testing for it. 540 */ 541 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 542 } 543 544 static void sci_start_tx(struct uart_port *port) 545 { 546 struct sci_port *s = to_sci_port(port); 547 unsigned short ctrl; 548 549 #ifdef CONFIG_SERIAL_SH_SCI_DMA 550 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 551 u16 new, scr = serial_port_in(port, SCSCR); 552 if (s->chan_tx) 553 new = scr | SCSCR_TDRQE; 554 else 555 new = scr & ~SCSCR_TDRQE; 556 if (new != scr) 557 serial_port_out(port, SCSCR, new); 558 } 559 560 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 561 dma_submit_error(s->cookie_tx)) { 562 s->cookie_tx = 0; 563 schedule_work(&s->work_tx); 564 } 565 #endif 566 567 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 568 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 569 ctrl = serial_port_in(port, SCSCR); 570 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 571 } 572 } 573 574 static void sci_stop_tx(struct uart_port *port) 575 { 576 unsigned short ctrl; 577 578 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 579 ctrl = serial_port_in(port, SCSCR); 580 581 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 582 ctrl &= ~SCSCR_TDRQE; 583 584 ctrl &= ~SCSCR_TIE; 585 586 serial_port_out(port, SCSCR, ctrl); 587 } 588 589 static void sci_start_rx(struct uart_port *port) 590 { 591 unsigned short ctrl; 592 593 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 594 595 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 596 ctrl &= ~SCSCR_RDRQE; 597 598 serial_port_out(port, SCSCR, ctrl); 599 } 600 601 static void sci_stop_rx(struct uart_port *port) 602 { 603 unsigned short ctrl; 604 605 ctrl = serial_port_in(port, SCSCR); 606 607 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 608 ctrl &= ~SCSCR_RDRQE; 609 610 ctrl &= ~port_rx_irq_mask(port); 611 612 serial_port_out(port, SCSCR, ctrl); 613 } 614 615 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 616 { 617 if (port->type == PORT_SCI) { 618 /* Just store the mask */ 619 serial_port_out(port, SCxSR, mask); 620 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 621 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 622 /* Only clear the status bits we want to clear */ 623 serial_port_out(port, SCxSR, 624 serial_port_in(port, SCxSR) & mask); 625 } else { 626 /* Store the mask, clear parity/framing errors */ 627 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 628 } 629 } 630 631 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 632 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 633 634 #ifdef CONFIG_CONSOLE_POLL 635 static int sci_poll_get_char(struct uart_port *port) 636 { 637 unsigned short status; 638 int c; 639 640 do { 641 status = serial_port_in(port, SCxSR); 642 if (status & SCxSR_ERRORS(port)) { 643 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 644 continue; 645 } 646 break; 647 } while (1); 648 649 if (!(status & SCxSR_RDxF(port))) 650 return NO_POLL_CHAR; 651 652 c = serial_port_in(port, SCxRDR); 653 654 /* Dummy read */ 655 serial_port_in(port, SCxSR); 656 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 657 658 return c; 659 } 660 #endif 661 662 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 663 { 664 unsigned short status; 665 666 do { 667 status = serial_port_in(port, SCxSR); 668 } while (!(status & SCxSR_TDxE(port))); 669 670 serial_port_out(port, SCxTDR, c); 671 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 672 } 673 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 674 CONFIG_SERIAL_SH_SCI_EARLYCON */ 675 676 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 677 { 678 struct sci_port *s = to_sci_port(port); 679 680 /* 681 * Use port-specific handler if provided. 682 */ 683 if (s->cfg->ops && s->cfg->ops->init_pins) { 684 s->cfg->ops->init_pins(port, cflag); 685 return; 686 } 687 688 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 689 u16 data = serial_port_in(port, SCPDR); 690 u16 ctrl = serial_port_in(port, SCPCR); 691 692 /* Enable RXD and TXD pin functions */ 693 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 694 if (to_sci_port(port)->has_rtscts) { 695 /* RTS# is output, active low, unless autorts */ 696 if (!(port->mctrl & TIOCM_RTS)) { 697 ctrl |= SCPCR_RTSC; 698 data |= SCPDR_RTSD; 699 } else if (!s->autorts) { 700 ctrl |= SCPCR_RTSC; 701 data &= ~SCPDR_RTSD; 702 } else { 703 /* Enable RTS# pin function */ 704 ctrl &= ~SCPCR_RTSC; 705 } 706 /* Enable CTS# pin function */ 707 ctrl &= ~SCPCR_CTSC; 708 } 709 serial_port_out(port, SCPDR, data); 710 serial_port_out(port, SCPCR, ctrl); 711 } else if (sci_getreg(port, SCSPTR)->size) { 712 u16 status = serial_port_in(port, SCSPTR); 713 714 /* RTS# is always output; and active low, unless autorts */ 715 status |= SCSPTR_RTSIO; 716 if (!(port->mctrl & TIOCM_RTS)) 717 status |= SCSPTR_RTSDT; 718 else if (!s->autorts) 719 status &= ~SCSPTR_RTSDT; 720 /* CTS# and SCK are inputs */ 721 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 722 serial_port_out(port, SCSPTR, status); 723 } 724 } 725 726 static int sci_txfill(struct uart_port *port) 727 { 728 struct sci_port *s = to_sci_port(port); 729 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 730 const struct plat_sci_reg *reg; 731 732 reg = sci_getreg(port, SCTFDR); 733 if (reg->size) 734 return serial_port_in(port, SCTFDR) & fifo_mask; 735 736 reg = sci_getreg(port, SCFDR); 737 if (reg->size) 738 return serial_port_in(port, SCFDR) >> 8; 739 740 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 741 } 742 743 static int sci_txroom(struct uart_port *port) 744 { 745 return port->fifosize - sci_txfill(port); 746 } 747 748 static int sci_rxfill(struct uart_port *port) 749 { 750 struct sci_port *s = to_sci_port(port); 751 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 752 const struct plat_sci_reg *reg; 753 754 reg = sci_getreg(port, SCRFDR); 755 if (reg->size) 756 return serial_port_in(port, SCRFDR) & fifo_mask; 757 758 reg = sci_getreg(port, SCFDR); 759 if (reg->size) 760 return serial_port_in(port, SCFDR) & fifo_mask; 761 762 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 763 } 764 765 /* ********************************************************************** * 766 * the interrupt related routines * 767 * ********************************************************************** */ 768 769 static void sci_transmit_chars(struct uart_port *port) 770 { 771 struct circ_buf *xmit = &port->state->xmit; 772 unsigned int stopped = uart_tx_stopped(port); 773 unsigned short status; 774 unsigned short ctrl; 775 int count; 776 777 status = serial_port_in(port, SCxSR); 778 if (!(status & SCxSR_TDxE(port))) { 779 ctrl = serial_port_in(port, SCSCR); 780 if (uart_circ_empty(xmit)) 781 ctrl &= ~SCSCR_TIE; 782 else 783 ctrl |= SCSCR_TIE; 784 serial_port_out(port, SCSCR, ctrl); 785 return; 786 } 787 788 count = sci_txroom(port); 789 790 do { 791 unsigned char c; 792 793 if (port->x_char) { 794 c = port->x_char; 795 port->x_char = 0; 796 } else if (!uart_circ_empty(xmit) && !stopped) { 797 c = xmit->buf[xmit->tail]; 798 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 799 } else { 800 break; 801 } 802 803 serial_port_out(port, SCxTDR, c); 804 805 port->icount.tx++; 806 } while (--count > 0); 807 808 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 809 810 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 811 uart_write_wakeup(port); 812 if (uart_circ_empty(xmit)) { 813 sci_stop_tx(port); 814 } else { 815 ctrl = serial_port_in(port, SCSCR); 816 817 if (port->type != PORT_SCI) { 818 serial_port_in(port, SCxSR); /* Dummy read */ 819 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 820 } 821 822 ctrl |= SCSCR_TIE; 823 serial_port_out(port, SCSCR, ctrl); 824 } 825 } 826 827 /* On SH3, SCIF may read end-of-break as a space->mark char */ 828 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 829 830 static void sci_receive_chars(struct uart_port *port) 831 { 832 struct tty_port *tport = &port->state->port; 833 int i, count, copied = 0; 834 unsigned short status; 835 unsigned char flag; 836 837 status = serial_port_in(port, SCxSR); 838 if (!(status & SCxSR_RDxF(port))) 839 return; 840 841 while (1) { 842 /* Don't copy more bytes than there is room for in the buffer */ 843 count = tty_buffer_request_room(tport, sci_rxfill(port)); 844 845 /* If for any reason we can't copy more data, we're done! */ 846 if (count == 0) 847 break; 848 849 if (port->type == PORT_SCI) { 850 char c = serial_port_in(port, SCxRDR); 851 if (uart_handle_sysrq_char(port, c)) 852 count = 0; 853 else 854 tty_insert_flip_char(tport, c, TTY_NORMAL); 855 } else { 856 for (i = 0; i < count; i++) { 857 char c = serial_port_in(port, SCxRDR); 858 859 status = serial_port_in(port, SCxSR); 860 if (uart_handle_sysrq_char(port, c)) { 861 count--; i--; 862 continue; 863 } 864 865 /* Store data and status */ 866 if (status & SCxSR_FER(port)) { 867 flag = TTY_FRAME; 868 port->icount.frame++; 869 dev_notice(port->dev, "frame error\n"); 870 } else if (status & SCxSR_PER(port)) { 871 flag = TTY_PARITY; 872 port->icount.parity++; 873 dev_notice(port->dev, "parity error\n"); 874 } else 875 flag = TTY_NORMAL; 876 877 tty_insert_flip_char(tport, c, flag); 878 } 879 } 880 881 serial_port_in(port, SCxSR); /* dummy read */ 882 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 883 884 copied += count; 885 port->icount.rx += count; 886 } 887 888 if (copied) { 889 /* Tell the rest of the system the news. New characters! */ 890 tty_flip_buffer_push(tport); 891 } else { 892 serial_port_in(port, SCxSR); /* dummy read */ 893 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 894 } 895 } 896 897 static int sci_handle_errors(struct uart_port *port) 898 { 899 int copied = 0; 900 unsigned short status = serial_port_in(port, SCxSR); 901 struct tty_port *tport = &port->state->port; 902 struct sci_port *s = to_sci_port(port); 903 904 /* Handle overruns */ 905 if (status & s->params->overrun_mask) { 906 port->icount.overrun++; 907 908 /* overrun error */ 909 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 910 copied++; 911 912 dev_notice(port->dev, "overrun error\n"); 913 } 914 915 if (status & SCxSR_FER(port)) { 916 /* frame error */ 917 port->icount.frame++; 918 919 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 920 copied++; 921 922 dev_notice(port->dev, "frame error\n"); 923 } 924 925 if (status & SCxSR_PER(port)) { 926 /* parity error */ 927 port->icount.parity++; 928 929 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 930 copied++; 931 932 dev_notice(port->dev, "parity error\n"); 933 } 934 935 if (copied) 936 tty_flip_buffer_push(tport); 937 938 return copied; 939 } 940 941 static int sci_handle_fifo_overrun(struct uart_port *port) 942 { 943 struct tty_port *tport = &port->state->port; 944 struct sci_port *s = to_sci_port(port); 945 const struct plat_sci_reg *reg; 946 int copied = 0; 947 u16 status; 948 949 reg = sci_getreg(port, s->params->overrun_reg); 950 if (!reg->size) 951 return 0; 952 953 status = serial_port_in(port, s->params->overrun_reg); 954 if (status & s->params->overrun_mask) { 955 status &= ~s->params->overrun_mask; 956 serial_port_out(port, s->params->overrun_reg, status); 957 958 port->icount.overrun++; 959 960 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 961 tty_flip_buffer_push(tport); 962 963 dev_dbg(port->dev, "overrun error\n"); 964 copied++; 965 } 966 967 return copied; 968 } 969 970 static int sci_handle_breaks(struct uart_port *port) 971 { 972 int copied = 0; 973 unsigned short status = serial_port_in(port, SCxSR); 974 struct tty_port *tport = &port->state->port; 975 976 if (uart_handle_break(port)) 977 return 0; 978 979 if (status & SCxSR_BRK(port)) { 980 port->icount.brk++; 981 982 /* Notify of BREAK */ 983 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 984 copied++; 985 986 dev_dbg(port->dev, "BREAK detected\n"); 987 } 988 989 if (copied) 990 tty_flip_buffer_push(tport); 991 992 copied += sci_handle_fifo_overrun(port); 993 994 return copied; 995 } 996 997 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 998 { 999 unsigned int bits; 1000 1001 if (rx_trig < 1) 1002 rx_trig = 1; 1003 if (rx_trig >= port->fifosize) 1004 rx_trig = port->fifosize; 1005 1006 /* HSCIF can be set to an arbitrary level. */ 1007 if (sci_getreg(port, HSRTRGR)->size) { 1008 serial_port_out(port, HSRTRGR, rx_trig); 1009 return rx_trig; 1010 } 1011 1012 switch (port->type) { 1013 case PORT_SCIF: 1014 if (rx_trig < 4) { 1015 bits = 0; 1016 rx_trig = 1; 1017 } else if (rx_trig < 8) { 1018 bits = SCFCR_RTRG0; 1019 rx_trig = 4; 1020 } else if (rx_trig < 14) { 1021 bits = SCFCR_RTRG1; 1022 rx_trig = 8; 1023 } else { 1024 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1025 rx_trig = 14; 1026 } 1027 break; 1028 case PORT_SCIFA: 1029 case PORT_SCIFB: 1030 if (rx_trig < 16) { 1031 bits = 0; 1032 rx_trig = 1; 1033 } else if (rx_trig < 32) { 1034 bits = SCFCR_RTRG0; 1035 rx_trig = 16; 1036 } else if (rx_trig < 48) { 1037 bits = SCFCR_RTRG1; 1038 rx_trig = 32; 1039 } else { 1040 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1041 rx_trig = 48; 1042 } 1043 break; 1044 default: 1045 WARN(1, "unknown FIFO configuration"); 1046 return 1; 1047 } 1048 1049 serial_port_out(port, SCFCR, 1050 (serial_port_in(port, SCFCR) & 1051 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1052 1053 return rx_trig; 1054 } 1055 1056 static int scif_rtrg_enabled(struct uart_port *port) 1057 { 1058 if (sci_getreg(port, HSRTRGR)->size) 1059 return serial_port_in(port, HSRTRGR) != 0; 1060 else 1061 return (serial_port_in(port, SCFCR) & 1062 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1063 } 1064 1065 static void rx_fifo_timer_fn(unsigned long arg) 1066 { 1067 struct sci_port *s = (struct sci_port *)arg; 1068 struct uart_port *port = &s->port; 1069 1070 dev_dbg(port->dev, "Rx timed out\n"); 1071 scif_set_rtrg(port, 1); 1072 } 1073 1074 static ssize_t rx_trigger_show(struct device *dev, 1075 struct device_attribute *attr, 1076 char *buf) 1077 { 1078 struct uart_port *port = dev_get_drvdata(dev); 1079 struct sci_port *sci = to_sci_port(port); 1080 1081 return sprintf(buf, "%d\n", sci->rx_trigger); 1082 } 1083 1084 static ssize_t rx_trigger_store(struct device *dev, 1085 struct device_attribute *attr, 1086 const char *buf, 1087 size_t count) 1088 { 1089 struct uart_port *port = dev_get_drvdata(dev); 1090 struct sci_port *sci = to_sci_port(port); 1091 int ret; 1092 long r; 1093 1094 ret = kstrtol(buf, 0, &r); 1095 if (ret) 1096 return ret; 1097 1098 sci->rx_trigger = scif_set_rtrg(port, r); 1099 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1100 scif_set_rtrg(port, 1); 1101 1102 return count; 1103 } 1104 1105 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store); 1106 1107 static ssize_t rx_fifo_timeout_show(struct device *dev, 1108 struct device_attribute *attr, 1109 char *buf) 1110 { 1111 struct uart_port *port = dev_get_drvdata(dev); 1112 struct sci_port *sci = to_sci_port(port); 1113 int v; 1114 1115 if (port->type == PORT_HSCIF) 1116 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1117 else 1118 v = sci->rx_fifo_timeout; 1119 1120 return sprintf(buf, "%d\n", v); 1121 } 1122 1123 static ssize_t rx_fifo_timeout_store(struct device *dev, 1124 struct device_attribute *attr, 1125 const char *buf, 1126 size_t count) 1127 { 1128 struct uart_port *port = dev_get_drvdata(dev); 1129 struct sci_port *sci = to_sci_port(port); 1130 int ret; 1131 long r; 1132 1133 ret = kstrtol(buf, 0, &r); 1134 if (ret) 1135 return ret; 1136 1137 if (port->type == PORT_HSCIF) { 1138 if (r < 0 || r > 3) 1139 return -EINVAL; 1140 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1141 } else { 1142 sci->rx_fifo_timeout = r; 1143 scif_set_rtrg(port, 1); 1144 if (r > 0) 1145 setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn, 1146 (unsigned long)sci); 1147 } 1148 1149 return count; 1150 } 1151 1152 static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store); 1153 1154 1155 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1156 static void sci_dma_tx_complete(void *arg) 1157 { 1158 struct sci_port *s = arg; 1159 struct uart_port *port = &s->port; 1160 struct circ_buf *xmit = &port->state->xmit; 1161 unsigned long flags; 1162 1163 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1164 1165 spin_lock_irqsave(&port->lock, flags); 1166 1167 xmit->tail += s->tx_dma_len; 1168 xmit->tail &= UART_XMIT_SIZE - 1; 1169 1170 port->icount.tx += s->tx_dma_len; 1171 1172 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1173 uart_write_wakeup(port); 1174 1175 if (!uart_circ_empty(xmit)) { 1176 s->cookie_tx = 0; 1177 schedule_work(&s->work_tx); 1178 } else { 1179 s->cookie_tx = -EINVAL; 1180 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1181 u16 ctrl = serial_port_in(port, SCSCR); 1182 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1183 } 1184 } 1185 1186 spin_unlock_irqrestore(&port->lock, flags); 1187 } 1188 1189 /* Locking: called with port lock held */ 1190 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1191 { 1192 struct uart_port *port = &s->port; 1193 struct tty_port *tport = &port->state->port; 1194 int copied; 1195 1196 copied = tty_insert_flip_string(tport, buf, count); 1197 if (copied < count) 1198 port->icount.buf_overrun++; 1199 1200 port->icount.rx += copied; 1201 1202 return copied; 1203 } 1204 1205 static int sci_dma_rx_find_active(struct sci_port *s) 1206 { 1207 unsigned int i; 1208 1209 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1210 if (s->active_rx == s->cookie_rx[i]) 1211 return i; 1212 1213 return -1; 1214 } 1215 1216 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1217 { 1218 struct dma_chan *chan = s->chan_rx; 1219 struct uart_port *port = &s->port; 1220 unsigned long flags; 1221 1222 spin_lock_irqsave(&port->lock, flags); 1223 s->chan_rx = NULL; 1224 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1225 spin_unlock_irqrestore(&port->lock, flags); 1226 dmaengine_terminate_all(chan); 1227 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1228 sg_dma_address(&s->sg_rx[0])); 1229 dma_release_channel(chan); 1230 if (enable_pio) { 1231 spin_lock_irqsave(&port->lock, flags); 1232 sci_start_rx(port); 1233 spin_unlock_irqrestore(&port->lock, flags); 1234 } 1235 } 1236 1237 static void sci_dma_rx_complete(void *arg) 1238 { 1239 struct sci_port *s = arg; 1240 struct dma_chan *chan = s->chan_rx; 1241 struct uart_port *port = &s->port; 1242 struct dma_async_tx_descriptor *desc; 1243 unsigned long flags; 1244 int active, count = 0; 1245 1246 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1247 s->active_rx); 1248 1249 spin_lock_irqsave(&port->lock, flags); 1250 1251 active = sci_dma_rx_find_active(s); 1252 if (active >= 0) 1253 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1254 1255 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1256 1257 if (count) 1258 tty_flip_buffer_push(&port->state->port); 1259 1260 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1261 DMA_DEV_TO_MEM, 1262 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1263 if (!desc) 1264 goto fail; 1265 1266 desc->callback = sci_dma_rx_complete; 1267 desc->callback_param = s; 1268 s->cookie_rx[active] = dmaengine_submit(desc); 1269 if (dma_submit_error(s->cookie_rx[active])) 1270 goto fail; 1271 1272 s->active_rx = s->cookie_rx[!active]; 1273 1274 dma_async_issue_pending(chan); 1275 1276 spin_unlock_irqrestore(&port->lock, flags); 1277 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1278 __func__, s->cookie_rx[active], active, s->active_rx); 1279 return; 1280 1281 fail: 1282 spin_unlock_irqrestore(&port->lock, flags); 1283 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1284 sci_rx_dma_release(s, true); 1285 } 1286 1287 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1288 { 1289 struct dma_chan *chan = s->chan_tx; 1290 struct uart_port *port = &s->port; 1291 unsigned long flags; 1292 1293 spin_lock_irqsave(&port->lock, flags); 1294 s->chan_tx = NULL; 1295 s->cookie_tx = -EINVAL; 1296 spin_unlock_irqrestore(&port->lock, flags); 1297 dmaengine_terminate_all(chan); 1298 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1299 DMA_TO_DEVICE); 1300 dma_release_channel(chan); 1301 if (enable_pio) { 1302 spin_lock_irqsave(&port->lock, flags); 1303 sci_start_tx(port); 1304 spin_unlock_irqrestore(&port->lock, flags); 1305 } 1306 } 1307 1308 static void sci_submit_rx(struct sci_port *s) 1309 { 1310 struct dma_chan *chan = s->chan_rx; 1311 int i; 1312 1313 for (i = 0; i < 2; i++) { 1314 struct scatterlist *sg = &s->sg_rx[i]; 1315 struct dma_async_tx_descriptor *desc; 1316 1317 desc = dmaengine_prep_slave_sg(chan, 1318 sg, 1, DMA_DEV_TO_MEM, 1319 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1320 if (!desc) 1321 goto fail; 1322 1323 desc->callback = sci_dma_rx_complete; 1324 desc->callback_param = s; 1325 s->cookie_rx[i] = dmaengine_submit(desc); 1326 if (dma_submit_error(s->cookie_rx[i])) 1327 goto fail; 1328 1329 } 1330 1331 s->active_rx = s->cookie_rx[0]; 1332 1333 dma_async_issue_pending(chan); 1334 return; 1335 1336 fail: 1337 if (i) 1338 dmaengine_terminate_all(chan); 1339 for (i = 0; i < 2; i++) 1340 s->cookie_rx[i] = -EINVAL; 1341 s->active_rx = -EINVAL; 1342 sci_rx_dma_release(s, true); 1343 } 1344 1345 static void work_fn_tx(struct work_struct *work) 1346 { 1347 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1348 struct dma_async_tx_descriptor *desc; 1349 struct dma_chan *chan = s->chan_tx; 1350 struct uart_port *port = &s->port; 1351 struct circ_buf *xmit = &port->state->xmit; 1352 dma_addr_t buf; 1353 1354 /* 1355 * DMA is idle now. 1356 * Port xmit buffer is already mapped, and it is one page... Just adjust 1357 * offsets and lengths. Since it is a circular buffer, we have to 1358 * transmit till the end, and then the rest. Take the port lock to get a 1359 * consistent xmit buffer state. 1360 */ 1361 spin_lock_irq(&port->lock); 1362 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1)); 1363 s->tx_dma_len = min_t(unsigned int, 1364 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1365 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1366 spin_unlock_irq(&port->lock); 1367 1368 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1369 DMA_MEM_TO_DEV, 1370 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1371 if (!desc) { 1372 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1373 /* switch to PIO */ 1374 sci_tx_dma_release(s, true); 1375 return; 1376 } 1377 1378 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1379 DMA_TO_DEVICE); 1380 1381 spin_lock_irq(&port->lock); 1382 desc->callback = sci_dma_tx_complete; 1383 desc->callback_param = s; 1384 spin_unlock_irq(&port->lock); 1385 s->cookie_tx = dmaengine_submit(desc); 1386 if (dma_submit_error(s->cookie_tx)) { 1387 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1388 /* switch to PIO */ 1389 sci_tx_dma_release(s, true); 1390 return; 1391 } 1392 1393 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1394 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1395 1396 dma_async_issue_pending(chan); 1397 } 1398 1399 static void rx_timer_fn(unsigned long arg) 1400 { 1401 struct sci_port *s = (struct sci_port *)arg; 1402 struct dma_chan *chan = s->chan_rx; 1403 struct uart_port *port = &s->port; 1404 struct dma_tx_state state; 1405 enum dma_status status; 1406 unsigned long flags; 1407 unsigned int read; 1408 int active, count; 1409 u16 scr; 1410 1411 dev_dbg(port->dev, "DMA Rx timed out\n"); 1412 1413 spin_lock_irqsave(&port->lock, flags); 1414 1415 active = sci_dma_rx_find_active(s); 1416 if (active < 0) { 1417 spin_unlock_irqrestore(&port->lock, flags); 1418 return; 1419 } 1420 1421 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1422 if (status == DMA_COMPLETE) { 1423 spin_unlock_irqrestore(&port->lock, flags); 1424 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1425 s->active_rx, active); 1426 1427 /* Let packet complete handler take care of the packet */ 1428 return; 1429 } 1430 1431 dmaengine_pause(chan); 1432 1433 /* 1434 * sometimes DMA transfer doesn't stop even if it is stopped and 1435 * data keeps on coming until transaction is complete so check 1436 * for DMA_COMPLETE again 1437 * Let packet complete handler take care of the packet 1438 */ 1439 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1440 if (status == DMA_COMPLETE) { 1441 spin_unlock_irqrestore(&port->lock, flags); 1442 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1443 return; 1444 } 1445 1446 /* Handle incomplete DMA receive */ 1447 dmaengine_terminate_all(s->chan_rx); 1448 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1449 1450 if (read) { 1451 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1452 if (count) 1453 tty_flip_buffer_push(&port->state->port); 1454 } 1455 1456 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1457 sci_submit_rx(s); 1458 1459 /* Direct new serial port interrupts back to CPU */ 1460 scr = serial_port_in(port, SCSCR); 1461 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1462 scr &= ~SCSCR_RDRQE; 1463 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1464 } 1465 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1466 1467 spin_unlock_irqrestore(&port->lock, flags); 1468 } 1469 1470 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1471 enum dma_transfer_direction dir) 1472 { 1473 struct dma_chan *chan; 1474 struct dma_slave_config cfg; 1475 int ret; 1476 1477 chan = dma_request_slave_channel(port->dev, 1478 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1479 if (!chan) { 1480 dev_warn(port->dev, "dma_request_slave_channel failed\n"); 1481 return NULL; 1482 } 1483 1484 memset(&cfg, 0, sizeof(cfg)); 1485 cfg.direction = dir; 1486 if (dir == DMA_MEM_TO_DEV) { 1487 cfg.dst_addr = port->mapbase + 1488 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1489 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1490 } else { 1491 cfg.src_addr = port->mapbase + 1492 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1493 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1494 } 1495 1496 ret = dmaengine_slave_config(chan, &cfg); 1497 if (ret) { 1498 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1499 dma_release_channel(chan); 1500 return NULL; 1501 } 1502 1503 return chan; 1504 } 1505 1506 static void sci_request_dma(struct uart_port *port) 1507 { 1508 struct sci_port *s = to_sci_port(port); 1509 struct dma_chan *chan; 1510 1511 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1512 1513 if (!port->dev->of_node) 1514 return; 1515 1516 s->cookie_tx = -EINVAL; 1517 1518 /* 1519 * Don't request a dma channel if no channel was specified 1520 * in the device tree. 1521 */ 1522 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1523 return; 1524 1525 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1526 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1527 if (chan) { 1528 s->chan_tx = chan; 1529 /* UART circular tx buffer is an aligned page. */ 1530 s->tx_dma_addr = dma_map_single(chan->device->dev, 1531 port->state->xmit.buf, 1532 UART_XMIT_SIZE, 1533 DMA_TO_DEVICE); 1534 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1535 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1536 dma_release_channel(chan); 1537 s->chan_tx = NULL; 1538 } else { 1539 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1540 __func__, UART_XMIT_SIZE, 1541 port->state->xmit.buf, &s->tx_dma_addr); 1542 } 1543 1544 INIT_WORK(&s->work_tx, work_fn_tx); 1545 } 1546 1547 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1548 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1549 if (chan) { 1550 unsigned int i; 1551 dma_addr_t dma; 1552 void *buf; 1553 1554 s->chan_rx = chan; 1555 1556 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1557 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1558 &dma, GFP_KERNEL); 1559 if (!buf) { 1560 dev_warn(port->dev, 1561 "Failed to allocate Rx dma buffer, using PIO\n"); 1562 dma_release_channel(chan); 1563 s->chan_rx = NULL; 1564 return; 1565 } 1566 1567 for (i = 0; i < 2; i++) { 1568 struct scatterlist *sg = &s->sg_rx[i]; 1569 1570 sg_init_table(sg, 1); 1571 s->rx_buf[i] = buf; 1572 sg_dma_address(sg) = dma; 1573 sg_dma_len(sg) = s->buf_len_rx; 1574 1575 buf += s->buf_len_rx; 1576 dma += s->buf_len_rx; 1577 } 1578 1579 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1580 1581 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1582 sci_submit_rx(s); 1583 } 1584 } 1585 1586 static void sci_free_dma(struct uart_port *port) 1587 { 1588 struct sci_port *s = to_sci_port(port); 1589 1590 if (s->chan_tx) 1591 sci_tx_dma_release(s, false); 1592 if (s->chan_rx) 1593 sci_rx_dma_release(s, false); 1594 } 1595 1596 static void sci_flush_buffer(struct uart_port *port) 1597 { 1598 /* 1599 * In uart_flush_buffer(), the xmit circular buffer has just been 1600 * cleared, so we have to reset tx_dma_len accordingly. 1601 */ 1602 to_sci_port(port)->tx_dma_len = 0; 1603 } 1604 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1605 static inline void sci_request_dma(struct uart_port *port) 1606 { 1607 } 1608 1609 static inline void sci_free_dma(struct uart_port *port) 1610 { 1611 } 1612 1613 #define sci_flush_buffer NULL 1614 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1615 1616 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1617 { 1618 struct uart_port *port = ptr; 1619 struct sci_port *s = to_sci_port(port); 1620 1621 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1622 if (s->chan_rx) { 1623 u16 scr = serial_port_in(port, SCSCR); 1624 u16 ssr = serial_port_in(port, SCxSR); 1625 1626 /* Disable future Rx interrupts */ 1627 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1628 disable_irq_nosync(irq); 1629 scr |= SCSCR_RDRQE; 1630 } else { 1631 scr &= ~SCSCR_RIE; 1632 sci_submit_rx(s); 1633 } 1634 serial_port_out(port, SCSCR, scr); 1635 /* Clear current interrupt */ 1636 serial_port_out(port, SCxSR, 1637 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1638 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 1639 jiffies, s->rx_timeout); 1640 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1641 1642 return IRQ_HANDLED; 1643 } 1644 #endif 1645 1646 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1647 if (!scif_rtrg_enabled(port)) 1648 scif_set_rtrg(port, s->rx_trigger); 1649 1650 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1651 s->rx_frame * s->rx_fifo_timeout, 1000)); 1652 } 1653 1654 /* I think sci_receive_chars has to be called irrespective 1655 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1656 * to be disabled? 1657 */ 1658 sci_receive_chars(ptr); 1659 1660 return IRQ_HANDLED; 1661 } 1662 1663 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1664 { 1665 struct uart_port *port = ptr; 1666 unsigned long flags; 1667 1668 spin_lock_irqsave(&port->lock, flags); 1669 sci_transmit_chars(port); 1670 spin_unlock_irqrestore(&port->lock, flags); 1671 1672 return IRQ_HANDLED; 1673 } 1674 1675 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1676 { 1677 struct uart_port *port = ptr; 1678 struct sci_port *s = to_sci_port(port); 1679 1680 /* Handle errors */ 1681 if (port->type == PORT_SCI) { 1682 if (sci_handle_errors(port)) { 1683 /* discard character in rx buffer */ 1684 serial_port_in(port, SCxSR); 1685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1686 } 1687 } else { 1688 sci_handle_fifo_overrun(port); 1689 if (!s->chan_rx) 1690 sci_receive_chars(ptr); 1691 } 1692 1693 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1694 1695 /* Kick the transmission */ 1696 if (!s->chan_tx) 1697 sci_tx_interrupt(irq, ptr); 1698 1699 return IRQ_HANDLED; 1700 } 1701 1702 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1703 { 1704 struct uart_port *port = ptr; 1705 1706 /* Handle BREAKs */ 1707 sci_handle_breaks(port); 1708 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1709 1710 return IRQ_HANDLED; 1711 } 1712 1713 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1714 { 1715 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1716 struct uart_port *port = ptr; 1717 struct sci_port *s = to_sci_port(port); 1718 irqreturn_t ret = IRQ_NONE; 1719 1720 ssr_status = serial_port_in(port, SCxSR); 1721 scr_status = serial_port_in(port, SCSCR); 1722 if (s->params->overrun_reg == SCxSR) 1723 orer_status = ssr_status; 1724 else if (sci_getreg(port, s->params->overrun_reg)->size) 1725 orer_status = serial_port_in(port, s->params->overrun_reg); 1726 1727 err_enabled = scr_status & port_rx_irq_mask(port); 1728 1729 /* Tx Interrupt */ 1730 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1731 !s->chan_tx) 1732 ret = sci_tx_interrupt(irq, ptr); 1733 1734 /* 1735 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1736 * DR flags 1737 */ 1738 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1739 (scr_status & SCSCR_RIE)) 1740 ret = sci_rx_interrupt(irq, ptr); 1741 1742 /* Error Interrupt */ 1743 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1744 ret = sci_er_interrupt(irq, ptr); 1745 1746 /* Break Interrupt */ 1747 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1748 ret = sci_br_interrupt(irq, ptr); 1749 1750 /* Overrun Interrupt */ 1751 if (orer_status & s->params->overrun_mask) { 1752 sci_handle_fifo_overrun(port); 1753 ret = IRQ_HANDLED; 1754 } 1755 1756 return ret; 1757 } 1758 1759 static const struct sci_irq_desc { 1760 const char *desc; 1761 irq_handler_t handler; 1762 } sci_irq_desc[] = { 1763 /* 1764 * Split out handlers, the default case. 1765 */ 1766 [SCIx_ERI_IRQ] = { 1767 .desc = "rx err", 1768 .handler = sci_er_interrupt, 1769 }, 1770 1771 [SCIx_RXI_IRQ] = { 1772 .desc = "rx full", 1773 .handler = sci_rx_interrupt, 1774 }, 1775 1776 [SCIx_TXI_IRQ] = { 1777 .desc = "tx empty", 1778 .handler = sci_tx_interrupt, 1779 }, 1780 1781 [SCIx_BRI_IRQ] = { 1782 .desc = "break", 1783 .handler = sci_br_interrupt, 1784 }, 1785 1786 /* 1787 * Special muxed handler. 1788 */ 1789 [SCIx_MUX_IRQ] = { 1790 .desc = "mux", 1791 .handler = sci_mpxed_interrupt, 1792 }, 1793 }; 1794 1795 static int sci_request_irq(struct sci_port *port) 1796 { 1797 struct uart_port *up = &port->port; 1798 int i, j, ret = 0; 1799 1800 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1801 const struct sci_irq_desc *desc; 1802 int irq; 1803 1804 if (SCIx_IRQ_IS_MUXED(port)) { 1805 i = SCIx_MUX_IRQ; 1806 irq = up->irq; 1807 } else { 1808 irq = port->irqs[i]; 1809 1810 /* 1811 * Certain port types won't support all of the 1812 * available interrupt sources. 1813 */ 1814 if (unlikely(irq < 0)) 1815 continue; 1816 } 1817 1818 desc = sci_irq_desc + i; 1819 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1820 dev_name(up->dev), desc->desc); 1821 if (!port->irqstr[j]) { 1822 ret = -ENOMEM; 1823 goto out_nomem; 1824 } 1825 1826 ret = request_irq(irq, desc->handler, up->irqflags, 1827 port->irqstr[j], port); 1828 if (unlikely(ret)) { 1829 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1830 goto out_noirq; 1831 } 1832 } 1833 1834 return 0; 1835 1836 out_noirq: 1837 while (--i >= 0) 1838 free_irq(port->irqs[i], port); 1839 1840 out_nomem: 1841 while (--j >= 0) 1842 kfree(port->irqstr[j]); 1843 1844 return ret; 1845 } 1846 1847 static void sci_free_irq(struct sci_port *port) 1848 { 1849 int i; 1850 1851 /* 1852 * Intentionally in reverse order so we iterate over the muxed 1853 * IRQ first. 1854 */ 1855 for (i = 0; i < SCIx_NR_IRQS; i++) { 1856 int irq = port->irqs[i]; 1857 1858 /* 1859 * Certain port types won't support all of the available 1860 * interrupt sources. 1861 */ 1862 if (unlikely(irq < 0)) 1863 continue; 1864 1865 free_irq(port->irqs[i], port); 1866 kfree(port->irqstr[i]); 1867 1868 if (SCIx_IRQ_IS_MUXED(port)) { 1869 /* If there's only one IRQ, we're done. */ 1870 return; 1871 } 1872 } 1873 } 1874 1875 static unsigned int sci_tx_empty(struct uart_port *port) 1876 { 1877 unsigned short status = serial_port_in(port, SCxSR); 1878 unsigned short in_tx_fifo = sci_txfill(port); 1879 1880 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1881 } 1882 1883 static void sci_set_rts(struct uart_port *port, bool state) 1884 { 1885 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1886 u16 data = serial_port_in(port, SCPDR); 1887 1888 /* Active low */ 1889 if (state) 1890 data &= ~SCPDR_RTSD; 1891 else 1892 data |= SCPDR_RTSD; 1893 serial_port_out(port, SCPDR, data); 1894 1895 /* RTS# is output */ 1896 serial_port_out(port, SCPCR, 1897 serial_port_in(port, SCPCR) | SCPCR_RTSC); 1898 } else if (sci_getreg(port, SCSPTR)->size) { 1899 u16 ctrl = serial_port_in(port, SCSPTR); 1900 1901 /* Active low */ 1902 if (state) 1903 ctrl &= ~SCSPTR_RTSDT; 1904 else 1905 ctrl |= SCSPTR_RTSDT; 1906 serial_port_out(port, SCSPTR, ctrl); 1907 } 1908 } 1909 1910 static bool sci_get_cts(struct uart_port *port) 1911 { 1912 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1913 /* Active low */ 1914 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 1915 } else if (sci_getreg(port, SCSPTR)->size) { 1916 /* Active low */ 1917 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 1918 } 1919 1920 return true; 1921 } 1922 1923 /* 1924 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 1925 * CTS/RTS is supported in hardware by at least one port and controlled 1926 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 1927 * handled via the ->init_pins() op, which is a bit of a one-way street, 1928 * lacking any ability to defer pin control -- this will later be 1929 * converted over to the GPIO framework). 1930 * 1931 * Other modes (such as loopback) are supported generically on certain 1932 * port types, but not others. For these it's sufficient to test for the 1933 * existence of the support register and simply ignore the port type. 1934 */ 1935 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1936 { 1937 struct sci_port *s = to_sci_port(port); 1938 1939 if (mctrl & TIOCM_LOOP) { 1940 const struct plat_sci_reg *reg; 1941 1942 /* 1943 * Standard loopback mode for SCFCR ports. 1944 */ 1945 reg = sci_getreg(port, SCFCR); 1946 if (reg->size) 1947 serial_port_out(port, SCFCR, 1948 serial_port_in(port, SCFCR) | 1949 SCFCR_LOOP); 1950 } 1951 1952 mctrl_gpio_set(s->gpios, mctrl); 1953 1954 if (!s->has_rtscts) 1955 return; 1956 1957 if (!(mctrl & TIOCM_RTS)) { 1958 /* Disable Auto RTS */ 1959 serial_port_out(port, SCFCR, 1960 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 1961 1962 /* Clear RTS */ 1963 sci_set_rts(port, 0); 1964 } else if (s->autorts) { 1965 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1966 /* Enable RTS# pin function */ 1967 serial_port_out(port, SCPCR, 1968 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 1969 } 1970 1971 /* Enable Auto RTS */ 1972 serial_port_out(port, SCFCR, 1973 serial_port_in(port, SCFCR) | SCFCR_MCE); 1974 } else { 1975 /* Set RTS */ 1976 sci_set_rts(port, 1); 1977 } 1978 } 1979 1980 static unsigned int sci_get_mctrl(struct uart_port *port) 1981 { 1982 struct sci_port *s = to_sci_port(port); 1983 struct mctrl_gpios *gpios = s->gpios; 1984 unsigned int mctrl = 0; 1985 1986 mctrl_gpio_get(gpios, &mctrl); 1987 1988 /* 1989 * CTS/RTS is handled in hardware when supported, while nothing 1990 * else is wired up. 1991 */ 1992 if (s->autorts) { 1993 if (sci_get_cts(port)) 1994 mctrl |= TIOCM_CTS; 1995 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) { 1996 mctrl |= TIOCM_CTS; 1997 } 1998 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))) 1999 mctrl |= TIOCM_DSR; 2000 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))) 2001 mctrl |= TIOCM_CAR; 2002 2003 return mctrl; 2004 } 2005 2006 static void sci_enable_ms(struct uart_port *port) 2007 { 2008 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2009 } 2010 2011 static void sci_break_ctl(struct uart_port *port, int break_state) 2012 { 2013 unsigned short scscr, scsptr; 2014 unsigned long flags; 2015 2016 /* check wheter the port has SCSPTR */ 2017 if (!sci_getreg(port, SCSPTR)->size) { 2018 /* 2019 * Not supported by hardware. Most parts couple break and rx 2020 * interrupts together, with break detection always enabled. 2021 */ 2022 return; 2023 } 2024 2025 spin_lock_irqsave(&port->lock, flags); 2026 scsptr = serial_port_in(port, SCSPTR); 2027 scscr = serial_port_in(port, SCSCR); 2028 2029 if (break_state == -1) { 2030 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2031 scscr &= ~SCSCR_TE; 2032 } else { 2033 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2034 scscr |= SCSCR_TE; 2035 } 2036 2037 serial_port_out(port, SCSPTR, scsptr); 2038 serial_port_out(port, SCSCR, scscr); 2039 spin_unlock_irqrestore(&port->lock, flags); 2040 } 2041 2042 static int sci_startup(struct uart_port *port) 2043 { 2044 struct sci_port *s = to_sci_port(port); 2045 int ret; 2046 2047 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2048 2049 sci_request_dma(port); 2050 2051 ret = sci_request_irq(s); 2052 if (unlikely(ret < 0)) { 2053 sci_free_dma(port); 2054 return ret; 2055 } 2056 2057 return 0; 2058 } 2059 2060 static void sci_shutdown(struct uart_port *port) 2061 { 2062 struct sci_port *s = to_sci_port(port); 2063 unsigned long flags; 2064 u16 scr; 2065 2066 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2067 2068 s->autorts = false; 2069 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2070 2071 spin_lock_irqsave(&port->lock, flags); 2072 sci_stop_rx(port); 2073 sci_stop_tx(port); 2074 /* 2075 * Stop RX and TX, disable related interrupts, keep clock source 2076 * and HSCIF TOT bits 2077 */ 2078 scr = serial_port_in(port, SCSCR); 2079 serial_port_out(port, SCSCR, scr & 2080 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2081 spin_unlock_irqrestore(&port->lock, flags); 2082 2083 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2084 if (s->chan_rx) { 2085 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2086 port->line); 2087 del_timer_sync(&s->rx_timer); 2088 } 2089 #endif 2090 2091 sci_free_irq(s); 2092 sci_free_dma(port); 2093 } 2094 2095 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2096 unsigned int *srr) 2097 { 2098 unsigned long freq = s->clk_rates[SCI_SCK]; 2099 int err, min_err = INT_MAX; 2100 unsigned int sr; 2101 2102 if (s->port.type != PORT_HSCIF) 2103 freq *= 2; 2104 2105 for_each_sr(sr, s) { 2106 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2107 if (abs(err) >= abs(min_err)) 2108 continue; 2109 2110 min_err = err; 2111 *srr = sr - 1; 2112 2113 if (!err) 2114 break; 2115 } 2116 2117 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2118 *srr + 1); 2119 return min_err; 2120 } 2121 2122 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2123 unsigned long freq, unsigned int *dlr, 2124 unsigned int *srr) 2125 { 2126 int err, min_err = INT_MAX; 2127 unsigned int sr, dl; 2128 2129 if (s->port.type != PORT_HSCIF) 2130 freq *= 2; 2131 2132 for_each_sr(sr, s) { 2133 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2134 dl = clamp(dl, 1U, 65535U); 2135 2136 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2137 if (abs(err) >= abs(min_err)) 2138 continue; 2139 2140 min_err = err; 2141 *dlr = dl; 2142 *srr = sr - 1; 2143 2144 if (!err) 2145 break; 2146 } 2147 2148 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2149 min_err, *dlr, *srr + 1); 2150 return min_err; 2151 } 2152 2153 /* calculate sample rate, BRR, and clock select */ 2154 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2155 unsigned int *brr, unsigned int *srr, 2156 unsigned int *cks) 2157 { 2158 unsigned long freq = s->clk_rates[SCI_FCK]; 2159 unsigned int sr, br, prediv, scrate, c; 2160 int err, min_err = INT_MAX; 2161 2162 if (s->port.type != PORT_HSCIF) 2163 freq *= 2; 2164 2165 /* 2166 * Find the combination of sample rate and clock select with the 2167 * smallest deviation from the desired baud rate. 2168 * Prefer high sample rates to maximise the receive margin. 2169 * 2170 * M: Receive margin (%) 2171 * N: Ratio of bit rate to clock (N = sampling rate) 2172 * D: Clock duty (D = 0 to 1.0) 2173 * L: Frame length (L = 9 to 12) 2174 * F: Absolute value of clock frequency deviation 2175 * 2176 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2177 * (|D - 0.5| / N * (1 + F))| 2178 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2179 */ 2180 for_each_sr(sr, s) { 2181 for (c = 0; c <= 3; c++) { 2182 /* integerized formulas from HSCIF documentation */ 2183 prediv = sr * (1 << (2 * c + 1)); 2184 2185 /* 2186 * We need to calculate: 2187 * 2188 * br = freq / (prediv * bps) clamped to [1..256] 2189 * err = freq / (br * prediv) - bps 2190 * 2191 * Watch out for overflow when calculating the desired 2192 * sampling clock rate! 2193 */ 2194 if (bps > UINT_MAX / prediv) 2195 break; 2196 2197 scrate = prediv * bps; 2198 br = DIV_ROUND_CLOSEST(freq, scrate); 2199 br = clamp(br, 1U, 256U); 2200 2201 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2202 if (abs(err) >= abs(min_err)) 2203 continue; 2204 2205 min_err = err; 2206 *brr = br - 1; 2207 *srr = sr - 1; 2208 *cks = c; 2209 2210 if (!err) 2211 goto found; 2212 } 2213 } 2214 2215 found: 2216 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2217 min_err, *brr, *srr + 1, *cks); 2218 return min_err; 2219 } 2220 2221 static void sci_reset(struct uart_port *port) 2222 { 2223 const struct plat_sci_reg *reg; 2224 unsigned int status; 2225 struct sci_port *s = to_sci_port(port); 2226 2227 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2228 2229 reg = sci_getreg(port, SCFCR); 2230 if (reg->size) 2231 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2232 2233 sci_clear_SCxSR(port, 2234 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2235 SCxSR_BREAK_CLEAR(port)); 2236 if (sci_getreg(port, SCLSR)->size) { 2237 status = serial_port_in(port, SCLSR); 2238 status &= ~(SCLSR_TO | SCLSR_ORER); 2239 serial_port_out(port, SCLSR, status); 2240 } 2241 2242 if (s->rx_trigger > 1) { 2243 if (s->rx_fifo_timeout) { 2244 scif_set_rtrg(port, 1); 2245 setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn, 2246 (unsigned long)s); 2247 } else { 2248 if (port->type == PORT_SCIFA || 2249 port->type == PORT_SCIFB) 2250 scif_set_rtrg(port, 1); 2251 else 2252 scif_set_rtrg(port, s->rx_trigger); 2253 } 2254 } 2255 } 2256 2257 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2258 struct ktermios *old) 2259 { 2260 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2261 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2262 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2263 struct sci_port *s = to_sci_port(port); 2264 const struct plat_sci_reg *reg; 2265 int min_err = INT_MAX, err; 2266 unsigned long max_freq = 0; 2267 int best_clk = -1; 2268 unsigned long flags; 2269 2270 if ((termios->c_cflag & CSIZE) == CS7) 2271 smr_val |= SCSMR_CHR; 2272 if (termios->c_cflag & PARENB) 2273 smr_val |= SCSMR_PE; 2274 if (termios->c_cflag & PARODD) 2275 smr_val |= SCSMR_PE | SCSMR_ODD; 2276 if (termios->c_cflag & CSTOPB) 2277 smr_val |= SCSMR_STOP; 2278 2279 /* 2280 * earlyprintk comes here early on with port->uartclk set to zero. 2281 * the clock framework is not up and running at this point so here 2282 * we assume that 115200 is the maximum baud rate. please note that 2283 * the baud rate is not programmed during earlyprintk - it is assumed 2284 * that the previous boot loader has enabled required clocks and 2285 * setup the baud rate generator hardware for us already. 2286 */ 2287 if (!port->uartclk) { 2288 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2289 goto done; 2290 } 2291 2292 for (i = 0; i < SCI_NUM_CLKS; i++) 2293 max_freq = max(max_freq, s->clk_rates[i]); 2294 2295 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2296 if (!baud) 2297 goto done; 2298 2299 /* 2300 * There can be multiple sources for the sampling clock. Find the one 2301 * that gives us the smallest deviation from the desired baud rate. 2302 */ 2303 2304 /* Optional Undivided External Clock */ 2305 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2306 port->type != PORT_SCIFB) { 2307 err = sci_sck_calc(s, baud, &srr1); 2308 if (abs(err) < abs(min_err)) { 2309 best_clk = SCI_SCK; 2310 scr_val = SCSCR_CKE1; 2311 sccks = SCCKS_CKS; 2312 min_err = err; 2313 srr = srr1; 2314 if (!err) 2315 goto done; 2316 } 2317 } 2318 2319 /* Optional BRG Frequency Divided External Clock */ 2320 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2321 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2322 &srr1); 2323 if (abs(err) < abs(min_err)) { 2324 best_clk = SCI_SCIF_CLK; 2325 scr_val = SCSCR_CKE1; 2326 sccks = 0; 2327 min_err = err; 2328 dl = dl1; 2329 srr = srr1; 2330 if (!err) 2331 goto done; 2332 } 2333 } 2334 2335 /* Optional BRG Frequency Divided Internal Clock */ 2336 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2337 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2338 &srr1); 2339 if (abs(err) < abs(min_err)) { 2340 best_clk = SCI_BRG_INT; 2341 scr_val = SCSCR_CKE1; 2342 sccks = SCCKS_XIN; 2343 min_err = err; 2344 dl = dl1; 2345 srr = srr1; 2346 if (!min_err) 2347 goto done; 2348 } 2349 } 2350 2351 /* Divided Functional Clock using standard Bit Rate Register */ 2352 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2353 if (abs(err) < abs(min_err)) { 2354 best_clk = SCI_FCK; 2355 scr_val = 0; 2356 min_err = err; 2357 brr = brr1; 2358 srr = srr1; 2359 cks = cks1; 2360 } 2361 2362 done: 2363 if (best_clk >= 0) 2364 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2365 s->clks[best_clk], baud, min_err); 2366 2367 sci_port_enable(s); 2368 2369 /* 2370 * Program the optional External Baud Rate Generator (BRG) first. 2371 * It controls the mux to select (H)SCK or frequency divided clock. 2372 */ 2373 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2374 serial_port_out(port, SCDL, dl); 2375 serial_port_out(port, SCCKS, sccks); 2376 } 2377 2378 spin_lock_irqsave(&port->lock, flags); 2379 2380 sci_reset(port); 2381 2382 uart_update_timeout(port, termios->c_cflag, baud); 2383 2384 if (best_clk >= 0) { 2385 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2386 switch (srr + 1) { 2387 case 5: smr_val |= SCSMR_SRC_5; break; 2388 case 7: smr_val |= SCSMR_SRC_7; break; 2389 case 11: smr_val |= SCSMR_SRC_11; break; 2390 case 13: smr_val |= SCSMR_SRC_13; break; 2391 case 16: smr_val |= SCSMR_SRC_16; break; 2392 case 17: smr_val |= SCSMR_SRC_17; break; 2393 case 19: smr_val |= SCSMR_SRC_19; break; 2394 case 27: smr_val |= SCSMR_SRC_27; break; 2395 } 2396 smr_val |= cks; 2397 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2398 serial_port_out(port, SCSMR, smr_val); 2399 serial_port_out(port, SCBRR, brr); 2400 if (sci_getreg(port, HSSRR)->size) 2401 serial_port_out(port, HSSRR, srr | HSCIF_SRE); 2402 2403 /* Wait one bit interval */ 2404 udelay((1000000 + (baud - 1)) / baud); 2405 } else { 2406 /* Don't touch the bit rate configuration */ 2407 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2408 smr_val |= serial_port_in(port, SCSMR) & 2409 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2410 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2411 serial_port_out(port, SCSMR, smr_val); 2412 } 2413 2414 sci_init_pins(port, termios->c_cflag); 2415 2416 port->status &= ~UPSTAT_AUTOCTS; 2417 s->autorts = false; 2418 reg = sci_getreg(port, SCFCR); 2419 if (reg->size) { 2420 unsigned short ctrl = serial_port_in(port, SCFCR); 2421 2422 if ((port->flags & UPF_HARD_FLOW) && 2423 (termios->c_cflag & CRTSCTS)) { 2424 /* There is no CTS interrupt to restart the hardware */ 2425 port->status |= UPSTAT_AUTOCTS; 2426 /* MCE is enabled when RTS is raised */ 2427 s->autorts = true; 2428 } 2429 2430 /* 2431 * As we've done a sci_reset() above, ensure we don't 2432 * interfere with the FIFOs while toggling MCE. As the 2433 * reset values could still be set, simply mask them out. 2434 */ 2435 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2436 2437 serial_port_out(port, SCFCR, ctrl); 2438 } 2439 if (port->flags & UPF_HARD_FLOW) { 2440 /* Refresh (Auto) RTS */ 2441 sci_set_mctrl(port, port->mctrl); 2442 } 2443 2444 scr_val |= SCSCR_RE | SCSCR_TE | 2445 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2446 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2447 if ((srr + 1 == 5) && 2448 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2449 /* 2450 * In asynchronous mode, when the sampling rate is 1/5, first 2451 * received data may become invalid on some SCIFA and SCIFB. 2452 * To avoid this problem wait more than 1 serial data time (1 2453 * bit time x serial data number) after setting SCSCR.RE = 1. 2454 */ 2455 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2456 } 2457 2458 /* 2459 * Calculate delay for 2 DMA buffers (4 FIFO). 2460 * See serial_core.c::uart_update_timeout(). 2461 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2462 * function calculates 1 jiffie for the data plus 5 jiffies for the 2463 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2464 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2465 * value obtained by this formula is too small. Therefore, if the value 2466 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2467 */ 2468 /* byte size and parity */ 2469 switch (termios->c_cflag & CSIZE) { 2470 case CS5: 2471 bits = 7; 2472 break; 2473 case CS6: 2474 bits = 8; 2475 break; 2476 case CS7: 2477 bits = 9; 2478 break; 2479 default: 2480 bits = 10; 2481 break; 2482 } 2483 2484 if (termios->c_cflag & CSTOPB) 2485 bits++; 2486 if (termios->c_cflag & PARENB) 2487 bits++; 2488 2489 s->rx_frame = (100 * bits * HZ) / (baud / 10); 2490 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2491 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000); 2492 if (s->rx_timeout < msecs_to_jiffies(20)) 2493 s->rx_timeout = msecs_to_jiffies(20); 2494 #endif 2495 2496 if ((termios->c_cflag & CREAD) != 0) 2497 sci_start_rx(port); 2498 2499 spin_unlock_irqrestore(&port->lock, flags); 2500 2501 sci_port_disable(s); 2502 2503 if (UART_ENABLE_MS(port, termios->c_cflag)) 2504 sci_enable_ms(port); 2505 } 2506 2507 static void sci_pm(struct uart_port *port, unsigned int state, 2508 unsigned int oldstate) 2509 { 2510 struct sci_port *sci_port = to_sci_port(port); 2511 2512 switch (state) { 2513 case UART_PM_STATE_OFF: 2514 sci_port_disable(sci_port); 2515 break; 2516 default: 2517 sci_port_enable(sci_port); 2518 break; 2519 } 2520 } 2521 2522 static const char *sci_type(struct uart_port *port) 2523 { 2524 switch (port->type) { 2525 case PORT_IRDA: 2526 return "irda"; 2527 case PORT_SCI: 2528 return "sci"; 2529 case PORT_SCIF: 2530 return "scif"; 2531 case PORT_SCIFA: 2532 return "scifa"; 2533 case PORT_SCIFB: 2534 return "scifb"; 2535 case PORT_HSCIF: 2536 return "hscif"; 2537 } 2538 2539 return NULL; 2540 } 2541 2542 static int sci_remap_port(struct uart_port *port) 2543 { 2544 struct sci_port *sport = to_sci_port(port); 2545 2546 /* 2547 * Nothing to do if there's already an established membase. 2548 */ 2549 if (port->membase) 2550 return 0; 2551 2552 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2553 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2554 if (unlikely(!port->membase)) { 2555 dev_err(port->dev, "can't remap port#%d\n", port->line); 2556 return -ENXIO; 2557 } 2558 } else { 2559 /* 2560 * For the simple (and majority of) cases where we don't 2561 * need to do any remapping, just cast the cookie 2562 * directly. 2563 */ 2564 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2565 } 2566 2567 return 0; 2568 } 2569 2570 static void sci_release_port(struct uart_port *port) 2571 { 2572 struct sci_port *sport = to_sci_port(port); 2573 2574 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2575 iounmap(port->membase); 2576 port->membase = NULL; 2577 } 2578 2579 release_mem_region(port->mapbase, sport->reg_size); 2580 } 2581 2582 static int sci_request_port(struct uart_port *port) 2583 { 2584 struct resource *res; 2585 struct sci_port *sport = to_sci_port(port); 2586 int ret; 2587 2588 res = request_mem_region(port->mapbase, sport->reg_size, 2589 dev_name(port->dev)); 2590 if (unlikely(res == NULL)) { 2591 dev_err(port->dev, "request_mem_region failed."); 2592 return -EBUSY; 2593 } 2594 2595 ret = sci_remap_port(port); 2596 if (unlikely(ret != 0)) { 2597 release_resource(res); 2598 return ret; 2599 } 2600 2601 return 0; 2602 } 2603 2604 static void sci_config_port(struct uart_port *port, int flags) 2605 { 2606 if (flags & UART_CONFIG_TYPE) { 2607 struct sci_port *sport = to_sci_port(port); 2608 2609 port->type = sport->cfg->type; 2610 sci_request_port(port); 2611 } 2612 } 2613 2614 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2615 { 2616 if (ser->baud_base < 2400) 2617 /* No paper tape reader for Mitch.. */ 2618 return -EINVAL; 2619 2620 return 0; 2621 } 2622 2623 static const struct uart_ops sci_uart_ops = { 2624 .tx_empty = sci_tx_empty, 2625 .set_mctrl = sci_set_mctrl, 2626 .get_mctrl = sci_get_mctrl, 2627 .start_tx = sci_start_tx, 2628 .stop_tx = sci_stop_tx, 2629 .stop_rx = sci_stop_rx, 2630 .enable_ms = sci_enable_ms, 2631 .break_ctl = sci_break_ctl, 2632 .startup = sci_startup, 2633 .shutdown = sci_shutdown, 2634 .flush_buffer = sci_flush_buffer, 2635 .set_termios = sci_set_termios, 2636 .pm = sci_pm, 2637 .type = sci_type, 2638 .release_port = sci_release_port, 2639 .request_port = sci_request_port, 2640 .config_port = sci_config_port, 2641 .verify_port = sci_verify_port, 2642 #ifdef CONFIG_CONSOLE_POLL 2643 .poll_get_char = sci_poll_get_char, 2644 .poll_put_char = sci_poll_put_char, 2645 #endif 2646 }; 2647 2648 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2649 { 2650 const char *clk_names[] = { 2651 [SCI_FCK] = "fck", 2652 [SCI_SCK] = "sck", 2653 [SCI_BRG_INT] = "brg_int", 2654 [SCI_SCIF_CLK] = "scif_clk", 2655 }; 2656 struct clk *clk; 2657 unsigned int i; 2658 2659 if (sci_port->cfg->type == PORT_HSCIF) 2660 clk_names[SCI_SCK] = "hsck"; 2661 2662 for (i = 0; i < SCI_NUM_CLKS; i++) { 2663 clk = devm_clk_get(dev, clk_names[i]); 2664 if (PTR_ERR(clk) == -EPROBE_DEFER) 2665 return -EPROBE_DEFER; 2666 2667 if (IS_ERR(clk) && i == SCI_FCK) { 2668 /* 2669 * "fck" used to be called "sci_ick", and we need to 2670 * maintain DT backward compatibility. 2671 */ 2672 clk = devm_clk_get(dev, "sci_ick"); 2673 if (PTR_ERR(clk) == -EPROBE_DEFER) 2674 return -EPROBE_DEFER; 2675 2676 if (!IS_ERR(clk)) 2677 goto found; 2678 2679 /* 2680 * Not all SH platforms declare a clock lookup entry 2681 * for SCI devices, in which case we need to get the 2682 * global "peripheral_clk" clock. 2683 */ 2684 clk = devm_clk_get(dev, "peripheral_clk"); 2685 if (!IS_ERR(clk)) 2686 goto found; 2687 2688 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2689 PTR_ERR(clk)); 2690 return PTR_ERR(clk); 2691 } 2692 2693 found: 2694 if (IS_ERR(clk)) 2695 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2696 PTR_ERR(clk)); 2697 else 2698 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i], 2699 clk, clk); 2700 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2701 } 2702 return 0; 2703 } 2704 2705 static const struct sci_port_params * 2706 sci_probe_regmap(const struct plat_sci_port *cfg) 2707 { 2708 unsigned int regtype; 2709 2710 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2711 return &sci_port_params[cfg->regtype]; 2712 2713 switch (cfg->type) { 2714 case PORT_SCI: 2715 regtype = SCIx_SCI_REGTYPE; 2716 break; 2717 case PORT_IRDA: 2718 regtype = SCIx_IRDA_REGTYPE; 2719 break; 2720 case PORT_SCIFA: 2721 regtype = SCIx_SCIFA_REGTYPE; 2722 break; 2723 case PORT_SCIFB: 2724 regtype = SCIx_SCIFB_REGTYPE; 2725 break; 2726 case PORT_SCIF: 2727 /* 2728 * The SH-4 is a bit of a misnomer here, although that's 2729 * where this particular port layout originated. This 2730 * configuration (or some slight variation thereof) 2731 * remains the dominant model for all SCIFs. 2732 */ 2733 regtype = SCIx_SH4_SCIF_REGTYPE; 2734 break; 2735 case PORT_HSCIF: 2736 regtype = SCIx_HSCIF_REGTYPE; 2737 break; 2738 default: 2739 pr_err("Can't probe register map for given port\n"); 2740 return NULL; 2741 } 2742 2743 return &sci_port_params[regtype]; 2744 } 2745 2746 static int sci_init_single(struct platform_device *dev, 2747 struct sci_port *sci_port, unsigned int index, 2748 const struct plat_sci_port *p, bool early) 2749 { 2750 struct uart_port *port = &sci_port->port; 2751 const struct resource *res; 2752 unsigned int i; 2753 int ret; 2754 2755 sci_port->cfg = p; 2756 2757 port->ops = &sci_uart_ops; 2758 port->iotype = UPIO_MEM; 2759 port->line = index; 2760 2761 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2762 if (res == NULL) 2763 return -ENOMEM; 2764 2765 port->mapbase = res->start; 2766 sci_port->reg_size = resource_size(res); 2767 2768 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2769 sci_port->irqs[i] = platform_get_irq(dev, i); 2770 2771 /* The SCI generates several interrupts. They can be muxed together or 2772 * connected to different interrupt lines. In the muxed case only one 2773 * interrupt resource is specified. In the non-muxed case three or four 2774 * interrupt resources are specified, as the BRI interrupt is optional. 2775 */ 2776 if (sci_port->irqs[0] < 0) 2777 return -ENXIO; 2778 2779 if (sci_port->irqs[1] < 0) { 2780 sci_port->irqs[1] = sci_port->irqs[0]; 2781 sci_port->irqs[2] = sci_port->irqs[0]; 2782 sci_port->irqs[3] = sci_port->irqs[0]; 2783 } 2784 2785 sci_port->params = sci_probe_regmap(p); 2786 if (unlikely(sci_port->params == NULL)) 2787 return -EINVAL; 2788 2789 switch (p->type) { 2790 case PORT_SCIFB: 2791 sci_port->rx_trigger = 48; 2792 break; 2793 case PORT_HSCIF: 2794 sci_port->rx_trigger = 64; 2795 break; 2796 case PORT_SCIFA: 2797 sci_port->rx_trigger = 32; 2798 break; 2799 case PORT_SCIF: 2800 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2801 /* RX triggering not implemented for this IP */ 2802 sci_port->rx_trigger = 1; 2803 else 2804 sci_port->rx_trigger = 8; 2805 break; 2806 default: 2807 sci_port->rx_trigger = 1; 2808 break; 2809 } 2810 2811 sci_port->rx_fifo_timeout = 0; 2812 sci_port->hscif_tot = 0; 2813 2814 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2815 * match the SoC datasheet, this should be investigated. Let platform 2816 * data override the sampling rate for now. 2817 */ 2818 sci_port->sampling_rate_mask = p->sampling_rate 2819 ? SCI_SR(p->sampling_rate) 2820 : sci_port->params->sampling_rate_mask; 2821 2822 if (!early) { 2823 ret = sci_init_clocks(sci_port, &dev->dev); 2824 if (ret < 0) 2825 return ret; 2826 2827 port->dev = &dev->dev; 2828 2829 pm_runtime_enable(&dev->dev); 2830 } 2831 2832 port->type = p->type; 2833 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2834 port->fifosize = sci_port->params->fifosize; 2835 2836 if (port->type == PORT_SCI) { 2837 if (sci_port->reg_size >= 0x20) 2838 port->regshift = 2; 2839 else 2840 port->regshift = 1; 2841 } 2842 2843 /* 2844 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2845 * for the multi-IRQ ports, which is where we are primarily 2846 * concerned with the shutdown path synchronization. 2847 * 2848 * For the muxed case there's nothing more to do. 2849 */ 2850 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2851 port->irqflags = 0; 2852 2853 port->serial_in = sci_serial_in; 2854 port->serial_out = sci_serial_out; 2855 2856 return 0; 2857 } 2858 2859 static void sci_cleanup_single(struct sci_port *port) 2860 { 2861 pm_runtime_disable(port->port.dev); 2862 } 2863 2864 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2865 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2866 static void serial_console_putchar(struct uart_port *port, int ch) 2867 { 2868 sci_poll_put_char(port, ch); 2869 } 2870 2871 /* 2872 * Print a string to the serial port trying not to disturb 2873 * any possible real use of the port... 2874 */ 2875 static void serial_console_write(struct console *co, const char *s, 2876 unsigned count) 2877 { 2878 struct sci_port *sci_port = &sci_ports[co->index]; 2879 struct uart_port *port = &sci_port->port; 2880 unsigned short bits, ctrl, ctrl_temp; 2881 unsigned long flags; 2882 int locked = 1; 2883 2884 local_irq_save(flags); 2885 #if defined(SUPPORT_SYSRQ) 2886 if (port->sysrq) 2887 locked = 0; 2888 else 2889 #endif 2890 if (oops_in_progress) 2891 locked = spin_trylock(&port->lock); 2892 else 2893 spin_lock(&port->lock); 2894 2895 /* first save SCSCR then disable interrupts, keep clock source */ 2896 ctrl = serial_port_in(port, SCSCR); 2897 ctrl_temp = SCSCR_RE | SCSCR_TE | 2898 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 2899 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 2900 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 2901 2902 uart_console_write(port, s, count, serial_console_putchar); 2903 2904 /* wait until fifo is empty and last bit has been transmitted */ 2905 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2906 while ((serial_port_in(port, SCxSR) & bits) != bits) 2907 cpu_relax(); 2908 2909 /* restore the SCSCR */ 2910 serial_port_out(port, SCSCR, ctrl); 2911 2912 if (locked) 2913 spin_unlock(&port->lock); 2914 local_irq_restore(flags); 2915 } 2916 2917 static int serial_console_setup(struct console *co, char *options) 2918 { 2919 struct sci_port *sci_port; 2920 struct uart_port *port; 2921 int baud = 115200; 2922 int bits = 8; 2923 int parity = 'n'; 2924 int flow = 'n'; 2925 int ret; 2926 2927 /* 2928 * Refuse to handle any bogus ports. 2929 */ 2930 if (co->index < 0 || co->index >= SCI_NPORTS) 2931 return -ENODEV; 2932 2933 sci_port = &sci_ports[co->index]; 2934 port = &sci_port->port; 2935 2936 /* 2937 * Refuse to handle uninitialized ports. 2938 */ 2939 if (!port->ops) 2940 return -ENODEV; 2941 2942 ret = sci_remap_port(port); 2943 if (unlikely(ret != 0)) 2944 return ret; 2945 2946 if (options) 2947 uart_parse_options(options, &baud, &parity, &bits, &flow); 2948 2949 return uart_set_options(port, co, baud, parity, bits, flow); 2950 } 2951 2952 static struct console serial_console = { 2953 .name = "ttySC", 2954 .device = uart_console_device, 2955 .write = serial_console_write, 2956 .setup = serial_console_setup, 2957 .flags = CON_PRINTBUFFER, 2958 .index = -1, 2959 .data = &sci_uart_driver, 2960 }; 2961 2962 static struct console early_serial_console = { 2963 .name = "early_ttySC", 2964 .write = serial_console_write, 2965 .flags = CON_PRINTBUFFER, 2966 .index = -1, 2967 }; 2968 2969 static char early_serial_buf[32]; 2970 2971 static int sci_probe_earlyprintk(struct platform_device *pdev) 2972 { 2973 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 2974 2975 if (early_serial_console.data) 2976 return -EEXIST; 2977 2978 early_serial_console.index = pdev->id; 2979 2980 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 2981 2982 serial_console_setup(&early_serial_console, early_serial_buf); 2983 2984 if (!strstr(early_serial_buf, "keep")) 2985 early_serial_console.flags |= CON_BOOT; 2986 2987 register_console(&early_serial_console); 2988 return 0; 2989 } 2990 2991 #define SCI_CONSOLE (&serial_console) 2992 2993 #else 2994 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 2995 { 2996 return -EINVAL; 2997 } 2998 2999 #define SCI_CONSOLE NULL 3000 3001 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3002 3003 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3004 3005 static DEFINE_MUTEX(sci_uart_registration_lock); 3006 static struct uart_driver sci_uart_driver = { 3007 .owner = THIS_MODULE, 3008 .driver_name = "sci", 3009 .dev_name = "ttySC", 3010 .major = SCI_MAJOR, 3011 .minor = SCI_MINOR_START, 3012 .nr = SCI_NPORTS, 3013 .cons = SCI_CONSOLE, 3014 }; 3015 3016 static int sci_remove(struct platform_device *dev) 3017 { 3018 struct sci_port *port = platform_get_drvdata(dev); 3019 3020 uart_remove_one_port(&sci_uart_driver, &port->port); 3021 3022 sci_cleanup_single(port); 3023 3024 if (port->port.fifosize > 1) { 3025 sysfs_remove_file(&dev->dev.kobj, 3026 &dev_attr_rx_fifo_trigger.attr); 3027 } 3028 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB || 3029 port->port.type == PORT_HSCIF) { 3030 sysfs_remove_file(&dev->dev.kobj, 3031 &dev_attr_rx_fifo_timeout.attr); 3032 } 3033 3034 return 0; 3035 } 3036 3037 3038 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3039 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3040 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3041 3042 static const struct of_device_id of_sci_match[] = { 3043 /* SoC-specific types */ 3044 { 3045 .compatible = "renesas,scif-r7s72100", 3046 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3047 }, 3048 /* Family-specific types */ 3049 { 3050 .compatible = "renesas,rcar-gen1-scif", 3051 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3052 }, { 3053 .compatible = "renesas,rcar-gen2-scif", 3054 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3055 }, { 3056 .compatible = "renesas,rcar-gen3-scif", 3057 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3058 }, 3059 /* Generic types */ 3060 { 3061 .compatible = "renesas,scif", 3062 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3063 }, { 3064 .compatible = "renesas,scifa", 3065 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3066 }, { 3067 .compatible = "renesas,scifb", 3068 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3069 }, { 3070 .compatible = "renesas,hscif", 3071 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3072 }, { 3073 .compatible = "renesas,sci", 3074 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3075 }, { 3076 /* Terminator */ 3077 }, 3078 }; 3079 MODULE_DEVICE_TABLE(of, of_sci_match); 3080 3081 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3082 unsigned int *dev_id) 3083 { 3084 struct device_node *np = pdev->dev.of_node; 3085 struct plat_sci_port *p; 3086 struct sci_port *sp; 3087 const void *data; 3088 int id; 3089 3090 if (!IS_ENABLED(CONFIG_OF) || !np) 3091 return NULL; 3092 3093 data = of_device_get_match_data(&pdev->dev); 3094 3095 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3096 if (!p) 3097 return NULL; 3098 3099 /* Get the line number from the aliases node. */ 3100 id = of_alias_get_id(np, "serial"); 3101 if (id < 0) { 3102 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3103 return NULL; 3104 } 3105 3106 sp = &sci_ports[id]; 3107 *dev_id = id; 3108 3109 p->type = SCI_OF_TYPE(data); 3110 p->regtype = SCI_OF_REGTYPE(data); 3111 3112 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3113 3114 return p; 3115 } 3116 3117 static int sci_probe_single(struct platform_device *dev, 3118 unsigned int index, 3119 struct plat_sci_port *p, 3120 struct sci_port *sciport) 3121 { 3122 int ret; 3123 3124 /* Sanity check */ 3125 if (unlikely(index >= SCI_NPORTS)) { 3126 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3127 index+1, SCI_NPORTS); 3128 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3129 return -EINVAL; 3130 } 3131 3132 mutex_lock(&sci_uart_registration_lock); 3133 if (!sci_uart_driver.state) { 3134 ret = uart_register_driver(&sci_uart_driver); 3135 if (ret) { 3136 mutex_unlock(&sci_uart_registration_lock); 3137 return ret; 3138 } 3139 } 3140 mutex_unlock(&sci_uart_registration_lock); 3141 3142 ret = sci_init_single(dev, sciport, index, p, false); 3143 if (ret) 3144 return ret; 3145 3146 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3147 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS) 3148 return PTR_ERR(sciport->gpios); 3149 3150 if (sciport->has_rtscts) { 3151 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3152 UART_GPIO_CTS)) || 3153 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3154 UART_GPIO_RTS))) { 3155 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3156 return -EINVAL; 3157 } 3158 sciport->port.flags |= UPF_HARD_FLOW; 3159 } 3160 3161 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3162 if (ret) { 3163 sci_cleanup_single(sciport); 3164 return ret; 3165 } 3166 3167 return 0; 3168 } 3169 3170 static int sci_probe(struct platform_device *dev) 3171 { 3172 struct plat_sci_port *p; 3173 struct sci_port *sp; 3174 unsigned int dev_id; 3175 int ret; 3176 3177 /* 3178 * If we've come here via earlyprintk initialization, head off to 3179 * the special early probe. We don't have sufficient device state 3180 * to make it beyond this yet. 3181 */ 3182 if (is_early_platform_device(dev)) 3183 return sci_probe_earlyprintk(dev); 3184 3185 if (dev->dev.of_node) { 3186 p = sci_parse_dt(dev, &dev_id); 3187 if (p == NULL) 3188 return -EINVAL; 3189 } else { 3190 p = dev->dev.platform_data; 3191 if (p == NULL) { 3192 dev_err(&dev->dev, "no platform data supplied\n"); 3193 return -EINVAL; 3194 } 3195 3196 dev_id = dev->id; 3197 } 3198 3199 sp = &sci_ports[dev_id]; 3200 platform_set_drvdata(dev, sp); 3201 3202 ret = sci_probe_single(dev, dev_id, p, sp); 3203 if (ret) 3204 return ret; 3205 3206 if (sp->port.fifosize > 1) { 3207 ret = sysfs_create_file(&dev->dev.kobj, 3208 &dev_attr_rx_fifo_trigger.attr); 3209 if (ret) 3210 return ret; 3211 } 3212 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3213 sp->port.type == PORT_HSCIF) { 3214 ret = sysfs_create_file(&dev->dev.kobj, 3215 &dev_attr_rx_fifo_timeout.attr); 3216 if (ret) { 3217 if (sp->port.fifosize > 1) { 3218 sysfs_remove_file(&dev->dev.kobj, 3219 &dev_attr_rx_fifo_trigger.attr); 3220 } 3221 return ret; 3222 } 3223 } 3224 3225 #ifdef CONFIG_SH_STANDARD_BIOS 3226 sh_bios_gdb_detach(); 3227 #endif 3228 3229 return 0; 3230 } 3231 3232 static __maybe_unused int sci_suspend(struct device *dev) 3233 { 3234 struct sci_port *sport = dev_get_drvdata(dev); 3235 3236 if (sport) 3237 uart_suspend_port(&sci_uart_driver, &sport->port); 3238 3239 return 0; 3240 } 3241 3242 static __maybe_unused int sci_resume(struct device *dev) 3243 { 3244 struct sci_port *sport = dev_get_drvdata(dev); 3245 3246 if (sport) 3247 uart_resume_port(&sci_uart_driver, &sport->port); 3248 3249 return 0; 3250 } 3251 3252 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3253 3254 static struct platform_driver sci_driver = { 3255 .probe = sci_probe, 3256 .remove = sci_remove, 3257 .driver = { 3258 .name = "sh-sci", 3259 .pm = &sci_dev_pm_ops, 3260 .of_match_table = of_match_ptr(of_sci_match), 3261 }, 3262 }; 3263 3264 static int __init sci_init(void) 3265 { 3266 pr_info("%s\n", banner); 3267 3268 return platform_driver_register(&sci_driver); 3269 } 3270 3271 static void __exit sci_exit(void) 3272 { 3273 platform_driver_unregister(&sci_driver); 3274 3275 if (sci_uart_driver.state) 3276 uart_unregister_driver(&sci_uart_driver); 3277 } 3278 3279 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 3280 early_platform_init_buffer("earlyprintk", &sci_driver, 3281 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3282 #endif 3283 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3284 static struct plat_sci_port port_cfg __initdata; 3285 3286 static int __init early_console_setup(struct earlycon_device *device, 3287 int type) 3288 { 3289 if (!device->port.membase) 3290 return -ENODEV; 3291 3292 device->port.serial_in = sci_serial_in; 3293 device->port.serial_out = sci_serial_out; 3294 device->port.type = type; 3295 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3296 port_cfg.type = type; 3297 sci_ports[0].cfg = &port_cfg; 3298 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3299 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3300 sci_serial_out(&sci_ports[0].port, SCSCR, 3301 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3302 3303 device->con->write = serial_console_write; 3304 return 0; 3305 } 3306 static int __init sci_early_console_setup(struct earlycon_device *device, 3307 const char *opt) 3308 { 3309 return early_console_setup(device, PORT_SCI); 3310 } 3311 static int __init scif_early_console_setup(struct earlycon_device *device, 3312 const char *opt) 3313 { 3314 return early_console_setup(device, PORT_SCIF); 3315 } 3316 static int __init scifa_early_console_setup(struct earlycon_device *device, 3317 const char *opt) 3318 { 3319 return early_console_setup(device, PORT_SCIFA); 3320 } 3321 static int __init scifb_early_console_setup(struct earlycon_device *device, 3322 const char *opt) 3323 { 3324 return early_console_setup(device, PORT_SCIFB); 3325 } 3326 static int __init hscif_early_console_setup(struct earlycon_device *device, 3327 const char *opt) 3328 { 3329 return early_console_setup(device, PORT_HSCIF); 3330 } 3331 3332 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3333 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3334 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3335 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3336 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3337 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3338 3339 module_init(sci_init); 3340 module_exit(sci_exit); 3341 3342 MODULE_LICENSE("GPL"); 3343 MODULE_ALIAS("platform:sh-sci"); 3344 MODULE_AUTHOR("Paul Mundt"); 3345 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3346