1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/minmax.h> 35 #include <linux/module.h> 36 #include <linux/mm.h> 37 #include <linux/of.h> 38 #include <linux/platform_device.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/reset.h> 41 #include <linux/scatterlist.h> 42 #include <linux/serial.h> 43 #include <linux/serial_sci.h> 44 #include <linux/sh_dma.h> 45 #include <linux/slab.h> 46 #include <linux/string.h> 47 #include <linux/sysrq.h> 48 #include <linux/timer.h> 49 #include <linux/tty.h> 50 #include <linux/tty_flip.h> 51 52 #ifdef CONFIG_SUPERH 53 #include <asm/sh_bios.h> 54 #include <asm/platform_early.h> 55 #endif 56 57 #include "serial_mctrl_gpio.h" 58 #include "sh-sci.h" 59 60 /* Offsets into the sci_port->irqs array */ 61 enum { 62 SCIx_ERI_IRQ, 63 SCIx_RXI_IRQ, 64 SCIx_TXI_IRQ, 65 SCIx_BRI_IRQ, 66 SCIx_DRI_IRQ, 67 SCIx_TEI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71 }; 72 73 #define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79 enum SCI_CLKS { 80 SCI_FCK, /* Functional Clock */ 81 SCI_SCK, /* Optional External Clock */ 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 84 SCI_NUM_CLKS 85 }; 86 87 /* Bit x set means sampling rate x + 1 is supported */ 88 #define SCI_SR(x) BIT((x) - 1) 89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 90 91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 93 SCI_SR(19) | SCI_SR(27) 94 95 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 96 #define max_sr(_port) fls((_port)->sampling_rate_mask) 97 98 /* Iterate over all supported sampling rates, from high to low */ 99 #define for_each_sr(_sr, _port) \ 100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 101 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 102 103 struct plat_sci_reg { 104 u8 offset, size; 105 }; 106 107 struct sci_port_params { 108 const struct plat_sci_reg regs[SCIx_NR_REGS]; 109 unsigned int fifosize; 110 unsigned int overrun_reg; 111 unsigned int overrun_mask; 112 unsigned int sampling_rate_mask; 113 unsigned int error_mask; 114 unsigned int error_clear; 115 }; 116 117 struct sci_port { 118 struct uart_port port; 119 120 /* Platform configuration */ 121 const struct sci_port_params *params; 122 const struct plat_sci_port *cfg; 123 unsigned int sampling_rate_mask; 124 resource_size_t reg_size; 125 struct mctrl_gpios *gpios; 126 127 /* Clocks */ 128 struct clk *clks[SCI_NUM_CLKS]; 129 unsigned long clk_rates[SCI_NUM_CLKS]; 130 131 int irqs[SCIx_NR_IRQS]; 132 char *irqstr[SCIx_NR_IRQS]; 133 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 137 #ifdef CONFIG_SERIAL_SH_SCI_DMA 138 struct dma_chan *chan_tx_saved; 139 struct dma_chan *chan_rx_saved; 140 dma_cookie_t cookie_tx; 141 dma_cookie_t cookie_rx[2]; 142 dma_cookie_t active_rx; 143 dma_addr_t tx_dma_addr; 144 unsigned int tx_dma_len; 145 struct scatterlist sg_rx[2]; 146 void *rx_buf[2]; 147 size_t buf_len_rx; 148 struct work_struct work_tx; 149 struct hrtimer rx_timer; 150 unsigned int rx_timeout; /* microseconds */ 151 #endif 152 unsigned int rx_frame; 153 int rx_trigger; 154 struct timer_list rx_fifo_timer; 155 int rx_fifo_timeout; 156 u16 hscif_tot; 157 158 bool has_rtscts; 159 bool autorts; 160 }; 161 162 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 163 164 static struct sci_port sci_ports[SCI_NPORTS]; 165 static unsigned long sci_ports_in_use; 166 static struct uart_driver sci_uart_driver; 167 168 static inline struct sci_port * 169 to_sci_port(struct uart_port *uart) 170 { 171 return container_of(uart, struct sci_port, port); 172 } 173 174 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 175 /* 176 * Common SCI definitions, dependent on the port's regshift 177 * value. 178 */ 179 [SCIx_SCI_REGTYPE] = { 180 .regs = { 181 [SCSMR] = { 0x00, 8 }, 182 [SCBRR] = { 0x01, 8 }, 183 [SCSCR] = { 0x02, 8 }, 184 [SCxTDR] = { 0x03, 8 }, 185 [SCxSR] = { 0x04, 8 }, 186 [SCxRDR] = { 0x05, 8 }, 187 }, 188 .fifosize = 1, 189 .overrun_reg = SCxSR, 190 .overrun_mask = SCI_ORER, 191 .sampling_rate_mask = SCI_SR(32), 192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 194 }, 195 196 /* 197 * Common definitions for legacy IrDA ports. 198 */ 199 [SCIx_IRDA_REGTYPE] = { 200 .regs = { 201 [SCSMR] = { 0x00, 8 }, 202 [SCBRR] = { 0x02, 8 }, 203 [SCSCR] = { 0x04, 8 }, 204 [SCxTDR] = { 0x06, 8 }, 205 [SCxSR] = { 0x08, 16 }, 206 [SCxRDR] = { 0x0a, 8 }, 207 [SCFCR] = { 0x0c, 8 }, 208 [SCFDR] = { 0x0e, 16 }, 209 }, 210 .fifosize = 1, 211 .overrun_reg = SCxSR, 212 .overrun_mask = SCI_ORER, 213 .sampling_rate_mask = SCI_SR(32), 214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 216 }, 217 218 /* 219 * Common SCIFA definitions. 220 */ 221 [SCIx_SCIFA_REGTYPE] = { 222 .regs = { 223 [SCSMR] = { 0x00, 16 }, 224 [SCBRR] = { 0x04, 8 }, 225 [SCSCR] = { 0x08, 16 }, 226 [SCxTDR] = { 0x20, 8 }, 227 [SCxSR] = { 0x14, 16 }, 228 [SCxRDR] = { 0x24, 8 }, 229 [SCFCR] = { 0x18, 16 }, 230 [SCFDR] = { 0x1c, 16 }, 231 [SCPCR] = { 0x30, 16 }, 232 [SCPDR] = { 0x34, 16 }, 233 }, 234 .fifosize = 64, 235 .overrun_reg = SCxSR, 236 .overrun_mask = SCIFA_ORER, 237 .sampling_rate_mask = SCI_SR_SCIFAB, 238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 240 }, 241 242 /* 243 * Common SCIFB definitions. 244 */ 245 [SCIx_SCIFB_REGTYPE] = { 246 .regs = { 247 [SCSMR] = { 0x00, 16 }, 248 [SCBRR] = { 0x04, 8 }, 249 [SCSCR] = { 0x08, 16 }, 250 [SCxTDR] = { 0x40, 8 }, 251 [SCxSR] = { 0x14, 16 }, 252 [SCxRDR] = { 0x60, 8 }, 253 [SCFCR] = { 0x18, 16 }, 254 [SCTFDR] = { 0x38, 16 }, 255 [SCRFDR] = { 0x3c, 16 }, 256 [SCPCR] = { 0x30, 16 }, 257 [SCPDR] = { 0x34, 16 }, 258 }, 259 .fifosize = 256, 260 .overrun_reg = SCxSR, 261 .overrun_mask = SCIFA_ORER, 262 .sampling_rate_mask = SCI_SR_SCIFAB, 263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 265 }, 266 267 /* 268 * Common SH-2(A) SCIF definitions for ports with FIFO data 269 * count registers. 270 */ 271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 272 .regs = { 273 [SCSMR] = { 0x00, 16 }, 274 [SCBRR] = { 0x04, 8 }, 275 [SCSCR] = { 0x08, 16 }, 276 [SCxTDR] = { 0x0c, 8 }, 277 [SCxSR] = { 0x10, 16 }, 278 [SCxRDR] = { 0x14, 8 }, 279 [SCFCR] = { 0x18, 16 }, 280 [SCFDR] = { 0x1c, 16 }, 281 [SCSPTR] = { 0x20, 16 }, 282 [SCLSR] = { 0x24, 16 }, 283 }, 284 .fifosize = 16, 285 .overrun_reg = SCLSR, 286 .overrun_mask = SCLSR_ORER, 287 .sampling_rate_mask = SCI_SR(32), 288 .error_mask = SCIF_DEFAULT_ERROR_MASK, 289 .error_clear = SCIF_ERROR_CLEAR, 290 }, 291 292 /* 293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 294 * It looks like a normal SCIF with FIFO data, but with a 295 * compressed address space. Also, the break out of interrupts 296 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 297 */ 298 [SCIx_RZ_SCIFA_REGTYPE] = { 299 .regs = { 300 [SCSMR] = { 0x00, 16 }, 301 [SCBRR] = { 0x02, 8 }, 302 [SCSCR] = { 0x04, 16 }, 303 [SCxTDR] = { 0x06, 8 }, 304 [SCxSR] = { 0x08, 16 }, 305 [SCxRDR] = { 0x0A, 8 }, 306 [SCFCR] = { 0x0C, 16 }, 307 [SCFDR] = { 0x0E, 16 }, 308 [SCSPTR] = { 0x10, 16 }, 309 [SCLSR] = { 0x12, 16 }, 310 [SEMR] = { 0x14, 8 }, 311 }, 312 .fifosize = 16, 313 .overrun_reg = SCLSR, 314 .overrun_mask = SCLSR_ORER, 315 .sampling_rate_mask = SCI_SR(32), 316 .error_mask = SCIF_DEFAULT_ERROR_MASK, 317 .error_clear = SCIF_ERROR_CLEAR, 318 }, 319 320 /* 321 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC 322 * with below differences, 323 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI, 324 * TEI-DRI, RXI-EDGE and TXI-EDGE. 325 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode. 326 * - SCFCR register does not have SCFCR_MCE bit. 327 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO. 328 */ 329 [SCIx_RZV2H_SCIF_REGTYPE] = { 330 .regs = { 331 [SCSMR] = { 0x00, 16 }, 332 [SCBRR] = { 0x02, 8 }, 333 [SCSCR] = { 0x04, 16 }, 334 [SCxTDR] = { 0x06, 8 }, 335 [SCxSR] = { 0x08, 16 }, 336 [SCxRDR] = { 0x0a, 8 }, 337 [SCFCR] = { 0x0c, 16 }, 338 [SCFDR] = { 0x0e, 16 }, 339 [SCSPTR] = { 0x10, 16 }, 340 [SCLSR] = { 0x12, 16 }, 341 [SEMR] = { 0x14, 8 }, 342 }, 343 .fifosize = 16, 344 .overrun_reg = SCLSR, 345 .overrun_mask = SCLSR_ORER, 346 .sampling_rate_mask = SCI_SR(32), 347 .error_mask = SCIF_DEFAULT_ERROR_MASK, 348 .error_clear = SCIF_ERROR_CLEAR, 349 }, 350 351 /* 352 * Common SH-3 SCIF definitions. 353 */ 354 [SCIx_SH3_SCIF_REGTYPE] = { 355 .regs = { 356 [SCSMR] = { 0x00, 8 }, 357 [SCBRR] = { 0x02, 8 }, 358 [SCSCR] = { 0x04, 8 }, 359 [SCxTDR] = { 0x06, 8 }, 360 [SCxSR] = { 0x08, 16 }, 361 [SCxRDR] = { 0x0a, 8 }, 362 [SCFCR] = { 0x0c, 8 }, 363 [SCFDR] = { 0x0e, 16 }, 364 }, 365 .fifosize = 16, 366 .overrun_reg = SCLSR, 367 .overrun_mask = SCLSR_ORER, 368 .sampling_rate_mask = SCI_SR(32), 369 .error_mask = SCIF_DEFAULT_ERROR_MASK, 370 .error_clear = SCIF_ERROR_CLEAR, 371 }, 372 373 /* 374 * Common SH-4(A) SCIF(B) definitions. 375 */ 376 [SCIx_SH4_SCIF_REGTYPE] = { 377 .regs = { 378 [SCSMR] = { 0x00, 16 }, 379 [SCBRR] = { 0x04, 8 }, 380 [SCSCR] = { 0x08, 16 }, 381 [SCxTDR] = { 0x0c, 8 }, 382 [SCxSR] = { 0x10, 16 }, 383 [SCxRDR] = { 0x14, 8 }, 384 [SCFCR] = { 0x18, 16 }, 385 [SCFDR] = { 0x1c, 16 }, 386 [SCSPTR] = { 0x20, 16 }, 387 [SCLSR] = { 0x24, 16 }, 388 }, 389 .fifosize = 16, 390 .overrun_reg = SCLSR, 391 .overrun_mask = SCLSR_ORER, 392 .sampling_rate_mask = SCI_SR(32), 393 .error_mask = SCIF_DEFAULT_ERROR_MASK, 394 .error_clear = SCIF_ERROR_CLEAR, 395 }, 396 397 /* 398 * Common SCIF definitions for ports with a Baud Rate Generator for 399 * External Clock (BRG). 400 */ 401 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 402 .regs = { 403 [SCSMR] = { 0x00, 16 }, 404 [SCBRR] = { 0x04, 8 }, 405 [SCSCR] = { 0x08, 16 }, 406 [SCxTDR] = { 0x0c, 8 }, 407 [SCxSR] = { 0x10, 16 }, 408 [SCxRDR] = { 0x14, 8 }, 409 [SCFCR] = { 0x18, 16 }, 410 [SCFDR] = { 0x1c, 16 }, 411 [SCSPTR] = { 0x20, 16 }, 412 [SCLSR] = { 0x24, 16 }, 413 [SCDL] = { 0x30, 16 }, 414 [SCCKS] = { 0x34, 16 }, 415 }, 416 .fifosize = 16, 417 .overrun_reg = SCLSR, 418 .overrun_mask = SCLSR_ORER, 419 .sampling_rate_mask = SCI_SR(32), 420 .error_mask = SCIF_DEFAULT_ERROR_MASK, 421 .error_clear = SCIF_ERROR_CLEAR, 422 }, 423 424 /* 425 * Common HSCIF definitions. 426 */ 427 [SCIx_HSCIF_REGTYPE] = { 428 .regs = { 429 [SCSMR] = { 0x00, 16 }, 430 [SCBRR] = { 0x04, 8 }, 431 [SCSCR] = { 0x08, 16 }, 432 [SCxTDR] = { 0x0c, 8 }, 433 [SCxSR] = { 0x10, 16 }, 434 [SCxRDR] = { 0x14, 8 }, 435 [SCFCR] = { 0x18, 16 }, 436 [SCFDR] = { 0x1c, 16 }, 437 [SCSPTR] = { 0x20, 16 }, 438 [SCLSR] = { 0x24, 16 }, 439 [HSSRR] = { 0x40, 16 }, 440 [SCDL] = { 0x30, 16 }, 441 [SCCKS] = { 0x34, 16 }, 442 [HSRTRGR] = { 0x54, 16 }, 443 [HSTTRGR] = { 0x58, 16 }, 444 }, 445 .fifosize = 128, 446 .overrun_reg = SCLSR, 447 .overrun_mask = SCLSR_ORER, 448 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 449 .error_mask = SCIF_DEFAULT_ERROR_MASK, 450 .error_clear = SCIF_ERROR_CLEAR, 451 }, 452 453 /* 454 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 455 * register. 456 */ 457 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 458 .regs = { 459 [SCSMR] = { 0x00, 16 }, 460 [SCBRR] = { 0x04, 8 }, 461 [SCSCR] = { 0x08, 16 }, 462 [SCxTDR] = { 0x0c, 8 }, 463 [SCxSR] = { 0x10, 16 }, 464 [SCxRDR] = { 0x14, 8 }, 465 [SCFCR] = { 0x18, 16 }, 466 [SCFDR] = { 0x1c, 16 }, 467 [SCLSR] = { 0x24, 16 }, 468 }, 469 .fifosize = 16, 470 .overrun_reg = SCLSR, 471 .overrun_mask = SCLSR_ORER, 472 .sampling_rate_mask = SCI_SR(32), 473 .error_mask = SCIF_DEFAULT_ERROR_MASK, 474 .error_clear = SCIF_ERROR_CLEAR, 475 }, 476 477 /* 478 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 479 * count registers. 480 */ 481 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 482 .regs = { 483 [SCSMR] = { 0x00, 16 }, 484 [SCBRR] = { 0x04, 8 }, 485 [SCSCR] = { 0x08, 16 }, 486 [SCxTDR] = { 0x0c, 8 }, 487 [SCxSR] = { 0x10, 16 }, 488 [SCxRDR] = { 0x14, 8 }, 489 [SCFCR] = { 0x18, 16 }, 490 [SCFDR] = { 0x1c, 16 }, 491 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 492 [SCRFDR] = { 0x20, 16 }, 493 [SCSPTR] = { 0x24, 16 }, 494 [SCLSR] = { 0x28, 16 }, 495 }, 496 .fifosize = 16, 497 .overrun_reg = SCLSR, 498 .overrun_mask = SCLSR_ORER, 499 .sampling_rate_mask = SCI_SR(32), 500 .error_mask = SCIF_DEFAULT_ERROR_MASK, 501 .error_clear = SCIF_ERROR_CLEAR, 502 }, 503 504 /* 505 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 506 * registers. 507 */ 508 [SCIx_SH7705_SCIF_REGTYPE] = { 509 .regs = { 510 [SCSMR] = { 0x00, 16 }, 511 [SCBRR] = { 0x04, 8 }, 512 [SCSCR] = { 0x08, 16 }, 513 [SCxTDR] = { 0x20, 8 }, 514 [SCxSR] = { 0x14, 16 }, 515 [SCxRDR] = { 0x24, 8 }, 516 [SCFCR] = { 0x18, 16 }, 517 [SCFDR] = { 0x1c, 16 }, 518 }, 519 .fifosize = 64, 520 .overrun_reg = SCxSR, 521 .overrun_mask = SCIFA_ORER, 522 .sampling_rate_mask = SCI_SR(16), 523 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 524 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 525 }, 526 }; 527 528 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 529 530 /* 531 * The "offset" here is rather misleading, in that it refers to an enum 532 * value relative to the port mapping rather than the fixed offset 533 * itself, which needs to be manually retrieved from the platform's 534 * register map for the given port. 535 */ 536 static unsigned int sci_serial_in(struct uart_port *p, int offset) 537 { 538 const struct plat_sci_reg *reg = sci_getreg(p, offset); 539 540 if (reg->size == 8) 541 return ioread8(p->membase + (reg->offset << p->regshift)); 542 else if (reg->size == 16) 543 return ioread16(p->membase + (reg->offset << p->regshift)); 544 else 545 WARN(1, "Invalid register access\n"); 546 547 return 0; 548 } 549 550 static void sci_serial_out(struct uart_port *p, int offset, int value) 551 { 552 const struct plat_sci_reg *reg = sci_getreg(p, offset); 553 554 if (reg->size == 8) 555 iowrite8(value, p->membase + (reg->offset << p->regshift)); 556 else if (reg->size == 16) 557 iowrite16(value, p->membase + (reg->offset << p->regshift)); 558 else 559 WARN(1, "Invalid register access\n"); 560 } 561 562 static void sci_port_enable(struct sci_port *sci_port) 563 { 564 unsigned int i; 565 566 if (!sci_port->port.dev) 567 return; 568 569 pm_runtime_get_sync(sci_port->port.dev); 570 571 for (i = 0; i < SCI_NUM_CLKS; i++) { 572 clk_prepare_enable(sci_port->clks[i]); 573 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 574 } 575 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 576 } 577 578 static void sci_port_disable(struct sci_port *sci_port) 579 { 580 unsigned int i; 581 582 if (!sci_port->port.dev) 583 return; 584 585 for (i = SCI_NUM_CLKS; i-- > 0; ) 586 clk_disable_unprepare(sci_port->clks[i]); 587 588 pm_runtime_put_sync(sci_port->port.dev); 589 } 590 591 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 592 { 593 /* 594 * Not all ports (such as SCIFA) will support REIE. Rather than 595 * special-casing the port type, we check the port initialization 596 * IRQ enable mask to see whether the IRQ is desired at all. If 597 * it's unset, it's logically inferred that there's no point in 598 * testing for it. 599 */ 600 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 601 } 602 603 static void sci_start_tx(struct uart_port *port) 604 { 605 struct sci_port *s = to_sci_port(port); 606 unsigned short ctrl; 607 608 #ifdef CONFIG_SERIAL_SH_SCI_DMA 609 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 610 u16 new, scr = sci_serial_in(port, SCSCR); 611 if (s->chan_tx) 612 new = scr | SCSCR_TDRQE; 613 else 614 new = scr & ~SCSCR_TDRQE; 615 if (new != scr) 616 sci_serial_out(port, SCSCR, new); 617 } 618 619 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) && 620 dma_submit_error(s->cookie_tx)) { 621 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 622 /* Switch irq from SCIF to DMA */ 623 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); 624 625 s->cookie_tx = 0; 626 schedule_work(&s->work_tx); 627 } 628 #endif 629 630 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || 631 port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 632 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 633 ctrl = sci_serial_in(port, SCSCR); 634 635 /* 636 * For SCI, TE (transmit enable) must be set after setting TIE 637 * (transmit interrupt enable) or in the same instruction to start 638 * the transmit process. 639 */ 640 if (port->type == PORT_SCI) 641 ctrl |= SCSCR_TE; 642 643 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE); 644 } 645 } 646 647 static void sci_stop_tx(struct uart_port *port) 648 { 649 unsigned short ctrl; 650 651 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 652 ctrl = sci_serial_in(port, SCSCR); 653 654 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 655 ctrl &= ~SCSCR_TDRQE; 656 657 ctrl &= ~SCSCR_TIE; 658 659 sci_serial_out(port, SCSCR, ctrl); 660 661 #ifdef CONFIG_SERIAL_SH_SCI_DMA 662 if (to_sci_port(port)->chan_tx && 663 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 664 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 665 to_sci_port(port)->cookie_tx = -EINVAL; 666 } 667 #endif 668 } 669 670 static void sci_start_rx(struct uart_port *port) 671 { 672 unsigned short ctrl; 673 674 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port); 675 676 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 677 ctrl &= ~SCSCR_RDRQE; 678 679 sci_serial_out(port, SCSCR, ctrl); 680 } 681 682 static void sci_stop_rx(struct uart_port *port) 683 { 684 unsigned short ctrl; 685 686 ctrl = sci_serial_in(port, SCSCR); 687 688 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 689 ctrl &= ~SCSCR_RDRQE; 690 691 ctrl &= ~port_rx_irq_mask(port); 692 693 sci_serial_out(port, SCSCR, ctrl); 694 } 695 696 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 697 { 698 if (port->type == PORT_SCI) { 699 /* Just store the mask */ 700 sci_serial_out(port, SCxSR, mask); 701 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 702 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 703 /* Only clear the status bits we want to clear */ 704 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask); 705 } else { 706 /* Store the mask, clear parity/framing errors */ 707 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 708 } 709 } 710 711 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 712 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 713 714 #ifdef CONFIG_CONSOLE_POLL 715 static int sci_poll_get_char(struct uart_port *port) 716 { 717 unsigned short status; 718 int c; 719 720 do { 721 status = sci_serial_in(port, SCxSR); 722 if (status & SCxSR_ERRORS(port)) { 723 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 724 continue; 725 } 726 break; 727 } while (1); 728 729 if (!(status & SCxSR_RDxF(port))) 730 return NO_POLL_CHAR; 731 732 c = sci_serial_in(port, SCxRDR); 733 734 /* Dummy read */ 735 sci_serial_in(port, SCxSR); 736 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 737 738 return c; 739 } 740 #endif 741 742 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 743 { 744 unsigned short status; 745 746 do { 747 status = sci_serial_in(port, SCxSR); 748 } while (!(status & SCxSR_TDxE(port))); 749 750 sci_serial_out(port, SCxTDR, c); 751 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 752 } 753 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 754 CONFIG_SERIAL_SH_SCI_EARLYCON */ 755 756 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 757 { 758 struct sci_port *s = to_sci_port(port); 759 760 /* 761 * Use port-specific handler if provided. 762 */ 763 if (s->cfg->ops && s->cfg->ops->init_pins) { 764 s->cfg->ops->init_pins(port, cflag); 765 return; 766 } 767 768 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 769 u16 data = sci_serial_in(port, SCPDR); 770 u16 ctrl = sci_serial_in(port, SCPCR); 771 772 /* Enable RXD and TXD pin functions */ 773 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 774 if (to_sci_port(port)->has_rtscts) { 775 /* RTS# is output, active low, unless autorts */ 776 if (!(port->mctrl & TIOCM_RTS)) { 777 ctrl |= SCPCR_RTSC; 778 data |= SCPDR_RTSD; 779 } else if (!s->autorts) { 780 ctrl |= SCPCR_RTSC; 781 data &= ~SCPDR_RTSD; 782 } else { 783 /* Enable RTS# pin function */ 784 ctrl &= ~SCPCR_RTSC; 785 } 786 /* Enable CTS# pin function */ 787 ctrl &= ~SCPCR_CTSC; 788 } 789 sci_serial_out(port, SCPDR, data); 790 sci_serial_out(port, SCPCR, ctrl); 791 } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) { 792 u16 status = sci_serial_in(port, SCSPTR); 793 794 /* RTS# is always output; and active low, unless autorts */ 795 status |= SCSPTR_RTSIO; 796 if (!(port->mctrl & TIOCM_RTS)) 797 status |= SCSPTR_RTSDT; 798 else if (!s->autorts) 799 status &= ~SCSPTR_RTSDT; 800 /* CTS# and SCK are inputs */ 801 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 802 sci_serial_out(port, SCSPTR, status); 803 } 804 } 805 806 static int sci_txfill(struct uart_port *port) 807 { 808 struct sci_port *s = to_sci_port(port); 809 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 810 const struct plat_sci_reg *reg; 811 812 reg = sci_getreg(port, SCTFDR); 813 if (reg->size) 814 return sci_serial_in(port, SCTFDR) & fifo_mask; 815 816 reg = sci_getreg(port, SCFDR); 817 if (reg->size) 818 return sci_serial_in(port, SCFDR) >> 8; 819 820 return !(sci_serial_in(port, SCxSR) & SCI_TDRE); 821 } 822 823 static int sci_txroom(struct uart_port *port) 824 { 825 return port->fifosize - sci_txfill(port); 826 } 827 828 static int sci_rxfill(struct uart_port *port) 829 { 830 struct sci_port *s = to_sci_port(port); 831 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 832 const struct plat_sci_reg *reg; 833 834 reg = sci_getreg(port, SCRFDR); 835 if (reg->size) 836 return sci_serial_in(port, SCRFDR) & fifo_mask; 837 838 reg = sci_getreg(port, SCFDR); 839 if (reg->size) 840 return sci_serial_in(port, SCFDR) & fifo_mask; 841 842 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 843 } 844 845 /* ********************************************************************** * 846 * the interrupt related routines * 847 * ********************************************************************** */ 848 849 static void sci_transmit_chars(struct uart_port *port) 850 { 851 struct tty_port *tport = &port->state->port; 852 unsigned int stopped = uart_tx_stopped(port); 853 unsigned short status; 854 unsigned short ctrl; 855 int count; 856 857 status = sci_serial_in(port, SCxSR); 858 if (!(status & SCxSR_TDxE(port))) { 859 ctrl = sci_serial_in(port, SCSCR); 860 if (kfifo_is_empty(&tport->xmit_fifo)) 861 ctrl &= ~SCSCR_TIE; 862 else 863 ctrl |= SCSCR_TIE; 864 sci_serial_out(port, SCSCR, ctrl); 865 return; 866 } 867 868 count = sci_txroom(port); 869 870 do { 871 unsigned char c; 872 873 if (port->x_char) { 874 c = port->x_char; 875 port->x_char = 0; 876 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { 877 if (port->type == PORT_SCI && 878 kfifo_is_empty(&tport->xmit_fifo)) { 879 ctrl = sci_serial_in(port, SCSCR); 880 ctrl &= ~SCSCR_TE; 881 sci_serial_out(port, SCSCR, ctrl); 882 return; 883 } 884 break; 885 } 886 887 sci_serial_out(port, SCxTDR, c); 888 889 port->icount.tx++; 890 } while (--count > 0); 891 892 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 893 894 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 895 uart_write_wakeup(port); 896 if (kfifo_is_empty(&tport->xmit_fifo)) { 897 if (port->type == PORT_SCI) { 898 ctrl = sci_serial_in(port, SCSCR); 899 ctrl &= ~SCSCR_TIE; 900 ctrl |= SCSCR_TEIE; 901 sci_serial_out(port, SCSCR, ctrl); 902 } 903 904 sci_stop_tx(port); 905 } 906 } 907 908 static void sci_receive_chars(struct uart_port *port) 909 { 910 struct tty_port *tport = &port->state->port; 911 int i, count, copied = 0; 912 unsigned short status; 913 unsigned char flag; 914 915 status = sci_serial_in(port, SCxSR); 916 if (!(status & SCxSR_RDxF(port))) 917 return; 918 919 while (1) { 920 /* Don't copy more bytes than there is room for in the buffer */ 921 count = tty_buffer_request_room(tport, sci_rxfill(port)); 922 923 /* If for any reason we can't copy more data, we're done! */ 924 if (count == 0) 925 break; 926 927 if (port->type == PORT_SCI) { 928 char c = sci_serial_in(port, SCxRDR); 929 if (uart_handle_sysrq_char(port, c)) 930 count = 0; 931 else 932 tty_insert_flip_char(tport, c, TTY_NORMAL); 933 } else { 934 for (i = 0; i < count; i++) { 935 char c; 936 937 if (port->type == PORT_SCIF || 938 port->type == PORT_HSCIF) { 939 status = sci_serial_in(port, SCxSR); 940 c = sci_serial_in(port, SCxRDR); 941 } else { 942 c = sci_serial_in(port, SCxRDR); 943 status = sci_serial_in(port, SCxSR); 944 } 945 if (uart_handle_sysrq_char(port, c)) { 946 count--; i--; 947 continue; 948 } 949 950 /* Store data and status */ 951 if (status & SCxSR_FER(port)) { 952 flag = TTY_FRAME; 953 port->icount.frame++; 954 } else if (status & SCxSR_PER(port)) { 955 flag = TTY_PARITY; 956 port->icount.parity++; 957 } else 958 flag = TTY_NORMAL; 959 960 tty_insert_flip_char(tport, c, flag); 961 } 962 } 963 964 sci_serial_in(port, SCxSR); /* dummy read */ 965 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 966 967 copied += count; 968 port->icount.rx += count; 969 } 970 971 if (copied) { 972 /* Tell the rest of the system the news. New characters! */ 973 tty_flip_buffer_push(tport); 974 } else { 975 /* TTY buffers full; read from RX reg to prevent lockup */ 976 sci_serial_in(port, SCxRDR); 977 sci_serial_in(port, SCxSR); /* dummy read */ 978 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 979 } 980 } 981 982 static int sci_handle_errors(struct uart_port *port) 983 { 984 int copied = 0; 985 unsigned short status = sci_serial_in(port, SCxSR); 986 struct tty_port *tport = &port->state->port; 987 struct sci_port *s = to_sci_port(port); 988 989 /* Handle overruns */ 990 if (status & s->params->overrun_mask) { 991 port->icount.overrun++; 992 993 /* overrun error */ 994 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 995 copied++; 996 } 997 998 if (status & SCxSR_FER(port)) { 999 /* frame error */ 1000 port->icount.frame++; 1001 1002 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 1003 copied++; 1004 } 1005 1006 if (status & SCxSR_PER(port)) { 1007 /* parity error */ 1008 port->icount.parity++; 1009 1010 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 1011 copied++; 1012 } 1013 1014 if (copied) 1015 tty_flip_buffer_push(tport); 1016 1017 return copied; 1018 } 1019 1020 static int sci_handle_fifo_overrun(struct uart_port *port) 1021 { 1022 struct tty_port *tport = &port->state->port; 1023 struct sci_port *s = to_sci_port(port); 1024 const struct plat_sci_reg *reg; 1025 int copied = 0; 1026 u16 status; 1027 1028 reg = sci_getreg(port, s->params->overrun_reg); 1029 if (!reg->size) 1030 return 0; 1031 1032 status = sci_serial_in(port, s->params->overrun_reg); 1033 if (status & s->params->overrun_mask) { 1034 status &= ~s->params->overrun_mask; 1035 sci_serial_out(port, s->params->overrun_reg, status); 1036 1037 port->icount.overrun++; 1038 1039 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1040 tty_flip_buffer_push(tport); 1041 copied++; 1042 } 1043 1044 return copied; 1045 } 1046 1047 static int sci_handle_breaks(struct uart_port *port) 1048 { 1049 int copied = 0; 1050 unsigned short status = sci_serial_in(port, SCxSR); 1051 struct tty_port *tport = &port->state->port; 1052 1053 if (uart_handle_break(port)) 1054 return 0; 1055 1056 if (status & SCxSR_BRK(port)) { 1057 port->icount.brk++; 1058 1059 /* Notify of BREAK */ 1060 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1061 copied++; 1062 } 1063 1064 if (copied) 1065 tty_flip_buffer_push(tport); 1066 1067 copied += sci_handle_fifo_overrun(port); 1068 1069 return copied; 1070 } 1071 1072 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1073 { 1074 unsigned int bits; 1075 1076 if (rx_trig >= port->fifosize) 1077 rx_trig = port->fifosize - 1; 1078 if (rx_trig < 1) 1079 rx_trig = 1; 1080 1081 /* HSCIF can be set to an arbitrary level. */ 1082 if (sci_getreg(port, HSRTRGR)->size) { 1083 sci_serial_out(port, HSRTRGR, rx_trig); 1084 return rx_trig; 1085 } 1086 1087 switch (port->type) { 1088 case PORT_SCIF: 1089 if (rx_trig < 4) { 1090 bits = 0; 1091 rx_trig = 1; 1092 } else if (rx_trig < 8) { 1093 bits = SCFCR_RTRG0; 1094 rx_trig = 4; 1095 } else if (rx_trig < 14) { 1096 bits = SCFCR_RTRG1; 1097 rx_trig = 8; 1098 } else { 1099 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1100 rx_trig = 14; 1101 } 1102 break; 1103 case PORT_SCIFA: 1104 case PORT_SCIFB: 1105 if (rx_trig < 16) { 1106 bits = 0; 1107 rx_trig = 1; 1108 } else if (rx_trig < 32) { 1109 bits = SCFCR_RTRG0; 1110 rx_trig = 16; 1111 } else if (rx_trig < 48) { 1112 bits = SCFCR_RTRG1; 1113 rx_trig = 32; 1114 } else { 1115 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1116 rx_trig = 48; 1117 } 1118 break; 1119 default: 1120 WARN(1, "unknown FIFO configuration"); 1121 return 1; 1122 } 1123 1124 sci_serial_out(port, SCFCR, 1125 (sci_serial_in(port, SCFCR) & 1126 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1127 1128 return rx_trig; 1129 } 1130 1131 static int scif_rtrg_enabled(struct uart_port *port) 1132 { 1133 if (sci_getreg(port, HSRTRGR)->size) 1134 return sci_serial_in(port, HSRTRGR) != 0; 1135 else 1136 return (sci_serial_in(port, SCFCR) & 1137 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1138 } 1139 1140 static void rx_fifo_timer_fn(struct timer_list *t) 1141 { 1142 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1143 struct uart_port *port = &s->port; 1144 1145 dev_dbg(port->dev, "Rx timed out\n"); 1146 scif_set_rtrg(port, 1); 1147 } 1148 1149 static ssize_t rx_fifo_trigger_show(struct device *dev, 1150 struct device_attribute *attr, char *buf) 1151 { 1152 struct uart_port *port = dev_get_drvdata(dev); 1153 struct sci_port *sci = to_sci_port(port); 1154 1155 return sprintf(buf, "%d\n", sci->rx_trigger); 1156 } 1157 1158 static ssize_t rx_fifo_trigger_store(struct device *dev, 1159 struct device_attribute *attr, 1160 const char *buf, size_t count) 1161 { 1162 struct uart_port *port = dev_get_drvdata(dev); 1163 struct sci_port *sci = to_sci_port(port); 1164 int ret; 1165 long r; 1166 1167 ret = kstrtol(buf, 0, &r); 1168 if (ret) 1169 return ret; 1170 1171 sci->rx_trigger = scif_set_rtrg(port, r); 1172 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1173 scif_set_rtrg(port, 1); 1174 1175 return count; 1176 } 1177 1178 static DEVICE_ATTR_RW(rx_fifo_trigger); 1179 1180 static ssize_t rx_fifo_timeout_show(struct device *dev, 1181 struct device_attribute *attr, 1182 char *buf) 1183 { 1184 struct uart_port *port = dev_get_drvdata(dev); 1185 struct sci_port *sci = to_sci_port(port); 1186 int v; 1187 1188 if (port->type == PORT_HSCIF) 1189 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1190 else 1191 v = sci->rx_fifo_timeout; 1192 1193 return sprintf(buf, "%d\n", v); 1194 } 1195 1196 static ssize_t rx_fifo_timeout_store(struct device *dev, 1197 struct device_attribute *attr, 1198 const char *buf, 1199 size_t count) 1200 { 1201 struct uart_port *port = dev_get_drvdata(dev); 1202 struct sci_port *sci = to_sci_port(port); 1203 int ret; 1204 long r; 1205 1206 ret = kstrtol(buf, 0, &r); 1207 if (ret) 1208 return ret; 1209 1210 if (port->type == PORT_HSCIF) { 1211 if (r < 0 || r > 3) 1212 return -EINVAL; 1213 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1214 } else { 1215 sci->rx_fifo_timeout = r; 1216 scif_set_rtrg(port, 1); 1217 if (r > 0) 1218 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1219 } 1220 1221 return count; 1222 } 1223 1224 static DEVICE_ATTR_RW(rx_fifo_timeout); 1225 1226 1227 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1228 static void sci_dma_tx_complete(void *arg) 1229 { 1230 struct sci_port *s = arg; 1231 struct uart_port *port = &s->port; 1232 struct tty_port *tport = &port->state->port; 1233 unsigned long flags; 1234 1235 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1236 1237 uart_port_lock_irqsave(port, &flags); 1238 1239 uart_xmit_advance(port, s->tx_dma_len); 1240 1241 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1242 uart_write_wakeup(port); 1243 1244 if (!kfifo_is_empty(&tport->xmit_fifo)) { 1245 s->cookie_tx = 0; 1246 schedule_work(&s->work_tx); 1247 } else { 1248 s->cookie_tx = -EINVAL; 1249 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1250 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1251 u16 ctrl = sci_serial_in(port, SCSCR); 1252 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1253 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1254 /* Switch irq from DMA to SCIF */ 1255 dmaengine_pause(s->chan_tx_saved); 1256 enable_irq(s->irqs[SCIx_TXI_IRQ]); 1257 } 1258 } 1259 } 1260 1261 uart_port_unlock_irqrestore(port, flags); 1262 } 1263 1264 /* Locking: called with port lock held */ 1265 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1266 { 1267 struct uart_port *port = &s->port; 1268 struct tty_port *tport = &port->state->port; 1269 int copied; 1270 1271 copied = tty_insert_flip_string(tport, buf, count); 1272 if (copied < count) 1273 port->icount.buf_overrun++; 1274 1275 port->icount.rx += copied; 1276 1277 return copied; 1278 } 1279 1280 static int sci_dma_rx_find_active(struct sci_port *s) 1281 { 1282 unsigned int i; 1283 1284 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1285 if (s->active_rx == s->cookie_rx[i]) 1286 return i; 1287 1288 return -1; 1289 } 1290 1291 /* Must only be called with uart_port_lock taken */ 1292 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1293 { 1294 unsigned int i; 1295 1296 s->chan_rx = NULL; 1297 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1298 s->cookie_rx[i] = -EINVAL; 1299 s->active_rx = 0; 1300 } 1301 1302 static void sci_dma_rx_release(struct sci_port *s) 1303 { 1304 struct dma_chan *chan = s->chan_rx_saved; 1305 struct uart_port *port = &s->port; 1306 unsigned long flags; 1307 1308 uart_port_lock_irqsave(port, &flags); 1309 s->chan_rx_saved = NULL; 1310 sci_dma_rx_chan_invalidate(s); 1311 uart_port_unlock_irqrestore(port, flags); 1312 1313 dmaengine_terminate_sync(chan); 1314 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1315 sg_dma_address(&s->sg_rx[0])); 1316 dma_release_channel(chan); 1317 } 1318 1319 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1320 { 1321 long sec = usec / 1000000; 1322 long nsec = (usec % 1000000) * 1000; 1323 ktime_t t = ktime_set(sec, nsec); 1324 1325 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1326 } 1327 1328 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1329 { 1330 struct uart_port *port = &s->port; 1331 u16 scr; 1332 1333 /* Direct new serial port interrupts back to CPU */ 1334 scr = sci_serial_in(port, SCSCR); 1335 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1336 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1337 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1338 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1339 scif_set_rtrg(port, s->rx_trigger); 1340 else 1341 scr &= ~SCSCR_RDRQE; 1342 } 1343 sci_serial_out(port, SCSCR, scr | SCSCR_RIE); 1344 } 1345 1346 static void sci_dma_rx_complete(void *arg) 1347 { 1348 struct sci_port *s = arg; 1349 struct dma_chan *chan = s->chan_rx; 1350 struct uart_port *port = &s->port; 1351 struct dma_async_tx_descriptor *desc; 1352 unsigned long flags; 1353 int active, count = 0; 1354 1355 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1356 s->active_rx); 1357 1358 hrtimer_cancel(&s->rx_timer); 1359 1360 uart_port_lock_irqsave(port, &flags); 1361 1362 active = sci_dma_rx_find_active(s); 1363 if (active >= 0) 1364 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1365 1366 if (count) 1367 tty_flip_buffer_push(&port->state->port); 1368 1369 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1370 DMA_DEV_TO_MEM, 1371 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1372 if (!desc) 1373 goto fail; 1374 1375 desc->callback = sci_dma_rx_complete; 1376 desc->callback_param = s; 1377 s->cookie_rx[active] = dmaengine_submit(desc); 1378 if (dma_submit_error(s->cookie_rx[active])) 1379 goto fail; 1380 1381 s->active_rx = s->cookie_rx[!active]; 1382 1383 dma_async_issue_pending(chan); 1384 1385 uart_port_unlock_irqrestore(port, flags); 1386 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1387 __func__, s->cookie_rx[active], active, s->active_rx); 1388 1389 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1390 1391 return; 1392 1393 fail: 1394 /* Switch to PIO */ 1395 dmaengine_terminate_async(chan); 1396 sci_dma_rx_chan_invalidate(s); 1397 sci_dma_rx_reenable_irq(s); 1398 uart_port_unlock_irqrestore(port, flags); 1399 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1400 } 1401 1402 static void sci_dma_tx_release(struct sci_port *s) 1403 { 1404 struct dma_chan *chan = s->chan_tx_saved; 1405 1406 cancel_work_sync(&s->work_tx); 1407 s->chan_tx_saved = s->chan_tx = NULL; 1408 s->cookie_tx = -EINVAL; 1409 dmaengine_terminate_sync(chan); 1410 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1411 DMA_TO_DEVICE); 1412 dma_release_channel(chan); 1413 } 1414 1415 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1416 { 1417 struct dma_chan *chan = s->chan_rx; 1418 struct uart_port *port = &s->port; 1419 unsigned long flags; 1420 int i; 1421 1422 for (i = 0; i < 2; i++) { 1423 struct scatterlist *sg = &s->sg_rx[i]; 1424 struct dma_async_tx_descriptor *desc; 1425 1426 desc = dmaengine_prep_slave_sg(chan, 1427 sg, 1, DMA_DEV_TO_MEM, 1428 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1429 if (!desc) 1430 goto fail; 1431 1432 desc->callback = sci_dma_rx_complete; 1433 desc->callback_param = s; 1434 s->cookie_rx[i] = dmaengine_submit(desc); 1435 if (dma_submit_error(s->cookie_rx[i])) 1436 goto fail; 1437 1438 } 1439 1440 s->active_rx = s->cookie_rx[0]; 1441 1442 dma_async_issue_pending(chan); 1443 return 0; 1444 1445 fail: 1446 /* Switch to PIO */ 1447 if (!port_lock_held) 1448 uart_port_lock_irqsave(port, &flags); 1449 if (i) 1450 dmaengine_terminate_async(chan); 1451 sci_dma_rx_chan_invalidate(s); 1452 sci_start_rx(port); 1453 if (!port_lock_held) 1454 uart_port_unlock_irqrestore(port, flags); 1455 return -EAGAIN; 1456 } 1457 1458 static void sci_dma_tx_work_fn(struct work_struct *work) 1459 { 1460 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1461 struct dma_async_tx_descriptor *desc; 1462 struct dma_chan *chan = s->chan_tx; 1463 struct uart_port *port = &s->port; 1464 struct tty_port *tport = &port->state->port; 1465 unsigned long flags; 1466 unsigned int tail; 1467 dma_addr_t buf; 1468 1469 /* 1470 * DMA is idle now. 1471 * Port xmit buffer is already mapped, and it is one page... Just adjust 1472 * offsets and lengths. Since it is a circular buffer, we have to 1473 * transmit till the end, and then the rest. Take the port lock to get a 1474 * consistent xmit buffer state. 1475 */ 1476 uart_port_lock_irq(port); 1477 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail, 1478 UART_XMIT_SIZE); 1479 buf = s->tx_dma_addr + tail; 1480 if (!s->tx_dma_len) { 1481 /* Transmit buffer has been flushed */ 1482 uart_port_unlock_irq(port); 1483 return; 1484 } 1485 1486 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1487 DMA_MEM_TO_DEV, 1488 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1489 if (!desc) { 1490 uart_port_unlock_irq(port); 1491 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1492 goto switch_to_pio; 1493 } 1494 1495 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1496 DMA_TO_DEVICE); 1497 1498 desc->callback = sci_dma_tx_complete; 1499 desc->callback_param = s; 1500 s->cookie_tx = dmaengine_submit(desc); 1501 if (dma_submit_error(s->cookie_tx)) { 1502 uart_port_unlock_irq(port); 1503 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1504 goto switch_to_pio; 1505 } 1506 1507 uart_port_unlock_irq(port); 1508 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n", 1509 __func__, tport->xmit_buf, tail, s->cookie_tx); 1510 1511 dma_async_issue_pending(chan); 1512 return; 1513 1514 switch_to_pio: 1515 uart_port_lock_irqsave(port, &flags); 1516 s->chan_tx = NULL; 1517 sci_start_tx(port); 1518 uart_port_unlock_irqrestore(port, flags); 1519 return; 1520 } 1521 1522 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1523 { 1524 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1525 struct dma_chan *chan = s->chan_rx; 1526 struct uart_port *port = &s->port; 1527 struct dma_tx_state state; 1528 enum dma_status status; 1529 unsigned long flags; 1530 unsigned int read; 1531 int active, count; 1532 1533 dev_dbg(port->dev, "DMA Rx timed out\n"); 1534 1535 uart_port_lock_irqsave(port, &flags); 1536 1537 active = sci_dma_rx_find_active(s); 1538 if (active < 0) { 1539 uart_port_unlock_irqrestore(port, flags); 1540 return HRTIMER_NORESTART; 1541 } 1542 1543 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1544 if (status == DMA_COMPLETE) { 1545 uart_port_unlock_irqrestore(port, flags); 1546 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1547 s->active_rx, active); 1548 1549 /* Let packet complete handler take care of the packet */ 1550 return HRTIMER_NORESTART; 1551 } 1552 1553 dmaengine_pause(chan); 1554 1555 /* 1556 * sometimes DMA transfer doesn't stop even if it is stopped and 1557 * data keeps on coming until transaction is complete so check 1558 * for DMA_COMPLETE again 1559 * Let packet complete handler take care of the packet 1560 */ 1561 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1562 if (status == DMA_COMPLETE) { 1563 uart_port_unlock_irqrestore(port, flags); 1564 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1565 return HRTIMER_NORESTART; 1566 } 1567 1568 /* Handle incomplete DMA receive */ 1569 dmaengine_terminate_async(s->chan_rx); 1570 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1571 1572 if (read) { 1573 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1574 if (count) 1575 tty_flip_buffer_push(&port->state->port); 1576 } 1577 1578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1579 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1580 sci_dma_rx_submit(s, true); 1581 1582 sci_dma_rx_reenable_irq(s); 1583 1584 uart_port_unlock_irqrestore(port, flags); 1585 1586 return HRTIMER_NORESTART; 1587 } 1588 1589 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1590 enum dma_transfer_direction dir) 1591 { 1592 struct dma_chan *chan; 1593 struct dma_slave_config cfg; 1594 int ret; 1595 1596 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1597 if (IS_ERR(chan)) { 1598 dev_dbg(port->dev, "dma_request_chan failed\n"); 1599 return NULL; 1600 } 1601 1602 memset(&cfg, 0, sizeof(cfg)); 1603 cfg.direction = dir; 1604 cfg.dst_addr = port->mapbase + 1605 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1606 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1607 cfg.src_addr = port->mapbase + 1608 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1609 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1610 1611 ret = dmaengine_slave_config(chan, &cfg); 1612 if (ret) { 1613 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1614 dma_release_channel(chan); 1615 return NULL; 1616 } 1617 1618 return chan; 1619 } 1620 1621 static void sci_request_dma(struct uart_port *port) 1622 { 1623 struct sci_port *s = to_sci_port(port); 1624 struct tty_port *tport = &port->state->port; 1625 struct dma_chan *chan; 1626 1627 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1628 1629 /* 1630 * DMA on console may interfere with Kernel log messages which use 1631 * plain putchar(). So, simply don't use it with a console. 1632 */ 1633 if (uart_console(port)) 1634 return; 1635 1636 if (!port->dev->of_node) 1637 return; 1638 1639 s->cookie_tx = -EINVAL; 1640 1641 /* 1642 * Don't request a dma channel if no channel was specified 1643 * in the device tree. 1644 */ 1645 if (!of_property_present(port->dev->of_node, "dmas")) 1646 return; 1647 1648 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1649 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1650 if (chan) { 1651 /* UART circular tx buffer is an aligned page. */ 1652 s->tx_dma_addr = dma_map_single(chan->device->dev, 1653 tport->xmit_buf, 1654 UART_XMIT_SIZE, 1655 DMA_TO_DEVICE); 1656 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1657 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1658 dma_release_channel(chan); 1659 } else { 1660 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1661 __func__, UART_XMIT_SIZE, 1662 tport->xmit_buf, &s->tx_dma_addr); 1663 1664 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1665 s->chan_tx_saved = s->chan_tx = chan; 1666 } 1667 } 1668 1669 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1670 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1671 if (chan) { 1672 unsigned int i; 1673 dma_addr_t dma; 1674 void *buf; 1675 1676 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1677 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1678 &dma, GFP_KERNEL); 1679 if (!buf) { 1680 dev_warn(port->dev, 1681 "Failed to allocate Rx dma buffer, using PIO\n"); 1682 dma_release_channel(chan); 1683 return; 1684 } 1685 1686 for (i = 0; i < 2; i++) { 1687 struct scatterlist *sg = &s->sg_rx[i]; 1688 1689 sg_init_table(sg, 1); 1690 s->rx_buf[i] = buf; 1691 sg_dma_address(sg) = dma; 1692 sg_dma_len(sg) = s->buf_len_rx; 1693 1694 buf += s->buf_len_rx; 1695 dma += s->buf_len_rx; 1696 } 1697 1698 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1699 s->rx_timer.function = sci_dma_rx_timer_fn; 1700 1701 s->chan_rx_saved = s->chan_rx = chan; 1702 1703 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1704 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1705 sci_dma_rx_submit(s, false); 1706 } 1707 } 1708 1709 static void sci_free_dma(struct uart_port *port) 1710 { 1711 struct sci_port *s = to_sci_port(port); 1712 1713 if (s->chan_tx_saved) 1714 sci_dma_tx_release(s); 1715 if (s->chan_rx_saved) 1716 sci_dma_rx_release(s); 1717 } 1718 1719 static void sci_flush_buffer(struct uart_port *port) 1720 { 1721 struct sci_port *s = to_sci_port(port); 1722 1723 /* 1724 * In uart_flush_buffer(), the xmit circular buffer has just been 1725 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1726 * pending transfers 1727 */ 1728 s->tx_dma_len = 0; 1729 if (s->chan_tx) { 1730 dmaengine_terminate_async(s->chan_tx); 1731 s->cookie_tx = -EINVAL; 1732 } 1733 } 1734 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1735 static inline void sci_request_dma(struct uart_port *port) 1736 { 1737 } 1738 1739 static inline void sci_free_dma(struct uart_port *port) 1740 { 1741 } 1742 1743 #define sci_flush_buffer NULL 1744 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1745 1746 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1747 { 1748 struct uart_port *port = ptr; 1749 struct sci_port *s = to_sci_port(port); 1750 1751 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1752 if (s->chan_rx) { 1753 u16 scr = sci_serial_in(port, SCSCR); 1754 u16 ssr = sci_serial_in(port, SCxSR); 1755 1756 /* Disable future Rx interrupts */ 1757 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1758 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1759 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); 1760 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1761 scif_set_rtrg(port, 1); 1762 scr |= SCSCR_RIE; 1763 } else { 1764 scr |= SCSCR_RDRQE; 1765 } 1766 } else { 1767 if (sci_dma_rx_submit(s, false) < 0) 1768 goto handle_pio; 1769 1770 scr &= ~SCSCR_RIE; 1771 } 1772 sci_serial_out(port, SCSCR, scr); 1773 /* Clear current interrupt */ 1774 sci_serial_out(port, SCxSR, 1775 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1776 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1777 jiffies, s->rx_timeout); 1778 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1779 1780 return IRQ_HANDLED; 1781 } 1782 1783 handle_pio: 1784 #endif 1785 1786 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1787 if (!scif_rtrg_enabled(port)) 1788 scif_set_rtrg(port, s->rx_trigger); 1789 1790 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1791 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1792 } 1793 1794 /* I think sci_receive_chars has to be called irrespective 1795 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1796 * to be disabled? 1797 */ 1798 sci_receive_chars(port); 1799 1800 return IRQ_HANDLED; 1801 } 1802 1803 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1804 { 1805 struct uart_port *port = ptr; 1806 unsigned long flags; 1807 1808 uart_port_lock_irqsave(port, &flags); 1809 sci_transmit_chars(port); 1810 uart_port_unlock_irqrestore(port, flags); 1811 1812 return IRQ_HANDLED; 1813 } 1814 1815 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) 1816 { 1817 struct uart_port *port = ptr; 1818 unsigned long flags; 1819 unsigned short ctrl; 1820 1821 if (port->type != PORT_SCI) 1822 return sci_tx_interrupt(irq, ptr); 1823 1824 uart_port_lock_irqsave(port, &flags); 1825 ctrl = sci_serial_in(port, SCSCR); 1826 ctrl &= ~(SCSCR_TE | SCSCR_TEIE); 1827 sci_serial_out(port, SCSCR, ctrl); 1828 uart_port_unlock_irqrestore(port, flags); 1829 1830 return IRQ_HANDLED; 1831 } 1832 1833 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1834 { 1835 struct uart_port *port = ptr; 1836 1837 /* Handle BREAKs */ 1838 sci_handle_breaks(port); 1839 1840 /* drop invalid character received before break was detected */ 1841 sci_serial_in(port, SCxRDR); 1842 1843 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1844 1845 return IRQ_HANDLED; 1846 } 1847 1848 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1849 { 1850 struct uart_port *port = ptr; 1851 struct sci_port *s = to_sci_port(port); 1852 1853 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1854 /* Break and Error interrupts are muxed */ 1855 unsigned short ssr_status = sci_serial_in(port, SCxSR); 1856 1857 /* Break Interrupt */ 1858 if (ssr_status & SCxSR_BRK(port)) 1859 sci_br_interrupt(irq, ptr); 1860 1861 /* Break only? */ 1862 if (!(ssr_status & SCxSR_ERRORS(port))) 1863 return IRQ_HANDLED; 1864 } 1865 1866 /* Handle errors */ 1867 if (port->type == PORT_SCI) { 1868 if (sci_handle_errors(port)) { 1869 /* discard character in rx buffer */ 1870 sci_serial_in(port, SCxSR); 1871 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1872 } 1873 } else { 1874 sci_handle_fifo_overrun(port); 1875 if (!s->chan_rx) 1876 sci_receive_chars(port); 1877 } 1878 1879 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1880 1881 /* Kick the transmission */ 1882 if (!s->chan_tx) 1883 sci_tx_interrupt(irq, ptr); 1884 1885 return IRQ_HANDLED; 1886 } 1887 1888 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1889 { 1890 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1891 struct uart_port *port = ptr; 1892 struct sci_port *s = to_sci_port(port); 1893 irqreturn_t ret = IRQ_NONE; 1894 1895 ssr_status = sci_serial_in(port, SCxSR); 1896 scr_status = sci_serial_in(port, SCSCR); 1897 if (s->params->overrun_reg == SCxSR) 1898 orer_status = ssr_status; 1899 else if (sci_getreg(port, s->params->overrun_reg)->size) 1900 orer_status = sci_serial_in(port, s->params->overrun_reg); 1901 1902 err_enabled = scr_status & port_rx_irq_mask(port); 1903 1904 /* Tx Interrupt */ 1905 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1906 !s->chan_tx) 1907 ret = sci_tx_interrupt(irq, ptr); 1908 1909 /* 1910 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1911 * DR flags 1912 */ 1913 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1914 (scr_status & SCSCR_RIE)) 1915 ret = sci_rx_interrupt(irq, ptr); 1916 1917 /* Error Interrupt */ 1918 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1919 ret = sci_er_interrupt(irq, ptr); 1920 1921 /* Break Interrupt */ 1922 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 1923 (ssr_status & SCxSR_BRK(port)) && err_enabled) 1924 ret = sci_br_interrupt(irq, ptr); 1925 1926 /* Overrun Interrupt */ 1927 if (orer_status & s->params->overrun_mask) { 1928 sci_handle_fifo_overrun(port); 1929 ret = IRQ_HANDLED; 1930 } 1931 1932 return ret; 1933 } 1934 1935 static const struct sci_irq_desc { 1936 const char *desc; 1937 irq_handler_t handler; 1938 } sci_irq_desc[] = { 1939 /* 1940 * Split out handlers, the default case. 1941 */ 1942 [SCIx_ERI_IRQ] = { 1943 .desc = "rx err", 1944 .handler = sci_er_interrupt, 1945 }, 1946 1947 [SCIx_RXI_IRQ] = { 1948 .desc = "rx full", 1949 .handler = sci_rx_interrupt, 1950 }, 1951 1952 [SCIx_TXI_IRQ] = { 1953 .desc = "tx empty", 1954 .handler = sci_tx_interrupt, 1955 }, 1956 1957 [SCIx_BRI_IRQ] = { 1958 .desc = "break", 1959 .handler = sci_br_interrupt, 1960 }, 1961 1962 [SCIx_DRI_IRQ] = { 1963 .desc = "rx ready", 1964 .handler = sci_rx_interrupt, 1965 }, 1966 1967 [SCIx_TEI_IRQ] = { 1968 .desc = "tx end", 1969 .handler = sci_tx_end_interrupt, 1970 }, 1971 1972 /* 1973 * Special muxed handler. 1974 */ 1975 [SCIx_MUX_IRQ] = { 1976 .desc = "mux", 1977 .handler = sci_mpxed_interrupt, 1978 }, 1979 }; 1980 1981 static int sci_request_irq(struct sci_port *port) 1982 { 1983 struct uart_port *up = &port->port; 1984 int i, j, w, ret = 0; 1985 1986 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1987 const struct sci_irq_desc *desc; 1988 int irq; 1989 1990 /* Check if already registered (muxed) */ 1991 for (w = 0; w < i; w++) 1992 if (port->irqs[w] == port->irqs[i]) 1993 w = i + 1; 1994 if (w > i) 1995 continue; 1996 1997 if (SCIx_IRQ_IS_MUXED(port)) { 1998 i = SCIx_MUX_IRQ; 1999 irq = up->irq; 2000 } else { 2001 irq = port->irqs[i]; 2002 2003 /* 2004 * Certain port types won't support all of the 2005 * available interrupt sources. 2006 */ 2007 if (unlikely(irq < 0)) 2008 continue; 2009 } 2010 2011 desc = sci_irq_desc + i; 2012 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 2013 dev_name(up->dev), desc->desc); 2014 if (!port->irqstr[j]) { 2015 ret = -ENOMEM; 2016 goto out_nomem; 2017 } 2018 2019 ret = request_irq(irq, desc->handler, up->irqflags, 2020 port->irqstr[j], port); 2021 if (unlikely(ret)) { 2022 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 2023 goto out_noirq; 2024 } 2025 } 2026 2027 return 0; 2028 2029 out_noirq: 2030 while (--i >= 0) 2031 free_irq(port->irqs[i], port); 2032 2033 out_nomem: 2034 while (--j >= 0) 2035 kfree(port->irqstr[j]); 2036 2037 return ret; 2038 } 2039 2040 static void sci_free_irq(struct sci_port *port) 2041 { 2042 int i, j; 2043 2044 /* 2045 * Intentionally in reverse order so we iterate over the muxed 2046 * IRQ first. 2047 */ 2048 for (i = 0; i < SCIx_NR_IRQS; i++) { 2049 int irq = port->irqs[i]; 2050 2051 /* 2052 * Certain port types won't support all of the available 2053 * interrupt sources. 2054 */ 2055 if (unlikely(irq < 0)) 2056 continue; 2057 2058 /* Check if already freed (irq was muxed) */ 2059 for (j = 0; j < i; j++) 2060 if (port->irqs[j] == irq) 2061 j = i + 1; 2062 if (j > i) 2063 continue; 2064 2065 free_irq(port->irqs[i], port); 2066 kfree(port->irqstr[i]); 2067 2068 if (SCIx_IRQ_IS_MUXED(port)) { 2069 /* If there's only one IRQ, we're done. */ 2070 return; 2071 } 2072 } 2073 } 2074 2075 static unsigned int sci_tx_empty(struct uart_port *port) 2076 { 2077 unsigned short status = sci_serial_in(port, SCxSR); 2078 unsigned short in_tx_fifo = sci_txfill(port); 2079 2080 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 2081 } 2082 2083 static void sci_set_rts(struct uart_port *port, bool state) 2084 { 2085 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2086 u16 data = sci_serial_in(port, SCPDR); 2087 2088 /* Active low */ 2089 if (state) 2090 data &= ~SCPDR_RTSD; 2091 else 2092 data |= SCPDR_RTSD; 2093 sci_serial_out(port, SCPDR, data); 2094 2095 /* RTS# is output */ 2096 sci_serial_out(port, SCPCR, 2097 sci_serial_in(port, SCPCR) | SCPCR_RTSC); 2098 } else if (sci_getreg(port, SCSPTR)->size) { 2099 u16 ctrl = sci_serial_in(port, SCSPTR); 2100 2101 /* Active low */ 2102 if (state) 2103 ctrl &= ~SCSPTR_RTSDT; 2104 else 2105 ctrl |= SCSPTR_RTSDT; 2106 sci_serial_out(port, SCSPTR, ctrl); 2107 } 2108 } 2109 2110 static bool sci_get_cts(struct uart_port *port) 2111 { 2112 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2113 /* Active low */ 2114 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD); 2115 } else if (sci_getreg(port, SCSPTR)->size) { 2116 /* Active low */ 2117 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT); 2118 } 2119 2120 return true; 2121 } 2122 2123 /* 2124 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2125 * CTS/RTS is supported in hardware by at least one port and controlled 2126 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2127 * handled via the ->init_pins() op, which is a bit of a one-way street, 2128 * lacking any ability to defer pin control -- this will later be 2129 * converted over to the GPIO framework). 2130 * 2131 * Other modes (such as loopback) are supported generically on certain 2132 * port types, but not others. For these it's sufficient to test for the 2133 * existence of the support register and simply ignore the port type. 2134 */ 2135 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2136 { 2137 struct sci_port *s = to_sci_port(port); 2138 2139 if (mctrl & TIOCM_LOOP) { 2140 const struct plat_sci_reg *reg; 2141 2142 /* 2143 * Standard loopback mode for SCFCR ports. 2144 */ 2145 reg = sci_getreg(port, SCFCR); 2146 if (reg->size) 2147 sci_serial_out(port, SCFCR, 2148 sci_serial_in(port, SCFCR) | SCFCR_LOOP); 2149 } 2150 2151 mctrl_gpio_set(s->gpios, mctrl); 2152 2153 if (!s->has_rtscts) 2154 return; 2155 2156 if (!(mctrl & TIOCM_RTS)) { 2157 /* Disable Auto RTS */ 2158 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2159 sci_serial_out(port, SCFCR, 2160 sci_serial_in(port, SCFCR) & ~SCFCR_MCE); 2161 2162 /* Clear RTS */ 2163 sci_set_rts(port, 0); 2164 } else if (s->autorts) { 2165 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2166 /* Enable RTS# pin function */ 2167 sci_serial_out(port, SCPCR, 2168 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC); 2169 } 2170 2171 /* Enable Auto RTS */ 2172 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2173 sci_serial_out(port, SCFCR, 2174 sci_serial_in(port, SCFCR) | SCFCR_MCE); 2175 } else { 2176 /* Set RTS */ 2177 sci_set_rts(port, 1); 2178 } 2179 } 2180 2181 static unsigned int sci_get_mctrl(struct uart_port *port) 2182 { 2183 struct sci_port *s = to_sci_port(port); 2184 struct mctrl_gpios *gpios = s->gpios; 2185 unsigned int mctrl = 0; 2186 2187 mctrl_gpio_get(gpios, &mctrl); 2188 2189 /* 2190 * CTS/RTS is handled in hardware when supported, while nothing 2191 * else is wired up. 2192 */ 2193 if (s->autorts) { 2194 if (sci_get_cts(port)) 2195 mctrl |= TIOCM_CTS; 2196 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2197 mctrl |= TIOCM_CTS; 2198 } 2199 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2200 mctrl |= TIOCM_DSR; 2201 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2202 mctrl |= TIOCM_CAR; 2203 2204 return mctrl; 2205 } 2206 2207 static void sci_enable_ms(struct uart_port *port) 2208 { 2209 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2210 } 2211 2212 static void sci_break_ctl(struct uart_port *port, int break_state) 2213 { 2214 unsigned short scscr, scsptr; 2215 unsigned long flags; 2216 2217 /* check whether the port has SCSPTR */ 2218 if (!sci_getreg(port, SCSPTR)->size) { 2219 /* 2220 * Not supported by hardware. Most parts couple break and rx 2221 * interrupts together, with break detection always enabled. 2222 */ 2223 return; 2224 } 2225 2226 uart_port_lock_irqsave(port, &flags); 2227 scsptr = sci_serial_in(port, SCSPTR); 2228 scscr = sci_serial_in(port, SCSCR); 2229 2230 if (break_state == -1) { 2231 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2232 scscr &= ~SCSCR_TE; 2233 } else { 2234 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2235 scscr |= SCSCR_TE; 2236 } 2237 2238 sci_serial_out(port, SCSPTR, scsptr); 2239 sci_serial_out(port, SCSCR, scscr); 2240 uart_port_unlock_irqrestore(port, flags); 2241 } 2242 2243 static int sci_startup(struct uart_port *port) 2244 { 2245 struct sci_port *s = to_sci_port(port); 2246 int ret; 2247 2248 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2249 2250 sci_request_dma(port); 2251 2252 ret = sci_request_irq(s); 2253 if (unlikely(ret < 0)) { 2254 sci_free_dma(port); 2255 return ret; 2256 } 2257 2258 return 0; 2259 } 2260 2261 static void sci_shutdown(struct uart_port *port) 2262 { 2263 struct sci_port *s = to_sci_port(port); 2264 unsigned long flags; 2265 u16 scr; 2266 2267 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2268 2269 s->autorts = false; 2270 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2271 2272 uart_port_lock_irqsave(port, &flags); 2273 sci_stop_rx(port); 2274 sci_stop_tx(port); 2275 /* 2276 * Stop RX and TX, disable related interrupts, keep clock source 2277 * and HSCIF TOT bits 2278 */ 2279 scr = sci_serial_in(port, SCSCR); 2280 sci_serial_out(port, SCSCR, 2281 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2282 uart_port_unlock_irqrestore(port, flags); 2283 2284 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2285 if (s->chan_rx_saved) { 2286 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2287 port->line); 2288 hrtimer_cancel(&s->rx_timer); 2289 } 2290 #endif 2291 2292 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2293 del_timer_sync(&s->rx_fifo_timer); 2294 sci_free_irq(s); 2295 sci_free_dma(port); 2296 } 2297 2298 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2299 unsigned int *srr) 2300 { 2301 unsigned long freq = s->clk_rates[SCI_SCK]; 2302 int err, min_err = INT_MAX; 2303 unsigned int sr; 2304 2305 if (s->port.type != PORT_HSCIF) 2306 freq *= 2; 2307 2308 for_each_sr(sr, s) { 2309 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2310 if (abs(err) >= abs(min_err)) 2311 continue; 2312 2313 min_err = err; 2314 *srr = sr - 1; 2315 2316 if (!err) 2317 break; 2318 } 2319 2320 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2321 *srr + 1); 2322 return min_err; 2323 } 2324 2325 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2326 unsigned long freq, unsigned int *dlr, 2327 unsigned int *srr) 2328 { 2329 int err, min_err = INT_MAX; 2330 unsigned int sr, dl; 2331 2332 if (s->port.type != PORT_HSCIF) 2333 freq *= 2; 2334 2335 for_each_sr(sr, s) { 2336 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2337 dl = clamp(dl, 1U, 65535U); 2338 2339 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2340 if (abs(err) >= abs(min_err)) 2341 continue; 2342 2343 min_err = err; 2344 *dlr = dl; 2345 *srr = sr - 1; 2346 2347 if (!err) 2348 break; 2349 } 2350 2351 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2352 min_err, *dlr, *srr + 1); 2353 return min_err; 2354 } 2355 2356 /* calculate sample rate, BRR, and clock select */ 2357 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2358 unsigned int *brr, unsigned int *srr, 2359 unsigned int *cks) 2360 { 2361 unsigned long freq = s->clk_rates[SCI_FCK]; 2362 unsigned int sr, br, prediv, scrate, c; 2363 int err, min_err = INT_MAX; 2364 2365 if (s->port.type != PORT_HSCIF) 2366 freq *= 2; 2367 2368 /* 2369 * Find the combination of sample rate and clock select with the 2370 * smallest deviation from the desired baud rate. 2371 * Prefer high sample rates to maximise the receive margin. 2372 * 2373 * M: Receive margin (%) 2374 * N: Ratio of bit rate to clock (N = sampling rate) 2375 * D: Clock duty (D = 0 to 1.0) 2376 * L: Frame length (L = 9 to 12) 2377 * F: Absolute value of clock frequency deviation 2378 * 2379 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2380 * (|D - 0.5| / N * (1 + F))| 2381 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2382 */ 2383 for_each_sr(sr, s) { 2384 for (c = 0; c <= 3; c++) { 2385 /* integerized formulas from HSCIF documentation */ 2386 prediv = sr << (2 * c + 1); 2387 2388 /* 2389 * We need to calculate: 2390 * 2391 * br = freq / (prediv * bps) clamped to [1..256] 2392 * err = freq / (br * prediv) - bps 2393 * 2394 * Watch out for overflow when calculating the desired 2395 * sampling clock rate! 2396 */ 2397 if (bps > UINT_MAX / prediv) 2398 break; 2399 2400 scrate = prediv * bps; 2401 br = DIV_ROUND_CLOSEST(freq, scrate); 2402 br = clamp(br, 1U, 256U); 2403 2404 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2405 if (abs(err) >= abs(min_err)) 2406 continue; 2407 2408 min_err = err; 2409 *brr = br - 1; 2410 *srr = sr - 1; 2411 *cks = c; 2412 2413 if (!err) 2414 goto found; 2415 } 2416 } 2417 2418 found: 2419 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2420 min_err, *brr, *srr + 1, *cks); 2421 return min_err; 2422 } 2423 2424 static void sci_reset(struct uart_port *port) 2425 { 2426 const struct plat_sci_reg *reg; 2427 unsigned int status; 2428 struct sci_port *s = to_sci_port(port); 2429 2430 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2431 2432 reg = sci_getreg(port, SCFCR); 2433 if (reg->size) 2434 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2435 2436 sci_clear_SCxSR(port, 2437 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2438 SCxSR_BREAK_CLEAR(port)); 2439 if (sci_getreg(port, SCLSR)->size) { 2440 status = sci_serial_in(port, SCLSR); 2441 status &= ~(SCLSR_TO | SCLSR_ORER); 2442 sci_serial_out(port, SCLSR, status); 2443 } 2444 2445 if (s->rx_trigger > 1) { 2446 if (s->rx_fifo_timeout) { 2447 scif_set_rtrg(port, 1); 2448 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2449 } else { 2450 if (port->type == PORT_SCIFA || 2451 port->type == PORT_SCIFB) 2452 scif_set_rtrg(port, 1); 2453 else 2454 scif_set_rtrg(port, s->rx_trigger); 2455 } 2456 } 2457 } 2458 2459 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2460 const struct ktermios *old) 2461 { 2462 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2463 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2464 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2465 struct sci_port *s = to_sci_port(port); 2466 const struct plat_sci_reg *reg; 2467 int min_err = INT_MAX, err; 2468 unsigned long max_freq = 0; 2469 int best_clk = -1; 2470 unsigned long flags; 2471 2472 if ((termios->c_cflag & CSIZE) == CS7) { 2473 smr_val |= SCSMR_CHR; 2474 } else { 2475 termios->c_cflag &= ~CSIZE; 2476 termios->c_cflag |= CS8; 2477 } 2478 if (termios->c_cflag & PARENB) 2479 smr_val |= SCSMR_PE; 2480 if (termios->c_cflag & PARODD) 2481 smr_val |= SCSMR_PE | SCSMR_ODD; 2482 if (termios->c_cflag & CSTOPB) 2483 smr_val |= SCSMR_STOP; 2484 2485 /* 2486 * earlyprintk comes here early on with port->uartclk set to zero. 2487 * the clock framework is not up and running at this point so here 2488 * we assume that 115200 is the maximum baud rate. please note that 2489 * the baud rate is not programmed during earlyprintk - it is assumed 2490 * that the previous boot loader has enabled required clocks and 2491 * setup the baud rate generator hardware for us already. 2492 */ 2493 if (!port->uartclk) { 2494 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2495 goto done; 2496 } 2497 2498 for (i = 0; i < SCI_NUM_CLKS; i++) 2499 max_freq = max(max_freq, s->clk_rates[i]); 2500 2501 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2502 if (!baud) 2503 goto done; 2504 2505 /* 2506 * There can be multiple sources for the sampling clock. Find the one 2507 * that gives us the smallest deviation from the desired baud rate. 2508 */ 2509 2510 /* Optional Undivided External Clock */ 2511 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2512 port->type != PORT_SCIFB) { 2513 err = sci_sck_calc(s, baud, &srr1); 2514 if (abs(err) < abs(min_err)) { 2515 best_clk = SCI_SCK; 2516 scr_val = SCSCR_CKE1; 2517 sccks = SCCKS_CKS; 2518 min_err = err; 2519 srr = srr1; 2520 if (!err) 2521 goto done; 2522 } 2523 } 2524 2525 /* Optional BRG Frequency Divided External Clock */ 2526 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2527 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2528 &srr1); 2529 if (abs(err) < abs(min_err)) { 2530 best_clk = SCI_SCIF_CLK; 2531 scr_val = SCSCR_CKE1; 2532 sccks = 0; 2533 min_err = err; 2534 dl = dl1; 2535 srr = srr1; 2536 if (!err) 2537 goto done; 2538 } 2539 } 2540 2541 /* Optional BRG Frequency Divided Internal Clock */ 2542 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2543 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2544 &srr1); 2545 if (abs(err) < abs(min_err)) { 2546 best_clk = SCI_BRG_INT; 2547 scr_val = SCSCR_CKE1; 2548 sccks = SCCKS_XIN; 2549 min_err = err; 2550 dl = dl1; 2551 srr = srr1; 2552 if (!min_err) 2553 goto done; 2554 } 2555 } 2556 2557 /* Divided Functional Clock using standard Bit Rate Register */ 2558 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2559 if (abs(err) < abs(min_err)) { 2560 best_clk = SCI_FCK; 2561 scr_val = 0; 2562 min_err = err; 2563 brr = brr1; 2564 srr = srr1; 2565 cks = cks1; 2566 } 2567 2568 done: 2569 if (best_clk >= 0) 2570 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2571 s->clks[best_clk], baud, min_err); 2572 2573 sci_port_enable(s); 2574 2575 /* 2576 * Program the optional External Baud Rate Generator (BRG) first. 2577 * It controls the mux to select (H)SCK or frequency divided clock. 2578 */ 2579 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2580 sci_serial_out(port, SCDL, dl); 2581 sci_serial_out(port, SCCKS, sccks); 2582 } 2583 2584 uart_port_lock_irqsave(port, &flags); 2585 2586 sci_reset(port); 2587 2588 uart_update_timeout(port, termios->c_cflag, baud); 2589 2590 /* byte size and parity */ 2591 bits = tty_get_frame_size(termios->c_cflag); 2592 2593 if (sci_getreg(port, SEMR)->size) 2594 sci_serial_out(port, SEMR, 0); 2595 2596 if (best_clk >= 0) { 2597 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2598 switch (srr + 1) { 2599 case 5: smr_val |= SCSMR_SRC_5; break; 2600 case 7: smr_val |= SCSMR_SRC_7; break; 2601 case 11: smr_val |= SCSMR_SRC_11; break; 2602 case 13: smr_val |= SCSMR_SRC_13; break; 2603 case 16: smr_val |= SCSMR_SRC_16; break; 2604 case 17: smr_val |= SCSMR_SRC_17; break; 2605 case 19: smr_val |= SCSMR_SRC_19; break; 2606 case 27: smr_val |= SCSMR_SRC_27; break; 2607 } 2608 smr_val |= cks; 2609 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2610 sci_serial_out(port, SCSMR, smr_val); 2611 sci_serial_out(port, SCBRR, brr); 2612 if (sci_getreg(port, HSSRR)->size) { 2613 unsigned int hssrr = srr | HSCIF_SRE; 2614 /* Calculate deviation from intended rate at the 2615 * center of the last stop bit in sampling clocks. 2616 */ 2617 int last_stop = bits * 2 - 1; 2618 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2619 (int)(srr + 1), 2620 2 * (int)baud); 2621 2622 if (abs(deviation) >= 2) { 2623 /* At least two sampling clocks off at the 2624 * last stop bit; we can increase the error 2625 * margin by shifting the sampling point. 2626 */ 2627 int shift = clamp(deviation / 2, -8, 7); 2628 2629 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2630 HSCIF_SRHP_MASK; 2631 hssrr |= HSCIF_SRDE; 2632 } 2633 sci_serial_out(port, HSSRR, hssrr); 2634 } 2635 2636 /* Wait one bit interval */ 2637 udelay((1000000 + (baud - 1)) / baud); 2638 } else { 2639 /* Don't touch the bit rate configuration */ 2640 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2641 smr_val |= sci_serial_in(port, SCSMR) & 2642 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2643 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2644 sci_serial_out(port, SCSMR, smr_val); 2645 } 2646 2647 sci_init_pins(port, termios->c_cflag); 2648 2649 port->status &= ~UPSTAT_AUTOCTS; 2650 s->autorts = false; 2651 reg = sci_getreg(port, SCFCR); 2652 if (reg->size) { 2653 unsigned short ctrl = sci_serial_in(port, SCFCR); 2654 2655 if ((port->flags & UPF_HARD_FLOW) && 2656 (termios->c_cflag & CRTSCTS)) { 2657 /* There is no CTS interrupt to restart the hardware */ 2658 port->status |= UPSTAT_AUTOCTS; 2659 /* MCE is enabled when RTS is raised */ 2660 s->autorts = true; 2661 } 2662 2663 /* 2664 * As we've done a sci_reset() above, ensure we don't 2665 * interfere with the FIFOs while toggling MCE. As the 2666 * reset values could still be set, simply mask them out. 2667 */ 2668 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2669 2670 sci_serial_out(port, SCFCR, ctrl); 2671 } 2672 if (port->flags & UPF_HARD_FLOW) { 2673 /* Refresh (Auto) RTS */ 2674 sci_set_mctrl(port, port->mctrl); 2675 } 2676 2677 /* 2678 * For SCI, TE (transmit enable) must be set after setting TIE 2679 * (transmit interrupt enable) or in the same instruction to 2680 * start the transmitting process. So skip setting TE here for SCI. 2681 */ 2682 if (port->type != PORT_SCI) 2683 scr_val |= SCSCR_TE; 2684 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2685 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2686 if ((srr + 1 == 5) && 2687 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2688 /* 2689 * In asynchronous mode, when the sampling rate is 1/5, first 2690 * received data may become invalid on some SCIFA and SCIFB. 2691 * To avoid this problem wait more than 1 serial data time (1 2692 * bit time x serial data number) after setting SCSCR.RE = 1. 2693 */ 2694 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2695 } 2696 2697 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2698 s->rx_frame = (10000 * bits) / (baud / 100); 2699 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2700 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2701 #endif 2702 2703 if ((termios->c_cflag & CREAD) != 0) 2704 sci_start_rx(port); 2705 2706 uart_port_unlock_irqrestore(port, flags); 2707 2708 sci_port_disable(s); 2709 2710 if (UART_ENABLE_MS(port, termios->c_cflag)) 2711 sci_enable_ms(port); 2712 } 2713 2714 static void sci_pm(struct uart_port *port, unsigned int state, 2715 unsigned int oldstate) 2716 { 2717 struct sci_port *sci_port = to_sci_port(port); 2718 2719 switch (state) { 2720 case UART_PM_STATE_OFF: 2721 sci_port_disable(sci_port); 2722 break; 2723 default: 2724 sci_port_enable(sci_port); 2725 break; 2726 } 2727 } 2728 2729 static const char *sci_type(struct uart_port *port) 2730 { 2731 switch (port->type) { 2732 case PORT_IRDA: 2733 return "irda"; 2734 case PORT_SCI: 2735 return "sci"; 2736 case PORT_SCIF: 2737 return "scif"; 2738 case PORT_SCIFA: 2739 return "scifa"; 2740 case PORT_SCIFB: 2741 return "scifb"; 2742 case PORT_HSCIF: 2743 return "hscif"; 2744 } 2745 2746 return NULL; 2747 } 2748 2749 static int sci_remap_port(struct uart_port *port) 2750 { 2751 struct sci_port *sport = to_sci_port(port); 2752 2753 /* 2754 * Nothing to do if there's already an established membase. 2755 */ 2756 if (port->membase) 2757 return 0; 2758 2759 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2760 port->membase = ioremap(port->mapbase, sport->reg_size); 2761 if (unlikely(!port->membase)) { 2762 dev_err(port->dev, "can't remap port#%d\n", port->line); 2763 return -ENXIO; 2764 } 2765 } else { 2766 /* 2767 * For the simple (and majority of) cases where we don't 2768 * need to do any remapping, just cast the cookie 2769 * directly. 2770 */ 2771 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2772 } 2773 2774 return 0; 2775 } 2776 2777 static void sci_release_port(struct uart_port *port) 2778 { 2779 struct sci_port *sport = to_sci_port(port); 2780 2781 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2782 iounmap(port->membase); 2783 port->membase = NULL; 2784 } 2785 2786 release_mem_region(port->mapbase, sport->reg_size); 2787 } 2788 2789 static int sci_request_port(struct uart_port *port) 2790 { 2791 struct resource *res; 2792 struct sci_port *sport = to_sci_port(port); 2793 int ret; 2794 2795 res = request_mem_region(port->mapbase, sport->reg_size, 2796 dev_name(port->dev)); 2797 if (unlikely(res == NULL)) { 2798 dev_err(port->dev, "request_mem_region failed."); 2799 return -EBUSY; 2800 } 2801 2802 ret = sci_remap_port(port); 2803 if (unlikely(ret != 0)) { 2804 release_resource(res); 2805 return ret; 2806 } 2807 2808 return 0; 2809 } 2810 2811 static void sci_config_port(struct uart_port *port, int flags) 2812 { 2813 if (flags & UART_CONFIG_TYPE) { 2814 struct sci_port *sport = to_sci_port(port); 2815 2816 port->type = sport->cfg->type; 2817 sci_request_port(port); 2818 } 2819 } 2820 2821 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2822 { 2823 if (ser->baud_base < 2400) 2824 /* No paper tape reader for Mitch.. */ 2825 return -EINVAL; 2826 2827 return 0; 2828 } 2829 2830 static const struct uart_ops sci_uart_ops = { 2831 .tx_empty = sci_tx_empty, 2832 .set_mctrl = sci_set_mctrl, 2833 .get_mctrl = sci_get_mctrl, 2834 .start_tx = sci_start_tx, 2835 .stop_tx = sci_stop_tx, 2836 .stop_rx = sci_stop_rx, 2837 .enable_ms = sci_enable_ms, 2838 .break_ctl = sci_break_ctl, 2839 .startup = sci_startup, 2840 .shutdown = sci_shutdown, 2841 .flush_buffer = sci_flush_buffer, 2842 .set_termios = sci_set_termios, 2843 .pm = sci_pm, 2844 .type = sci_type, 2845 .release_port = sci_release_port, 2846 .request_port = sci_request_port, 2847 .config_port = sci_config_port, 2848 .verify_port = sci_verify_port, 2849 #ifdef CONFIG_CONSOLE_POLL 2850 .poll_get_char = sci_poll_get_char, 2851 .poll_put_char = sci_poll_put_char, 2852 #endif 2853 }; 2854 2855 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2856 { 2857 const char *clk_names[] = { 2858 [SCI_FCK] = "fck", 2859 [SCI_SCK] = "sck", 2860 [SCI_BRG_INT] = "brg_int", 2861 [SCI_SCIF_CLK] = "scif_clk", 2862 }; 2863 struct clk *clk; 2864 unsigned int i; 2865 2866 if (sci_port->cfg->type == PORT_HSCIF) 2867 clk_names[SCI_SCK] = "hsck"; 2868 2869 for (i = 0; i < SCI_NUM_CLKS; i++) { 2870 clk = devm_clk_get_optional(dev, clk_names[i]); 2871 if (IS_ERR(clk)) 2872 return PTR_ERR(clk); 2873 2874 if (!clk && i == SCI_FCK) { 2875 /* 2876 * Not all SH platforms declare a clock lookup entry 2877 * for SCI devices, in which case we need to get the 2878 * global "peripheral_clk" clock. 2879 */ 2880 clk = devm_clk_get(dev, "peripheral_clk"); 2881 if (IS_ERR(clk)) 2882 return dev_err_probe(dev, PTR_ERR(clk), 2883 "failed to get %s\n", 2884 clk_names[i]); 2885 } 2886 2887 if (!clk) 2888 dev_dbg(dev, "failed to get %s\n", clk_names[i]); 2889 else 2890 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2891 clk, clk_get_rate(clk)); 2892 sci_port->clks[i] = clk; 2893 } 2894 return 0; 2895 } 2896 2897 static const struct sci_port_params * 2898 sci_probe_regmap(const struct plat_sci_port *cfg) 2899 { 2900 unsigned int regtype; 2901 2902 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2903 return &sci_port_params[cfg->regtype]; 2904 2905 switch (cfg->type) { 2906 case PORT_SCI: 2907 regtype = SCIx_SCI_REGTYPE; 2908 break; 2909 case PORT_IRDA: 2910 regtype = SCIx_IRDA_REGTYPE; 2911 break; 2912 case PORT_SCIFA: 2913 regtype = SCIx_SCIFA_REGTYPE; 2914 break; 2915 case PORT_SCIFB: 2916 regtype = SCIx_SCIFB_REGTYPE; 2917 break; 2918 case PORT_SCIF: 2919 /* 2920 * The SH-4 is a bit of a misnomer here, although that's 2921 * where this particular port layout originated. This 2922 * configuration (or some slight variation thereof) 2923 * remains the dominant model for all SCIFs. 2924 */ 2925 regtype = SCIx_SH4_SCIF_REGTYPE; 2926 break; 2927 case PORT_HSCIF: 2928 regtype = SCIx_HSCIF_REGTYPE; 2929 break; 2930 default: 2931 pr_err("Can't probe register map for given port\n"); 2932 return NULL; 2933 } 2934 2935 return &sci_port_params[regtype]; 2936 } 2937 2938 static int sci_init_single(struct platform_device *dev, 2939 struct sci_port *sci_port, unsigned int index, 2940 const struct plat_sci_port *p, bool early) 2941 { 2942 struct uart_port *port = &sci_port->port; 2943 const struct resource *res; 2944 unsigned int i; 2945 int ret; 2946 2947 sci_port->cfg = p; 2948 2949 port->ops = &sci_uart_ops; 2950 port->iotype = UPIO_MEM; 2951 port->line = index; 2952 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2953 2954 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2955 if (res == NULL) 2956 return -ENOMEM; 2957 2958 port->mapbase = res->start; 2959 sci_port->reg_size = resource_size(res); 2960 2961 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2962 if (i) 2963 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2964 else 2965 sci_port->irqs[i] = platform_get_irq(dev, i); 2966 } 2967 2968 /* 2969 * The fourth interrupt on SCI port is transmit end interrupt, so 2970 * shuffle the interrupts. 2971 */ 2972 if (p->type == PORT_SCI) 2973 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); 2974 2975 /* The SCI generates several interrupts. They can be muxed together or 2976 * connected to different interrupt lines. In the muxed case only one 2977 * interrupt resource is specified as there is only one interrupt ID. 2978 * In the non-muxed case, up to 6 interrupt signals might be generated 2979 * from the SCI, however those signals might have their own individual 2980 * interrupt ID numbers, or muxed together with another interrupt. 2981 */ 2982 if (sci_port->irqs[0] < 0) 2983 return -ENXIO; 2984 2985 if (sci_port->irqs[1] < 0) 2986 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2987 sci_port->irqs[i] = sci_port->irqs[0]; 2988 2989 sci_port->params = sci_probe_regmap(p); 2990 if (unlikely(sci_port->params == NULL)) 2991 return -EINVAL; 2992 2993 switch (p->type) { 2994 case PORT_SCIFB: 2995 sci_port->rx_trigger = 48; 2996 break; 2997 case PORT_HSCIF: 2998 sci_port->rx_trigger = 64; 2999 break; 3000 case PORT_SCIFA: 3001 sci_port->rx_trigger = 32; 3002 break; 3003 case PORT_SCIF: 3004 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 3005 /* RX triggering not implemented for this IP */ 3006 sci_port->rx_trigger = 1; 3007 else 3008 sci_port->rx_trigger = 8; 3009 break; 3010 default: 3011 sci_port->rx_trigger = 1; 3012 break; 3013 } 3014 3015 sci_port->rx_fifo_timeout = 0; 3016 sci_port->hscif_tot = 0; 3017 3018 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 3019 * match the SoC datasheet, this should be investigated. Let platform 3020 * data override the sampling rate for now. 3021 */ 3022 sci_port->sampling_rate_mask = p->sampling_rate 3023 ? SCI_SR(p->sampling_rate) 3024 : sci_port->params->sampling_rate_mask; 3025 3026 if (!early) { 3027 ret = sci_init_clocks(sci_port, &dev->dev); 3028 if (ret < 0) 3029 return ret; 3030 3031 port->dev = &dev->dev; 3032 3033 pm_runtime_enable(&dev->dev); 3034 } 3035 3036 port->type = p->type; 3037 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 3038 port->fifosize = sci_port->params->fifosize; 3039 3040 if (port->type == PORT_SCI && !dev->dev.of_node) { 3041 if (sci_port->reg_size >= 0x20) 3042 port->regshift = 2; 3043 else 3044 port->regshift = 1; 3045 } 3046 3047 /* 3048 * The UART port needs an IRQ value, so we peg this to the RX IRQ 3049 * for the multi-IRQ ports, which is where we are primarily 3050 * concerned with the shutdown path synchronization. 3051 * 3052 * For the muxed case there's nothing more to do. 3053 */ 3054 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 3055 port->irqflags = 0; 3056 3057 return 0; 3058 } 3059 3060 static void sci_cleanup_single(struct sci_port *port) 3061 { 3062 pm_runtime_disable(port->port.dev); 3063 } 3064 3065 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3066 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3067 static void serial_console_putchar(struct uart_port *port, unsigned char ch) 3068 { 3069 sci_poll_put_char(port, ch); 3070 } 3071 3072 /* 3073 * Print a string to the serial port trying not to disturb 3074 * any possible real use of the port... 3075 */ 3076 static void serial_console_write(struct console *co, const char *s, 3077 unsigned count) 3078 { 3079 struct sci_port *sci_port = &sci_ports[co->index]; 3080 struct uart_port *port = &sci_port->port; 3081 unsigned short bits, ctrl, ctrl_temp; 3082 unsigned long flags; 3083 int locked = 1; 3084 3085 if (port->sysrq) 3086 locked = 0; 3087 else if (oops_in_progress) 3088 locked = uart_port_trylock_irqsave(port, &flags); 3089 else 3090 uart_port_lock_irqsave(port, &flags); 3091 3092 /* first save SCSCR then disable interrupts, keep clock source */ 3093 ctrl = sci_serial_in(port, SCSCR); 3094 ctrl_temp = SCSCR_RE | SCSCR_TE | 3095 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3096 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3097 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3098 3099 uart_console_write(port, s, count, serial_console_putchar); 3100 3101 /* wait until fifo is empty and last bit has been transmitted */ 3102 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3103 while ((sci_serial_in(port, SCxSR) & bits) != bits) 3104 cpu_relax(); 3105 3106 /* restore the SCSCR */ 3107 sci_serial_out(port, SCSCR, ctrl); 3108 3109 if (locked) 3110 uart_port_unlock_irqrestore(port, flags); 3111 } 3112 3113 static int serial_console_setup(struct console *co, char *options) 3114 { 3115 struct sci_port *sci_port; 3116 struct uart_port *port; 3117 int baud = 115200; 3118 int bits = 8; 3119 int parity = 'n'; 3120 int flow = 'n'; 3121 int ret; 3122 3123 /* 3124 * Refuse to handle any bogus ports. 3125 */ 3126 if (co->index < 0 || co->index >= SCI_NPORTS) 3127 return -ENODEV; 3128 3129 sci_port = &sci_ports[co->index]; 3130 port = &sci_port->port; 3131 3132 /* 3133 * Refuse to handle uninitialized ports. 3134 */ 3135 if (!port->ops) 3136 return -ENODEV; 3137 3138 ret = sci_remap_port(port); 3139 if (unlikely(ret != 0)) 3140 return ret; 3141 3142 if (options) 3143 uart_parse_options(options, &baud, &parity, &bits, &flow); 3144 3145 return uart_set_options(port, co, baud, parity, bits, flow); 3146 } 3147 3148 static struct console serial_console = { 3149 .name = "ttySC", 3150 .device = uart_console_device, 3151 .write = serial_console_write, 3152 .setup = serial_console_setup, 3153 .flags = CON_PRINTBUFFER, 3154 .index = -1, 3155 .data = &sci_uart_driver, 3156 }; 3157 3158 #ifdef CONFIG_SUPERH 3159 static char early_serial_buf[32]; 3160 3161 static int early_serial_console_setup(struct console *co, char *options) 3162 { 3163 /* 3164 * This early console is always registered using the earlyprintk= 3165 * parameter, which does not call add_preferred_console(). Thus 3166 * @options is always NULL and the options for this early console 3167 * are passed using a custom buffer. 3168 */ 3169 WARN_ON(options); 3170 3171 return serial_console_setup(co, early_serial_buf); 3172 } 3173 3174 static struct console early_serial_console = { 3175 .name = "early_ttySC", 3176 .write = serial_console_write, 3177 .setup = early_serial_console_setup, 3178 .flags = CON_PRINTBUFFER, 3179 .index = -1, 3180 }; 3181 3182 static int sci_probe_earlyprintk(struct platform_device *pdev) 3183 { 3184 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3185 3186 if (early_serial_console.data) 3187 return -EEXIST; 3188 3189 early_serial_console.index = pdev->id; 3190 3191 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3192 3193 if (!strstr(early_serial_buf, "keep")) 3194 early_serial_console.flags |= CON_BOOT; 3195 3196 register_console(&early_serial_console); 3197 return 0; 3198 } 3199 #endif 3200 3201 #define SCI_CONSOLE (&serial_console) 3202 3203 #else 3204 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3205 { 3206 return -EINVAL; 3207 } 3208 3209 #define SCI_CONSOLE NULL 3210 3211 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3212 3213 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3214 3215 static DEFINE_MUTEX(sci_uart_registration_lock); 3216 static struct uart_driver sci_uart_driver = { 3217 .owner = THIS_MODULE, 3218 .driver_name = "sci", 3219 .dev_name = "ttySC", 3220 .major = SCI_MAJOR, 3221 .minor = SCI_MINOR_START, 3222 .nr = SCI_NPORTS, 3223 .cons = SCI_CONSOLE, 3224 }; 3225 3226 static void sci_remove(struct platform_device *dev) 3227 { 3228 struct sci_port *port = platform_get_drvdata(dev); 3229 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3230 3231 sci_ports_in_use &= ~BIT(port->port.line); 3232 uart_remove_one_port(&sci_uart_driver, &port->port); 3233 3234 sci_cleanup_single(port); 3235 3236 if (port->port.fifosize > 1) 3237 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3238 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3239 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3240 } 3241 3242 3243 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3244 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3245 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3246 3247 static const struct of_device_id of_sci_match[] __maybe_unused = { 3248 /* SoC-specific types */ 3249 { 3250 .compatible = "renesas,scif-r7s72100", 3251 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3252 }, 3253 { 3254 .compatible = "renesas,scif-r7s9210", 3255 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3256 }, 3257 { 3258 .compatible = "renesas,scif-r9a07g044", 3259 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3260 }, 3261 { 3262 .compatible = "renesas,scif-r9a09g057", 3263 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE), 3264 }, 3265 /* Family-specific types */ 3266 { 3267 .compatible = "renesas,rcar-gen1-scif", 3268 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3269 }, { 3270 .compatible = "renesas,rcar-gen2-scif", 3271 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3272 }, { 3273 .compatible = "renesas,rcar-gen3-scif", 3274 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3275 }, { 3276 .compatible = "renesas,rcar-gen4-scif", 3277 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3278 }, 3279 /* Generic types */ 3280 { 3281 .compatible = "renesas,scif", 3282 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3283 }, { 3284 .compatible = "renesas,scifa", 3285 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3286 }, { 3287 .compatible = "renesas,scifb", 3288 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3289 }, { 3290 .compatible = "renesas,hscif", 3291 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3292 }, { 3293 .compatible = "renesas,sci", 3294 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3295 }, { 3296 /* Terminator */ 3297 }, 3298 }; 3299 MODULE_DEVICE_TABLE(of, of_sci_match); 3300 3301 static void sci_reset_control_assert(void *data) 3302 { 3303 reset_control_assert(data); 3304 } 3305 3306 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3307 unsigned int *dev_id) 3308 { 3309 struct device_node *np = pdev->dev.of_node; 3310 struct reset_control *rstc; 3311 struct plat_sci_port *p; 3312 struct sci_port *sp; 3313 const void *data; 3314 int id, ret; 3315 3316 if (!IS_ENABLED(CONFIG_OF) || !np) 3317 return ERR_PTR(-EINVAL); 3318 3319 data = of_device_get_match_data(&pdev->dev); 3320 3321 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3322 if (IS_ERR(rstc)) 3323 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3324 "failed to get reset ctrl\n")); 3325 3326 ret = reset_control_deassert(rstc); 3327 if (ret) { 3328 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3329 return ERR_PTR(ret); 3330 } 3331 3332 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3333 if (ret) { 3334 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3335 ret); 3336 return ERR_PTR(ret); 3337 } 3338 3339 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3340 if (!p) 3341 return ERR_PTR(-ENOMEM); 3342 3343 /* Get the line number from the aliases node. */ 3344 id = of_alias_get_id(np, "serial"); 3345 if (id < 0 && ~sci_ports_in_use) 3346 id = ffz(sci_ports_in_use); 3347 if (id < 0) { 3348 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3349 return ERR_PTR(-EINVAL); 3350 } 3351 if (id >= ARRAY_SIZE(sci_ports)) { 3352 dev_err(&pdev->dev, "serial%d out of range\n", id); 3353 return ERR_PTR(-EINVAL); 3354 } 3355 3356 sp = &sci_ports[id]; 3357 *dev_id = id; 3358 3359 p->type = SCI_OF_TYPE(data); 3360 p->regtype = SCI_OF_REGTYPE(data); 3361 3362 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3363 3364 return p; 3365 } 3366 3367 static int sci_probe_single(struct platform_device *dev, 3368 unsigned int index, 3369 struct plat_sci_port *p, 3370 struct sci_port *sciport) 3371 { 3372 int ret; 3373 3374 /* Sanity check */ 3375 if (unlikely(index >= SCI_NPORTS)) { 3376 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3377 index+1, SCI_NPORTS); 3378 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3379 return -EINVAL; 3380 } 3381 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3382 if (sci_ports_in_use & BIT(index)) 3383 return -EBUSY; 3384 3385 mutex_lock(&sci_uart_registration_lock); 3386 if (!sci_uart_driver.state) { 3387 ret = uart_register_driver(&sci_uart_driver); 3388 if (ret) { 3389 mutex_unlock(&sci_uart_registration_lock); 3390 return ret; 3391 } 3392 } 3393 mutex_unlock(&sci_uart_registration_lock); 3394 3395 ret = sci_init_single(dev, sciport, index, p, false); 3396 if (ret) 3397 return ret; 3398 3399 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3400 if (IS_ERR(sciport->gpios)) 3401 return PTR_ERR(sciport->gpios); 3402 3403 if (sciport->has_rtscts) { 3404 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3405 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3406 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3407 return -EINVAL; 3408 } 3409 sciport->port.flags |= UPF_HARD_FLOW; 3410 } 3411 3412 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3413 if (ret) { 3414 sci_cleanup_single(sciport); 3415 return ret; 3416 } 3417 3418 return 0; 3419 } 3420 3421 static int sci_probe(struct platform_device *dev) 3422 { 3423 struct plat_sci_port *p; 3424 struct sci_port *sp; 3425 unsigned int dev_id; 3426 int ret; 3427 3428 /* 3429 * If we've come here via earlyprintk initialization, head off to 3430 * the special early probe. We don't have sufficient device state 3431 * to make it beyond this yet. 3432 */ 3433 #ifdef CONFIG_SUPERH 3434 if (is_sh_early_platform_device(dev)) 3435 return sci_probe_earlyprintk(dev); 3436 #endif 3437 3438 if (dev->dev.of_node) { 3439 p = sci_parse_dt(dev, &dev_id); 3440 if (IS_ERR(p)) 3441 return PTR_ERR(p); 3442 } else { 3443 p = dev->dev.platform_data; 3444 if (p == NULL) { 3445 dev_err(&dev->dev, "no platform data supplied\n"); 3446 return -EINVAL; 3447 } 3448 3449 dev_id = dev->id; 3450 } 3451 3452 sp = &sci_ports[dev_id]; 3453 platform_set_drvdata(dev, sp); 3454 3455 ret = sci_probe_single(dev, dev_id, p, sp); 3456 if (ret) 3457 return ret; 3458 3459 if (sp->port.fifosize > 1) { 3460 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3461 if (ret) 3462 return ret; 3463 } 3464 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3465 sp->port.type == PORT_HSCIF) { 3466 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3467 if (ret) { 3468 if (sp->port.fifosize > 1) { 3469 device_remove_file(&dev->dev, 3470 &dev_attr_rx_fifo_trigger); 3471 } 3472 return ret; 3473 } 3474 } 3475 3476 #ifdef CONFIG_SH_STANDARD_BIOS 3477 sh_bios_gdb_detach(); 3478 #endif 3479 3480 sci_ports_in_use |= BIT(dev_id); 3481 return 0; 3482 } 3483 3484 static __maybe_unused int sci_suspend(struct device *dev) 3485 { 3486 struct sci_port *sport = dev_get_drvdata(dev); 3487 3488 if (sport) 3489 uart_suspend_port(&sci_uart_driver, &sport->port); 3490 3491 return 0; 3492 } 3493 3494 static __maybe_unused int sci_resume(struct device *dev) 3495 { 3496 struct sci_port *sport = dev_get_drvdata(dev); 3497 3498 if (sport) 3499 uart_resume_port(&sci_uart_driver, &sport->port); 3500 3501 return 0; 3502 } 3503 3504 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3505 3506 static struct platform_driver sci_driver = { 3507 .probe = sci_probe, 3508 .remove_new = sci_remove, 3509 .driver = { 3510 .name = "sh-sci", 3511 .pm = &sci_dev_pm_ops, 3512 .of_match_table = of_match_ptr(of_sci_match), 3513 }, 3514 }; 3515 3516 static int __init sci_init(void) 3517 { 3518 pr_info("%s\n", banner); 3519 3520 return platform_driver_register(&sci_driver); 3521 } 3522 3523 static void __exit sci_exit(void) 3524 { 3525 platform_driver_unregister(&sci_driver); 3526 3527 if (sci_uart_driver.state) 3528 uart_unregister_driver(&sci_uart_driver); 3529 } 3530 3531 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3532 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3533 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3534 #endif 3535 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3536 static struct plat_sci_port port_cfg __initdata; 3537 3538 static int __init early_console_setup(struct earlycon_device *device, 3539 int type) 3540 { 3541 if (!device->port.membase) 3542 return -ENODEV; 3543 3544 device->port.type = type; 3545 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3546 port_cfg.type = type; 3547 sci_ports[0].cfg = &port_cfg; 3548 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3549 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3550 sci_serial_out(&sci_ports[0].port, SCSCR, 3551 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3552 3553 device->con->write = serial_console_write; 3554 return 0; 3555 } 3556 static int __init sci_early_console_setup(struct earlycon_device *device, 3557 const char *opt) 3558 { 3559 return early_console_setup(device, PORT_SCI); 3560 } 3561 static int __init scif_early_console_setup(struct earlycon_device *device, 3562 const char *opt) 3563 { 3564 return early_console_setup(device, PORT_SCIF); 3565 } 3566 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3567 const char *opt) 3568 { 3569 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3570 return early_console_setup(device, PORT_SCIF); 3571 } 3572 3573 static int __init rzv2hscif_early_console_setup(struct earlycon_device *device, 3574 const char *opt) 3575 { 3576 port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE; 3577 return early_console_setup(device, PORT_SCIF); 3578 } 3579 3580 static int __init scifa_early_console_setup(struct earlycon_device *device, 3581 const char *opt) 3582 { 3583 return early_console_setup(device, PORT_SCIFA); 3584 } 3585 static int __init scifb_early_console_setup(struct earlycon_device *device, 3586 const char *opt) 3587 { 3588 return early_console_setup(device, PORT_SCIFB); 3589 } 3590 static int __init hscif_early_console_setup(struct earlycon_device *device, 3591 const char *opt) 3592 { 3593 return early_console_setup(device, PORT_HSCIF); 3594 } 3595 3596 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3597 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3598 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3599 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3600 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup); 3601 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3602 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3603 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3604 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3605 3606 module_init(sci_init); 3607 module_exit(sci_exit); 3608 3609 MODULE_LICENSE("GPL"); 3610 MODULE_ALIAS("platform:sh-sci"); 3611 MODULE_AUTHOR("Paul Mundt"); 3612 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3613