1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 #define SUPPORT_SYSRQ 20 #endif 21 22 #undef DEBUG 23 24 #include <linux/clk.h> 25 #include <linux/console.h> 26 #include <linux/ctype.h> 27 #include <linux/cpufreq.h> 28 #include <linux/delay.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/init.h> 34 #include <linux/interrupt.h> 35 #include <linux/ioport.h> 36 #include <linux/major.h> 37 #include <linux/module.h> 38 #include <linux/mm.h> 39 #include <linux/of.h> 40 #include <linux/of_device.h> 41 #include <linux/platform_device.h> 42 #include <linux/pm_runtime.h> 43 #include <linux/scatterlist.h> 44 #include <linux/serial.h> 45 #include <linux/serial_sci.h> 46 #include <linux/sh_dma.h> 47 #include <linux/slab.h> 48 #include <linux/string.h> 49 #include <linux/sysrq.h> 50 #include <linux/timer.h> 51 #include <linux/tty.h> 52 #include <linux/tty_flip.h> 53 54 #ifdef CONFIG_SUPERH 55 #include <asm/sh_bios.h> 56 #endif 57 58 #include "serial_mctrl_gpio.h" 59 #include "sh-sci.h" 60 61 /* Offsets into the sci_port->irqs array */ 62 enum { 63 SCIx_ERI_IRQ, 64 SCIx_RXI_IRQ, 65 SCIx_TXI_IRQ, 66 SCIx_BRI_IRQ, 67 SCIx_NR_IRQS, 68 69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 70 }; 71 72 #define SCIx_IRQ_IS_MUXED(port) \ 73 ((port)->irqs[SCIx_ERI_IRQ] == \ 74 (port)->irqs[SCIx_RXI_IRQ]) || \ 75 ((port)->irqs[SCIx_ERI_IRQ] && \ 76 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 77 78 enum SCI_CLKS { 79 SCI_FCK, /* Functional Clock */ 80 SCI_SCK, /* Optional External Clock */ 81 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 82 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 83 SCI_NUM_CLKS 84 }; 85 86 /* Bit x set means sampling rate x + 1 is supported */ 87 #define SCI_SR(x) BIT((x) - 1) 88 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 89 90 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 91 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 92 SCI_SR(19) | SCI_SR(27) 93 94 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 95 #define max_sr(_port) fls((_port)->sampling_rate_mask) 96 97 /* Iterate over all supported sampling rates, from high to low */ 98 #define for_each_sr(_sr, _port) \ 99 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 100 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 101 102 struct plat_sci_reg { 103 u8 offset, size; 104 }; 105 106 struct sci_port_params { 107 const struct plat_sci_reg regs[SCIx_NR_REGS]; 108 unsigned int fifosize; 109 unsigned int overrun_reg; 110 unsigned int overrun_mask; 111 unsigned int sampling_rate_mask; 112 unsigned int error_mask; 113 unsigned int error_clear; 114 }; 115 116 struct sci_port { 117 struct uart_port port; 118 119 /* Platform configuration */ 120 const struct sci_port_params *params; 121 const struct plat_sci_port *cfg; 122 unsigned int sampling_rate_mask; 123 resource_size_t reg_size; 124 struct mctrl_gpios *gpios; 125 126 /* Clocks */ 127 struct clk *clks[SCI_NUM_CLKS]; 128 unsigned long clk_rates[SCI_NUM_CLKS]; 129 130 int irqs[SCIx_NR_IRQS]; 131 char *irqstr[SCIx_NR_IRQS]; 132 133 struct dma_chan *chan_tx; 134 struct dma_chan *chan_rx; 135 136 #ifdef CONFIG_SERIAL_SH_SCI_DMA 137 dma_cookie_t cookie_tx; 138 dma_cookie_t cookie_rx[2]; 139 dma_cookie_t active_rx; 140 dma_addr_t tx_dma_addr; 141 unsigned int tx_dma_len; 142 struct scatterlist sg_rx[2]; 143 void *rx_buf[2]; 144 size_t buf_len_rx; 145 struct work_struct work_tx; 146 struct timer_list rx_timer; 147 unsigned int rx_timeout; 148 #endif 149 unsigned int rx_frame; 150 int rx_trigger; 151 struct timer_list rx_fifo_timer; 152 int rx_fifo_timeout; 153 u16 hscif_tot; 154 155 bool has_rtscts; 156 bool autorts; 157 }; 158 159 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 160 161 static struct sci_port sci_ports[SCI_NPORTS]; 162 static struct uart_driver sci_uart_driver; 163 164 static inline struct sci_port * 165 to_sci_port(struct uart_port *uart) 166 { 167 return container_of(uart, struct sci_port, port); 168 } 169 170 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 171 /* 172 * Common SCI definitions, dependent on the port's regshift 173 * value. 174 */ 175 [SCIx_SCI_REGTYPE] = { 176 .regs = { 177 [SCSMR] = { 0x00, 8 }, 178 [SCBRR] = { 0x01, 8 }, 179 [SCSCR] = { 0x02, 8 }, 180 [SCxTDR] = { 0x03, 8 }, 181 [SCxSR] = { 0x04, 8 }, 182 [SCxRDR] = { 0x05, 8 }, 183 }, 184 .fifosize = 1, 185 .overrun_reg = SCxSR, 186 .overrun_mask = SCI_ORER, 187 .sampling_rate_mask = SCI_SR(32), 188 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 189 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 190 }, 191 192 /* 193 * Common definitions for legacy IrDA ports. 194 */ 195 [SCIx_IRDA_REGTYPE] = { 196 .regs = { 197 [SCSMR] = { 0x00, 8 }, 198 [SCBRR] = { 0x02, 8 }, 199 [SCSCR] = { 0x04, 8 }, 200 [SCxTDR] = { 0x06, 8 }, 201 [SCxSR] = { 0x08, 16 }, 202 [SCxRDR] = { 0x0a, 8 }, 203 [SCFCR] = { 0x0c, 8 }, 204 [SCFDR] = { 0x0e, 16 }, 205 }, 206 .fifosize = 1, 207 .overrun_reg = SCxSR, 208 .overrun_mask = SCI_ORER, 209 .sampling_rate_mask = SCI_SR(32), 210 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 211 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 212 }, 213 214 /* 215 * Common SCIFA definitions. 216 */ 217 [SCIx_SCIFA_REGTYPE] = { 218 .regs = { 219 [SCSMR] = { 0x00, 16 }, 220 [SCBRR] = { 0x04, 8 }, 221 [SCSCR] = { 0x08, 16 }, 222 [SCxTDR] = { 0x20, 8 }, 223 [SCxSR] = { 0x14, 16 }, 224 [SCxRDR] = { 0x24, 8 }, 225 [SCFCR] = { 0x18, 16 }, 226 [SCFDR] = { 0x1c, 16 }, 227 [SCPCR] = { 0x30, 16 }, 228 [SCPDR] = { 0x34, 16 }, 229 }, 230 .fifosize = 64, 231 .overrun_reg = SCxSR, 232 .overrun_mask = SCIFA_ORER, 233 .sampling_rate_mask = SCI_SR_SCIFAB, 234 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 235 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 236 }, 237 238 /* 239 * Common SCIFB definitions. 240 */ 241 [SCIx_SCIFB_REGTYPE] = { 242 .regs = { 243 [SCSMR] = { 0x00, 16 }, 244 [SCBRR] = { 0x04, 8 }, 245 [SCSCR] = { 0x08, 16 }, 246 [SCxTDR] = { 0x40, 8 }, 247 [SCxSR] = { 0x14, 16 }, 248 [SCxRDR] = { 0x60, 8 }, 249 [SCFCR] = { 0x18, 16 }, 250 [SCTFDR] = { 0x38, 16 }, 251 [SCRFDR] = { 0x3c, 16 }, 252 [SCPCR] = { 0x30, 16 }, 253 [SCPDR] = { 0x34, 16 }, 254 }, 255 .fifosize = 256, 256 .overrun_reg = SCxSR, 257 .overrun_mask = SCIFA_ORER, 258 .sampling_rate_mask = SCI_SR_SCIFAB, 259 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 260 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 261 }, 262 263 /* 264 * Common SH-2(A) SCIF definitions for ports with FIFO data 265 * count registers. 266 */ 267 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 268 .regs = { 269 [SCSMR] = { 0x00, 16 }, 270 [SCBRR] = { 0x04, 8 }, 271 [SCSCR] = { 0x08, 16 }, 272 [SCxTDR] = { 0x0c, 8 }, 273 [SCxSR] = { 0x10, 16 }, 274 [SCxRDR] = { 0x14, 8 }, 275 [SCFCR] = { 0x18, 16 }, 276 [SCFDR] = { 0x1c, 16 }, 277 [SCSPTR] = { 0x20, 16 }, 278 [SCLSR] = { 0x24, 16 }, 279 }, 280 .fifosize = 16, 281 .overrun_reg = SCLSR, 282 .overrun_mask = SCLSR_ORER, 283 .sampling_rate_mask = SCI_SR(32), 284 .error_mask = SCIF_DEFAULT_ERROR_MASK, 285 .error_clear = SCIF_ERROR_CLEAR, 286 }, 287 288 /* 289 * Common SH-3 SCIF definitions. 290 */ 291 [SCIx_SH3_SCIF_REGTYPE] = { 292 .regs = { 293 [SCSMR] = { 0x00, 8 }, 294 [SCBRR] = { 0x02, 8 }, 295 [SCSCR] = { 0x04, 8 }, 296 [SCxTDR] = { 0x06, 8 }, 297 [SCxSR] = { 0x08, 16 }, 298 [SCxRDR] = { 0x0a, 8 }, 299 [SCFCR] = { 0x0c, 8 }, 300 [SCFDR] = { 0x0e, 16 }, 301 }, 302 .fifosize = 16, 303 .overrun_reg = SCLSR, 304 .overrun_mask = SCLSR_ORER, 305 .sampling_rate_mask = SCI_SR(32), 306 .error_mask = SCIF_DEFAULT_ERROR_MASK, 307 .error_clear = SCIF_ERROR_CLEAR, 308 }, 309 310 /* 311 * Common SH-4(A) SCIF(B) definitions. 312 */ 313 [SCIx_SH4_SCIF_REGTYPE] = { 314 .regs = { 315 [SCSMR] = { 0x00, 16 }, 316 [SCBRR] = { 0x04, 8 }, 317 [SCSCR] = { 0x08, 16 }, 318 [SCxTDR] = { 0x0c, 8 }, 319 [SCxSR] = { 0x10, 16 }, 320 [SCxRDR] = { 0x14, 8 }, 321 [SCFCR] = { 0x18, 16 }, 322 [SCFDR] = { 0x1c, 16 }, 323 [SCSPTR] = { 0x20, 16 }, 324 [SCLSR] = { 0x24, 16 }, 325 }, 326 .fifosize = 16, 327 .overrun_reg = SCLSR, 328 .overrun_mask = SCLSR_ORER, 329 .sampling_rate_mask = SCI_SR(32), 330 .error_mask = SCIF_DEFAULT_ERROR_MASK, 331 .error_clear = SCIF_ERROR_CLEAR, 332 }, 333 334 /* 335 * Common SCIF definitions for ports with a Baud Rate Generator for 336 * External Clock (BRG). 337 */ 338 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 339 .regs = { 340 [SCSMR] = { 0x00, 16 }, 341 [SCBRR] = { 0x04, 8 }, 342 [SCSCR] = { 0x08, 16 }, 343 [SCxTDR] = { 0x0c, 8 }, 344 [SCxSR] = { 0x10, 16 }, 345 [SCxRDR] = { 0x14, 8 }, 346 [SCFCR] = { 0x18, 16 }, 347 [SCFDR] = { 0x1c, 16 }, 348 [SCSPTR] = { 0x20, 16 }, 349 [SCLSR] = { 0x24, 16 }, 350 [SCDL] = { 0x30, 16 }, 351 [SCCKS] = { 0x34, 16 }, 352 }, 353 .fifosize = 16, 354 .overrun_reg = SCLSR, 355 .overrun_mask = SCLSR_ORER, 356 .sampling_rate_mask = SCI_SR(32), 357 .error_mask = SCIF_DEFAULT_ERROR_MASK, 358 .error_clear = SCIF_ERROR_CLEAR, 359 }, 360 361 /* 362 * Common HSCIF definitions. 363 */ 364 [SCIx_HSCIF_REGTYPE] = { 365 .regs = { 366 [SCSMR] = { 0x00, 16 }, 367 [SCBRR] = { 0x04, 8 }, 368 [SCSCR] = { 0x08, 16 }, 369 [SCxTDR] = { 0x0c, 8 }, 370 [SCxSR] = { 0x10, 16 }, 371 [SCxRDR] = { 0x14, 8 }, 372 [SCFCR] = { 0x18, 16 }, 373 [SCFDR] = { 0x1c, 16 }, 374 [SCSPTR] = { 0x20, 16 }, 375 [SCLSR] = { 0x24, 16 }, 376 [HSSRR] = { 0x40, 16 }, 377 [SCDL] = { 0x30, 16 }, 378 [SCCKS] = { 0x34, 16 }, 379 [HSRTRGR] = { 0x54, 16 }, 380 [HSTTRGR] = { 0x58, 16 }, 381 }, 382 .fifosize = 128, 383 .overrun_reg = SCLSR, 384 .overrun_mask = SCLSR_ORER, 385 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 386 .error_mask = SCIF_DEFAULT_ERROR_MASK, 387 .error_clear = SCIF_ERROR_CLEAR, 388 }, 389 390 /* 391 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 392 * register. 393 */ 394 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 395 .regs = { 396 [SCSMR] = { 0x00, 16 }, 397 [SCBRR] = { 0x04, 8 }, 398 [SCSCR] = { 0x08, 16 }, 399 [SCxTDR] = { 0x0c, 8 }, 400 [SCxSR] = { 0x10, 16 }, 401 [SCxRDR] = { 0x14, 8 }, 402 [SCFCR] = { 0x18, 16 }, 403 [SCFDR] = { 0x1c, 16 }, 404 [SCLSR] = { 0x24, 16 }, 405 }, 406 .fifosize = 16, 407 .overrun_reg = SCLSR, 408 .overrun_mask = SCLSR_ORER, 409 .sampling_rate_mask = SCI_SR(32), 410 .error_mask = SCIF_DEFAULT_ERROR_MASK, 411 .error_clear = SCIF_ERROR_CLEAR, 412 }, 413 414 /* 415 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 416 * count registers. 417 */ 418 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 419 .regs = { 420 [SCSMR] = { 0x00, 16 }, 421 [SCBRR] = { 0x04, 8 }, 422 [SCSCR] = { 0x08, 16 }, 423 [SCxTDR] = { 0x0c, 8 }, 424 [SCxSR] = { 0x10, 16 }, 425 [SCxRDR] = { 0x14, 8 }, 426 [SCFCR] = { 0x18, 16 }, 427 [SCFDR] = { 0x1c, 16 }, 428 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 429 [SCRFDR] = { 0x20, 16 }, 430 [SCSPTR] = { 0x24, 16 }, 431 [SCLSR] = { 0x28, 16 }, 432 }, 433 .fifosize = 16, 434 .overrun_reg = SCLSR, 435 .overrun_mask = SCLSR_ORER, 436 .sampling_rate_mask = SCI_SR(32), 437 .error_mask = SCIF_DEFAULT_ERROR_MASK, 438 .error_clear = SCIF_ERROR_CLEAR, 439 }, 440 441 /* 442 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 443 * registers. 444 */ 445 [SCIx_SH7705_SCIF_REGTYPE] = { 446 .regs = { 447 [SCSMR] = { 0x00, 16 }, 448 [SCBRR] = { 0x04, 8 }, 449 [SCSCR] = { 0x08, 16 }, 450 [SCxTDR] = { 0x20, 8 }, 451 [SCxSR] = { 0x14, 16 }, 452 [SCxRDR] = { 0x24, 8 }, 453 [SCFCR] = { 0x18, 16 }, 454 [SCFDR] = { 0x1c, 16 }, 455 }, 456 .fifosize = 64, 457 .overrun_reg = SCxSR, 458 .overrun_mask = SCIFA_ORER, 459 .sampling_rate_mask = SCI_SR(16), 460 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 461 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 462 }, 463 }; 464 465 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 466 467 /* 468 * The "offset" here is rather misleading, in that it refers to an enum 469 * value relative to the port mapping rather than the fixed offset 470 * itself, which needs to be manually retrieved from the platform's 471 * register map for the given port. 472 */ 473 static unsigned int sci_serial_in(struct uart_port *p, int offset) 474 { 475 const struct plat_sci_reg *reg = sci_getreg(p, offset); 476 477 if (reg->size == 8) 478 return ioread8(p->membase + (reg->offset << p->regshift)); 479 else if (reg->size == 16) 480 return ioread16(p->membase + (reg->offset << p->regshift)); 481 else 482 WARN(1, "Invalid register access\n"); 483 484 return 0; 485 } 486 487 static void sci_serial_out(struct uart_port *p, int offset, int value) 488 { 489 const struct plat_sci_reg *reg = sci_getreg(p, offset); 490 491 if (reg->size == 8) 492 iowrite8(value, p->membase + (reg->offset << p->regshift)); 493 else if (reg->size == 16) 494 iowrite16(value, p->membase + (reg->offset << p->regshift)); 495 else 496 WARN(1, "Invalid register access\n"); 497 } 498 499 static void sci_port_enable(struct sci_port *sci_port) 500 { 501 unsigned int i; 502 503 if (!sci_port->port.dev) 504 return; 505 506 pm_runtime_get_sync(sci_port->port.dev); 507 508 for (i = 0; i < SCI_NUM_CLKS; i++) { 509 clk_prepare_enable(sci_port->clks[i]); 510 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 511 } 512 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 513 } 514 515 static void sci_port_disable(struct sci_port *sci_port) 516 { 517 unsigned int i; 518 519 if (!sci_port->port.dev) 520 return; 521 522 for (i = SCI_NUM_CLKS; i-- > 0; ) 523 clk_disable_unprepare(sci_port->clks[i]); 524 525 pm_runtime_put_sync(sci_port->port.dev); 526 } 527 528 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 529 { 530 /* 531 * Not all ports (such as SCIFA) will support REIE. Rather than 532 * special-casing the port type, we check the port initialization 533 * IRQ enable mask to see whether the IRQ is desired at all. If 534 * it's unset, it's logically inferred that there's no point in 535 * testing for it. 536 */ 537 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 538 } 539 540 static void sci_start_tx(struct uart_port *port) 541 { 542 struct sci_port *s = to_sci_port(port); 543 unsigned short ctrl; 544 545 #ifdef CONFIG_SERIAL_SH_SCI_DMA 546 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 547 u16 new, scr = serial_port_in(port, SCSCR); 548 if (s->chan_tx) 549 new = scr | SCSCR_TDRQE; 550 else 551 new = scr & ~SCSCR_TDRQE; 552 if (new != scr) 553 serial_port_out(port, SCSCR, new); 554 } 555 556 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 557 dma_submit_error(s->cookie_tx)) { 558 s->cookie_tx = 0; 559 schedule_work(&s->work_tx); 560 } 561 #endif 562 563 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 564 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 565 ctrl = serial_port_in(port, SCSCR); 566 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 567 } 568 } 569 570 static void sci_stop_tx(struct uart_port *port) 571 { 572 unsigned short ctrl; 573 574 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 575 ctrl = serial_port_in(port, SCSCR); 576 577 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 578 ctrl &= ~SCSCR_TDRQE; 579 580 ctrl &= ~SCSCR_TIE; 581 582 serial_port_out(port, SCSCR, ctrl); 583 } 584 585 static void sci_start_rx(struct uart_port *port) 586 { 587 unsigned short ctrl; 588 589 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 590 591 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 592 ctrl &= ~SCSCR_RDRQE; 593 594 serial_port_out(port, SCSCR, ctrl); 595 } 596 597 static void sci_stop_rx(struct uart_port *port) 598 { 599 unsigned short ctrl; 600 601 ctrl = serial_port_in(port, SCSCR); 602 603 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 604 ctrl &= ~SCSCR_RDRQE; 605 606 ctrl &= ~port_rx_irq_mask(port); 607 608 serial_port_out(port, SCSCR, ctrl); 609 } 610 611 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 612 { 613 if (port->type == PORT_SCI) { 614 /* Just store the mask */ 615 serial_port_out(port, SCxSR, mask); 616 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 617 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 618 /* Only clear the status bits we want to clear */ 619 serial_port_out(port, SCxSR, 620 serial_port_in(port, SCxSR) & mask); 621 } else { 622 /* Store the mask, clear parity/framing errors */ 623 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 624 } 625 } 626 627 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 628 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 629 630 #ifdef CONFIG_CONSOLE_POLL 631 static int sci_poll_get_char(struct uart_port *port) 632 { 633 unsigned short status; 634 int c; 635 636 do { 637 status = serial_port_in(port, SCxSR); 638 if (status & SCxSR_ERRORS(port)) { 639 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 640 continue; 641 } 642 break; 643 } while (1); 644 645 if (!(status & SCxSR_RDxF(port))) 646 return NO_POLL_CHAR; 647 648 c = serial_port_in(port, SCxRDR); 649 650 /* Dummy read */ 651 serial_port_in(port, SCxSR); 652 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 653 654 return c; 655 } 656 #endif 657 658 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 659 { 660 unsigned short status; 661 662 do { 663 status = serial_port_in(port, SCxSR); 664 } while (!(status & SCxSR_TDxE(port))); 665 666 serial_port_out(port, SCxTDR, c); 667 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 668 } 669 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 670 CONFIG_SERIAL_SH_SCI_EARLYCON */ 671 672 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 673 { 674 struct sci_port *s = to_sci_port(port); 675 676 /* 677 * Use port-specific handler if provided. 678 */ 679 if (s->cfg->ops && s->cfg->ops->init_pins) { 680 s->cfg->ops->init_pins(port, cflag); 681 return; 682 } 683 684 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 685 u16 data = serial_port_in(port, SCPDR); 686 u16 ctrl = serial_port_in(port, SCPCR); 687 688 /* Enable RXD and TXD pin functions */ 689 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 690 if (to_sci_port(port)->has_rtscts) { 691 /* RTS# is output, active low, unless autorts */ 692 if (!(port->mctrl & TIOCM_RTS)) { 693 ctrl |= SCPCR_RTSC; 694 data |= SCPDR_RTSD; 695 } else if (!s->autorts) { 696 ctrl |= SCPCR_RTSC; 697 data &= ~SCPDR_RTSD; 698 } else { 699 /* Enable RTS# pin function */ 700 ctrl &= ~SCPCR_RTSC; 701 } 702 /* Enable CTS# pin function */ 703 ctrl &= ~SCPCR_CTSC; 704 } 705 serial_port_out(port, SCPDR, data); 706 serial_port_out(port, SCPCR, ctrl); 707 } else if (sci_getreg(port, SCSPTR)->size) { 708 u16 status = serial_port_in(port, SCSPTR); 709 710 /* RTS# is always output; and active low, unless autorts */ 711 status |= SCSPTR_RTSIO; 712 if (!(port->mctrl & TIOCM_RTS)) 713 status |= SCSPTR_RTSDT; 714 else if (!s->autorts) 715 status &= ~SCSPTR_RTSDT; 716 /* CTS# and SCK are inputs */ 717 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 718 serial_port_out(port, SCSPTR, status); 719 } 720 } 721 722 static int sci_txfill(struct uart_port *port) 723 { 724 struct sci_port *s = to_sci_port(port); 725 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 726 const struct plat_sci_reg *reg; 727 728 reg = sci_getreg(port, SCTFDR); 729 if (reg->size) 730 return serial_port_in(port, SCTFDR) & fifo_mask; 731 732 reg = sci_getreg(port, SCFDR); 733 if (reg->size) 734 return serial_port_in(port, SCFDR) >> 8; 735 736 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 737 } 738 739 static int sci_txroom(struct uart_port *port) 740 { 741 return port->fifosize - sci_txfill(port); 742 } 743 744 static int sci_rxfill(struct uart_port *port) 745 { 746 struct sci_port *s = to_sci_port(port); 747 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 748 const struct plat_sci_reg *reg; 749 750 reg = sci_getreg(port, SCRFDR); 751 if (reg->size) 752 return serial_port_in(port, SCRFDR) & fifo_mask; 753 754 reg = sci_getreg(port, SCFDR); 755 if (reg->size) 756 return serial_port_in(port, SCFDR) & fifo_mask; 757 758 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 759 } 760 761 /* ********************************************************************** * 762 * the interrupt related routines * 763 * ********************************************************************** */ 764 765 static void sci_transmit_chars(struct uart_port *port) 766 { 767 struct circ_buf *xmit = &port->state->xmit; 768 unsigned int stopped = uart_tx_stopped(port); 769 unsigned short status; 770 unsigned short ctrl; 771 int count; 772 773 status = serial_port_in(port, SCxSR); 774 if (!(status & SCxSR_TDxE(port))) { 775 ctrl = serial_port_in(port, SCSCR); 776 if (uart_circ_empty(xmit)) 777 ctrl &= ~SCSCR_TIE; 778 else 779 ctrl |= SCSCR_TIE; 780 serial_port_out(port, SCSCR, ctrl); 781 return; 782 } 783 784 count = sci_txroom(port); 785 786 do { 787 unsigned char c; 788 789 if (port->x_char) { 790 c = port->x_char; 791 port->x_char = 0; 792 } else if (!uart_circ_empty(xmit) && !stopped) { 793 c = xmit->buf[xmit->tail]; 794 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 795 } else { 796 break; 797 } 798 799 serial_port_out(port, SCxTDR, c); 800 801 port->icount.tx++; 802 } while (--count > 0); 803 804 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 805 806 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 807 uart_write_wakeup(port); 808 if (uart_circ_empty(xmit)) { 809 sci_stop_tx(port); 810 } else { 811 ctrl = serial_port_in(port, SCSCR); 812 813 if (port->type != PORT_SCI) { 814 serial_port_in(port, SCxSR); /* Dummy read */ 815 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 816 } 817 818 ctrl |= SCSCR_TIE; 819 serial_port_out(port, SCSCR, ctrl); 820 } 821 } 822 823 /* On SH3, SCIF may read end-of-break as a space->mark char */ 824 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 825 826 static void sci_receive_chars(struct uart_port *port) 827 { 828 struct tty_port *tport = &port->state->port; 829 int i, count, copied = 0; 830 unsigned short status; 831 unsigned char flag; 832 833 status = serial_port_in(port, SCxSR); 834 if (!(status & SCxSR_RDxF(port))) 835 return; 836 837 while (1) { 838 /* Don't copy more bytes than there is room for in the buffer */ 839 count = tty_buffer_request_room(tport, sci_rxfill(port)); 840 841 /* If for any reason we can't copy more data, we're done! */ 842 if (count == 0) 843 break; 844 845 if (port->type == PORT_SCI) { 846 char c = serial_port_in(port, SCxRDR); 847 if (uart_handle_sysrq_char(port, c)) 848 count = 0; 849 else 850 tty_insert_flip_char(tport, c, TTY_NORMAL); 851 } else { 852 for (i = 0; i < count; i++) { 853 char c = serial_port_in(port, SCxRDR); 854 855 status = serial_port_in(port, SCxSR); 856 if (uart_handle_sysrq_char(port, c)) { 857 count--; i--; 858 continue; 859 } 860 861 /* Store data and status */ 862 if (status & SCxSR_FER(port)) { 863 flag = TTY_FRAME; 864 port->icount.frame++; 865 dev_notice(port->dev, "frame error\n"); 866 } else if (status & SCxSR_PER(port)) { 867 flag = TTY_PARITY; 868 port->icount.parity++; 869 dev_notice(port->dev, "parity error\n"); 870 } else 871 flag = TTY_NORMAL; 872 873 tty_insert_flip_char(tport, c, flag); 874 } 875 } 876 877 serial_port_in(port, SCxSR); /* dummy read */ 878 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 879 880 copied += count; 881 port->icount.rx += count; 882 } 883 884 if (copied) { 885 /* Tell the rest of the system the news. New characters! */ 886 tty_flip_buffer_push(tport); 887 } else { 888 /* TTY buffers full; read from RX reg to prevent lockup */ 889 serial_port_in(port, SCxRDR); 890 serial_port_in(port, SCxSR); /* dummy read */ 891 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 892 } 893 } 894 895 static int sci_handle_errors(struct uart_port *port) 896 { 897 int copied = 0; 898 unsigned short status = serial_port_in(port, SCxSR); 899 struct tty_port *tport = &port->state->port; 900 struct sci_port *s = to_sci_port(port); 901 902 /* Handle overruns */ 903 if (status & s->params->overrun_mask) { 904 port->icount.overrun++; 905 906 /* overrun error */ 907 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 908 copied++; 909 910 dev_notice(port->dev, "overrun error\n"); 911 } 912 913 if (status & SCxSR_FER(port)) { 914 /* frame error */ 915 port->icount.frame++; 916 917 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 918 copied++; 919 920 dev_notice(port->dev, "frame error\n"); 921 } 922 923 if (status & SCxSR_PER(port)) { 924 /* parity error */ 925 port->icount.parity++; 926 927 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 928 copied++; 929 930 dev_notice(port->dev, "parity error\n"); 931 } 932 933 if (copied) 934 tty_flip_buffer_push(tport); 935 936 return copied; 937 } 938 939 static int sci_handle_fifo_overrun(struct uart_port *port) 940 { 941 struct tty_port *tport = &port->state->port; 942 struct sci_port *s = to_sci_port(port); 943 const struct plat_sci_reg *reg; 944 int copied = 0; 945 u16 status; 946 947 reg = sci_getreg(port, s->params->overrun_reg); 948 if (!reg->size) 949 return 0; 950 951 status = serial_port_in(port, s->params->overrun_reg); 952 if (status & s->params->overrun_mask) { 953 status &= ~s->params->overrun_mask; 954 serial_port_out(port, s->params->overrun_reg, status); 955 956 port->icount.overrun++; 957 958 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 959 tty_flip_buffer_push(tport); 960 961 dev_dbg(port->dev, "overrun error\n"); 962 copied++; 963 } 964 965 return copied; 966 } 967 968 static int sci_handle_breaks(struct uart_port *port) 969 { 970 int copied = 0; 971 unsigned short status = serial_port_in(port, SCxSR); 972 struct tty_port *tport = &port->state->port; 973 974 if (uart_handle_break(port)) 975 return 0; 976 977 if (status & SCxSR_BRK(port)) { 978 port->icount.brk++; 979 980 /* Notify of BREAK */ 981 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 982 copied++; 983 984 dev_dbg(port->dev, "BREAK detected\n"); 985 } 986 987 if (copied) 988 tty_flip_buffer_push(tport); 989 990 copied += sci_handle_fifo_overrun(port); 991 992 return copied; 993 } 994 995 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 996 { 997 unsigned int bits; 998 999 if (rx_trig < 1) 1000 rx_trig = 1; 1001 if (rx_trig >= port->fifosize) 1002 rx_trig = port->fifosize; 1003 1004 /* HSCIF can be set to an arbitrary level. */ 1005 if (sci_getreg(port, HSRTRGR)->size) { 1006 serial_port_out(port, HSRTRGR, rx_trig); 1007 return rx_trig; 1008 } 1009 1010 switch (port->type) { 1011 case PORT_SCIF: 1012 if (rx_trig < 4) { 1013 bits = 0; 1014 rx_trig = 1; 1015 } else if (rx_trig < 8) { 1016 bits = SCFCR_RTRG0; 1017 rx_trig = 4; 1018 } else if (rx_trig < 14) { 1019 bits = SCFCR_RTRG1; 1020 rx_trig = 8; 1021 } else { 1022 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1023 rx_trig = 14; 1024 } 1025 break; 1026 case PORT_SCIFA: 1027 case PORT_SCIFB: 1028 if (rx_trig < 16) { 1029 bits = 0; 1030 rx_trig = 1; 1031 } else if (rx_trig < 32) { 1032 bits = SCFCR_RTRG0; 1033 rx_trig = 16; 1034 } else if (rx_trig < 48) { 1035 bits = SCFCR_RTRG1; 1036 rx_trig = 32; 1037 } else { 1038 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1039 rx_trig = 48; 1040 } 1041 break; 1042 default: 1043 WARN(1, "unknown FIFO configuration"); 1044 return 1; 1045 } 1046 1047 serial_port_out(port, SCFCR, 1048 (serial_port_in(port, SCFCR) & 1049 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1050 1051 return rx_trig; 1052 } 1053 1054 static int scif_rtrg_enabled(struct uart_port *port) 1055 { 1056 if (sci_getreg(port, HSRTRGR)->size) 1057 return serial_port_in(port, HSRTRGR) != 0; 1058 else 1059 return (serial_port_in(port, SCFCR) & 1060 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1061 } 1062 1063 static void rx_fifo_timer_fn(struct timer_list *t) 1064 { 1065 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1066 struct uart_port *port = &s->port; 1067 1068 dev_dbg(port->dev, "Rx timed out\n"); 1069 scif_set_rtrg(port, 1); 1070 } 1071 1072 static ssize_t rx_trigger_show(struct device *dev, 1073 struct device_attribute *attr, 1074 char *buf) 1075 { 1076 struct uart_port *port = dev_get_drvdata(dev); 1077 struct sci_port *sci = to_sci_port(port); 1078 1079 return sprintf(buf, "%d\n", sci->rx_trigger); 1080 } 1081 1082 static ssize_t rx_trigger_store(struct device *dev, 1083 struct device_attribute *attr, 1084 const char *buf, 1085 size_t count) 1086 { 1087 struct uart_port *port = dev_get_drvdata(dev); 1088 struct sci_port *sci = to_sci_port(port); 1089 int ret; 1090 long r; 1091 1092 ret = kstrtol(buf, 0, &r); 1093 if (ret) 1094 return ret; 1095 1096 sci->rx_trigger = scif_set_rtrg(port, r); 1097 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1098 scif_set_rtrg(port, 1); 1099 1100 return count; 1101 } 1102 1103 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store); 1104 1105 static ssize_t rx_fifo_timeout_show(struct device *dev, 1106 struct device_attribute *attr, 1107 char *buf) 1108 { 1109 struct uart_port *port = dev_get_drvdata(dev); 1110 struct sci_port *sci = to_sci_port(port); 1111 int v; 1112 1113 if (port->type == PORT_HSCIF) 1114 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1115 else 1116 v = sci->rx_fifo_timeout; 1117 1118 return sprintf(buf, "%d\n", v); 1119 } 1120 1121 static ssize_t rx_fifo_timeout_store(struct device *dev, 1122 struct device_attribute *attr, 1123 const char *buf, 1124 size_t count) 1125 { 1126 struct uart_port *port = dev_get_drvdata(dev); 1127 struct sci_port *sci = to_sci_port(port); 1128 int ret; 1129 long r; 1130 1131 ret = kstrtol(buf, 0, &r); 1132 if (ret) 1133 return ret; 1134 1135 if (port->type == PORT_HSCIF) { 1136 if (r < 0 || r > 3) 1137 return -EINVAL; 1138 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1139 } else { 1140 sci->rx_fifo_timeout = r; 1141 scif_set_rtrg(port, 1); 1142 if (r > 0) 1143 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1144 } 1145 1146 return count; 1147 } 1148 1149 static DEVICE_ATTR_RW(rx_fifo_timeout); 1150 1151 1152 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1153 static void sci_dma_tx_complete(void *arg) 1154 { 1155 struct sci_port *s = arg; 1156 struct uart_port *port = &s->port; 1157 struct circ_buf *xmit = &port->state->xmit; 1158 unsigned long flags; 1159 1160 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1161 1162 spin_lock_irqsave(&port->lock, flags); 1163 1164 xmit->tail += s->tx_dma_len; 1165 xmit->tail &= UART_XMIT_SIZE - 1; 1166 1167 port->icount.tx += s->tx_dma_len; 1168 1169 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1170 uart_write_wakeup(port); 1171 1172 if (!uart_circ_empty(xmit)) { 1173 s->cookie_tx = 0; 1174 schedule_work(&s->work_tx); 1175 } else { 1176 s->cookie_tx = -EINVAL; 1177 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1178 u16 ctrl = serial_port_in(port, SCSCR); 1179 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1180 } 1181 } 1182 1183 spin_unlock_irqrestore(&port->lock, flags); 1184 } 1185 1186 /* Locking: called with port lock held */ 1187 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1188 { 1189 struct uart_port *port = &s->port; 1190 struct tty_port *tport = &port->state->port; 1191 int copied; 1192 1193 copied = tty_insert_flip_string(tport, buf, count); 1194 if (copied < count) 1195 port->icount.buf_overrun++; 1196 1197 port->icount.rx += copied; 1198 1199 return copied; 1200 } 1201 1202 static int sci_dma_rx_find_active(struct sci_port *s) 1203 { 1204 unsigned int i; 1205 1206 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1207 if (s->active_rx == s->cookie_rx[i]) 1208 return i; 1209 1210 return -1; 1211 } 1212 1213 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1214 { 1215 struct dma_chan *chan = s->chan_rx; 1216 struct uart_port *port = &s->port; 1217 unsigned long flags; 1218 1219 spin_lock_irqsave(&port->lock, flags); 1220 s->chan_rx = NULL; 1221 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1222 spin_unlock_irqrestore(&port->lock, flags); 1223 dmaengine_terminate_all(chan); 1224 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1225 sg_dma_address(&s->sg_rx[0])); 1226 dma_release_channel(chan); 1227 if (enable_pio) { 1228 spin_lock_irqsave(&port->lock, flags); 1229 sci_start_rx(port); 1230 spin_unlock_irqrestore(&port->lock, flags); 1231 } 1232 } 1233 1234 static void sci_dma_rx_complete(void *arg) 1235 { 1236 struct sci_port *s = arg; 1237 struct dma_chan *chan = s->chan_rx; 1238 struct uart_port *port = &s->port; 1239 struct dma_async_tx_descriptor *desc; 1240 unsigned long flags; 1241 int active, count = 0; 1242 1243 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1244 s->active_rx); 1245 1246 spin_lock_irqsave(&port->lock, flags); 1247 1248 active = sci_dma_rx_find_active(s); 1249 if (active >= 0) 1250 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1251 1252 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1253 1254 if (count) 1255 tty_flip_buffer_push(&port->state->port); 1256 1257 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1258 DMA_DEV_TO_MEM, 1259 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1260 if (!desc) 1261 goto fail; 1262 1263 desc->callback = sci_dma_rx_complete; 1264 desc->callback_param = s; 1265 s->cookie_rx[active] = dmaengine_submit(desc); 1266 if (dma_submit_error(s->cookie_rx[active])) 1267 goto fail; 1268 1269 s->active_rx = s->cookie_rx[!active]; 1270 1271 dma_async_issue_pending(chan); 1272 1273 spin_unlock_irqrestore(&port->lock, flags); 1274 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1275 __func__, s->cookie_rx[active], active, s->active_rx); 1276 return; 1277 1278 fail: 1279 spin_unlock_irqrestore(&port->lock, flags); 1280 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1281 sci_rx_dma_release(s, true); 1282 } 1283 1284 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1285 { 1286 struct dma_chan *chan = s->chan_tx; 1287 struct uart_port *port = &s->port; 1288 unsigned long flags; 1289 1290 spin_lock_irqsave(&port->lock, flags); 1291 s->chan_tx = NULL; 1292 s->cookie_tx = -EINVAL; 1293 spin_unlock_irqrestore(&port->lock, flags); 1294 dmaengine_terminate_all(chan); 1295 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1296 DMA_TO_DEVICE); 1297 dma_release_channel(chan); 1298 if (enable_pio) { 1299 spin_lock_irqsave(&port->lock, flags); 1300 sci_start_tx(port); 1301 spin_unlock_irqrestore(&port->lock, flags); 1302 } 1303 } 1304 1305 static void sci_submit_rx(struct sci_port *s) 1306 { 1307 struct dma_chan *chan = s->chan_rx; 1308 int i; 1309 1310 for (i = 0; i < 2; i++) { 1311 struct scatterlist *sg = &s->sg_rx[i]; 1312 struct dma_async_tx_descriptor *desc; 1313 1314 desc = dmaengine_prep_slave_sg(chan, 1315 sg, 1, DMA_DEV_TO_MEM, 1316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1317 if (!desc) 1318 goto fail; 1319 1320 desc->callback = sci_dma_rx_complete; 1321 desc->callback_param = s; 1322 s->cookie_rx[i] = dmaengine_submit(desc); 1323 if (dma_submit_error(s->cookie_rx[i])) 1324 goto fail; 1325 1326 } 1327 1328 s->active_rx = s->cookie_rx[0]; 1329 1330 dma_async_issue_pending(chan); 1331 return; 1332 1333 fail: 1334 if (i) 1335 dmaengine_terminate_all(chan); 1336 for (i = 0; i < 2; i++) 1337 s->cookie_rx[i] = -EINVAL; 1338 s->active_rx = -EINVAL; 1339 sci_rx_dma_release(s, true); 1340 } 1341 1342 static void work_fn_tx(struct work_struct *work) 1343 { 1344 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1345 struct dma_async_tx_descriptor *desc; 1346 struct dma_chan *chan = s->chan_tx; 1347 struct uart_port *port = &s->port; 1348 struct circ_buf *xmit = &port->state->xmit; 1349 dma_addr_t buf; 1350 1351 /* 1352 * DMA is idle now. 1353 * Port xmit buffer is already mapped, and it is one page... Just adjust 1354 * offsets and lengths. Since it is a circular buffer, we have to 1355 * transmit till the end, and then the rest. Take the port lock to get a 1356 * consistent xmit buffer state. 1357 */ 1358 spin_lock_irq(&port->lock); 1359 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1)); 1360 s->tx_dma_len = min_t(unsigned int, 1361 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1362 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1363 spin_unlock_irq(&port->lock); 1364 1365 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1366 DMA_MEM_TO_DEV, 1367 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1368 if (!desc) { 1369 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1370 /* switch to PIO */ 1371 sci_tx_dma_release(s, true); 1372 return; 1373 } 1374 1375 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1376 DMA_TO_DEVICE); 1377 1378 spin_lock_irq(&port->lock); 1379 desc->callback = sci_dma_tx_complete; 1380 desc->callback_param = s; 1381 spin_unlock_irq(&port->lock); 1382 s->cookie_tx = dmaengine_submit(desc); 1383 if (dma_submit_error(s->cookie_tx)) { 1384 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1385 /* switch to PIO */ 1386 sci_tx_dma_release(s, true); 1387 return; 1388 } 1389 1390 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1391 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1392 1393 dma_async_issue_pending(chan); 1394 } 1395 1396 static void rx_timer_fn(struct timer_list *t) 1397 { 1398 struct sci_port *s = from_timer(s, t, rx_timer); 1399 struct dma_chan *chan = s->chan_rx; 1400 struct uart_port *port = &s->port; 1401 struct dma_tx_state state; 1402 enum dma_status status; 1403 unsigned long flags; 1404 unsigned int read; 1405 int active, count; 1406 u16 scr; 1407 1408 dev_dbg(port->dev, "DMA Rx timed out\n"); 1409 1410 spin_lock_irqsave(&port->lock, flags); 1411 1412 active = sci_dma_rx_find_active(s); 1413 if (active < 0) { 1414 spin_unlock_irqrestore(&port->lock, flags); 1415 return; 1416 } 1417 1418 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1419 if (status == DMA_COMPLETE) { 1420 spin_unlock_irqrestore(&port->lock, flags); 1421 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1422 s->active_rx, active); 1423 1424 /* Let packet complete handler take care of the packet */ 1425 return; 1426 } 1427 1428 dmaengine_pause(chan); 1429 1430 /* 1431 * sometimes DMA transfer doesn't stop even if it is stopped and 1432 * data keeps on coming until transaction is complete so check 1433 * for DMA_COMPLETE again 1434 * Let packet complete handler take care of the packet 1435 */ 1436 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1437 if (status == DMA_COMPLETE) { 1438 spin_unlock_irqrestore(&port->lock, flags); 1439 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1440 return; 1441 } 1442 1443 /* Handle incomplete DMA receive */ 1444 dmaengine_terminate_all(s->chan_rx); 1445 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1446 1447 if (read) { 1448 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1449 if (count) 1450 tty_flip_buffer_push(&port->state->port); 1451 } 1452 1453 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1454 sci_submit_rx(s); 1455 1456 /* Direct new serial port interrupts back to CPU */ 1457 scr = serial_port_in(port, SCSCR); 1458 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1459 scr &= ~SCSCR_RDRQE; 1460 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1461 } 1462 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1463 1464 spin_unlock_irqrestore(&port->lock, flags); 1465 } 1466 1467 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1468 enum dma_transfer_direction dir) 1469 { 1470 struct dma_chan *chan; 1471 struct dma_slave_config cfg; 1472 int ret; 1473 1474 chan = dma_request_slave_channel(port->dev, 1475 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1476 if (!chan) { 1477 dev_warn(port->dev, "dma_request_slave_channel failed\n"); 1478 return NULL; 1479 } 1480 1481 memset(&cfg, 0, sizeof(cfg)); 1482 cfg.direction = dir; 1483 if (dir == DMA_MEM_TO_DEV) { 1484 cfg.dst_addr = port->mapbase + 1485 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1486 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1487 } else { 1488 cfg.src_addr = port->mapbase + 1489 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1490 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1491 } 1492 1493 ret = dmaengine_slave_config(chan, &cfg); 1494 if (ret) { 1495 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1496 dma_release_channel(chan); 1497 return NULL; 1498 } 1499 1500 return chan; 1501 } 1502 1503 static void sci_request_dma(struct uart_port *port) 1504 { 1505 struct sci_port *s = to_sci_port(port); 1506 struct dma_chan *chan; 1507 1508 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1509 1510 if (!port->dev->of_node) 1511 return; 1512 1513 s->cookie_tx = -EINVAL; 1514 1515 /* 1516 * Don't request a dma channel if no channel was specified 1517 * in the device tree. 1518 */ 1519 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1520 return; 1521 1522 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1523 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1524 if (chan) { 1525 s->chan_tx = chan; 1526 /* UART circular tx buffer is an aligned page. */ 1527 s->tx_dma_addr = dma_map_single(chan->device->dev, 1528 port->state->xmit.buf, 1529 UART_XMIT_SIZE, 1530 DMA_TO_DEVICE); 1531 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1532 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1533 dma_release_channel(chan); 1534 s->chan_tx = NULL; 1535 } else { 1536 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1537 __func__, UART_XMIT_SIZE, 1538 port->state->xmit.buf, &s->tx_dma_addr); 1539 } 1540 1541 INIT_WORK(&s->work_tx, work_fn_tx); 1542 } 1543 1544 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1545 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1546 if (chan) { 1547 unsigned int i; 1548 dma_addr_t dma; 1549 void *buf; 1550 1551 s->chan_rx = chan; 1552 1553 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1554 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1555 &dma, GFP_KERNEL); 1556 if (!buf) { 1557 dev_warn(port->dev, 1558 "Failed to allocate Rx dma buffer, using PIO\n"); 1559 dma_release_channel(chan); 1560 s->chan_rx = NULL; 1561 return; 1562 } 1563 1564 for (i = 0; i < 2; i++) { 1565 struct scatterlist *sg = &s->sg_rx[i]; 1566 1567 sg_init_table(sg, 1); 1568 s->rx_buf[i] = buf; 1569 sg_dma_address(sg) = dma; 1570 sg_dma_len(sg) = s->buf_len_rx; 1571 1572 buf += s->buf_len_rx; 1573 dma += s->buf_len_rx; 1574 } 1575 1576 timer_setup(&s->rx_timer, rx_timer_fn, 0); 1577 1578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1579 sci_submit_rx(s); 1580 } 1581 } 1582 1583 static void sci_free_dma(struct uart_port *port) 1584 { 1585 struct sci_port *s = to_sci_port(port); 1586 1587 if (s->chan_tx) 1588 sci_tx_dma_release(s, false); 1589 if (s->chan_rx) 1590 sci_rx_dma_release(s, false); 1591 } 1592 1593 static void sci_flush_buffer(struct uart_port *port) 1594 { 1595 /* 1596 * In uart_flush_buffer(), the xmit circular buffer has just been 1597 * cleared, so we have to reset tx_dma_len accordingly. 1598 */ 1599 to_sci_port(port)->tx_dma_len = 0; 1600 } 1601 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1602 static inline void sci_request_dma(struct uart_port *port) 1603 { 1604 } 1605 1606 static inline void sci_free_dma(struct uart_port *port) 1607 { 1608 } 1609 1610 #define sci_flush_buffer NULL 1611 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1612 1613 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1614 { 1615 struct uart_port *port = ptr; 1616 struct sci_port *s = to_sci_port(port); 1617 1618 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1619 if (s->chan_rx) { 1620 u16 scr = serial_port_in(port, SCSCR); 1621 u16 ssr = serial_port_in(port, SCxSR); 1622 1623 /* Disable future Rx interrupts */ 1624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1625 disable_irq_nosync(irq); 1626 scr |= SCSCR_RDRQE; 1627 } else { 1628 scr &= ~SCSCR_RIE; 1629 sci_submit_rx(s); 1630 } 1631 serial_port_out(port, SCSCR, scr); 1632 /* Clear current interrupt */ 1633 serial_port_out(port, SCxSR, 1634 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1635 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 1636 jiffies, s->rx_timeout); 1637 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1638 1639 return IRQ_HANDLED; 1640 } 1641 #endif 1642 1643 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1644 if (!scif_rtrg_enabled(port)) 1645 scif_set_rtrg(port, s->rx_trigger); 1646 1647 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1648 s->rx_frame * s->rx_fifo_timeout, 1000)); 1649 } 1650 1651 /* I think sci_receive_chars has to be called irrespective 1652 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1653 * to be disabled? 1654 */ 1655 sci_receive_chars(ptr); 1656 1657 return IRQ_HANDLED; 1658 } 1659 1660 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1661 { 1662 struct uart_port *port = ptr; 1663 unsigned long flags; 1664 1665 spin_lock_irqsave(&port->lock, flags); 1666 sci_transmit_chars(port); 1667 spin_unlock_irqrestore(&port->lock, flags); 1668 1669 return IRQ_HANDLED; 1670 } 1671 1672 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1673 { 1674 struct uart_port *port = ptr; 1675 struct sci_port *s = to_sci_port(port); 1676 1677 /* Handle errors */ 1678 if (port->type == PORT_SCI) { 1679 if (sci_handle_errors(port)) { 1680 /* discard character in rx buffer */ 1681 serial_port_in(port, SCxSR); 1682 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1683 } 1684 } else { 1685 sci_handle_fifo_overrun(port); 1686 if (!s->chan_rx) 1687 sci_receive_chars(ptr); 1688 } 1689 1690 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1691 1692 /* Kick the transmission */ 1693 if (!s->chan_tx) 1694 sci_tx_interrupt(irq, ptr); 1695 1696 return IRQ_HANDLED; 1697 } 1698 1699 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1700 { 1701 struct uart_port *port = ptr; 1702 1703 /* Handle BREAKs */ 1704 sci_handle_breaks(port); 1705 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1706 1707 return IRQ_HANDLED; 1708 } 1709 1710 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1711 { 1712 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1713 struct uart_port *port = ptr; 1714 struct sci_port *s = to_sci_port(port); 1715 irqreturn_t ret = IRQ_NONE; 1716 1717 ssr_status = serial_port_in(port, SCxSR); 1718 scr_status = serial_port_in(port, SCSCR); 1719 if (s->params->overrun_reg == SCxSR) 1720 orer_status = ssr_status; 1721 else if (sci_getreg(port, s->params->overrun_reg)->size) 1722 orer_status = serial_port_in(port, s->params->overrun_reg); 1723 1724 err_enabled = scr_status & port_rx_irq_mask(port); 1725 1726 /* Tx Interrupt */ 1727 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1728 !s->chan_tx) 1729 ret = sci_tx_interrupt(irq, ptr); 1730 1731 /* 1732 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1733 * DR flags 1734 */ 1735 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1736 (scr_status & SCSCR_RIE)) 1737 ret = sci_rx_interrupt(irq, ptr); 1738 1739 /* Error Interrupt */ 1740 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1741 ret = sci_er_interrupt(irq, ptr); 1742 1743 /* Break Interrupt */ 1744 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1745 ret = sci_br_interrupt(irq, ptr); 1746 1747 /* Overrun Interrupt */ 1748 if (orer_status & s->params->overrun_mask) { 1749 sci_handle_fifo_overrun(port); 1750 ret = IRQ_HANDLED; 1751 } 1752 1753 return ret; 1754 } 1755 1756 static const struct sci_irq_desc { 1757 const char *desc; 1758 irq_handler_t handler; 1759 } sci_irq_desc[] = { 1760 /* 1761 * Split out handlers, the default case. 1762 */ 1763 [SCIx_ERI_IRQ] = { 1764 .desc = "rx err", 1765 .handler = sci_er_interrupt, 1766 }, 1767 1768 [SCIx_RXI_IRQ] = { 1769 .desc = "rx full", 1770 .handler = sci_rx_interrupt, 1771 }, 1772 1773 [SCIx_TXI_IRQ] = { 1774 .desc = "tx empty", 1775 .handler = sci_tx_interrupt, 1776 }, 1777 1778 [SCIx_BRI_IRQ] = { 1779 .desc = "break", 1780 .handler = sci_br_interrupt, 1781 }, 1782 1783 /* 1784 * Special muxed handler. 1785 */ 1786 [SCIx_MUX_IRQ] = { 1787 .desc = "mux", 1788 .handler = sci_mpxed_interrupt, 1789 }, 1790 }; 1791 1792 static int sci_request_irq(struct sci_port *port) 1793 { 1794 struct uart_port *up = &port->port; 1795 int i, j, ret = 0; 1796 1797 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1798 const struct sci_irq_desc *desc; 1799 int irq; 1800 1801 if (SCIx_IRQ_IS_MUXED(port)) { 1802 i = SCIx_MUX_IRQ; 1803 irq = up->irq; 1804 } else { 1805 irq = port->irqs[i]; 1806 1807 /* 1808 * Certain port types won't support all of the 1809 * available interrupt sources. 1810 */ 1811 if (unlikely(irq < 0)) 1812 continue; 1813 } 1814 1815 desc = sci_irq_desc + i; 1816 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1817 dev_name(up->dev), desc->desc); 1818 if (!port->irqstr[j]) { 1819 ret = -ENOMEM; 1820 goto out_nomem; 1821 } 1822 1823 ret = request_irq(irq, desc->handler, up->irqflags, 1824 port->irqstr[j], port); 1825 if (unlikely(ret)) { 1826 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1827 goto out_noirq; 1828 } 1829 } 1830 1831 return 0; 1832 1833 out_noirq: 1834 while (--i >= 0) 1835 free_irq(port->irqs[i], port); 1836 1837 out_nomem: 1838 while (--j >= 0) 1839 kfree(port->irqstr[j]); 1840 1841 return ret; 1842 } 1843 1844 static void sci_free_irq(struct sci_port *port) 1845 { 1846 int i; 1847 1848 /* 1849 * Intentionally in reverse order so we iterate over the muxed 1850 * IRQ first. 1851 */ 1852 for (i = 0; i < SCIx_NR_IRQS; i++) { 1853 int irq = port->irqs[i]; 1854 1855 /* 1856 * Certain port types won't support all of the available 1857 * interrupt sources. 1858 */ 1859 if (unlikely(irq < 0)) 1860 continue; 1861 1862 free_irq(port->irqs[i], port); 1863 kfree(port->irqstr[i]); 1864 1865 if (SCIx_IRQ_IS_MUXED(port)) { 1866 /* If there's only one IRQ, we're done. */ 1867 return; 1868 } 1869 } 1870 } 1871 1872 static unsigned int sci_tx_empty(struct uart_port *port) 1873 { 1874 unsigned short status = serial_port_in(port, SCxSR); 1875 unsigned short in_tx_fifo = sci_txfill(port); 1876 1877 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1878 } 1879 1880 static void sci_set_rts(struct uart_port *port, bool state) 1881 { 1882 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1883 u16 data = serial_port_in(port, SCPDR); 1884 1885 /* Active low */ 1886 if (state) 1887 data &= ~SCPDR_RTSD; 1888 else 1889 data |= SCPDR_RTSD; 1890 serial_port_out(port, SCPDR, data); 1891 1892 /* RTS# is output */ 1893 serial_port_out(port, SCPCR, 1894 serial_port_in(port, SCPCR) | SCPCR_RTSC); 1895 } else if (sci_getreg(port, SCSPTR)->size) { 1896 u16 ctrl = serial_port_in(port, SCSPTR); 1897 1898 /* Active low */ 1899 if (state) 1900 ctrl &= ~SCSPTR_RTSDT; 1901 else 1902 ctrl |= SCSPTR_RTSDT; 1903 serial_port_out(port, SCSPTR, ctrl); 1904 } 1905 } 1906 1907 static bool sci_get_cts(struct uart_port *port) 1908 { 1909 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1910 /* Active low */ 1911 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 1912 } else if (sci_getreg(port, SCSPTR)->size) { 1913 /* Active low */ 1914 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 1915 } 1916 1917 return true; 1918 } 1919 1920 /* 1921 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 1922 * CTS/RTS is supported in hardware by at least one port and controlled 1923 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 1924 * handled via the ->init_pins() op, which is a bit of a one-way street, 1925 * lacking any ability to defer pin control -- this will later be 1926 * converted over to the GPIO framework). 1927 * 1928 * Other modes (such as loopback) are supported generically on certain 1929 * port types, but not others. For these it's sufficient to test for the 1930 * existence of the support register and simply ignore the port type. 1931 */ 1932 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1933 { 1934 struct sci_port *s = to_sci_port(port); 1935 1936 if (mctrl & TIOCM_LOOP) { 1937 const struct plat_sci_reg *reg; 1938 1939 /* 1940 * Standard loopback mode for SCFCR ports. 1941 */ 1942 reg = sci_getreg(port, SCFCR); 1943 if (reg->size) 1944 serial_port_out(port, SCFCR, 1945 serial_port_in(port, SCFCR) | 1946 SCFCR_LOOP); 1947 } 1948 1949 mctrl_gpio_set(s->gpios, mctrl); 1950 1951 if (!s->has_rtscts) 1952 return; 1953 1954 if (!(mctrl & TIOCM_RTS)) { 1955 /* Disable Auto RTS */ 1956 serial_port_out(port, SCFCR, 1957 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 1958 1959 /* Clear RTS */ 1960 sci_set_rts(port, 0); 1961 } else if (s->autorts) { 1962 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1963 /* Enable RTS# pin function */ 1964 serial_port_out(port, SCPCR, 1965 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 1966 } 1967 1968 /* Enable Auto RTS */ 1969 serial_port_out(port, SCFCR, 1970 serial_port_in(port, SCFCR) | SCFCR_MCE); 1971 } else { 1972 /* Set RTS */ 1973 sci_set_rts(port, 1); 1974 } 1975 } 1976 1977 static unsigned int sci_get_mctrl(struct uart_port *port) 1978 { 1979 struct sci_port *s = to_sci_port(port); 1980 struct mctrl_gpios *gpios = s->gpios; 1981 unsigned int mctrl = 0; 1982 1983 mctrl_gpio_get(gpios, &mctrl); 1984 1985 /* 1986 * CTS/RTS is handled in hardware when supported, while nothing 1987 * else is wired up. 1988 */ 1989 if (s->autorts) { 1990 if (sci_get_cts(port)) 1991 mctrl |= TIOCM_CTS; 1992 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) { 1993 mctrl |= TIOCM_CTS; 1994 } 1995 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))) 1996 mctrl |= TIOCM_DSR; 1997 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))) 1998 mctrl |= TIOCM_CAR; 1999 2000 return mctrl; 2001 } 2002 2003 static void sci_enable_ms(struct uart_port *port) 2004 { 2005 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2006 } 2007 2008 static void sci_break_ctl(struct uart_port *port, int break_state) 2009 { 2010 unsigned short scscr, scsptr; 2011 unsigned long flags; 2012 2013 /* check wheter the port has SCSPTR */ 2014 if (!sci_getreg(port, SCSPTR)->size) { 2015 /* 2016 * Not supported by hardware. Most parts couple break and rx 2017 * interrupts together, with break detection always enabled. 2018 */ 2019 return; 2020 } 2021 2022 spin_lock_irqsave(&port->lock, flags); 2023 scsptr = serial_port_in(port, SCSPTR); 2024 scscr = serial_port_in(port, SCSCR); 2025 2026 if (break_state == -1) { 2027 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2028 scscr &= ~SCSCR_TE; 2029 } else { 2030 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2031 scscr |= SCSCR_TE; 2032 } 2033 2034 serial_port_out(port, SCSPTR, scsptr); 2035 serial_port_out(port, SCSCR, scscr); 2036 spin_unlock_irqrestore(&port->lock, flags); 2037 } 2038 2039 static int sci_startup(struct uart_port *port) 2040 { 2041 struct sci_port *s = to_sci_port(port); 2042 int ret; 2043 2044 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2045 2046 sci_request_dma(port); 2047 2048 ret = sci_request_irq(s); 2049 if (unlikely(ret < 0)) { 2050 sci_free_dma(port); 2051 return ret; 2052 } 2053 2054 return 0; 2055 } 2056 2057 static void sci_shutdown(struct uart_port *port) 2058 { 2059 struct sci_port *s = to_sci_port(port); 2060 unsigned long flags; 2061 u16 scr; 2062 2063 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2064 2065 s->autorts = false; 2066 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2067 2068 spin_lock_irqsave(&port->lock, flags); 2069 sci_stop_rx(port); 2070 sci_stop_tx(port); 2071 /* 2072 * Stop RX and TX, disable related interrupts, keep clock source 2073 * and HSCIF TOT bits 2074 */ 2075 scr = serial_port_in(port, SCSCR); 2076 serial_port_out(port, SCSCR, scr & 2077 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2078 spin_unlock_irqrestore(&port->lock, flags); 2079 2080 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2081 if (s->chan_rx) { 2082 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2083 port->line); 2084 del_timer_sync(&s->rx_timer); 2085 } 2086 #endif 2087 2088 sci_free_irq(s); 2089 sci_free_dma(port); 2090 } 2091 2092 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2093 unsigned int *srr) 2094 { 2095 unsigned long freq = s->clk_rates[SCI_SCK]; 2096 int err, min_err = INT_MAX; 2097 unsigned int sr; 2098 2099 if (s->port.type != PORT_HSCIF) 2100 freq *= 2; 2101 2102 for_each_sr(sr, s) { 2103 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2104 if (abs(err) >= abs(min_err)) 2105 continue; 2106 2107 min_err = err; 2108 *srr = sr - 1; 2109 2110 if (!err) 2111 break; 2112 } 2113 2114 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2115 *srr + 1); 2116 return min_err; 2117 } 2118 2119 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2120 unsigned long freq, unsigned int *dlr, 2121 unsigned int *srr) 2122 { 2123 int err, min_err = INT_MAX; 2124 unsigned int sr, dl; 2125 2126 if (s->port.type != PORT_HSCIF) 2127 freq *= 2; 2128 2129 for_each_sr(sr, s) { 2130 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2131 dl = clamp(dl, 1U, 65535U); 2132 2133 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2134 if (abs(err) >= abs(min_err)) 2135 continue; 2136 2137 min_err = err; 2138 *dlr = dl; 2139 *srr = sr - 1; 2140 2141 if (!err) 2142 break; 2143 } 2144 2145 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2146 min_err, *dlr, *srr + 1); 2147 return min_err; 2148 } 2149 2150 /* calculate sample rate, BRR, and clock select */ 2151 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2152 unsigned int *brr, unsigned int *srr, 2153 unsigned int *cks) 2154 { 2155 unsigned long freq = s->clk_rates[SCI_FCK]; 2156 unsigned int sr, br, prediv, scrate, c; 2157 int err, min_err = INT_MAX; 2158 2159 if (s->port.type != PORT_HSCIF) 2160 freq *= 2; 2161 2162 /* 2163 * Find the combination of sample rate and clock select with the 2164 * smallest deviation from the desired baud rate. 2165 * Prefer high sample rates to maximise the receive margin. 2166 * 2167 * M: Receive margin (%) 2168 * N: Ratio of bit rate to clock (N = sampling rate) 2169 * D: Clock duty (D = 0 to 1.0) 2170 * L: Frame length (L = 9 to 12) 2171 * F: Absolute value of clock frequency deviation 2172 * 2173 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2174 * (|D - 0.5| / N * (1 + F))| 2175 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2176 */ 2177 for_each_sr(sr, s) { 2178 for (c = 0; c <= 3; c++) { 2179 /* integerized formulas from HSCIF documentation */ 2180 prediv = sr * (1 << (2 * c + 1)); 2181 2182 /* 2183 * We need to calculate: 2184 * 2185 * br = freq / (prediv * bps) clamped to [1..256] 2186 * err = freq / (br * prediv) - bps 2187 * 2188 * Watch out for overflow when calculating the desired 2189 * sampling clock rate! 2190 */ 2191 if (bps > UINT_MAX / prediv) 2192 break; 2193 2194 scrate = prediv * bps; 2195 br = DIV_ROUND_CLOSEST(freq, scrate); 2196 br = clamp(br, 1U, 256U); 2197 2198 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2199 if (abs(err) >= abs(min_err)) 2200 continue; 2201 2202 min_err = err; 2203 *brr = br - 1; 2204 *srr = sr - 1; 2205 *cks = c; 2206 2207 if (!err) 2208 goto found; 2209 } 2210 } 2211 2212 found: 2213 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2214 min_err, *brr, *srr + 1, *cks); 2215 return min_err; 2216 } 2217 2218 static void sci_reset(struct uart_port *port) 2219 { 2220 const struct plat_sci_reg *reg; 2221 unsigned int status; 2222 struct sci_port *s = to_sci_port(port); 2223 2224 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2225 2226 reg = sci_getreg(port, SCFCR); 2227 if (reg->size) 2228 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2229 2230 sci_clear_SCxSR(port, 2231 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2232 SCxSR_BREAK_CLEAR(port)); 2233 if (sci_getreg(port, SCLSR)->size) { 2234 status = serial_port_in(port, SCLSR); 2235 status &= ~(SCLSR_TO | SCLSR_ORER); 2236 serial_port_out(port, SCLSR, status); 2237 } 2238 2239 if (s->rx_trigger > 1) { 2240 if (s->rx_fifo_timeout) { 2241 scif_set_rtrg(port, 1); 2242 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2243 } else { 2244 if (port->type == PORT_SCIFA || 2245 port->type == PORT_SCIFB) 2246 scif_set_rtrg(port, 1); 2247 else 2248 scif_set_rtrg(port, s->rx_trigger); 2249 } 2250 } 2251 } 2252 2253 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2254 struct ktermios *old) 2255 { 2256 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2257 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2258 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2259 struct sci_port *s = to_sci_port(port); 2260 const struct plat_sci_reg *reg; 2261 int min_err = INT_MAX, err; 2262 unsigned long max_freq = 0; 2263 int best_clk = -1; 2264 unsigned long flags; 2265 2266 if ((termios->c_cflag & CSIZE) == CS7) 2267 smr_val |= SCSMR_CHR; 2268 if (termios->c_cflag & PARENB) 2269 smr_val |= SCSMR_PE; 2270 if (termios->c_cflag & PARODD) 2271 smr_val |= SCSMR_PE | SCSMR_ODD; 2272 if (termios->c_cflag & CSTOPB) 2273 smr_val |= SCSMR_STOP; 2274 2275 /* 2276 * earlyprintk comes here early on with port->uartclk set to zero. 2277 * the clock framework is not up and running at this point so here 2278 * we assume that 115200 is the maximum baud rate. please note that 2279 * the baud rate is not programmed during earlyprintk - it is assumed 2280 * that the previous boot loader has enabled required clocks and 2281 * setup the baud rate generator hardware for us already. 2282 */ 2283 if (!port->uartclk) { 2284 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2285 goto done; 2286 } 2287 2288 for (i = 0; i < SCI_NUM_CLKS; i++) 2289 max_freq = max(max_freq, s->clk_rates[i]); 2290 2291 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2292 if (!baud) 2293 goto done; 2294 2295 /* 2296 * There can be multiple sources for the sampling clock. Find the one 2297 * that gives us the smallest deviation from the desired baud rate. 2298 */ 2299 2300 /* Optional Undivided External Clock */ 2301 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2302 port->type != PORT_SCIFB) { 2303 err = sci_sck_calc(s, baud, &srr1); 2304 if (abs(err) < abs(min_err)) { 2305 best_clk = SCI_SCK; 2306 scr_val = SCSCR_CKE1; 2307 sccks = SCCKS_CKS; 2308 min_err = err; 2309 srr = srr1; 2310 if (!err) 2311 goto done; 2312 } 2313 } 2314 2315 /* Optional BRG Frequency Divided External Clock */ 2316 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2317 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2318 &srr1); 2319 if (abs(err) < abs(min_err)) { 2320 best_clk = SCI_SCIF_CLK; 2321 scr_val = SCSCR_CKE1; 2322 sccks = 0; 2323 min_err = err; 2324 dl = dl1; 2325 srr = srr1; 2326 if (!err) 2327 goto done; 2328 } 2329 } 2330 2331 /* Optional BRG Frequency Divided Internal Clock */ 2332 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2333 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2334 &srr1); 2335 if (abs(err) < abs(min_err)) { 2336 best_clk = SCI_BRG_INT; 2337 scr_val = SCSCR_CKE1; 2338 sccks = SCCKS_XIN; 2339 min_err = err; 2340 dl = dl1; 2341 srr = srr1; 2342 if (!min_err) 2343 goto done; 2344 } 2345 } 2346 2347 /* Divided Functional Clock using standard Bit Rate Register */ 2348 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2349 if (abs(err) < abs(min_err)) { 2350 best_clk = SCI_FCK; 2351 scr_val = 0; 2352 min_err = err; 2353 brr = brr1; 2354 srr = srr1; 2355 cks = cks1; 2356 } 2357 2358 done: 2359 if (best_clk >= 0) 2360 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2361 s->clks[best_clk], baud, min_err); 2362 2363 sci_port_enable(s); 2364 2365 /* 2366 * Program the optional External Baud Rate Generator (BRG) first. 2367 * It controls the mux to select (H)SCK or frequency divided clock. 2368 */ 2369 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2370 serial_port_out(port, SCDL, dl); 2371 serial_port_out(port, SCCKS, sccks); 2372 } 2373 2374 spin_lock_irqsave(&port->lock, flags); 2375 2376 sci_reset(port); 2377 2378 uart_update_timeout(port, termios->c_cflag, baud); 2379 2380 if (best_clk >= 0) { 2381 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2382 switch (srr + 1) { 2383 case 5: smr_val |= SCSMR_SRC_5; break; 2384 case 7: smr_val |= SCSMR_SRC_7; break; 2385 case 11: smr_val |= SCSMR_SRC_11; break; 2386 case 13: smr_val |= SCSMR_SRC_13; break; 2387 case 16: smr_val |= SCSMR_SRC_16; break; 2388 case 17: smr_val |= SCSMR_SRC_17; break; 2389 case 19: smr_val |= SCSMR_SRC_19; break; 2390 case 27: smr_val |= SCSMR_SRC_27; break; 2391 } 2392 smr_val |= cks; 2393 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2394 serial_port_out(port, SCSMR, smr_val); 2395 serial_port_out(port, SCBRR, brr); 2396 if (sci_getreg(port, HSSRR)->size) 2397 serial_port_out(port, HSSRR, srr | HSCIF_SRE); 2398 2399 /* Wait one bit interval */ 2400 udelay((1000000 + (baud - 1)) / baud); 2401 } else { 2402 /* Don't touch the bit rate configuration */ 2403 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2404 smr_val |= serial_port_in(port, SCSMR) & 2405 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2406 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2407 serial_port_out(port, SCSMR, smr_val); 2408 } 2409 2410 sci_init_pins(port, termios->c_cflag); 2411 2412 port->status &= ~UPSTAT_AUTOCTS; 2413 s->autorts = false; 2414 reg = sci_getreg(port, SCFCR); 2415 if (reg->size) { 2416 unsigned short ctrl = serial_port_in(port, SCFCR); 2417 2418 if ((port->flags & UPF_HARD_FLOW) && 2419 (termios->c_cflag & CRTSCTS)) { 2420 /* There is no CTS interrupt to restart the hardware */ 2421 port->status |= UPSTAT_AUTOCTS; 2422 /* MCE is enabled when RTS is raised */ 2423 s->autorts = true; 2424 } 2425 2426 /* 2427 * As we've done a sci_reset() above, ensure we don't 2428 * interfere with the FIFOs while toggling MCE. As the 2429 * reset values could still be set, simply mask them out. 2430 */ 2431 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2432 2433 serial_port_out(port, SCFCR, ctrl); 2434 } 2435 if (port->flags & UPF_HARD_FLOW) { 2436 /* Refresh (Auto) RTS */ 2437 sci_set_mctrl(port, port->mctrl); 2438 } 2439 2440 scr_val |= SCSCR_RE | SCSCR_TE | 2441 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2442 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2443 if ((srr + 1 == 5) && 2444 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2445 /* 2446 * In asynchronous mode, when the sampling rate is 1/5, first 2447 * received data may become invalid on some SCIFA and SCIFB. 2448 * To avoid this problem wait more than 1 serial data time (1 2449 * bit time x serial data number) after setting SCSCR.RE = 1. 2450 */ 2451 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2452 } 2453 2454 /* 2455 * Calculate delay for 2 DMA buffers (4 FIFO). 2456 * See serial_core.c::uart_update_timeout(). 2457 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2458 * function calculates 1 jiffie for the data plus 5 jiffies for the 2459 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2460 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2461 * value obtained by this formula is too small. Therefore, if the value 2462 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2463 */ 2464 /* byte size and parity */ 2465 switch (termios->c_cflag & CSIZE) { 2466 case CS5: 2467 bits = 7; 2468 break; 2469 case CS6: 2470 bits = 8; 2471 break; 2472 case CS7: 2473 bits = 9; 2474 break; 2475 default: 2476 bits = 10; 2477 break; 2478 } 2479 2480 if (termios->c_cflag & CSTOPB) 2481 bits++; 2482 if (termios->c_cflag & PARENB) 2483 bits++; 2484 2485 s->rx_frame = (100 * bits * HZ) / (baud / 10); 2486 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2487 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000); 2488 if (s->rx_timeout < msecs_to_jiffies(20)) 2489 s->rx_timeout = msecs_to_jiffies(20); 2490 #endif 2491 2492 if ((termios->c_cflag & CREAD) != 0) 2493 sci_start_rx(port); 2494 2495 spin_unlock_irqrestore(&port->lock, flags); 2496 2497 sci_port_disable(s); 2498 2499 if (UART_ENABLE_MS(port, termios->c_cflag)) 2500 sci_enable_ms(port); 2501 } 2502 2503 static void sci_pm(struct uart_port *port, unsigned int state, 2504 unsigned int oldstate) 2505 { 2506 struct sci_port *sci_port = to_sci_port(port); 2507 2508 switch (state) { 2509 case UART_PM_STATE_OFF: 2510 sci_port_disable(sci_port); 2511 break; 2512 default: 2513 sci_port_enable(sci_port); 2514 break; 2515 } 2516 } 2517 2518 static const char *sci_type(struct uart_port *port) 2519 { 2520 switch (port->type) { 2521 case PORT_IRDA: 2522 return "irda"; 2523 case PORT_SCI: 2524 return "sci"; 2525 case PORT_SCIF: 2526 return "scif"; 2527 case PORT_SCIFA: 2528 return "scifa"; 2529 case PORT_SCIFB: 2530 return "scifb"; 2531 case PORT_HSCIF: 2532 return "hscif"; 2533 } 2534 2535 return NULL; 2536 } 2537 2538 static int sci_remap_port(struct uart_port *port) 2539 { 2540 struct sci_port *sport = to_sci_port(port); 2541 2542 /* 2543 * Nothing to do if there's already an established membase. 2544 */ 2545 if (port->membase) 2546 return 0; 2547 2548 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2549 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2550 if (unlikely(!port->membase)) { 2551 dev_err(port->dev, "can't remap port#%d\n", port->line); 2552 return -ENXIO; 2553 } 2554 } else { 2555 /* 2556 * For the simple (and majority of) cases where we don't 2557 * need to do any remapping, just cast the cookie 2558 * directly. 2559 */ 2560 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2561 } 2562 2563 return 0; 2564 } 2565 2566 static void sci_release_port(struct uart_port *port) 2567 { 2568 struct sci_port *sport = to_sci_port(port); 2569 2570 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2571 iounmap(port->membase); 2572 port->membase = NULL; 2573 } 2574 2575 release_mem_region(port->mapbase, sport->reg_size); 2576 } 2577 2578 static int sci_request_port(struct uart_port *port) 2579 { 2580 struct resource *res; 2581 struct sci_port *sport = to_sci_port(port); 2582 int ret; 2583 2584 res = request_mem_region(port->mapbase, sport->reg_size, 2585 dev_name(port->dev)); 2586 if (unlikely(res == NULL)) { 2587 dev_err(port->dev, "request_mem_region failed."); 2588 return -EBUSY; 2589 } 2590 2591 ret = sci_remap_port(port); 2592 if (unlikely(ret != 0)) { 2593 release_resource(res); 2594 return ret; 2595 } 2596 2597 return 0; 2598 } 2599 2600 static void sci_config_port(struct uart_port *port, int flags) 2601 { 2602 if (flags & UART_CONFIG_TYPE) { 2603 struct sci_port *sport = to_sci_port(port); 2604 2605 port->type = sport->cfg->type; 2606 sci_request_port(port); 2607 } 2608 } 2609 2610 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2611 { 2612 if (ser->baud_base < 2400) 2613 /* No paper tape reader for Mitch.. */ 2614 return -EINVAL; 2615 2616 return 0; 2617 } 2618 2619 static const struct uart_ops sci_uart_ops = { 2620 .tx_empty = sci_tx_empty, 2621 .set_mctrl = sci_set_mctrl, 2622 .get_mctrl = sci_get_mctrl, 2623 .start_tx = sci_start_tx, 2624 .stop_tx = sci_stop_tx, 2625 .stop_rx = sci_stop_rx, 2626 .enable_ms = sci_enable_ms, 2627 .break_ctl = sci_break_ctl, 2628 .startup = sci_startup, 2629 .shutdown = sci_shutdown, 2630 .flush_buffer = sci_flush_buffer, 2631 .set_termios = sci_set_termios, 2632 .pm = sci_pm, 2633 .type = sci_type, 2634 .release_port = sci_release_port, 2635 .request_port = sci_request_port, 2636 .config_port = sci_config_port, 2637 .verify_port = sci_verify_port, 2638 #ifdef CONFIG_CONSOLE_POLL 2639 .poll_get_char = sci_poll_get_char, 2640 .poll_put_char = sci_poll_put_char, 2641 #endif 2642 }; 2643 2644 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2645 { 2646 const char *clk_names[] = { 2647 [SCI_FCK] = "fck", 2648 [SCI_SCK] = "sck", 2649 [SCI_BRG_INT] = "brg_int", 2650 [SCI_SCIF_CLK] = "scif_clk", 2651 }; 2652 struct clk *clk; 2653 unsigned int i; 2654 2655 if (sci_port->cfg->type == PORT_HSCIF) 2656 clk_names[SCI_SCK] = "hsck"; 2657 2658 for (i = 0; i < SCI_NUM_CLKS; i++) { 2659 clk = devm_clk_get(dev, clk_names[i]); 2660 if (PTR_ERR(clk) == -EPROBE_DEFER) 2661 return -EPROBE_DEFER; 2662 2663 if (IS_ERR(clk) && i == SCI_FCK) { 2664 /* 2665 * "fck" used to be called "sci_ick", and we need to 2666 * maintain DT backward compatibility. 2667 */ 2668 clk = devm_clk_get(dev, "sci_ick"); 2669 if (PTR_ERR(clk) == -EPROBE_DEFER) 2670 return -EPROBE_DEFER; 2671 2672 if (!IS_ERR(clk)) 2673 goto found; 2674 2675 /* 2676 * Not all SH platforms declare a clock lookup entry 2677 * for SCI devices, in which case we need to get the 2678 * global "peripheral_clk" clock. 2679 */ 2680 clk = devm_clk_get(dev, "peripheral_clk"); 2681 if (!IS_ERR(clk)) 2682 goto found; 2683 2684 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2685 PTR_ERR(clk)); 2686 return PTR_ERR(clk); 2687 } 2688 2689 found: 2690 if (IS_ERR(clk)) 2691 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2692 PTR_ERR(clk)); 2693 else 2694 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i], 2695 clk, clk); 2696 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2697 } 2698 return 0; 2699 } 2700 2701 static const struct sci_port_params * 2702 sci_probe_regmap(const struct plat_sci_port *cfg) 2703 { 2704 unsigned int regtype; 2705 2706 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2707 return &sci_port_params[cfg->regtype]; 2708 2709 switch (cfg->type) { 2710 case PORT_SCI: 2711 regtype = SCIx_SCI_REGTYPE; 2712 break; 2713 case PORT_IRDA: 2714 regtype = SCIx_IRDA_REGTYPE; 2715 break; 2716 case PORT_SCIFA: 2717 regtype = SCIx_SCIFA_REGTYPE; 2718 break; 2719 case PORT_SCIFB: 2720 regtype = SCIx_SCIFB_REGTYPE; 2721 break; 2722 case PORT_SCIF: 2723 /* 2724 * The SH-4 is a bit of a misnomer here, although that's 2725 * where this particular port layout originated. This 2726 * configuration (or some slight variation thereof) 2727 * remains the dominant model for all SCIFs. 2728 */ 2729 regtype = SCIx_SH4_SCIF_REGTYPE; 2730 break; 2731 case PORT_HSCIF: 2732 regtype = SCIx_HSCIF_REGTYPE; 2733 break; 2734 default: 2735 pr_err("Can't probe register map for given port\n"); 2736 return NULL; 2737 } 2738 2739 return &sci_port_params[regtype]; 2740 } 2741 2742 static int sci_init_single(struct platform_device *dev, 2743 struct sci_port *sci_port, unsigned int index, 2744 const struct plat_sci_port *p, bool early) 2745 { 2746 struct uart_port *port = &sci_port->port; 2747 const struct resource *res; 2748 unsigned int i; 2749 int ret; 2750 2751 sci_port->cfg = p; 2752 2753 port->ops = &sci_uart_ops; 2754 port->iotype = UPIO_MEM; 2755 port->line = index; 2756 2757 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2758 if (res == NULL) 2759 return -ENOMEM; 2760 2761 port->mapbase = res->start; 2762 sci_port->reg_size = resource_size(res); 2763 2764 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2765 sci_port->irqs[i] = platform_get_irq(dev, i); 2766 2767 /* The SCI generates several interrupts. They can be muxed together or 2768 * connected to different interrupt lines. In the muxed case only one 2769 * interrupt resource is specified. In the non-muxed case three or four 2770 * interrupt resources are specified, as the BRI interrupt is optional. 2771 */ 2772 if (sci_port->irqs[0] < 0) 2773 return -ENXIO; 2774 2775 if (sci_port->irqs[1] < 0) { 2776 sci_port->irqs[1] = sci_port->irqs[0]; 2777 sci_port->irqs[2] = sci_port->irqs[0]; 2778 sci_port->irqs[3] = sci_port->irqs[0]; 2779 } 2780 2781 sci_port->params = sci_probe_regmap(p); 2782 if (unlikely(sci_port->params == NULL)) 2783 return -EINVAL; 2784 2785 switch (p->type) { 2786 case PORT_SCIFB: 2787 sci_port->rx_trigger = 48; 2788 break; 2789 case PORT_HSCIF: 2790 sci_port->rx_trigger = 64; 2791 break; 2792 case PORT_SCIFA: 2793 sci_port->rx_trigger = 32; 2794 break; 2795 case PORT_SCIF: 2796 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2797 /* RX triggering not implemented for this IP */ 2798 sci_port->rx_trigger = 1; 2799 else 2800 sci_port->rx_trigger = 8; 2801 break; 2802 default: 2803 sci_port->rx_trigger = 1; 2804 break; 2805 } 2806 2807 sci_port->rx_fifo_timeout = 0; 2808 sci_port->hscif_tot = 0; 2809 2810 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2811 * match the SoC datasheet, this should be investigated. Let platform 2812 * data override the sampling rate for now. 2813 */ 2814 sci_port->sampling_rate_mask = p->sampling_rate 2815 ? SCI_SR(p->sampling_rate) 2816 : sci_port->params->sampling_rate_mask; 2817 2818 if (!early) { 2819 ret = sci_init_clocks(sci_port, &dev->dev); 2820 if (ret < 0) 2821 return ret; 2822 2823 port->dev = &dev->dev; 2824 2825 pm_runtime_enable(&dev->dev); 2826 } 2827 2828 port->type = p->type; 2829 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2830 port->fifosize = sci_port->params->fifosize; 2831 2832 if (port->type == PORT_SCI) { 2833 if (sci_port->reg_size >= 0x20) 2834 port->regshift = 2; 2835 else 2836 port->regshift = 1; 2837 } 2838 2839 /* 2840 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2841 * for the multi-IRQ ports, which is where we are primarily 2842 * concerned with the shutdown path synchronization. 2843 * 2844 * For the muxed case there's nothing more to do. 2845 */ 2846 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2847 port->irqflags = 0; 2848 2849 port->serial_in = sci_serial_in; 2850 port->serial_out = sci_serial_out; 2851 2852 return 0; 2853 } 2854 2855 static void sci_cleanup_single(struct sci_port *port) 2856 { 2857 pm_runtime_disable(port->port.dev); 2858 } 2859 2860 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2861 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2862 static void serial_console_putchar(struct uart_port *port, int ch) 2863 { 2864 sci_poll_put_char(port, ch); 2865 } 2866 2867 /* 2868 * Print a string to the serial port trying not to disturb 2869 * any possible real use of the port... 2870 */ 2871 static void serial_console_write(struct console *co, const char *s, 2872 unsigned count) 2873 { 2874 struct sci_port *sci_port = &sci_ports[co->index]; 2875 struct uart_port *port = &sci_port->port; 2876 unsigned short bits, ctrl, ctrl_temp; 2877 unsigned long flags; 2878 int locked = 1; 2879 2880 local_irq_save(flags); 2881 #if defined(SUPPORT_SYSRQ) 2882 if (port->sysrq) 2883 locked = 0; 2884 else 2885 #endif 2886 if (oops_in_progress) 2887 locked = spin_trylock(&port->lock); 2888 else 2889 spin_lock(&port->lock); 2890 2891 /* first save SCSCR then disable interrupts, keep clock source */ 2892 ctrl = serial_port_in(port, SCSCR); 2893 ctrl_temp = SCSCR_RE | SCSCR_TE | 2894 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 2895 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 2896 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 2897 2898 uart_console_write(port, s, count, serial_console_putchar); 2899 2900 /* wait until fifo is empty and last bit has been transmitted */ 2901 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2902 while ((serial_port_in(port, SCxSR) & bits) != bits) 2903 cpu_relax(); 2904 2905 /* restore the SCSCR */ 2906 serial_port_out(port, SCSCR, ctrl); 2907 2908 if (locked) 2909 spin_unlock(&port->lock); 2910 local_irq_restore(flags); 2911 } 2912 2913 static int serial_console_setup(struct console *co, char *options) 2914 { 2915 struct sci_port *sci_port; 2916 struct uart_port *port; 2917 int baud = 115200; 2918 int bits = 8; 2919 int parity = 'n'; 2920 int flow = 'n'; 2921 int ret; 2922 2923 /* 2924 * Refuse to handle any bogus ports. 2925 */ 2926 if (co->index < 0 || co->index >= SCI_NPORTS) 2927 return -ENODEV; 2928 2929 sci_port = &sci_ports[co->index]; 2930 port = &sci_port->port; 2931 2932 /* 2933 * Refuse to handle uninitialized ports. 2934 */ 2935 if (!port->ops) 2936 return -ENODEV; 2937 2938 ret = sci_remap_port(port); 2939 if (unlikely(ret != 0)) 2940 return ret; 2941 2942 if (options) 2943 uart_parse_options(options, &baud, &parity, &bits, &flow); 2944 2945 return uart_set_options(port, co, baud, parity, bits, flow); 2946 } 2947 2948 static struct console serial_console = { 2949 .name = "ttySC", 2950 .device = uart_console_device, 2951 .write = serial_console_write, 2952 .setup = serial_console_setup, 2953 .flags = CON_PRINTBUFFER, 2954 .index = -1, 2955 .data = &sci_uart_driver, 2956 }; 2957 2958 static struct console early_serial_console = { 2959 .name = "early_ttySC", 2960 .write = serial_console_write, 2961 .flags = CON_PRINTBUFFER, 2962 .index = -1, 2963 }; 2964 2965 static char early_serial_buf[32]; 2966 2967 static int sci_probe_earlyprintk(struct platform_device *pdev) 2968 { 2969 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 2970 2971 if (early_serial_console.data) 2972 return -EEXIST; 2973 2974 early_serial_console.index = pdev->id; 2975 2976 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 2977 2978 serial_console_setup(&early_serial_console, early_serial_buf); 2979 2980 if (!strstr(early_serial_buf, "keep")) 2981 early_serial_console.flags |= CON_BOOT; 2982 2983 register_console(&early_serial_console); 2984 return 0; 2985 } 2986 2987 #define SCI_CONSOLE (&serial_console) 2988 2989 #else 2990 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 2991 { 2992 return -EINVAL; 2993 } 2994 2995 #define SCI_CONSOLE NULL 2996 2997 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 2998 2999 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3000 3001 static DEFINE_MUTEX(sci_uart_registration_lock); 3002 static struct uart_driver sci_uart_driver = { 3003 .owner = THIS_MODULE, 3004 .driver_name = "sci", 3005 .dev_name = "ttySC", 3006 .major = SCI_MAJOR, 3007 .minor = SCI_MINOR_START, 3008 .nr = SCI_NPORTS, 3009 .cons = SCI_CONSOLE, 3010 }; 3011 3012 static int sci_remove(struct platform_device *dev) 3013 { 3014 struct sci_port *port = platform_get_drvdata(dev); 3015 3016 uart_remove_one_port(&sci_uart_driver, &port->port); 3017 3018 sci_cleanup_single(port); 3019 3020 if (port->port.fifosize > 1) { 3021 sysfs_remove_file(&dev->dev.kobj, 3022 &dev_attr_rx_fifo_trigger.attr); 3023 } 3024 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB || 3025 port->port.type == PORT_HSCIF) { 3026 sysfs_remove_file(&dev->dev.kobj, 3027 &dev_attr_rx_fifo_timeout.attr); 3028 } 3029 3030 return 0; 3031 } 3032 3033 3034 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3035 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3036 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3037 3038 static const struct of_device_id of_sci_match[] = { 3039 /* SoC-specific types */ 3040 { 3041 .compatible = "renesas,scif-r7s72100", 3042 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3043 }, 3044 /* Family-specific types */ 3045 { 3046 .compatible = "renesas,rcar-gen1-scif", 3047 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3048 }, { 3049 .compatible = "renesas,rcar-gen2-scif", 3050 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3051 }, { 3052 .compatible = "renesas,rcar-gen3-scif", 3053 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3054 }, 3055 /* Generic types */ 3056 { 3057 .compatible = "renesas,scif", 3058 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3059 }, { 3060 .compatible = "renesas,scifa", 3061 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3062 }, { 3063 .compatible = "renesas,scifb", 3064 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3065 }, { 3066 .compatible = "renesas,hscif", 3067 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3068 }, { 3069 .compatible = "renesas,sci", 3070 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3071 }, { 3072 /* Terminator */ 3073 }, 3074 }; 3075 MODULE_DEVICE_TABLE(of, of_sci_match); 3076 3077 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3078 unsigned int *dev_id) 3079 { 3080 struct device_node *np = pdev->dev.of_node; 3081 struct plat_sci_port *p; 3082 struct sci_port *sp; 3083 const void *data; 3084 int id; 3085 3086 if (!IS_ENABLED(CONFIG_OF) || !np) 3087 return NULL; 3088 3089 data = of_device_get_match_data(&pdev->dev); 3090 3091 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3092 if (!p) 3093 return NULL; 3094 3095 /* Get the line number from the aliases node. */ 3096 id = of_alias_get_id(np, "serial"); 3097 if (id < 0) { 3098 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3099 return NULL; 3100 } 3101 3102 sp = &sci_ports[id]; 3103 *dev_id = id; 3104 3105 p->type = SCI_OF_TYPE(data); 3106 p->regtype = SCI_OF_REGTYPE(data); 3107 3108 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3109 3110 return p; 3111 } 3112 3113 static int sci_probe_single(struct platform_device *dev, 3114 unsigned int index, 3115 struct plat_sci_port *p, 3116 struct sci_port *sciport) 3117 { 3118 int ret; 3119 3120 /* Sanity check */ 3121 if (unlikely(index >= SCI_NPORTS)) { 3122 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3123 index+1, SCI_NPORTS); 3124 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3125 return -EINVAL; 3126 } 3127 3128 mutex_lock(&sci_uart_registration_lock); 3129 if (!sci_uart_driver.state) { 3130 ret = uart_register_driver(&sci_uart_driver); 3131 if (ret) { 3132 mutex_unlock(&sci_uart_registration_lock); 3133 return ret; 3134 } 3135 } 3136 mutex_unlock(&sci_uart_registration_lock); 3137 3138 ret = sci_init_single(dev, sciport, index, p, false); 3139 if (ret) 3140 return ret; 3141 3142 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3143 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS) 3144 return PTR_ERR(sciport->gpios); 3145 3146 if (sciport->has_rtscts) { 3147 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3148 UART_GPIO_CTS)) || 3149 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3150 UART_GPIO_RTS))) { 3151 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3152 return -EINVAL; 3153 } 3154 sciport->port.flags |= UPF_HARD_FLOW; 3155 } 3156 3157 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3158 if (ret) { 3159 sci_cleanup_single(sciport); 3160 return ret; 3161 } 3162 3163 return 0; 3164 } 3165 3166 static int sci_probe(struct platform_device *dev) 3167 { 3168 struct plat_sci_port *p; 3169 struct sci_port *sp; 3170 unsigned int dev_id; 3171 int ret; 3172 3173 /* 3174 * If we've come here via earlyprintk initialization, head off to 3175 * the special early probe. We don't have sufficient device state 3176 * to make it beyond this yet. 3177 */ 3178 if (is_early_platform_device(dev)) 3179 return sci_probe_earlyprintk(dev); 3180 3181 if (dev->dev.of_node) { 3182 p = sci_parse_dt(dev, &dev_id); 3183 if (p == NULL) 3184 return -EINVAL; 3185 } else { 3186 p = dev->dev.platform_data; 3187 if (p == NULL) { 3188 dev_err(&dev->dev, "no platform data supplied\n"); 3189 return -EINVAL; 3190 } 3191 3192 dev_id = dev->id; 3193 } 3194 3195 sp = &sci_ports[dev_id]; 3196 platform_set_drvdata(dev, sp); 3197 3198 ret = sci_probe_single(dev, dev_id, p, sp); 3199 if (ret) 3200 return ret; 3201 3202 if (sp->port.fifosize > 1) { 3203 ret = sysfs_create_file(&dev->dev.kobj, 3204 &dev_attr_rx_fifo_trigger.attr); 3205 if (ret) 3206 return ret; 3207 } 3208 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3209 sp->port.type == PORT_HSCIF) { 3210 ret = sysfs_create_file(&dev->dev.kobj, 3211 &dev_attr_rx_fifo_timeout.attr); 3212 if (ret) { 3213 if (sp->port.fifosize > 1) { 3214 sysfs_remove_file(&dev->dev.kobj, 3215 &dev_attr_rx_fifo_trigger.attr); 3216 } 3217 return ret; 3218 } 3219 } 3220 3221 #ifdef CONFIG_SH_STANDARD_BIOS 3222 sh_bios_gdb_detach(); 3223 #endif 3224 3225 return 0; 3226 } 3227 3228 static __maybe_unused int sci_suspend(struct device *dev) 3229 { 3230 struct sci_port *sport = dev_get_drvdata(dev); 3231 3232 if (sport) 3233 uart_suspend_port(&sci_uart_driver, &sport->port); 3234 3235 return 0; 3236 } 3237 3238 static __maybe_unused int sci_resume(struct device *dev) 3239 { 3240 struct sci_port *sport = dev_get_drvdata(dev); 3241 3242 if (sport) 3243 uart_resume_port(&sci_uart_driver, &sport->port); 3244 3245 return 0; 3246 } 3247 3248 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3249 3250 static struct platform_driver sci_driver = { 3251 .probe = sci_probe, 3252 .remove = sci_remove, 3253 .driver = { 3254 .name = "sh-sci", 3255 .pm = &sci_dev_pm_ops, 3256 .of_match_table = of_match_ptr(of_sci_match), 3257 }, 3258 }; 3259 3260 static int __init sci_init(void) 3261 { 3262 pr_info("%s\n", banner); 3263 3264 return platform_driver_register(&sci_driver); 3265 } 3266 3267 static void __exit sci_exit(void) 3268 { 3269 platform_driver_unregister(&sci_driver); 3270 3271 if (sci_uart_driver.state) 3272 uart_unregister_driver(&sci_uart_driver); 3273 } 3274 3275 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 3276 early_platform_init_buffer("earlyprintk", &sci_driver, 3277 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3278 #endif 3279 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3280 static struct plat_sci_port port_cfg __initdata; 3281 3282 static int __init early_console_setup(struct earlycon_device *device, 3283 int type) 3284 { 3285 if (!device->port.membase) 3286 return -ENODEV; 3287 3288 device->port.serial_in = sci_serial_in; 3289 device->port.serial_out = sci_serial_out; 3290 device->port.type = type; 3291 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3292 port_cfg.type = type; 3293 sci_ports[0].cfg = &port_cfg; 3294 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3295 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3296 sci_serial_out(&sci_ports[0].port, SCSCR, 3297 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3298 3299 device->con->write = serial_console_write; 3300 return 0; 3301 } 3302 static int __init sci_early_console_setup(struct earlycon_device *device, 3303 const char *opt) 3304 { 3305 return early_console_setup(device, PORT_SCI); 3306 } 3307 static int __init scif_early_console_setup(struct earlycon_device *device, 3308 const char *opt) 3309 { 3310 return early_console_setup(device, PORT_SCIF); 3311 } 3312 static int __init scifa_early_console_setup(struct earlycon_device *device, 3313 const char *opt) 3314 { 3315 return early_console_setup(device, PORT_SCIFA); 3316 } 3317 static int __init scifb_early_console_setup(struct earlycon_device *device, 3318 const char *opt) 3319 { 3320 return early_console_setup(device, PORT_SCIFB); 3321 } 3322 static int __init hscif_early_console_setup(struct earlycon_device *device, 3323 const char *opt) 3324 { 3325 return early_console_setup(device, PORT_HSCIF); 3326 } 3327 3328 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3329 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3330 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3331 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3332 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3333 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3334 3335 module_init(sci_init); 3336 module_exit(sci_exit); 3337 3338 MODULE_LICENSE("GPL"); 3339 MODULE_ALIAS("platform:sh-sci"); 3340 MODULE_AUTHOR("Paul Mundt"); 3341 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3342