1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/minmax.h> 35 #include <linux/module.h> 36 #include <linux/mm.h> 37 #include <linux/of.h> 38 #include <linux/platform_device.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/reset.h> 41 #include <linux/scatterlist.h> 42 #include <linux/serial.h> 43 #include <linux/serial_sci.h> 44 #include <linux/sh_dma.h> 45 #include <linux/slab.h> 46 #include <linux/string.h> 47 #include <linux/sysrq.h> 48 #include <linux/timer.h> 49 #include <linux/tty.h> 50 #include <linux/tty_flip.h> 51 52 #ifdef CONFIG_SUPERH 53 #include <asm/sh_bios.h> 54 #include <asm/platform_early.h> 55 #endif 56 57 #include "serial_mctrl_gpio.h" 58 #include "sh-sci.h" 59 60 /* Offsets into the sci_port->irqs array */ 61 enum { 62 SCIx_ERI_IRQ, 63 SCIx_RXI_IRQ, 64 SCIx_TXI_IRQ, 65 SCIx_BRI_IRQ, 66 SCIx_DRI_IRQ, 67 SCIx_TEI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71 }; 72 73 #define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79 enum SCI_CLKS { 80 SCI_FCK, /* Functional Clock */ 81 SCI_SCK, /* Optional External Clock */ 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 84 SCI_NUM_CLKS 85 }; 86 87 /* Bit x set means sampling rate x + 1 is supported */ 88 #define SCI_SR(x) BIT((x) - 1) 89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 90 91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 93 SCI_SR(19) | SCI_SR(27) 94 95 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 96 #define max_sr(_port) fls((_port)->sampling_rate_mask) 97 98 /* Iterate over all supported sampling rates, from high to low */ 99 #define for_each_sr(_sr, _port) \ 100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 101 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 102 103 struct plat_sci_reg { 104 u8 offset, size; 105 }; 106 107 struct sci_port_params { 108 const struct plat_sci_reg regs[SCIx_NR_REGS]; 109 unsigned int fifosize; 110 unsigned int overrun_reg; 111 unsigned int overrun_mask; 112 unsigned int sampling_rate_mask; 113 unsigned int error_mask; 114 unsigned int error_clear; 115 }; 116 117 struct sci_port { 118 struct uart_port port; 119 120 /* Platform configuration */ 121 const struct sci_port_params *params; 122 const struct plat_sci_port *cfg; 123 unsigned int sampling_rate_mask; 124 resource_size_t reg_size; 125 struct mctrl_gpios *gpios; 126 127 /* Clocks */ 128 struct clk *clks[SCI_NUM_CLKS]; 129 unsigned long clk_rates[SCI_NUM_CLKS]; 130 131 int irqs[SCIx_NR_IRQS]; 132 char *irqstr[SCIx_NR_IRQS]; 133 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 137 #ifdef CONFIG_SERIAL_SH_SCI_DMA 138 struct dma_chan *chan_tx_saved; 139 struct dma_chan *chan_rx_saved; 140 dma_cookie_t cookie_tx; 141 dma_cookie_t cookie_rx[2]; 142 dma_cookie_t active_rx; 143 dma_addr_t tx_dma_addr; 144 unsigned int tx_dma_len; 145 struct scatterlist sg_rx[2]; 146 void *rx_buf[2]; 147 size_t buf_len_rx; 148 struct work_struct work_tx; 149 struct hrtimer rx_timer; 150 unsigned int rx_timeout; /* microseconds */ 151 #endif 152 unsigned int rx_frame; 153 int rx_trigger; 154 struct timer_list rx_fifo_timer; 155 int rx_fifo_timeout; 156 u16 hscif_tot; 157 158 bool has_rtscts; 159 bool autorts; 160 bool tx_occurred; 161 }; 162 163 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 164 165 static struct sci_port sci_ports[SCI_NPORTS]; 166 static unsigned long sci_ports_in_use; 167 static struct uart_driver sci_uart_driver; 168 static bool sci_uart_earlycon; 169 static bool sci_uart_earlycon_dev_probing; 170 171 static inline struct sci_port * 172 to_sci_port(struct uart_port *uart) 173 { 174 return container_of(uart, struct sci_port, port); 175 } 176 177 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 178 /* 179 * Common SCI definitions, dependent on the port's regshift 180 * value. 181 */ 182 [SCIx_SCI_REGTYPE] = { 183 .regs = { 184 [SCSMR] = { 0x00, 8 }, 185 [SCBRR] = { 0x01, 8 }, 186 [SCSCR] = { 0x02, 8 }, 187 [SCxTDR] = { 0x03, 8 }, 188 [SCxSR] = { 0x04, 8 }, 189 [SCxRDR] = { 0x05, 8 }, 190 }, 191 .fifosize = 1, 192 .overrun_reg = SCxSR, 193 .overrun_mask = SCI_ORER, 194 .sampling_rate_mask = SCI_SR(32), 195 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 196 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 197 }, 198 199 /* 200 * Common definitions for legacy IrDA ports. 201 */ 202 [SCIx_IRDA_REGTYPE] = { 203 .regs = { 204 [SCSMR] = { 0x00, 8 }, 205 [SCBRR] = { 0x02, 8 }, 206 [SCSCR] = { 0x04, 8 }, 207 [SCxTDR] = { 0x06, 8 }, 208 [SCxSR] = { 0x08, 16 }, 209 [SCxRDR] = { 0x0a, 8 }, 210 [SCFCR] = { 0x0c, 8 }, 211 [SCFDR] = { 0x0e, 16 }, 212 }, 213 .fifosize = 1, 214 .overrun_reg = SCxSR, 215 .overrun_mask = SCI_ORER, 216 .sampling_rate_mask = SCI_SR(32), 217 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 218 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 219 }, 220 221 /* 222 * Common SCIFA definitions. 223 */ 224 [SCIx_SCIFA_REGTYPE] = { 225 .regs = { 226 [SCSMR] = { 0x00, 16 }, 227 [SCBRR] = { 0x04, 8 }, 228 [SCSCR] = { 0x08, 16 }, 229 [SCxTDR] = { 0x20, 8 }, 230 [SCxSR] = { 0x14, 16 }, 231 [SCxRDR] = { 0x24, 8 }, 232 [SCFCR] = { 0x18, 16 }, 233 [SCFDR] = { 0x1c, 16 }, 234 [SCPCR] = { 0x30, 16 }, 235 [SCPDR] = { 0x34, 16 }, 236 }, 237 .fifosize = 64, 238 .overrun_reg = SCxSR, 239 .overrun_mask = SCIFA_ORER, 240 .sampling_rate_mask = SCI_SR_SCIFAB, 241 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 242 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 243 }, 244 245 /* 246 * Common SCIFB definitions. 247 */ 248 [SCIx_SCIFB_REGTYPE] = { 249 .regs = { 250 [SCSMR] = { 0x00, 16 }, 251 [SCBRR] = { 0x04, 8 }, 252 [SCSCR] = { 0x08, 16 }, 253 [SCxTDR] = { 0x40, 8 }, 254 [SCxSR] = { 0x14, 16 }, 255 [SCxRDR] = { 0x60, 8 }, 256 [SCFCR] = { 0x18, 16 }, 257 [SCTFDR] = { 0x38, 16 }, 258 [SCRFDR] = { 0x3c, 16 }, 259 [SCPCR] = { 0x30, 16 }, 260 [SCPDR] = { 0x34, 16 }, 261 }, 262 .fifosize = 256, 263 .overrun_reg = SCxSR, 264 .overrun_mask = SCIFA_ORER, 265 .sampling_rate_mask = SCI_SR_SCIFAB, 266 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 267 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 268 }, 269 270 /* 271 * Common SH-2(A) SCIF definitions for ports with FIFO data 272 * count registers. 273 */ 274 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 275 .regs = { 276 [SCSMR] = { 0x00, 16 }, 277 [SCBRR] = { 0x04, 8 }, 278 [SCSCR] = { 0x08, 16 }, 279 [SCxTDR] = { 0x0c, 8 }, 280 [SCxSR] = { 0x10, 16 }, 281 [SCxRDR] = { 0x14, 8 }, 282 [SCFCR] = { 0x18, 16 }, 283 [SCFDR] = { 0x1c, 16 }, 284 [SCSPTR] = { 0x20, 16 }, 285 [SCLSR] = { 0x24, 16 }, 286 }, 287 .fifosize = 16, 288 .overrun_reg = SCLSR, 289 .overrun_mask = SCLSR_ORER, 290 .sampling_rate_mask = SCI_SR(32), 291 .error_mask = SCIF_DEFAULT_ERROR_MASK, 292 .error_clear = SCIF_ERROR_CLEAR, 293 }, 294 295 /* 296 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 297 * It looks like a normal SCIF with FIFO data, but with a 298 * compressed address space. Also, the break out of interrupts 299 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 300 */ 301 [SCIx_RZ_SCIFA_REGTYPE] = { 302 .regs = { 303 [SCSMR] = { 0x00, 16 }, 304 [SCBRR] = { 0x02, 8 }, 305 [SCSCR] = { 0x04, 16 }, 306 [SCxTDR] = { 0x06, 8 }, 307 [SCxSR] = { 0x08, 16 }, 308 [SCxRDR] = { 0x0A, 8 }, 309 [SCFCR] = { 0x0C, 16 }, 310 [SCFDR] = { 0x0E, 16 }, 311 [SCSPTR] = { 0x10, 16 }, 312 [SCLSR] = { 0x12, 16 }, 313 [SEMR] = { 0x14, 8 }, 314 }, 315 .fifosize = 16, 316 .overrun_reg = SCLSR, 317 .overrun_mask = SCLSR_ORER, 318 .sampling_rate_mask = SCI_SR(32), 319 .error_mask = SCIF_DEFAULT_ERROR_MASK, 320 .error_clear = SCIF_ERROR_CLEAR, 321 }, 322 323 /* 324 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC 325 * with below differences, 326 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI, 327 * TEI-DRI, RXI-EDGE and TXI-EDGE. 328 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode. 329 * - SCFCR register does not have SCFCR_MCE bit. 330 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO. 331 */ 332 [SCIx_RZV2H_SCIF_REGTYPE] = { 333 .regs = { 334 [SCSMR] = { 0x00, 16 }, 335 [SCBRR] = { 0x02, 8 }, 336 [SCSCR] = { 0x04, 16 }, 337 [SCxTDR] = { 0x06, 8 }, 338 [SCxSR] = { 0x08, 16 }, 339 [SCxRDR] = { 0x0a, 8 }, 340 [SCFCR] = { 0x0c, 16 }, 341 [SCFDR] = { 0x0e, 16 }, 342 [SCSPTR] = { 0x10, 16 }, 343 [SCLSR] = { 0x12, 16 }, 344 [SEMR] = { 0x14, 8 }, 345 }, 346 .fifosize = 16, 347 .overrun_reg = SCLSR, 348 .overrun_mask = SCLSR_ORER, 349 .sampling_rate_mask = SCI_SR(32), 350 .error_mask = SCIF_DEFAULT_ERROR_MASK, 351 .error_clear = SCIF_ERROR_CLEAR, 352 }, 353 354 /* 355 * Common SH-3 SCIF definitions. 356 */ 357 [SCIx_SH3_SCIF_REGTYPE] = { 358 .regs = { 359 [SCSMR] = { 0x00, 8 }, 360 [SCBRR] = { 0x02, 8 }, 361 [SCSCR] = { 0x04, 8 }, 362 [SCxTDR] = { 0x06, 8 }, 363 [SCxSR] = { 0x08, 16 }, 364 [SCxRDR] = { 0x0a, 8 }, 365 [SCFCR] = { 0x0c, 8 }, 366 [SCFDR] = { 0x0e, 16 }, 367 }, 368 .fifosize = 16, 369 .overrun_reg = SCLSR, 370 .overrun_mask = SCLSR_ORER, 371 .sampling_rate_mask = SCI_SR(32), 372 .error_mask = SCIF_DEFAULT_ERROR_MASK, 373 .error_clear = SCIF_ERROR_CLEAR, 374 }, 375 376 /* 377 * Common SH-4(A) SCIF(B) definitions. 378 */ 379 [SCIx_SH4_SCIF_REGTYPE] = { 380 .regs = { 381 [SCSMR] = { 0x00, 16 }, 382 [SCBRR] = { 0x04, 8 }, 383 [SCSCR] = { 0x08, 16 }, 384 [SCxTDR] = { 0x0c, 8 }, 385 [SCxSR] = { 0x10, 16 }, 386 [SCxRDR] = { 0x14, 8 }, 387 [SCFCR] = { 0x18, 16 }, 388 [SCFDR] = { 0x1c, 16 }, 389 [SCSPTR] = { 0x20, 16 }, 390 [SCLSR] = { 0x24, 16 }, 391 }, 392 .fifosize = 16, 393 .overrun_reg = SCLSR, 394 .overrun_mask = SCLSR_ORER, 395 .sampling_rate_mask = SCI_SR(32), 396 .error_mask = SCIF_DEFAULT_ERROR_MASK, 397 .error_clear = SCIF_ERROR_CLEAR, 398 }, 399 400 /* 401 * Common SCIF definitions for ports with a Baud Rate Generator for 402 * External Clock (BRG). 403 */ 404 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 405 .regs = { 406 [SCSMR] = { 0x00, 16 }, 407 [SCBRR] = { 0x04, 8 }, 408 [SCSCR] = { 0x08, 16 }, 409 [SCxTDR] = { 0x0c, 8 }, 410 [SCxSR] = { 0x10, 16 }, 411 [SCxRDR] = { 0x14, 8 }, 412 [SCFCR] = { 0x18, 16 }, 413 [SCFDR] = { 0x1c, 16 }, 414 [SCSPTR] = { 0x20, 16 }, 415 [SCLSR] = { 0x24, 16 }, 416 [SCDL] = { 0x30, 16 }, 417 [SCCKS] = { 0x34, 16 }, 418 }, 419 .fifosize = 16, 420 .overrun_reg = SCLSR, 421 .overrun_mask = SCLSR_ORER, 422 .sampling_rate_mask = SCI_SR(32), 423 .error_mask = SCIF_DEFAULT_ERROR_MASK, 424 .error_clear = SCIF_ERROR_CLEAR, 425 }, 426 427 /* 428 * Common HSCIF definitions. 429 */ 430 [SCIx_HSCIF_REGTYPE] = { 431 .regs = { 432 [SCSMR] = { 0x00, 16 }, 433 [SCBRR] = { 0x04, 8 }, 434 [SCSCR] = { 0x08, 16 }, 435 [SCxTDR] = { 0x0c, 8 }, 436 [SCxSR] = { 0x10, 16 }, 437 [SCxRDR] = { 0x14, 8 }, 438 [SCFCR] = { 0x18, 16 }, 439 [SCFDR] = { 0x1c, 16 }, 440 [SCSPTR] = { 0x20, 16 }, 441 [SCLSR] = { 0x24, 16 }, 442 [HSSRR] = { 0x40, 16 }, 443 [SCDL] = { 0x30, 16 }, 444 [SCCKS] = { 0x34, 16 }, 445 [HSRTRGR] = { 0x54, 16 }, 446 [HSTTRGR] = { 0x58, 16 }, 447 }, 448 .fifosize = 128, 449 .overrun_reg = SCLSR, 450 .overrun_mask = SCLSR_ORER, 451 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 452 .error_mask = SCIF_DEFAULT_ERROR_MASK, 453 .error_clear = SCIF_ERROR_CLEAR, 454 }, 455 456 /* 457 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 458 * register. 459 */ 460 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 461 .regs = { 462 [SCSMR] = { 0x00, 16 }, 463 [SCBRR] = { 0x04, 8 }, 464 [SCSCR] = { 0x08, 16 }, 465 [SCxTDR] = { 0x0c, 8 }, 466 [SCxSR] = { 0x10, 16 }, 467 [SCxRDR] = { 0x14, 8 }, 468 [SCFCR] = { 0x18, 16 }, 469 [SCFDR] = { 0x1c, 16 }, 470 [SCLSR] = { 0x24, 16 }, 471 }, 472 .fifosize = 16, 473 .overrun_reg = SCLSR, 474 .overrun_mask = SCLSR_ORER, 475 .sampling_rate_mask = SCI_SR(32), 476 .error_mask = SCIF_DEFAULT_ERROR_MASK, 477 .error_clear = SCIF_ERROR_CLEAR, 478 }, 479 480 /* 481 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 482 * count registers. 483 */ 484 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 485 .regs = { 486 [SCSMR] = { 0x00, 16 }, 487 [SCBRR] = { 0x04, 8 }, 488 [SCSCR] = { 0x08, 16 }, 489 [SCxTDR] = { 0x0c, 8 }, 490 [SCxSR] = { 0x10, 16 }, 491 [SCxRDR] = { 0x14, 8 }, 492 [SCFCR] = { 0x18, 16 }, 493 [SCFDR] = { 0x1c, 16 }, 494 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 495 [SCRFDR] = { 0x20, 16 }, 496 [SCSPTR] = { 0x24, 16 }, 497 [SCLSR] = { 0x28, 16 }, 498 }, 499 .fifosize = 16, 500 .overrun_reg = SCLSR, 501 .overrun_mask = SCLSR_ORER, 502 .sampling_rate_mask = SCI_SR(32), 503 .error_mask = SCIF_DEFAULT_ERROR_MASK, 504 .error_clear = SCIF_ERROR_CLEAR, 505 }, 506 507 /* 508 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 509 * registers. 510 */ 511 [SCIx_SH7705_SCIF_REGTYPE] = { 512 .regs = { 513 [SCSMR] = { 0x00, 16 }, 514 [SCBRR] = { 0x04, 8 }, 515 [SCSCR] = { 0x08, 16 }, 516 [SCxTDR] = { 0x20, 8 }, 517 [SCxSR] = { 0x14, 16 }, 518 [SCxRDR] = { 0x24, 8 }, 519 [SCFCR] = { 0x18, 16 }, 520 [SCFDR] = { 0x1c, 16 }, 521 }, 522 .fifosize = 64, 523 .overrun_reg = SCxSR, 524 .overrun_mask = SCIFA_ORER, 525 .sampling_rate_mask = SCI_SR(16), 526 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 527 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 528 }, 529 }; 530 531 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 532 533 /* 534 * The "offset" here is rather misleading, in that it refers to an enum 535 * value relative to the port mapping rather than the fixed offset 536 * itself, which needs to be manually retrieved from the platform's 537 * register map for the given port. 538 */ 539 static unsigned int sci_serial_in(struct uart_port *p, int offset) 540 { 541 const struct plat_sci_reg *reg = sci_getreg(p, offset); 542 543 if (reg->size == 8) 544 return ioread8(p->membase + (reg->offset << p->regshift)); 545 else if (reg->size == 16) 546 return ioread16(p->membase + (reg->offset << p->regshift)); 547 else 548 WARN(1, "Invalid register access\n"); 549 550 return 0; 551 } 552 553 static void sci_serial_out(struct uart_port *p, int offset, int value) 554 { 555 const struct plat_sci_reg *reg = sci_getreg(p, offset); 556 557 if (reg->size == 8) 558 iowrite8(value, p->membase + (reg->offset << p->regshift)); 559 else if (reg->size == 16) 560 iowrite16(value, p->membase + (reg->offset << p->regshift)); 561 else 562 WARN(1, "Invalid register access\n"); 563 } 564 565 static void sci_port_enable(struct sci_port *sci_port) 566 { 567 unsigned int i; 568 569 if (!sci_port->port.dev) 570 return; 571 572 pm_runtime_get_sync(sci_port->port.dev); 573 574 for (i = 0; i < SCI_NUM_CLKS; i++) { 575 clk_prepare_enable(sci_port->clks[i]); 576 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 577 } 578 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 579 } 580 581 static void sci_port_disable(struct sci_port *sci_port) 582 { 583 unsigned int i; 584 585 if (!sci_port->port.dev) 586 return; 587 588 for (i = SCI_NUM_CLKS; i-- > 0; ) 589 clk_disable_unprepare(sci_port->clks[i]); 590 591 pm_runtime_put_sync(sci_port->port.dev); 592 } 593 594 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 595 { 596 /* 597 * Not all ports (such as SCIFA) will support REIE. Rather than 598 * special-casing the port type, we check the port initialization 599 * IRQ enable mask to see whether the IRQ is desired at all. If 600 * it's unset, it's logically inferred that there's no point in 601 * testing for it. 602 */ 603 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 604 } 605 606 static void sci_start_tx(struct uart_port *port) 607 { 608 struct sci_port *s = to_sci_port(port); 609 unsigned short ctrl; 610 611 #ifdef CONFIG_SERIAL_SH_SCI_DMA 612 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 613 u16 new, scr = sci_serial_in(port, SCSCR); 614 if (s->chan_tx) 615 new = scr | SCSCR_TDRQE; 616 else 617 new = scr & ~SCSCR_TDRQE; 618 if (new != scr) 619 sci_serial_out(port, SCSCR, new); 620 } 621 622 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) && 623 dma_submit_error(s->cookie_tx)) { 624 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 625 /* Switch irq from SCIF to DMA */ 626 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); 627 628 s->cookie_tx = 0; 629 schedule_work(&s->work_tx); 630 } 631 #endif 632 633 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || 634 port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 635 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 636 ctrl = sci_serial_in(port, SCSCR); 637 638 /* 639 * For SCI, TE (transmit enable) must be set after setting TIE 640 * (transmit interrupt enable) or in the same instruction to start 641 * the transmit process. 642 */ 643 if (port->type == PORT_SCI) 644 ctrl |= SCSCR_TE; 645 646 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE); 647 } 648 } 649 650 static void sci_stop_tx(struct uart_port *port) 651 { 652 unsigned short ctrl; 653 654 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 655 ctrl = sci_serial_in(port, SCSCR); 656 657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 658 ctrl &= ~SCSCR_TDRQE; 659 660 ctrl &= ~SCSCR_TIE; 661 662 sci_serial_out(port, SCSCR, ctrl); 663 664 #ifdef CONFIG_SERIAL_SH_SCI_DMA 665 if (to_sci_port(port)->chan_tx && 666 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 667 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 668 to_sci_port(port)->cookie_tx = -EINVAL; 669 } 670 #endif 671 } 672 673 static void sci_start_rx(struct uart_port *port) 674 { 675 unsigned short ctrl; 676 677 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port); 678 679 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 680 ctrl &= ~SCSCR_RDRQE; 681 682 sci_serial_out(port, SCSCR, ctrl); 683 } 684 685 static void sci_stop_rx(struct uart_port *port) 686 { 687 unsigned short ctrl; 688 689 ctrl = sci_serial_in(port, SCSCR); 690 691 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 692 ctrl &= ~SCSCR_RDRQE; 693 694 ctrl &= ~port_rx_irq_mask(port); 695 696 sci_serial_out(port, SCSCR, ctrl); 697 } 698 699 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 700 { 701 if (port->type == PORT_SCI) { 702 /* Just store the mask */ 703 sci_serial_out(port, SCxSR, mask); 704 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 705 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 706 /* Only clear the status bits we want to clear */ 707 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask); 708 } else { 709 /* Store the mask, clear parity/framing errors */ 710 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 711 } 712 } 713 714 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 715 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 716 717 #ifdef CONFIG_CONSOLE_POLL 718 static int sci_poll_get_char(struct uart_port *port) 719 { 720 unsigned short status; 721 int c; 722 723 do { 724 status = sci_serial_in(port, SCxSR); 725 if (status & SCxSR_ERRORS(port)) { 726 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 727 continue; 728 } 729 break; 730 } while (1); 731 732 if (!(status & SCxSR_RDxF(port))) 733 return NO_POLL_CHAR; 734 735 c = sci_serial_in(port, SCxRDR); 736 737 /* Dummy read */ 738 sci_serial_in(port, SCxSR); 739 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 740 741 return c; 742 } 743 #endif 744 745 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 746 { 747 unsigned short status; 748 749 do { 750 status = sci_serial_in(port, SCxSR); 751 } while (!(status & SCxSR_TDxE(port))); 752 753 sci_serial_out(port, SCxTDR, c); 754 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 755 } 756 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 757 CONFIG_SERIAL_SH_SCI_EARLYCON */ 758 759 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 760 { 761 struct sci_port *s = to_sci_port(port); 762 763 /* 764 * Use port-specific handler if provided. 765 */ 766 if (s->cfg->ops && s->cfg->ops->init_pins) { 767 s->cfg->ops->init_pins(port, cflag); 768 return; 769 } 770 771 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 772 u16 data = sci_serial_in(port, SCPDR); 773 u16 ctrl = sci_serial_in(port, SCPCR); 774 775 /* Enable RXD and TXD pin functions */ 776 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 777 if (to_sci_port(port)->has_rtscts) { 778 /* RTS# is output, active low, unless autorts */ 779 if (!(port->mctrl & TIOCM_RTS)) { 780 ctrl |= SCPCR_RTSC; 781 data |= SCPDR_RTSD; 782 } else if (!s->autorts) { 783 ctrl |= SCPCR_RTSC; 784 data &= ~SCPDR_RTSD; 785 } else { 786 /* Enable RTS# pin function */ 787 ctrl &= ~SCPCR_RTSC; 788 } 789 /* Enable CTS# pin function */ 790 ctrl &= ~SCPCR_CTSC; 791 } 792 sci_serial_out(port, SCPDR, data); 793 sci_serial_out(port, SCPCR, ctrl); 794 } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) { 795 u16 status = sci_serial_in(port, SCSPTR); 796 797 /* RTS# is always output; and active low, unless autorts */ 798 status |= SCSPTR_RTSIO; 799 if (!(port->mctrl & TIOCM_RTS)) 800 status |= SCSPTR_RTSDT; 801 else if (!s->autorts) 802 status &= ~SCSPTR_RTSDT; 803 /* CTS# and SCK are inputs */ 804 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 805 sci_serial_out(port, SCSPTR, status); 806 } 807 } 808 809 static int sci_txfill(struct uart_port *port) 810 { 811 struct sci_port *s = to_sci_port(port); 812 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 813 const struct plat_sci_reg *reg; 814 815 reg = sci_getreg(port, SCTFDR); 816 if (reg->size) 817 return sci_serial_in(port, SCTFDR) & fifo_mask; 818 819 reg = sci_getreg(port, SCFDR); 820 if (reg->size) 821 return sci_serial_in(port, SCFDR) >> 8; 822 823 return !(sci_serial_in(port, SCxSR) & SCI_TDRE); 824 } 825 826 static int sci_txroom(struct uart_port *port) 827 { 828 return port->fifosize - sci_txfill(port); 829 } 830 831 static int sci_rxfill(struct uart_port *port) 832 { 833 struct sci_port *s = to_sci_port(port); 834 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 835 const struct plat_sci_reg *reg; 836 837 reg = sci_getreg(port, SCRFDR); 838 if (reg->size) 839 return sci_serial_in(port, SCRFDR) & fifo_mask; 840 841 reg = sci_getreg(port, SCFDR); 842 if (reg->size) 843 return sci_serial_in(port, SCFDR) & fifo_mask; 844 845 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 846 } 847 848 /* ********************************************************************** * 849 * the interrupt related routines * 850 * ********************************************************************** */ 851 852 static void sci_transmit_chars(struct uart_port *port) 853 { 854 struct tty_port *tport = &port->state->port; 855 unsigned int stopped = uart_tx_stopped(port); 856 struct sci_port *s = to_sci_port(port); 857 unsigned short status; 858 unsigned short ctrl; 859 int count; 860 861 status = sci_serial_in(port, SCxSR); 862 if (!(status & SCxSR_TDxE(port))) { 863 ctrl = sci_serial_in(port, SCSCR); 864 if (kfifo_is_empty(&tport->xmit_fifo)) 865 ctrl &= ~SCSCR_TIE; 866 else 867 ctrl |= SCSCR_TIE; 868 sci_serial_out(port, SCSCR, ctrl); 869 return; 870 } 871 872 count = sci_txroom(port); 873 874 do { 875 unsigned char c; 876 877 if (port->x_char) { 878 c = port->x_char; 879 port->x_char = 0; 880 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { 881 if (port->type == PORT_SCI && 882 kfifo_is_empty(&tport->xmit_fifo)) { 883 ctrl = sci_serial_in(port, SCSCR); 884 ctrl &= ~SCSCR_TE; 885 sci_serial_out(port, SCSCR, ctrl); 886 return; 887 } 888 break; 889 } 890 891 sci_serial_out(port, SCxTDR, c); 892 s->tx_occurred = true; 893 894 port->icount.tx++; 895 } while (--count > 0); 896 897 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 898 899 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 900 uart_write_wakeup(port); 901 if (kfifo_is_empty(&tport->xmit_fifo)) { 902 if (port->type == PORT_SCI) { 903 ctrl = sci_serial_in(port, SCSCR); 904 ctrl &= ~SCSCR_TIE; 905 ctrl |= SCSCR_TEIE; 906 sci_serial_out(port, SCSCR, ctrl); 907 } 908 909 sci_stop_tx(port); 910 } 911 } 912 913 static void sci_receive_chars(struct uart_port *port) 914 { 915 struct tty_port *tport = &port->state->port; 916 int i, count, copied = 0; 917 unsigned short status; 918 unsigned char flag; 919 920 status = sci_serial_in(port, SCxSR); 921 if (!(status & SCxSR_RDxF(port))) 922 return; 923 924 while (1) { 925 /* Don't copy more bytes than there is room for in the buffer */ 926 count = tty_buffer_request_room(tport, sci_rxfill(port)); 927 928 /* If for any reason we can't copy more data, we're done! */ 929 if (count == 0) 930 break; 931 932 if (port->type == PORT_SCI) { 933 char c = sci_serial_in(port, SCxRDR); 934 if (uart_handle_sysrq_char(port, c)) 935 count = 0; 936 else 937 tty_insert_flip_char(tport, c, TTY_NORMAL); 938 } else { 939 for (i = 0; i < count; i++) { 940 char c; 941 942 if (port->type == PORT_SCIF || 943 port->type == PORT_HSCIF) { 944 status = sci_serial_in(port, SCxSR); 945 c = sci_serial_in(port, SCxRDR); 946 } else { 947 c = sci_serial_in(port, SCxRDR); 948 status = sci_serial_in(port, SCxSR); 949 } 950 if (uart_handle_sysrq_char(port, c)) { 951 count--; i--; 952 continue; 953 } 954 955 /* Store data and status */ 956 if (status & SCxSR_FER(port)) { 957 flag = TTY_FRAME; 958 port->icount.frame++; 959 } else if (status & SCxSR_PER(port)) { 960 flag = TTY_PARITY; 961 port->icount.parity++; 962 } else 963 flag = TTY_NORMAL; 964 965 tty_insert_flip_char(tport, c, flag); 966 } 967 } 968 969 sci_serial_in(port, SCxSR); /* dummy read */ 970 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 971 972 copied += count; 973 port->icount.rx += count; 974 } 975 976 if (copied) { 977 /* Tell the rest of the system the news. New characters! */ 978 tty_flip_buffer_push(tport); 979 } else { 980 /* TTY buffers full; read from RX reg to prevent lockup */ 981 sci_serial_in(port, SCxRDR); 982 sci_serial_in(port, SCxSR); /* dummy read */ 983 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 984 } 985 } 986 987 static int sci_handle_errors(struct uart_port *port) 988 { 989 int copied = 0; 990 unsigned short status = sci_serial_in(port, SCxSR); 991 struct tty_port *tport = &port->state->port; 992 struct sci_port *s = to_sci_port(port); 993 994 /* Handle overruns */ 995 if (status & s->params->overrun_mask) { 996 port->icount.overrun++; 997 998 /* overrun error */ 999 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 1000 copied++; 1001 } 1002 1003 if (status & SCxSR_FER(port)) { 1004 /* frame error */ 1005 port->icount.frame++; 1006 1007 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 1008 copied++; 1009 } 1010 1011 if (status & SCxSR_PER(port)) { 1012 /* parity error */ 1013 port->icount.parity++; 1014 1015 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 1016 copied++; 1017 } 1018 1019 if (copied) 1020 tty_flip_buffer_push(tport); 1021 1022 return copied; 1023 } 1024 1025 static int sci_handle_fifo_overrun(struct uart_port *port) 1026 { 1027 struct tty_port *tport = &port->state->port; 1028 struct sci_port *s = to_sci_port(port); 1029 const struct plat_sci_reg *reg; 1030 int copied = 0; 1031 u16 status; 1032 1033 reg = sci_getreg(port, s->params->overrun_reg); 1034 if (!reg->size) 1035 return 0; 1036 1037 status = sci_serial_in(port, s->params->overrun_reg); 1038 if (status & s->params->overrun_mask) { 1039 status &= ~s->params->overrun_mask; 1040 sci_serial_out(port, s->params->overrun_reg, status); 1041 1042 port->icount.overrun++; 1043 1044 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1045 tty_flip_buffer_push(tport); 1046 copied++; 1047 } 1048 1049 return copied; 1050 } 1051 1052 static int sci_handle_breaks(struct uart_port *port) 1053 { 1054 int copied = 0; 1055 unsigned short status = sci_serial_in(port, SCxSR); 1056 struct tty_port *tport = &port->state->port; 1057 1058 if (uart_handle_break(port)) 1059 return 0; 1060 1061 if (status & SCxSR_BRK(port)) { 1062 port->icount.brk++; 1063 1064 /* Notify of BREAK */ 1065 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1066 copied++; 1067 } 1068 1069 if (copied) 1070 tty_flip_buffer_push(tport); 1071 1072 copied += sci_handle_fifo_overrun(port); 1073 1074 return copied; 1075 } 1076 1077 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1078 { 1079 unsigned int bits; 1080 1081 if (rx_trig >= port->fifosize) 1082 rx_trig = port->fifosize - 1; 1083 if (rx_trig < 1) 1084 rx_trig = 1; 1085 1086 /* HSCIF can be set to an arbitrary level. */ 1087 if (sci_getreg(port, HSRTRGR)->size) { 1088 sci_serial_out(port, HSRTRGR, rx_trig); 1089 return rx_trig; 1090 } 1091 1092 switch (port->type) { 1093 case PORT_SCIF: 1094 if (rx_trig < 4) { 1095 bits = 0; 1096 rx_trig = 1; 1097 } else if (rx_trig < 8) { 1098 bits = SCFCR_RTRG0; 1099 rx_trig = 4; 1100 } else if (rx_trig < 14) { 1101 bits = SCFCR_RTRG1; 1102 rx_trig = 8; 1103 } else { 1104 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1105 rx_trig = 14; 1106 } 1107 break; 1108 case PORT_SCIFA: 1109 case PORT_SCIFB: 1110 if (rx_trig < 16) { 1111 bits = 0; 1112 rx_trig = 1; 1113 } else if (rx_trig < 32) { 1114 bits = SCFCR_RTRG0; 1115 rx_trig = 16; 1116 } else if (rx_trig < 48) { 1117 bits = SCFCR_RTRG1; 1118 rx_trig = 32; 1119 } else { 1120 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1121 rx_trig = 48; 1122 } 1123 break; 1124 default: 1125 WARN(1, "unknown FIFO configuration"); 1126 return 1; 1127 } 1128 1129 sci_serial_out(port, SCFCR, 1130 (sci_serial_in(port, SCFCR) & 1131 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1132 1133 return rx_trig; 1134 } 1135 1136 static int scif_rtrg_enabled(struct uart_port *port) 1137 { 1138 if (sci_getreg(port, HSRTRGR)->size) 1139 return sci_serial_in(port, HSRTRGR) != 0; 1140 else 1141 return (sci_serial_in(port, SCFCR) & 1142 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1143 } 1144 1145 static void rx_fifo_timer_fn(struct timer_list *t) 1146 { 1147 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1148 struct uart_port *port = &s->port; 1149 1150 dev_dbg(port->dev, "Rx timed out\n"); 1151 scif_set_rtrg(port, 1); 1152 } 1153 1154 static ssize_t rx_fifo_trigger_show(struct device *dev, 1155 struct device_attribute *attr, char *buf) 1156 { 1157 struct uart_port *port = dev_get_drvdata(dev); 1158 struct sci_port *sci = to_sci_port(port); 1159 1160 return sprintf(buf, "%d\n", sci->rx_trigger); 1161 } 1162 1163 static ssize_t rx_fifo_trigger_store(struct device *dev, 1164 struct device_attribute *attr, 1165 const char *buf, size_t count) 1166 { 1167 struct uart_port *port = dev_get_drvdata(dev); 1168 struct sci_port *sci = to_sci_port(port); 1169 int ret; 1170 long r; 1171 1172 ret = kstrtol(buf, 0, &r); 1173 if (ret) 1174 return ret; 1175 1176 sci->rx_trigger = scif_set_rtrg(port, r); 1177 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1178 scif_set_rtrg(port, 1); 1179 1180 return count; 1181 } 1182 1183 static DEVICE_ATTR_RW(rx_fifo_trigger); 1184 1185 static ssize_t rx_fifo_timeout_show(struct device *dev, 1186 struct device_attribute *attr, 1187 char *buf) 1188 { 1189 struct uart_port *port = dev_get_drvdata(dev); 1190 struct sci_port *sci = to_sci_port(port); 1191 int v; 1192 1193 if (port->type == PORT_HSCIF) 1194 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1195 else 1196 v = sci->rx_fifo_timeout; 1197 1198 return sprintf(buf, "%d\n", v); 1199 } 1200 1201 static ssize_t rx_fifo_timeout_store(struct device *dev, 1202 struct device_attribute *attr, 1203 const char *buf, 1204 size_t count) 1205 { 1206 struct uart_port *port = dev_get_drvdata(dev); 1207 struct sci_port *sci = to_sci_port(port); 1208 int ret; 1209 long r; 1210 1211 ret = kstrtol(buf, 0, &r); 1212 if (ret) 1213 return ret; 1214 1215 if (port->type == PORT_HSCIF) { 1216 if (r < 0 || r > 3) 1217 return -EINVAL; 1218 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1219 } else { 1220 sci->rx_fifo_timeout = r; 1221 scif_set_rtrg(port, 1); 1222 if (r > 0) 1223 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1224 } 1225 1226 return count; 1227 } 1228 1229 static DEVICE_ATTR_RW(rx_fifo_timeout); 1230 1231 1232 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1233 static void sci_dma_tx_complete(void *arg) 1234 { 1235 struct sci_port *s = arg; 1236 struct uart_port *port = &s->port; 1237 struct tty_port *tport = &port->state->port; 1238 unsigned long flags; 1239 1240 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1241 1242 uart_port_lock_irqsave(port, &flags); 1243 1244 uart_xmit_advance(port, s->tx_dma_len); 1245 1246 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1247 uart_write_wakeup(port); 1248 1249 s->tx_occurred = true; 1250 1251 if (!kfifo_is_empty(&tport->xmit_fifo)) { 1252 s->cookie_tx = 0; 1253 schedule_work(&s->work_tx); 1254 } else { 1255 s->cookie_tx = -EINVAL; 1256 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1257 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1258 u16 ctrl = sci_serial_in(port, SCSCR); 1259 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1260 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1261 /* Switch irq from DMA to SCIF */ 1262 dmaengine_pause(s->chan_tx_saved); 1263 enable_irq(s->irqs[SCIx_TXI_IRQ]); 1264 } 1265 } 1266 } 1267 1268 uart_port_unlock_irqrestore(port, flags); 1269 } 1270 1271 /* Locking: called with port lock held */ 1272 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1273 { 1274 struct uart_port *port = &s->port; 1275 struct tty_port *tport = &port->state->port; 1276 int copied; 1277 1278 copied = tty_insert_flip_string(tport, buf, count); 1279 if (copied < count) 1280 port->icount.buf_overrun++; 1281 1282 port->icount.rx += copied; 1283 1284 return copied; 1285 } 1286 1287 static int sci_dma_rx_find_active(struct sci_port *s) 1288 { 1289 unsigned int i; 1290 1291 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1292 if (s->active_rx == s->cookie_rx[i]) 1293 return i; 1294 1295 return -1; 1296 } 1297 1298 /* Must only be called with uart_port_lock taken */ 1299 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1300 { 1301 unsigned int i; 1302 1303 s->chan_rx = NULL; 1304 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1305 s->cookie_rx[i] = -EINVAL; 1306 s->active_rx = 0; 1307 } 1308 1309 static void sci_dma_rx_release(struct sci_port *s) 1310 { 1311 struct dma_chan *chan = s->chan_rx_saved; 1312 struct uart_port *port = &s->port; 1313 unsigned long flags; 1314 1315 uart_port_lock_irqsave(port, &flags); 1316 s->chan_rx_saved = NULL; 1317 sci_dma_rx_chan_invalidate(s); 1318 uart_port_unlock_irqrestore(port, flags); 1319 1320 dmaengine_terminate_sync(chan); 1321 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1322 sg_dma_address(&s->sg_rx[0])); 1323 dma_release_channel(chan); 1324 } 1325 1326 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1327 { 1328 long sec = usec / 1000000; 1329 long nsec = (usec % 1000000) * 1000; 1330 ktime_t t = ktime_set(sec, nsec); 1331 1332 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1333 } 1334 1335 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1336 { 1337 struct uart_port *port = &s->port; 1338 u16 scr; 1339 1340 /* Direct new serial port interrupts back to CPU */ 1341 scr = sci_serial_in(port, SCSCR); 1342 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1343 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1344 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1345 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1346 scif_set_rtrg(port, s->rx_trigger); 1347 else 1348 scr &= ~SCSCR_RDRQE; 1349 } 1350 sci_serial_out(port, SCSCR, scr | SCSCR_RIE); 1351 } 1352 1353 static void sci_dma_rx_complete(void *arg) 1354 { 1355 struct sci_port *s = arg; 1356 struct dma_chan *chan = s->chan_rx; 1357 struct uart_port *port = &s->port; 1358 struct dma_async_tx_descriptor *desc; 1359 unsigned long flags; 1360 int active, count = 0; 1361 1362 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1363 s->active_rx); 1364 1365 hrtimer_cancel(&s->rx_timer); 1366 1367 uart_port_lock_irqsave(port, &flags); 1368 1369 active = sci_dma_rx_find_active(s); 1370 if (active >= 0) 1371 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1372 1373 if (count) 1374 tty_flip_buffer_push(&port->state->port); 1375 1376 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1377 DMA_DEV_TO_MEM, 1378 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1379 if (!desc) 1380 goto fail; 1381 1382 desc->callback = sci_dma_rx_complete; 1383 desc->callback_param = s; 1384 s->cookie_rx[active] = dmaengine_submit(desc); 1385 if (dma_submit_error(s->cookie_rx[active])) 1386 goto fail; 1387 1388 s->active_rx = s->cookie_rx[!active]; 1389 1390 dma_async_issue_pending(chan); 1391 1392 uart_port_unlock_irqrestore(port, flags); 1393 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1394 __func__, s->cookie_rx[active], active, s->active_rx); 1395 1396 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1397 1398 return; 1399 1400 fail: 1401 /* Switch to PIO */ 1402 dmaengine_terminate_async(chan); 1403 sci_dma_rx_chan_invalidate(s); 1404 sci_dma_rx_reenable_irq(s); 1405 uart_port_unlock_irqrestore(port, flags); 1406 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1407 } 1408 1409 static void sci_dma_tx_release(struct sci_port *s) 1410 { 1411 struct dma_chan *chan = s->chan_tx_saved; 1412 1413 cancel_work_sync(&s->work_tx); 1414 s->chan_tx_saved = s->chan_tx = NULL; 1415 s->cookie_tx = -EINVAL; 1416 dmaengine_terminate_sync(chan); 1417 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1418 DMA_TO_DEVICE); 1419 dma_release_channel(chan); 1420 } 1421 1422 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1423 { 1424 struct dma_chan *chan = s->chan_rx; 1425 struct uart_port *port = &s->port; 1426 unsigned long flags; 1427 int i; 1428 1429 for (i = 0; i < 2; i++) { 1430 struct scatterlist *sg = &s->sg_rx[i]; 1431 struct dma_async_tx_descriptor *desc; 1432 1433 desc = dmaengine_prep_slave_sg(chan, 1434 sg, 1, DMA_DEV_TO_MEM, 1435 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1436 if (!desc) 1437 goto fail; 1438 1439 desc->callback = sci_dma_rx_complete; 1440 desc->callback_param = s; 1441 s->cookie_rx[i] = dmaengine_submit(desc); 1442 if (dma_submit_error(s->cookie_rx[i])) 1443 goto fail; 1444 1445 } 1446 1447 s->active_rx = s->cookie_rx[0]; 1448 1449 dma_async_issue_pending(chan); 1450 return 0; 1451 1452 fail: 1453 /* Switch to PIO */ 1454 if (!port_lock_held) 1455 uart_port_lock_irqsave(port, &flags); 1456 if (i) 1457 dmaengine_terminate_async(chan); 1458 sci_dma_rx_chan_invalidate(s); 1459 sci_start_rx(port); 1460 if (!port_lock_held) 1461 uart_port_unlock_irqrestore(port, flags); 1462 return -EAGAIN; 1463 } 1464 1465 static void sci_dma_tx_work_fn(struct work_struct *work) 1466 { 1467 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1468 struct dma_async_tx_descriptor *desc; 1469 struct dma_chan *chan = s->chan_tx; 1470 struct uart_port *port = &s->port; 1471 struct tty_port *tport = &port->state->port; 1472 unsigned long flags; 1473 unsigned int tail; 1474 dma_addr_t buf; 1475 1476 /* 1477 * DMA is idle now. 1478 * Port xmit buffer is already mapped, and it is one page... Just adjust 1479 * offsets and lengths. Since it is a circular buffer, we have to 1480 * transmit till the end, and then the rest. Take the port lock to get a 1481 * consistent xmit buffer state. 1482 */ 1483 uart_port_lock_irq(port); 1484 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail, 1485 UART_XMIT_SIZE); 1486 buf = s->tx_dma_addr + tail; 1487 if (!s->tx_dma_len) { 1488 /* Transmit buffer has been flushed */ 1489 uart_port_unlock_irq(port); 1490 return; 1491 } 1492 1493 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1494 DMA_MEM_TO_DEV, 1495 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1496 if (!desc) { 1497 uart_port_unlock_irq(port); 1498 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1499 goto switch_to_pio; 1500 } 1501 1502 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1503 DMA_TO_DEVICE); 1504 1505 desc->callback = sci_dma_tx_complete; 1506 desc->callback_param = s; 1507 s->cookie_tx = dmaengine_submit(desc); 1508 if (dma_submit_error(s->cookie_tx)) { 1509 uart_port_unlock_irq(port); 1510 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1511 goto switch_to_pio; 1512 } 1513 1514 uart_port_unlock_irq(port); 1515 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n", 1516 __func__, tport->xmit_buf, tail, s->cookie_tx); 1517 1518 dma_async_issue_pending(chan); 1519 return; 1520 1521 switch_to_pio: 1522 uart_port_lock_irqsave(port, &flags); 1523 s->chan_tx = NULL; 1524 sci_start_tx(port); 1525 uart_port_unlock_irqrestore(port, flags); 1526 return; 1527 } 1528 1529 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1530 { 1531 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1532 struct dma_chan *chan = s->chan_rx; 1533 struct uart_port *port = &s->port; 1534 struct dma_tx_state state; 1535 enum dma_status status; 1536 unsigned long flags; 1537 unsigned int read; 1538 int active, count; 1539 1540 dev_dbg(port->dev, "DMA Rx timed out\n"); 1541 1542 uart_port_lock_irqsave(port, &flags); 1543 1544 active = sci_dma_rx_find_active(s); 1545 if (active < 0) { 1546 uart_port_unlock_irqrestore(port, flags); 1547 return HRTIMER_NORESTART; 1548 } 1549 1550 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1551 if (status == DMA_COMPLETE) { 1552 uart_port_unlock_irqrestore(port, flags); 1553 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1554 s->active_rx, active); 1555 1556 /* Let packet complete handler take care of the packet */ 1557 return HRTIMER_NORESTART; 1558 } 1559 1560 dmaengine_pause(chan); 1561 1562 /* 1563 * sometimes DMA transfer doesn't stop even if it is stopped and 1564 * data keeps on coming until transaction is complete so check 1565 * for DMA_COMPLETE again 1566 * Let packet complete handler take care of the packet 1567 */ 1568 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1569 if (status == DMA_COMPLETE) { 1570 uart_port_unlock_irqrestore(port, flags); 1571 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1572 return HRTIMER_NORESTART; 1573 } 1574 1575 /* Handle incomplete DMA receive */ 1576 dmaengine_terminate_async(s->chan_rx); 1577 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1578 1579 if (read) { 1580 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1581 if (count) 1582 tty_flip_buffer_push(&port->state->port); 1583 } 1584 1585 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1586 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1587 sci_dma_rx_submit(s, true); 1588 1589 sci_dma_rx_reenable_irq(s); 1590 1591 uart_port_unlock_irqrestore(port, flags); 1592 1593 return HRTIMER_NORESTART; 1594 } 1595 1596 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1597 enum dma_transfer_direction dir) 1598 { 1599 struct dma_chan *chan; 1600 struct dma_slave_config cfg; 1601 int ret; 1602 1603 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1604 if (IS_ERR(chan)) { 1605 dev_dbg(port->dev, "dma_request_chan failed\n"); 1606 return NULL; 1607 } 1608 1609 memset(&cfg, 0, sizeof(cfg)); 1610 cfg.direction = dir; 1611 cfg.dst_addr = port->mapbase + 1612 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1613 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1614 cfg.src_addr = port->mapbase + 1615 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1616 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1617 1618 ret = dmaengine_slave_config(chan, &cfg); 1619 if (ret) { 1620 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1621 dma_release_channel(chan); 1622 return NULL; 1623 } 1624 1625 return chan; 1626 } 1627 1628 static void sci_request_dma(struct uart_port *port) 1629 { 1630 struct sci_port *s = to_sci_port(port); 1631 struct tty_port *tport = &port->state->port; 1632 struct dma_chan *chan; 1633 1634 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1635 1636 /* 1637 * DMA on console may interfere with Kernel log messages which use 1638 * plain putchar(). So, simply don't use it with a console. 1639 */ 1640 if (uart_console(port)) 1641 return; 1642 1643 if (!port->dev->of_node) 1644 return; 1645 1646 s->cookie_tx = -EINVAL; 1647 1648 /* 1649 * Don't request a dma channel if no channel was specified 1650 * in the device tree. 1651 */ 1652 if (!of_property_present(port->dev->of_node, "dmas")) 1653 return; 1654 1655 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1656 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1657 if (chan) { 1658 /* UART circular tx buffer is an aligned page. */ 1659 s->tx_dma_addr = dma_map_single(chan->device->dev, 1660 tport->xmit_buf, 1661 UART_XMIT_SIZE, 1662 DMA_TO_DEVICE); 1663 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1664 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1665 dma_release_channel(chan); 1666 } else { 1667 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1668 __func__, UART_XMIT_SIZE, 1669 tport->xmit_buf, &s->tx_dma_addr); 1670 1671 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1672 s->chan_tx_saved = s->chan_tx = chan; 1673 } 1674 } 1675 1676 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1677 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1678 if (chan) { 1679 unsigned int i; 1680 dma_addr_t dma; 1681 void *buf; 1682 1683 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1684 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1685 &dma, GFP_KERNEL); 1686 if (!buf) { 1687 dev_warn(port->dev, 1688 "Failed to allocate Rx dma buffer, using PIO\n"); 1689 dma_release_channel(chan); 1690 return; 1691 } 1692 1693 for (i = 0; i < 2; i++) { 1694 struct scatterlist *sg = &s->sg_rx[i]; 1695 1696 sg_init_table(sg, 1); 1697 s->rx_buf[i] = buf; 1698 sg_dma_address(sg) = dma; 1699 sg_dma_len(sg) = s->buf_len_rx; 1700 1701 buf += s->buf_len_rx; 1702 dma += s->buf_len_rx; 1703 } 1704 1705 hrtimer_setup(&s->rx_timer, sci_dma_rx_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1706 1707 s->chan_rx_saved = s->chan_rx = chan; 1708 1709 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1710 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1711 sci_dma_rx_submit(s, false); 1712 } 1713 } 1714 1715 static void sci_free_dma(struct uart_port *port) 1716 { 1717 struct sci_port *s = to_sci_port(port); 1718 1719 if (s->chan_tx_saved) 1720 sci_dma_tx_release(s); 1721 if (s->chan_rx_saved) 1722 sci_dma_rx_release(s); 1723 } 1724 1725 static void sci_flush_buffer(struct uart_port *port) 1726 { 1727 struct sci_port *s = to_sci_port(port); 1728 1729 /* 1730 * In uart_flush_buffer(), the xmit circular buffer has just been 1731 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1732 * pending transfers 1733 */ 1734 s->tx_dma_len = 0; 1735 if (s->chan_tx) { 1736 dmaengine_terminate_async(s->chan_tx); 1737 s->cookie_tx = -EINVAL; 1738 } 1739 } 1740 1741 static void sci_dma_check_tx_occurred(struct sci_port *s) 1742 { 1743 struct dma_tx_state state; 1744 enum dma_status status; 1745 1746 if (!s->chan_tx) 1747 return; 1748 1749 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state); 1750 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS) 1751 s->tx_occurred = true; 1752 } 1753 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1754 static inline void sci_request_dma(struct uart_port *port) 1755 { 1756 } 1757 1758 static inline void sci_free_dma(struct uart_port *port) 1759 { 1760 } 1761 1762 static void sci_dma_check_tx_occurred(struct sci_port *s) 1763 { 1764 } 1765 1766 #define sci_flush_buffer NULL 1767 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1768 1769 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1770 { 1771 struct uart_port *port = ptr; 1772 struct sci_port *s = to_sci_port(port); 1773 1774 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1775 if (s->chan_rx) { 1776 u16 scr = sci_serial_in(port, SCSCR); 1777 u16 ssr = sci_serial_in(port, SCxSR); 1778 1779 /* Disable future Rx interrupts */ 1780 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1781 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1782 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); 1783 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1784 scif_set_rtrg(port, 1); 1785 scr |= SCSCR_RIE; 1786 } else { 1787 scr |= SCSCR_RDRQE; 1788 } 1789 } else { 1790 if (sci_dma_rx_submit(s, false) < 0) 1791 goto handle_pio; 1792 1793 scr &= ~SCSCR_RIE; 1794 } 1795 sci_serial_out(port, SCSCR, scr); 1796 /* Clear current interrupt */ 1797 sci_serial_out(port, SCxSR, 1798 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1799 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1800 jiffies, s->rx_timeout); 1801 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1802 1803 return IRQ_HANDLED; 1804 } 1805 1806 handle_pio: 1807 #endif 1808 1809 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1810 if (!scif_rtrg_enabled(port)) 1811 scif_set_rtrg(port, s->rx_trigger); 1812 1813 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1814 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1815 } 1816 1817 /* I think sci_receive_chars has to be called irrespective 1818 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1819 * to be disabled? 1820 */ 1821 sci_receive_chars(port); 1822 1823 return IRQ_HANDLED; 1824 } 1825 1826 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1827 { 1828 struct uart_port *port = ptr; 1829 unsigned long flags; 1830 1831 uart_port_lock_irqsave(port, &flags); 1832 sci_transmit_chars(port); 1833 uart_port_unlock_irqrestore(port, flags); 1834 1835 return IRQ_HANDLED; 1836 } 1837 1838 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) 1839 { 1840 struct uart_port *port = ptr; 1841 unsigned long flags; 1842 unsigned short ctrl; 1843 1844 if (port->type != PORT_SCI) 1845 return sci_tx_interrupt(irq, ptr); 1846 1847 uart_port_lock_irqsave(port, &flags); 1848 ctrl = sci_serial_in(port, SCSCR); 1849 ctrl &= ~(SCSCR_TE | SCSCR_TEIE); 1850 sci_serial_out(port, SCSCR, ctrl); 1851 uart_port_unlock_irqrestore(port, flags); 1852 1853 return IRQ_HANDLED; 1854 } 1855 1856 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1857 { 1858 struct uart_port *port = ptr; 1859 1860 /* Handle BREAKs */ 1861 sci_handle_breaks(port); 1862 1863 /* drop invalid character received before break was detected */ 1864 sci_serial_in(port, SCxRDR); 1865 1866 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1867 1868 return IRQ_HANDLED; 1869 } 1870 1871 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1872 { 1873 struct uart_port *port = ptr; 1874 struct sci_port *s = to_sci_port(port); 1875 1876 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1877 /* Break and Error interrupts are muxed */ 1878 unsigned short ssr_status = sci_serial_in(port, SCxSR); 1879 1880 /* Break Interrupt */ 1881 if (ssr_status & SCxSR_BRK(port)) 1882 sci_br_interrupt(irq, ptr); 1883 1884 /* Break only? */ 1885 if (!(ssr_status & SCxSR_ERRORS(port))) 1886 return IRQ_HANDLED; 1887 } 1888 1889 /* Handle errors */ 1890 if (port->type == PORT_SCI) { 1891 if (sci_handle_errors(port)) { 1892 /* discard character in rx buffer */ 1893 sci_serial_in(port, SCxSR); 1894 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1895 } 1896 } else { 1897 sci_handle_fifo_overrun(port); 1898 if (!s->chan_rx) 1899 sci_receive_chars(port); 1900 } 1901 1902 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1903 1904 /* Kick the transmission */ 1905 if (!s->chan_tx) 1906 sci_tx_interrupt(irq, ptr); 1907 1908 return IRQ_HANDLED; 1909 } 1910 1911 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1912 { 1913 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1914 struct uart_port *port = ptr; 1915 struct sci_port *s = to_sci_port(port); 1916 irqreturn_t ret = IRQ_NONE; 1917 1918 ssr_status = sci_serial_in(port, SCxSR); 1919 scr_status = sci_serial_in(port, SCSCR); 1920 if (s->params->overrun_reg == SCxSR) 1921 orer_status = ssr_status; 1922 else if (sci_getreg(port, s->params->overrun_reg)->size) 1923 orer_status = sci_serial_in(port, s->params->overrun_reg); 1924 1925 err_enabled = scr_status & port_rx_irq_mask(port); 1926 1927 /* Tx Interrupt */ 1928 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1929 !s->chan_tx) 1930 ret = sci_tx_interrupt(irq, ptr); 1931 1932 /* 1933 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1934 * DR flags 1935 */ 1936 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1937 (scr_status & SCSCR_RIE)) 1938 ret = sci_rx_interrupt(irq, ptr); 1939 1940 /* Error Interrupt */ 1941 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1942 ret = sci_er_interrupt(irq, ptr); 1943 1944 /* Break Interrupt */ 1945 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 1946 (ssr_status & SCxSR_BRK(port)) && err_enabled) 1947 ret = sci_br_interrupt(irq, ptr); 1948 1949 /* Overrun Interrupt */ 1950 if (orer_status & s->params->overrun_mask) { 1951 sci_handle_fifo_overrun(port); 1952 ret = IRQ_HANDLED; 1953 } 1954 1955 return ret; 1956 } 1957 1958 static const struct sci_irq_desc { 1959 const char *desc; 1960 irq_handler_t handler; 1961 } sci_irq_desc[] = { 1962 /* 1963 * Split out handlers, the default case. 1964 */ 1965 [SCIx_ERI_IRQ] = { 1966 .desc = "rx err", 1967 .handler = sci_er_interrupt, 1968 }, 1969 1970 [SCIx_RXI_IRQ] = { 1971 .desc = "rx full", 1972 .handler = sci_rx_interrupt, 1973 }, 1974 1975 [SCIx_TXI_IRQ] = { 1976 .desc = "tx empty", 1977 .handler = sci_tx_interrupt, 1978 }, 1979 1980 [SCIx_BRI_IRQ] = { 1981 .desc = "break", 1982 .handler = sci_br_interrupt, 1983 }, 1984 1985 [SCIx_DRI_IRQ] = { 1986 .desc = "rx ready", 1987 .handler = sci_rx_interrupt, 1988 }, 1989 1990 [SCIx_TEI_IRQ] = { 1991 .desc = "tx end", 1992 .handler = sci_tx_end_interrupt, 1993 }, 1994 1995 /* 1996 * Special muxed handler. 1997 */ 1998 [SCIx_MUX_IRQ] = { 1999 .desc = "mux", 2000 .handler = sci_mpxed_interrupt, 2001 }, 2002 }; 2003 2004 static int sci_request_irq(struct sci_port *port) 2005 { 2006 struct uart_port *up = &port->port; 2007 int i, j, w, ret = 0; 2008 2009 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 2010 const struct sci_irq_desc *desc; 2011 int irq; 2012 2013 /* Check if already registered (muxed) */ 2014 for (w = 0; w < i; w++) 2015 if (port->irqs[w] == port->irqs[i]) 2016 w = i + 1; 2017 if (w > i) 2018 continue; 2019 2020 if (SCIx_IRQ_IS_MUXED(port)) { 2021 i = SCIx_MUX_IRQ; 2022 irq = up->irq; 2023 } else { 2024 irq = port->irqs[i]; 2025 2026 /* 2027 * Certain port types won't support all of the 2028 * available interrupt sources. 2029 */ 2030 if (unlikely(irq < 0)) 2031 continue; 2032 } 2033 2034 desc = sci_irq_desc + i; 2035 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 2036 dev_name(up->dev), desc->desc); 2037 if (!port->irqstr[j]) { 2038 ret = -ENOMEM; 2039 goto out_nomem; 2040 } 2041 2042 ret = request_irq(irq, desc->handler, up->irqflags, 2043 port->irqstr[j], port); 2044 if (unlikely(ret)) { 2045 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 2046 goto out_noirq; 2047 } 2048 } 2049 2050 return 0; 2051 2052 out_noirq: 2053 while (--i >= 0) 2054 free_irq(port->irqs[i], port); 2055 2056 out_nomem: 2057 while (--j >= 0) 2058 kfree(port->irqstr[j]); 2059 2060 return ret; 2061 } 2062 2063 static void sci_free_irq(struct sci_port *port) 2064 { 2065 int i, j; 2066 2067 /* 2068 * Intentionally in reverse order so we iterate over the muxed 2069 * IRQ first. 2070 */ 2071 for (i = 0; i < SCIx_NR_IRQS; i++) { 2072 int irq = port->irqs[i]; 2073 2074 /* 2075 * Certain port types won't support all of the available 2076 * interrupt sources. 2077 */ 2078 if (unlikely(irq < 0)) 2079 continue; 2080 2081 /* Check if already freed (irq was muxed) */ 2082 for (j = 0; j < i; j++) 2083 if (port->irqs[j] == irq) 2084 j = i + 1; 2085 if (j > i) 2086 continue; 2087 2088 free_irq(port->irqs[i], port); 2089 kfree(port->irqstr[i]); 2090 2091 if (SCIx_IRQ_IS_MUXED(port)) { 2092 /* If there's only one IRQ, we're done. */ 2093 return; 2094 } 2095 } 2096 } 2097 2098 static unsigned int sci_tx_empty(struct uart_port *port) 2099 { 2100 unsigned short status = sci_serial_in(port, SCxSR); 2101 unsigned short in_tx_fifo = sci_txfill(port); 2102 struct sci_port *s = to_sci_port(port); 2103 2104 sci_dma_check_tx_occurred(s); 2105 2106 if (!s->tx_occurred) 2107 return TIOCSER_TEMT; 2108 2109 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 2110 } 2111 2112 static void sci_set_rts(struct uart_port *port, bool state) 2113 { 2114 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2115 u16 data = sci_serial_in(port, SCPDR); 2116 2117 /* Active low */ 2118 if (state) 2119 data &= ~SCPDR_RTSD; 2120 else 2121 data |= SCPDR_RTSD; 2122 sci_serial_out(port, SCPDR, data); 2123 2124 /* RTS# is output */ 2125 sci_serial_out(port, SCPCR, 2126 sci_serial_in(port, SCPCR) | SCPCR_RTSC); 2127 } else if (sci_getreg(port, SCSPTR)->size) { 2128 u16 ctrl = sci_serial_in(port, SCSPTR); 2129 2130 /* Active low */ 2131 if (state) 2132 ctrl &= ~SCSPTR_RTSDT; 2133 else 2134 ctrl |= SCSPTR_RTSDT; 2135 sci_serial_out(port, SCSPTR, ctrl); 2136 } 2137 } 2138 2139 static bool sci_get_cts(struct uart_port *port) 2140 { 2141 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2142 /* Active low */ 2143 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD); 2144 } else if (sci_getreg(port, SCSPTR)->size) { 2145 /* Active low */ 2146 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT); 2147 } 2148 2149 return true; 2150 } 2151 2152 /* 2153 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2154 * CTS/RTS is supported in hardware by at least one port and controlled 2155 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2156 * handled via the ->init_pins() op, which is a bit of a one-way street, 2157 * lacking any ability to defer pin control -- this will later be 2158 * converted over to the GPIO framework). 2159 * 2160 * Other modes (such as loopback) are supported generically on certain 2161 * port types, but not others. For these it's sufficient to test for the 2162 * existence of the support register and simply ignore the port type. 2163 */ 2164 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2165 { 2166 struct sci_port *s = to_sci_port(port); 2167 2168 if (mctrl & TIOCM_LOOP) { 2169 const struct plat_sci_reg *reg; 2170 2171 /* 2172 * Standard loopback mode for SCFCR ports. 2173 */ 2174 reg = sci_getreg(port, SCFCR); 2175 if (reg->size) 2176 sci_serial_out(port, SCFCR, 2177 sci_serial_in(port, SCFCR) | SCFCR_LOOP); 2178 } 2179 2180 mctrl_gpio_set(s->gpios, mctrl); 2181 2182 if (!s->has_rtscts) 2183 return; 2184 2185 if (!(mctrl & TIOCM_RTS)) { 2186 /* Disable Auto RTS */ 2187 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2188 sci_serial_out(port, SCFCR, 2189 sci_serial_in(port, SCFCR) & ~SCFCR_MCE); 2190 2191 /* Clear RTS */ 2192 sci_set_rts(port, 0); 2193 } else if (s->autorts) { 2194 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2195 /* Enable RTS# pin function */ 2196 sci_serial_out(port, SCPCR, 2197 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC); 2198 } 2199 2200 /* Enable Auto RTS */ 2201 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2202 sci_serial_out(port, SCFCR, 2203 sci_serial_in(port, SCFCR) | SCFCR_MCE); 2204 } else { 2205 /* Set RTS */ 2206 sci_set_rts(port, 1); 2207 } 2208 } 2209 2210 static unsigned int sci_get_mctrl(struct uart_port *port) 2211 { 2212 struct sci_port *s = to_sci_port(port); 2213 struct mctrl_gpios *gpios = s->gpios; 2214 unsigned int mctrl = 0; 2215 2216 mctrl_gpio_get(gpios, &mctrl); 2217 2218 /* 2219 * CTS/RTS is handled in hardware when supported, while nothing 2220 * else is wired up. 2221 */ 2222 if (s->autorts) { 2223 if (sci_get_cts(port)) 2224 mctrl |= TIOCM_CTS; 2225 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2226 mctrl |= TIOCM_CTS; 2227 } 2228 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2229 mctrl |= TIOCM_DSR; 2230 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2231 mctrl |= TIOCM_CAR; 2232 2233 return mctrl; 2234 } 2235 2236 static void sci_enable_ms(struct uart_port *port) 2237 { 2238 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2239 } 2240 2241 static void sci_break_ctl(struct uart_port *port, int break_state) 2242 { 2243 unsigned short scscr, scsptr; 2244 unsigned long flags; 2245 2246 /* check whether the port has SCSPTR */ 2247 if (!sci_getreg(port, SCSPTR)->size) { 2248 /* 2249 * Not supported by hardware. Most parts couple break and rx 2250 * interrupts together, with break detection always enabled. 2251 */ 2252 return; 2253 } 2254 2255 uart_port_lock_irqsave(port, &flags); 2256 scsptr = sci_serial_in(port, SCSPTR); 2257 scscr = sci_serial_in(port, SCSCR); 2258 2259 if (break_state == -1) { 2260 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2261 scscr &= ~SCSCR_TE; 2262 } else { 2263 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2264 scscr |= SCSCR_TE; 2265 } 2266 2267 sci_serial_out(port, SCSPTR, scsptr); 2268 sci_serial_out(port, SCSCR, scscr); 2269 uart_port_unlock_irqrestore(port, flags); 2270 } 2271 2272 static int sci_startup(struct uart_port *port) 2273 { 2274 struct sci_port *s = to_sci_port(port); 2275 int ret; 2276 2277 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2278 2279 s->tx_occurred = false; 2280 sci_request_dma(port); 2281 2282 ret = sci_request_irq(s); 2283 if (unlikely(ret < 0)) { 2284 sci_free_dma(port); 2285 return ret; 2286 } 2287 2288 return 0; 2289 } 2290 2291 static void sci_shutdown(struct uart_port *port) 2292 { 2293 struct sci_port *s = to_sci_port(port); 2294 unsigned long flags; 2295 u16 scr; 2296 2297 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2298 2299 s->autorts = false; 2300 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2301 2302 uart_port_lock_irqsave(port, &flags); 2303 sci_stop_rx(port); 2304 sci_stop_tx(port); 2305 /* 2306 * Stop RX and TX, disable related interrupts, keep clock source 2307 * and HSCIF TOT bits 2308 */ 2309 scr = sci_serial_in(port, SCSCR); 2310 sci_serial_out(port, SCSCR, 2311 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2312 uart_port_unlock_irqrestore(port, flags); 2313 2314 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2315 if (s->chan_rx_saved) { 2316 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2317 port->line); 2318 hrtimer_cancel(&s->rx_timer); 2319 } 2320 #endif 2321 2322 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2323 del_timer_sync(&s->rx_fifo_timer); 2324 sci_free_irq(s); 2325 sci_free_dma(port); 2326 } 2327 2328 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2329 unsigned int *srr) 2330 { 2331 unsigned long freq = s->clk_rates[SCI_SCK]; 2332 int err, min_err = INT_MAX; 2333 unsigned int sr; 2334 2335 if (s->port.type != PORT_HSCIF) 2336 freq *= 2; 2337 2338 for_each_sr(sr, s) { 2339 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2340 if (abs(err) >= abs(min_err)) 2341 continue; 2342 2343 min_err = err; 2344 *srr = sr - 1; 2345 2346 if (!err) 2347 break; 2348 } 2349 2350 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2351 *srr + 1); 2352 return min_err; 2353 } 2354 2355 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2356 unsigned long freq, unsigned int *dlr, 2357 unsigned int *srr) 2358 { 2359 int err, min_err = INT_MAX; 2360 unsigned int sr, dl; 2361 2362 if (s->port.type != PORT_HSCIF) 2363 freq *= 2; 2364 2365 for_each_sr(sr, s) { 2366 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2367 dl = clamp(dl, 1U, 65535U); 2368 2369 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2370 if (abs(err) >= abs(min_err)) 2371 continue; 2372 2373 min_err = err; 2374 *dlr = dl; 2375 *srr = sr - 1; 2376 2377 if (!err) 2378 break; 2379 } 2380 2381 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2382 min_err, *dlr, *srr + 1); 2383 return min_err; 2384 } 2385 2386 /* calculate sample rate, BRR, and clock select */ 2387 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2388 unsigned int *brr, unsigned int *srr, 2389 unsigned int *cks) 2390 { 2391 unsigned long freq = s->clk_rates[SCI_FCK]; 2392 unsigned int sr, br, prediv, scrate, c; 2393 int err, min_err = INT_MAX; 2394 2395 if (s->port.type != PORT_HSCIF) 2396 freq *= 2; 2397 2398 /* 2399 * Find the combination of sample rate and clock select with the 2400 * smallest deviation from the desired baud rate. 2401 * Prefer high sample rates to maximise the receive margin. 2402 * 2403 * M: Receive margin (%) 2404 * N: Ratio of bit rate to clock (N = sampling rate) 2405 * D: Clock duty (D = 0 to 1.0) 2406 * L: Frame length (L = 9 to 12) 2407 * F: Absolute value of clock frequency deviation 2408 * 2409 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2410 * (|D - 0.5| / N * (1 + F))| 2411 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2412 */ 2413 for_each_sr(sr, s) { 2414 for (c = 0; c <= 3; c++) { 2415 /* integerized formulas from HSCIF documentation */ 2416 prediv = sr << (2 * c + 1); 2417 2418 /* 2419 * We need to calculate: 2420 * 2421 * br = freq / (prediv * bps) clamped to [1..256] 2422 * err = freq / (br * prediv) - bps 2423 * 2424 * Watch out for overflow when calculating the desired 2425 * sampling clock rate! 2426 */ 2427 if (bps > UINT_MAX / prediv) 2428 break; 2429 2430 scrate = prediv * bps; 2431 br = DIV_ROUND_CLOSEST(freq, scrate); 2432 br = clamp(br, 1U, 256U); 2433 2434 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2435 if (abs(err) >= abs(min_err)) 2436 continue; 2437 2438 min_err = err; 2439 *brr = br - 1; 2440 *srr = sr - 1; 2441 *cks = c; 2442 2443 if (!err) 2444 goto found; 2445 } 2446 } 2447 2448 found: 2449 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2450 min_err, *brr, *srr + 1, *cks); 2451 return min_err; 2452 } 2453 2454 static void sci_reset(struct uart_port *port) 2455 { 2456 const struct plat_sci_reg *reg; 2457 unsigned int status; 2458 struct sci_port *s = to_sci_port(port); 2459 2460 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2461 2462 reg = sci_getreg(port, SCFCR); 2463 if (reg->size) 2464 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2465 2466 sci_clear_SCxSR(port, 2467 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2468 SCxSR_BREAK_CLEAR(port)); 2469 if (sci_getreg(port, SCLSR)->size) { 2470 status = sci_serial_in(port, SCLSR); 2471 status &= ~(SCLSR_TO | SCLSR_ORER); 2472 sci_serial_out(port, SCLSR, status); 2473 } 2474 2475 if (s->rx_trigger > 1) { 2476 if (s->rx_fifo_timeout) { 2477 scif_set_rtrg(port, 1); 2478 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2479 } else { 2480 if (port->type == PORT_SCIFA || 2481 port->type == PORT_SCIFB) 2482 scif_set_rtrg(port, 1); 2483 else 2484 scif_set_rtrg(port, s->rx_trigger); 2485 } 2486 } 2487 } 2488 2489 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2490 const struct ktermios *old) 2491 { 2492 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2493 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2494 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2495 struct sci_port *s = to_sci_port(port); 2496 const struct plat_sci_reg *reg; 2497 int min_err = INT_MAX, err; 2498 unsigned long max_freq = 0; 2499 int best_clk = -1; 2500 unsigned long flags; 2501 2502 if ((termios->c_cflag & CSIZE) == CS7) { 2503 smr_val |= SCSMR_CHR; 2504 } else { 2505 termios->c_cflag &= ~CSIZE; 2506 termios->c_cflag |= CS8; 2507 } 2508 if (termios->c_cflag & PARENB) 2509 smr_val |= SCSMR_PE; 2510 if (termios->c_cflag & PARODD) 2511 smr_val |= SCSMR_PE | SCSMR_ODD; 2512 if (termios->c_cflag & CSTOPB) 2513 smr_val |= SCSMR_STOP; 2514 2515 /* 2516 * earlyprintk comes here early on with port->uartclk set to zero. 2517 * the clock framework is not up and running at this point so here 2518 * we assume that 115200 is the maximum baud rate. please note that 2519 * the baud rate is not programmed during earlyprintk - it is assumed 2520 * that the previous boot loader has enabled required clocks and 2521 * setup the baud rate generator hardware for us already. 2522 */ 2523 if (!port->uartclk) { 2524 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2525 goto done; 2526 } 2527 2528 for (i = 0; i < SCI_NUM_CLKS; i++) 2529 max_freq = max(max_freq, s->clk_rates[i]); 2530 2531 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2532 if (!baud) 2533 goto done; 2534 2535 /* 2536 * There can be multiple sources for the sampling clock. Find the one 2537 * that gives us the smallest deviation from the desired baud rate. 2538 */ 2539 2540 /* Optional Undivided External Clock */ 2541 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2542 port->type != PORT_SCIFB) { 2543 err = sci_sck_calc(s, baud, &srr1); 2544 if (abs(err) < abs(min_err)) { 2545 best_clk = SCI_SCK; 2546 scr_val = SCSCR_CKE1; 2547 sccks = SCCKS_CKS; 2548 min_err = err; 2549 srr = srr1; 2550 if (!err) 2551 goto done; 2552 } 2553 } 2554 2555 /* Optional BRG Frequency Divided External Clock */ 2556 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2557 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2558 &srr1); 2559 if (abs(err) < abs(min_err)) { 2560 best_clk = SCI_SCIF_CLK; 2561 scr_val = SCSCR_CKE1; 2562 sccks = 0; 2563 min_err = err; 2564 dl = dl1; 2565 srr = srr1; 2566 if (!err) 2567 goto done; 2568 } 2569 } 2570 2571 /* Optional BRG Frequency Divided Internal Clock */ 2572 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2573 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2574 &srr1); 2575 if (abs(err) < abs(min_err)) { 2576 best_clk = SCI_BRG_INT; 2577 scr_val = SCSCR_CKE1; 2578 sccks = SCCKS_XIN; 2579 min_err = err; 2580 dl = dl1; 2581 srr = srr1; 2582 if (!min_err) 2583 goto done; 2584 } 2585 } 2586 2587 /* Divided Functional Clock using standard Bit Rate Register */ 2588 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2589 if (abs(err) < abs(min_err)) { 2590 best_clk = SCI_FCK; 2591 scr_val = 0; 2592 min_err = err; 2593 brr = brr1; 2594 srr = srr1; 2595 cks = cks1; 2596 } 2597 2598 done: 2599 if (best_clk >= 0) 2600 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2601 s->clks[best_clk], baud, min_err); 2602 2603 sci_port_enable(s); 2604 2605 /* 2606 * Program the optional External Baud Rate Generator (BRG) first. 2607 * It controls the mux to select (H)SCK or frequency divided clock. 2608 */ 2609 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2610 sci_serial_out(port, SCDL, dl); 2611 sci_serial_out(port, SCCKS, sccks); 2612 } 2613 2614 uart_port_lock_irqsave(port, &flags); 2615 2616 sci_reset(port); 2617 2618 uart_update_timeout(port, termios->c_cflag, baud); 2619 2620 /* byte size and parity */ 2621 bits = tty_get_frame_size(termios->c_cflag); 2622 2623 if (sci_getreg(port, SEMR)->size) 2624 sci_serial_out(port, SEMR, 0); 2625 2626 if (best_clk >= 0) { 2627 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2628 switch (srr + 1) { 2629 case 5: smr_val |= SCSMR_SRC_5; break; 2630 case 7: smr_val |= SCSMR_SRC_7; break; 2631 case 11: smr_val |= SCSMR_SRC_11; break; 2632 case 13: smr_val |= SCSMR_SRC_13; break; 2633 case 16: smr_val |= SCSMR_SRC_16; break; 2634 case 17: smr_val |= SCSMR_SRC_17; break; 2635 case 19: smr_val |= SCSMR_SRC_19; break; 2636 case 27: smr_val |= SCSMR_SRC_27; break; 2637 } 2638 smr_val |= cks; 2639 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2640 sci_serial_out(port, SCSMR, smr_val); 2641 sci_serial_out(port, SCBRR, brr); 2642 if (sci_getreg(port, HSSRR)->size) { 2643 unsigned int hssrr = srr | HSCIF_SRE; 2644 /* Calculate deviation from intended rate at the 2645 * center of the last stop bit in sampling clocks. 2646 */ 2647 int last_stop = bits * 2 - 1; 2648 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2649 (int)(srr + 1), 2650 2 * (int)baud); 2651 2652 if (abs(deviation) >= 2) { 2653 /* At least two sampling clocks off at the 2654 * last stop bit; we can increase the error 2655 * margin by shifting the sampling point. 2656 */ 2657 int shift = clamp(deviation / 2, -8, 7); 2658 2659 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2660 HSCIF_SRHP_MASK; 2661 hssrr |= HSCIF_SRDE; 2662 } 2663 sci_serial_out(port, HSSRR, hssrr); 2664 } 2665 2666 /* Wait one bit interval */ 2667 udelay((1000000 + (baud - 1)) / baud); 2668 } else { 2669 /* Don't touch the bit rate configuration */ 2670 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2671 smr_val |= sci_serial_in(port, SCSMR) & 2672 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2673 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2674 sci_serial_out(port, SCSMR, smr_val); 2675 } 2676 2677 sci_init_pins(port, termios->c_cflag); 2678 2679 port->status &= ~UPSTAT_AUTOCTS; 2680 s->autorts = false; 2681 reg = sci_getreg(port, SCFCR); 2682 if (reg->size) { 2683 unsigned short ctrl = sci_serial_in(port, SCFCR); 2684 2685 if ((port->flags & UPF_HARD_FLOW) && 2686 (termios->c_cflag & CRTSCTS)) { 2687 /* There is no CTS interrupt to restart the hardware */ 2688 port->status |= UPSTAT_AUTOCTS; 2689 /* MCE is enabled when RTS is raised */ 2690 s->autorts = true; 2691 } 2692 2693 /* 2694 * As we've done a sci_reset() above, ensure we don't 2695 * interfere with the FIFOs while toggling MCE. As the 2696 * reset values could still be set, simply mask them out. 2697 */ 2698 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2699 2700 sci_serial_out(port, SCFCR, ctrl); 2701 } 2702 if (port->flags & UPF_HARD_FLOW) { 2703 /* Refresh (Auto) RTS */ 2704 sci_set_mctrl(port, port->mctrl); 2705 } 2706 2707 /* 2708 * For SCI, TE (transmit enable) must be set after setting TIE 2709 * (transmit interrupt enable) or in the same instruction to 2710 * start the transmitting process. So skip setting TE here for SCI. 2711 */ 2712 if (port->type != PORT_SCI) 2713 scr_val |= SCSCR_TE; 2714 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2715 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2716 if ((srr + 1 == 5) && 2717 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2718 /* 2719 * In asynchronous mode, when the sampling rate is 1/5, first 2720 * received data may become invalid on some SCIFA and SCIFB. 2721 * To avoid this problem wait more than 1 serial data time (1 2722 * bit time x serial data number) after setting SCSCR.RE = 1. 2723 */ 2724 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2725 } 2726 2727 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2728 s->rx_frame = (10000 * bits) / (baud / 100); 2729 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2730 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2731 #endif 2732 2733 if ((termios->c_cflag & CREAD) != 0) 2734 sci_start_rx(port); 2735 2736 uart_port_unlock_irqrestore(port, flags); 2737 2738 sci_port_disable(s); 2739 2740 if (UART_ENABLE_MS(port, termios->c_cflag)) 2741 sci_enable_ms(port); 2742 } 2743 2744 static void sci_pm(struct uart_port *port, unsigned int state, 2745 unsigned int oldstate) 2746 { 2747 struct sci_port *sci_port = to_sci_port(port); 2748 2749 switch (state) { 2750 case UART_PM_STATE_OFF: 2751 sci_port_disable(sci_port); 2752 break; 2753 default: 2754 sci_port_enable(sci_port); 2755 break; 2756 } 2757 } 2758 2759 static const char *sci_type(struct uart_port *port) 2760 { 2761 switch (port->type) { 2762 case PORT_IRDA: 2763 return "irda"; 2764 case PORT_SCI: 2765 return "sci"; 2766 case PORT_SCIF: 2767 return "scif"; 2768 case PORT_SCIFA: 2769 return "scifa"; 2770 case PORT_SCIFB: 2771 return "scifb"; 2772 case PORT_HSCIF: 2773 return "hscif"; 2774 } 2775 2776 return NULL; 2777 } 2778 2779 static int sci_remap_port(struct uart_port *port) 2780 { 2781 struct sci_port *sport = to_sci_port(port); 2782 2783 /* 2784 * Nothing to do if there's already an established membase. 2785 */ 2786 if (port->membase) 2787 return 0; 2788 2789 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2790 port->membase = ioremap(port->mapbase, sport->reg_size); 2791 if (unlikely(!port->membase)) { 2792 dev_err(port->dev, "can't remap port#%d\n", port->line); 2793 return -ENXIO; 2794 } 2795 } else { 2796 /* 2797 * For the simple (and majority of) cases where we don't 2798 * need to do any remapping, just cast the cookie 2799 * directly. 2800 */ 2801 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2802 } 2803 2804 return 0; 2805 } 2806 2807 static void sci_release_port(struct uart_port *port) 2808 { 2809 struct sci_port *sport = to_sci_port(port); 2810 2811 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2812 iounmap(port->membase); 2813 port->membase = NULL; 2814 } 2815 2816 release_mem_region(port->mapbase, sport->reg_size); 2817 } 2818 2819 static int sci_request_port(struct uart_port *port) 2820 { 2821 struct resource *res; 2822 struct sci_port *sport = to_sci_port(port); 2823 int ret; 2824 2825 res = request_mem_region(port->mapbase, sport->reg_size, 2826 dev_name(port->dev)); 2827 if (unlikely(res == NULL)) { 2828 dev_err(port->dev, "request_mem_region failed."); 2829 return -EBUSY; 2830 } 2831 2832 ret = sci_remap_port(port); 2833 if (unlikely(ret != 0)) { 2834 release_resource(res); 2835 return ret; 2836 } 2837 2838 return 0; 2839 } 2840 2841 static void sci_config_port(struct uart_port *port, int flags) 2842 { 2843 if (flags & UART_CONFIG_TYPE) { 2844 struct sci_port *sport = to_sci_port(port); 2845 2846 port->type = sport->cfg->type; 2847 sci_request_port(port); 2848 } 2849 } 2850 2851 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2852 { 2853 if (ser->baud_base < 2400) 2854 /* No paper tape reader for Mitch.. */ 2855 return -EINVAL; 2856 2857 return 0; 2858 } 2859 2860 static const struct uart_ops sci_uart_ops = { 2861 .tx_empty = sci_tx_empty, 2862 .set_mctrl = sci_set_mctrl, 2863 .get_mctrl = sci_get_mctrl, 2864 .start_tx = sci_start_tx, 2865 .stop_tx = sci_stop_tx, 2866 .stop_rx = sci_stop_rx, 2867 .enable_ms = sci_enable_ms, 2868 .break_ctl = sci_break_ctl, 2869 .startup = sci_startup, 2870 .shutdown = sci_shutdown, 2871 .flush_buffer = sci_flush_buffer, 2872 .set_termios = sci_set_termios, 2873 .pm = sci_pm, 2874 .type = sci_type, 2875 .release_port = sci_release_port, 2876 .request_port = sci_request_port, 2877 .config_port = sci_config_port, 2878 .verify_port = sci_verify_port, 2879 #ifdef CONFIG_CONSOLE_POLL 2880 .poll_get_char = sci_poll_get_char, 2881 .poll_put_char = sci_poll_put_char, 2882 #endif 2883 }; 2884 2885 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2886 { 2887 const char *clk_names[] = { 2888 [SCI_FCK] = "fck", 2889 [SCI_SCK] = "sck", 2890 [SCI_BRG_INT] = "brg_int", 2891 [SCI_SCIF_CLK] = "scif_clk", 2892 }; 2893 struct clk *clk; 2894 unsigned int i; 2895 2896 if (sci_port->cfg->type == PORT_HSCIF) 2897 clk_names[SCI_SCK] = "hsck"; 2898 2899 for (i = 0; i < SCI_NUM_CLKS; i++) { 2900 clk = devm_clk_get_optional(dev, clk_names[i]); 2901 if (IS_ERR(clk)) 2902 return PTR_ERR(clk); 2903 2904 if (!clk && i == SCI_FCK) { 2905 /* 2906 * Not all SH platforms declare a clock lookup entry 2907 * for SCI devices, in which case we need to get the 2908 * global "peripheral_clk" clock. 2909 */ 2910 clk = devm_clk_get(dev, "peripheral_clk"); 2911 if (IS_ERR(clk)) 2912 return dev_err_probe(dev, PTR_ERR(clk), 2913 "failed to get %s\n", 2914 clk_names[i]); 2915 } 2916 2917 if (!clk) 2918 dev_dbg(dev, "failed to get %s\n", clk_names[i]); 2919 else 2920 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2921 clk, clk_get_rate(clk)); 2922 sci_port->clks[i] = clk; 2923 } 2924 return 0; 2925 } 2926 2927 static const struct sci_port_params * 2928 sci_probe_regmap(const struct plat_sci_port *cfg) 2929 { 2930 unsigned int regtype; 2931 2932 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2933 return &sci_port_params[cfg->regtype]; 2934 2935 switch (cfg->type) { 2936 case PORT_SCI: 2937 regtype = SCIx_SCI_REGTYPE; 2938 break; 2939 case PORT_IRDA: 2940 regtype = SCIx_IRDA_REGTYPE; 2941 break; 2942 case PORT_SCIFA: 2943 regtype = SCIx_SCIFA_REGTYPE; 2944 break; 2945 case PORT_SCIFB: 2946 regtype = SCIx_SCIFB_REGTYPE; 2947 break; 2948 case PORT_SCIF: 2949 /* 2950 * The SH-4 is a bit of a misnomer here, although that's 2951 * where this particular port layout originated. This 2952 * configuration (or some slight variation thereof) 2953 * remains the dominant model for all SCIFs. 2954 */ 2955 regtype = SCIx_SH4_SCIF_REGTYPE; 2956 break; 2957 case PORT_HSCIF: 2958 regtype = SCIx_HSCIF_REGTYPE; 2959 break; 2960 default: 2961 pr_err("Can't probe register map for given port\n"); 2962 return NULL; 2963 } 2964 2965 return &sci_port_params[regtype]; 2966 } 2967 2968 static int sci_init_single(struct platform_device *dev, 2969 struct sci_port *sci_port, unsigned int index, 2970 const struct plat_sci_port *p, bool early) 2971 { 2972 struct uart_port *port = &sci_port->port; 2973 const struct resource *res; 2974 unsigned int i; 2975 int ret; 2976 2977 sci_port->cfg = p; 2978 2979 port->ops = &sci_uart_ops; 2980 port->iotype = UPIO_MEM; 2981 port->line = index; 2982 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2983 2984 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2985 if (res == NULL) 2986 return -ENOMEM; 2987 2988 port->mapbase = res->start; 2989 sci_port->reg_size = resource_size(res); 2990 2991 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2992 if (i) 2993 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2994 else 2995 sci_port->irqs[i] = platform_get_irq(dev, i); 2996 } 2997 2998 /* 2999 * The fourth interrupt on SCI port is transmit end interrupt, so 3000 * shuffle the interrupts. 3001 */ 3002 if (p->type == PORT_SCI) 3003 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); 3004 3005 /* The SCI generates several interrupts. They can be muxed together or 3006 * connected to different interrupt lines. In the muxed case only one 3007 * interrupt resource is specified as there is only one interrupt ID. 3008 * In the non-muxed case, up to 6 interrupt signals might be generated 3009 * from the SCI, however those signals might have their own individual 3010 * interrupt ID numbers, or muxed together with another interrupt. 3011 */ 3012 if (sci_port->irqs[0] < 0) 3013 return -ENXIO; 3014 3015 if (sci_port->irqs[1] < 0) 3016 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 3017 sci_port->irqs[i] = sci_port->irqs[0]; 3018 3019 sci_port->params = sci_probe_regmap(p); 3020 if (unlikely(sci_port->params == NULL)) 3021 return -EINVAL; 3022 3023 switch (p->type) { 3024 case PORT_SCIFB: 3025 sci_port->rx_trigger = 48; 3026 break; 3027 case PORT_HSCIF: 3028 sci_port->rx_trigger = 64; 3029 break; 3030 case PORT_SCIFA: 3031 sci_port->rx_trigger = 32; 3032 break; 3033 case PORT_SCIF: 3034 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 3035 /* RX triggering not implemented for this IP */ 3036 sci_port->rx_trigger = 1; 3037 else 3038 sci_port->rx_trigger = 8; 3039 break; 3040 default: 3041 sci_port->rx_trigger = 1; 3042 break; 3043 } 3044 3045 sci_port->rx_fifo_timeout = 0; 3046 sci_port->hscif_tot = 0; 3047 3048 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 3049 * match the SoC datasheet, this should be investigated. Let platform 3050 * data override the sampling rate for now. 3051 */ 3052 sci_port->sampling_rate_mask = p->sampling_rate 3053 ? SCI_SR(p->sampling_rate) 3054 : sci_port->params->sampling_rate_mask; 3055 3056 if (!early) { 3057 ret = sci_init_clocks(sci_port, &dev->dev); 3058 if (ret < 0) 3059 return ret; 3060 } 3061 3062 port->type = p->type; 3063 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 3064 port->fifosize = sci_port->params->fifosize; 3065 3066 if (port->type == PORT_SCI && !dev->dev.of_node) { 3067 if (sci_port->reg_size >= 0x20) 3068 port->regshift = 2; 3069 else 3070 port->regshift = 1; 3071 } 3072 3073 /* 3074 * The UART port needs an IRQ value, so we peg this to the RX IRQ 3075 * for the multi-IRQ ports, which is where we are primarily 3076 * concerned with the shutdown path synchronization. 3077 * 3078 * For the muxed case there's nothing more to do. 3079 */ 3080 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 3081 port->irqflags = 0; 3082 3083 return 0; 3084 } 3085 3086 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3087 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3088 static void serial_console_putchar(struct uart_port *port, unsigned char ch) 3089 { 3090 sci_poll_put_char(port, ch); 3091 } 3092 3093 /* 3094 * Print a string to the serial port trying not to disturb 3095 * any possible real use of the port... 3096 */ 3097 static void serial_console_write(struct console *co, const char *s, 3098 unsigned count) 3099 { 3100 struct sci_port *sci_port = &sci_ports[co->index]; 3101 struct uart_port *port = &sci_port->port; 3102 unsigned short bits, ctrl, ctrl_temp; 3103 unsigned long flags; 3104 int locked = 1; 3105 3106 if (port->sysrq) 3107 locked = 0; 3108 else if (oops_in_progress) 3109 locked = uart_port_trylock_irqsave(port, &flags); 3110 else 3111 uart_port_lock_irqsave(port, &flags); 3112 3113 /* first save SCSCR then disable interrupts, keep clock source */ 3114 ctrl = sci_serial_in(port, SCSCR); 3115 ctrl_temp = SCSCR_RE | SCSCR_TE | 3116 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3117 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3118 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3119 3120 uart_console_write(port, s, count, serial_console_putchar); 3121 3122 /* wait until fifo is empty and last bit has been transmitted */ 3123 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3124 while ((sci_serial_in(port, SCxSR) & bits) != bits) 3125 cpu_relax(); 3126 3127 /* restore the SCSCR */ 3128 sci_serial_out(port, SCSCR, ctrl); 3129 3130 if (locked) 3131 uart_port_unlock_irqrestore(port, flags); 3132 } 3133 3134 static int serial_console_setup(struct console *co, char *options) 3135 { 3136 struct sci_port *sci_port; 3137 struct uart_port *port; 3138 int baud = 115200; 3139 int bits = 8; 3140 int parity = 'n'; 3141 int flow = 'n'; 3142 int ret; 3143 3144 /* 3145 * Refuse to handle any bogus ports. 3146 */ 3147 if (co->index < 0 || co->index >= SCI_NPORTS) 3148 return -ENODEV; 3149 3150 sci_port = &sci_ports[co->index]; 3151 port = &sci_port->port; 3152 3153 /* 3154 * Refuse to handle uninitialized ports. 3155 */ 3156 if (!port->ops) 3157 return -ENODEV; 3158 3159 ret = sci_remap_port(port); 3160 if (unlikely(ret != 0)) 3161 return ret; 3162 3163 if (options) 3164 uart_parse_options(options, &baud, &parity, &bits, &flow); 3165 3166 return uart_set_options(port, co, baud, parity, bits, flow); 3167 } 3168 3169 static struct console serial_console = { 3170 .name = "ttySC", 3171 .device = uart_console_device, 3172 .write = serial_console_write, 3173 .setup = serial_console_setup, 3174 .flags = CON_PRINTBUFFER, 3175 .index = -1, 3176 .data = &sci_uart_driver, 3177 }; 3178 3179 #ifdef CONFIG_SUPERH 3180 static char early_serial_buf[32]; 3181 3182 static int early_serial_console_setup(struct console *co, char *options) 3183 { 3184 /* 3185 * This early console is always registered using the earlyprintk= 3186 * parameter, which does not call add_preferred_console(). Thus 3187 * @options is always NULL and the options for this early console 3188 * are passed using a custom buffer. 3189 */ 3190 WARN_ON(options); 3191 3192 return serial_console_setup(co, early_serial_buf); 3193 } 3194 3195 static struct console early_serial_console = { 3196 .name = "early_ttySC", 3197 .write = serial_console_write, 3198 .setup = early_serial_console_setup, 3199 .flags = CON_PRINTBUFFER, 3200 .index = -1, 3201 }; 3202 3203 static int sci_probe_earlyprintk(struct platform_device *pdev) 3204 { 3205 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3206 3207 if (early_serial_console.data) 3208 return -EEXIST; 3209 3210 early_serial_console.index = pdev->id; 3211 3212 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3213 3214 if (!strstr(early_serial_buf, "keep")) 3215 early_serial_console.flags |= CON_BOOT; 3216 3217 register_console(&early_serial_console); 3218 return 0; 3219 } 3220 #endif 3221 3222 #define SCI_CONSOLE (&serial_console) 3223 3224 #else 3225 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3226 { 3227 return -EINVAL; 3228 } 3229 3230 #define SCI_CONSOLE NULL 3231 3232 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3233 3234 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3235 3236 static DEFINE_MUTEX(sci_uart_registration_lock); 3237 static struct uart_driver sci_uart_driver = { 3238 .owner = THIS_MODULE, 3239 .driver_name = "sci", 3240 .dev_name = "ttySC", 3241 .major = SCI_MAJOR, 3242 .minor = SCI_MINOR_START, 3243 .nr = SCI_NPORTS, 3244 .cons = SCI_CONSOLE, 3245 }; 3246 3247 static void sci_remove(struct platform_device *dev) 3248 { 3249 struct sci_port *port = platform_get_drvdata(dev); 3250 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3251 3252 sci_ports_in_use &= ~BIT(port->port.line); 3253 uart_remove_one_port(&sci_uart_driver, &port->port); 3254 3255 if (port->port.fifosize > 1) 3256 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3257 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3258 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3259 } 3260 3261 3262 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3263 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3264 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3265 3266 static const struct of_device_id of_sci_match[] __maybe_unused = { 3267 /* SoC-specific types */ 3268 { 3269 .compatible = "renesas,scif-r7s72100", 3270 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3271 }, 3272 { 3273 .compatible = "renesas,scif-r7s9210", 3274 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3275 }, 3276 { 3277 .compatible = "renesas,scif-r9a07g044", 3278 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3279 }, 3280 { 3281 .compatible = "renesas,scif-r9a09g057", 3282 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE), 3283 }, 3284 /* Family-specific types */ 3285 { 3286 .compatible = "renesas,rcar-gen1-scif", 3287 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3288 }, { 3289 .compatible = "renesas,rcar-gen2-scif", 3290 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3291 }, { 3292 .compatible = "renesas,rcar-gen3-scif", 3293 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3294 }, { 3295 .compatible = "renesas,rcar-gen4-scif", 3296 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3297 }, 3298 /* Generic types */ 3299 { 3300 .compatible = "renesas,scif", 3301 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3302 }, { 3303 .compatible = "renesas,scifa", 3304 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3305 }, { 3306 .compatible = "renesas,scifb", 3307 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3308 }, { 3309 .compatible = "renesas,hscif", 3310 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3311 }, { 3312 .compatible = "renesas,sci", 3313 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3314 }, { 3315 /* Terminator */ 3316 }, 3317 }; 3318 MODULE_DEVICE_TABLE(of, of_sci_match); 3319 3320 static void sci_reset_control_assert(void *data) 3321 { 3322 reset_control_assert(data); 3323 } 3324 3325 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3326 unsigned int *dev_id) 3327 { 3328 struct device_node *np = pdev->dev.of_node; 3329 struct reset_control *rstc; 3330 struct plat_sci_port *p; 3331 struct sci_port *sp; 3332 const void *data; 3333 int id, ret; 3334 3335 if (!IS_ENABLED(CONFIG_OF) || !np) 3336 return ERR_PTR(-EINVAL); 3337 3338 data = of_device_get_match_data(&pdev->dev); 3339 3340 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3341 if (IS_ERR(rstc)) 3342 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3343 "failed to get reset ctrl\n")); 3344 3345 ret = reset_control_deassert(rstc); 3346 if (ret) { 3347 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3348 return ERR_PTR(ret); 3349 } 3350 3351 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3352 if (ret) { 3353 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3354 ret); 3355 return ERR_PTR(ret); 3356 } 3357 3358 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3359 if (!p) 3360 return ERR_PTR(-ENOMEM); 3361 3362 /* Get the line number from the aliases node. */ 3363 id = of_alias_get_id(np, "serial"); 3364 if (id < 0 && ~sci_ports_in_use) 3365 id = ffz(sci_ports_in_use); 3366 if (id < 0) { 3367 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3368 return ERR_PTR(-EINVAL); 3369 } 3370 if (id >= ARRAY_SIZE(sci_ports)) { 3371 dev_err(&pdev->dev, "serial%d out of range\n", id); 3372 return ERR_PTR(-EINVAL); 3373 } 3374 3375 sp = &sci_ports[id]; 3376 *dev_id = id; 3377 3378 p->type = SCI_OF_TYPE(data); 3379 p->regtype = SCI_OF_REGTYPE(data); 3380 3381 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3382 3383 return p; 3384 } 3385 3386 static int sci_probe_single(struct platform_device *dev, 3387 unsigned int index, 3388 struct plat_sci_port *p, 3389 struct sci_port *sciport, 3390 struct resource *sci_res) 3391 { 3392 int ret; 3393 3394 /* Sanity check */ 3395 if (unlikely(index >= SCI_NPORTS)) { 3396 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3397 index+1, SCI_NPORTS); 3398 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3399 return -EINVAL; 3400 } 3401 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3402 if (sci_ports_in_use & BIT(index)) 3403 return -EBUSY; 3404 3405 mutex_lock(&sci_uart_registration_lock); 3406 if (!sci_uart_driver.state) { 3407 ret = uart_register_driver(&sci_uart_driver); 3408 if (ret) { 3409 mutex_unlock(&sci_uart_registration_lock); 3410 return ret; 3411 } 3412 } 3413 mutex_unlock(&sci_uart_registration_lock); 3414 3415 ret = sci_init_single(dev, sciport, index, p, false); 3416 if (ret) 3417 return ret; 3418 3419 sciport->port.dev = &dev->dev; 3420 ret = devm_pm_runtime_enable(&dev->dev); 3421 if (ret) 3422 return ret; 3423 3424 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3425 if (IS_ERR(sciport->gpios)) 3426 return PTR_ERR(sciport->gpios); 3427 3428 if (sciport->has_rtscts) { 3429 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3430 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3431 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3432 return -EINVAL; 3433 } 3434 sciport->port.flags |= UPF_HARD_FLOW; 3435 } 3436 3437 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) { 3438 /* 3439 * In case: 3440 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and 3441 * - it now maps to an alias other than zero and 3442 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is 3443 * available in bootargs) 3444 * 3445 * we need to avoid disabling clocks and PM domains through the runtime 3446 * PM APIs called in __device_attach(). For this, increment the runtime 3447 * PM reference counter (the clocks and PM domains were already enabled 3448 * by the bootloader). Otherwise the earlycon may access the HW when it 3449 * has no clocks enabled leading to failures (infinite loop in 3450 * sci_poll_put_char()). 3451 */ 3452 pm_runtime_get_noresume(&dev->dev); 3453 3454 /* 3455 * Skip cleanup the sci_port[0] in early_console_exit(), this 3456 * port is the same as the earlycon one. 3457 */ 3458 sci_uart_earlycon_dev_probing = true; 3459 } 3460 3461 return uart_add_one_port(&sci_uart_driver, &sciport->port); 3462 } 3463 3464 static int sci_probe(struct platform_device *dev) 3465 { 3466 struct plat_sci_port *p; 3467 struct resource *res; 3468 struct sci_port *sp; 3469 unsigned int dev_id; 3470 int ret; 3471 3472 /* 3473 * If we've come here via earlyprintk initialization, head off to 3474 * the special early probe. We don't have sufficient device state 3475 * to make it beyond this yet. 3476 */ 3477 #ifdef CONFIG_SUPERH 3478 if (is_sh_early_platform_device(dev)) 3479 return sci_probe_earlyprintk(dev); 3480 #endif 3481 3482 if (dev->dev.of_node) { 3483 p = sci_parse_dt(dev, &dev_id); 3484 if (IS_ERR(p)) 3485 return PTR_ERR(p); 3486 } else { 3487 p = dev->dev.platform_data; 3488 if (p == NULL) { 3489 dev_err(&dev->dev, "no platform data supplied\n"); 3490 return -EINVAL; 3491 } 3492 3493 dev_id = dev->id; 3494 } 3495 3496 sp = &sci_ports[dev_id]; 3497 3498 /* 3499 * In case: 3500 * - the probed port alias is zero (as the one used by earlycon), and 3501 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in 3502 * bootargs) 3503 * 3504 * defer the probe of this serial. This is a debug scenario and the user 3505 * must be aware of it. 3506 * 3507 * Except when the probed port is the same as the earlycon port. 3508 */ 3509 3510 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 3511 if (!res) 3512 return -ENODEV; 3513 3514 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start) 3515 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n"); 3516 3517 platform_set_drvdata(dev, sp); 3518 3519 ret = sci_probe_single(dev, dev_id, p, sp, res); 3520 if (ret) 3521 return ret; 3522 3523 if (sp->port.fifosize > 1) { 3524 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3525 if (ret) 3526 return ret; 3527 } 3528 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3529 sp->port.type == PORT_HSCIF) { 3530 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3531 if (ret) { 3532 if (sp->port.fifosize > 1) { 3533 device_remove_file(&dev->dev, 3534 &dev_attr_rx_fifo_trigger); 3535 } 3536 return ret; 3537 } 3538 } 3539 3540 #ifdef CONFIG_SH_STANDARD_BIOS 3541 sh_bios_gdb_detach(); 3542 #endif 3543 3544 sci_ports_in_use |= BIT(dev_id); 3545 return 0; 3546 } 3547 3548 static __maybe_unused int sci_suspend(struct device *dev) 3549 { 3550 struct sci_port *sport = dev_get_drvdata(dev); 3551 3552 if (sport) 3553 uart_suspend_port(&sci_uart_driver, &sport->port); 3554 3555 return 0; 3556 } 3557 3558 static __maybe_unused int sci_resume(struct device *dev) 3559 { 3560 struct sci_port *sport = dev_get_drvdata(dev); 3561 3562 if (sport) 3563 uart_resume_port(&sci_uart_driver, &sport->port); 3564 3565 return 0; 3566 } 3567 3568 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3569 3570 static struct platform_driver sci_driver = { 3571 .probe = sci_probe, 3572 .remove = sci_remove, 3573 .driver = { 3574 .name = "sh-sci", 3575 .pm = &sci_dev_pm_ops, 3576 .of_match_table = of_match_ptr(of_sci_match), 3577 }, 3578 }; 3579 3580 static int __init sci_init(void) 3581 { 3582 pr_info("%s\n", banner); 3583 3584 return platform_driver_register(&sci_driver); 3585 } 3586 3587 static void __exit sci_exit(void) 3588 { 3589 platform_driver_unregister(&sci_driver); 3590 3591 if (sci_uart_driver.state) 3592 uart_unregister_driver(&sci_uart_driver); 3593 } 3594 3595 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3596 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3597 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3598 #endif 3599 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3600 static struct plat_sci_port port_cfg; 3601 3602 static int early_console_exit(struct console *co) 3603 { 3604 struct sci_port *sci_port = &sci_ports[0]; 3605 3606 /* 3607 * Clean the slot used by earlycon. A new SCI device might 3608 * map to this slot. 3609 */ 3610 if (!sci_uart_earlycon_dev_probing) { 3611 memset(sci_port, 0, sizeof(*sci_port)); 3612 sci_uart_earlycon = false; 3613 } 3614 3615 return 0; 3616 } 3617 3618 static int __init early_console_setup(struct earlycon_device *device, 3619 int type) 3620 { 3621 if (!device->port.membase) 3622 return -ENODEV; 3623 3624 device->port.type = type; 3625 sci_ports[0].port = device->port; 3626 port_cfg.type = type; 3627 sci_ports[0].cfg = &port_cfg; 3628 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3629 sci_uart_earlycon = true; 3630 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3631 sci_serial_out(&sci_ports[0].port, SCSCR, 3632 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3633 3634 device->con->write = serial_console_write; 3635 device->con->exit = early_console_exit; 3636 3637 return 0; 3638 } 3639 static int __init sci_early_console_setup(struct earlycon_device *device, 3640 const char *opt) 3641 { 3642 return early_console_setup(device, PORT_SCI); 3643 } 3644 static int __init scif_early_console_setup(struct earlycon_device *device, 3645 const char *opt) 3646 { 3647 return early_console_setup(device, PORT_SCIF); 3648 } 3649 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3650 const char *opt) 3651 { 3652 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3653 return early_console_setup(device, PORT_SCIF); 3654 } 3655 3656 static int __init rzv2hscif_early_console_setup(struct earlycon_device *device, 3657 const char *opt) 3658 { 3659 port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE; 3660 return early_console_setup(device, PORT_SCIF); 3661 } 3662 3663 static int __init scifa_early_console_setup(struct earlycon_device *device, 3664 const char *opt) 3665 { 3666 return early_console_setup(device, PORT_SCIFA); 3667 } 3668 static int __init scifb_early_console_setup(struct earlycon_device *device, 3669 const char *opt) 3670 { 3671 return early_console_setup(device, PORT_SCIFB); 3672 } 3673 static int __init hscif_early_console_setup(struct earlycon_device *device, 3674 const char *opt) 3675 { 3676 return early_console_setup(device, PORT_HSCIF); 3677 } 3678 3679 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3680 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3681 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3682 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3683 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup); 3684 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3685 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3686 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3687 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3688 3689 module_init(sci_init); 3690 module_exit(sci_exit); 3691 3692 MODULE_LICENSE("GPL"); 3693 MODULE_ALIAS("platform:sh-sci"); 3694 MODULE_AUTHOR("Paul Mundt"); 3695 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3696