1 /* 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 3 * 4 * Copyright (C) 2002 - 2011 Paul Mundt 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 6 * 7 * based off of the old drivers/char/sh-sci.c by: 8 * 9 * Copyright (C) 1999, 2000 Niibe Yutaka 10 * Copyright (C) 2000 Sugioka Toshinobu 11 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 12 * Modified to support SecureEdge. David McCullough (2002) 13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 14 * Removed SH7300 support (Jul 2007). 15 * 16 * This file is subject to the terms and conditions of the GNU General Public 17 * License. See the file "COPYING" in the main directory of this archive 18 * for more details. 19 */ 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21 #define SUPPORT_SYSRQ 22 #endif 23 24 #undef DEBUG 25 26 #include <linux/module.h> 27 #include <linux/errno.h> 28 #include <linux/timer.h> 29 #include <linux/interrupt.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial.h> 33 #include <linux/major.h> 34 #include <linux/string.h> 35 #include <linux/sysrq.h> 36 #include <linux/ioport.h> 37 #include <linux/mm.h> 38 #include <linux/init.h> 39 #include <linux/delay.h> 40 #include <linux/console.h> 41 #include <linux/platform_device.h> 42 #include <linux/serial_sci.h> 43 #include <linux/notifier.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/cpufreq.h> 46 #include <linux/clk.h> 47 #include <linux/ctype.h> 48 #include <linux/err.h> 49 #include <linux/dmaengine.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/scatterlist.h> 52 #include <linux/slab.h> 53 54 #ifdef CONFIG_SUPERH 55 #include <asm/sh_bios.h> 56 #endif 57 58 #include "sh-sci.h" 59 60 struct sci_port { 61 struct uart_port port; 62 63 /* Platform configuration */ 64 struct plat_sci_port *cfg; 65 66 /* Break timer */ 67 struct timer_list break_timer; 68 int break_flag; 69 70 /* Interface clock */ 71 struct clk *iclk; 72 /* Function clock */ 73 struct clk *fclk; 74 75 char *irqstr[SCIx_NR_IRQS]; 76 77 struct dma_chan *chan_tx; 78 struct dma_chan *chan_rx; 79 80 #ifdef CONFIG_SERIAL_SH_SCI_DMA 81 struct dma_async_tx_descriptor *desc_tx; 82 struct dma_async_tx_descriptor *desc_rx[2]; 83 dma_cookie_t cookie_tx; 84 dma_cookie_t cookie_rx[2]; 85 dma_cookie_t active_rx; 86 struct scatterlist sg_tx; 87 unsigned int sg_len_tx; 88 struct scatterlist sg_rx[2]; 89 size_t buf_len_rx; 90 struct sh_dmae_slave param_tx; 91 struct sh_dmae_slave param_rx; 92 struct work_struct work_tx; 93 struct work_struct work_rx; 94 struct timer_list rx_timer; 95 unsigned int rx_timeout; 96 #endif 97 98 struct notifier_block freq_transition; 99 100 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 101 unsigned short saved_smr; 102 unsigned short saved_fcr; 103 unsigned char saved_brr; 104 #endif 105 }; 106 107 /* Function prototypes */ 108 static void sci_start_tx(struct uart_port *port); 109 static void sci_stop_tx(struct uart_port *port); 110 static void sci_start_rx(struct uart_port *port); 111 112 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 113 114 static struct sci_port sci_ports[SCI_NPORTS]; 115 static struct uart_driver sci_uart_driver; 116 117 static inline struct sci_port * 118 to_sci_port(struct uart_port *uart) 119 { 120 return container_of(uart, struct sci_port, port); 121 } 122 123 struct plat_sci_reg { 124 u8 offset, size; 125 }; 126 127 /* Helper for invalidating specific entries of an inherited map. */ 128 #define sci_reg_invalid { .offset = 0, .size = 0 } 129 130 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 131 [SCIx_PROBE_REGTYPE] = { 132 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, 133 }, 134 135 /* 136 * Common SCI definitions, dependent on the port's regshift 137 * value. 138 */ 139 [SCIx_SCI_REGTYPE] = { 140 [SCSMR] = { 0x00, 8 }, 141 [SCBRR] = { 0x01, 8 }, 142 [SCSCR] = { 0x02, 8 }, 143 [SCxTDR] = { 0x03, 8 }, 144 [SCxSR] = { 0x04, 8 }, 145 [SCxRDR] = { 0x05, 8 }, 146 [SCFCR] = sci_reg_invalid, 147 [SCFDR] = sci_reg_invalid, 148 [SCTFDR] = sci_reg_invalid, 149 [SCRFDR] = sci_reg_invalid, 150 [SCSPTR] = sci_reg_invalid, 151 [SCLSR] = sci_reg_invalid, 152 }, 153 154 /* 155 * Common definitions for legacy IrDA ports, dependent on 156 * regshift value. 157 */ 158 [SCIx_IRDA_REGTYPE] = { 159 [SCSMR] = { 0x00, 8 }, 160 [SCBRR] = { 0x01, 8 }, 161 [SCSCR] = { 0x02, 8 }, 162 [SCxTDR] = { 0x03, 8 }, 163 [SCxSR] = { 0x04, 8 }, 164 [SCxRDR] = { 0x05, 8 }, 165 [SCFCR] = { 0x06, 8 }, 166 [SCFDR] = { 0x07, 16 }, 167 [SCTFDR] = sci_reg_invalid, 168 [SCRFDR] = sci_reg_invalid, 169 [SCSPTR] = sci_reg_invalid, 170 [SCLSR] = sci_reg_invalid, 171 }, 172 173 /* 174 * Common SCIFA definitions. 175 */ 176 [SCIx_SCIFA_REGTYPE] = { 177 [SCSMR] = { 0x00, 16 }, 178 [SCBRR] = { 0x04, 8 }, 179 [SCSCR] = { 0x08, 16 }, 180 [SCxTDR] = { 0x20, 8 }, 181 [SCxSR] = { 0x14, 16 }, 182 [SCxRDR] = { 0x24, 8 }, 183 [SCFCR] = { 0x18, 16 }, 184 [SCFDR] = { 0x1c, 16 }, 185 [SCTFDR] = sci_reg_invalid, 186 [SCRFDR] = sci_reg_invalid, 187 [SCSPTR] = sci_reg_invalid, 188 [SCLSR] = sci_reg_invalid, 189 }, 190 191 /* 192 * Common SCIFB definitions. 193 */ 194 [SCIx_SCIFB_REGTYPE] = { 195 [SCSMR] = { 0x00, 16 }, 196 [SCBRR] = { 0x04, 8 }, 197 [SCSCR] = { 0x08, 16 }, 198 [SCxTDR] = { 0x40, 8 }, 199 [SCxSR] = { 0x14, 16 }, 200 [SCxRDR] = { 0x60, 8 }, 201 [SCFCR] = { 0x18, 16 }, 202 [SCFDR] = { 0x1c, 16 }, 203 [SCTFDR] = sci_reg_invalid, 204 [SCRFDR] = sci_reg_invalid, 205 [SCSPTR] = sci_reg_invalid, 206 [SCLSR] = sci_reg_invalid, 207 }, 208 209 /* 210 * Common SH-3 SCIF definitions. 211 */ 212 [SCIx_SH3_SCIF_REGTYPE] = { 213 [SCSMR] = { 0x00, 8 }, 214 [SCBRR] = { 0x02, 8 }, 215 [SCSCR] = { 0x04, 8 }, 216 [SCxTDR] = { 0x06, 8 }, 217 [SCxSR] = { 0x08, 16 }, 218 [SCxRDR] = { 0x0a, 8 }, 219 [SCFCR] = { 0x0c, 8 }, 220 [SCFDR] = { 0x0e, 16 }, 221 [SCTFDR] = sci_reg_invalid, 222 [SCRFDR] = sci_reg_invalid, 223 [SCSPTR] = sci_reg_invalid, 224 [SCLSR] = sci_reg_invalid, 225 }, 226 227 /* 228 * Common SH-4(A) SCIF(B) definitions. 229 */ 230 [SCIx_SH4_SCIF_REGTYPE] = { 231 [SCSMR] = { 0x00, 16 }, 232 [SCBRR] = { 0x04, 8 }, 233 [SCSCR] = { 0x08, 16 }, 234 [SCxTDR] = { 0x0c, 8 }, 235 [SCxSR] = { 0x10, 16 }, 236 [SCxRDR] = { 0x14, 8 }, 237 [SCFCR] = { 0x18, 16 }, 238 [SCFDR] = { 0x1c, 16 }, 239 [SCTFDR] = sci_reg_invalid, 240 [SCRFDR] = sci_reg_invalid, 241 [SCSPTR] = { 0x20, 16 }, 242 [SCLSR] = { 0x24, 16 }, 243 }, 244 245 /* 246 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 247 * register. 248 */ 249 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 250 [SCSMR] = { 0x00, 16 }, 251 [SCBRR] = { 0x04, 8 }, 252 [SCSCR] = { 0x08, 16 }, 253 [SCxTDR] = { 0x0c, 8 }, 254 [SCxSR] = { 0x10, 16 }, 255 [SCxRDR] = { 0x14, 8 }, 256 [SCFCR] = { 0x18, 16 }, 257 [SCFDR] = { 0x1c, 16 }, 258 [SCTFDR] = sci_reg_invalid, 259 [SCRFDR] = sci_reg_invalid, 260 [SCSPTR] = sci_reg_invalid, 261 [SCLSR] = { 0x24, 16 }, 262 }, 263 264 /* 265 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 266 * count registers. 267 */ 268 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 269 [SCSMR] = { 0x00, 16 }, 270 [SCBRR] = { 0x04, 8 }, 271 [SCSCR] = { 0x08, 16 }, 272 [SCxTDR] = { 0x0c, 8 }, 273 [SCxSR] = { 0x10, 16 }, 274 [SCxRDR] = { 0x14, 8 }, 275 [SCFCR] = { 0x18, 16 }, 276 [SCFDR] = { 0x1c, 16 }, 277 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 278 [SCRFDR] = { 0x20, 16 }, 279 [SCSPTR] = { 0x24, 16 }, 280 [SCLSR] = { 0x28, 16 }, 281 }, 282 283 /* 284 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 285 * registers. 286 */ 287 [SCIx_SH7705_SCIF_REGTYPE] = { 288 [SCSMR] = { 0x00, 16 }, 289 [SCBRR] = { 0x04, 8 }, 290 [SCSCR] = { 0x08, 16 }, 291 [SCxTDR] = { 0x20, 8 }, 292 [SCxSR] = { 0x14, 16 }, 293 [SCxRDR] = { 0x24, 8 }, 294 [SCFCR] = { 0x18, 16 }, 295 [SCFDR] = { 0x1c, 16 }, 296 [SCTFDR] = sci_reg_invalid, 297 [SCRFDR] = sci_reg_invalid, 298 [SCSPTR] = sci_reg_invalid, 299 [SCLSR] = sci_reg_invalid, 300 }, 301 }; 302 303 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) 304 305 /* 306 * The "offset" here is rather misleading, in that it refers to an enum 307 * value relative to the port mapping rather than the fixed offset 308 * itself, which needs to be manually retrieved from the platform's 309 * register map for the given port. 310 */ 311 static unsigned int sci_serial_in(struct uart_port *p, int offset) 312 { 313 struct plat_sci_reg *reg = sci_getreg(p, offset); 314 315 if (reg->size == 8) 316 return ioread8(p->membase + (reg->offset << p->regshift)); 317 else if (reg->size == 16) 318 return ioread16(p->membase + (reg->offset << p->regshift)); 319 else 320 WARN(1, "Invalid register access\n"); 321 322 return 0; 323 } 324 325 static void sci_serial_out(struct uart_port *p, int offset, int value) 326 { 327 struct plat_sci_reg *reg = sci_getreg(p, offset); 328 329 if (reg->size == 8) 330 iowrite8(value, p->membase + (reg->offset << p->regshift)); 331 else if (reg->size == 16) 332 iowrite16(value, p->membase + (reg->offset << p->regshift)); 333 else 334 WARN(1, "Invalid register access\n"); 335 } 336 337 #define sci_in(up, offset) (up->serial_in(up, offset)) 338 #define sci_out(up, offset, value) (up->serial_out(up, offset, value)) 339 340 static int sci_probe_regmap(struct plat_sci_port *cfg) 341 { 342 switch (cfg->type) { 343 case PORT_SCI: 344 cfg->regtype = SCIx_SCI_REGTYPE; 345 break; 346 case PORT_IRDA: 347 cfg->regtype = SCIx_IRDA_REGTYPE; 348 break; 349 case PORT_SCIFA: 350 cfg->regtype = SCIx_SCIFA_REGTYPE; 351 break; 352 case PORT_SCIFB: 353 cfg->regtype = SCIx_SCIFB_REGTYPE; 354 break; 355 case PORT_SCIF: 356 /* 357 * The SH-4 is a bit of a misnomer here, although that's 358 * where this particular port layout originated. This 359 * configuration (or some slight variation thereof) 360 * remains the dominant model for all SCIFs. 361 */ 362 cfg->regtype = SCIx_SH4_SCIF_REGTYPE; 363 break; 364 default: 365 printk(KERN_ERR "Can't probe register map for given port\n"); 366 return -EINVAL; 367 } 368 369 return 0; 370 } 371 372 static void sci_port_enable(struct sci_port *sci_port) 373 { 374 if (!sci_port->port.dev) 375 return; 376 377 pm_runtime_get_sync(sci_port->port.dev); 378 379 clk_enable(sci_port->iclk); 380 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 381 clk_enable(sci_port->fclk); 382 } 383 384 static void sci_port_disable(struct sci_port *sci_port) 385 { 386 if (!sci_port->port.dev) 387 return; 388 389 clk_disable(sci_port->fclk); 390 clk_disable(sci_port->iclk); 391 392 pm_runtime_put_sync(sci_port->port.dev); 393 } 394 395 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 396 397 #ifdef CONFIG_CONSOLE_POLL 398 static int sci_poll_get_char(struct uart_port *port) 399 { 400 unsigned short status; 401 int c; 402 403 do { 404 status = sci_in(port, SCxSR); 405 if (status & SCxSR_ERRORS(port)) { 406 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 407 continue; 408 } 409 break; 410 } while (1); 411 412 if (!(status & SCxSR_RDxF(port))) 413 return NO_POLL_CHAR; 414 415 c = sci_in(port, SCxRDR); 416 417 /* Dummy read */ 418 sci_in(port, SCxSR); 419 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 420 421 return c; 422 } 423 #endif 424 425 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 426 { 427 unsigned short status; 428 429 do { 430 status = sci_in(port, SCxSR); 431 } while (!(status & SCxSR_TDxE(port))); 432 433 sci_out(port, SCxTDR, c); 434 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 435 } 436 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 437 438 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 439 { 440 struct sci_port *s = to_sci_port(port); 441 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 442 443 /* 444 * Use port-specific handler if provided. 445 */ 446 if (s->cfg->ops && s->cfg->ops->init_pins) { 447 s->cfg->ops->init_pins(port, cflag); 448 return; 449 } 450 451 /* 452 * For the generic path SCSPTR is necessary. Bail out if that's 453 * unavailable, too. 454 */ 455 if (!reg->size) 456 return; 457 458 if (!(cflag & CRTSCTS)) 459 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */ 460 } 461 462 static int sci_txfill(struct uart_port *port) 463 { 464 struct plat_sci_reg *reg; 465 466 reg = sci_getreg(port, SCTFDR); 467 if (reg->size) 468 return sci_in(port, SCTFDR) & 0xff; 469 470 reg = sci_getreg(port, SCFDR); 471 if (reg->size) 472 return sci_in(port, SCFDR) >> 8; 473 474 return !(sci_in(port, SCxSR) & SCI_TDRE); 475 } 476 477 static int sci_txroom(struct uart_port *port) 478 { 479 return port->fifosize - sci_txfill(port); 480 } 481 482 static int sci_rxfill(struct uart_port *port) 483 { 484 struct plat_sci_reg *reg; 485 486 reg = sci_getreg(port, SCRFDR); 487 if (reg->size) 488 return sci_in(port, SCRFDR) & 0xff; 489 490 reg = sci_getreg(port, SCFDR); 491 if (reg->size) 492 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1); 493 494 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 495 } 496 497 /* 498 * SCI helper for checking the state of the muxed port/RXD pins. 499 */ 500 static inline int sci_rxd_in(struct uart_port *port) 501 { 502 struct sci_port *s = to_sci_port(port); 503 504 if (s->cfg->port_reg <= 0) 505 return 1; 506 507 return !!__raw_readb(s->cfg->port_reg); 508 } 509 510 /* ********************************************************************** * 511 * the interrupt related routines * 512 * ********************************************************************** */ 513 514 static void sci_transmit_chars(struct uart_port *port) 515 { 516 struct circ_buf *xmit = &port->state->xmit; 517 unsigned int stopped = uart_tx_stopped(port); 518 unsigned short status; 519 unsigned short ctrl; 520 int count; 521 522 status = sci_in(port, SCxSR); 523 if (!(status & SCxSR_TDxE(port))) { 524 ctrl = sci_in(port, SCSCR); 525 if (uart_circ_empty(xmit)) 526 ctrl &= ~SCSCR_TIE; 527 else 528 ctrl |= SCSCR_TIE; 529 sci_out(port, SCSCR, ctrl); 530 return; 531 } 532 533 count = sci_txroom(port); 534 535 do { 536 unsigned char c; 537 538 if (port->x_char) { 539 c = port->x_char; 540 port->x_char = 0; 541 } else if (!uart_circ_empty(xmit) && !stopped) { 542 c = xmit->buf[xmit->tail]; 543 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 544 } else { 545 break; 546 } 547 548 sci_out(port, SCxTDR, c); 549 550 port->icount.tx++; 551 } while (--count > 0); 552 553 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 554 555 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 556 uart_write_wakeup(port); 557 if (uart_circ_empty(xmit)) { 558 sci_stop_tx(port); 559 } else { 560 ctrl = sci_in(port, SCSCR); 561 562 if (port->type != PORT_SCI) { 563 sci_in(port, SCxSR); /* Dummy read */ 564 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 565 } 566 567 ctrl |= SCSCR_TIE; 568 sci_out(port, SCSCR, ctrl); 569 } 570 } 571 572 /* On SH3, SCIF may read end-of-break as a space->mark char */ 573 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 574 575 static void sci_receive_chars(struct uart_port *port) 576 { 577 struct sci_port *sci_port = to_sci_port(port); 578 struct tty_struct *tty = port->state->port.tty; 579 int i, count, copied = 0; 580 unsigned short status; 581 unsigned char flag; 582 583 status = sci_in(port, SCxSR); 584 if (!(status & SCxSR_RDxF(port))) 585 return; 586 587 while (1) { 588 /* Don't copy more bytes than there is room for in the buffer */ 589 count = tty_buffer_request_room(tty, sci_rxfill(port)); 590 591 /* If for any reason we can't copy more data, we're done! */ 592 if (count == 0) 593 break; 594 595 if (port->type == PORT_SCI) { 596 char c = sci_in(port, SCxRDR); 597 if (uart_handle_sysrq_char(port, c) || 598 sci_port->break_flag) 599 count = 0; 600 else 601 tty_insert_flip_char(tty, c, TTY_NORMAL); 602 } else { 603 for (i = 0; i < count; i++) { 604 char c = sci_in(port, SCxRDR); 605 status = sci_in(port, SCxSR); 606 #if defined(CONFIG_CPU_SH3) 607 /* Skip "chars" during break */ 608 if (sci_port->break_flag) { 609 if ((c == 0) && 610 (status & SCxSR_FER(port))) { 611 count--; i--; 612 continue; 613 } 614 615 /* Nonzero => end-of-break */ 616 dev_dbg(port->dev, "debounce<%02x>\n", c); 617 sci_port->break_flag = 0; 618 619 if (STEPFN(c)) { 620 count--; i--; 621 continue; 622 } 623 } 624 #endif /* CONFIG_CPU_SH3 */ 625 if (uart_handle_sysrq_char(port, c)) { 626 count--; i--; 627 continue; 628 } 629 630 /* Store data and status */ 631 if (status & SCxSR_FER(port)) { 632 flag = TTY_FRAME; 633 dev_notice(port->dev, "frame error\n"); 634 } else if (status & SCxSR_PER(port)) { 635 flag = TTY_PARITY; 636 dev_notice(port->dev, "parity error\n"); 637 } else 638 flag = TTY_NORMAL; 639 640 tty_insert_flip_char(tty, c, flag); 641 } 642 } 643 644 sci_in(port, SCxSR); /* dummy read */ 645 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 646 647 copied += count; 648 port->icount.rx += count; 649 } 650 651 if (copied) { 652 /* Tell the rest of the system the news. New characters! */ 653 tty_flip_buffer_push(tty); 654 } else { 655 sci_in(port, SCxSR); /* dummy read */ 656 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 657 } 658 } 659 660 #define SCI_BREAK_JIFFIES (HZ/20) 661 662 /* 663 * The sci generates interrupts during the break, 664 * 1 per millisecond or so during the break period, for 9600 baud. 665 * So dont bother disabling interrupts. 666 * But dont want more than 1 break event. 667 * Use a kernel timer to periodically poll the rx line until 668 * the break is finished. 669 */ 670 static inline void sci_schedule_break_timer(struct sci_port *port) 671 { 672 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); 673 } 674 675 /* Ensure that two consecutive samples find the break over. */ 676 static void sci_break_timer(unsigned long data) 677 { 678 struct sci_port *port = (struct sci_port *)data; 679 680 sci_port_enable(port); 681 682 if (sci_rxd_in(&port->port) == 0) { 683 port->break_flag = 1; 684 sci_schedule_break_timer(port); 685 } else if (port->break_flag == 1) { 686 /* break is over. */ 687 port->break_flag = 2; 688 sci_schedule_break_timer(port); 689 } else 690 port->break_flag = 0; 691 692 sci_port_disable(port); 693 } 694 695 static int sci_handle_errors(struct uart_port *port) 696 { 697 int copied = 0; 698 unsigned short status = sci_in(port, SCxSR); 699 struct tty_struct *tty = port->state->port.tty; 700 struct sci_port *s = to_sci_port(port); 701 702 /* 703 * Handle overruns, if supported. 704 */ 705 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) { 706 if (status & (1 << s->cfg->overrun_bit)) { 707 /* overrun error */ 708 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 709 copied++; 710 711 dev_notice(port->dev, "overrun error"); 712 } 713 } 714 715 if (status & SCxSR_FER(port)) { 716 if (sci_rxd_in(port) == 0) { 717 /* Notify of BREAK */ 718 struct sci_port *sci_port = to_sci_port(port); 719 720 if (!sci_port->break_flag) { 721 sci_port->break_flag = 1; 722 sci_schedule_break_timer(sci_port); 723 724 /* Do sysrq handling. */ 725 if (uart_handle_break(port)) 726 return 0; 727 728 dev_dbg(port->dev, "BREAK detected\n"); 729 730 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 731 copied++; 732 } 733 734 } else { 735 /* frame error */ 736 if (tty_insert_flip_char(tty, 0, TTY_FRAME)) 737 copied++; 738 739 dev_notice(port->dev, "frame error\n"); 740 } 741 } 742 743 if (status & SCxSR_PER(port)) { 744 /* parity error */ 745 if (tty_insert_flip_char(tty, 0, TTY_PARITY)) 746 copied++; 747 748 dev_notice(port->dev, "parity error"); 749 } 750 751 if (copied) 752 tty_flip_buffer_push(tty); 753 754 return copied; 755 } 756 757 static int sci_handle_fifo_overrun(struct uart_port *port) 758 { 759 struct tty_struct *tty = port->state->port.tty; 760 struct sci_port *s = to_sci_port(port); 761 struct plat_sci_reg *reg; 762 int copied = 0; 763 764 reg = sci_getreg(port, SCLSR); 765 if (!reg->size) 766 return 0; 767 768 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) { 769 sci_out(port, SCLSR, 0); 770 771 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 772 tty_flip_buffer_push(tty); 773 774 dev_notice(port->dev, "overrun error\n"); 775 copied++; 776 } 777 778 return copied; 779 } 780 781 static int sci_handle_breaks(struct uart_port *port) 782 { 783 int copied = 0; 784 unsigned short status = sci_in(port, SCxSR); 785 struct tty_struct *tty = port->state->port.tty; 786 struct sci_port *s = to_sci_port(port); 787 788 if (uart_handle_break(port)) 789 return 0; 790 791 if (!s->break_flag && status & SCxSR_BRK(port)) { 792 #if defined(CONFIG_CPU_SH3) 793 /* Debounce break */ 794 s->break_flag = 1; 795 #endif 796 /* Notify of BREAK */ 797 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 798 copied++; 799 800 dev_dbg(port->dev, "BREAK detected\n"); 801 } 802 803 if (copied) 804 tty_flip_buffer_push(tty); 805 806 copied += sci_handle_fifo_overrun(port); 807 808 return copied; 809 } 810 811 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 812 { 813 #ifdef CONFIG_SERIAL_SH_SCI_DMA 814 struct uart_port *port = ptr; 815 struct sci_port *s = to_sci_port(port); 816 817 if (s->chan_rx) { 818 u16 scr = sci_in(port, SCSCR); 819 u16 ssr = sci_in(port, SCxSR); 820 821 /* Disable future Rx interrupts */ 822 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 823 disable_irq_nosync(irq); 824 scr |= 0x4000; 825 } else { 826 scr &= ~SCSCR_RIE; 827 } 828 sci_out(port, SCSCR, scr); 829 /* Clear current interrupt */ 830 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); 831 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 832 jiffies, s->rx_timeout); 833 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 834 835 return IRQ_HANDLED; 836 } 837 #endif 838 839 /* I think sci_receive_chars has to be called irrespective 840 * of whether the I_IXOFF is set, otherwise, how is the interrupt 841 * to be disabled? 842 */ 843 sci_receive_chars(ptr); 844 845 return IRQ_HANDLED; 846 } 847 848 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 849 { 850 struct uart_port *port = ptr; 851 unsigned long flags; 852 853 spin_lock_irqsave(&port->lock, flags); 854 sci_transmit_chars(port); 855 spin_unlock_irqrestore(&port->lock, flags); 856 857 return IRQ_HANDLED; 858 } 859 860 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 861 { 862 struct uart_port *port = ptr; 863 864 /* Handle errors */ 865 if (port->type == PORT_SCI) { 866 if (sci_handle_errors(port)) { 867 /* discard character in rx buffer */ 868 sci_in(port, SCxSR); 869 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 870 } 871 } else { 872 sci_handle_fifo_overrun(port); 873 sci_rx_interrupt(irq, ptr); 874 } 875 876 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 877 878 /* Kick the transmission */ 879 sci_tx_interrupt(irq, ptr); 880 881 return IRQ_HANDLED; 882 } 883 884 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 885 { 886 struct uart_port *port = ptr; 887 888 /* Handle BREAKs */ 889 sci_handle_breaks(port); 890 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 891 892 return IRQ_HANDLED; 893 } 894 895 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 896 { 897 /* 898 * Not all ports (such as SCIFA) will support REIE. Rather than 899 * special-casing the port type, we check the port initialization 900 * IRQ enable mask to see whether the IRQ is desired at all. If 901 * it's unset, it's logically inferred that there's no point in 902 * testing for it. 903 */ 904 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 905 } 906 907 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 908 { 909 unsigned short ssr_status, scr_status, err_enabled; 910 struct uart_port *port = ptr; 911 struct sci_port *s = to_sci_port(port); 912 irqreturn_t ret = IRQ_NONE; 913 914 ssr_status = sci_in(port, SCxSR); 915 scr_status = sci_in(port, SCSCR); 916 err_enabled = scr_status & port_rx_irq_mask(port); 917 918 /* Tx Interrupt */ 919 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 920 !s->chan_tx) 921 ret = sci_tx_interrupt(irq, ptr); 922 923 /* 924 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 925 * DR flags 926 */ 927 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 928 (scr_status & SCSCR_RIE)) 929 ret = sci_rx_interrupt(irq, ptr); 930 931 /* Error Interrupt */ 932 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 933 ret = sci_er_interrupt(irq, ptr); 934 935 /* Break Interrupt */ 936 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 937 ret = sci_br_interrupt(irq, ptr); 938 939 return ret; 940 } 941 942 /* 943 * Here we define a transition notifier so that we can update all of our 944 * ports' baud rate when the peripheral clock changes. 945 */ 946 static int sci_notifier(struct notifier_block *self, 947 unsigned long phase, void *p) 948 { 949 struct sci_port *sci_port; 950 unsigned long flags; 951 952 sci_port = container_of(self, struct sci_port, freq_transition); 953 954 if ((phase == CPUFREQ_POSTCHANGE) || 955 (phase == CPUFREQ_RESUMECHANGE)) { 956 struct uart_port *port = &sci_port->port; 957 958 spin_lock_irqsave(&port->lock, flags); 959 port->uartclk = clk_get_rate(sci_port->iclk); 960 spin_unlock_irqrestore(&port->lock, flags); 961 } 962 963 return NOTIFY_OK; 964 } 965 966 static struct sci_irq_desc { 967 const char *desc; 968 irq_handler_t handler; 969 } sci_irq_desc[] = { 970 /* 971 * Split out handlers, the default case. 972 */ 973 [SCIx_ERI_IRQ] = { 974 .desc = "rx err", 975 .handler = sci_er_interrupt, 976 }, 977 978 [SCIx_RXI_IRQ] = { 979 .desc = "rx full", 980 .handler = sci_rx_interrupt, 981 }, 982 983 [SCIx_TXI_IRQ] = { 984 .desc = "tx empty", 985 .handler = sci_tx_interrupt, 986 }, 987 988 [SCIx_BRI_IRQ] = { 989 .desc = "break", 990 .handler = sci_br_interrupt, 991 }, 992 993 /* 994 * Special muxed handler. 995 */ 996 [SCIx_MUX_IRQ] = { 997 .desc = "mux", 998 .handler = sci_mpxed_interrupt, 999 }, 1000 }; 1001 1002 static int sci_request_irq(struct sci_port *port) 1003 { 1004 struct uart_port *up = &port->port; 1005 int i, j, ret = 0; 1006 1007 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1008 struct sci_irq_desc *desc; 1009 unsigned int irq; 1010 1011 if (SCIx_IRQ_IS_MUXED(port)) { 1012 i = SCIx_MUX_IRQ; 1013 irq = up->irq; 1014 } else 1015 irq = port->cfg->irqs[i]; 1016 1017 desc = sci_irq_desc + i; 1018 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1019 dev_name(up->dev), desc->desc); 1020 if (!port->irqstr[j]) { 1021 dev_err(up->dev, "Failed to allocate %s IRQ string\n", 1022 desc->desc); 1023 goto out_nomem; 1024 } 1025 1026 ret = request_irq(irq, desc->handler, up->irqflags, 1027 port->irqstr[j], port); 1028 if (unlikely(ret)) { 1029 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1030 goto out_noirq; 1031 } 1032 } 1033 1034 return 0; 1035 1036 out_noirq: 1037 while (--i >= 0) 1038 free_irq(port->cfg->irqs[i], port); 1039 1040 out_nomem: 1041 while (--j >= 0) 1042 kfree(port->irqstr[j]); 1043 1044 return ret; 1045 } 1046 1047 static void sci_free_irq(struct sci_port *port) 1048 { 1049 int i; 1050 1051 /* 1052 * Intentionally in reverse order so we iterate over the muxed 1053 * IRQ first. 1054 */ 1055 for (i = 0; i < SCIx_NR_IRQS; i++) { 1056 free_irq(port->cfg->irqs[i], port); 1057 kfree(port->irqstr[i]); 1058 1059 if (SCIx_IRQ_IS_MUXED(port)) { 1060 /* If there's only one IRQ, we're done. */ 1061 return; 1062 } 1063 } 1064 } 1065 1066 static unsigned int sci_tx_empty(struct uart_port *port) 1067 { 1068 unsigned short status = sci_in(port, SCxSR); 1069 unsigned short in_tx_fifo = sci_txfill(port); 1070 1071 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1072 } 1073 1074 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1075 { 1076 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ 1077 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ 1078 /* If you have signals for DTR and DCD, please implement here. */ 1079 } 1080 1081 static unsigned int sci_get_mctrl(struct uart_port *port) 1082 { 1083 /* This routine is used for getting signals of: DTR, DCD, DSR, RI, 1084 and CTS/RTS */ 1085 1086 return TIOCM_DTR | TIOCM_RTS | TIOCM_CTS | TIOCM_DSR; 1087 } 1088 1089 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1090 static void sci_dma_tx_complete(void *arg) 1091 { 1092 struct sci_port *s = arg; 1093 struct uart_port *port = &s->port; 1094 struct circ_buf *xmit = &port->state->xmit; 1095 unsigned long flags; 1096 1097 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1098 1099 spin_lock_irqsave(&port->lock, flags); 1100 1101 xmit->tail += sg_dma_len(&s->sg_tx); 1102 xmit->tail &= UART_XMIT_SIZE - 1; 1103 1104 port->icount.tx += sg_dma_len(&s->sg_tx); 1105 1106 async_tx_ack(s->desc_tx); 1107 s->cookie_tx = -EINVAL; 1108 s->desc_tx = NULL; 1109 1110 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1111 uart_write_wakeup(port); 1112 1113 if (!uart_circ_empty(xmit)) { 1114 schedule_work(&s->work_tx); 1115 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1116 u16 ctrl = sci_in(port, SCSCR); 1117 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1118 } 1119 1120 spin_unlock_irqrestore(&port->lock, flags); 1121 } 1122 1123 /* Locking: called with port lock held */ 1124 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty, 1125 size_t count) 1126 { 1127 struct uart_port *port = &s->port; 1128 int i, active, room; 1129 1130 room = tty_buffer_request_room(tty, count); 1131 1132 if (s->active_rx == s->cookie_rx[0]) { 1133 active = 0; 1134 } else if (s->active_rx == s->cookie_rx[1]) { 1135 active = 1; 1136 } else { 1137 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1138 return 0; 1139 } 1140 1141 if (room < count) 1142 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 1143 count - room); 1144 if (!room) 1145 return room; 1146 1147 for (i = 0; i < room; i++) 1148 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i], 1149 TTY_NORMAL); 1150 1151 port->icount.rx += room; 1152 1153 return room; 1154 } 1155 1156 static void sci_dma_rx_complete(void *arg) 1157 { 1158 struct sci_port *s = arg; 1159 struct uart_port *port = &s->port; 1160 struct tty_struct *tty = port->state->port.tty; 1161 unsigned long flags; 1162 int count; 1163 1164 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); 1165 1166 spin_lock_irqsave(&port->lock, flags); 1167 1168 count = sci_dma_rx_push(s, tty, s->buf_len_rx); 1169 1170 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1171 1172 spin_unlock_irqrestore(&port->lock, flags); 1173 1174 if (count) 1175 tty_flip_buffer_push(tty); 1176 1177 schedule_work(&s->work_rx); 1178 } 1179 1180 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1181 { 1182 struct dma_chan *chan = s->chan_rx; 1183 struct uart_port *port = &s->port; 1184 1185 s->chan_rx = NULL; 1186 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1187 dma_release_channel(chan); 1188 if (sg_dma_address(&s->sg_rx[0])) 1189 dma_free_coherent(port->dev, s->buf_len_rx * 2, 1190 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); 1191 if (enable_pio) 1192 sci_start_rx(port); 1193 } 1194 1195 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1196 { 1197 struct dma_chan *chan = s->chan_tx; 1198 struct uart_port *port = &s->port; 1199 1200 s->chan_tx = NULL; 1201 s->cookie_tx = -EINVAL; 1202 dma_release_channel(chan); 1203 if (enable_pio) 1204 sci_start_tx(port); 1205 } 1206 1207 static void sci_submit_rx(struct sci_port *s) 1208 { 1209 struct dma_chan *chan = s->chan_rx; 1210 int i; 1211 1212 for (i = 0; i < 2; i++) { 1213 struct scatterlist *sg = &s->sg_rx[i]; 1214 struct dma_async_tx_descriptor *desc; 1215 1216 desc = chan->device->device_prep_slave_sg(chan, 1217 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT); 1218 1219 if (desc) { 1220 s->desc_rx[i] = desc; 1221 desc->callback = sci_dma_rx_complete; 1222 desc->callback_param = s; 1223 s->cookie_rx[i] = desc->tx_submit(desc); 1224 } 1225 1226 if (!desc || s->cookie_rx[i] < 0) { 1227 if (i) { 1228 async_tx_ack(s->desc_rx[0]); 1229 s->cookie_rx[0] = -EINVAL; 1230 } 1231 if (desc) { 1232 async_tx_ack(desc); 1233 s->cookie_rx[i] = -EINVAL; 1234 } 1235 dev_warn(s->port.dev, 1236 "failed to re-start DMA, using PIO\n"); 1237 sci_rx_dma_release(s, true); 1238 return; 1239 } 1240 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, 1241 s->cookie_rx[i], i); 1242 } 1243 1244 s->active_rx = s->cookie_rx[0]; 1245 1246 dma_async_issue_pending(chan); 1247 } 1248 1249 static void work_fn_rx(struct work_struct *work) 1250 { 1251 struct sci_port *s = container_of(work, struct sci_port, work_rx); 1252 struct uart_port *port = &s->port; 1253 struct dma_async_tx_descriptor *desc; 1254 int new; 1255 1256 if (s->active_rx == s->cookie_rx[0]) { 1257 new = 0; 1258 } else if (s->active_rx == s->cookie_rx[1]) { 1259 new = 1; 1260 } else { 1261 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1262 return; 1263 } 1264 desc = s->desc_rx[new]; 1265 1266 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != 1267 DMA_SUCCESS) { 1268 /* Handle incomplete DMA receive */ 1269 struct tty_struct *tty = port->state->port.tty; 1270 struct dma_chan *chan = s->chan_rx; 1271 struct sh_desc *sh_desc = container_of(desc, struct sh_desc, 1272 async_tx); 1273 unsigned long flags; 1274 int count; 1275 1276 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 1277 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", 1278 sh_desc->partial, sh_desc->cookie); 1279 1280 spin_lock_irqsave(&port->lock, flags); 1281 count = sci_dma_rx_push(s, tty, sh_desc->partial); 1282 spin_unlock_irqrestore(&port->lock, flags); 1283 1284 if (count) 1285 tty_flip_buffer_push(tty); 1286 1287 sci_submit_rx(s); 1288 1289 return; 1290 } 1291 1292 s->cookie_rx[new] = desc->tx_submit(desc); 1293 if (s->cookie_rx[new] < 0) { 1294 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1295 sci_rx_dma_release(s, true); 1296 return; 1297 } 1298 1299 s->active_rx = s->cookie_rx[!new]; 1300 1301 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, 1302 s->cookie_rx[new], new, s->active_rx); 1303 } 1304 1305 static void work_fn_tx(struct work_struct *work) 1306 { 1307 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1308 struct dma_async_tx_descriptor *desc; 1309 struct dma_chan *chan = s->chan_tx; 1310 struct uart_port *port = &s->port; 1311 struct circ_buf *xmit = &port->state->xmit; 1312 struct scatterlist *sg = &s->sg_tx; 1313 1314 /* 1315 * DMA is idle now. 1316 * Port xmit buffer is already mapped, and it is one page... Just adjust 1317 * offsets and lengths. Since it is a circular buffer, we have to 1318 * transmit till the end, and then the rest. Take the port lock to get a 1319 * consistent xmit buffer state. 1320 */ 1321 spin_lock_irq(&port->lock); 1322 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 1323 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + 1324 sg->offset; 1325 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1326 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1327 spin_unlock_irq(&port->lock); 1328 1329 BUG_ON(!sg_dma_len(sg)); 1330 1331 desc = chan->device->device_prep_slave_sg(chan, 1332 sg, s->sg_len_tx, DMA_TO_DEVICE, 1333 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1334 if (!desc) { 1335 /* switch to PIO */ 1336 sci_tx_dma_release(s, true); 1337 return; 1338 } 1339 1340 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 1341 1342 spin_lock_irq(&port->lock); 1343 s->desc_tx = desc; 1344 desc->callback = sci_dma_tx_complete; 1345 desc->callback_param = s; 1346 spin_unlock_irq(&port->lock); 1347 s->cookie_tx = desc->tx_submit(desc); 1348 if (s->cookie_tx < 0) { 1349 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1350 /* switch to PIO */ 1351 sci_tx_dma_release(s, true); 1352 return; 1353 } 1354 1355 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, 1356 xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1357 1358 dma_async_issue_pending(chan); 1359 } 1360 #endif 1361 1362 static void sci_start_tx(struct uart_port *port) 1363 { 1364 struct sci_port *s = to_sci_port(port); 1365 unsigned short ctrl; 1366 1367 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1368 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1369 u16 new, scr = sci_in(port, SCSCR); 1370 if (s->chan_tx) 1371 new = scr | 0x8000; 1372 else 1373 new = scr & ~0x8000; 1374 if (new != scr) 1375 sci_out(port, SCSCR, new); 1376 } 1377 1378 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 1379 s->cookie_tx < 0) 1380 schedule_work(&s->work_tx); 1381 #endif 1382 1383 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1384 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1385 ctrl = sci_in(port, SCSCR); 1386 sci_out(port, SCSCR, ctrl | SCSCR_TIE); 1387 } 1388 } 1389 1390 static void sci_stop_tx(struct uart_port *port) 1391 { 1392 unsigned short ctrl; 1393 1394 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1395 ctrl = sci_in(port, SCSCR); 1396 1397 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1398 ctrl &= ~0x8000; 1399 1400 ctrl &= ~SCSCR_TIE; 1401 1402 sci_out(port, SCSCR, ctrl); 1403 } 1404 1405 static void sci_start_rx(struct uart_port *port) 1406 { 1407 unsigned short ctrl; 1408 1409 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port); 1410 1411 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1412 ctrl &= ~0x4000; 1413 1414 sci_out(port, SCSCR, ctrl); 1415 } 1416 1417 static void sci_stop_rx(struct uart_port *port) 1418 { 1419 unsigned short ctrl; 1420 1421 ctrl = sci_in(port, SCSCR); 1422 1423 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1424 ctrl &= ~0x4000; 1425 1426 ctrl &= ~port_rx_irq_mask(port); 1427 1428 sci_out(port, SCSCR, ctrl); 1429 } 1430 1431 static void sci_enable_ms(struct uart_port *port) 1432 { 1433 /* Nothing here yet .. */ 1434 } 1435 1436 static void sci_break_ctl(struct uart_port *port, int break_state) 1437 { 1438 /* Nothing here yet .. */ 1439 } 1440 1441 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1442 static bool filter(struct dma_chan *chan, void *slave) 1443 { 1444 struct sh_dmae_slave *param = slave; 1445 1446 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, 1447 param->slave_id); 1448 1449 chan->private = param; 1450 return true; 1451 } 1452 1453 static void rx_timer_fn(unsigned long arg) 1454 { 1455 struct sci_port *s = (struct sci_port *)arg; 1456 struct uart_port *port = &s->port; 1457 u16 scr = sci_in(port, SCSCR); 1458 1459 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1460 scr &= ~0x4000; 1461 enable_irq(s->cfg->irqs[1]); 1462 } 1463 sci_out(port, SCSCR, scr | SCSCR_RIE); 1464 dev_dbg(port->dev, "DMA Rx timed out\n"); 1465 schedule_work(&s->work_rx); 1466 } 1467 1468 static void sci_request_dma(struct uart_port *port) 1469 { 1470 struct sci_port *s = to_sci_port(port); 1471 struct sh_dmae_slave *param; 1472 struct dma_chan *chan; 1473 dma_cap_mask_t mask; 1474 int nent; 1475 1476 dev_dbg(port->dev, "%s: port %d\n", __func__, 1477 port->line); 1478 1479 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0) 1480 return; 1481 1482 dma_cap_zero(mask); 1483 dma_cap_set(DMA_SLAVE, mask); 1484 1485 param = &s->param_tx; 1486 1487 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ 1488 param->slave_id = s->cfg->dma_slave_tx; 1489 1490 s->cookie_tx = -EINVAL; 1491 chan = dma_request_channel(mask, filter, param); 1492 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1493 if (chan) { 1494 s->chan_tx = chan; 1495 sg_init_table(&s->sg_tx, 1); 1496 /* UART circular tx buffer is an aligned page. */ 1497 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 1498 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), 1499 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); 1500 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); 1501 if (!nent) 1502 sci_tx_dma_release(s, false); 1503 else 1504 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1505 sg_dma_len(&s->sg_tx), 1506 port->state->xmit.buf, sg_dma_address(&s->sg_tx)); 1507 1508 s->sg_len_tx = nent; 1509 1510 INIT_WORK(&s->work_tx, work_fn_tx); 1511 } 1512 1513 param = &s->param_rx; 1514 1515 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ 1516 param->slave_id = s->cfg->dma_slave_rx; 1517 1518 chan = dma_request_channel(mask, filter, param); 1519 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1520 if (chan) { 1521 dma_addr_t dma[2]; 1522 void *buf[2]; 1523 int i; 1524 1525 s->chan_rx = chan; 1526 1527 s->buf_len_rx = 2 * max(16, (int)port->fifosize); 1528 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, 1529 &dma[0], GFP_KERNEL); 1530 1531 if (!buf[0]) { 1532 dev_warn(port->dev, 1533 "failed to allocate dma buffer, using PIO\n"); 1534 sci_rx_dma_release(s, true); 1535 return; 1536 } 1537 1538 buf[1] = buf[0] + s->buf_len_rx; 1539 dma[1] = dma[0] + s->buf_len_rx; 1540 1541 for (i = 0; i < 2; i++) { 1542 struct scatterlist *sg = &s->sg_rx[i]; 1543 1544 sg_init_table(sg, 1); 1545 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, 1546 (int)buf[i] & ~PAGE_MASK); 1547 sg_dma_address(sg) = dma[i]; 1548 } 1549 1550 INIT_WORK(&s->work_rx, work_fn_rx); 1551 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1552 1553 sci_submit_rx(s); 1554 } 1555 } 1556 1557 static void sci_free_dma(struct uart_port *port) 1558 { 1559 struct sci_port *s = to_sci_port(port); 1560 1561 if (s->chan_tx) 1562 sci_tx_dma_release(s, false); 1563 if (s->chan_rx) 1564 sci_rx_dma_release(s, false); 1565 } 1566 #else 1567 static inline void sci_request_dma(struct uart_port *port) 1568 { 1569 } 1570 1571 static inline void sci_free_dma(struct uart_port *port) 1572 { 1573 } 1574 #endif 1575 1576 static int sci_startup(struct uart_port *port) 1577 { 1578 struct sci_port *s = to_sci_port(port); 1579 int ret; 1580 1581 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1582 1583 sci_port_enable(s); 1584 1585 ret = sci_request_irq(s); 1586 if (unlikely(ret < 0)) 1587 return ret; 1588 1589 sci_request_dma(port); 1590 1591 sci_start_tx(port); 1592 sci_start_rx(port); 1593 1594 return 0; 1595 } 1596 1597 static void sci_shutdown(struct uart_port *port) 1598 { 1599 struct sci_port *s = to_sci_port(port); 1600 1601 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1602 1603 sci_stop_rx(port); 1604 sci_stop_tx(port); 1605 1606 sci_free_dma(port); 1607 sci_free_irq(s); 1608 1609 sci_port_disable(s); 1610 } 1611 1612 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, 1613 unsigned long freq) 1614 { 1615 switch (algo_id) { 1616 case SCBRR_ALGO_1: 1617 return ((freq + 16 * bps) / (16 * bps) - 1); 1618 case SCBRR_ALGO_2: 1619 return ((freq + 16 * bps) / (32 * bps) - 1); 1620 case SCBRR_ALGO_3: 1621 return (((freq * 2) + 16 * bps) / (16 * bps) - 1); 1622 case SCBRR_ALGO_4: 1623 return (((freq * 2) + 16 * bps) / (32 * bps) - 1); 1624 case SCBRR_ALGO_5: 1625 return (((freq * 1000 / 32) / bps) - 1); 1626 } 1627 1628 /* Warn, but use a safe default */ 1629 WARN_ON(1); 1630 1631 return ((freq + 16 * bps) / (32 * bps) - 1); 1632 } 1633 1634 static void sci_reset(struct uart_port *port) 1635 { 1636 unsigned int status; 1637 1638 do { 1639 status = sci_in(port, SCxSR); 1640 } while (!(status & SCxSR_TEND(port))); 1641 1642 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1643 1644 if (port->type != PORT_SCI) 1645 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1646 } 1647 1648 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1649 struct ktermios *old) 1650 { 1651 struct sci_port *s = to_sci_port(port); 1652 unsigned int baud, smr_val, max_baud; 1653 int t = -1; 1654 u16 scfcr = 0; 1655 1656 /* 1657 * earlyprintk comes here early on with port->uartclk set to zero. 1658 * the clock framework is not up and running at this point so here 1659 * we assume that 115200 is the maximum baud rate. please note that 1660 * the baud rate is not programmed during earlyprintk - it is assumed 1661 * that the previous boot loader has enabled required clocks and 1662 * setup the baud rate generator hardware for us already. 1663 */ 1664 max_baud = port->uartclk ? port->uartclk / 16 : 115200; 1665 1666 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1667 if (likely(baud && port->uartclk)) 1668 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); 1669 1670 sci_port_enable(s); 1671 1672 sci_reset(port); 1673 1674 smr_val = sci_in(port, SCSMR) & 3; 1675 1676 if ((termios->c_cflag & CSIZE) == CS7) 1677 smr_val |= 0x40; 1678 if (termios->c_cflag & PARENB) 1679 smr_val |= 0x20; 1680 if (termios->c_cflag & PARODD) 1681 smr_val |= 0x30; 1682 if (termios->c_cflag & CSTOPB) 1683 smr_val |= 0x08; 1684 1685 uart_update_timeout(port, termios->c_cflag, baud); 1686 1687 sci_out(port, SCSMR, smr_val); 1688 1689 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t, 1690 s->cfg->scscr); 1691 1692 if (t > 0) { 1693 if (t >= 256) { 1694 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); 1695 t >>= 2; 1696 } else 1697 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); 1698 1699 sci_out(port, SCBRR, t); 1700 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1701 } 1702 1703 sci_init_pins(port, termios->c_cflag); 1704 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0)); 1705 1706 sci_out(port, SCSCR, s->cfg->scscr); 1707 1708 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1709 /* 1710 * Calculate delay for 1.5 DMA buffers: see 1711 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits 1712 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function 1713 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." 1714 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO 1715 * sizes), but it has been found out experimentally, that this is not 1716 * enough: the driver too often needlessly runs on a DMA timeout. 20ms 1717 * as a minimum seem to work perfectly. 1718 */ 1719 if (s->chan_rx) { 1720 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / 1721 port->fifosize / 2; 1722 dev_dbg(port->dev, 1723 "DMA Rx t-out %ums, tty t-out %u jiffies\n", 1724 s->rx_timeout * 1000 / HZ, port->timeout); 1725 if (s->rx_timeout < msecs_to_jiffies(20)) 1726 s->rx_timeout = msecs_to_jiffies(20); 1727 } 1728 #endif 1729 1730 if ((termios->c_cflag & CREAD) != 0) 1731 sci_start_rx(port); 1732 1733 sci_port_disable(s); 1734 } 1735 1736 static const char *sci_type(struct uart_port *port) 1737 { 1738 switch (port->type) { 1739 case PORT_IRDA: 1740 return "irda"; 1741 case PORT_SCI: 1742 return "sci"; 1743 case PORT_SCIF: 1744 return "scif"; 1745 case PORT_SCIFA: 1746 return "scifa"; 1747 case PORT_SCIFB: 1748 return "scifb"; 1749 } 1750 1751 return NULL; 1752 } 1753 1754 static inline unsigned long sci_port_size(struct uart_port *port) 1755 { 1756 /* 1757 * Pick an arbitrary size that encapsulates all of the base 1758 * registers by default. This can be optimized later, or derived 1759 * from platform resource data at such a time that ports begin to 1760 * behave more erratically. 1761 */ 1762 return 64; 1763 } 1764 1765 static int sci_remap_port(struct uart_port *port) 1766 { 1767 unsigned long size = sci_port_size(port); 1768 1769 /* 1770 * Nothing to do if there's already an established membase. 1771 */ 1772 if (port->membase) 1773 return 0; 1774 1775 if (port->flags & UPF_IOREMAP) { 1776 port->membase = ioremap_nocache(port->mapbase, size); 1777 if (unlikely(!port->membase)) { 1778 dev_err(port->dev, "can't remap port#%d\n", port->line); 1779 return -ENXIO; 1780 } 1781 } else { 1782 /* 1783 * For the simple (and majority of) cases where we don't 1784 * need to do any remapping, just cast the cookie 1785 * directly. 1786 */ 1787 port->membase = (void __iomem *)port->mapbase; 1788 } 1789 1790 return 0; 1791 } 1792 1793 static void sci_release_port(struct uart_port *port) 1794 { 1795 if (port->flags & UPF_IOREMAP) { 1796 iounmap(port->membase); 1797 port->membase = NULL; 1798 } 1799 1800 release_mem_region(port->mapbase, sci_port_size(port)); 1801 } 1802 1803 static int sci_request_port(struct uart_port *port) 1804 { 1805 unsigned long size = sci_port_size(port); 1806 struct resource *res; 1807 int ret; 1808 1809 res = request_mem_region(port->mapbase, size, dev_name(port->dev)); 1810 if (unlikely(res == NULL)) 1811 return -EBUSY; 1812 1813 ret = sci_remap_port(port); 1814 if (unlikely(ret != 0)) { 1815 release_resource(res); 1816 return ret; 1817 } 1818 1819 return 0; 1820 } 1821 1822 static void sci_config_port(struct uart_port *port, int flags) 1823 { 1824 if (flags & UART_CONFIG_TYPE) { 1825 struct sci_port *sport = to_sci_port(port); 1826 1827 port->type = sport->cfg->type; 1828 sci_request_port(port); 1829 } 1830 } 1831 1832 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 1833 { 1834 struct sci_port *s = to_sci_port(port); 1835 1836 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) 1837 return -EINVAL; 1838 if (ser->baud_base < 2400) 1839 /* No paper tape reader for Mitch.. */ 1840 return -EINVAL; 1841 1842 return 0; 1843 } 1844 1845 static struct uart_ops sci_uart_ops = { 1846 .tx_empty = sci_tx_empty, 1847 .set_mctrl = sci_set_mctrl, 1848 .get_mctrl = sci_get_mctrl, 1849 .start_tx = sci_start_tx, 1850 .stop_tx = sci_stop_tx, 1851 .stop_rx = sci_stop_rx, 1852 .enable_ms = sci_enable_ms, 1853 .break_ctl = sci_break_ctl, 1854 .startup = sci_startup, 1855 .shutdown = sci_shutdown, 1856 .set_termios = sci_set_termios, 1857 .type = sci_type, 1858 .release_port = sci_release_port, 1859 .request_port = sci_request_port, 1860 .config_port = sci_config_port, 1861 .verify_port = sci_verify_port, 1862 #ifdef CONFIG_CONSOLE_POLL 1863 .poll_get_char = sci_poll_get_char, 1864 .poll_put_char = sci_poll_put_char, 1865 #endif 1866 }; 1867 1868 static int __devinit sci_init_single(struct platform_device *dev, 1869 struct sci_port *sci_port, 1870 unsigned int index, 1871 struct plat_sci_port *p) 1872 { 1873 struct uart_port *port = &sci_port->port; 1874 int ret; 1875 1876 port->ops = &sci_uart_ops; 1877 port->iotype = UPIO_MEM; 1878 port->line = index; 1879 1880 switch (p->type) { 1881 case PORT_SCIFB: 1882 port->fifosize = 256; 1883 break; 1884 case PORT_SCIFA: 1885 port->fifosize = 64; 1886 break; 1887 case PORT_SCIF: 1888 port->fifosize = 16; 1889 break; 1890 default: 1891 port->fifosize = 1; 1892 break; 1893 } 1894 1895 if (p->regtype == SCIx_PROBE_REGTYPE) { 1896 ret = sci_probe_regmap(p); 1897 if (unlikely(ret)) 1898 return ret; 1899 } 1900 1901 if (dev) { 1902 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 1903 if (IS_ERR(sci_port->iclk)) { 1904 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); 1905 if (IS_ERR(sci_port->iclk)) { 1906 dev_err(&dev->dev, "can't get iclk\n"); 1907 return PTR_ERR(sci_port->iclk); 1908 } 1909 } 1910 1911 /* 1912 * The function clock is optional, ignore it if we can't 1913 * find it. 1914 */ 1915 sci_port->fclk = clk_get(&dev->dev, "sci_fck"); 1916 if (IS_ERR(sci_port->fclk)) 1917 sci_port->fclk = NULL; 1918 1919 port->dev = &dev->dev; 1920 1921 pm_runtime_irq_safe(&dev->dev); 1922 pm_runtime_enable(&dev->dev); 1923 } 1924 1925 sci_port->break_timer.data = (unsigned long)sci_port; 1926 sci_port->break_timer.function = sci_break_timer; 1927 init_timer(&sci_port->break_timer); 1928 1929 /* 1930 * Establish some sensible defaults for the error detection. 1931 */ 1932 if (!p->error_mask) 1933 p->error_mask = (p->type == PORT_SCI) ? 1934 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; 1935 1936 /* 1937 * Establish sensible defaults for the overrun detection, unless 1938 * the part has explicitly disabled support for it. 1939 */ 1940 if (p->overrun_bit != SCIx_NOT_SUPPORTED) { 1941 if (p->type == PORT_SCI) 1942 p->overrun_bit = 5; 1943 else if (p->scbrr_algo_id == SCBRR_ALGO_4) 1944 p->overrun_bit = 9; 1945 else 1946 p->overrun_bit = 0; 1947 1948 /* 1949 * Make the error mask inclusive of overrun detection, if 1950 * supported. 1951 */ 1952 p->error_mask |= (1 << p->overrun_bit); 1953 } 1954 1955 sci_port->cfg = p; 1956 1957 port->mapbase = p->mapbase; 1958 port->type = p->type; 1959 port->flags = p->flags; 1960 port->regshift = p->regshift; 1961 1962 /* 1963 * The UART port needs an IRQ value, so we peg this to the RX IRQ 1964 * for the multi-IRQ ports, which is where we are primarily 1965 * concerned with the shutdown path synchronization. 1966 * 1967 * For the muxed case there's nothing more to do. 1968 */ 1969 port->irq = p->irqs[SCIx_RXI_IRQ]; 1970 port->irqflags = 0; 1971 1972 port->serial_in = sci_serial_in; 1973 port->serial_out = sci_serial_out; 1974 1975 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) 1976 dev_dbg(port->dev, "DMA tx %d, rx %d\n", 1977 p->dma_slave_tx, p->dma_slave_rx); 1978 1979 return 0; 1980 } 1981 1982 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1983 static void serial_console_putchar(struct uart_port *port, int ch) 1984 { 1985 sci_poll_put_char(port, ch); 1986 } 1987 1988 /* 1989 * Print a string to the serial port trying not to disturb 1990 * any possible real use of the port... 1991 */ 1992 static void serial_console_write(struct console *co, const char *s, 1993 unsigned count) 1994 { 1995 struct sci_port *sci_port = &sci_ports[co->index]; 1996 struct uart_port *port = &sci_port->port; 1997 unsigned short bits; 1998 1999 sci_port_enable(sci_port); 2000 2001 uart_console_write(port, s, count, serial_console_putchar); 2002 2003 /* wait until fifo is empty and last bit has been transmitted */ 2004 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2005 while ((sci_in(port, SCxSR) & bits) != bits) 2006 cpu_relax(); 2007 2008 sci_port_disable(sci_port); 2009 } 2010 2011 static int __devinit serial_console_setup(struct console *co, char *options) 2012 { 2013 struct sci_port *sci_port; 2014 struct uart_port *port; 2015 int baud = 115200; 2016 int bits = 8; 2017 int parity = 'n'; 2018 int flow = 'n'; 2019 int ret; 2020 2021 /* 2022 * Refuse to handle any bogus ports. 2023 */ 2024 if (co->index < 0 || co->index >= SCI_NPORTS) 2025 return -ENODEV; 2026 2027 sci_port = &sci_ports[co->index]; 2028 port = &sci_port->port; 2029 2030 /* 2031 * Refuse to handle uninitialized ports. 2032 */ 2033 if (!port->ops) 2034 return -ENODEV; 2035 2036 ret = sci_remap_port(port); 2037 if (unlikely(ret != 0)) 2038 return ret; 2039 2040 sci_port_enable(sci_port); 2041 2042 if (options) 2043 uart_parse_options(options, &baud, &parity, &bits, &flow); 2044 2045 sci_port_disable(sci_port); 2046 2047 return uart_set_options(port, co, baud, parity, bits, flow); 2048 } 2049 2050 static struct console serial_console = { 2051 .name = "ttySC", 2052 .device = uart_console_device, 2053 .write = serial_console_write, 2054 .setup = serial_console_setup, 2055 .flags = CON_PRINTBUFFER, 2056 .index = -1, 2057 .data = &sci_uart_driver, 2058 }; 2059 2060 static struct console early_serial_console = { 2061 .name = "early_ttySC", 2062 .write = serial_console_write, 2063 .flags = CON_PRINTBUFFER, 2064 .index = -1, 2065 }; 2066 2067 static char early_serial_buf[32]; 2068 2069 static int __devinit sci_probe_earlyprintk(struct platform_device *pdev) 2070 { 2071 struct plat_sci_port *cfg = pdev->dev.platform_data; 2072 2073 if (early_serial_console.data) 2074 return -EEXIST; 2075 2076 early_serial_console.index = pdev->id; 2077 2078 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg); 2079 2080 serial_console_setup(&early_serial_console, early_serial_buf); 2081 2082 if (!strstr(early_serial_buf, "keep")) 2083 early_serial_console.flags |= CON_BOOT; 2084 2085 register_console(&early_serial_console); 2086 return 0; 2087 } 2088 2089 #define uart_console(port) ((port)->cons->index == (port)->line) 2090 2091 static int sci_runtime_suspend(struct device *dev) 2092 { 2093 struct sci_port *sci_port = dev_get_drvdata(dev); 2094 struct uart_port *port = &sci_port->port; 2095 2096 if (uart_console(port)) { 2097 sci_port->saved_smr = sci_in(port, SCSMR); 2098 sci_port->saved_brr = sci_in(port, SCBRR); 2099 sci_port->saved_fcr = sci_in(port, SCFCR); 2100 } 2101 return 0; 2102 } 2103 2104 static int sci_runtime_resume(struct device *dev) 2105 { 2106 struct sci_port *sci_port = dev_get_drvdata(dev); 2107 struct uart_port *port = &sci_port->port; 2108 2109 if (uart_console(port)) { 2110 sci_reset(port); 2111 sci_out(port, SCSMR, sci_port->saved_smr); 2112 sci_out(port, SCBRR, sci_port->saved_brr); 2113 sci_out(port, SCFCR, sci_port->saved_fcr); 2114 sci_out(port, SCSCR, sci_port->cfg->scscr); 2115 } 2116 return 0; 2117 } 2118 2119 #define SCI_CONSOLE (&serial_console) 2120 2121 #else 2122 static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev) 2123 { 2124 return -EINVAL; 2125 } 2126 2127 #define SCI_CONSOLE NULL 2128 #define sci_runtime_suspend NULL 2129 #define sci_runtime_resume NULL 2130 2131 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 2132 2133 static char banner[] __initdata = 2134 KERN_INFO "SuperH SCI(F) driver initialized\n"; 2135 2136 static struct uart_driver sci_uart_driver = { 2137 .owner = THIS_MODULE, 2138 .driver_name = "sci", 2139 .dev_name = "ttySC", 2140 .major = SCI_MAJOR, 2141 .minor = SCI_MINOR_START, 2142 .nr = SCI_NPORTS, 2143 .cons = SCI_CONSOLE, 2144 }; 2145 2146 static int sci_remove(struct platform_device *dev) 2147 { 2148 struct sci_port *port = platform_get_drvdata(dev); 2149 2150 cpufreq_unregister_notifier(&port->freq_transition, 2151 CPUFREQ_TRANSITION_NOTIFIER); 2152 2153 uart_remove_one_port(&sci_uart_driver, &port->port); 2154 2155 clk_put(port->iclk); 2156 clk_put(port->fclk); 2157 2158 pm_runtime_disable(&dev->dev); 2159 return 0; 2160 } 2161 2162 static int __devinit sci_probe_single(struct platform_device *dev, 2163 unsigned int index, 2164 struct plat_sci_port *p, 2165 struct sci_port *sciport) 2166 { 2167 int ret; 2168 2169 /* Sanity check */ 2170 if (unlikely(index >= SCI_NPORTS)) { 2171 dev_notice(&dev->dev, "Attempting to register port " 2172 "%d when only %d are available.\n", 2173 index+1, SCI_NPORTS); 2174 dev_notice(&dev->dev, "Consider bumping " 2175 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 2176 return 0; 2177 } 2178 2179 ret = sci_init_single(dev, sciport, index, p); 2180 if (ret) 2181 return ret; 2182 2183 return uart_add_one_port(&sci_uart_driver, &sciport->port); 2184 } 2185 2186 static int __devinit sci_probe(struct platform_device *dev) 2187 { 2188 struct plat_sci_port *p = dev->dev.platform_data; 2189 struct sci_port *sp = &sci_ports[dev->id]; 2190 int ret; 2191 2192 /* 2193 * If we've come here via earlyprintk initialization, head off to 2194 * the special early probe. We don't have sufficient device state 2195 * to make it beyond this yet. 2196 */ 2197 if (is_early_platform_device(dev)) 2198 return sci_probe_earlyprintk(dev); 2199 2200 platform_set_drvdata(dev, sp); 2201 2202 ret = sci_probe_single(dev, dev->id, p, sp); 2203 if (ret) 2204 goto err_unreg; 2205 2206 sp->freq_transition.notifier_call = sci_notifier; 2207 2208 ret = cpufreq_register_notifier(&sp->freq_transition, 2209 CPUFREQ_TRANSITION_NOTIFIER); 2210 if (unlikely(ret < 0)) 2211 goto err_unreg; 2212 2213 #ifdef CONFIG_SH_STANDARD_BIOS 2214 sh_bios_gdb_detach(); 2215 #endif 2216 2217 return 0; 2218 2219 err_unreg: 2220 sci_remove(dev); 2221 return ret; 2222 } 2223 2224 static int sci_suspend(struct device *dev) 2225 { 2226 struct sci_port *sport = dev_get_drvdata(dev); 2227 2228 if (sport) 2229 uart_suspend_port(&sci_uart_driver, &sport->port); 2230 2231 return 0; 2232 } 2233 2234 static int sci_resume(struct device *dev) 2235 { 2236 struct sci_port *sport = dev_get_drvdata(dev); 2237 2238 if (sport) 2239 uart_resume_port(&sci_uart_driver, &sport->port); 2240 2241 return 0; 2242 } 2243 2244 static const struct dev_pm_ops sci_dev_pm_ops = { 2245 .runtime_suspend = sci_runtime_suspend, 2246 .runtime_resume = sci_runtime_resume, 2247 .suspend = sci_suspend, 2248 .resume = sci_resume, 2249 }; 2250 2251 static struct platform_driver sci_driver = { 2252 .probe = sci_probe, 2253 .remove = sci_remove, 2254 .driver = { 2255 .name = "sh-sci", 2256 .owner = THIS_MODULE, 2257 .pm = &sci_dev_pm_ops, 2258 }, 2259 }; 2260 2261 static int __init sci_init(void) 2262 { 2263 int ret; 2264 2265 printk(banner); 2266 2267 ret = uart_register_driver(&sci_uart_driver); 2268 if (likely(ret == 0)) { 2269 ret = platform_driver_register(&sci_driver); 2270 if (unlikely(ret)) 2271 uart_unregister_driver(&sci_uart_driver); 2272 } 2273 2274 return ret; 2275 } 2276 2277 static void __exit sci_exit(void) 2278 { 2279 platform_driver_unregister(&sci_driver); 2280 uart_unregister_driver(&sci_uart_driver); 2281 } 2282 2283 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2284 early_platform_init_buffer("earlyprintk", &sci_driver, 2285 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 2286 #endif 2287 module_init(sci_init); 2288 module_exit(sci_exit); 2289 2290 MODULE_LICENSE("GPL"); 2291 MODULE_ALIAS("platform:sh-sci"); 2292 MODULE_AUTHOR("Paul Mundt"); 2293 MODULE_DESCRIPTION("SuperH SCI(F) serial driver"); 2294