1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/minmax.h> 35 #include <linux/module.h> 36 #include <linux/mm.h> 37 #include <linux/of.h> 38 #include <linux/platform_device.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/reset.h> 41 #include <linux/scatterlist.h> 42 #include <linux/serial.h> 43 #include <linux/serial_sci.h> 44 #include <linux/sh_dma.h> 45 #include <linux/slab.h> 46 #include <linux/string.h> 47 #include <linux/sysrq.h> 48 #include <linux/timer.h> 49 #include <linux/tty.h> 50 #include <linux/tty_flip.h> 51 52 #ifdef CONFIG_SUPERH 53 #include <asm/sh_bios.h> 54 #include <asm/platform_early.h> 55 #endif 56 57 #include "serial_mctrl_gpio.h" 58 #include "sh-sci.h" 59 60 /* Offsets into the sci_port->irqs array */ 61 enum { 62 SCIx_ERI_IRQ, 63 SCIx_RXI_IRQ, 64 SCIx_TXI_IRQ, 65 SCIx_BRI_IRQ, 66 SCIx_DRI_IRQ, 67 SCIx_TEI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71 }; 72 73 #define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79 enum SCI_CLKS { 80 SCI_FCK, /* Functional Clock */ 81 SCI_SCK, /* Optional External Clock */ 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 84 SCI_NUM_CLKS 85 }; 86 87 /* Bit x set means sampling rate x + 1 is supported */ 88 #define SCI_SR(x) BIT((x) - 1) 89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 90 91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 93 SCI_SR(19) | SCI_SR(27) 94 95 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 96 #define max_sr(_port) fls((_port)->sampling_rate_mask) 97 98 /* Iterate over all supported sampling rates, from high to low */ 99 #define for_each_sr(_sr, _port) \ 100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 101 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 102 103 struct plat_sci_reg { 104 u8 offset, size; 105 }; 106 107 struct sci_port_params { 108 const struct plat_sci_reg regs[SCIx_NR_REGS]; 109 unsigned int fifosize; 110 unsigned int overrun_reg; 111 unsigned int overrun_mask; 112 unsigned int sampling_rate_mask; 113 unsigned int error_mask; 114 unsigned int error_clear; 115 }; 116 117 struct sci_port { 118 struct uart_port port; 119 120 /* Platform configuration */ 121 const struct sci_port_params *params; 122 const struct plat_sci_port *cfg; 123 unsigned int sampling_rate_mask; 124 resource_size_t reg_size; 125 struct mctrl_gpios *gpios; 126 127 /* Clocks */ 128 struct clk *clks[SCI_NUM_CLKS]; 129 unsigned long clk_rates[SCI_NUM_CLKS]; 130 131 int irqs[SCIx_NR_IRQS]; 132 char *irqstr[SCIx_NR_IRQS]; 133 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 137 #ifdef CONFIG_SERIAL_SH_SCI_DMA 138 struct dma_chan *chan_tx_saved; 139 struct dma_chan *chan_rx_saved; 140 dma_cookie_t cookie_tx; 141 dma_cookie_t cookie_rx[2]; 142 dma_cookie_t active_rx; 143 dma_addr_t tx_dma_addr; 144 unsigned int tx_dma_len; 145 struct scatterlist sg_rx[2]; 146 void *rx_buf[2]; 147 size_t buf_len_rx; 148 struct work_struct work_tx; 149 struct hrtimer rx_timer; 150 unsigned int rx_timeout; /* microseconds */ 151 #endif 152 unsigned int rx_frame; 153 int rx_trigger; 154 struct timer_list rx_fifo_timer; 155 int rx_fifo_timeout; 156 u16 hscif_tot; 157 158 bool has_rtscts; 159 bool autorts; 160 bool tx_occurred; 161 }; 162 163 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 164 165 static struct sci_port sci_ports[SCI_NPORTS]; 166 static unsigned long sci_ports_in_use; 167 static struct uart_driver sci_uart_driver; 168 169 static inline struct sci_port * 170 to_sci_port(struct uart_port *uart) 171 { 172 return container_of(uart, struct sci_port, port); 173 } 174 175 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 176 /* 177 * Common SCI definitions, dependent on the port's regshift 178 * value. 179 */ 180 [SCIx_SCI_REGTYPE] = { 181 .regs = { 182 [SCSMR] = { 0x00, 8 }, 183 [SCBRR] = { 0x01, 8 }, 184 [SCSCR] = { 0x02, 8 }, 185 [SCxTDR] = { 0x03, 8 }, 186 [SCxSR] = { 0x04, 8 }, 187 [SCxRDR] = { 0x05, 8 }, 188 }, 189 .fifosize = 1, 190 .overrun_reg = SCxSR, 191 .overrun_mask = SCI_ORER, 192 .sampling_rate_mask = SCI_SR(32), 193 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 194 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 195 }, 196 197 /* 198 * Common definitions for legacy IrDA ports. 199 */ 200 [SCIx_IRDA_REGTYPE] = { 201 .regs = { 202 [SCSMR] = { 0x00, 8 }, 203 [SCBRR] = { 0x02, 8 }, 204 [SCSCR] = { 0x04, 8 }, 205 [SCxTDR] = { 0x06, 8 }, 206 [SCxSR] = { 0x08, 16 }, 207 [SCxRDR] = { 0x0a, 8 }, 208 [SCFCR] = { 0x0c, 8 }, 209 [SCFDR] = { 0x0e, 16 }, 210 }, 211 .fifosize = 1, 212 .overrun_reg = SCxSR, 213 .overrun_mask = SCI_ORER, 214 .sampling_rate_mask = SCI_SR(32), 215 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 216 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 217 }, 218 219 /* 220 * Common SCIFA definitions. 221 */ 222 [SCIx_SCIFA_REGTYPE] = { 223 .regs = { 224 [SCSMR] = { 0x00, 16 }, 225 [SCBRR] = { 0x04, 8 }, 226 [SCSCR] = { 0x08, 16 }, 227 [SCxTDR] = { 0x20, 8 }, 228 [SCxSR] = { 0x14, 16 }, 229 [SCxRDR] = { 0x24, 8 }, 230 [SCFCR] = { 0x18, 16 }, 231 [SCFDR] = { 0x1c, 16 }, 232 [SCPCR] = { 0x30, 16 }, 233 [SCPDR] = { 0x34, 16 }, 234 }, 235 .fifosize = 64, 236 .overrun_reg = SCxSR, 237 .overrun_mask = SCIFA_ORER, 238 .sampling_rate_mask = SCI_SR_SCIFAB, 239 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 240 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 241 }, 242 243 /* 244 * Common SCIFB definitions. 245 */ 246 [SCIx_SCIFB_REGTYPE] = { 247 .regs = { 248 [SCSMR] = { 0x00, 16 }, 249 [SCBRR] = { 0x04, 8 }, 250 [SCSCR] = { 0x08, 16 }, 251 [SCxTDR] = { 0x40, 8 }, 252 [SCxSR] = { 0x14, 16 }, 253 [SCxRDR] = { 0x60, 8 }, 254 [SCFCR] = { 0x18, 16 }, 255 [SCTFDR] = { 0x38, 16 }, 256 [SCRFDR] = { 0x3c, 16 }, 257 [SCPCR] = { 0x30, 16 }, 258 [SCPDR] = { 0x34, 16 }, 259 }, 260 .fifosize = 256, 261 .overrun_reg = SCxSR, 262 .overrun_mask = SCIFA_ORER, 263 .sampling_rate_mask = SCI_SR_SCIFAB, 264 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 265 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 266 }, 267 268 /* 269 * Common SH-2(A) SCIF definitions for ports with FIFO data 270 * count registers. 271 */ 272 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 273 .regs = { 274 [SCSMR] = { 0x00, 16 }, 275 [SCBRR] = { 0x04, 8 }, 276 [SCSCR] = { 0x08, 16 }, 277 [SCxTDR] = { 0x0c, 8 }, 278 [SCxSR] = { 0x10, 16 }, 279 [SCxRDR] = { 0x14, 8 }, 280 [SCFCR] = { 0x18, 16 }, 281 [SCFDR] = { 0x1c, 16 }, 282 [SCSPTR] = { 0x20, 16 }, 283 [SCLSR] = { 0x24, 16 }, 284 }, 285 .fifosize = 16, 286 .overrun_reg = SCLSR, 287 .overrun_mask = SCLSR_ORER, 288 .sampling_rate_mask = SCI_SR(32), 289 .error_mask = SCIF_DEFAULT_ERROR_MASK, 290 .error_clear = SCIF_ERROR_CLEAR, 291 }, 292 293 /* 294 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 295 * It looks like a normal SCIF with FIFO data, but with a 296 * compressed address space. Also, the break out of interrupts 297 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 298 */ 299 [SCIx_RZ_SCIFA_REGTYPE] = { 300 .regs = { 301 [SCSMR] = { 0x00, 16 }, 302 [SCBRR] = { 0x02, 8 }, 303 [SCSCR] = { 0x04, 16 }, 304 [SCxTDR] = { 0x06, 8 }, 305 [SCxSR] = { 0x08, 16 }, 306 [SCxRDR] = { 0x0A, 8 }, 307 [SCFCR] = { 0x0C, 16 }, 308 [SCFDR] = { 0x0E, 16 }, 309 [SCSPTR] = { 0x10, 16 }, 310 [SCLSR] = { 0x12, 16 }, 311 [SEMR] = { 0x14, 8 }, 312 }, 313 .fifosize = 16, 314 .overrun_reg = SCLSR, 315 .overrun_mask = SCLSR_ORER, 316 .sampling_rate_mask = SCI_SR(32), 317 .error_mask = SCIF_DEFAULT_ERROR_MASK, 318 .error_clear = SCIF_ERROR_CLEAR, 319 }, 320 321 /* 322 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC 323 * with below differences, 324 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI, 325 * TEI-DRI, RXI-EDGE and TXI-EDGE. 326 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode. 327 * - SCFCR register does not have SCFCR_MCE bit. 328 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO. 329 */ 330 [SCIx_RZV2H_SCIF_REGTYPE] = { 331 .regs = { 332 [SCSMR] = { 0x00, 16 }, 333 [SCBRR] = { 0x02, 8 }, 334 [SCSCR] = { 0x04, 16 }, 335 [SCxTDR] = { 0x06, 8 }, 336 [SCxSR] = { 0x08, 16 }, 337 [SCxRDR] = { 0x0a, 8 }, 338 [SCFCR] = { 0x0c, 16 }, 339 [SCFDR] = { 0x0e, 16 }, 340 [SCSPTR] = { 0x10, 16 }, 341 [SCLSR] = { 0x12, 16 }, 342 [SEMR] = { 0x14, 8 }, 343 }, 344 .fifosize = 16, 345 .overrun_reg = SCLSR, 346 .overrun_mask = SCLSR_ORER, 347 .sampling_rate_mask = SCI_SR(32), 348 .error_mask = SCIF_DEFAULT_ERROR_MASK, 349 .error_clear = SCIF_ERROR_CLEAR, 350 }, 351 352 /* 353 * Common SH-3 SCIF definitions. 354 */ 355 [SCIx_SH3_SCIF_REGTYPE] = { 356 .regs = { 357 [SCSMR] = { 0x00, 8 }, 358 [SCBRR] = { 0x02, 8 }, 359 [SCSCR] = { 0x04, 8 }, 360 [SCxTDR] = { 0x06, 8 }, 361 [SCxSR] = { 0x08, 16 }, 362 [SCxRDR] = { 0x0a, 8 }, 363 [SCFCR] = { 0x0c, 8 }, 364 [SCFDR] = { 0x0e, 16 }, 365 }, 366 .fifosize = 16, 367 .overrun_reg = SCLSR, 368 .overrun_mask = SCLSR_ORER, 369 .sampling_rate_mask = SCI_SR(32), 370 .error_mask = SCIF_DEFAULT_ERROR_MASK, 371 .error_clear = SCIF_ERROR_CLEAR, 372 }, 373 374 /* 375 * Common SH-4(A) SCIF(B) definitions. 376 */ 377 [SCIx_SH4_SCIF_REGTYPE] = { 378 .regs = { 379 [SCSMR] = { 0x00, 16 }, 380 [SCBRR] = { 0x04, 8 }, 381 [SCSCR] = { 0x08, 16 }, 382 [SCxTDR] = { 0x0c, 8 }, 383 [SCxSR] = { 0x10, 16 }, 384 [SCxRDR] = { 0x14, 8 }, 385 [SCFCR] = { 0x18, 16 }, 386 [SCFDR] = { 0x1c, 16 }, 387 [SCSPTR] = { 0x20, 16 }, 388 [SCLSR] = { 0x24, 16 }, 389 }, 390 .fifosize = 16, 391 .overrun_reg = SCLSR, 392 .overrun_mask = SCLSR_ORER, 393 .sampling_rate_mask = SCI_SR(32), 394 .error_mask = SCIF_DEFAULT_ERROR_MASK, 395 .error_clear = SCIF_ERROR_CLEAR, 396 }, 397 398 /* 399 * Common SCIF definitions for ports with a Baud Rate Generator for 400 * External Clock (BRG). 401 */ 402 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 403 .regs = { 404 [SCSMR] = { 0x00, 16 }, 405 [SCBRR] = { 0x04, 8 }, 406 [SCSCR] = { 0x08, 16 }, 407 [SCxTDR] = { 0x0c, 8 }, 408 [SCxSR] = { 0x10, 16 }, 409 [SCxRDR] = { 0x14, 8 }, 410 [SCFCR] = { 0x18, 16 }, 411 [SCFDR] = { 0x1c, 16 }, 412 [SCSPTR] = { 0x20, 16 }, 413 [SCLSR] = { 0x24, 16 }, 414 [SCDL] = { 0x30, 16 }, 415 [SCCKS] = { 0x34, 16 }, 416 }, 417 .fifosize = 16, 418 .overrun_reg = SCLSR, 419 .overrun_mask = SCLSR_ORER, 420 .sampling_rate_mask = SCI_SR(32), 421 .error_mask = SCIF_DEFAULT_ERROR_MASK, 422 .error_clear = SCIF_ERROR_CLEAR, 423 }, 424 425 /* 426 * Common HSCIF definitions. 427 */ 428 [SCIx_HSCIF_REGTYPE] = { 429 .regs = { 430 [SCSMR] = { 0x00, 16 }, 431 [SCBRR] = { 0x04, 8 }, 432 [SCSCR] = { 0x08, 16 }, 433 [SCxTDR] = { 0x0c, 8 }, 434 [SCxSR] = { 0x10, 16 }, 435 [SCxRDR] = { 0x14, 8 }, 436 [SCFCR] = { 0x18, 16 }, 437 [SCFDR] = { 0x1c, 16 }, 438 [SCSPTR] = { 0x20, 16 }, 439 [SCLSR] = { 0x24, 16 }, 440 [HSSRR] = { 0x40, 16 }, 441 [SCDL] = { 0x30, 16 }, 442 [SCCKS] = { 0x34, 16 }, 443 [HSRTRGR] = { 0x54, 16 }, 444 [HSTTRGR] = { 0x58, 16 }, 445 }, 446 .fifosize = 128, 447 .overrun_reg = SCLSR, 448 .overrun_mask = SCLSR_ORER, 449 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 450 .error_mask = SCIF_DEFAULT_ERROR_MASK, 451 .error_clear = SCIF_ERROR_CLEAR, 452 }, 453 454 /* 455 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 456 * register. 457 */ 458 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 459 .regs = { 460 [SCSMR] = { 0x00, 16 }, 461 [SCBRR] = { 0x04, 8 }, 462 [SCSCR] = { 0x08, 16 }, 463 [SCxTDR] = { 0x0c, 8 }, 464 [SCxSR] = { 0x10, 16 }, 465 [SCxRDR] = { 0x14, 8 }, 466 [SCFCR] = { 0x18, 16 }, 467 [SCFDR] = { 0x1c, 16 }, 468 [SCLSR] = { 0x24, 16 }, 469 }, 470 .fifosize = 16, 471 .overrun_reg = SCLSR, 472 .overrun_mask = SCLSR_ORER, 473 .sampling_rate_mask = SCI_SR(32), 474 .error_mask = SCIF_DEFAULT_ERROR_MASK, 475 .error_clear = SCIF_ERROR_CLEAR, 476 }, 477 478 /* 479 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 480 * count registers. 481 */ 482 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 483 .regs = { 484 [SCSMR] = { 0x00, 16 }, 485 [SCBRR] = { 0x04, 8 }, 486 [SCSCR] = { 0x08, 16 }, 487 [SCxTDR] = { 0x0c, 8 }, 488 [SCxSR] = { 0x10, 16 }, 489 [SCxRDR] = { 0x14, 8 }, 490 [SCFCR] = { 0x18, 16 }, 491 [SCFDR] = { 0x1c, 16 }, 492 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 493 [SCRFDR] = { 0x20, 16 }, 494 [SCSPTR] = { 0x24, 16 }, 495 [SCLSR] = { 0x28, 16 }, 496 }, 497 .fifosize = 16, 498 .overrun_reg = SCLSR, 499 .overrun_mask = SCLSR_ORER, 500 .sampling_rate_mask = SCI_SR(32), 501 .error_mask = SCIF_DEFAULT_ERROR_MASK, 502 .error_clear = SCIF_ERROR_CLEAR, 503 }, 504 505 /* 506 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 507 * registers. 508 */ 509 [SCIx_SH7705_SCIF_REGTYPE] = { 510 .regs = { 511 [SCSMR] = { 0x00, 16 }, 512 [SCBRR] = { 0x04, 8 }, 513 [SCSCR] = { 0x08, 16 }, 514 [SCxTDR] = { 0x20, 8 }, 515 [SCxSR] = { 0x14, 16 }, 516 [SCxRDR] = { 0x24, 8 }, 517 [SCFCR] = { 0x18, 16 }, 518 [SCFDR] = { 0x1c, 16 }, 519 }, 520 .fifosize = 64, 521 .overrun_reg = SCxSR, 522 .overrun_mask = SCIFA_ORER, 523 .sampling_rate_mask = SCI_SR(16), 524 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 525 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 526 }, 527 }; 528 529 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 530 531 /* 532 * The "offset" here is rather misleading, in that it refers to an enum 533 * value relative to the port mapping rather than the fixed offset 534 * itself, which needs to be manually retrieved from the platform's 535 * register map for the given port. 536 */ 537 static unsigned int sci_serial_in(struct uart_port *p, int offset) 538 { 539 const struct plat_sci_reg *reg = sci_getreg(p, offset); 540 541 if (reg->size == 8) 542 return ioread8(p->membase + (reg->offset << p->regshift)); 543 else if (reg->size == 16) 544 return ioread16(p->membase + (reg->offset << p->regshift)); 545 else 546 WARN(1, "Invalid register access\n"); 547 548 return 0; 549 } 550 551 static void sci_serial_out(struct uart_port *p, int offset, int value) 552 { 553 const struct plat_sci_reg *reg = sci_getreg(p, offset); 554 555 if (reg->size == 8) 556 iowrite8(value, p->membase + (reg->offset << p->regshift)); 557 else if (reg->size == 16) 558 iowrite16(value, p->membase + (reg->offset << p->regshift)); 559 else 560 WARN(1, "Invalid register access\n"); 561 } 562 563 static void sci_port_enable(struct sci_port *sci_port) 564 { 565 unsigned int i; 566 567 if (!sci_port->port.dev) 568 return; 569 570 pm_runtime_get_sync(sci_port->port.dev); 571 572 for (i = 0; i < SCI_NUM_CLKS; i++) { 573 clk_prepare_enable(sci_port->clks[i]); 574 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 575 } 576 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 577 } 578 579 static void sci_port_disable(struct sci_port *sci_port) 580 { 581 unsigned int i; 582 583 if (!sci_port->port.dev) 584 return; 585 586 for (i = SCI_NUM_CLKS; i-- > 0; ) 587 clk_disable_unprepare(sci_port->clks[i]); 588 589 pm_runtime_put_sync(sci_port->port.dev); 590 } 591 592 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 593 { 594 /* 595 * Not all ports (such as SCIFA) will support REIE. Rather than 596 * special-casing the port type, we check the port initialization 597 * IRQ enable mask to see whether the IRQ is desired at all. If 598 * it's unset, it's logically inferred that there's no point in 599 * testing for it. 600 */ 601 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 602 } 603 604 static void sci_start_tx(struct uart_port *port) 605 { 606 struct sci_port *s = to_sci_port(port); 607 unsigned short ctrl; 608 609 #ifdef CONFIG_SERIAL_SH_SCI_DMA 610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 611 u16 new, scr = sci_serial_in(port, SCSCR); 612 if (s->chan_tx) 613 new = scr | SCSCR_TDRQE; 614 else 615 new = scr & ~SCSCR_TDRQE; 616 if (new != scr) 617 sci_serial_out(port, SCSCR, new); 618 } 619 620 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) && 621 dma_submit_error(s->cookie_tx)) { 622 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 623 /* Switch irq from SCIF to DMA */ 624 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); 625 626 s->cookie_tx = 0; 627 schedule_work(&s->work_tx); 628 } 629 #endif 630 631 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || 632 port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 633 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 634 ctrl = sci_serial_in(port, SCSCR); 635 636 /* 637 * For SCI, TE (transmit enable) must be set after setting TIE 638 * (transmit interrupt enable) or in the same instruction to start 639 * the transmit process. 640 */ 641 if (port->type == PORT_SCI) 642 ctrl |= SCSCR_TE; 643 644 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE); 645 } 646 } 647 648 static void sci_stop_tx(struct uart_port *port) 649 { 650 unsigned short ctrl; 651 652 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 653 ctrl = sci_serial_in(port, SCSCR); 654 655 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 656 ctrl &= ~SCSCR_TDRQE; 657 658 ctrl &= ~SCSCR_TIE; 659 660 sci_serial_out(port, SCSCR, ctrl); 661 662 #ifdef CONFIG_SERIAL_SH_SCI_DMA 663 if (to_sci_port(port)->chan_tx && 664 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 665 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 666 to_sci_port(port)->cookie_tx = -EINVAL; 667 } 668 #endif 669 } 670 671 static void sci_start_rx(struct uart_port *port) 672 { 673 unsigned short ctrl; 674 675 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port); 676 677 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 678 ctrl &= ~SCSCR_RDRQE; 679 680 sci_serial_out(port, SCSCR, ctrl); 681 } 682 683 static void sci_stop_rx(struct uart_port *port) 684 { 685 unsigned short ctrl; 686 687 ctrl = sci_serial_in(port, SCSCR); 688 689 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 690 ctrl &= ~SCSCR_RDRQE; 691 692 ctrl &= ~port_rx_irq_mask(port); 693 694 sci_serial_out(port, SCSCR, ctrl); 695 } 696 697 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 698 { 699 if (port->type == PORT_SCI) { 700 /* Just store the mask */ 701 sci_serial_out(port, SCxSR, mask); 702 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 703 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 704 /* Only clear the status bits we want to clear */ 705 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask); 706 } else { 707 /* Store the mask, clear parity/framing errors */ 708 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 709 } 710 } 711 712 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 713 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 714 715 #ifdef CONFIG_CONSOLE_POLL 716 static int sci_poll_get_char(struct uart_port *port) 717 { 718 unsigned short status; 719 int c; 720 721 do { 722 status = sci_serial_in(port, SCxSR); 723 if (status & SCxSR_ERRORS(port)) { 724 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 725 continue; 726 } 727 break; 728 } while (1); 729 730 if (!(status & SCxSR_RDxF(port))) 731 return NO_POLL_CHAR; 732 733 c = sci_serial_in(port, SCxRDR); 734 735 /* Dummy read */ 736 sci_serial_in(port, SCxSR); 737 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 738 739 return c; 740 } 741 #endif 742 743 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 744 { 745 unsigned short status; 746 747 do { 748 status = sci_serial_in(port, SCxSR); 749 } while (!(status & SCxSR_TDxE(port))); 750 751 sci_serial_out(port, SCxTDR, c); 752 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 753 } 754 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 755 CONFIG_SERIAL_SH_SCI_EARLYCON */ 756 757 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 758 { 759 struct sci_port *s = to_sci_port(port); 760 761 /* 762 * Use port-specific handler if provided. 763 */ 764 if (s->cfg->ops && s->cfg->ops->init_pins) { 765 s->cfg->ops->init_pins(port, cflag); 766 return; 767 } 768 769 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 770 u16 data = sci_serial_in(port, SCPDR); 771 u16 ctrl = sci_serial_in(port, SCPCR); 772 773 /* Enable RXD and TXD pin functions */ 774 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 775 if (to_sci_port(port)->has_rtscts) { 776 /* RTS# is output, active low, unless autorts */ 777 if (!(port->mctrl & TIOCM_RTS)) { 778 ctrl |= SCPCR_RTSC; 779 data |= SCPDR_RTSD; 780 } else if (!s->autorts) { 781 ctrl |= SCPCR_RTSC; 782 data &= ~SCPDR_RTSD; 783 } else { 784 /* Enable RTS# pin function */ 785 ctrl &= ~SCPCR_RTSC; 786 } 787 /* Enable CTS# pin function */ 788 ctrl &= ~SCPCR_CTSC; 789 } 790 sci_serial_out(port, SCPDR, data); 791 sci_serial_out(port, SCPCR, ctrl); 792 } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) { 793 u16 status = sci_serial_in(port, SCSPTR); 794 795 /* RTS# is always output; and active low, unless autorts */ 796 status |= SCSPTR_RTSIO; 797 if (!(port->mctrl & TIOCM_RTS)) 798 status |= SCSPTR_RTSDT; 799 else if (!s->autorts) 800 status &= ~SCSPTR_RTSDT; 801 /* CTS# and SCK are inputs */ 802 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 803 sci_serial_out(port, SCSPTR, status); 804 } 805 } 806 807 static int sci_txfill(struct uart_port *port) 808 { 809 struct sci_port *s = to_sci_port(port); 810 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 811 const struct plat_sci_reg *reg; 812 813 reg = sci_getreg(port, SCTFDR); 814 if (reg->size) 815 return sci_serial_in(port, SCTFDR) & fifo_mask; 816 817 reg = sci_getreg(port, SCFDR); 818 if (reg->size) 819 return sci_serial_in(port, SCFDR) >> 8; 820 821 return !(sci_serial_in(port, SCxSR) & SCI_TDRE); 822 } 823 824 static int sci_txroom(struct uart_port *port) 825 { 826 return port->fifosize - sci_txfill(port); 827 } 828 829 static int sci_rxfill(struct uart_port *port) 830 { 831 struct sci_port *s = to_sci_port(port); 832 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 833 const struct plat_sci_reg *reg; 834 835 reg = sci_getreg(port, SCRFDR); 836 if (reg->size) 837 return sci_serial_in(port, SCRFDR) & fifo_mask; 838 839 reg = sci_getreg(port, SCFDR); 840 if (reg->size) 841 return sci_serial_in(port, SCFDR) & fifo_mask; 842 843 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 844 } 845 846 /* ********************************************************************** * 847 * the interrupt related routines * 848 * ********************************************************************** */ 849 850 static void sci_transmit_chars(struct uart_port *port) 851 { 852 struct tty_port *tport = &port->state->port; 853 unsigned int stopped = uart_tx_stopped(port); 854 struct sci_port *s = to_sci_port(port); 855 unsigned short status; 856 unsigned short ctrl; 857 int count; 858 859 status = sci_serial_in(port, SCxSR); 860 if (!(status & SCxSR_TDxE(port))) { 861 ctrl = sci_serial_in(port, SCSCR); 862 if (kfifo_is_empty(&tport->xmit_fifo)) 863 ctrl &= ~SCSCR_TIE; 864 else 865 ctrl |= SCSCR_TIE; 866 sci_serial_out(port, SCSCR, ctrl); 867 return; 868 } 869 870 count = sci_txroom(port); 871 872 do { 873 unsigned char c; 874 875 if (port->x_char) { 876 c = port->x_char; 877 port->x_char = 0; 878 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { 879 if (port->type == PORT_SCI && 880 kfifo_is_empty(&tport->xmit_fifo)) { 881 ctrl = sci_serial_in(port, SCSCR); 882 ctrl &= ~SCSCR_TE; 883 sci_serial_out(port, SCSCR, ctrl); 884 return; 885 } 886 break; 887 } 888 889 sci_serial_out(port, SCxTDR, c); 890 s->tx_occurred = true; 891 892 port->icount.tx++; 893 } while (--count > 0); 894 895 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 896 897 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 898 uart_write_wakeup(port); 899 if (kfifo_is_empty(&tport->xmit_fifo)) { 900 if (port->type == PORT_SCI) { 901 ctrl = sci_serial_in(port, SCSCR); 902 ctrl &= ~SCSCR_TIE; 903 ctrl |= SCSCR_TEIE; 904 sci_serial_out(port, SCSCR, ctrl); 905 } 906 907 sci_stop_tx(port); 908 } 909 } 910 911 static void sci_receive_chars(struct uart_port *port) 912 { 913 struct tty_port *tport = &port->state->port; 914 int i, count, copied = 0; 915 unsigned short status; 916 unsigned char flag; 917 918 status = sci_serial_in(port, SCxSR); 919 if (!(status & SCxSR_RDxF(port))) 920 return; 921 922 while (1) { 923 /* Don't copy more bytes than there is room for in the buffer */ 924 count = tty_buffer_request_room(tport, sci_rxfill(port)); 925 926 /* If for any reason we can't copy more data, we're done! */ 927 if (count == 0) 928 break; 929 930 if (port->type == PORT_SCI) { 931 char c = sci_serial_in(port, SCxRDR); 932 if (uart_handle_sysrq_char(port, c)) 933 count = 0; 934 else 935 tty_insert_flip_char(tport, c, TTY_NORMAL); 936 } else { 937 for (i = 0; i < count; i++) { 938 char c; 939 940 if (port->type == PORT_SCIF || 941 port->type == PORT_HSCIF) { 942 status = sci_serial_in(port, SCxSR); 943 c = sci_serial_in(port, SCxRDR); 944 } else { 945 c = sci_serial_in(port, SCxRDR); 946 status = sci_serial_in(port, SCxSR); 947 } 948 if (uart_handle_sysrq_char(port, c)) { 949 count--; i--; 950 continue; 951 } 952 953 /* Store data and status */ 954 if (status & SCxSR_FER(port)) { 955 flag = TTY_FRAME; 956 port->icount.frame++; 957 } else if (status & SCxSR_PER(port)) { 958 flag = TTY_PARITY; 959 port->icount.parity++; 960 } else 961 flag = TTY_NORMAL; 962 963 tty_insert_flip_char(tport, c, flag); 964 } 965 } 966 967 sci_serial_in(port, SCxSR); /* dummy read */ 968 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 969 970 copied += count; 971 port->icount.rx += count; 972 } 973 974 if (copied) { 975 /* Tell the rest of the system the news. New characters! */ 976 tty_flip_buffer_push(tport); 977 } else { 978 /* TTY buffers full; read from RX reg to prevent lockup */ 979 sci_serial_in(port, SCxRDR); 980 sci_serial_in(port, SCxSR); /* dummy read */ 981 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 982 } 983 } 984 985 static int sci_handle_errors(struct uart_port *port) 986 { 987 int copied = 0; 988 unsigned short status = sci_serial_in(port, SCxSR); 989 struct tty_port *tport = &port->state->port; 990 struct sci_port *s = to_sci_port(port); 991 992 /* Handle overruns */ 993 if (status & s->params->overrun_mask) { 994 port->icount.overrun++; 995 996 /* overrun error */ 997 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 998 copied++; 999 } 1000 1001 if (status & SCxSR_FER(port)) { 1002 /* frame error */ 1003 port->icount.frame++; 1004 1005 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 1006 copied++; 1007 } 1008 1009 if (status & SCxSR_PER(port)) { 1010 /* parity error */ 1011 port->icount.parity++; 1012 1013 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 1014 copied++; 1015 } 1016 1017 if (copied) 1018 tty_flip_buffer_push(tport); 1019 1020 return copied; 1021 } 1022 1023 static int sci_handle_fifo_overrun(struct uart_port *port) 1024 { 1025 struct tty_port *tport = &port->state->port; 1026 struct sci_port *s = to_sci_port(port); 1027 const struct plat_sci_reg *reg; 1028 int copied = 0; 1029 u16 status; 1030 1031 reg = sci_getreg(port, s->params->overrun_reg); 1032 if (!reg->size) 1033 return 0; 1034 1035 status = sci_serial_in(port, s->params->overrun_reg); 1036 if (status & s->params->overrun_mask) { 1037 status &= ~s->params->overrun_mask; 1038 sci_serial_out(port, s->params->overrun_reg, status); 1039 1040 port->icount.overrun++; 1041 1042 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1043 tty_flip_buffer_push(tport); 1044 copied++; 1045 } 1046 1047 return copied; 1048 } 1049 1050 static int sci_handle_breaks(struct uart_port *port) 1051 { 1052 int copied = 0; 1053 unsigned short status = sci_serial_in(port, SCxSR); 1054 struct tty_port *tport = &port->state->port; 1055 1056 if (uart_handle_break(port)) 1057 return 0; 1058 1059 if (status & SCxSR_BRK(port)) { 1060 port->icount.brk++; 1061 1062 /* Notify of BREAK */ 1063 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1064 copied++; 1065 } 1066 1067 if (copied) 1068 tty_flip_buffer_push(tport); 1069 1070 copied += sci_handle_fifo_overrun(port); 1071 1072 return copied; 1073 } 1074 1075 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1076 { 1077 unsigned int bits; 1078 1079 if (rx_trig >= port->fifosize) 1080 rx_trig = port->fifosize - 1; 1081 if (rx_trig < 1) 1082 rx_trig = 1; 1083 1084 /* HSCIF can be set to an arbitrary level. */ 1085 if (sci_getreg(port, HSRTRGR)->size) { 1086 sci_serial_out(port, HSRTRGR, rx_trig); 1087 return rx_trig; 1088 } 1089 1090 switch (port->type) { 1091 case PORT_SCIF: 1092 if (rx_trig < 4) { 1093 bits = 0; 1094 rx_trig = 1; 1095 } else if (rx_trig < 8) { 1096 bits = SCFCR_RTRG0; 1097 rx_trig = 4; 1098 } else if (rx_trig < 14) { 1099 bits = SCFCR_RTRG1; 1100 rx_trig = 8; 1101 } else { 1102 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1103 rx_trig = 14; 1104 } 1105 break; 1106 case PORT_SCIFA: 1107 case PORT_SCIFB: 1108 if (rx_trig < 16) { 1109 bits = 0; 1110 rx_trig = 1; 1111 } else if (rx_trig < 32) { 1112 bits = SCFCR_RTRG0; 1113 rx_trig = 16; 1114 } else if (rx_trig < 48) { 1115 bits = SCFCR_RTRG1; 1116 rx_trig = 32; 1117 } else { 1118 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1119 rx_trig = 48; 1120 } 1121 break; 1122 default: 1123 WARN(1, "unknown FIFO configuration"); 1124 return 1; 1125 } 1126 1127 sci_serial_out(port, SCFCR, 1128 (sci_serial_in(port, SCFCR) & 1129 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1130 1131 return rx_trig; 1132 } 1133 1134 static int scif_rtrg_enabled(struct uart_port *port) 1135 { 1136 if (sci_getreg(port, HSRTRGR)->size) 1137 return sci_serial_in(port, HSRTRGR) != 0; 1138 else 1139 return (sci_serial_in(port, SCFCR) & 1140 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1141 } 1142 1143 static void rx_fifo_timer_fn(struct timer_list *t) 1144 { 1145 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1146 struct uart_port *port = &s->port; 1147 1148 dev_dbg(port->dev, "Rx timed out\n"); 1149 scif_set_rtrg(port, 1); 1150 } 1151 1152 static ssize_t rx_fifo_trigger_show(struct device *dev, 1153 struct device_attribute *attr, char *buf) 1154 { 1155 struct uart_port *port = dev_get_drvdata(dev); 1156 struct sci_port *sci = to_sci_port(port); 1157 1158 return sprintf(buf, "%d\n", sci->rx_trigger); 1159 } 1160 1161 static ssize_t rx_fifo_trigger_store(struct device *dev, 1162 struct device_attribute *attr, 1163 const char *buf, size_t count) 1164 { 1165 struct uart_port *port = dev_get_drvdata(dev); 1166 struct sci_port *sci = to_sci_port(port); 1167 int ret; 1168 long r; 1169 1170 ret = kstrtol(buf, 0, &r); 1171 if (ret) 1172 return ret; 1173 1174 sci->rx_trigger = scif_set_rtrg(port, r); 1175 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1176 scif_set_rtrg(port, 1); 1177 1178 return count; 1179 } 1180 1181 static DEVICE_ATTR_RW(rx_fifo_trigger); 1182 1183 static ssize_t rx_fifo_timeout_show(struct device *dev, 1184 struct device_attribute *attr, 1185 char *buf) 1186 { 1187 struct uart_port *port = dev_get_drvdata(dev); 1188 struct sci_port *sci = to_sci_port(port); 1189 int v; 1190 1191 if (port->type == PORT_HSCIF) 1192 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1193 else 1194 v = sci->rx_fifo_timeout; 1195 1196 return sprintf(buf, "%d\n", v); 1197 } 1198 1199 static ssize_t rx_fifo_timeout_store(struct device *dev, 1200 struct device_attribute *attr, 1201 const char *buf, 1202 size_t count) 1203 { 1204 struct uart_port *port = dev_get_drvdata(dev); 1205 struct sci_port *sci = to_sci_port(port); 1206 int ret; 1207 long r; 1208 1209 ret = kstrtol(buf, 0, &r); 1210 if (ret) 1211 return ret; 1212 1213 if (port->type == PORT_HSCIF) { 1214 if (r < 0 || r > 3) 1215 return -EINVAL; 1216 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1217 } else { 1218 sci->rx_fifo_timeout = r; 1219 scif_set_rtrg(port, 1); 1220 if (r > 0) 1221 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1222 } 1223 1224 return count; 1225 } 1226 1227 static DEVICE_ATTR_RW(rx_fifo_timeout); 1228 1229 1230 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1231 static void sci_dma_tx_complete(void *arg) 1232 { 1233 struct sci_port *s = arg; 1234 struct uart_port *port = &s->port; 1235 struct tty_port *tport = &port->state->port; 1236 unsigned long flags; 1237 1238 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1239 1240 uart_port_lock_irqsave(port, &flags); 1241 1242 uart_xmit_advance(port, s->tx_dma_len); 1243 1244 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1245 uart_write_wakeup(port); 1246 1247 s->tx_occurred = true; 1248 1249 if (!kfifo_is_empty(&tport->xmit_fifo)) { 1250 s->cookie_tx = 0; 1251 schedule_work(&s->work_tx); 1252 } else { 1253 s->cookie_tx = -EINVAL; 1254 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1255 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1256 u16 ctrl = sci_serial_in(port, SCSCR); 1257 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1258 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1259 /* Switch irq from DMA to SCIF */ 1260 dmaengine_pause(s->chan_tx_saved); 1261 enable_irq(s->irqs[SCIx_TXI_IRQ]); 1262 } 1263 } 1264 } 1265 1266 uart_port_unlock_irqrestore(port, flags); 1267 } 1268 1269 /* Locking: called with port lock held */ 1270 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1271 { 1272 struct uart_port *port = &s->port; 1273 struct tty_port *tport = &port->state->port; 1274 int copied; 1275 1276 copied = tty_insert_flip_string(tport, buf, count); 1277 if (copied < count) 1278 port->icount.buf_overrun++; 1279 1280 port->icount.rx += copied; 1281 1282 return copied; 1283 } 1284 1285 static int sci_dma_rx_find_active(struct sci_port *s) 1286 { 1287 unsigned int i; 1288 1289 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1290 if (s->active_rx == s->cookie_rx[i]) 1291 return i; 1292 1293 return -1; 1294 } 1295 1296 /* Must only be called with uart_port_lock taken */ 1297 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1298 { 1299 unsigned int i; 1300 1301 s->chan_rx = NULL; 1302 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1303 s->cookie_rx[i] = -EINVAL; 1304 s->active_rx = 0; 1305 } 1306 1307 static void sci_dma_rx_release(struct sci_port *s) 1308 { 1309 struct dma_chan *chan = s->chan_rx_saved; 1310 struct uart_port *port = &s->port; 1311 unsigned long flags; 1312 1313 uart_port_lock_irqsave(port, &flags); 1314 s->chan_rx_saved = NULL; 1315 sci_dma_rx_chan_invalidate(s); 1316 uart_port_unlock_irqrestore(port, flags); 1317 1318 dmaengine_terminate_sync(chan); 1319 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1320 sg_dma_address(&s->sg_rx[0])); 1321 dma_release_channel(chan); 1322 } 1323 1324 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1325 { 1326 long sec = usec / 1000000; 1327 long nsec = (usec % 1000000) * 1000; 1328 ktime_t t = ktime_set(sec, nsec); 1329 1330 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1331 } 1332 1333 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1334 { 1335 struct uart_port *port = &s->port; 1336 u16 scr; 1337 1338 /* Direct new serial port interrupts back to CPU */ 1339 scr = sci_serial_in(port, SCSCR); 1340 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1341 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1342 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1343 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1344 scif_set_rtrg(port, s->rx_trigger); 1345 else 1346 scr &= ~SCSCR_RDRQE; 1347 } 1348 sci_serial_out(port, SCSCR, scr | SCSCR_RIE); 1349 } 1350 1351 static void sci_dma_rx_complete(void *arg) 1352 { 1353 struct sci_port *s = arg; 1354 struct dma_chan *chan = s->chan_rx; 1355 struct uart_port *port = &s->port; 1356 struct dma_async_tx_descriptor *desc; 1357 unsigned long flags; 1358 int active, count = 0; 1359 1360 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1361 s->active_rx); 1362 1363 hrtimer_cancel(&s->rx_timer); 1364 1365 uart_port_lock_irqsave(port, &flags); 1366 1367 active = sci_dma_rx_find_active(s); 1368 if (active >= 0) 1369 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1370 1371 if (count) 1372 tty_flip_buffer_push(&port->state->port); 1373 1374 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1375 DMA_DEV_TO_MEM, 1376 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1377 if (!desc) 1378 goto fail; 1379 1380 desc->callback = sci_dma_rx_complete; 1381 desc->callback_param = s; 1382 s->cookie_rx[active] = dmaengine_submit(desc); 1383 if (dma_submit_error(s->cookie_rx[active])) 1384 goto fail; 1385 1386 s->active_rx = s->cookie_rx[!active]; 1387 1388 dma_async_issue_pending(chan); 1389 1390 uart_port_unlock_irqrestore(port, flags); 1391 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1392 __func__, s->cookie_rx[active], active, s->active_rx); 1393 1394 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1395 1396 return; 1397 1398 fail: 1399 /* Switch to PIO */ 1400 dmaengine_terminate_async(chan); 1401 sci_dma_rx_chan_invalidate(s); 1402 sci_dma_rx_reenable_irq(s); 1403 uart_port_unlock_irqrestore(port, flags); 1404 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1405 } 1406 1407 static void sci_dma_tx_release(struct sci_port *s) 1408 { 1409 struct dma_chan *chan = s->chan_tx_saved; 1410 1411 cancel_work_sync(&s->work_tx); 1412 s->chan_tx_saved = s->chan_tx = NULL; 1413 s->cookie_tx = -EINVAL; 1414 dmaengine_terminate_sync(chan); 1415 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1416 DMA_TO_DEVICE); 1417 dma_release_channel(chan); 1418 } 1419 1420 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1421 { 1422 struct dma_chan *chan = s->chan_rx; 1423 struct uart_port *port = &s->port; 1424 unsigned long flags; 1425 int i; 1426 1427 for (i = 0; i < 2; i++) { 1428 struct scatterlist *sg = &s->sg_rx[i]; 1429 struct dma_async_tx_descriptor *desc; 1430 1431 desc = dmaengine_prep_slave_sg(chan, 1432 sg, 1, DMA_DEV_TO_MEM, 1433 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1434 if (!desc) 1435 goto fail; 1436 1437 desc->callback = sci_dma_rx_complete; 1438 desc->callback_param = s; 1439 s->cookie_rx[i] = dmaengine_submit(desc); 1440 if (dma_submit_error(s->cookie_rx[i])) 1441 goto fail; 1442 1443 } 1444 1445 s->active_rx = s->cookie_rx[0]; 1446 1447 dma_async_issue_pending(chan); 1448 return 0; 1449 1450 fail: 1451 /* Switch to PIO */ 1452 if (!port_lock_held) 1453 uart_port_lock_irqsave(port, &flags); 1454 if (i) 1455 dmaengine_terminate_async(chan); 1456 sci_dma_rx_chan_invalidate(s); 1457 sci_start_rx(port); 1458 if (!port_lock_held) 1459 uart_port_unlock_irqrestore(port, flags); 1460 return -EAGAIN; 1461 } 1462 1463 static void sci_dma_tx_work_fn(struct work_struct *work) 1464 { 1465 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1466 struct dma_async_tx_descriptor *desc; 1467 struct dma_chan *chan = s->chan_tx; 1468 struct uart_port *port = &s->port; 1469 struct tty_port *tport = &port->state->port; 1470 unsigned long flags; 1471 unsigned int tail; 1472 dma_addr_t buf; 1473 1474 /* 1475 * DMA is idle now. 1476 * Port xmit buffer is already mapped, and it is one page... Just adjust 1477 * offsets and lengths. Since it is a circular buffer, we have to 1478 * transmit till the end, and then the rest. Take the port lock to get a 1479 * consistent xmit buffer state. 1480 */ 1481 uart_port_lock_irq(port); 1482 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail, 1483 UART_XMIT_SIZE); 1484 buf = s->tx_dma_addr + tail; 1485 if (!s->tx_dma_len) { 1486 /* Transmit buffer has been flushed */ 1487 uart_port_unlock_irq(port); 1488 return; 1489 } 1490 1491 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1492 DMA_MEM_TO_DEV, 1493 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1494 if (!desc) { 1495 uart_port_unlock_irq(port); 1496 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1497 goto switch_to_pio; 1498 } 1499 1500 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1501 DMA_TO_DEVICE); 1502 1503 desc->callback = sci_dma_tx_complete; 1504 desc->callback_param = s; 1505 s->cookie_tx = dmaengine_submit(desc); 1506 if (dma_submit_error(s->cookie_tx)) { 1507 uart_port_unlock_irq(port); 1508 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1509 goto switch_to_pio; 1510 } 1511 1512 uart_port_unlock_irq(port); 1513 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n", 1514 __func__, tport->xmit_buf, tail, s->cookie_tx); 1515 1516 dma_async_issue_pending(chan); 1517 return; 1518 1519 switch_to_pio: 1520 uart_port_lock_irqsave(port, &flags); 1521 s->chan_tx = NULL; 1522 sci_start_tx(port); 1523 uart_port_unlock_irqrestore(port, flags); 1524 return; 1525 } 1526 1527 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1528 { 1529 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1530 struct dma_chan *chan = s->chan_rx; 1531 struct uart_port *port = &s->port; 1532 struct dma_tx_state state; 1533 enum dma_status status; 1534 unsigned long flags; 1535 unsigned int read; 1536 int active, count; 1537 1538 dev_dbg(port->dev, "DMA Rx timed out\n"); 1539 1540 uart_port_lock_irqsave(port, &flags); 1541 1542 active = sci_dma_rx_find_active(s); 1543 if (active < 0) { 1544 uart_port_unlock_irqrestore(port, flags); 1545 return HRTIMER_NORESTART; 1546 } 1547 1548 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1549 if (status == DMA_COMPLETE) { 1550 uart_port_unlock_irqrestore(port, flags); 1551 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1552 s->active_rx, active); 1553 1554 /* Let packet complete handler take care of the packet */ 1555 return HRTIMER_NORESTART; 1556 } 1557 1558 dmaengine_pause(chan); 1559 1560 /* 1561 * sometimes DMA transfer doesn't stop even if it is stopped and 1562 * data keeps on coming until transaction is complete so check 1563 * for DMA_COMPLETE again 1564 * Let packet complete handler take care of the packet 1565 */ 1566 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1567 if (status == DMA_COMPLETE) { 1568 uart_port_unlock_irqrestore(port, flags); 1569 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1570 return HRTIMER_NORESTART; 1571 } 1572 1573 /* Handle incomplete DMA receive */ 1574 dmaengine_terminate_async(s->chan_rx); 1575 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1576 1577 if (read) { 1578 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1579 if (count) 1580 tty_flip_buffer_push(&port->state->port); 1581 } 1582 1583 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1584 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1585 sci_dma_rx_submit(s, true); 1586 1587 sci_dma_rx_reenable_irq(s); 1588 1589 uart_port_unlock_irqrestore(port, flags); 1590 1591 return HRTIMER_NORESTART; 1592 } 1593 1594 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1595 enum dma_transfer_direction dir) 1596 { 1597 struct dma_chan *chan; 1598 struct dma_slave_config cfg; 1599 int ret; 1600 1601 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1602 if (IS_ERR(chan)) { 1603 dev_dbg(port->dev, "dma_request_chan failed\n"); 1604 return NULL; 1605 } 1606 1607 memset(&cfg, 0, sizeof(cfg)); 1608 cfg.direction = dir; 1609 cfg.dst_addr = port->mapbase + 1610 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1611 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1612 cfg.src_addr = port->mapbase + 1613 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1614 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1615 1616 ret = dmaengine_slave_config(chan, &cfg); 1617 if (ret) { 1618 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1619 dma_release_channel(chan); 1620 return NULL; 1621 } 1622 1623 return chan; 1624 } 1625 1626 static void sci_request_dma(struct uart_port *port) 1627 { 1628 struct sci_port *s = to_sci_port(port); 1629 struct tty_port *tport = &port->state->port; 1630 struct dma_chan *chan; 1631 1632 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1633 1634 /* 1635 * DMA on console may interfere with Kernel log messages which use 1636 * plain putchar(). So, simply don't use it with a console. 1637 */ 1638 if (uart_console(port)) 1639 return; 1640 1641 if (!port->dev->of_node) 1642 return; 1643 1644 s->cookie_tx = -EINVAL; 1645 1646 /* 1647 * Don't request a dma channel if no channel was specified 1648 * in the device tree. 1649 */ 1650 if (!of_property_present(port->dev->of_node, "dmas")) 1651 return; 1652 1653 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1654 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1655 if (chan) { 1656 /* UART circular tx buffer is an aligned page. */ 1657 s->tx_dma_addr = dma_map_single(chan->device->dev, 1658 tport->xmit_buf, 1659 UART_XMIT_SIZE, 1660 DMA_TO_DEVICE); 1661 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1662 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1663 dma_release_channel(chan); 1664 } else { 1665 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1666 __func__, UART_XMIT_SIZE, 1667 tport->xmit_buf, &s->tx_dma_addr); 1668 1669 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1670 s->chan_tx_saved = s->chan_tx = chan; 1671 } 1672 } 1673 1674 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1675 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1676 if (chan) { 1677 unsigned int i; 1678 dma_addr_t dma; 1679 void *buf; 1680 1681 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1682 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1683 &dma, GFP_KERNEL); 1684 if (!buf) { 1685 dev_warn(port->dev, 1686 "Failed to allocate Rx dma buffer, using PIO\n"); 1687 dma_release_channel(chan); 1688 return; 1689 } 1690 1691 for (i = 0; i < 2; i++) { 1692 struct scatterlist *sg = &s->sg_rx[i]; 1693 1694 sg_init_table(sg, 1); 1695 s->rx_buf[i] = buf; 1696 sg_dma_address(sg) = dma; 1697 sg_dma_len(sg) = s->buf_len_rx; 1698 1699 buf += s->buf_len_rx; 1700 dma += s->buf_len_rx; 1701 } 1702 1703 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1704 s->rx_timer.function = sci_dma_rx_timer_fn; 1705 1706 s->chan_rx_saved = s->chan_rx = chan; 1707 1708 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1709 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1710 sci_dma_rx_submit(s, false); 1711 } 1712 } 1713 1714 static void sci_free_dma(struct uart_port *port) 1715 { 1716 struct sci_port *s = to_sci_port(port); 1717 1718 if (s->chan_tx_saved) 1719 sci_dma_tx_release(s); 1720 if (s->chan_rx_saved) 1721 sci_dma_rx_release(s); 1722 } 1723 1724 static void sci_flush_buffer(struct uart_port *port) 1725 { 1726 struct sci_port *s = to_sci_port(port); 1727 1728 /* 1729 * In uart_flush_buffer(), the xmit circular buffer has just been 1730 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1731 * pending transfers 1732 */ 1733 s->tx_dma_len = 0; 1734 if (s->chan_tx) { 1735 dmaengine_terminate_async(s->chan_tx); 1736 s->cookie_tx = -EINVAL; 1737 } 1738 } 1739 1740 static void sci_dma_check_tx_occurred(struct sci_port *s) 1741 { 1742 struct dma_tx_state state; 1743 enum dma_status status; 1744 1745 if (!s->chan_tx) 1746 return; 1747 1748 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state); 1749 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS) 1750 s->tx_occurred = true; 1751 } 1752 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1753 static inline void sci_request_dma(struct uart_port *port) 1754 { 1755 } 1756 1757 static inline void sci_free_dma(struct uart_port *port) 1758 { 1759 } 1760 1761 static void sci_dma_check_tx_occurred(struct sci_port *s) 1762 { 1763 } 1764 1765 #define sci_flush_buffer NULL 1766 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1767 1768 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1769 { 1770 struct uart_port *port = ptr; 1771 struct sci_port *s = to_sci_port(port); 1772 1773 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1774 if (s->chan_rx) { 1775 u16 scr = sci_serial_in(port, SCSCR); 1776 u16 ssr = sci_serial_in(port, SCxSR); 1777 1778 /* Disable future Rx interrupts */ 1779 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1780 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1781 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); 1782 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1783 scif_set_rtrg(port, 1); 1784 scr |= SCSCR_RIE; 1785 } else { 1786 scr |= SCSCR_RDRQE; 1787 } 1788 } else { 1789 if (sci_dma_rx_submit(s, false) < 0) 1790 goto handle_pio; 1791 1792 scr &= ~SCSCR_RIE; 1793 } 1794 sci_serial_out(port, SCSCR, scr); 1795 /* Clear current interrupt */ 1796 sci_serial_out(port, SCxSR, 1797 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1798 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1799 jiffies, s->rx_timeout); 1800 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1801 1802 return IRQ_HANDLED; 1803 } 1804 1805 handle_pio: 1806 #endif 1807 1808 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1809 if (!scif_rtrg_enabled(port)) 1810 scif_set_rtrg(port, s->rx_trigger); 1811 1812 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1813 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1814 } 1815 1816 /* I think sci_receive_chars has to be called irrespective 1817 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1818 * to be disabled? 1819 */ 1820 sci_receive_chars(port); 1821 1822 return IRQ_HANDLED; 1823 } 1824 1825 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1826 { 1827 struct uart_port *port = ptr; 1828 unsigned long flags; 1829 1830 uart_port_lock_irqsave(port, &flags); 1831 sci_transmit_chars(port); 1832 uart_port_unlock_irqrestore(port, flags); 1833 1834 return IRQ_HANDLED; 1835 } 1836 1837 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) 1838 { 1839 struct uart_port *port = ptr; 1840 unsigned long flags; 1841 unsigned short ctrl; 1842 1843 if (port->type != PORT_SCI) 1844 return sci_tx_interrupt(irq, ptr); 1845 1846 uart_port_lock_irqsave(port, &flags); 1847 ctrl = sci_serial_in(port, SCSCR); 1848 ctrl &= ~(SCSCR_TE | SCSCR_TEIE); 1849 sci_serial_out(port, SCSCR, ctrl); 1850 uart_port_unlock_irqrestore(port, flags); 1851 1852 return IRQ_HANDLED; 1853 } 1854 1855 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1856 { 1857 struct uart_port *port = ptr; 1858 1859 /* Handle BREAKs */ 1860 sci_handle_breaks(port); 1861 1862 /* drop invalid character received before break was detected */ 1863 sci_serial_in(port, SCxRDR); 1864 1865 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1866 1867 return IRQ_HANDLED; 1868 } 1869 1870 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1871 { 1872 struct uart_port *port = ptr; 1873 struct sci_port *s = to_sci_port(port); 1874 1875 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1876 /* Break and Error interrupts are muxed */ 1877 unsigned short ssr_status = sci_serial_in(port, SCxSR); 1878 1879 /* Break Interrupt */ 1880 if (ssr_status & SCxSR_BRK(port)) 1881 sci_br_interrupt(irq, ptr); 1882 1883 /* Break only? */ 1884 if (!(ssr_status & SCxSR_ERRORS(port))) 1885 return IRQ_HANDLED; 1886 } 1887 1888 /* Handle errors */ 1889 if (port->type == PORT_SCI) { 1890 if (sci_handle_errors(port)) { 1891 /* discard character in rx buffer */ 1892 sci_serial_in(port, SCxSR); 1893 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1894 } 1895 } else { 1896 sci_handle_fifo_overrun(port); 1897 if (!s->chan_rx) 1898 sci_receive_chars(port); 1899 } 1900 1901 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1902 1903 /* Kick the transmission */ 1904 if (!s->chan_tx) 1905 sci_tx_interrupt(irq, ptr); 1906 1907 return IRQ_HANDLED; 1908 } 1909 1910 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1911 { 1912 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1913 struct uart_port *port = ptr; 1914 struct sci_port *s = to_sci_port(port); 1915 irqreturn_t ret = IRQ_NONE; 1916 1917 ssr_status = sci_serial_in(port, SCxSR); 1918 scr_status = sci_serial_in(port, SCSCR); 1919 if (s->params->overrun_reg == SCxSR) 1920 orer_status = ssr_status; 1921 else if (sci_getreg(port, s->params->overrun_reg)->size) 1922 orer_status = sci_serial_in(port, s->params->overrun_reg); 1923 1924 err_enabled = scr_status & port_rx_irq_mask(port); 1925 1926 /* Tx Interrupt */ 1927 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1928 !s->chan_tx) 1929 ret = sci_tx_interrupt(irq, ptr); 1930 1931 /* 1932 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1933 * DR flags 1934 */ 1935 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1936 (scr_status & SCSCR_RIE)) 1937 ret = sci_rx_interrupt(irq, ptr); 1938 1939 /* Error Interrupt */ 1940 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1941 ret = sci_er_interrupt(irq, ptr); 1942 1943 /* Break Interrupt */ 1944 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 1945 (ssr_status & SCxSR_BRK(port)) && err_enabled) 1946 ret = sci_br_interrupt(irq, ptr); 1947 1948 /* Overrun Interrupt */ 1949 if (orer_status & s->params->overrun_mask) { 1950 sci_handle_fifo_overrun(port); 1951 ret = IRQ_HANDLED; 1952 } 1953 1954 return ret; 1955 } 1956 1957 static const struct sci_irq_desc { 1958 const char *desc; 1959 irq_handler_t handler; 1960 } sci_irq_desc[] = { 1961 /* 1962 * Split out handlers, the default case. 1963 */ 1964 [SCIx_ERI_IRQ] = { 1965 .desc = "rx err", 1966 .handler = sci_er_interrupt, 1967 }, 1968 1969 [SCIx_RXI_IRQ] = { 1970 .desc = "rx full", 1971 .handler = sci_rx_interrupt, 1972 }, 1973 1974 [SCIx_TXI_IRQ] = { 1975 .desc = "tx empty", 1976 .handler = sci_tx_interrupt, 1977 }, 1978 1979 [SCIx_BRI_IRQ] = { 1980 .desc = "break", 1981 .handler = sci_br_interrupt, 1982 }, 1983 1984 [SCIx_DRI_IRQ] = { 1985 .desc = "rx ready", 1986 .handler = sci_rx_interrupt, 1987 }, 1988 1989 [SCIx_TEI_IRQ] = { 1990 .desc = "tx end", 1991 .handler = sci_tx_end_interrupt, 1992 }, 1993 1994 /* 1995 * Special muxed handler. 1996 */ 1997 [SCIx_MUX_IRQ] = { 1998 .desc = "mux", 1999 .handler = sci_mpxed_interrupt, 2000 }, 2001 }; 2002 2003 static int sci_request_irq(struct sci_port *port) 2004 { 2005 struct uart_port *up = &port->port; 2006 int i, j, w, ret = 0; 2007 2008 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 2009 const struct sci_irq_desc *desc; 2010 int irq; 2011 2012 /* Check if already registered (muxed) */ 2013 for (w = 0; w < i; w++) 2014 if (port->irqs[w] == port->irqs[i]) 2015 w = i + 1; 2016 if (w > i) 2017 continue; 2018 2019 if (SCIx_IRQ_IS_MUXED(port)) { 2020 i = SCIx_MUX_IRQ; 2021 irq = up->irq; 2022 } else { 2023 irq = port->irqs[i]; 2024 2025 /* 2026 * Certain port types won't support all of the 2027 * available interrupt sources. 2028 */ 2029 if (unlikely(irq < 0)) 2030 continue; 2031 } 2032 2033 desc = sci_irq_desc + i; 2034 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 2035 dev_name(up->dev), desc->desc); 2036 if (!port->irqstr[j]) { 2037 ret = -ENOMEM; 2038 goto out_nomem; 2039 } 2040 2041 ret = request_irq(irq, desc->handler, up->irqflags, 2042 port->irqstr[j], port); 2043 if (unlikely(ret)) { 2044 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 2045 goto out_noirq; 2046 } 2047 } 2048 2049 return 0; 2050 2051 out_noirq: 2052 while (--i >= 0) 2053 free_irq(port->irqs[i], port); 2054 2055 out_nomem: 2056 while (--j >= 0) 2057 kfree(port->irqstr[j]); 2058 2059 return ret; 2060 } 2061 2062 static void sci_free_irq(struct sci_port *port) 2063 { 2064 int i, j; 2065 2066 /* 2067 * Intentionally in reverse order so we iterate over the muxed 2068 * IRQ first. 2069 */ 2070 for (i = 0; i < SCIx_NR_IRQS; i++) { 2071 int irq = port->irqs[i]; 2072 2073 /* 2074 * Certain port types won't support all of the available 2075 * interrupt sources. 2076 */ 2077 if (unlikely(irq < 0)) 2078 continue; 2079 2080 /* Check if already freed (irq was muxed) */ 2081 for (j = 0; j < i; j++) 2082 if (port->irqs[j] == irq) 2083 j = i + 1; 2084 if (j > i) 2085 continue; 2086 2087 free_irq(port->irqs[i], port); 2088 kfree(port->irqstr[i]); 2089 2090 if (SCIx_IRQ_IS_MUXED(port)) { 2091 /* If there's only one IRQ, we're done. */ 2092 return; 2093 } 2094 } 2095 } 2096 2097 static unsigned int sci_tx_empty(struct uart_port *port) 2098 { 2099 unsigned short status = sci_serial_in(port, SCxSR); 2100 unsigned short in_tx_fifo = sci_txfill(port); 2101 struct sci_port *s = to_sci_port(port); 2102 2103 sci_dma_check_tx_occurred(s); 2104 2105 if (!s->tx_occurred) 2106 return TIOCSER_TEMT; 2107 2108 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 2109 } 2110 2111 static void sci_set_rts(struct uart_port *port, bool state) 2112 { 2113 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2114 u16 data = sci_serial_in(port, SCPDR); 2115 2116 /* Active low */ 2117 if (state) 2118 data &= ~SCPDR_RTSD; 2119 else 2120 data |= SCPDR_RTSD; 2121 sci_serial_out(port, SCPDR, data); 2122 2123 /* RTS# is output */ 2124 sci_serial_out(port, SCPCR, 2125 sci_serial_in(port, SCPCR) | SCPCR_RTSC); 2126 } else if (sci_getreg(port, SCSPTR)->size) { 2127 u16 ctrl = sci_serial_in(port, SCSPTR); 2128 2129 /* Active low */ 2130 if (state) 2131 ctrl &= ~SCSPTR_RTSDT; 2132 else 2133 ctrl |= SCSPTR_RTSDT; 2134 sci_serial_out(port, SCSPTR, ctrl); 2135 } 2136 } 2137 2138 static bool sci_get_cts(struct uart_port *port) 2139 { 2140 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2141 /* Active low */ 2142 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD); 2143 } else if (sci_getreg(port, SCSPTR)->size) { 2144 /* Active low */ 2145 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT); 2146 } 2147 2148 return true; 2149 } 2150 2151 /* 2152 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2153 * CTS/RTS is supported in hardware by at least one port and controlled 2154 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2155 * handled via the ->init_pins() op, which is a bit of a one-way street, 2156 * lacking any ability to defer pin control -- this will later be 2157 * converted over to the GPIO framework). 2158 * 2159 * Other modes (such as loopback) are supported generically on certain 2160 * port types, but not others. For these it's sufficient to test for the 2161 * existence of the support register and simply ignore the port type. 2162 */ 2163 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2164 { 2165 struct sci_port *s = to_sci_port(port); 2166 2167 if (mctrl & TIOCM_LOOP) { 2168 const struct plat_sci_reg *reg; 2169 2170 /* 2171 * Standard loopback mode for SCFCR ports. 2172 */ 2173 reg = sci_getreg(port, SCFCR); 2174 if (reg->size) 2175 sci_serial_out(port, SCFCR, 2176 sci_serial_in(port, SCFCR) | SCFCR_LOOP); 2177 } 2178 2179 mctrl_gpio_set(s->gpios, mctrl); 2180 2181 if (!s->has_rtscts) 2182 return; 2183 2184 if (!(mctrl & TIOCM_RTS)) { 2185 /* Disable Auto RTS */ 2186 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2187 sci_serial_out(port, SCFCR, 2188 sci_serial_in(port, SCFCR) & ~SCFCR_MCE); 2189 2190 /* Clear RTS */ 2191 sci_set_rts(port, 0); 2192 } else if (s->autorts) { 2193 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2194 /* Enable RTS# pin function */ 2195 sci_serial_out(port, SCPCR, 2196 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC); 2197 } 2198 2199 /* Enable Auto RTS */ 2200 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2201 sci_serial_out(port, SCFCR, 2202 sci_serial_in(port, SCFCR) | SCFCR_MCE); 2203 } else { 2204 /* Set RTS */ 2205 sci_set_rts(port, 1); 2206 } 2207 } 2208 2209 static unsigned int sci_get_mctrl(struct uart_port *port) 2210 { 2211 struct sci_port *s = to_sci_port(port); 2212 struct mctrl_gpios *gpios = s->gpios; 2213 unsigned int mctrl = 0; 2214 2215 mctrl_gpio_get(gpios, &mctrl); 2216 2217 /* 2218 * CTS/RTS is handled in hardware when supported, while nothing 2219 * else is wired up. 2220 */ 2221 if (s->autorts) { 2222 if (sci_get_cts(port)) 2223 mctrl |= TIOCM_CTS; 2224 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2225 mctrl |= TIOCM_CTS; 2226 } 2227 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2228 mctrl |= TIOCM_DSR; 2229 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2230 mctrl |= TIOCM_CAR; 2231 2232 return mctrl; 2233 } 2234 2235 static void sci_enable_ms(struct uart_port *port) 2236 { 2237 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2238 } 2239 2240 static void sci_break_ctl(struct uart_port *port, int break_state) 2241 { 2242 unsigned short scscr, scsptr; 2243 unsigned long flags; 2244 2245 /* check whether the port has SCSPTR */ 2246 if (!sci_getreg(port, SCSPTR)->size) { 2247 /* 2248 * Not supported by hardware. Most parts couple break and rx 2249 * interrupts together, with break detection always enabled. 2250 */ 2251 return; 2252 } 2253 2254 uart_port_lock_irqsave(port, &flags); 2255 scsptr = sci_serial_in(port, SCSPTR); 2256 scscr = sci_serial_in(port, SCSCR); 2257 2258 if (break_state == -1) { 2259 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2260 scscr &= ~SCSCR_TE; 2261 } else { 2262 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2263 scscr |= SCSCR_TE; 2264 } 2265 2266 sci_serial_out(port, SCSPTR, scsptr); 2267 sci_serial_out(port, SCSCR, scscr); 2268 uart_port_unlock_irqrestore(port, flags); 2269 } 2270 2271 static int sci_startup(struct uart_port *port) 2272 { 2273 struct sci_port *s = to_sci_port(port); 2274 int ret; 2275 2276 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2277 2278 s->tx_occurred = false; 2279 sci_request_dma(port); 2280 2281 ret = sci_request_irq(s); 2282 if (unlikely(ret < 0)) { 2283 sci_free_dma(port); 2284 return ret; 2285 } 2286 2287 return 0; 2288 } 2289 2290 static void sci_shutdown(struct uart_port *port) 2291 { 2292 struct sci_port *s = to_sci_port(port); 2293 unsigned long flags; 2294 u16 scr; 2295 2296 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2297 2298 s->autorts = false; 2299 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2300 2301 uart_port_lock_irqsave(port, &flags); 2302 sci_stop_rx(port); 2303 sci_stop_tx(port); 2304 /* 2305 * Stop RX and TX, disable related interrupts, keep clock source 2306 * and HSCIF TOT bits 2307 */ 2308 scr = sci_serial_in(port, SCSCR); 2309 sci_serial_out(port, SCSCR, 2310 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2311 uart_port_unlock_irqrestore(port, flags); 2312 2313 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2314 if (s->chan_rx_saved) { 2315 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2316 port->line); 2317 hrtimer_cancel(&s->rx_timer); 2318 } 2319 #endif 2320 2321 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2322 del_timer_sync(&s->rx_fifo_timer); 2323 sci_free_irq(s); 2324 sci_free_dma(port); 2325 } 2326 2327 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2328 unsigned int *srr) 2329 { 2330 unsigned long freq = s->clk_rates[SCI_SCK]; 2331 int err, min_err = INT_MAX; 2332 unsigned int sr; 2333 2334 if (s->port.type != PORT_HSCIF) 2335 freq *= 2; 2336 2337 for_each_sr(sr, s) { 2338 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2339 if (abs(err) >= abs(min_err)) 2340 continue; 2341 2342 min_err = err; 2343 *srr = sr - 1; 2344 2345 if (!err) 2346 break; 2347 } 2348 2349 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2350 *srr + 1); 2351 return min_err; 2352 } 2353 2354 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2355 unsigned long freq, unsigned int *dlr, 2356 unsigned int *srr) 2357 { 2358 int err, min_err = INT_MAX; 2359 unsigned int sr, dl; 2360 2361 if (s->port.type != PORT_HSCIF) 2362 freq *= 2; 2363 2364 for_each_sr(sr, s) { 2365 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2366 dl = clamp(dl, 1U, 65535U); 2367 2368 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2369 if (abs(err) >= abs(min_err)) 2370 continue; 2371 2372 min_err = err; 2373 *dlr = dl; 2374 *srr = sr - 1; 2375 2376 if (!err) 2377 break; 2378 } 2379 2380 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2381 min_err, *dlr, *srr + 1); 2382 return min_err; 2383 } 2384 2385 /* calculate sample rate, BRR, and clock select */ 2386 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2387 unsigned int *brr, unsigned int *srr, 2388 unsigned int *cks) 2389 { 2390 unsigned long freq = s->clk_rates[SCI_FCK]; 2391 unsigned int sr, br, prediv, scrate, c; 2392 int err, min_err = INT_MAX; 2393 2394 if (s->port.type != PORT_HSCIF) 2395 freq *= 2; 2396 2397 /* 2398 * Find the combination of sample rate and clock select with the 2399 * smallest deviation from the desired baud rate. 2400 * Prefer high sample rates to maximise the receive margin. 2401 * 2402 * M: Receive margin (%) 2403 * N: Ratio of bit rate to clock (N = sampling rate) 2404 * D: Clock duty (D = 0 to 1.0) 2405 * L: Frame length (L = 9 to 12) 2406 * F: Absolute value of clock frequency deviation 2407 * 2408 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2409 * (|D - 0.5| / N * (1 + F))| 2410 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2411 */ 2412 for_each_sr(sr, s) { 2413 for (c = 0; c <= 3; c++) { 2414 /* integerized formulas from HSCIF documentation */ 2415 prediv = sr << (2 * c + 1); 2416 2417 /* 2418 * We need to calculate: 2419 * 2420 * br = freq / (prediv * bps) clamped to [1..256] 2421 * err = freq / (br * prediv) - bps 2422 * 2423 * Watch out for overflow when calculating the desired 2424 * sampling clock rate! 2425 */ 2426 if (bps > UINT_MAX / prediv) 2427 break; 2428 2429 scrate = prediv * bps; 2430 br = DIV_ROUND_CLOSEST(freq, scrate); 2431 br = clamp(br, 1U, 256U); 2432 2433 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2434 if (abs(err) >= abs(min_err)) 2435 continue; 2436 2437 min_err = err; 2438 *brr = br - 1; 2439 *srr = sr - 1; 2440 *cks = c; 2441 2442 if (!err) 2443 goto found; 2444 } 2445 } 2446 2447 found: 2448 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2449 min_err, *brr, *srr + 1, *cks); 2450 return min_err; 2451 } 2452 2453 static void sci_reset(struct uart_port *port) 2454 { 2455 const struct plat_sci_reg *reg; 2456 unsigned int status; 2457 struct sci_port *s = to_sci_port(port); 2458 2459 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2460 2461 reg = sci_getreg(port, SCFCR); 2462 if (reg->size) 2463 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2464 2465 sci_clear_SCxSR(port, 2466 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2467 SCxSR_BREAK_CLEAR(port)); 2468 if (sci_getreg(port, SCLSR)->size) { 2469 status = sci_serial_in(port, SCLSR); 2470 status &= ~(SCLSR_TO | SCLSR_ORER); 2471 sci_serial_out(port, SCLSR, status); 2472 } 2473 2474 if (s->rx_trigger > 1) { 2475 if (s->rx_fifo_timeout) { 2476 scif_set_rtrg(port, 1); 2477 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2478 } else { 2479 if (port->type == PORT_SCIFA || 2480 port->type == PORT_SCIFB) 2481 scif_set_rtrg(port, 1); 2482 else 2483 scif_set_rtrg(port, s->rx_trigger); 2484 } 2485 } 2486 } 2487 2488 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2489 const struct ktermios *old) 2490 { 2491 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2492 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2493 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2494 struct sci_port *s = to_sci_port(port); 2495 const struct plat_sci_reg *reg; 2496 int min_err = INT_MAX, err; 2497 unsigned long max_freq = 0; 2498 int best_clk = -1; 2499 unsigned long flags; 2500 2501 if ((termios->c_cflag & CSIZE) == CS7) { 2502 smr_val |= SCSMR_CHR; 2503 } else { 2504 termios->c_cflag &= ~CSIZE; 2505 termios->c_cflag |= CS8; 2506 } 2507 if (termios->c_cflag & PARENB) 2508 smr_val |= SCSMR_PE; 2509 if (termios->c_cflag & PARODD) 2510 smr_val |= SCSMR_PE | SCSMR_ODD; 2511 if (termios->c_cflag & CSTOPB) 2512 smr_val |= SCSMR_STOP; 2513 2514 /* 2515 * earlyprintk comes here early on with port->uartclk set to zero. 2516 * the clock framework is not up and running at this point so here 2517 * we assume that 115200 is the maximum baud rate. please note that 2518 * the baud rate is not programmed during earlyprintk - it is assumed 2519 * that the previous boot loader has enabled required clocks and 2520 * setup the baud rate generator hardware for us already. 2521 */ 2522 if (!port->uartclk) { 2523 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2524 goto done; 2525 } 2526 2527 for (i = 0; i < SCI_NUM_CLKS; i++) 2528 max_freq = max(max_freq, s->clk_rates[i]); 2529 2530 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2531 if (!baud) 2532 goto done; 2533 2534 /* 2535 * There can be multiple sources for the sampling clock. Find the one 2536 * that gives us the smallest deviation from the desired baud rate. 2537 */ 2538 2539 /* Optional Undivided External Clock */ 2540 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2541 port->type != PORT_SCIFB) { 2542 err = sci_sck_calc(s, baud, &srr1); 2543 if (abs(err) < abs(min_err)) { 2544 best_clk = SCI_SCK; 2545 scr_val = SCSCR_CKE1; 2546 sccks = SCCKS_CKS; 2547 min_err = err; 2548 srr = srr1; 2549 if (!err) 2550 goto done; 2551 } 2552 } 2553 2554 /* Optional BRG Frequency Divided External Clock */ 2555 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2556 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2557 &srr1); 2558 if (abs(err) < abs(min_err)) { 2559 best_clk = SCI_SCIF_CLK; 2560 scr_val = SCSCR_CKE1; 2561 sccks = 0; 2562 min_err = err; 2563 dl = dl1; 2564 srr = srr1; 2565 if (!err) 2566 goto done; 2567 } 2568 } 2569 2570 /* Optional BRG Frequency Divided Internal Clock */ 2571 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2572 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2573 &srr1); 2574 if (abs(err) < abs(min_err)) { 2575 best_clk = SCI_BRG_INT; 2576 scr_val = SCSCR_CKE1; 2577 sccks = SCCKS_XIN; 2578 min_err = err; 2579 dl = dl1; 2580 srr = srr1; 2581 if (!min_err) 2582 goto done; 2583 } 2584 } 2585 2586 /* Divided Functional Clock using standard Bit Rate Register */ 2587 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2588 if (abs(err) < abs(min_err)) { 2589 best_clk = SCI_FCK; 2590 scr_val = 0; 2591 min_err = err; 2592 brr = brr1; 2593 srr = srr1; 2594 cks = cks1; 2595 } 2596 2597 done: 2598 if (best_clk >= 0) 2599 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2600 s->clks[best_clk], baud, min_err); 2601 2602 sci_port_enable(s); 2603 2604 /* 2605 * Program the optional External Baud Rate Generator (BRG) first. 2606 * It controls the mux to select (H)SCK or frequency divided clock. 2607 */ 2608 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2609 sci_serial_out(port, SCDL, dl); 2610 sci_serial_out(port, SCCKS, sccks); 2611 } 2612 2613 uart_port_lock_irqsave(port, &flags); 2614 2615 sci_reset(port); 2616 2617 uart_update_timeout(port, termios->c_cflag, baud); 2618 2619 /* byte size and parity */ 2620 bits = tty_get_frame_size(termios->c_cflag); 2621 2622 if (sci_getreg(port, SEMR)->size) 2623 sci_serial_out(port, SEMR, 0); 2624 2625 if (best_clk >= 0) { 2626 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2627 switch (srr + 1) { 2628 case 5: smr_val |= SCSMR_SRC_5; break; 2629 case 7: smr_val |= SCSMR_SRC_7; break; 2630 case 11: smr_val |= SCSMR_SRC_11; break; 2631 case 13: smr_val |= SCSMR_SRC_13; break; 2632 case 16: smr_val |= SCSMR_SRC_16; break; 2633 case 17: smr_val |= SCSMR_SRC_17; break; 2634 case 19: smr_val |= SCSMR_SRC_19; break; 2635 case 27: smr_val |= SCSMR_SRC_27; break; 2636 } 2637 smr_val |= cks; 2638 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2639 sci_serial_out(port, SCSMR, smr_val); 2640 sci_serial_out(port, SCBRR, brr); 2641 if (sci_getreg(port, HSSRR)->size) { 2642 unsigned int hssrr = srr | HSCIF_SRE; 2643 /* Calculate deviation from intended rate at the 2644 * center of the last stop bit in sampling clocks. 2645 */ 2646 int last_stop = bits * 2 - 1; 2647 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2648 (int)(srr + 1), 2649 2 * (int)baud); 2650 2651 if (abs(deviation) >= 2) { 2652 /* At least two sampling clocks off at the 2653 * last stop bit; we can increase the error 2654 * margin by shifting the sampling point. 2655 */ 2656 int shift = clamp(deviation / 2, -8, 7); 2657 2658 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2659 HSCIF_SRHP_MASK; 2660 hssrr |= HSCIF_SRDE; 2661 } 2662 sci_serial_out(port, HSSRR, hssrr); 2663 } 2664 2665 /* Wait one bit interval */ 2666 udelay((1000000 + (baud - 1)) / baud); 2667 } else { 2668 /* Don't touch the bit rate configuration */ 2669 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2670 smr_val |= sci_serial_in(port, SCSMR) & 2671 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2672 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2673 sci_serial_out(port, SCSMR, smr_val); 2674 } 2675 2676 sci_init_pins(port, termios->c_cflag); 2677 2678 port->status &= ~UPSTAT_AUTOCTS; 2679 s->autorts = false; 2680 reg = sci_getreg(port, SCFCR); 2681 if (reg->size) { 2682 unsigned short ctrl = sci_serial_in(port, SCFCR); 2683 2684 if ((port->flags & UPF_HARD_FLOW) && 2685 (termios->c_cflag & CRTSCTS)) { 2686 /* There is no CTS interrupt to restart the hardware */ 2687 port->status |= UPSTAT_AUTOCTS; 2688 /* MCE is enabled when RTS is raised */ 2689 s->autorts = true; 2690 } 2691 2692 /* 2693 * As we've done a sci_reset() above, ensure we don't 2694 * interfere with the FIFOs while toggling MCE. As the 2695 * reset values could still be set, simply mask them out. 2696 */ 2697 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2698 2699 sci_serial_out(port, SCFCR, ctrl); 2700 } 2701 if (port->flags & UPF_HARD_FLOW) { 2702 /* Refresh (Auto) RTS */ 2703 sci_set_mctrl(port, port->mctrl); 2704 } 2705 2706 /* 2707 * For SCI, TE (transmit enable) must be set after setting TIE 2708 * (transmit interrupt enable) or in the same instruction to 2709 * start the transmitting process. So skip setting TE here for SCI. 2710 */ 2711 if (port->type != PORT_SCI) 2712 scr_val |= SCSCR_TE; 2713 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2714 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2715 if ((srr + 1 == 5) && 2716 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2717 /* 2718 * In asynchronous mode, when the sampling rate is 1/5, first 2719 * received data may become invalid on some SCIFA and SCIFB. 2720 * To avoid this problem wait more than 1 serial data time (1 2721 * bit time x serial data number) after setting SCSCR.RE = 1. 2722 */ 2723 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2724 } 2725 2726 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2727 s->rx_frame = (10000 * bits) / (baud / 100); 2728 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2729 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2730 #endif 2731 2732 if ((termios->c_cflag & CREAD) != 0) 2733 sci_start_rx(port); 2734 2735 uart_port_unlock_irqrestore(port, flags); 2736 2737 sci_port_disable(s); 2738 2739 if (UART_ENABLE_MS(port, termios->c_cflag)) 2740 sci_enable_ms(port); 2741 } 2742 2743 static void sci_pm(struct uart_port *port, unsigned int state, 2744 unsigned int oldstate) 2745 { 2746 struct sci_port *sci_port = to_sci_port(port); 2747 2748 switch (state) { 2749 case UART_PM_STATE_OFF: 2750 sci_port_disable(sci_port); 2751 break; 2752 default: 2753 sci_port_enable(sci_port); 2754 break; 2755 } 2756 } 2757 2758 static const char *sci_type(struct uart_port *port) 2759 { 2760 switch (port->type) { 2761 case PORT_IRDA: 2762 return "irda"; 2763 case PORT_SCI: 2764 return "sci"; 2765 case PORT_SCIF: 2766 return "scif"; 2767 case PORT_SCIFA: 2768 return "scifa"; 2769 case PORT_SCIFB: 2770 return "scifb"; 2771 case PORT_HSCIF: 2772 return "hscif"; 2773 } 2774 2775 return NULL; 2776 } 2777 2778 static int sci_remap_port(struct uart_port *port) 2779 { 2780 struct sci_port *sport = to_sci_port(port); 2781 2782 /* 2783 * Nothing to do if there's already an established membase. 2784 */ 2785 if (port->membase) 2786 return 0; 2787 2788 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2789 port->membase = ioremap(port->mapbase, sport->reg_size); 2790 if (unlikely(!port->membase)) { 2791 dev_err(port->dev, "can't remap port#%d\n", port->line); 2792 return -ENXIO; 2793 } 2794 } else { 2795 /* 2796 * For the simple (and majority of) cases where we don't 2797 * need to do any remapping, just cast the cookie 2798 * directly. 2799 */ 2800 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2801 } 2802 2803 return 0; 2804 } 2805 2806 static void sci_release_port(struct uart_port *port) 2807 { 2808 struct sci_port *sport = to_sci_port(port); 2809 2810 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2811 iounmap(port->membase); 2812 port->membase = NULL; 2813 } 2814 2815 release_mem_region(port->mapbase, sport->reg_size); 2816 } 2817 2818 static int sci_request_port(struct uart_port *port) 2819 { 2820 struct resource *res; 2821 struct sci_port *sport = to_sci_port(port); 2822 int ret; 2823 2824 res = request_mem_region(port->mapbase, sport->reg_size, 2825 dev_name(port->dev)); 2826 if (unlikely(res == NULL)) { 2827 dev_err(port->dev, "request_mem_region failed."); 2828 return -EBUSY; 2829 } 2830 2831 ret = sci_remap_port(port); 2832 if (unlikely(ret != 0)) { 2833 release_resource(res); 2834 return ret; 2835 } 2836 2837 return 0; 2838 } 2839 2840 static void sci_config_port(struct uart_port *port, int flags) 2841 { 2842 if (flags & UART_CONFIG_TYPE) { 2843 struct sci_port *sport = to_sci_port(port); 2844 2845 port->type = sport->cfg->type; 2846 sci_request_port(port); 2847 } 2848 } 2849 2850 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2851 { 2852 if (ser->baud_base < 2400) 2853 /* No paper tape reader for Mitch.. */ 2854 return -EINVAL; 2855 2856 return 0; 2857 } 2858 2859 static const struct uart_ops sci_uart_ops = { 2860 .tx_empty = sci_tx_empty, 2861 .set_mctrl = sci_set_mctrl, 2862 .get_mctrl = sci_get_mctrl, 2863 .start_tx = sci_start_tx, 2864 .stop_tx = sci_stop_tx, 2865 .stop_rx = sci_stop_rx, 2866 .enable_ms = sci_enable_ms, 2867 .break_ctl = sci_break_ctl, 2868 .startup = sci_startup, 2869 .shutdown = sci_shutdown, 2870 .flush_buffer = sci_flush_buffer, 2871 .set_termios = sci_set_termios, 2872 .pm = sci_pm, 2873 .type = sci_type, 2874 .release_port = sci_release_port, 2875 .request_port = sci_request_port, 2876 .config_port = sci_config_port, 2877 .verify_port = sci_verify_port, 2878 #ifdef CONFIG_CONSOLE_POLL 2879 .poll_get_char = sci_poll_get_char, 2880 .poll_put_char = sci_poll_put_char, 2881 #endif 2882 }; 2883 2884 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2885 { 2886 const char *clk_names[] = { 2887 [SCI_FCK] = "fck", 2888 [SCI_SCK] = "sck", 2889 [SCI_BRG_INT] = "brg_int", 2890 [SCI_SCIF_CLK] = "scif_clk", 2891 }; 2892 struct clk *clk; 2893 unsigned int i; 2894 2895 if (sci_port->cfg->type == PORT_HSCIF) 2896 clk_names[SCI_SCK] = "hsck"; 2897 2898 for (i = 0; i < SCI_NUM_CLKS; i++) { 2899 clk = devm_clk_get_optional(dev, clk_names[i]); 2900 if (IS_ERR(clk)) 2901 return PTR_ERR(clk); 2902 2903 if (!clk && i == SCI_FCK) { 2904 /* 2905 * Not all SH platforms declare a clock lookup entry 2906 * for SCI devices, in which case we need to get the 2907 * global "peripheral_clk" clock. 2908 */ 2909 clk = devm_clk_get(dev, "peripheral_clk"); 2910 if (IS_ERR(clk)) 2911 return dev_err_probe(dev, PTR_ERR(clk), 2912 "failed to get %s\n", 2913 clk_names[i]); 2914 } 2915 2916 if (!clk) 2917 dev_dbg(dev, "failed to get %s\n", clk_names[i]); 2918 else 2919 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2920 clk, clk_get_rate(clk)); 2921 sci_port->clks[i] = clk; 2922 } 2923 return 0; 2924 } 2925 2926 static const struct sci_port_params * 2927 sci_probe_regmap(const struct plat_sci_port *cfg) 2928 { 2929 unsigned int regtype; 2930 2931 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2932 return &sci_port_params[cfg->regtype]; 2933 2934 switch (cfg->type) { 2935 case PORT_SCI: 2936 regtype = SCIx_SCI_REGTYPE; 2937 break; 2938 case PORT_IRDA: 2939 regtype = SCIx_IRDA_REGTYPE; 2940 break; 2941 case PORT_SCIFA: 2942 regtype = SCIx_SCIFA_REGTYPE; 2943 break; 2944 case PORT_SCIFB: 2945 regtype = SCIx_SCIFB_REGTYPE; 2946 break; 2947 case PORT_SCIF: 2948 /* 2949 * The SH-4 is a bit of a misnomer here, although that's 2950 * where this particular port layout originated. This 2951 * configuration (or some slight variation thereof) 2952 * remains the dominant model for all SCIFs. 2953 */ 2954 regtype = SCIx_SH4_SCIF_REGTYPE; 2955 break; 2956 case PORT_HSCIF: 2957 regtype = SCIx_HSCIF_REGTYPE; 2958 break; 2959 default: 2960 pr_err("Can't probe register map for given port\n"); 2961 return NULL; 2962 } 2963 2964 return &sci_port_params[regtype]; 2965 } 2966 2967 static int sci_init_single(struct platform_device *dev, 2968 struct sci_port *sci_port, unsigned int index, 2969 const struct plat_sci_port *p, bool early) 2970 { 2971 struct uart_port *port = &sci_port->port; 2972 const struct resource *res; 2973 unsigned int i; 2974 int ret; 2975 2976 sci_port->cfg = p; 2977 2978 port->ops = &sci_uart_ops; 2979 port->iotype = UPIO_MEM; 2980 port->line = index; 2981 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2982 2983 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2984 if (res == NULL) 2985 return -ENOMEM; 2986 2987 port->mapbase = res->start; 2988 sci_port->reg_size = resource_size(res); 2989 2990 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2991 if (i) 2992 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2993 else 2994 sci_port->irqs[i] = platform_get_irq(dev, i); 2995 } 2996 2997 /* 2998 * The fourth interrupt on SCI port is transmit end interrupt, so 2999 * shuffle the interrupts. 3000 */ 3001 if (p->type == PORT_SCI) 3002 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); 3003 3004 /* The SCI generates several interrupts. They can be muxed together or 3005 * connected to different interrupt lines. In the muxed case only one 3006 * interrupt resource is specified as there is only one interrupt ID. 3007 * In the non-muxed case, up to 6 interrupt signals might be generated 3008 * from the SCI, however those signals might have their own individual 3009 * interrupt ID numbers, or muxed together with another interrupt. 3010 */ 3011 if (sci_port->irqs[0] < 0) 3012 return -ENXIO; 3013 3014 if (sci_port->irqs[1] < 0) 3015 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 3016 sci_port->irqs[i] = sci_port->irqs[0]; 3017 3018 sci_port->params = sci_probe_regmap(p); 3019 if (unlikely(sci_port->params == NULL)) 3020 return -EINVAL; 3021 3022 switch (p->type) { 3023 case PORT_SCIFB: 3024 sci_port->rx_trigger = 48; 3025 break; 3026 case PORT_HSCIF: 3027 sci_port->rx_trigger = 64; 3028 break; 3029 case PORT_SCIFA: 3030 sci_port->rx_trigger = 32; 3031 break; 3032 case PORT_SCIF: 3033 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 3034 /* RX triggering not implemented for this IP */ 3035 sci_port->rx_trigger = 1; 3036 else 3037 sci_port->rx_trigger = 8; 3038 break; 3039 default: 3040 sci_port->rx_trigger = 1; 3041 break; 3042 } 3043 3044 sci_port->rx_fifo_timeout = 0; 3045 sci_port->hscif_tot = 0; 3046 3047 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 3048 * match the SoC datasheet, this should be investigated. Let platform 3049 * data override the sampling rate for now. 3050 */ 3051 sci_port->sampling_rate_mask = p->sampling_rate 3052 ? SCI_SR(p->sampling_rate) 3053 : sci_port->params->sampling_rate_mask; 3054 3055 if (!early) { 3056 ret = sci_init_clocks(sci_port, &dev->dev); 3057 if (ret < 0) 3058 return ret; 3059 3060 port->dev = &dev->dev; 3061 3062 pm_runtime_enable(&dev->dev); 3063 } 3064 3065 port->type = p->type; 3066 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 3067 port->fifosize = sci_port->params->fifosize; 3068 3069 if (port->type == PORT_SCI && !dev->dev.of_node) { 3070 if (sci_port->reg_size >= 0x20) 3071 port->regshift = 2; 3072 else 3073 port->regshift = 1; 3074 } 3075 3076 /* 3077 * The UART port needs an IRQ value, so we peg this to the RX IRQ 3078 * for the multi-IRQ ports, which is where we are primarily 3079 * concerned with the shutdown path synchronization. 3080 * 3081 * For the muxed case there's nothing more to do. 3082 */ 3083 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 3084 port->irqflags = 0; 3085 3086 return 0; 3087 } 3088 3089 static void sci_cleanup_single(struct sci_port *port) 3090 { 3091 pm_runtime_disable(port->port.dev); 3092 } 3093 3094 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3095 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3096 static void serial_console_putchar(struct uart_port *port, unsigned char ch) 3097 { 3098 sci_poll_put_char(port, ch); 3099 } 3100 3101 /* 3102 * Print a string to the serial port trying not to disturb 3103 * any possible real use of the port... 3104 */ 3105 static void serial_console_write(struct console *co, const char *s, 3106 unsigned count) 3107 { 3108 struct sci_port *sci_port = &sci_ports[co->index]; 3109 struct uart_port *port = &sci_port->port; 3110 unsigned short bits, ctrl, ctrl_temp; 3111 unsigned long flags; 3112 int locked = 1; 3113 3114 if (port->sysrq) 3115 locked = 0; 3116 else if (oops_in_progress) 3117 locked = uart_port_trylock_irqsave(port, &flags); 3118 else 3119 uart_port_lock_irqsave(port, &flags); 3120 3121 /* first save SCSCR then disable interrupts, keep clock source */ 3122 ctrl = sci_serial_in(port, SCSCR); 3123 ctrl_temp = SCSCR_RE | SCSCR_TE | 3124 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3125 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3126 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3127 3128 uart_console_write(port, s, count, serial_console_putchar); 3129 3130 /* wait until fifo is empty and last bit has been transmitted */ 3131 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3132 while ((sci_serial_in(port, SCxSR) & bits) != bits) 3133 cpu_relax(); 3134 3135 /* restore the SCSCR */ 3136 sci_serial_out(port, SCSCR, ctrl); 3137 3138 if (locked) 3139 uart_port_unlock_irqrestore(port, flags); 3140 } 3141 3142 static int serial_console_setup(struct console *co, char *options) 3143 { 3144 struct sci_port *sci_port; 3145 struct uart_port *port; 3146 int baud = 115200; 3147 int bits = 8; 3148 int parity = 'n'; 3149 int flow = 'n'; 3150 int ret; 3151 3152 /* 3153 * Refuse to handle any bogus ports. 3154 */ 3155 if (co->index < 0 || co->index >= SCI_NPORTS) 3156 return -ENODEV; 3157 3158 sci_port = &sci_ports[co->index]; 3159 port = &sci_port->port; 3160 3161 /* 3162 * Refuse to handle uninitialized ports. 3163 */ 3164 if (!port->ops) 3165 return -ENODEV; 3166 3167 ret = sci_remap_port(port); 3168 if (unlikely(ret != 0)) 3169 return ret; 3170 3171 if (options) 3172 uart_parse_options(options, &baud, &parity, &bits, &flow); 3173 3174 return uart_set_options(port, co, baud, parity, bits, flow); 3175 } 3176 3177 static struct console serial_console = { 3178 .name = "ttySC", 3179 .device = uart_console_device, 3180 .write = serial_console_write, 3181 .setup = serial_console_setup, 3182 .flags = CON_PRINTBUFFER, 3183 .index = -1, 3184 .data = &sci_uart_driver, 3185 }; 3186 3187 #ifdef CONFIG_SUPERH 3188 static char early_serial_buf[32]; 3189 3190 static int early_serial_console_setup(struct console *co, char *options) 3191 { 3192 /* 3193 * This early console is always registered using the earlyprintk= 3194 * parameter, which does not call add_preferred_console(). Thus 3195 * @options is always NULL and the options for this early console 3196 * are passed using a custom buffer. 3197 */ 3198 WARN_ON(options); 3199 3200 return serial_console_setup(co, early_serial_buf); 3201 } 3202 3203 static struct console early_serial_console = { 3204 .name = "early_ttySC", 3205 .write = serial_console_write, 3206 .setup = early_serial_console_setup, 3207 .flags = CON_PRINTBUFFER, 3208 .index = -1, 3209 }; 3210 3211 static int sci_probe_earlyprintk(struct platform_device *pdev) 3212 { 3213 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3214 3215 if (early_serial_console.data) 3216 return -EEXIST; 3217 3218 early_serial_console.index = pdev->id; 3219 3220 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3221 3222 if (!strstr(early_serial_buf, "keep")) 3223 early_serial_console.flags |= CON_BOOT; 3224 3225 register_console(&early_serial_console); 3226 return 0; 3227 } 3228 #endif 3229 3230 #define SCI_CONSOLE (&serial_console) 3231 3232 #else 3233 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3234 { 3235 return -EINVAL; 3236 } 3237 3238 #define SCI_CONSOLE NULL 3239 3240 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3241 3242 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3243 3244 static DEFINE_MUTEX(sci_uart_registration_lock); 3245 static struct uart_driver sci_uart_driver = { 3246 .owner = THIS_MODULE, 3247 .driver_name = "sci", 3248 .dev_name = "ttySC", 3249 .major = SCI_MAJOR, 3250 .minor = SCI_MINOR_START, 3251 .nr = SCI_NPORTS, 3252 .cons = SCI_CONSOLE, 3253 }; 3254 3255 static void sci_remove(struct platform_device *dev) 3256 { 3257 struct sci_port *port = platform_get_drvdata(dev); 3258 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3259 3260 sci_ports_in_use &= ~BIT(port->port.line); 3261 uart_remove_one_port(&sci_uart_driver, &port->port); 3262 3263 sci_cleanup_single(port); 3264 3265 if (port->port.fifosize > 1) 3266 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3267 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3268 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3269 } 3270 3271 3272 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3273 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3274 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3275 3276 static const struct of_device_id of_sci_match[] __maybe_unused = { 3277 /* SoC-specific types */ 3278 { 3279 .compatible = "renesas,scif-r7s72100", 3280 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3281 }, 3282 { 3283 .compatible = "renesas,scif-r7s9210", 3284 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3285 }, 3286 { 3287 .compatible = "renesas,scif-r9a07g044", 3288 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3289 }, 3290 { 3291 .compatible = "renesas,scif-r9a09g057", 3292 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE), 3293 }, 3294 /* Family-specific types */ 3295 { 3296 .compatible = "renesas,rcar-gen1-scif", 3297 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3298 }, { 3299 .compatible = "renesas,rcar-gen2-scif", 3300 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3301 }, { 3302 .compatible = "renesas,rcar-gen3-scif", 3303 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3304 }, { 3305 .compatible = "renesas,rcar-gen4-scif", 3306 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3307 }, 3308 /* Generic types */ 3309 { 3310 .compatible = "renesas,scif", 3311 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3312 }, { 3313 .compatible = "renesas,scifa", 3314 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3315 }, { 3316 .compatible = "renesas,scifb", 3317 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3318 }, { 3319 .compatible = "renesas,hscif", 3320 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3321 }, { 3322 .compatible = "renesas,sci", 3323 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3324 }, { 3325 /* Terminator */ 3326 }, 3327 }; 3328 MODULE_DEVICE_TABLE(of, of_sci_match); 3329 3330 static void sci_reset_control_assert(void *data) 3331 { 3332 reset_control_assert(data); 3333 } 3334 3335 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3336 unsigned int *dev_id) 3337 { 3338 struct device_node *np = pdev->dev.of_node; 3339 struct reset_control *rstc; 3340 struct plat_sci_port *p; 3341 struct sci_port *sp; 3342 const void *data; 3343 int id, ret; 3344 3345 if (!IS_ENABLED(CONFIG_OF) || !np) 3346 return ERR_PTR(-EINVAL); 3347 3348 data = of_device_get_match_data(&pdev->dev); 3349 3350 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3351 if (IS_ERR(rstc)) 3352 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3353 "failed to get reset ctrl\n")); 3354 3355 ret = reset_control_deassert(rstc); 3356 if (ret) { 3357 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3358 return ERR_PTR(ret); 3359 } 3360 3361 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3362 if (ret) { 3363 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3364 ret); 3365 return ERR_PTR(ret); 3366 } 3367 3368 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3369 if (!p) 3370 return ERR_PTR(-ENOMEM); 3371 3372 /* Get the line number from the aliases node. */ 3373 id = of_alias_get_id(np, "serial"); 3374 if (id < 0 && ~sci_ports_in_use) 3375 id = ffz(sci_ports_in_use); 3376 if (id < 0) { 3377 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3378 return ERR_PTR(-EINVAL); 3379 } 3380 if (id >= ARRAY_SIZE(sci_ports)) { 3381 dev_err(&pdev->dev, "serial%d out of range\n", id); 3382 return ERR_PTR(-EINVAL); 3383 } 3384 3385 sp = &sci_ports[id]; 3386 *dev_id = id; 3387 3388 p->type = SCI_OF_TYPE(data); 3389 p->regtype = SCI_OF_REGTYPE(data); 3390 3391 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3392 3393 return p; 3394 } 3395 3396 static int sci_probe_single(struct platform_device *dev, 3397 unsigned int index, 3398 struct plat_sci_port *p, 3399 struct sci_port *sciport) 3400 { 3401 int ret; 3402 3403 /* Sanity check */ 3404 if (unlikely(index >= SCI_NPORTS)) { 3405 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3406 index+1, SCI_NPORTS); 3407 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3408 return -EINVAL; 3409 } 3410 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3411 if (sci_ports_in_use & BIT(index)) 3412 return -EBUSY; 3413 3414 mutex_lock(&sci_uart_registration_lock); 3415 if (!sci_uart_driver.state) { 3416 ret = uart_register_driver(&sci_uart_driver); 3417 if (ret) { 3418 mutex_unlock(&sci_uart_registration_lock); 3419 return ret; 3420 } 3421 } 3422 mutex_unlock(&sci_uart_registration_lock); 3423 3424 ret = sci_init_single(dev, sciport, index, p, false); 3425 if (ret) 3426 return ret; 3427 3428 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3429 if (IS_ERR(sciport->gpios)) 3430 return PTR_ERR(sciport->gpios); 3431 3432 if (sciport->has_rtscts) { 3433 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3434 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3435 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3436 return -EINVAL; 3437 } 3438 sciport->port.flags |= UPF_HARD_FLOW; 3439 } 3440 3441 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3442 if (ret) { 3443 sci_cleanup_single(sciport); 3444 return ret; 3445 } 3446 3447 return 0; 3448 } 3449 3450 static int sci_probe(struct platform_device *dev) 3451 { 3452 struct plat_sci_port *p; 3453 struct sci_port *sp; 3454 unsigned int dev_id; 3455 int ret; 3456 3457 /* 3458 * If we've come here via earlyprintk initialization, head off to 3459 * the special early probe. We don't have sufficient device state 3460 * to make it beyond this yet. 3461 */ 3462 #ifdef CONFIG_SUPERH 3463 if (is_sh_early_platform_device(dev)) 3464 return sci_probe_earlyprintk(dev); 3465 #endif 3466 3467 if (dev->dev.of_node) { 3468 p = sci_parse_dt(dev, &dev_id); 3469 if (IS_ERR(p)) 3470 return PTR_ERR(p); 3471 } else { 3472 p = dev->dev.platform_data; 3473 if (p == NULL) { 3474 dev_err(&dev->dev, "no platform data supplied\n"); 3475 return -EINVAL; 3476 } 3477 3478 dev_id = dev->id; 3479 } 3480 3481 sp = &sci_ports[dev_id]; 3482 platform_set_drvdata(dev, sp); 3483 3484 ret = sci_probe_single(dev, dev_id, p, sp); 3485 if (ret) 3486 return ret; 3487 3488 if (sp->port.fifosize > 1) { 3489 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3490 if (ret) 3491 return ret; 3492 } 3493 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3494 sp->port.type == PORT_HSCIF) { 3495 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3496 if (ret) { 3497 if (sp->port.fifosize > 1) { 3498 device_remove_file(&dev->dev, 3499 &dev_attr_rx_fifo_trigger); 3500 } 3501 return ret; 3502 } 3503 } 3504 3505 #ifdef CONFIG_SH_STANDARD_BIOS 3506 sh_bios_gdb_detach(); 3507 #endif 3508 3509 sci_ports_in_use |= BIT(dev_id); 3510 return 0; 3511 } 3512 3513 static __maybe_unused int sci_suspend(struct device *dev) 3514 { 3515 struct sci_port *sport = dev_get_drvdata(dev); 3516 3517 if (sport) 3518 uart_suspend_port(&sci_uart_driver, &sport->port); 3519 3520 return 0; 3521 } 3522 3523 static __maybe_unused int sci_resume(struct device *dev) 3524 { 3525 struct sci_port *sport = dev_get_drvdata(dev); 3526 3527 if (sport) 3528 uart_resume_port(&sci_uart_driver, &sport->port); 3529 3530 return 0; 3531 } 3532 3533 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3534 3535 static struct platform_driver sci_driver = { 3536 .probe = sci_probe, 3537 .remove = sci_remove, 3538 .driver = { 3539 .name = "sh-sci", 3540 .pm = &sci_dev_pm_ops, 3541 .of_match_table = of_match_ptr(of_sci_match), 3542 }, 3543 }; 3544 3545 static int __init sci_init(void) 3546 { 3547 pr_info("%s\n", banner); 3548 3549 return platform_driver_register(&sci_driver); 3550 } 3551 3552 static void __exit sci_exit(void) 3553 { 3554 platform_driver_unregister(&sci_driver); 3555 3556 if (sci_uart_driver.state) 3557 uart_unregister_driver(&sci_uart_driver); 3558 } 3559 3560 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3561 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3562 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3563 #endif 3564 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3565 static struct plat_sci_port port_cfg __initdata; 3566 3567 static int __init early_console_setup(struct earlycon_device *device, 3568 int type) 3569 { 3570 if (!device->port.membase) 3571 return -ENODEV; 3572 3573 device->port.type = type; 3574 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3575 port_cfg.type = type; 3576 sci_ports[0].cfg = &port_cfg; 3577 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3578 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3579 sci_serial_out(&sci_ports[0].port, SCSCR, 3580 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3581 3582 device->con->write = serial_console_write; 3583 return 0; 3584 } 3585 static int __init sci_early_console_setup(struct earlycon_device *device, 3586 const char *opt) 3587 { 3588 return early_console_setup(device, PORT_SCI); 3589 } 3590 static int __init scif_early_console_setup(struct earlycon_device *device, 3591 const char *opt) 3592 { 3593 return early_console_setup(device, PORT_SCIF); 3594 } 3595 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3596 const char *opt) 3597 { 3598 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3599 return early_console_setup(device, PORT_SCIF); 3600 } 3601 3602 static int __init rzv2hscif_early_console_setup(struct earlycon_device *device, 3603 const char *opt) 3604 { 3605 port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE; 3606 return early_console_setup(device, PORT_SCIF); 3607 } 3608 3609 static int __init scifa_early_console_setup(struct earlycon_device *device, 3610 const char *opt) 3611 { 3612 return early_console_setup(device, PORT_SCIFA); 3613 } 3614 static int __init scifb_early_console_setup(struct earlycon_device *device, 3615 const char *opt) 3616 { 3617 return early_console_setup(device, PORT_SCIFB); 3618 } 3619 static int __init hscif_early_console_setup(struct earlycon_device *device, 3620 const char *opt) 3621 { 3622 return early_console_setup(device, PORT_HSCIF); 3623 } 3624 3625 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3626 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3627 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3628 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3629 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup); 3630 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3631 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3632 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3633 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3634 3635 module_init(sci_init); 3636 module_exit(sci_exit); 3637 3638 MODULE_LICENSE("GPL"); 3639 MODULE_ALIAS("platform:sh-sci"); 3640 MODULE_AUTHOR("Paul Mundt"); 3641 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3642