1 /* 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 3 * 4 * Copyright (C) 2002 - 2011 Paul Mundt 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 6 * 7 * based off of the old drivers/char/sh-sci.c by: 8 * 9 * Copyright (C) 1999, 2000 Niibe Yutaka 10 * Copyright (C) 2000 Sugioka Toshinobu 11 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 12 * Modified to support SecureEdge. David McCullough (2002) 13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 14 * Removed SH7300 support (Jul 2007). 15 * 16 * This file is subject to the terms and conditions of the GNU General Public 17 * License. See the file "COPYING" in the main directory of this archive 18 * for more details. 19 */ 20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21 #define SUPPORT_SYSRQ 22 #endif 23 24 #undef DEBUG 25 26 #include <linux/module.h> 27 #include <linux/errno.h> 28 #include <linux/timer.h> 29 #include <linux/interrupt.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial.h> 33 #include <linux/major.h> 34 #include <linux/string.h> 35 #include <linux/sysrq.h> 36 #include <linux/ioport.h> 37 #include <linux/mm.h> 38 #include <linux/init.h> 39 #include <linux/delay.h> 40 #include <linux/console.h> 41 #include <linux/platform_device.h> 42 #include <linux/serial_sci.h> 43 #include <linux/notifier.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/cpufreq.h> 46 #include <linux/clk.h> 47 #include <linux/ctype.h> 48 #include <linux/err.h> 49 #include <linux/dmaengine.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/scatterlist.h> 52 #include <linux/slab.h> 53 54 #ifdef CONFIG_SUPERH 55 #include <asm/sh_bios.h> 56 #endif 57 58 #include "sh-sci.h" 59 60 struct sci_port { 61 struct uart_port port; 62 63 /* Platform configuration */ 64 struct plat_sci_port *cfg; 65 66 /* Break timer */ 67 struct timer_list break_timer; 68 int break_flag; 69 70 /* Interface clock */ 71 struct clk *iclk; 72 /* Function clock */ 73 struct clk *fclk; 74 75 char *irqstr[SCIx_NR_IRQS]; 76 77 struct dma_chan *chan_tx; 78 struct dma_chan *chan_rx; 79 80 #ifdef CONFIG_SERIAL_SH_SCI_DMA 81 struct dma_async_tx_descriptor *desc_tx; 82 struct dma_async_tx_descriptor *desc_rx[2]; 83 dma_cookie_t cookie_tx; 84 dma_cookie_t cookie_rx[2]; 85 dma_cookie_t active_rx; 86 struct scatterlist sg_tx; 87 unsigned int sg_len_tx; 88 struct scatterlist sg_rx[2]; 89 size_t buf_len_rx; 90 struct sh_dmae_slave param_tx; 91 struct sh_dmae_slave param_rx; 92 struct work_struct work_tx; 93 struct work_struct work_rx; 94 struct timer_list rx_timer; 95 unsigned int rx_timeout; 96 #endif 97 98 struct notifier_block freq_transition; 99 100 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 101 unsigned short saved_smr; 102 unsigned short saved_fcr; 103 unsigned char saved_brr; 104 #endif 105 }; 106 107 /* Function prototypes */ 108 static void sci_start_tx(struct uart_port *port); 109 static void sci_stop_tx(struct uart_port *port); 110 static void sci_start_rx(struct uart_port *port); 111 112 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 113 114 static struct sci_port sci_ports[SCI_NPORTS]; 115 static struct uart_driver sci_uart_driver; 116 117 static inline struct sci_port * 118 to_sci_port(struct uart_port *uart) 119 { 120 return container_of(uart, struct sci_port, port); 121 } 122 123 struct plat_sci_reg { 124 u8 offset, size; 125 }; 126 127 /* Helper for invalidating specific entries of an inherited map. */ 128 #define sci_reg_invalid { .offset = 0, .size = 0 } 129 130 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { 131 [SCIx_PROBE_REGTYPE] = { 132 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, 133 }, 134 135 /* 136 * Common SCI definitions, dependent on the port's regshift 137 * value. 138 */ 139 [SCIx_SCI_REGTYPE] = { 140 [SCSMR] = { 0x00, 8 }, 141 [SCBRR] = { 0x01, 8 }, 142 [SCSCR] = { 0x02, 8 }, 143 [SCxTDR] = { 0x03, 8 }, 144 [SCxSR] = { 0x04, 8 }, 145 [SCxRDR] = { 0x05, 8 }, 146 [SCFCR] = sci_reg_invalid, 147 [SCFDR] = sci_reg_invalid, 148 [SCTFDR] = sci_reg_invalid, 149 [SCRFDR] = sci_reg_invalid, 150 [SCSPTR] = sci_reg_invalid, 151 [SCLSR] = sci_reg_invalid, 152 }, 153 154 /* 155 * Common definitions for legacy IrDA ports, dependent on 156 * regshift value. 157 */ 158 [SCIx_IRDA_REGTYPE] = { 159 [SCSMR] = { 0x00, 8 }, 160 [SCBRR] = { 0x01, 8 }, 161 [SCSCR] = { 0x02, 8 }, 162 [SCxTDR] = { 0x03, 8 }, 163 [SCxSR] = { 0x04, 8 }, 164 [SCxRDR] = { 0x05, 8 }, 165 [SCFCR] = { 0x06, 8 }, 166 [SCFDR] = { 0x07, 16 }, 167 [SCTFDR] = sci_reg_invalid, 168 [SCRFDR] = sci_reg_invalid, 169 [SCSPTR] = sci_reg_invalid, 170 [SCLSR] = sci_reg_invalid, 171 }, 172 173 /* 174 * Common SCIFA definitions. 175 */ 176 [SCIx_SCIFA_REGTYPE] = { 177 [SCSMR] = { 0x00, 16 }, 178 [SCBRR] = { 0x04, 8 }, 179 [SCSCR] = { 0x08, 16 }, 180 [SCxTDR] = { 0x20, 8 }, 181 [SCxSR] = { 0x14, 16 }, 182 [SCxRDR] = { 0x24, 8 }, 183 [SCFCR] = { 0x18, 16 }, 184 [SCFDR] = { 0x1c, 16 }, 185 [SCTFDR] = sci_reg_invalid, 186 [SCRFDR] = sci_reg_invalid, 187 [SCSPTR] = sci_reg_invalid, 188 [SCLSR] = sci_reg_invalid, 189 }, 190 191 /* 192 * Common SCIFB definitions. 193 */ 194 [SCIx_SCIFB_REGTYPE] = { 195 [SCSMR] = { 0x00, 16 }, 196 [SCBRR] = { 0x04, 8 }, 197 [SCSCR] = { 0x08, 16 }, 198 [SCxTDR] = { 0x40, 8 }, 199 [SCxSR] = { 0x14, 16 }, 200 [SCxRDR] = { 0x60, 8 }, 201 [SCFCR] = { 0x18, 16 }, 202 [SCFDR] = { 0x1c, 16 }, 203 [SCTFDR] = sci_reg_invalid, 204 [SCRFDR] = sci_reg_invalid, 205 [SCSPTR] = sci_reg_invalid, 206 [SCLSR] = sci_reg_invalid, 207 }, 208 209 /* 210 * Common SH-3 SCIF definitions. 211 */ 212 [SCIx_SH3_SCIF_REGTYPE] = { 213 [SCSMR] = { 0x00, 8 }, 214 [SCBRR] = { 0x02, 8 }, 215 [SCSCR] = { 0x04, 8 }, 216 [SCxTDR] = { 0x06, 8 }, 217 [SCxSR] = { 0x08, 16 }, 218 [SCxRDR] = { 0x0a, 8 }, 219 [SCFCR] = { 0x0c, 8 }, 220 [SCFDR] = { 0x0e, 16 }, 221 [SCTFDR] = sci_reg_invalid, 222 [SCRFDR] = sci_reg_invalid, 223 [SCSPTR] = sci_reg_invalid, 224 [SCLSR] = sci_reg_invalid, 225 }, 226 227 /* 228 * Common SH-4(A) SCIF(B) definitions. 229 */ 230 [SCIx_SH4_SCIF_REGTYPE] = { 231 [SCSMR] = { 0x00, 16 }, 232 [SCBRR] = { 0x04, 8 }, 233 [SCSCR] = { 0x08, 16 }, 234 [SCxTDR] = { 0x0c, 8 }, 235 [SCxSR] = { 0x10, 16 }, 236 [SCxRDR] = { 0x14, 8 }, 237 [SCFCR] = { 0x18, 16 }, 238 [SCFDR] = { 0x1c, 16 }, 239 [SCTFDR] = sci_reg_invalid, 240 [SCRFDR] = sci_reg_invalid, 241 [SCSPTR] = { 0x20, 16 }, 242 [SCLSR] = { 0x24, 16 }, 243 }, 244 245 /* 246 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 247 * register. 248 */ 249 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 250 [SCSMR] = { 0x00, 16 }, 251 [SCBRR] = { 0x04, 8 }, 252 [SCSCR] = { 0x08, 16 }, 253 [SCxTDR] = { 0x0c, 8 }, 254 [SCxSR] = { 0x10, 16 }, 255 [SCxRDR] = { 0x14, 8 }, 256 [SCFCR] = { 0x18, 16 }, 257 [SCFDR] = { 0x1c, 16 }, 258 [SCTFDR] = sci_reg_invalid, 259 [SCRFDR] = sci_reg_invalid, 260 [SCSPTR] = sci_reg_invalid, 261 [SCLSR] = { 0x24, 16 }, 262 }, 263 264 /* 265 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 266 * count registers. 267 */ 268 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 269 [SCSMR] = { 0x00, 16 }, 270 [SCBRR] = { 0x04, 8 }, 271 [SCSCR] = { 0x08, 16 }, 272 [SCxTDR] = { 0x0c, 8 }, 273 [SCxSR] = { 0x10, 16 }, 274 [SCxRDR] = { 0x14, 8 }, 275 [SCFCR] = { 0x18, 16 }, 276 [SCFDR] = { 0x1c, 16 }, 277 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 278 [SCRFDR] = { 0x20, 16 }, 279 [SCSPTR] = { 0x24, 16 }, 280 [SCLSR] = { 0x28, 16 }, 281 }, 282 283 /* 284 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 285 * registers. 286 */ 287 [SCIx_SH7705_SCIF_REGTYPE] = { 288 [SCSMR] = { 0x00, 16 }, 289 [SCBRR] = { 0x04, 8 }, 290 [SCSCR] = { 0x08, 16 }, 291 [SCxTDR] = { 0x20, 8 }, 292 [SCxSR] = { 0x14, 16 }, 293 [SCxRDR] = { 0x24, 8 }, 294 [SCFCR] = { 0x18, 16 }, 295 [SCFDR] = { 0x1c, 16 }, 296 [SCTFDR] = sci_reg_invalid, 297 [SCRFDR] = sci_reg_invalid, 298 [SCSPTR] = sci_reg_invalid, 299 [SCLSR] = sci_reg_invalid, 300 }, 301 }; 302 303 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) 304 305 /* 306 * The "offset" here is rather misleading, in that it refers to an enum 307 * value relative to the port mapping rather than the fixed offset 308 * itself, which needs to be manually retrieved from the platform's 309 * register map for the given port. 310 */ 311 static unsigned int sci_serial_in(struct uart_port *p, int offset) 312 { 313 struct plat_sci_reg *reg = sci_getreg(p, offset); 314 315 if (reg->size == 8) 316 return ioread8(p->membase + (reg->offset << p->regshift)); 317 else if (reg->size == 16) 318 return ioread16(p->membase + (reg->offset << p->regshift)); 319 else 320 WARN(1, "Invalid register access\n"); 321 322 return 0; 323 } 324 325 static void sci_serial_out(struct uart_port *p, int offset, int value) 326 { 327 struct plat_sci_reg *reg = sci_getreg(p, offset); 328 329 if (reg->size == 8) 330 iowrite8(value, p->membase + (reg->offset << p->regshift)); 331 else if (reg->size == 16) 332 iowrite16(value, p->membase + (reg->offset << p->regshift)); 333 else 334 WARN(1, "Invalid register access\n"); 335 } 336 337 #define sci_in(up, offset) (up->serial_in(up, offset)) 338 #define sci_out(up, offset, value) (up->serial_out(up, offset, value)) 339 340 static int sci_probe_regmap(struct plat_sci_port *cfg) 341 { 342 switch (cfg->type) { 343 case PORT_SCI: 344 cfg->regtype = SCIx_SCI_REGTYPE; 345 break; 346 case PORT_IRDA: 347 cfg->regtype = SCIx_IRDA_REGTYPE; 348 break; 349 case PORT_SCIFA: 350 cfg->regtype = SCIx_SCIFA_REGTYPE; 351 break; 352 case PORT_SCIFB: 353 cfg->regtype = SCIx_SCIFB_REGTYPE; 354 break; 355 case PORT_SCIF: 356 /* 357 * The SH-4 is a bit of a misnomer here, although that's 358 * where this particular port layout originated. This 359 * configuration (or some slight variation thereof) 360 * remains the dominant model for all SCIFs. 361 */ 362 cfg->regtype = SCIx_SH4_SCIF_REGTYPE; 363 break; 364 default: 365 printk(KERN_ERR "Can't probe register map for given port\n"); 366 return -EINVAL; 367 } 368 369 return 0; 370 } 371 372 static void sci_port_enable(struct sci_port *sci_port) 373 { 374 if (!sci_port->port.dev) 375 return; 376 377 pm_runtime_get_sync(sci_port->port.dev); 378 379 clk_enable(sci_port->iclk); 380 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 381 clk_enable(sci_port->fclk); 382 } 383 384 static void sci_port_disable(struct sci_port *sci_port) 385 { 386 if (!sci_port->port.dev) 387 return; 388 389 clk_disable(sci_port->fclk); 390 clk_disable(sci_port->iclk); 391 392 pm_runtime_put_sync(sci_port->port.dev); 393 } 394 395 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 396 397 #ifdef CONFIG_CONSOLE_POLL 398 static int sci_poll_get_char(struct uart_port *port) 399 { 400 unsigned short status; 401 int c; 402 403 do { 404 status = sci_in(port, SCxSR); 405 if (status & SCxSR_ERRORS(port)) { 406 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 407 continue; 408 } 409 break; 410 } while (1); 411 412 if (!(status & SCxSR_RDxF(port))) 413 return NO_POLL_CHAR; 414 415 c = sci_in(port, SCxRDR); 416 417 /* Dummy read */ 418 sci_in(port, SCxSR); 419 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 420 421 return c; 422 } 423 #endif 424 425 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 426 { 427 unsigned short status; 428 429 do { 430 status = sci_in(port, SCxSR); 431 } while (!(status & SCxSR_TDxE(port))); 432 433 sci_out(port, SCxTDR, c); 434 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 435 } 436 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 437 438 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 439 { 440 struct sci_port *s = to_sci_port(port); 441 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; 442 443 /* 444 * Use port-specific handler if provided. 445 */ 446 if (s->cfg->ops && s->cfg->ops->init_pins) { 447 s->cfg->ops->init_pins(port, cflag); 448 return; 449 } 450 451 /* 452 * For the generic path SCSPTR is necessary. Bail out if that's 453 * unavailable, too. 454 */ 455 if (!reg->size) 456 return; 457 458 if (!(cflag & CRTSCTS)) 459 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */ 460 } 461 462 static int sci_txfill(struct uart_port *port) 463 { 464 struct plat_sci_reg *reg; 465 466 reg = sci_getreg(port, SCTFDR); 467 if (reg->size) 468 return sci_in(port, SCTFDR) & 0xff; 469 470 reg = sci_getreg(port, SCFDR); 471 if (reg->size) 472 return sci_in(port, SCFDR) >> 8; 473 474 return !(sci_in(port, SCxSR) & SCI_TDRE); 475 } 476 477 static int sci_txroom(struct uart_port *port) 478 { 479 return port->fifosize - sci_txfill(port); 480 } 481 482 static int sci_rxfill(struct uart_port *port) 483 { 484 struct plat_sci_reg *reg; 485 486 reg = sci_getreg(port, SCRFDR); 487 if (reg->size) 488 return sci_in(port, SCRFDR) & 0xff; 489 490 reg = sci_getreg(port, SCFDR); 491 if (reg->size) 492 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1); 493 494 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 495 } 496 497 /* 498 * SCI helper for checking the state of the muxed port/RXD pins. 499 */ 500 static inline int sci_rxd_in(struct uart_port *port) 501 { 502 struct sci_port *s = to_sci_port(port); 503 504 if (s->cfg->port_reg <= 0) 505 return 1; 506 507 return !!__raw_readb(s->cfg->port_reg); 508 } 509 510 /* ********************************************************************** * 511 * the interrupt related routines * 512 * ********************************************************************** */ 513 514 static void sci_transmit_chars(struct uart_port *port) 515 { 516 struct circ_buf *xmit = &port->state->xmit; 517 unsigned int stopped = uart_tx_stopped(port); 518 unsigned short status; 519 unsigned short ctrl; 520 int count; 521 522 status = sci_in(port, SCxSR); 523 if (!(status & SCxSR_TDxE(port))) { 524 ctrl = sci_in(port, SCSCR); 525 if (uart_circ_empty(xmit)) 526 ctrl &= ~SCSCR_TIE; 527 else 528 ctrl |= SCSCR_TIE; 529 sci_out(port, SCSCR, ctrl); 530 return; 531 } 532 533 count = sci_txroom(port); 534 535 do { 536 unsigned char c; 537 538 if (port->x_char) { 539 c = port->x_char; 540 port->x_char = 0; 541 } else if (!uart_circ_empty(xmit) && !stopped) { 542 c = xmit->buf[xmit->tail]; 543 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 544 } else { 545 break; 546 } 547 548 sci_out(port, SCxTDR, c); 549 550 port->icount.tx++; 551 } while (--count > 0); 552 553 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 554 555 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 556 uart_write_wakeup(port); 557 if (uart_circ_empty(xmit)) { 558 sci_stop_tx(port); 559 } else { 560 ctrl = sci_in(port, SCSCR); 561 562 if (port->type != PORT_SCI) { 563 sci_in(port, SCxSR); /* Dummy read */ 564 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 565 } 566 567 ctrl |= SCSCR_TIE; 568 sci_out(port, SCSCR, ctrl); 569 } 570 } 571 572 /* On SH3, SCIF may read end-of-break as a space->mark char */ 573 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 574 575 static void sci_receive_chars(struct uart_port *port) 576 { 577 struct sci_port *sci_port = to_sci_port(port); 578 struct tty_struct *tty = port->state->port.tty; 579 int i, count, copied = 0; 580 unsigned short status; 581 unsigned char flag; 582 583 status = sci_in(port, SCxSR); 584 if (!(status & SCxSR_RDxF(port))) 585 return; 586 587 while (1) { 588 /* Don't copy more bytes than there is room for in the buffer */ 589 count = tty_buffer_request_room(tty, sci_rxfill(port)); 590 591 /* If for any reason we can't copy more data, we're done! */ 592 if (count == 0) 593 break; 594 595 if (port->type == PORT_SCI) { 596 char c = sci_in(port, SCxRDR); 597 if (uart_handle_sysrq_char(port, c) || 598 sci_port->break_flag) 599 count = 0; 600 else 601 tty_insert_flip_char(tty, c, TTY_NORMAL); 602 } else { 603 for (i = 0; i < count; i++) { 604 char c = sci_in(port, SCxRDR); 605 status = sci_in(port, SCxSR); 606 #if defined(CONFIG_CPU_SH3) 607 /* Skip "chars" during break */ 608 if (sci_port->break_flag) { 609 if ((c == 0) && 610 (status & SCxSR_FER(port))) { 611 count--; i--; 612 continue; 613 } 614 615 /* Nonzero => end-of-break */ 616 dev_dbg(port->dev, "debounce<%02x>\n", c); 617 sci_port->break_flag = 0; 618 619 if (STEPFN(c)) { 620 count--; i--; 621 continue; 622 } 623 } 624 #endif /* CONFIG_CPU_SH3 */ 625 if (uart_handle_sysrq_char(port, c)) { 626 count--; i--; 627 continue; 628 } 629 630 /* Store data and status */ 631 if (status & SCxSR_FER(port)) { 632 flag = TTY_FRAME; 633 dev_notice(port->dev, "frame error\n"); 634 } else if (status & SCxSR_PER(port)) { 635 flag = TTY_PARITY; 636 dev_notice(port->dev, "parity error\n"); 637 } else 638 flag = TTY_NORMAL; 639 640 tty_insert_flip_char(tty, c, flag); 641 } 642 } 643 644 sci_in(port, SCxSR); /* dummy read */ 645 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 646 647 copied += count; 648 port->icount.rx += count; 649 } 650 651 if (copied) { 652 /* Tell the rest of the system the news. New characters! */ 653 tty_flip_buffer_push(tty); 654 } else { 655 sci_in(port, SCxSR); /* dummy read */ 656 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 657 } 658 } 659 660 #define SCI_BREAK_JIFFIES (HZ/20) 661 662 /* 663 * The sci generates interrupts during the break, 664 * 1 per millisecond or so during the break period, for 9600 baud. 665 * So dont bother disabling interrupts. 666 * But dont want more than 1 break event. 667 * Use a kernel timer to periodically poll the rx line until 668 * the break is finished. 669 */ 670 static inline void sci_schedule_break_timer(struct sci_port *port) 671 { 672 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); 673 } 674 675 /* Ensure that two consecutive samples find the break over. */ 676 static void sci_break_timer(unsigned long data) 677 { 678 struct sci_port *port = (struct sci_port *)data; 679 680 sci_port_enable(port); 681 682 if (sci_rxd_in(&port->port) == 0) { 683 port->break_flag = 1; 684 sci_schedule_break_timer(port); 685 } else if (port->break_flag == 1) { 686 /* break is over. */ 687 port->break_flag = 2; 688 sci_schedule_break_timer(port); 689 } else 690 port->break_flag = 0; 691 692 sci_port_disable(port); 693 } 694 695 static int sci_handle_errors(struct uart_port *port) 696 { 697 int copied = 0; 698 unsigned short status = sci_in(port, SCxSR); 699 struct tty_struct *tty = port->state->port.tty; 700 struct sci_port *s = to_sci_port(port); 701 702 /* 703 * Handle overruns, if supported. 704 */ 705 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) { 706 if (status & (1 << s->cfg->overrun_bit)) { 707 /* overrun error */ 708 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 709 copied++; 710 711 dev_notice(port->dev, "overrun error"); 712 } 713 } 714 715 if (status & SCxSR_FER(port)) { 716 if (sci_rxd_in(port) == 0) { 717 /* Notify of BREAK */ 718 struct sci_port *sci_port = to_sci_port(port); 719 720 if (!sci_port->break_flag) { 721 sci_port->break_flag = 1; 722 sci_schedule_break_timer(sci_port); 723 724 /* Do sysrq handling. */ 725 if (uart_handle_break(port)) 726 return 0; 727 728 dev_dbg(port->dev, "BREAK detected\n"); 729 730 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 731 copied++; 732 } 733 734 } else { 735 /* frame error */ 736 if (tty_insert_flip_char(tty, 0, TTY_FRAME)) 737 copied++; 738 739 dev_notice(port->dev, "frame error\n"); 740 } 741 } 742 743 if (status & SCxSR_PER(port)) { 744 /* parity error */ 745 if (tty_insert_flip_char(tty, 0, TTY_PARITY)) 746 copied++; 747 748 dev_notice(port->dev, "parity error"); 749 } 750 751 if (copied) 752 tty_flip_buffer_push(tty); 753 754 return copied; 755 } 756 757 static int sci_handle_fifo_overrun(struct uart_port *port) 758 { 759 struct tty_struct *tty = port->state->port.tty; 760 struct sci_port *s = to_sci_port(port); 761 struct plat_sci_reg *reg; 762 int copied = 0; 763 764 reg = sci_getreg(port, SCLSR); 765 if (!reg->size) 766 return 0; 767 768 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) { 769 sci_out(port, SCLSR, 0); 770 771 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 772 tty_flip_buffer_push(tty); 773 774 dev_notice(port->dev, "overrun error\n"); 775 copied++; 776 } 777 778 return copied; 779 } 780 781 static int sci_handle_breaks(struct uart_port *port) 782 { 783 int copied = 0; 784 unsigned short status = sci_in(port, SCxSR); 785 struct tty_struct *tty = port->state->port.tty; 786 struct sci_port *s = to_sci_port(port); 787 788 if (uart_handle_break(port)) 789 return 0; 790 791 if (!s->break_flag && status & SCxSR_BRK(port)) { 792 #if defined(CONFIG_CPU_SH3) 793 /* Debounce break */ 794 s->break_flag = 1; 795 #endif 796 /* Notify of BREAK */ 797 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 798 copied++; 799 800 dev_dbg(port->dev, "BREAK detected\n"); 801 } 802 803 if (copied) 804 tty_flip_buffer_push(tty); 805 806 copied += sci_handle_fifo_overrun(port); 807 808 return copied; 809 } 810 811 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 812 { 813 #ifdef CONFIG_SERIAL_SH_SCI_DMA 814 struct uart_port *port = ptr; 815 struct sci_port *s = to_sci_port(port); 816 817 if (s->chan_rx) { 818 u16 scr = sci_in(port, SCSCR); 819 u16 ssr = sci_in(port, SCxSR); 820 821 /* Disable future Rx interrupts */ 822 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 823 disable_irq_nosync(irq); 824 scr |= 0x4000; 825 } else { 826 scr &= ~SCSCR_RIE; 827 } 828 sci_out(port, SCSCR, scr); 829 /* Clear current interrupt */ 830 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); 831 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 832 jiffies, s->rx_timeout); 833 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 834 835 return IRQ_HANDLED; 836 } 837 #endif 838 839 /* I think sci_receive_chars has to be called irrespective 840 * of whether the I_IXOFF is set, otherwise, how is the interrupt 841 * to be disabled? 842 */ 843 sci_receive_chars(ptr); 844 845 return IRQ_HANDLED; 846 } 847 848 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 849 { 850 struct uart_port *port = ptr; 851 unsigned long flags; 852 853 spin_lock_irqsave(&port->lock, flags); 854 sci_transmit_chars(port); 855 spin_unlock_irqrestore(&port->lock, flags); 856 857 return IRQ_HANDLED; 858 } 859 860 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 861 { 862 struct uart_port *port = ptr; 863 864 /* Handle errors */ 865 if (port->type == PORT_SCI) { 866 if (sci_handle_errors(port)) { 867 /* discard character in rx buffer */ 868 sci_in(port, SCxSR); 869 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 870 } 871 } else { 872 sci_handle_fifo_overrun(port); 873 sci_rx_interrupt(irq, ptr); 874 } 875 876 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 877 878 /* Kick the transmission */ 879 sci_tx_interrupt(irq, ptr); 880 881 return IRQ_HANDLED; 882 } 883 884 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 885 { 886 struct uart_port *port = ptr; 887 888 /* Handle BREAKs */ 889 sci_handle_breaks(port); 890 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); 891 892 return IRQ_HANDLED; 893 } 894 895 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 896 { 897 /* 898 * Not all ports (such as SCIFA) will support REIE. Rather than 899 * special-casing the port type, we check the port initialization 900 * IRQ enable mask to see whether the IRQ is desired at all. If 901 * it's unset, it's logically inferred that there's no point in 902 * testing for it. 903 */ 904 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 905 } 906 907 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 908 { 909 unsigned short ssr_status, scr_status, err_enabled; 910 struct uart_port *port = ptr; 911 struct sci_port *s = to_sci_port(port); 912 irqreturn_t ret = IRQ_NONE; 913 914 ssr_status = sci_in(port, SCxSR); 915 scr_status = sci_in(port, SCSCR); 916 err_enabled = scr_status & port_rx_irq_mask(port); 917 918 /* Tx Interrupt */ 919 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 920 !s->chan_tx) 921 ret = sci_tx_interrupt(irq, ptr); 922 923 /* 924 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 925 * DR flags 926 */ 927 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 928 (scr_status & SCSCR_RIE)) 929 ret = sci_rx_interrupt(irq, ptr); 930 931 /* Error Interrupt */ 932 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 933 ret = sci_er_interrupt(irq, ptr); 934 935 /* Break Interrupt */ 936 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 937 ret = sci_br_interrupt(irq, ptr); 938 939 return ret; 940 } 941 942 /* 943 * Here we define a transition notifier so that we can update all of our 944 * ports' baud rate when the peripheral clock changes. 945 */ 946 static int sci_notifier(struct notifier_block *self, 947 unsigned long phase, void *p) 948 { 949 struct sci_port *sci_port; 950 unsigned long flags; 951 952 sci_port = container_of(self, struct sci_port, freq_transition); 953 954 if ((phase == CPUFREQ_POSTCHANGE) || 955 (phase == CPUFREQ_RESUMECHANGE)) { 956 struct uart_port *port = &sci_port->port; 957 958 spin_lock_irqsave(&port->lock, flags); 959 port->uartclk = clk_get_rate(sci_port->iclk); 960 spin_unlock_irqrestore(&port->lock, flags); 961 } 962 963 return NOTIFY_OK; 964 } 965 966 static struct sci_irq_desc { 967 const char *desc; 968 irq_handler_t handler; 969 } sci_irq_desc[] = { 970 /* 971 * Split out handlers, the default case. 972 */ 973 [SCIx_ERI_IRQ] = { 974 .desc = "rx err", 975 .handler = sci_er_interrupt, 976 }, 977 978 [SCIx_RXI_IRQ] = { 979 .desc = "rx full", 980 .handler = sci_rx_interrupt, 981 }, 982 983 [SCIx_TXI_IRQ] = { 984 .desc = "tx empty", 985 .handler = sci_tx_interrupt, 986 }, 987 988 [SCIx_BRI_IRQ] = { 989 .desc = "break", 990 .handler = sci_br_interrupt, 991 }, 992 993 /* 994 * Special muxed handler. 995 */ 996 [SCIx_MUX_IRQ] = { 997 .desc = "mux", 998 .handler = sci_mpxed_interrupt, 999 }, 1000 }; 1001 1002 static int sci_request_irq(struct sci_port *port) 1003 { 1004 struct uart_port *up = &port->port; 1005 int i, j, ret = 0; 1006 1007 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1008 struct sci_irq_desc *desc; 1009 unsigned int irq; 1010 1011 if (SCIx_IRQ_IS_MUXED(port)) { 1012 i = SCIx_MUX_IRQ; 1013 irq = up->irq; 1014 } else 1015 irq = port->cfg->irqs[i]; 1016 1017 desc = sci_irq_desc + i; 1018 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1019 dev_name(up->dev), desc->desc); 1020 if (!port->irqstr[j]) { 1021 dev_err(up->dev, "Failed to allocate %s IRQ string\n", 1022 desc->desc); 1023 goto out_nomem; 1024 } 1025 1026 ret = request_irq(irq, desc->handler, up->irqflags, 1027 port->irqstr[j], port); 1028 if (unlikely(ret)) { 1029 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1030 goto out_noirq; 1031 } 1032 } 1033 1034 return 0; 1035 1036 out_noirq: 1037 while (--i >= 0) 1038 free_irq(port->cfg->irqs[i], port); 1039 1040 out_nomem: 1041 while (--j >= 0) 1042 kfree(port->irqstr[j]); 1043 1044 return ret; 1045 } 1046 1047 static void sci_free_irq(struct sci_port *port) 1048 { 1049 int i; 1050 1051 /* 1052 * Intentionally in reverse order so we iterate over the muxed 1053 * IRQ first. 1054 */ 1055 for (i = 0; i < SCIx_NR_IRQS; i++) { 1056 free_irq(port->cfg->irqs[i], port); 1057 kfree(port->irqstr[i]); 1058 1059 if (SCIx_IRQ_IS_MUXED(port)) { 1060 /* If there's only one IRQ, we're done. */ 1061 return; 1062 } 1063 } 1064 } 1065 1066 static unsigned int sci_tx_empty(struct uart_port *port) 1067 { 1068 unsigned short status = sci_in(port, SCxSR); 1069 unsigned short in_tx_fifo = sci_txfill(port); 1070 1071 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1072 } 1073 1074 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1075 { 1076 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ 1077 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ 1078 /* If you have signals for DTR and DCD, please implement here. */ 1079 } 1080 1081 static unsigned int sci_get_mctrl(struct uart_port *port) 1082 { 1083 /* This routine is used for getting signals of: DTR, DCD, DSR, RI, 1084 and CTS/RTS */ 1085 1086 return TIOCM_DTR | TIOCM_RTS | TIOCM_CTS | TIOCM_DSR; 1087 } 1088 1089 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1090 static void sci_dma_tx_complete(void *arg) 1091 { 1092 struct sci_port *s = arg; 1093 struct uart_port *port = &s->port; 1094 struct circ_buf *xmit = &port->state->xmit; 1095 unsigned long flags; 1096 1097 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1098 1099 spin_lock_irqsave(&port->lock, flags); 1100 1101 xmit->tail += sg_dma_len(&s->sg_tx); 1102 xmit->tail &= UART_XMIT_SIZE - 1; 1103 1104 port->icount.tx += sg_dma_len(&s->sg_tx); 1105 1106 async_tx_ack(s->desc_tx); 1107 s->cookie_tx = -EINVAL; 1108 s->desc_tx = NULL; 1109 1110 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1111 uart_write_wakeup(port); 1112 1113 if (!uart_circ_empty(xmit)) { 1114 schedule_work(&s->work_tx); 1115 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1116 u16 ctrl = sci_in(port, SCSCR); 1117 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1118 } 1119 1120 spin_unlock_irqrestore(&port->lock, flags); 1121 } 1122 1123 /* Locking: called with port lock held */ 1124 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty, 1125 size_t count) 1126 { 1127 struct uart_port *port = &s->port; 1128 int i, active, room; 1129 1130 room = tty_buffer_request_room(tty, count); 1131 1132 if (s->active_rx == s->cookie_rx[0]) { 1133 active = 0; 1134 } else if (s->active_rx == s->cookie_rx[1]) { 1135 active = 1; 1136 } else { 1137 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1138 return 0; 1139 } 1140 1141 if (room < count) 1142 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 1143 count - room); 1144 if (!room) 1145 return room; 1146 1147 for (i = 0; i < room; i++) 1148 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i], 1149 TTY_NORMAL); 1150 1151 port->icount.rx += room; 1152 1153 return room; 1154 } 1155 1156 static void sci_dma_rx_complete(void *arg) 1157 { 1158 struct sci_port *s = arg; 1159 struct uart_port *port = &s->port; 1160 struct tty_struct *tty = port->state->port.tty; 1161 unsigned long flags; 1162 int count; 1163 1164 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); 1165 1166 spin_lock_irqsave(&port->lock, flags); 1167 1168 count = sci_dma_rx_push(s, tty, s->buf_len_rx); 1169 1170 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1171 1172 spin_unlock_irqrestore(&port->lock, flags); 1173 1174 if (count) 1175 tty_flip_buffer_push(tty); 1176 1177 schedule_work(&s->work_rx); 1178 } 1179 1180 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1181 { 1182 struct dma_chan *chan = s->chan_rx; 1183 struct uart_port *port = &s->port; 1184 1185 s->chan_rx = NULL; 1186 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1187 dma_release_channel(chan); 1188 if (sg_dma_address(&s->sg_rx[0])) 1189 dma_free_coherent(port->dev, s->buf_len_rx * 2, 1190 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); 1191 if (enable_pio) 1192 sci_start_rx(port); 1193 } 1194 1195 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1196 { 1197 struct dma_chan *chan = s->chan_tx; 1198 struct uart_port *port = &s->port; 1199 1200 s->chan_tx = NULL; 1201 s->cookie_tx = -EINVAL; 1202 dma_release_channel(chan); 1203 if (enable_pio) 1204 sci_start_tx(port); 1205 } 1206 1207 static void sci_submit_rx(struct sci_port *s) 1208 { 1209 struct dma_chan *chan = s->chan_rx; 1210 int i; 1211 1212 for (i = 0; i < 2; i++) { 1213 struct scatterlist *sg = &s->sg_rx[i]; 1214 struct dma_async_tx_descriptor *desc; 1215 1216 desc = chan->device->device_prep_slave_sg(chan, 1217 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT); 1218 1219 if (desc) { 1220 s->desc_rx[i] = desc; 1221 desc->callback = sci_dma_rx_complete; 1222 desc->callback_param = s; 1223 s->cookie_rx[i] = desc->tx_submit(desc); 1224 } 1225 1226 if (!desc || s->cookie_rx[i] < 0) { 1227 if (i) { 1228 async_tx_ack(s->desc_rx[0]); 1229 s->cookie_rx[0] = -EINVAL; 1230 } 1231 if (desc) { 1232 async_tx_ack(desc); 1233 s->cookie_rx[i] = -EINVAL; 1234 } 1235 dev_warn(s->port.dev, 1236 "failed to re-start DMA, using PIO\n"); 1237 sci_rx_dma_release(s, true); 1238 return; 1239 } 1240 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, 1241 s->cookie_rx[i], i); 1242 } 1243 1244 s->active_rx = s->cookie_rx[0]; 1245 1246 dma_async_issue_pending(chan); 1247 } 1248 1249 static void work_fn_rx(struct work_struct *work) 1250 { 1251 struct sci_port *s = container_of(work, struct sci_port, work_rx); 1252 struct uart_port *port = &s->port; 1253 struct dma_async_tx_descriptor *desc; 1254 int new; 1255 1256 if (s->active_rx == s->cookie_rx[0]) { 1257 new = 0; 1258 } else if (s->active_rx == s->cookie_rx[1]) { 1259 new = 1; 1260 } else { 1261 dev_err(port->dev, "cookie %d not found!\n", s->active_rx); 1262 return; 1263 } 1264 desc = s->desc_rx[new]; 1265 1266 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != 1267 DMA_SUCCESS) { 1268 /* Handle incomplete DMA receive */ 1269 struct tty_struct *tty = port->state->port.tty; 1270 struct dma_chan *chan = s->chan_rx; 1271 struct sh_desc *sh_desc = container_of(desc, struct sh_desc, 1272 async_tx); 1273 unsigned long flags; 1274 int count; 1275 1276 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 1277 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", 1278 sh_desc->partial, sh_desc->cookie); 1279 1280 spin_lock_irqsave(&port->lock, flags); 1281 count = sci_dma_rx_push(s, tty, sh_desc->partial); 1282 spin_unlock_irqrestore(&port->lock, flags); 1283 1284 if (count) 1285 tty_flip_buffer_push(tty); 1286 1287 sci_submit_rx(s); 1288 1289 return; 1290 } 1291 1292 s->cookie_rx[new] = desc->tx_submit(desc); 1293 if (s->cookie_rx[new] < 0) { 1294 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1295 sci_rx_dma_release(s, true); 1296 return; 1297 } 1298 1299 s->active_rx = s->cookie_rx[!new]; 1300 1301 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, 1302 s->cookie_rx[new], new, s->active_rx); 1303 } 1304 1305 static void work_fn_tx(struct work_struct *work) 1306 { 1307 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1308 struct dma_async_tx_descriptor *desc; 1309 struct dma_chan *chan = s->chan_tx; 1310 struct uart_port *port = &s->port; 1311 struct circ_buf *xmit = &port->state->xmit; 1312 struct scatterlist *sg = &s->sg_tx; 1313 1314 /* 1315 * DMA is idle now. 1316 * Port xmit buffer is already mapped, and it is one page... Just adjust 1317 * offsets and lengths. Since it is a circular buffer, we have to 1318 * transmit till the end, and then the rest. Take the port lock to get a 1319 * consistent xmit buffer state. 1320 */ 1321 spin_lock_irq(&port->lock); 1322 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 1323 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + 1324 sg->offset; 1325 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1326 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1327 spin_unlock_irq(&port->lock); 1328 1329 BUG_ON(!sg_dma_len(sg)); 1330 1331 desc = chan->device->device_prep_slave_sg(chan, 1332 sg, s->sg_len_tx, DMA_TO_DEVICE, 1333 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1334 if (!desc) { 1335 /* switch to PIO */ 1336 sci_tx_dma_release(s, true); 1337 return; 1338 } 1339 1340 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 1341 1342 spin_lock_irq(&port->lock); 1343 s->desc_tx = desc; 1344 desc->callback = sci_dma_tx_complete; 1345 desc->callback_param = s; 1346 spin_unlock_irq(&port->lock); 1347 s->cookie_tx = desc->tx_submit(desc); 1348 if (s->cookie_tx < 0) { 1349 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1350 /* switch to PIO */ 1351 sci_tx_dma_release(s, true); 1352 return; 1353 } 1354 1355 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, 1356 xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1357 1358 dma_async_issue_pending(chan); 1359 } 1360 #endif 1361 1362 static void sci_start_tx(struct uart_port *port) 1363 { 1364 struct sci_port *s = to_sci_port(port); 1365 unsigned short ctrl; 1366 1367 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1368 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1369 u16 new, scr = sci_in(port, SCSCR); 1370 if (s->chan_tx) 1371 new = scr | 0x8000; 1372 else 1373 new = scr & ~0x8000; 1374 if (new != scr) 1375 sci_out(port, SCSCR, new); 1376 } 1377 1378 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 1379 s->cookie_tx < 0) 1380 schedule_work(&s->work_tx); 1381 #endif 1382 1383 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1384 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 1385 ctrl = sci_in(port, SCSCR); 1386 sci_out(port, SCSCR, ctrl | SCSCR_TIE); 1387 } 1388 } 1389 1390 static void sci_stop_tx(struct uart_port *port) 1391 { 1392 unsigned short ctrl; 1393 1394 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 1395 ctrl = sci_in(port, SCSCR); 1396 1397 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1398 ctrl &= ~0x8000; 1399 1400 ctrl &= ~SCSCR_TIE; 1401 1402 sci_out(port, SCSCR, ctrl); 1403 } 1404 1405 static void sci_start_rx(struct uart_port *port) 1406 { 1407 unsigned short ctrl; 1408 1409 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port); 1410 1411 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1412 ctrl &= ~0x4000; 1413 1414 sci_out(port, SCSCR, ctrl); 1415 } 1416 1417 static void sci_stop_rx(struct uart_port *port) 1418 { 1419 unsigned short ctrl; 1420 1421 ctrl = sci_in(port, SCSCR); 1422 1423 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1424 ctrl &= ~0x4000; 1425 1426 ctrl &= ~port_rx_irq_mask(port); 1427 1428 sci_out(port, SCSCR, ctrl); 1429 } 1430 1431 static void sci_enable_ms(struct uart_port *port) 1432 { 1433 /* Nothing here yet .. */ 1434 } 1435 1436 static void sci_break_ctl(struct uart_port *port, int break_state) 1437 { 1438 /* Nothing here yet .. */ 1439 } 1440 1441 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1442 static bool filter(struct dma_chan *chan, void *slave) 1443 { 1444 struct sh_dmae_slave *param = slave; 1445 1446 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, 1447 param->slave_id); 1448 1449 if (param->dma_dev == chan->device->dev) { 1450 chan->private = param; 1451 return true; 1452 } else { 1453 return false; 1454 } 1455 } 1456 1457 static void rx_timer_fn(unsigned long arg) 1458 { 1459 struct sci_port *s = (struct sci_port *)arg; 1460 struct uart_port *port = &s->port; 1461 u16 scr = sci_in(port, SCSCR); 1462 1463 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1464 scr &= ~0x4000; 1465 enable_irq(s->cfg->irqs[1]); 1466 } 1467 sci_out(port, SCSCR, scr | SCSCR_RIE); 1468 dev_dbg(port->dev, "DMA Rx timed out\n"); 1469 schedule_work(&s->work_rx); 1470 } 1471 1472 static void sci_request_dma(struct uart_port *port) 1473 { 1474 struct sci_port *s = to_sci_port(port); 1475 struct sh_dmae_slave *param; 1476 struct dma_chan *chan; 1477 dma_cap_mask_t mask; 1478 int nent; 1479 1480 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__, 1481 port->line, s->cfg->dma_dev); 1482 1483 if (!s->cfg->dma_dev) 1484 return; 1485 1486 dma_cap_zero(mask); 1487 dma_cap_set(DMA_SLAVE, mask); 1488 1489 param = &s->param_tx; 1490 1491 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ 1492 param->slave_id = s->cfg->dma_slave_tx; 1493 param->dma_dev = s->cfg->dma_dev; 1494 1495 s->cookie_tx = -EINVAL; 1496 chan = dma_request_channel(mask, filter, param); 1497 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1498 if (chan) { 1499 s->chan_tx = chan; 1500 sg_init_table(&s->sg_tx, 1); 1501 /* UART circular tx buffer is an aligned page. */ 1502 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 1503 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), 1504 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); 1505 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); 1506 if (!nent) 1507 sci_tx_dma_release(s, false); 1508 else 1509 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1510 sg_dma_len(&s->sg_tx), 1511 port->state->xmit.buf, sg_dma_address(&s->sg_tx)); 1512 1513 s->sg_len_tx = nent; 1514 1515 INIT_WORK(&s->work_tx, work_fn_tx); 1516 } 1517 1518 param = &s->param_rx; 1519 1520 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ 1521 param->slave_id = s->cfg->dma_slave_rx; 1522 param->dma_dev = s->cfg->dma_dev; 1523 1524 chan = dma_request_channel(mask, filter, param); 1525 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1526 if (chan) { 1527 dma_addr_t dma[2]; 1528 void *buf[2]; 1529 int i; 1530 1531 s->chan_rx = chan; 1532 1533 s->buf_len_rx = 2 * max(16, (int)port->fifosize); 1534 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, 1535 &dma[0], GFP_KERNEL); 1536 1537 if (!buf[0]) { 1538 dev_warn(port->dev, 1539 "failed to allocate dma buffer, using PIO\n"); 1540 sci_rx_dma_release(s, true); 1541 return; 1542 } 1543 1544 buf[1] = buf[0] + s->buf_len_rx; 1545 dma[1] = dma[0] + s->buf_len_rx; 1546 1547 for (i = 0; i < 2; i++) { 1548 struct scatterlist *sg = &s->sg_rx[i]; 1549 1550 sg_init_table(sg, 1); 1551 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, 1552 (int)buf[i] & ~PAGE_MASK); 1553 sg_dma_address(sg) = dma[i]; 1554 } 1555 1556 INIT_WORK(&s->work_rx, work_fn_rx); 1557 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1558 1559 sci_submit_rx(s); 1560 } 1561 } 1562 1563 static void sci_free_dma(struct uart_port *port) 1564 { 1565 struct sci_port *s = to_sci_port(port); 1566 1567 if (!s->cfg->dma_dev) 1568 return; 1569 1570 if (s->chan_tx) 1571 sci_tx_dma_release(s, false); 1572 if (s->chan_rx) 1573 sci_rx_dma_release(s, false); 1574 } 1575 #else 1576 static inline void sci_request_dma(struct uart_port *port) 1577 { 1578 } 1579 1580 static inline void sci_free_dma(struct uart_port *port) 1581 { 1582 } 1583 #endif 1584 1585 static int sci_startup(struct uart_port *port) 1586 { 1587 struct sci_port *s = to_sci_port(port); 1588 int ret; 1589 1590 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1591 1592 sci_port_enable(s); 1593 1594 ret = sci_request_irq(s); 1595 if (unlikely(ret < 0)) 1596 return ret; 1597 1598 sci_request_dma(port); 1599 1600 sci_start_tx(port); 1601 sci_start_rx(port); 1602 1603 return 0; 1604 } 1605 1606 static void sci_shutdown(struct uart_port *port) 1607 { 1608 struct sci_port *s = to_sci_port(port); 1609 1610 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1611 1612 sci_stop_rx(port); 1613 sci_stop_tx(port); 1614 1615 sci_free_dma(port); 1616 sci_free_irq(s); 1617 1618 sci_port_disable(s); 1619 } 1620 1621 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, 1622 unsigned long freq) 1623 { 1624 switch (algo_id) { 1625 case SCBRR_ALGO_1: 1626 return ((freq + 16 * bps) / (16 * bps) - 1); 1627 case SCBRR_ALGO_2: 1628 return ((freq + 16 * bps) / (32 * bps) - 1); 1629 case SCBRR_ALGO_3: 1630 return (((freq * 2) + 16 * bps) / (16 * bps) - 1); 1631 case SCBRR_ALGO_4: 1632 return (((freq * 2) + 16 * bps) / (32 * bps) - 1); 1633 case SCBRR_ALGO_5: 1634 return (((freq * 1000 / 32) / bps) - 1); 1635 } 1636 1637 /* Warn, but use a safe default */ 1638 WARN_ON(1); 1639 1640 return ((freq + 16 * bps) / (32 * bps) - 1); 1641 } 1642 1643 static void sci_reset(struct uart_port *port) 1644 { 1645 unsigned int status; 1646 1647 do { 1648 status = sci_in(port, SCxSR); 1649 } while (!(status & SCxSR_TEND(port))); 1650 1651 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1652 1653 if (port->type != PORT_SCI) 1654 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1655 } 1656 1657 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 1658 struct ktermios *old) 1659 { 1660 struct sci_port *s = to_sci_port(port); 1661 unsigned int baud, smr_val, max_baud; 1662 int t = -1; 1663 u16 scfcr = 0; 1664 1665 /* 1666 * earlyprintk comes here early on with port->uartclk set to zero. 1667 * the clock framework is not up and running at this point so here 1668 * we assume that 115200 is the maximum baud rate. please note that 1669 * the baud rate is not programmed during earlyprintk - it is assumed 1670 * that the previous boot loader has enabled required clocks and 1671 * setup the baud rate generator hardware for us already. 1672 */ 1673 max_baud = port->uartclk ? port->uartclk / 16 : 115200; 1674 1675 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 1676 if (likely(baud && port->uartclk)) 1677 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); 1678 1679 sci_port_enable(s); 1680 1681 sci_reset(port); 1682 1683 smr_val = sci_in(port, SCSMR) & 3; 1684 1685 if ((termios->c_cflag & CSIZE) == CS7) 1686 smr_val |= 0x40; 1687 if (termios->c_cflag & PARENB) 1688 smr_val |= 0x20; 1689 if (termios->c_cflag & PARODD) 1690 smr_val |= 0x30; 1691 if (termios->c_cflag & CSTOPB) 1692 smr_val |= 0x08; 1693 1694 uart_update_timeout(port, termios->c_cflag, baud); 1695 1696 sci_out(port, SCSMR, smr_val); 1697 1698 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t, 1699 s->cfg->scscr); 1700 1701 if (t > 0) { 1702 if (t >= 256) { 1703 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); 1704 t >>= 2; 1705 } else 1706 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); 1707 1708 sci_out(port, SCBRR, t); 1709 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 1710 } 1711 1712 sci_init_pins(port, termios->c_cflag); 1713 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0)); 1714 1715 sci_out(port, SCSCR, s->cfg->scscr); 1716 1717 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1718 /* 1719 * Calculate delay for 1.5 DMA buffers: see 1720 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits 1721 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function 1722 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." 1723 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO 1724 * sizes), but it has been found out experimentally, that this is not 1725 * enough: the driver too often needlessly runs on a DMA timeout. 20ms 1726 * as a minimum seem to work perfectly. 1727 */ 1728 if (s->chan_rx) { 1729 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / 1730 port->fifosize / 2; 1731 dev_dbg(port->dev, 1732 "DMA Rx t-out %ums, tty t-out %u jiffies\n", 1733 s->rx_timeout * 1000 / HZ, port->timeout); 1734 if (s->rx_timeout < msecs_to_jiffies(20)) 1735 s->rx_timeout = msecs_to_jiffies(20); 1736 } 1737 #endif 1738 1739 if ((termios->c_cflag & CREAD) != 0) 1740 sci_start_rx(port); 1741 1742 sci_port_disable(s); 1743 } 1744 1745 static const char *sci_type(struct uart_port *port) 1746 { 1747 switch (port->type) { 1748 case PORT_IRDA: 1749 return "irda"; 1750 case PORT_SCI: 1751 return "sci"; 1752 case PORT_SCIF: 1753 return "scif"; 1754 case PORT_SCIFA: 1755 return "scifa"; 1756 case PORT_SCIFB: 1757 return "scifb"; 1758 } 1759 1760 return NULL; 1761 } 1762 1763 static inline unsigned long sci_port_size(struct uart_port *port) 1764 { 1765 /* 1766 * Pick an arbitrary size that encapsulates all of the base 1767 * registers by default. This can be optimized later, or derived 1768 * from platform resource data at such a time that ports begin to 1769 * behave more erratically. 1770 */ 1771 return 64; 1772 } 1773 1774 static int sci_remap_port(struct uart_port *port) 1775 { 1776 unsigned long size = sci_port_size(port); 1777 1778 /* 1779 * Nothing to do if there's already an established membase. 1780 */ 1781 if (port->membase) 1782 return 0; 1783 1784 if (port->flags & UPF_IOREMAP) { 1785 port->membase = ioremap_nocache(port->mapbase, size); 1786 if (unlikely(!port->membase)) { 1787 dev_err(port->dev, "can't remap port#%d\n", port->line); 1788 return -ENXIO; 1789 } 1790 } else { 1791 /* 1792 * For the simple (and majority of) cases where we don't 1793 * need to do any remapping, just cast the cookie 1794 * directly. 1795 */ 1796 port->membase = (void __iomem *)port->mapbase; 1797 } 1798 1799 return 0; 1800 } 1801 1802 static void sci_release_port(struct uart_port *port) 1803 { 1804 if (port->flags & UPF_IOREMAP) { 1805 iounmap(port->membase); 1806 port->membase = NULL; 1807 } 1808 1809 release_mem_region(port->mapbase, sci_port_size(port)); 1810 } 1811 1812 static int sci_request_port(struct uart_port *port) 1813 { 1814 unsigned long size = sci_port_size(port); 1815 struct resource *res; 1816 int ret; 1817 1818 res = request_mem_region(port->mapbase, size, dev_name(port->dev)); 1819 if (unlikely(res == NULL)) 1820 return -EBUSY; 1821 1822 ret = sci_remap_port(port); 1823 if (unlikely(ret != 0)) { 1824 release_resource(res); 1825 return ret; 1826 } 1827 1828 return 0; 1829 } 1830 1831 static void sci_config_port(struct uart_port *port, int flags) 1832 { 1833 if (flags & UART_CONFIG_TYPE) { 1834 struct sci_port *sport = to_sci_port(port); 1835 1836 port->type = sport->cfg->type; 1837 sci_request_port(port); 1838 } 1839 } 1840 1841 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 1842 { 1843 struct sci_port *s = to_sci_port(port); 1844 1845 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) 1846 return -EINVAL; 1847 if (ser->baud_base < 2400) 1848 /* No paper tape reader for Mitch.. */ 1849 return -EINVAL; 1850 1851 return 0; 1852 } 1853 1854 static struct uart_ops sci_uart_ops = { 1855 .tx_empty = sci_tx_empty, 1856 .set_mctrl = sci_set_mctrl, 1857 .get_mctrl = sci_get_mctrl, 1858 .start_tx = sci_start_tx, 1859 .stop_tx = sci_stop_tx, 1860 .stop_rx = sci_stop_rx, 1861 .enable_ms = sci_enable_ms, 1862 .break_ctl = sci_break_ctl, 1863 .startup = sci_startup, 1864 .shutdown = sci_shutdown, 1865 .set_termios = sci_set_termios, 1866 .type = sci_type, 1867 .release_port = sci_release_port, 1868 .request_port = sci_request_port, 1869 .config_port = sci_config_port, 1870 .verify_port = sci_verify_port, 1871 #ifdef CONFIG_CONSOLE_POLL 1872 .poll_get_char = sci_poll_get_char, 1873 .poll_put_char = sci_poll_put_char, 1874 #endif 1875 }; 1876 1877 static int __devinit sci_init_single(struct platform_device *dev, 1878 struct sci_port *sci_port, 1879 unsigned int index, 1880 struct plat_sci_port *p) 1881 { 1882 struct uart_port *port = &sci_port->port; 1883 int ret; 1884 1885 port->ops = &sci_uart_ops; 1886 port->iotype = UPIO_MEM; 1887 port->line = index; 1888 1889 switch (p->type) { 1890 case PORT_SCIFB: 1891 port->fifosize = 256; 1892 break; 1893 case PORT_SCIFA: 1894 port->fifosize = 64; 1895 break; 1896 case PORT_SCIF: 1897 port->fifosize = 16; 1898 break; 1899 default: 1900 port->fifosize = 1; 1901 break; 1902 } 1903 1904 if (p->regtype == SCIx_PROBE_REGTYPE) { 1905 ret = sci_probe_regmap(p); 1906 if (unlikely(ret)) 1907 return ret; 1908 } 1909 1910 if (dev) { 1911 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 1912 if (IS_ERR(sci_port->iclk)) { 1913 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); 1914 if (IS_ERR(sci_port->iclk)) { 1915 dev_err(&dev->dev, "can't get iclk\n"); 1916 return PTR_ERR(sci_port->iclk); 1917 } 1918 } 1919 1920 /* 1921 * The function clock is optional, ignore it if we can't 1922 * find it. 1923 */ 1924 sci_port->fclk = clk_get(&dev->dev, "sci_fck"); 1925 if (IS_ERR(sci_port->fclk)) 1926 sci_port->fclk = NULL; 1927 1928 port->dev = &dev->dev; 1929 1930 pm_runtime_irq_safe(&dev->dev); 1931 pm_runtime_enable(&dev->dev); 1932 } 1933 1934 sci_port->break_timer.data = (unsigned long)sci_port; 1935 sci_port->break_timer.function = sci_break_timer; 1936 init_timer(&sci_port->break_timer); 1937 1938 /* 1939 * Establish some sensible defaults for the error detection. 1940 */ 1941 if (!p->error_mask) 1942 p->error_mask = (p->type == PORT_SCI) ? 1943 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; 1944 1945 /* 1946 * Establish sensible defaults for the overrun detection, unless 1947 * the part has explicitly disabled support for it. 1948 */ 1949 if (p->overrun_bit != SCIx_NOT_SUPPORTED) { 1950 if (p->type == PORT_SCI) 1951 p->overrun_bit = 5; 1952 else if (p->scbrr_algo_id == SCBRR_ALGO_4) 1953 p->overrun_bit = 9; 1954 else 1955 p->overrun_bit = 0; 1956 1957 /* 1958 * Make the error mask inclusive of overrun detection, if 1959 * supported. 1960 */ 1961 p->error_mask |= (1 << p->overrun_bit); 1962 } 1963 1964 sci_port->cfg = p; 1965 1966 port->mapbase = p->mapbase; 1967 port->type = p->type; 1968 port->flags = p->flags; 1969 port->regshift = p->regshift; 1970 1971 /* 1972 * The UART port needs an IRQ value, so we peg this to the RX IRQ 1973 * for the multi-IRQ ports, which is where we are primarily 1974 * concerned with the shutdown path synchronization. 1975 * 1976 * For the muxed case there's nothing more to do. 1977 */ 1978 port->irq = p->irqs[SCIx_RXI_IRQ]; 1979 port->irqflags = IRQF_DISABLED; 1980 1981 port->serial_in = sci_serial_in; 1982 port->serial_out = sci_serial_out; 1983 1984 if (p->dma_dev) 1985 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n", 1986 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx); 1987 1988 return 0; 1989 } 1990 1991 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1992 static void serial_console_putchar(struct uart_port *port, int ch) 1993 { 1994 sci_poll_put_char(port, ch); 1995 } 1996 1997 /* 1998 * Print a string to the serial port trying not to disturb 1999 * any possible real use of the port... 2000 */ 2001 static void serial_console_write(struct console *co, const char *s, 2002 unsigned count) 2003 { 2004 struct sci_port *sci_port = &sci_ports[co->index]; 2005 struct uart_port *port = &sci_port->port; 2006 unsigned short bits; 2007 2008 sci_port_enable(sci_port); 2009 2010 uart_console_write(port, s, count, serial_console_putchar); 2011 2012 /* wait until fifo is empty and last bit has been transmitted */ 2013 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2014 while ((sci_in(port, SCxSR) & bits) != bits) 2015 cpu_relax(); 2016 2017 sci_port_disable(sci_port); 2018 } 2019 2020 static int __devinit serial_console_setup(struct console *co, char *options) 2021 { 2022 struct sci_port *sci_port; 2023 struct uart_port *port; 2024 int baud = 115200; 2025 int bits = 8; 2026 int parity = 'n'; 2027 int flow = 'n'; 2028 int ret; 2029 2030 /* 2031 * Refuse to handle any bogus ports. 2032 */ 2033 if (co->index < 0 || co->index >= SCI_NPORTS) 2034 return -ENODEV; 2035 2036 sci_port = &sci_ports[co->index]; 2037 port = &sci_port->port; 2038 2039 /* 2040 * Refuse to handle uninitialized ports. 2041 */ 2042 if (!port->ops) 2043 return -ENODEV; 2044 2045 ret = sci_remap_port(port); 2046 if (unlikely(ret != 0)) 2047 return ret; 2048 2049 sci_port_enable(sci_port); 2050 2051 if (options) 2052 uart_parse_options(options, &baud, &parity, &bits, &flow); 2053 2054 sci_port_disable(sci_port); 2055 2056 return uart_set_options(port, co, baud, parity, bits, flow); 2057 } 2058 2059 static struct console serial_console = { 2060 .name = "ttySC", 2061 .device = uart_console_device, 2062 .write = serial_console_write, 2063 .setup = serial_console_setup, 2064 .flags = CON_PRINTBUFFER, 2065 .index = -1, 2066 .data = &sci_uart_driver, 2067 }; 2068 2069 static struct console early_serial_console = { 2070 .name = "early_ttySC", 2071 .write = serial_console_write, 2072 .flags = CON_PRINTBUFFER, 2073 .index = -1, 2074 }; 2075 2076 static char early_serial_buf[32]; 2077 2078 static int __devinit sci_probe_earlyprintk(struct platform_device *pdev) 2079 { 2080 struct plat_sci_port *cfg = pdev->dev.platform_data; 2081 2082 if (early_serial_console.data) 2083 return -EEXIST; 2084 2085 early_serial_console.index = pdev->id; 2086 2087 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg); 2088 2089 serial_console_setup(&early_serial_console, early_serial_buf); 2090 2091 if (!strstr(early_serial_buf, "keep")) 2092 early_serial_console.flags |= CON_BOOT; 2093 2094 register_console(&early_serial_console); 2095 return 0; 2096 } 2097 2098 #define uart_console(port) ((port)->cons->index == (port)->line) 2099 2100 static int sci_runtime_suspend(struct device *dev) 2101 { 2102 struct sci_port *sci_port = dev_get_drvdata(dev); 2103 struct uart_port *port = &sci_port->port; 2104 2105 if (uart_console(port)) { 2106 sci_port->saved_smr = sci_in(port, SCSMR); 2107 sci_port->saved_brr = sci_in(port, SCBRR); 2108 sci_port->saved_fcr = sci_in(port, SCFCR); 2109 } 2110 return 0; 2111 } 2112 2113 static int sci_runtime_resume(struct device *dev) 2114 { 2115 struct sci_port *sci_port = dev_get_drvdata(dev); 2116 struct uart_port *port = &sci_port->port; 2117 2118 if (uart_console(port)) { 2119 sci_reset(port); 2120 sci_out(port, SCSMR, sci_port->saved_smr); 2121 sci_out(port, SCBRR, sci_port->saved_brr); 2122 sci_out(port, SCFCR, sci_port->saved_fcr); 2123 sci_out(port, SCSCR, sci_port->cfg->scscr); 2124 } 2125 return 0; 2126 } 2127 2128 #define SCI_CONSOLE (&serial_console) 2129 2130 #else 2131 static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev) 2132 { 2133 return -EINVAL; 2134 } 2135 2136 #define SCI_CONSOLE NULL 2137 #define sci_runtime_suspend NULL 2138 #define sci_runtime_resume NULL 2139 2140 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ 2141 2142 static char banner[] __initdata = 2143 KERN_INFO "SuperH SCI(F) driver initialized\n"; 2144 2145 static struct uart_driver sci_uart_driver = { 2146 .owner = THIS_MODULE, 2147 .driver_name = "sci", 2148 .dev_name = "ttySC", 2149 .major = SCI_MAJOR, 2150 .minor = SCI_MINOR_START, 2151 .nr = SCI_NPORTS, 2152 .cons = SCI_CONSOLE, 2153 }; 2154 2155 static int sci_remove(struct platform_device *dev) 2156 { 2157 struct sci_port *port = platform_get_drvdata(dev); 2158 2159 cpufreq_unregister_notifier(&port->freq_transition, 2160 CPUFREQ_TRANSITION_NOTIFIER); 2161 2162 uart_remove_one_port(&sci_uart_driver, &port->port); 2163 2164 clk_put(port->iclk); 2165 clk_put(port->fclk); 2166 2167 pm_runtime_disable(&dev->dev); 2168 return 0; 2169 } 2170 2171 static int __devinit sci_probe_single(struct platform_device *dev, 2172 unsigned int index, 2173 struct plat_sci_port *p, 2174 struct sci_port *sciport) 2175 { 2176 int ret; 2177 2178 /* Sanity check */ 2179 if (unlikely(index >= SCI_NPORTS)) { 2180 dev_notice(&dev->dev, "Attempting to register port " 2181 "%d when only %d are available.\n", 2182 index+1, SCI_NPORTS); 2183 dev_notice(&dev->dev, "Consider bumping " 2184 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 2185 return 0; 2186 } 2187 2188 ret = sci_init_single(dev, sciport, index, p); 2189 if (ret) 2190 return ret; 2191 2192 return uart_add_one_port(&sci_uart_driver, &sciport->port); 2193 } 2194 2195 static int __devinit sci_probe(struct platform_device *dev) 2196 { 2197 struct plat_sci_port *p = dev->dev.platform_data; 2198 struct sci_port *sp = &sci_ports[dev->id]; 2199 int ret; 2200 2201 /* 2202 * If we've come here via earlyprintk initialization, head off to 2203 * the special early probe. We don't have sufficient device state 2204 * to make it beyond this yet. 2205 */ 2206 if (is_early_platform_device(dev)) 2207 return sci_probe_earlyprintk(dev); 2208 2209 platform_set_drvdata(dev, sp); 2210 2211 ret = sci_probe_single(dev, dev->id, p, sp); 2212 if (ret) 2213 goto err_unreg; 2214 2215 sp->freq_transition.notifier_call = sci_notifier; 2216 2217 ret = cpufreq_register_notifier(&sp->freq_transition, 2218 CPUFREQ_TRANSITION_NOTIFIER); 2219 if (unlikely(ret < 0)) 2220 goto err_unreg; 2221 2222 #ifdef CONFIG_SH_STANDARD_BIOS 2223 sh_bios_gdb_detach(); 2224 #endif 2225 2226 return 0; 2227 2228 err_unreg: 2229 sci_remove(dev); 2230 return ret; 2231 } 2232 2233 static int sci_suspend(struct device *dev) 2234 { 2235 struct sci_port *sport = dev_get_drvdata(dev); 2236 2237 if (sport) 2238 uart_suspend_port(&sci_uart_driver, &sport->port); 2239 2240 return 0; 2241 } 2242 2243 static int sci_resume(struct device *dev) 2244 { 2245 struct sci_port *sport = dev_get_drvdata(dev); 2246 2247 if (sport) 2248 uart_resume_port(&sci_uart_driver, &sport->port); 2249 2250 return 0; 2251 } 2252 2253 static const struct dev_pm_ops sci_dev_pm_ops = { 2254 .runtime_suspend = sci_runtime_suspend, 2255 .runtime_resume = sci_runtime_resume, 2256 .suspend = sci_suspend, 2257 .resume = sci_resume, 2258 }; 2259 2260 static struct platform_driver sci_driver = { 2261 .probe = sci_probe, 2262 .remove = sci_remove, 2263 .driver = { 2264 .name = "sh-sci", 2265 .owner = THIS_MODULE, 2266 .pm = &sci_dev_pm_ops, 2267 }, 2268 }; 2269 2270 static int __init sci_init(void) 2271 { 2272 int ret; 2273 2274 printk(banner); 2275 2276 ret = uart_register_driver(&sci_uart_driver); 2277 if (likely(ret == 0)) { 2278 ret = platform_driver_register(&sci_driver); 2279 if (unlikely(ret)) 2280 uart_unregister_driver(&sci_uart_driver); 2281 } 2282 2283 return ret; 2284 } 2285 2286 static void __exit sci_exit(void) 2287 { 2288 platform_driver_unregister(&sci_driver); 2289 uart_unregister_driver(&sci_uart_driver); 2290 } 2291 2292 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2293 early_platform_init_buffer("earlyprintk", &sci_driver, 2294 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 2295 #endif 2296 module_init(sci_init); 2297 module_exit(sci_exit); 2298 2299 MODULE_LICENSE("GPL"); 2300 MODULE_ALIAS("platform:sh-sci"); 2301 MODULE_AUTHOR("Paul Mundt"); 2302 MODULE_DESCRIPTION("SuperH SCI(F) serial driver"); 2303