1 /* 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 3 * 4 * Copyright (C) 2002 - 2011 Paul Mundt 5 * Copyright (C) 2015 Glider bvba 6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 7 * 8 * based off of the old drivers/char/sh-sci.c by: 9 * 10 * Copyright (C) 1999, 2000 Niibe Yutaka 11 * Copyright (C) 2000 Sugioka Toshinobu 12 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 13 * Modified to support SecureEdge. David McCullough (2002) 14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 15 * Removed SH7300 support (Jul 2007). 16 * 17 * This file is subject to the terms and conditions of the GNU General Public 18 * License. See the file "COPYING" in the main directory of this archive 19 * for more details. 20 */ 21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 22 #define SUPPORT_SYSRQ 23 #endif 24 25 #undef DEBUG 26 27 #include <linux/clk.h> 28 #include <linux/console.h> 29 #include <linux/ctype.h> 30 #include <linux/cpufreq.h> 31 #include <linux/delay.h> 32 #include <linux/dmaengine.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/err.h> 35 #include <linux/errno.h> 36 #include <linux/init.h> 37 #include <linux/interrupt.h> 38 #include <linux/ioport.h> 39 #include <linux/major.h> 40 #include <linux/module.h> 41 #include <linux/mm.h> 42 #include <linux/of.h> 43 #include <linux/platform_device.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/scatterlist.h> 46 #include <linux/serial.h> 47 #include <linux/serial_sci.h> 48 #include <linux/sh_dma.h> 49 #include <linux/slab.h> 50 #include <linux/string.h> 51 #include <linux/sysrq.h> 52 #include <linux/timer.h> 53 #include <linux/tty.h> 54 #include <linux/tty_flip.h> 55 56 #ifdef CONFIG_SUPERH 57 #include <asm/sh_bios.h> 58 #endif 59 60 #include "serial_mctrl_gpio.h" 61 #include "sh-sci.h" 62 63 /* Offsets into the sci_port->irqs array */ 64 enum { 65 SCIx_ERI_IRQ, 66 SCIx_RXI_IRQ, 67 SCIx_TXI_IRQ, 68 SCIx_BRI_IRQ, 69 SCIx_NR_IRQS, 70 71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 72 }; 73 74 #define SCIx_IRQ_IS_MUXED(port) \ 75 ((port)->irqs[SCIx_ERI_IRQ] == \ 76 (port)->irqs[SCIx_RXI_IRQ]) || \ 77 ((port)->irqs[SCIx_ERI_IRQ] && \ 78 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 79 80 enum SCI_CLKS { 81 SCI_FCK, /* Functional Clock */ 82 SCI_SCK, /* Optional External Clock */ 83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 85 SCI_NUM_CLKS 86 }; 87 88 /* Bit x set means sampling rate x + 1 is supported */ 89 #define SCI_SR(x) BIT((x) - 1) 90 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 91 92 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 94 SCI_SR(19) | SCI_SR(27) 95 96 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 97 #define max_sr(_port) fls((_port)->sampling_rate_mask) 98 99 /* Iterate over all supported sampling rates, from high to low */ 100 #define for_each_sr(_sr, _port) \ 101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 102 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 103 104 struct plat_sci_reg { 105 u8 offset, size; 106 }; 107 108 struct sci_port_params { 109 const struct plat_sci_reg regs[SCIx_NR_REGS]; 110 unsigned int fifosize; 111 unsigned int overrun_reg; 112 unsigned int overrun_mask; 113 unsigned int sampling_rate_mask; 114 unsigned int error_mask; 115 unsigned int error_clear; 116 }; 117 118 struct sci_port { 119 struct uart_port port; 120 121 /* Platform configuration */ 122 const struct sci_port_params *params; 123 const struct plat_sci_port *cfg; 124 unsigned int sampling_rate_mask; 125 resource_size_t reg_size; 126 struct mctrl_gpios *gpios; 127 128 /* Clocks */ 129 struct clk *clks[SCI_NUM_CLKS]; 130 unsigned long clk_rates[SCI_NUM_CLKS]; 131 132 int irqs[SCIx_NR_IRQS]; 133 char *irqstr[SCIx_NR_IRQS]; 134 135 struct dma_chan *chan_tx; 136 struct dma_chan *chan_rx; 137 138 #ifdef CONFIG_SERIAL_SH_SCI_DMA 139 dma_cookie_t cookie_tx; 140 dma_cookie_t cookie_rx[2]; 141 dma_cookie_t active_rx; 142 dma_addr_t tx_dma_addr; 143 unsigned int tx_dma_len; 144 struct scatterlist sg_rx[2]; 145 void *rx_buf[2]; 146 size_t buf_len_rx; 147 struct work_struct work_tx; 148 struct timer_list rx_timer; 149 unsigned int rx_timeout; 150 #endif 151 152 bool has_rtscts; 153 bool autorts; 154 }; 155 156 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 157 158 static struct sci_port sci_ports[SCI_NPORTS]; 159 static struct uart_driver sci_uart_driver; 160 161 static inline struct sci_port * 162 to_sci_port(struct uart_port *uart) 163 { 164 return container_of(uart, struct sci_port, port); 165 } 166 167 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 168 /* 169 * Common SCI definitions, dependent on the port's regshift 170 * value. 171 */ 172 [SCIx_SCI_REGTYPE] = { 173 .regs = { 174 [SCSMR] = { 0x00, 8 }, 175 [SCBRR] = { 0x01, 8 }, 176 [SCSCR] = { 0x02, 8 }, 177 [SCxTDR] = { 0x03, 8 }, 178 [SCxSR] = { 0x04, 8 }, 179 [SCxRDR] = { 0x05, 8 }, 180 }, 181 .fifosize = 1, 182 .overrun_reg = SCxSR, 183 .overrun_mask = SCI_ORER, 184 .sampling_rate_mask = SCI_SR(32), 185 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 186 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 187 }, 188 189 /* 190 * Common definitions for legacy IrDA ports. 191 */ 192 [SCIx_IRDA_REGTYPE] = { 193 .regs = { 194 [SCSMR] = { 0x00, 8 }, 195 [SCBRR] = { 0x02, 8 }, 196 [SCSCR] = { 0x04, 8 }, 197 [SCxTDR] = { 0x06, 8 }, 198 [SCxSR] = { 0x08, 16 }, 199 [SCxRDR] = { 0x0a, 8 }, 200 [SCFCR] = { 0x0c, 8 }, 201 [SCFDR] = { 0x0e, 16 }, 202 }, 203 .fifosize = 1, 204 .overrun_reg = SCxSR, 205 .overrun_mask = SCI_ORER, 206 .sampling_rate_mask = SCI_SR(32), 207 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 208 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 209 }, 210 211 /* 212 * Common SCIFA definitions. 213 */ 214 [SCIx_SCIFA_REGTYPE] = { 215 .regs = { 216 [SCSMR] = { 0x00, 16 }, 217 [SCBRR] = { 0x04, 8 }, 218 [SCSCR] = { 0x08, 16 }, 219 [SCxTDR] = { 0x20, 8 }, 220 [SCxSR] = { 0x14, 16 }, 221 [SCxRDR] = { 0x24, 8 }, 222 [SCFCR] = { 0x18, 16 }, 223 [SCFDR] = { 0x1c, 16 }, 224 [SCPCR] = { 0x30, 16 }, 225 [SCPDR] = { 0x34, 16 }, 226 }, 227 .fifosize = 64, 228 .overrun_reg = SCxSR, 229 .overrun_mask = SCIFA_ORER, 230 .sampling_rate_mask = SCI_SR_SCIFAB, 231 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 232 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 233 }, 234 235 /* 236 * Common SCIFB definitions. 237 */ 238 [SCIx_SCIFB_REGTYPE] = { 239 .regs = { 240 [SCSMR] = { 0x00, 16 }, 241 [SCBRR] = { 0x04, 8 }, 242 [SCSCR] = { 0x08, 16 }, 243 [SCxTDR] = { 0x40, 8 }, 244 [SCxSR] = { 0x14, 16 }, 245 [SCxRDR] = { 0x60, 8 }, 246 [SCFCR] = { 0x18, 16 }, 247 [SCTFDR] = { 0x38, 16 }, 248 [SCRFDR] = { 0x3c, 16 }, 249 [SCPCR] = { 0x30, 16 }, 250 [SCPDR] = { 0x34, 16 }, 251 }, 252 .fifosize = 256, 253 .overrun_reg = SCxSR, 254 .overrun_mask = SCIFA_ORER, 255 .sampling_rate_mask = SCI_SR_SCIFAB, 256 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 257 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 258 }, 259 260 /* 261 * Common SH-2(A) SCIF definitions for ports with FIFO data 262 * count registers. 263 */ 264 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 265 .regs = { 266 [SCSMR] = { 0x00, 16 }, 267 [SCBRR] = { 0x04, 8 }, 268 [SCSCR] = { 0x08, 16 }, 269 [SCxTDR] = { 0x0c, 8 }, 270 [SCxSR] = { 0x10, 16 }, 271 [SCxRDR] = { 0x14, 8 }, 272 [SCFCR] = { 0x18, 16 }, 273 [SCFDR] = { 0x1c, 16 }, 274 [SCSPTR] = { 0x20, 16 }, 275 [SCLSR] = { 0x24, 16 }, 276 }, 277 .fifosize = 16, 278 .overrun_reg = SCLSR, 279 .overrun_mask = SCLSR_ORER, 280 .sampling_rate_mask = SCI_SR(32), 281 .error_mask = SCIF_DEFAULT_ERROR_MASK, 282 .error_clear = SCIF_ERROR_CLEAR, 283 }, 284 285 /* 286 * Common SH-3 SCIF definitions. 287 */ 288 [SCIx_SH3_SCIF_REGTYPE] = { 289 .regs = { 290 [SCSMR] = { 0x00, 8 }, 291 [SCBRR] = { 0x02, 8 }, 292 [SCSCR] = { 0x04, 8 }, 293 [SCxTDR] = { 0x06, 8 }, 294 [SCxSR] = { 0x08, 16 }, 295 [SCxRDR] = { 0x0a, 8 }, 296 [SCFCR] = { 0x0c, 8 }, 297 [SCFDR] = { 0x0e, 16 }, 298 }, 299 .fifosize = 16, 300 .overrun_reg = SCLSR, 301 .overrun_mask = SCLSR_ORER, 302 .sampling_rate_mask = SCI_SR(32), 303 .error_mask = SCIF_DEFAULT_ERROR_MASK, 304 .error_clear = SCIF_ERROR_CLEAR, 305 }, 306 307 /* 308 * Common SH-4(A) SCIF(B) definitions. 309 */ 310 [SCIx_SH4_SCIF_REGTYPE] = { 311 .regs = { 312 [SCSMR] = { 0x00, 16 }, 313 [SCBRR] = { 0x04, 8 }, 314 [SCSCR] = { 0x08, 16 }, 315 [SCxTDR] = { 0x0c, 8 }, 316 [SCxSR] = { 0x10, 16 }, 317 [SCxRDR] = { 0x14, 8 }, 318 [SCFCR] = { 0x18, 16 }, 319 [SCFDR] = { 0x1c, 16 }, 320 [SCSPTR] = { 0x20, 16 }, 321 [SCLSR] = { 0x24, 16 }, 322 }, 323 .fifosize = 16, 324 .overrun_reg = SCLSR, 325 .overrun_mask = SCLSR_ORER, 326 .sampling_rate_mask = SCI_SR(32), 327 .error_mask = SCIF_DEFAULT_ERROR_MASK, 328 .error_clear = SCIF_ERROR_CLEAR, 329 }, 330 331 /* 332 * Common SCIF definitions for ports with a Baud Rate Generator for 333 * External Clock (BRG). 334 */ 335 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 336 .regs = { 337 [SCSMR] = { 0x00, 16 }, 338 [SCBRR] = { 0x04, 8 }, 339 [SCSCR] = { 0x08, 16 }, 340 [SCxTDR] = { 0x0c, 8 }, 341 [SCxSR] = { 0x10, 16 }, 342 [SCxRDR] = { 0x14, 8 }, 343 [SCFCR] = { 0x18, 16 }, 344 [SCFDR] = { 0x1c, 16 }, 345 [SCSPTR] = { 0x20, 16 }, 346 [SCLSR] = { 0x24, 16 }, 347 [SCDL] = { 0x30, 16 }, 348 [SCCKS] = { 0x34, 16 }, 349 }, 350 .fifosize = 16, 351 .overrun_reg = SCLSR, 352 .overrun_mask = SCLSR_ORER, 353 .sampling_rate_mask = SCI_SR(32), 354 .error_mask = SCIF_DEFAULT_ERROR_MASK, 355 .error_clear = SCIF_ERROR_CLEAR, 356 }, 357 358 /* 359 * Common HSCIF definitions. 360 */ 361 [SCIx_HSCIF_REGTYPE] = { 362 .regs = { 363 [SCSMR] = { 0x00, 16 }, 364 [SCBRR] = { 0x04, 8 }, 365 [SCSCR] = { 0x08, 16 }, 366 [SCxTDR] = { 0x0c, 8 }, 367 [SCxSR] = { 0x10, 16 }, 368 [SCxRDR] = { 0x14, 8 }, 369 [SCFCR] = { 0x18, 16 }, 370 [SCFDR] = { 0x1c, 16 }, 371 [SCSPTR] = { 0x20, 16 }, 372 [SCLSR] = { 0x24, 16 }, 373 [HSSRR] = { 0x40, 16 }, 374 [SCDL] = { 0x30, 16 }, 375 [SCCKS] = { 0x34, 16 }, 376 }, 377 .fifosize = 128, 378 .overrun_reg = SCLSR, 379 .overrun_mask = SCLSR_ORER, 380 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 381 .error_mask = SCIF_DEFAULT_ERROR_MASK, 382 .error_clear = SCIF_ERROR_CLEAR, 383 }, 384 385 /* 386 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 387 * register. 388 */ 389 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 390 .regs = { 391 [SCSMR] = { 0x00, 16 }, 392 [SCBRR] = { 0x04, 8 }, 393 [SCSCR] = { 0x08, 16 }, 394 [SCxTDR] = { 0x0c, 8 }, 395 [SCxSR] = { 0x10, 16 }, 396 [SCxRDR] = { 0x14, 8 }, 397 [SCFCR] = { 0x18, 16 }, 398 [SCFDR] = { 0x1c, 16 }, 399 [SCLSR] = { 0x24, 16 }, 400 }, 401 .fifosize = 16, 402 .overrun_reg = SCLSR, 403 .overrun_mask = SCLSR_ORER, 404 .sampling_rate_mask = SCI_SR(32), 405 .error_mask = SCIF_DEFAULT_ERROR_MASK, 406 .error_clear = SCIF_ERROR_CLEAR, 407 }, 408 409 /* 410 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 411 * count registers. 412 */ 413 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 414 .regs = { 415 [SCSMR] = { 0x00, 16 }, 416 [SCBRR] = { 0x04, 8 }, 417 [SCSCR] = { 0x08, 16 }, 418 [SCxTDR] = { 0x0c, 8 }, 419 [SCxSR] = { 0x10, 16 }, 420 [SCxRDR] = { 0x14, 8 }, 421 [SCFCR] = { 0x18, 16 }, 422 [SCFDR] = { 0x1c, 16 }, 423 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 424 [SCRFDR] = { 0x20, 16 }, 425 [SCSPTR] = { 0x24, 16 }, 426 [SCLSR] = { 0x28, 16 }, 427 }, 428 .fifosize = 16, 429 .overrun_reg = SCLSR, 430 .overrun_mask = SCLSR_ORER, 431 .sampling_rate_mask = SCI_SR(32), 432 .error_mask = SCIF_DEFAULT_ERROR_MASK, 433 .error_clear = SCIF_ERROR_CLEAR, 434 }, 435 436 /* 437 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 438 * registers. 439 */ 440 [SCIx_SH7705_SCIF_REGTYPE] = { 441 .regs = { 442 [SCSMR] = { 0x00, 16 }, 443 [SCBRR] = { 0x04, 8 }, 444 [SCSCR] = { 0x08, 16 }, 445 [SCxTDR] = { 0x20, 8 }, 446 [SCxSR] = { 0x14, 16 }, 447 [SCxRDR] = { 0x24, 8 }, 448 [SCFCR] = { 0x18, 16 }, 449 [SCFDR] = { 0x1c, 16 }, 450 }, 451 .fifosize = 16, 452 .overrun_reg = SCxSR, 453 .overrun_mask = SCIFA_ORER, 454 .sampling_rate_mask = SCI_SR(16), 455 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 456 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 457 }, 458 }; 459 460 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 461 462 /* 463 * The "offset" here is rather misleading, in that it refers to an enum 464 * value relative to the port mapping rather than the fixed offset 465 * itself, which needs to be manually retrieved from the platform's 466 * register map for the given port. 467 */ 468 static unsigned int sci_serial_in(struct uart_port *p, int offset) 469 { 470 const struct plat_sci_reg *reg = sci_getreg(p, offset); 471 472 if (reg->size == 8) 473 return ioread8(p->membase + (reg->offset << p->regshift)); 474 else if (reg->size == 16) 475 return ioread16(p->membase + (reg->offset << p->regshift)); 476 else 477 WARN(1, "Invalid register access\n"); 478 479 return 0; 480 } 481 482 static void sci_serial_out(struct uart_port *p, int offset, int value) 483 { 484 const struct plat_sci_reg *reg = sci_getreg(p, offset); 485 486 if (reg->size == 8) 487 iowrite8(value, p->membase + (reg->offset << p->regshift)); 488 else if (reg->size == 16) 489 iowrite16(value, p->membase + (reg->offset << p->regshift)); 490 else 491 WARN(1, "Invalid register access\n"); 492 } 493 494 static void sci_port_enable(struct sci_port *sci_port) 495 { 496 unsigned int i; 497 498 if (!sci_port->port.dev) 499 return; 500 501 pm_runtime_get_sync(sci_port->port.dev); 502 503 for (i = 0; i < SCI_NUM_CLKS; i++) { 504 clk_prepare_enable(sci_port->clks[i]); 505 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 506 } 507 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 508 } 509 510 static void sci_port_disable(struct sci_port *sci_port) 511 { 512 unsigned int i; 513 514 if (!sci_port->port.dev) 515 return; 516 517 for (i = SCI_NUM_CLKS; i-- > 0; ) 518 clk_disable_unprepare(sci_port->clks[i]); 519 520 pm_runtime_put_sync(sci_port->port.dev); 521 } 522 523 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 524 { 525 /* 526 * Not all ports (such as SCIFA) will support REIE. Rather than 527 * special-casing the port type, we check the port initialization 528 * IRQ enable mask to see whether the IRQ is desired at all. If 529 * it's unset, it's logically inferred that there's no point in 530 * testing for it. 531 */ 532 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 533 } 534 535 static void sci_start_tx(struct uart_port *port) 536 { 537 struct sci_port *s = to_sci_port(port); 538 unsigned short ctrl; 539 540 #ifdef CONFIG_SERIAL_SH_SCI_DMA 541 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 542 u16 new, scr = serial_port_in(port, SCSCR); 543 if (s->chan_tx) 544 new = scr | SCSCR_TDRQE; 545 else 546 new = scr & ~SCSCR_TDRQE; 547 if (new != scr) 548 serial_port_out(port, SCSCR, new); 549 } 550 551 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 552 dma_submit_error(s->cookie_tx)) { 553 s->cookie_tx = 0; 554 schedule_work(&s->work_tx); 555 } 556 #endif 557 558 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 559 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 560 ctrl = serial_port_in(port, SCSCR); 561 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 562 } 563 } 564 565 static void sci_stop_tx(struct uart_port *port) 566 { 567 unsigned short ctrl; 568 569 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 570 ctrl = serial_port_in(port, SCSCR); 571 572 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 573 ctrl &= ~SCSCR_TDRQE; 574 575 ctrl &= ~SCSCR_TIE; 576 577 serial_port_out(port, SCSCR, ctrl); 578 } 579 580 static void sci_start_rx(struct uart_port *port) 581 { 582 unsigned short ctrl; 583 584 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 585 586 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 587 ctrl &= ~SCSCR_RDRQE; 588 589 serial_port_out(port, SCSCR, ctrl); 590 } 591 592 static void sci_stop_rx(struct uart_port *port) 593 { 594 unsigned short ctrl; 595 596 ctrl = serial_port_in(port, SCSCR); 597 598 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 599 ctrl &= ~SCSCR_RDRQE; 600 601 ctrl &= ~port_rx_irq_mask(port); 602 603 serial_port_out(port, SCSCR, ctrl); 604 } 605 606 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 607 { 608 if (port->type == PORT_SCI) { 609 /* Just store the mask */ 610 serial_port_out(port, SCxSR, mask); 611 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 612 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 613 /* Only clear the status bits we want to clear */ 614 serial_port_out(port, SCxSR, 615 serial_port_in(port, SCxSR) & mask); 616 } else { 617 /* Store the mask, clear parity/framing errors */ 618 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 619 } 620 } 621 622 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 623 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 624 625 #ifdef CONFIG_CONSOLE_POLL 626 static int sci_poll_get_char(struct uart_port *port) 627 { 628 unsigned short status; 629 int c; 630 631 do { 632 status = serial_port_in(port, SCxSR); 633 if (status & SCxSR_ERRORS(port)) { 634 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 635 continue; 636 } 637 break; 638 } while (1); 639 640 if (!(status & SCxSR_RDxF(port))) 641 return NO_POLL_CHAR; 642 643 c = serial_port_in(port, SCxRDR); 644 645 /* Dummy read */ 646 serial_port_in(port, SCxSR); 647 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 648 649 return c; 650 } 651 #endif 652 653 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 654 { 655 unsigned short status; 656 657 do { 658 status = serial_port_in(port, SCxSR); 659 } while (!(status & SCxSR_TDxE(port))); 660 661 serial_port_out(port, SCxTDR, c); 662 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 663 } 664 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 665 CONFIG_SERIAL_SH_SCI_EARLYCON */ 666 667 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 668 { 669 struct sci_port *s = to_sci_port(port); 670 671 /* 672 * Use port-specific handler if provided. 673 */ 674 if (s->cfg->ops && s->cfg->ops->init_pins) { 675 s->cfg->ops->init_pins(port, cflag); 676 return; 677 } 678 679 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 680 u16 ctrl = serial_port_in(port, SCPCR); 681 682 /* Enable RXD and TXD pin functions */ 683 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 684 if (to_sci_port(port)->has_rtscts) { 685 /* RTS# is output, driven 1 */ 686 ctrl |= SCPCR_RTSC; 687 serial_port_out(port, SCPDR, 688 serial_port_in(port, SCPDR) | SCPDR_RTSD); 689 /* Enable CTS# pin function */ 690 ctrl &= ~SCPCR_CTSC; 691 } 692 serial_port_out(port, SCPCR, ctrl); 693 } else if (sci_getreg(port, SCSPTR)->size) { 694 u16 status = serial_port_in(port, SCSPTR); 695 696 /* RTS# is output, driven 1 */ 697 status |= SCSPTR_RTSIO | SCSPTR_RTSDT; 698 /* CTS# and SCK are inputs */ 699 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 700 serial_port_out(port, SCSPTR, status); 701 } 702 } 703 704 static int sci_txfill(struct uart_port *port) 705 { 706 struct sci_port *s = to_sci_port(port); 707 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 708 const struct plat_sci_reg *reg; 709 710 reg = sci_getreg(port, SCTFDR); 711 if (reg->size) 712 return serial_port_in(port, SCTFDR) & fifo_mask; 713 714 reg = sci_getreg(port, SCFDR); 715 if (reg->size) 716 return serial_port_in(port, SCFDR) >> 8; 717 718 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 719 } 720 721 static int sci_txroom(struct uart_port *port) 722 { 723 return port->fifosize - sci_txfill(port); 724 } 725 726 static int sci_rxfill(struct uart_port *port) 727 { 728 struct sci_port *s = to_sci_port(port); 729 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 730 const struct plat_sci_reg *reg; 731 732 reg = sci_getreg(port, SCRFDR); 733 if (reg->size) 734 return serial_port_in(port, SCRFDR) & fifo_mask; 735 736 reg = sci_getreg(port, SCFDR); 737 if (reg->size) 738 return serial_port_in(port, SCFDR) & fifo_mask; 739 740 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 741 } 742 743 /* ********************************************************************** * 744 * the interrupt related routines * 745 * ********************************************************************** */ 746 747 static void sci_transmit_chars(struct uart_port *port) 748 { 749 struct circ_buf *xmit = &port->state->xmit; 750 unsigned int stopped = uart_tx_stopped(port); 751 unsigned short status; 752 unsigned short ctrl; 753 int count; 754 755 status = serial_port_in(port, SCxSR); 756 if (!(status & SCxSR_TDxE(port))) { 757 ctrl = serial_port_in(port, SCSCR); 758 if (uart_circ_empty(xmit)) 759 ctrl &= ~SCSCR_TIE; 760 else 761 ctrl |= SCSCR_TIE; 762 serial_port_out(port, SCSCR, ctrl); 763 return; 764 } 765 766 count = sci_txroom(port); 767 768 do { 769 unsigned char c; 770 771 if (port->x_char) { 772 c = port->x_char; 773 port->x_char = 0; 774 } else if (!uart_circ_empty(xmit) && !stopped) { 775 c = xmit->buf[xmit->tail]; 776 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 777 } else { 778 break; 779 } 780 781 serial_port_out(port, SCxTDR, c); 782 783 port->icount.tx++; 784 } while (--count > 0); 785 786 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 787 788 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 789 uart_write_wakeup(port); 790 if (uart_circ_empty(xmit)) { 791 sci_stop_tx(port); 792 } else { 793 ctrl = serial_port_in(port, SCSCR); 794 795 if (port->type != PORT_SCI) { 796 serial_port_in(port, SCxSR); /* Dummy read */ 797 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 798 } 799 800 ctrl |= SCSCR_TIE; 801 serial_port_out(port, SCSCR, ctrl); 802 } 803 } 804 805 /* On SH3, SCIF may read end-of-break as a space->mark char */ 806 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 807 808 static void sci_receive_chars(struct uart_port *port) 809 { 810 struct tty_port *tport = &port->state->port; 811 int i, count, copied = 0; 812 unsigned short status; 813 unsigned char flag; 814 815 status = serial_port_in(port, SCxSR); 816 if (!(status & SCxSR_RDxF(port))) 817 return; 818 819 while (1) { 820 /* Don't copy more bytes than there is room for in the buffer */ 821 count = tty_buffer_request_room(tport, sci_rxfill(port)); 822 823 /* If for any reason we can't copy more data, we're done! */ 824 if (count == 0) 825 break; 826 827 if (port->type == PORT_SCI) { 828 char c = serial_port_in(port, SCxRDR); 829 if (uart_handle_sysrq_char(port, c)) 830 count = 0; 831 else 832 tty_insert_flip_char(tport, c, TTY_NORMAL); 833 } else { 834 for (i = 0; i < count; i++) { 835 char c = serial_port_in(port, SCxRDR); 836 837 status = serial_port_in(port, SCxSR); 838 if (uart_handle_sysrq_char(port, c)) { 839 count--; i--; 840 continue; 841 } 842 843 /* Store data and status */ 844 if (status & SCxSR_FER(port)) { 845 flag = TTY_FRAME; 846 port->icount.frame++; 847 dev_notice(port->dev, "frame error\n"); 848 } else if (status & SCxSR_PER(port)) { 849 flag = TTY_PARITY; 850 port->icount.parity++; 851 dev_notice(port->dev, "parity error\n"); 852 } else 853 flag = TTY_NORMAL; 854 855 tty_insert_flip_char(tport, c, flag); 856 } 857 } 858 859 serial_port_in(port, SCxSR); /* dummy read */ 860 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 861 862 copied += count; 863 port->icount.rx += count; 864 } 865 866 if (copied) { 867 /* Tell the rest of the system the news. New characters! */ 868 tty_flip_buffer_push(tport); 869 } else { 870 serial_port_in(port, SCxSR); /* dummy read */ 871 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 872 } 873 } 874 875 static int sci_handle_errors(struct uart_port *port) 876 { 877 int copied = 0; 878 unsigned short status = serial_port_in(port, SCxSR); 879 struct tty_port *tport = &port->state->port; 880 struct sci_port *s = to_sci_port(port); 881 882 /* Handle overruns */ 883 if (status & s->params->overrun_mask) { 884 port->icount.overrun++; 885 886 /* overrun error */ 887 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 888 copied++; 889 890 dev_notice(port->dev, "overrun error\n"); 891 } 892 893 if (status & SCxSR_FER(port)) { 894 /* frame error */ 895 port->icount.frame++; 896 897 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 898 copied++; 899 900 dev_notice(port->dev, "frame error\n"); 901 } 902 903 if (status & SCxSR_PER(port)) { 904 /* parity error */ 905 port->icount.parity++; 906 907 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 908 copied++; 909 910 dev_notice(port->dev, "parity error\n"); 911 } 912 913 if (copied) 914 tty_flip_buffer_push(tport); 915 916 return copied; 917 } 918 919 static int sci_handle_fifo_overrun(struct uart_port *port) 920 { 921 struct tty_port *tport = &port->state->port; 922 struct sci_port *s = to_sci_port(port); 923 const struct plat_sci_reg *reg; 924 int copied = 0; 925 u16 status; 926 927 reg = sci_getreg(port, s->params->overrun_reg); 928 if (!reg->size) 929 return 0; 930 931 status = serial_port_in(port, s->params->overrun_reg); 932 if (status & s->params->overrun_mask) { 933 status &= ~s->params->overrun_mask; 934 serial_port_out(port, s->params->overrun_reg, status); 935 936 port->icount.overrun++; 937 938 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 939 tty_flip_buffer_push(tport); 940 941 dev_dbg(port->dev, "overrun error\n"); 942 copied++; 943 } 944 945 return copied; 946 } 947 948 static int sci_handle_breaks(struct uart_port *port) 949 { 950 int copied = 0; 951 unsigned short status = serial_port_in(port, SCxSR); 952 struct tty_port *tport = &port->state->port; 953 954 if (uart_handle_break(port)) 955 return 0; 956 957 if (status & SCxSR_BRK(port)) { 958 port->icount.brk++; 959 960 /* Notify of BREAK */ 961 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 962 copied++; 963 964 dev_dbg(port->dev, "BREAK detected\n"); 965 } 966 967 if (copied) 968 tty_flip_buffer_push(tport); 969 970 copied += sci_handle_fifo_overrun(port); 971 972 return copied; 973 } 974 975 #ifdef CONFIG_SERIAL_SH_SCI_DMA 976 static void sci_dma_tx_complete(void *arg) 977 { 978 struct sci_port *s = arg; 979 struct uart_port *port = &s->port; 980 struct circ_buf *xmit = &port->state->xmit; 981 unsigned long flags; 982 983 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 984 985 spin_lock_irqsave(&port->lock, flags); 986 987 xmit->tail += s->tx_dma_len; 988 xmit->tail &= UART_XMIT_SIZE - 1; 989 990 port->icount.tx += s->tx_dma_len; 991 992 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 993 uart_write_wakeup(port); 994 995 if (!uart_circ_empty(xmit)) { 996 s->cookie_tx = 0; 997 schedule_work(&s->work_tx); 998 } else { 999 s->cookie_tx = -EINVAL; 1000 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1001 u16 ctrl = serial_port_in(port, SCSCR); 1002 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1003 } 1004 } 1005 1006 spin_unlock_irqrestore(&port->lock, flags); 1007 } 1008 1009 /* Locking: called with port lock held */ 1010 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1011 { 1012 struct uart_port *port = &s->port; 1013 struct tty_port *tport = &port->state->port; 1014 int copied; 1015 1016 copied = tty_insert_flip_string(tport, buf, count); 1017 if (copied < count) 1018 port->icount.buf_overrun++; 1019 1020 port->icount.rx += copied; 1021 1022 return copied; 1023 } 1024 1025 static int sci_dma_rx_find_active(struct sci_port *s) 1026 { 1027 unsigned int i; 1028 1029 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1030 if (s->active_rx == s->cookie_rx[i]) 1031 return i; 1032 1033 return -1; 1034 } 1035 1036 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) 1037 { 1038 struct dma_chan *chan = s->chan_rx; 1039 struct uart_port *port = &s->port; 1040 unsigned long flags; 1041 1042 spin_lock_irqsave(&port->lock, flags); 1043 s->chan_rx = NULL; 1044 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; 1045 spin_unlock_irqrestore(&port->lock, flags); 1046 dmaengine_terminate_all(chan); 1047 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1048 sg_dma_address(&s->sg_rx[0])); 1049 dma_release_channel(chan); 1050 if (enable_pio) 1051 sci_start_rx(port); 1052 } 1053 1054 static void sci_dma_rx_complete(void *arg) 1055 { 1056 struct sci_port *s = arg; 1057 struct dma_chan *chan = s->chan_rx; 1058 struct uart_port *port = &s->port; 1059 struct dma_async_tx_descriptor *desc; 1060 unsigned long flags; 1061 int active, count = 0; 1062 1063 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1064 s->active_rx); 1065 1066 spin_lock_irqsave(&port->lock, flags); 1067 1068 active = sci_dma_rx_find_active(s); 1069 if (active >= 0) 1070 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1071 1072 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1073 1074 if (count) 1075 tty_flip_buffer_push(&port->state->port); 1076 1077 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1078 DMA_DEV_TO_MEM, 1079 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1080 if (!desc) 1081 goto fail; 1082 1083 desc->callback = sci_dma_rx_complete; 1084 desc->callback_param = s; 1085 s->cookie_rx[active] = dmaengine_submit(desc); 1086 if (dma_submit_error(s->cookie_rx[active])) 1087 goto fail; 1088 1089 s->active_rx = s->cookie_rx[!active]; 1090 1091 dma_async_issue_pending(chan); 1092 1093 spin_unlock_irqrestore(&port->lock, flags); 1094 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1095 __func__, s->cookie_rx[active], active, s->active_rx); 1096 return; 1097 1098 fail: 1099 spin_unlock_irqrestore(&port->lock, flags); 1100 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1101 sci_rx_dma_release(s, true); 1102 } 1103 1104 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) 1105 { 1106 struct dma_chan *chan = s->chan_tx; 1107 struct uart_port *port = &s->port; 1108 unsigned long flags; 1109 1110 spin_lock_irqsave(&port->lock, flags); 1111 s->chan_tx = NULL; 1112 s->cookie_tx = -EINVAL; 1113 spin_unlock_irqrestore(&port->lock, flags); 1114 dmaengine_terminate_all(chan); 1115 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1116 DMA_TO_DEVICE); 1117 dma_release_channel(chan); 1118 if (enable_pio) 1119 sci_start_tx(port); 1120 } 1121 1122 static void sci_submit_rx(struct sci_port *s) 1123 { 1124 struct dma_chan *chan = s->chan_rx; 1125 int i; 1126 1127 for (i = 0; i < 2; i++) { 1128 struct scatterlist *sg = &s->sg_rx[i]; 1129 struct dma_async_tx_descriptor *desc; 1130 1131 desc = dmaengine_prep_slave_sg(chan, 1132 sg, 1, DMA_DEV_TO_MEM, 1133 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1134 if (!desc) 1135 goto fail; 1136 1137 desc->callback = sci_dma_rx_complete; 1138 desc->callback_param = s; 1139 s->cookie_rx[i] = dmaengine_submit(desc); 1140 if (dma_submit_error(s->cookie_rx[i])) 1141 goto fail; 1142 1143 } 1144 1145 s->active_rx = s->cookie_rx[0]; 1146 1147 dma_async_issue_pending(chan); 1148 return; 1149 1150 fail: 1151 if (i) 1152 dmaengine_terminate_all(chan); 1153 for (i = 0; i < 2; i++) 1154 s->cookie_rx[i] = -EINVAL; 1155 s->active_rx = -EINVAL; 1156 sci_rx_dma_release(s, true); 1157 } 1158 1159 static void work_fn_tx(struct work_struct *work) 1160 { 1161 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1162 struct dma_async_tx_descriptor *desc; 1163 struct dma_chan *chan = s->chan_tx; 1164 struct uart_port *port = &s->port; 1165 struct circ_buf *xmit = &port->state->xmit; 1166 dma_addr_t buf; 1167 1168 /* 1169 * DMA is idle now. 1170 * Port xmit buffer is already mapped, and it is one page... Just adjust 1171 * offsets and lengths. Since it is a circular buffer, we have to 1172 * transmit till the end, and then the rest. Take the port lock to get a 1173 * consistent xmit buffer state. 1174 */ 1175 spin_lock_irq(&port->lock); 1176 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1)); 1177 s->tx_dma_len = min_t(unsigned int, 1178 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1179 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1180 spin_unlock_irq(&port->lock); 1181 1182 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1183 DMA_MEM_TO_DEV, 1184 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1185 if (!desc) { 1186 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1187 /* switch to PIO */ 1188 sci_tx_dma_release(s, true); 1189 return; 1190 } 1191 1192 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1193 DMA_TO_DEVICE); 1194 1195 spin_lock_irq(&port->lock); 1196 desc->callback = sci_dma_tx_complete; 1197 desc->callback_param = s; 1198 spin_unlock_irq(&port->lock); 1199 s->cookie_tx = dmaengine_submit(desc); 1200 if (dma_submit_error(s->cookie_tx)) { 1201 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1202 /* switch to PIO */ 1203 sci_tx_dma_release(s, true); 1204 return; 1205 } 1206 1207 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1208 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1209 1210 dma_async_issue_pending(chan); 1211 } 1212 1213 static void rx_timer_fn(unsigned long arg) 1214 { 1215 struct sci_port *s = (struct sci_port *)arg; 1216 struct dma_chan *chan = s->chan_rx; 1217 struct uart_port *port = &s->port; 1218 struct dma_tx_state state; 1219 enum dma_status status; 1220 unsigned long flags; 1221 unsigned int read; 1222 int active, count; 1223 u16 scr; 1224 1225 dev_dbg(port->dev, "DMA Rx timed out\n"); 1226 1227 spin_lock_irqsave(&port->lock, flags); 1228 1229 active = sci_dma_rx_find_active(s); 1230 if (active < 0) { 1231 spin_unlock_irqrestore(&port->lock, flags); 1232 return; 1233 } 1234 1235 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1236 if (status == DMA_COMPLETE) { 1237 spin_unlock_irqrestore(&port->lock, flags); 1238 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1239 s->active_rx, active); 1240 1241 /* Let packet complete handler take care of the packet */ 1242 return; 1243 } 1244 1245 dmaengine_pause(chan); 1246 1247 /* 1248 * sometimes DMA transfer doesn't stop even if it is stopped and 1249 * data keeps on coming until transaction is complete so check 1250 * for DMA_COMPLETE again 1251 * Let packet complete handler take care of the packet 1252 */ 1253 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1254 if (status == DMA_COMPLETE) { 1255 spin_unlock_irqrestore(&port->lock, flags); 1256 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1257 return; 1258 } 1259 1260 /* Handle incomplete DMA receive */ 1261 dmaengine_terminate_all(s->chan_rx); 1262 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1263 1264 if (read) { 1265 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1266 if (count) 1267 tty_flip_buffer_push(&port->state->port); 1268 } 1269 1270 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1271 sci_submit_rx(s); 1272 1273 /* Direct new serial port interrupts back to CPU */ 1274 scr = serial_port_in(port, SCSCR); 1275 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1276 scr &= ~SCSCR_RDRQE; 1277 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1278 } 1279 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1280 1281 spin_unlock_irqrestore(&port->lock, flags); 1282 } 1283 1284 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1285 enum dma_transfer_direction dir) 1286 { 1287 struct dma_chan *chan; 1288 struct dma_slave_config cfg; 1289 int ret; 1290 1291 chan = dma_request_slave_channel(port->dev, 1292 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1293 if (!chan) { 1294 dev_warn(port->dev, 1295 "dma_request_slave_channel_compat failed\n"); 1296 return NULL; 1297 } 1298 1299 memset(&cfg, 0, sizeof(cfg)); 1300 cfg.direction = dir; 1301 if (dir == DMA_MEM_TO_DEV) { 1302 cfg.dst_addr = port->mapbase + 1303 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1304 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1305 } else { 1306 cfg.src_addr = port->mapbase + 1307 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1308 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1309 } 1310 1311 ret = dmaengine_slave_config(chan, &cfg); 1312 if (ret) { 1313 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1314 dma_release_channel(chan); 1315 return NULL; 1316 } 1317 1318 return chan; 1319 } 1320 1321 static void sci_request_dma(struct uart_port *port) 1322 { 1323 struct sci_port *s = to_sci_port(port); 1324 struct dma_chan *chan; 1325 1326 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1327 1328 if (!port->dev->of_node) 1329 return; 1330 1331 s->cookie_tx = -EINVAL; 1332 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1333 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1334 if (chan) { 1335 s->chan_tx = chan; 1336 /* UART circular tx buffer is an aligned page. */ 1337 s->tx_dma_addr = dma_map_single(chan->device->dev, 1338 port->state->xmit.buf, 1339 UART_XMIT_SIZE, 1340 DMA_TO_DEVICE); 1341 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1342 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1343 dma_release_channel(chan); 1344 s->chan_tx = NULL; 1345 } else { 1346 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1347 __func__, UART_XMIT_SIZE, 1348 port->state->xmit.buf, &s->tx_dma_addr); 1349 } 1350 1351 INIT_WORK(&s->work_tx, work_fn_tx); 1352 } 1353 1354 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1355 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1356 if (chan) { 1357 unsigned int i; 1358 dma_addr_t dma; 1359 void *buf; 1360 1361 s->chan_rx = chan; 1362 1363 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1364 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1365 &dma, GFP_KERNEL); 1366 if (!buf) { 1367 dev_warn(port->dev, 1368 "Failed to allocate Rx dma buffer, using PIO\n"); 1369 dma_release_channel(chan); 1370 s->chan_rx = NULL; 1371 return; 1372 } 1373 1374 for (i = 0; i < 2; i++) { 1375 struct scatterlist *sg = &s->sg_rx[i]; 1376 1377 sg_init_table(sg, 1); 1378 s->rx_buf[i] = buf; 1379 sg_dma_address(sg) = dma; 1380 sg_dma_len(sg) = s->buf_len_rx; 1381 1382 buf += s->buf_len_rx; 1383 dma += s->buf_len_rx; 1384 } 1385 1386 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); 1387 1388 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1389 sci_submit_rx(s); 1390 } 1391 } 1392 1393 static void sci_free_dma(struct uart_port *port) 1394 { 1395 struct sci_port *s = to_sci_port(port); 1396 1397 if (s->chan_tx) 1398 sci_tx_dma_release(s, false); 1399 if (s->chan_rx) 1400 sci_rx_dma_release(s, false); 1401 } 1402 #else 1403 static inline void sci_request_dma(struct uart_port *port) 1404 { 1405 } 1406 1407 static inline void sci_free_dma(struct uart_port *port) 1408 { 1409 } 1410 #endif 1411 1412 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1413 { 1414 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1415 struct uart_port *port = ptr; 1416 struct sci_port *s = to_sci_port(port); 1417 1418 if (s->chan_rx) { 1419 u16 scr = serial_port_in(port, SCSCR); 1420 u16 ssr = serial_port_in(port, SCxSR); 1421 1422 /* Disable future Rx interrupts */ 1423 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1424 disable_irq_nosync(irq); 1425 scr |= SCSCR_RDRQE; 1426 } else { 1427 scr &= ~SCSCR_RIE; 1428 sci_submit_rx(s); 1429 } 1430 serial_port_out(port, SCSCR, scr); 1431 /* Clear current interrupt */ 1432 serial_port_out(port, SCxSR, 1433 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1434 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", 1435 jiffies, s->rx_timeout); 1436 mod_timer(&s->rx_timer, jiffies + s->rx_timeout); 1437 1438 return IRQ_HANDLED; 1439 } 1440 #endif 1441 1442 /* I think sci_receive_chars has to be called irrespective 1443 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1444 * to be disabled? 1445 */ 1446 sci_receive_chars(ptr); 1447 1448 return IRQ_HANDLED; 1449 } 1450 1451 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1452 { 1453 struct uart_port *port = ptr; 1454 unsigned long flags; 1455 1456 spin_lock_irqsave(&port->lock, flags); 1457 sci_transmit_chars(port); 1458 spin_unlock_irqrestore(&port->lock, flags); 1459 1460 return IRQ_HANDLED; 1461 } 1462 1463 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1464 { 1465 struct uart_port *port = ptr; 1466 struct sci_port *s = to_sci_port(port); 1467 1468 /* Handle errors */ 1469 if (port->type == PORT_SCI) { 1470 if (sci_handle_errors(port)) { 1471 /* discard character in rx buffer */ 1472 serial_port_in(port, SCxSR); 1473 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1474 } 1475 } else { 1476 sci_handle_fifo_overrun(port); 1477 if (!s->chan_rx) 1478 sci_receive_chars(ptr); 1479 } 1480 1481 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1482 1483 /* Kick the transmission */ 1484 if (!s->chan_tx) 1485 sci_tx_interrupt(irq, ptr); 1486 1487 return IRQ_HANDLED; 1488 } 1489 1490 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1491 { 1492 struct uart_port *port = ptr; 1493 1494 /* Handle BREAKs */ 1495 sci_handle_breaks(port); 1496 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1497 1498 return IRQ_HANDLED; 1499 } 1500 1501 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1502 { 1503 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1504 struct uart_port *port = ptr; 1505 struct sci_port *s = to_sci_port(port); 1506 irqreturn_t ret = IRQ_NONE; 1507 1508 ssr_status = serial_port_in(port, SCxSR); 1509 scr_status = serial_port_in(port, SCSCR); 1510 if (s->params->overrun_reg == SCxSR) 1511 orer_status = ssr_status; 1512 else if (sci_getreg(port, s->params->overrun_reg)->size) 1513 orer_status = serial_port_in(port, s->params->overrun_reg); 1514 1515 err_enabled = scr_status & port_rx_irq_mask(port); 1516 1517 /* Tx Interrupt */ 1518 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1519 !s->chan_tx) 1520 ret = sci_tx_interrupt(irq, ptr); 1521 1522 /* 1523 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1524 * DR flags 1525 */ 1526 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1527 (scr_status & SCSCR_RIE)) 1528 ret = sci_rx_interrupt(irq, ptr); 1529 1530 /* Error Interrupt */ 1531 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1532 ret = sci_er_interrupt(irq, ptr); 1533 1534 /* Break Interrupt */ 1535 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1536 ret = sci_br_interrupt(irq, ptr); 1537 1538 /* Overrun Interrupt */ 1539 if (orer_status & s->params->overrun_mask) { 1540 sci_handle_fifo_overrun(port); 1541 ret = IRQ_HANDLED; 1542 } 1543 1544 return ret; 1545 } 1546 1547 static const struct sci_irq_desc { 1548 const char *desc; 1549 irq_handler_t handler; 1550 } sci_irq_desc[] = { 1551 /* 1552 * Split out handlers, the default case. 1553 */ 1554 [SCIx_ERI_IRQ] = { 1555 .desc = "rx err", 1556 .handler = sci_er_interrupt, 1557 }, 1558 1559 [SCIx_RXI_IRQ] = { 1560 .desc = "rx full", 1561 .handler = sci_rx_interrupt, 1562 }, 1563 1564 [SCIx_TXI_IRQ] = { 1565 .desc = "tx empty", 1566 .handler = sci_tx_interrupt, 1567 }, 1568 1569 [SCIx_BRI_IRQ] = { 1570 .desc = "break", 1571 .handler = sci_br_interrupt, 1572 }, 1573 1574 /* 1575 * Special muxed handler. 1576 */ 1577 [SCIx_MUX_IRQ] = { 1578 .desc = "mux", 1579 .handler = sci_mpxed_interrupt, 1580 }, 1581 }; 1582 1583 static int sci_request_irq(struct sci_port *port) 1584 { 1585 struct uart_port *up = &port->port; 1586 int i, j, ret = 0; 1587 1588 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1589 const struct sci_irq_desc *desc; 1590 int irq; 1591 1592 if (SCIx_IRQ_IS_MUXED(port)) { 1593 i = SCIx_MUX_IRQ; 1594 irq = up->irq; 1595 } else { 1596 irq = port->irqs[i]; 1597 1598 /* 1599 * Certain port types won't support all of the 1600 * available interrupt sources. 1601 */ 1602 if (unlikely(irq < 0)) 1603 continue; 1604 } 1605 1606 desc = sci_irq_desc + i; 1607 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1608 dev_name(up->dev), desc->desc); 1609 if (!port->irqstr[j]) { 1610 ret = -ENOMEM; 1611 goto out_nomem; 1612 } 1613 1614 ret = request_irq(irq, desc->handler, up->irqflags, 1615 port->irqstr[j], port); 1616 if (unlikely(ret)) { 1617 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1618 goto out_noirq; 1619 } 1620 } 1621 1622 return 0; 1623 1624 out_noirq: 1625 while (--i >= 0) 1626 free_irq(port->irqs[i], port); 1627 1628 out_nomem: 1629 while (--j >= 0) 1630 kfree(port->irqstr[j]); 1631 1632 return ret; 1633 } 1634 1635 static void sci_free_irq(struct sci_port *port) 1636 { 1637 int i; 1638 1639 /* 1640 * Intentionally in reverse order so we iterate over the muxed 1641 * IRQ first. 1642 */ 1643 for (i = 0; i < SCIx_NR_IRQS; i++) { 1644 int irq = port->irqs[i]; 1645 1646 /* 1647 * Certain port types won't support all of the available 1648 * interrupt sources. 1649 */ 1650 if (unlikely(irq < 0)) 1651 continue; 1652 1653 free_irq(port->irqs[i], port); 1654 kfree(port->irqstr[i]); 1655 1656 if (SCIx_IRQ_IS_MUXED(port)) { 1657 /* If there's only one IRQ, we're done. */ 1658 return; 1659 } 1660 } 1661 } 1662 1663 static unsigned int sci_tx_empty(struct uart_port *port) 1664 { 1665 unsigned short status = serial_port_in(port, SCxSR); 1666 unsigned short in_tx_fifo = sci_txfill(port); 1667 1668 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1669 } 1670 1671 static void sci_set_rts(struct uart_port *port, bool state) 1672 { 1673 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1674 u16 data = serial_port_in(port, SCPDR); 1675 1676 /* Active low */ 1677 if (state) 1678 data &= ~SCPDR_RTSD; 1679 else 1680 data |= SCPDR_RTSD; 1681 serial_port_out(port, SCPDR, data); 1682 1683 /* RTS# is output */ 1684 serial_port_out(port, SCPCR, 1685 serial_port_in(port, SCPCR) | SCPCR_RTSC); 1686 } else if (sci_getreg(port, SCSPTR)->size) { 1687 u16 ctrl = serial_port_in(port, SCSPTR); 1688 1689 /* Active low */ 1690 if (state) 1691 ctrl &= ~SCSPTR_RTSDT; 1692 else 1693 ctrl |= SCSPTR_RTSDT; 1694 serial_port_out(port, SCSPTR, ctrl); 1695 } 1696 } 1697 1698 static bool sci_get_cts(struct uart_port *port) 1699 { 1700 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1701 /* Active low */ 1702 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 1703 } else if (sci_getreg(port, SCSPTR)->size) { 1704 /* Active low */ 1705 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 1706 } 1707 1708 return true; 1709 } 1710 1711 /* 1712 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 1713 * CTS/RTS is supported in hardware by at least one port and controlled 1714 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 1715 * handled via the ->init_pins() op, which is a bit of a one-way street, 1716 * lacking any ability to defer pin control -- this will later be 1717 * converted over to the GPIO framework). 1718 * 1719 * Other modes (such as loopback) are supported generically on certain 1720 * port types, but not others. For these it's sufficient to test for the 1721 * existence of the support register and simply ignore the port type. 1722 */ 1723 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1724 { 1725 struct sci_port *s = to_sci_port(port); 1726 1727 if (mctrl & TIOCM_LOOP) { 1728 const struct plat_sci_reg *reg; 1729 1730 /* 1731 * Standard loopback mode for SCFCR ports. 1732 */ 1733 reg = sci_getreg(port, SCFCR); 1734 if (reg->size) 1735 serial_port_out(port, SCFCR, 1736 serial_port_in(port, SCFCR) | 1737 SCFCR_LOOP); 1738 } 1739 1740 mctrl_gpio_set(s->gpios, mctrl); 1741 1742 if (!s->has_rtscts) 1743 return; 1744 1745 if (!(mctrl & TIOCM_RTS)) { 1746 /* Disable Auto RTS */ 1747 serial_port_out(port, SCFCR, 1748 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 1749 1750 /* Clear RTS */ 1751 sci_set_rts(port, 0); 1752 } else if (s->autorts) { 1753 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1754 /* Enable RTS# pin function */ 1755 serial_port_out(port, SCPCR, 1756 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 1757 } 1758 1759 /* Enable Auto RTS */ 1760 serial_port_out(port, SCFCR, 1761 serial_port_in(port, SCFCR) | SCFCR_MCE); 1762 } else { 1763 /* Set RTS */ 1764 sci_set_rts(port, 1); 1765 } 1766 } 1767 1768 static unsigned int sci_get_mctrl(struct uart_port *port) 1769 { 1770 struct sci_port *s = to_sci_port(port); 1771 struct mctrl_gpios *gpios = s->gpios; 1772 unsigned int mctrl = 0; 1773 1774 mctrl_gpio_get(gpios, &mctrl); 1775 1776 /* 1777 * CTS/RTS is handled in hardware when supported, while nothing 1778 * else is wired up. 1779 */ 1780 if (s->autorts) { 1781 if (sci_get_cts(port)) 1782 mctrl |= TIOCM_CTS; 1783 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) { 1784 mctrl |= TIOCM_CTS; 1785 } 1786 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))) 1787 mctrl |= TIOCM_DSR; 1788 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))) 1789 mctrl |= TIOCM_CAR; 1790 1791 return mctrl; 1792 } 1793 1794 static void sci_enable_ms(struct uart_port *port) 1795 { 1796 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 1797 } 1798 1799 static void sci_break_ctl(struct uart_port *port, int break_state) 1800 { 1801 unsigned short scscr, scsptr; 1802 1803 /* check wheter the port has SCSPTR */ 1804 if (!sci_getreg(port, SCSPTR)->size) { 1805 /* 1806 * Not supported by hardware. Most parts couple break and rx 1807 * interrupts together, with break detection always enabled. 1808 */ 1809 return; 1810 } 1811 1812 scsptr = serial_port_in(port, SCSPTR); 1813 scscr = serial_port_in(port, SCSCR); 1814 1815 if (break_state == -1) { 1816 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 1817 scscr &= ~SCSCR_TE; 1818 } else { 1819 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 1820 scscr |= SCSCR_TE; 1821 } 1822 1823 serial_port_out(port, SCSPTR, scsptr); 1824 serial_port_out(port, SCSCR, scscr); 1825 } 1826 1827 static int sci_startup(struct uart_port *port) 1828 { 1829 struct sci_port *s = to_sci_port(port); 1830 int ret; 1831 1832 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1833 1834 ret = sci_request_irq(s); 1835 if (unlikely(ret < 0)) 1836 return ret; 1837 1838 sci_request_dma(port); 1839 1840 return 0; 1841 } 1842 1843 static void sci_shutdown(struct uart_port *port) 1844 { 1845 struct sci_port *s = to_sci_port(port); 1846 unsigned long flags; 1847 u16 scr; 1848 1849 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1850 1851 s->autorts = false; 1852 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 1853 1854 spin_lock_irqsave(&port->lock, flags); 1855 sci_stop_rx(port); 1856 sci_stop_tx(port); 1857 /* Stop RX and TX, disable related interrupts, keep clock source */ 1858 scr = serial_port_in(port, SCSCR); 1859 serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0)); 1860 spin_unlock_irqrestore(&port->lock, flags); 1861 1862 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1863 if (s->chan_rx) { 1864 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 1865 port->line); 1866 del_timer_sync(&s->rx_timer); 1867 } 1868 #endif 1869 1870 sci_free_dma(port); 1871 sci_free_irq(s); 1872 } 1873 1874 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 1875 unsigned int *srr) 1876 { 1877 unsigned long freq = s->clk_rates[SCI_SCK]; 1878 int err, min_err = INT_MAX; 1879 unsigned int sr; 1880 1881 if (s->port.type != PORT_HSCIF) 1882 freq *= 2; 1883 1884 for_each_sr(sr, s) { 1885 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 1886 if (abs(err) >= abs(min_err)) 1887 continue; 1888 1889 min_err = err; 1890 *srr = sr - 1; 1891 1892 if (!err) 1893 break; 1894 } 1895 1896 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 1897 *srr + 1); 1898 return min_err; 1899 } 1900 1901 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 1902 unsigned long freq, unsigned int *dlr, 1903 unsigned int *srr) 1904 { 1905 int err, min_err = INT_MAX; 1906 unsigned int sr, dl; 1907 1908 if (s->port.type != PORT_HSCIF) 1909 freq *= 2; 1910 1911 for_each_sr(sr, s) { 1912 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 1913 dl = clamp(dl, 1U, 65535U); 1914 1915 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 1916 if (abs(err) >= abs(min_err)) 1917 continue; 1918 1919 min_err = err; 1920 *dlr = dl; 1921 *srr = sr - 1; 1922 1923 if (!err) 1924 break; 1925 } 1926 1927 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 1928 min_err, *dlr, *srr + 1); 1929 return min_err; 1930 } 1931 1932 /* calculate sample rate, BRR, and clock select */ 1933 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 1934 unsigned int *brr, unsigned int *srr, 1935 unsigned int *cks) 1936 { 1937 unsigned long freq = s->clk_rates[SCI_FCK]; 1938 unsigned int sr, br, prediv, scrate, c; 1939 int err, min_err = INT_MAX; 1940 1941 if (s->port.type != PORT_HSCIF) 1942 freq *= 2; 1943 1944 /* 1945 * Find the combination of sample rate and clock select with the 1946 * smallest deviation from the desired baud rate. 1947 * Prefer high sample rates to maximise the receive margin. 1948 * 1949 * M: Receive margin (%) 1950 * N: Ratio of bit rate to clock (N = sampling rate) 1951 * D: Clock duty (D = 0 to 1.0) 1952 * L: Frame length (L = 9 to 12) 1953 * F: Absolute value of clock frequency deviation 1954 * 1955 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 1956 * (|D - 0.5| / N * (1 + F))| 1957 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 1958 */ 1959 for_each_sr(sr, s) { 1960 for (c = 0; c <= 3; c++) { 1961 /* integerized formulas from HSCIF documentation */ 1962 prediv = sr * (1 << (2 * c + 1)); 1963 1964 /* 1965 * We need to calculate: 1966 * 1967 * br = freq / (prediv * bps) clamped to [1..256] 1968 * err = freq / (br * prediv) - bps 1969 * 1970 * Watch out for overflow when calculating the desired 1971 * sampling clock rate! 1972 */ 1973 if (bps > UINT_MAX / prediv) 1974 break; 1975 1976 scrate = prediv * bps; 1977 br = DIV_ROUND_CLOSEST(freq, scrate); 1978 br = clamp(br, 1U, 256U); 1979 1980 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 1981 if (abs(err) >= abs(min_err)) 1982 continue; 1983 1984 min_err = err; 1985 *brr = br - 1; 1986 *srr = sr - 1; 1987 *cks = c; 1988 1989 if (!err) 1990 goto found; 1991 } 1992 } 1993 1994 found: 1995 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 1996 min_err, *brr, *srr + 1, *cks); 1997 return min_err; 1998 } 1999 2000 static void sci_reset(struct uart_port *port) 2001 { 2002 const struct plat_sci_reg *reg; 2003 unsigned int status; 2004 2005 do { 2006 status = serial_port_in(port, SCxSR); 2007 } while (!(status & SCxSR_TEND(port))); 2008 2009 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 2010 2011 reg = sci_getreg(port, SCFCR); 2012 if (reg->size) 2013 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2014 2015 sci_clear_SCxSR(port, 2016 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2017 SCxSR_BREAK_CLEAR(port)); 2018 if (sci_getreg(port, SCLSR)->size) { 2019 status = serial_port_in(port, SCLSR); 2020 status &= ~(SCLSR_TO | SCLSR_ORER); 2021 serial_port_out(port, SCLSR, status); 2022 } 2023 } 2024 2025 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2026 struct ktermios *old) 2027 { 2028 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i; 2029 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2030 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2031 struct sci_port *s = to_sci_port(port); 2032 const struct plat_sci_reg *reg; 2033 int min_err = INT_MAX, err; 2034 unsigned long max_freq = 0; 2035 int best_clk = -1; 2036 2037 if ((termios->c_cflag & CSIZE) == CS7) 2038 smr_val |= SCSMR_CHR; 2039 if (termios->c_cflag & PARENB) 2040 smr_val |= SCSMR_PE; 2041 if (termios->c_cflag & PARODD) 2042 smr_val |= SCSMR_PE | SCSMR_ODD; 2043 if (termios->c_cflag & CSTOPB) 2044 smr_val |= SCSMR_STOP; 2045 2046 /* 2047 * earlyprintk comes here early on with port->uartclk set to zero. 2048 * the clock framework is not up and running at this point so here 2049 * we assume that 115200 is the maximum baud rate. please note that 2050 * the baud rate is not programmed during earlyprintk - it is assumed 2051 * that the previous boot loader has enabled required clocks and 2052 * setup the baud rate generator hardware for us already. 2053 */ 2054 if (!port->uartclk) { 2055 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2056 goto done; 2057 } 2058 2059 for (i = 0; i < SCI_NUM_CLKS; i++) 2060 max_freq = max(max_freq, s->clk_rates[i]); 2061 2062 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2063 if (!baud) 2064 goto done; 2065 2066 /* 2067 * There can be multiple sources for the sampling clock. Find the one 2068 * that gives us the smallest deviation from the desired baud rate. 2069 */ 2070 2071 /* Optional Undivided External Clock */ 2072 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2073 port->type != PORT_SCIFB) { 2074 err = sci_sck_calc(s, baud, &srr1); 2075 if (abs(err) < abs(min_err)) { 2076 best_clk = SCI_SCK; 2077 scr_val = SCSCR_CKE1; 2078 sccks = SCCKS_CKS; 2079 min_err = err; 2080 srr = srr1; 2081 if (!err) 2082 goto done; 2083 } 2084 } 2085 2086 /* Optional BRG Frequency Divided External Clock */ 2087 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2088 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2089 &srr1); 2090 if (abs(err) < abs(min_err)) { 2091 best_clk = SCI_SCIF_CLK; 2092 scr_val = SCSCR_CKE1; 2093 sccks = 0; 2094 min_err = err; 2095 dl = dl1; 2096 srr = srr1; 2097 if (!err) 2098 goto done; 2099 } 2100 } 2101 2102 /* Optional BRG Frequency Divided Internal Clock */ 2103 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2104 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2105 &srr1); 2106 if (abs(err) < abs(min_err)) { 2107 best_clk = SCI_BRG_INT; 2108 scr_val = SCSCR_CKE1; 2109 sccks = SCCKS_XIN; 2110 min_err = err; 2111 dl = dl1; 2112 srr = srr1; 2113 if (!min_err) 2114 goto done; 2115 } 2116 } 2117 2118 /* Divided Functional Clock using standard Bit Rate Register */ 2119 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2120 if (abs(err) < abs(min_err)) { 2121 best_clk = SCI_FCK; 2122 scr_val = 0; 2123 min_err = err; 2124 brr = brr1; 2125 srr = srr1; 2126 cks = cks1; 2127 } 2128 2129 done: 2130 if (best_clk >= 0) 2131 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2132 s->clks[best_clk], baud, min_err); 2133 2134 sci_port_enable(s); 2135 2136 /* 2137 * Program the optional External Baud Rate Generator (BRG) first. 2138 * It controls the mux to select (H)SCK or frequency divided clock. 2139 */ 2140 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2141 serial_port_out(port, SCDL, dl); 2142 serial_port_out(port, SCCKS, sccks); 2143 } 2144 2145 sci_reset(port); 2146 2147 uart_update_timeout(port, termios->c_cflag, baud); 2148 2149 if (best_clk >= 0) { 2150 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2151 switch (srr + 1) { 2152 case 5: smr_val |= SCSMR_SRC_5; break; 2153 case 7: smr_val |= SCSMR_SRC_7; break; 2154 case 11: smr_val |= SCSMR_SRC_11; break; 2155 case 13: smr_val |= SCSMR_SRC_13; break; 2156 case 16: smr_val |= SCSMR_SRC_16; break; 2157 case 17: smr_val |= SCSMR_SRC_17; break; 2158 case 19: smr_val |= SCSMR_SRC_19; break; 2159 case 27: smr_val |= SCSMR_SRC_27; break; 2160 } 2161 smr_val |= cks; 2162 dev_dbg(port->dev, 2163 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n", 2164 scr_val, smr_val, brr, sccks, dl, srr); 2165 serial_port_out(port, SCSCR, scr_val); 2166 serial_port_out(port, SCSMR, smr_val); 2167 serial_port_out(port, SCBRR, brr); 2168 if (sci_getreg(port, HSSRR)->size) 2169 serial_port_out(port, HSSRR, srr | HSCIF_SRE); 2170 2171 /* Wait one bit interval */ 2172 udelay((1000000 + (baud - 1)) / baud); 2173 } else { 2174 /* Don't touch the bit rate configuration */ 2175 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2176 smr_val |= serial_port_in(port, SCSMR) & 2177 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2178 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val); 2179 serial_port_out(port, SCSCR, scr_val); 2180 serial_port_out(port, SCSMR, smr_val); 2181 } 2182 2183 sci_init_pins(port, termios->c_cflag); 2184 2185 port->status &= ~UPSTAT_AUTOCTS; 2186 s->autorts = false; 2187 reg = sci_getreg(port, SCFCR); 2188 if (reg->size) { 2189 unsigned short ctrl = serial_port_in(port, SCFCR); 2190 2191 if ((port->flags & UPF_HARD_FLOW) && 2192 (termios->c_cflag & CRTSCTS)) { 2193 /* There is no CTS interrupt to restart the hardware */ 2194 port->status |= UPSTAT_AUTOCTS; 2195 /* MCE is enabled when RTS is raised */ 2196 s->autorts = true; 2197 } 2198 2199 /* 2200 * As we've done a sci_reset() above, ensure we don't 2201 * interfere with the FIFOs while toggling MCE. As the 2202 * reset values could still be set, simply mask them out. 2203 */ 2204 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2205 2206 serial_port_out(port, SCFCR, ctrl); 2207 } 2208 2209 scr_val |= SCSCR_RE | SCSCR_TE | 2210 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2211 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val); 2212 serial_port_out(port, SCSCR, scr_val); 2213 if ((srr + 1 == 5) && 2214 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2215 /* 2216 * In asynchronous mode, when the sampling rate is 1/5, first 2217 * received data may become invalid on some SCIFA and SCIFB. 2218 * To avoid this problem wait more than 1 serial data time (1 2219 * bit time x serial data number) after setting SCSCR.RE = 1. 2220 */ 2221 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2222 } 2223 2224 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2225 /* 2226 * Calculate delay for 2 DMA buffers (4 FIFO). 2227 * See serial_core.c::uart_update_timeout(). 2228 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2229 * function calculates 1 jiffie for the data plus 5 jiffies for the 2230 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2231 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2232 * value obtained by this formula is too small. Therefore, if the value 2233 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2234 */ 2235 if (s->chan_rx) { 2236 unsigned int bits; 2237 2238 /* byte size and parity */ 2239 switch (termios->c_cflag & CSIZE) { 2240 case CS5: 2241 bits = 7; 2242 break; 2243 case CS6: 2244 bits = 8; 2245 break; 2246 case CS7: 2247 bits = 9; 2248 break; 2249 default: 2250 bits = 10; 2251 break; 2252 } 2253 2254 if (termios->c_cflag & CSTOPB) 2255 bits++; 2256 if (termios->c_cflag & PARENB) 2257 bits++; 2258 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) / 2259 (baud / 10), 10); 2260 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n", 2261 s->rx_timeout * 1000 / HZ, port->timeout); 2262 if (s->rx_timeout < msecs_to_jiffies(20)) 2263 s->rx_timeout = msecs_to_jiffies(20); 2264 } 2265 #endif 2266 2267 if ((termios->c_cflag & CREAD) != 0) 2268 sci_start_rx(port); 2269 2270 sci_port_disable(s); 2271 2272 if (UART_ENABLE_MS(port, termios->c_cflag)) 2273 sci_enable_ms(port); 2274 } 2275 2276 static void sci_pm(struct uart_port *port, unsigned int state, 2277 unsigned int oldstate) 2278 { 2279 struct sci_port *sci_port = to_sci_port(port); 2280 2281 switch (state) { 2282 case UART_PM_STATE_OFF: 2283 sci_port_disable(sci_port); 2284 break; 2285 default: 2286 sci_port_enable(sci_port); 2287 break; 2288 } 2289 } 2290 2291 static const char *sci_type(struct uart_port *port) 2292 { 2293 switch (port->type) { 2294 case PORT_IRDA: 2295 return "irda"; 2296 case PORT_SCI: 2297 return "sci"; 2298 case PORT_SCIF: 2299 return "scif"; 2300 case PORT_SCIFA: 2301 return "scifa"; 2302 case PORT_SCIFB: 2303 return "scifb"; 2304 case PORT_HSCIF: 2305 return "hscif"; 2306 } 2307 2308 return NULL; 2309 } 2310 2311 static int sci_remap_port(struct uart_port *port) 2312 { 2313 struct sci_port *sport = to_sci_port(port); 2314 2315 /* 2316 * Nothing to do if there's already an established membase. 2317 */ 2318 if (port->membase) 2319 return 0; 2320 2321 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2322 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2323 if (unlikely(!port->membase)) { 2324 dev_err(port->dev, "can't remap port#%d\n", port->line); 2325 return -ENXIO; 2326 } 2327 } else { 2328 /* 2329 * For the simple (and majority of) cases where we don't 2330 * need to do any remapping, just cast the cookie 2331 * directly. 2332 */ 2333 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2334 } 2335 2336 return 0; 2337 } 2338 2339 static void sci_release_port(struct uart_port *port) 2340 { 2341 struct sci_port *sport = to_sci_port(port); 2342 2343 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2344 iounmap(port->membase); 2345 port->membase = NULL; 2346 } 2347 2348 release_mem_region(port->mapbase, sport->reg_size); 2349 } 2350 2351 static int sci_request_port(struct uart_port *port) 2352 { 2353 struct resource *res; 2354 struct sci_port *sport = to_sci_port(port); 2355 int ret; 2356 2357 res = request_mem_region(port->mapbase, sport->reg_size, 2358 dev_name(port->dev)); 2359 if (unlikely(res == NULL)) { 2360 dev_err(port->dev, "request_mem_region failed."); 2361 return -EBUSY; 2362 } 2363 2364 ret = sci_remap_port(port); 2365 if (unlikely(ret != 0)) { 2366 release_resource(res); 2367 return ret; 2368 } 2369 2370 return 0; 2371 } 2372 2373 static void sci_config_port(struct uart_port *port, int flags) 2374 { 2375 if (flags & UART_CONFIG_TYPE) { 2376 struct sci_port *sport = to_sci_port(port); 2377 2378 port->type = sport->cfg->type; 2379 sci_request_port(port); 2380 } 2381 } 2382 2383 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2384 { 2385 if (ser->baud_base < 2400) 2386 /* No paper tape reader for Mitch.. */ 2387 return -EINVAL; 2388 2389 return 0; 2390 } 2391 2392 static const struct uart_ops sci_uart_ops = { 2393 .tx_empty = sci_tx_empty, 2394 .set_mctrl = sci_set_mctrl, 2395 .get_mctrl = sci_get_mctrl, 2396 .start_tx = sci_start_tx, 2397 .stop_tx = sci_stop_tx, 2398 .stop_rx = sci_stop_rx, 2399 .enable_ms = sci_enable_ms, 2400 .break_ctl = sci_break_ctl, 2401 .startup = sci_startup, 2402 .shutdown = sci_shutdown, 2403 .set_termios = sci_set_termios, 2404 .pm = sci_pm, 2405 .type = sci_type, 2406 .release_port = sci_release_port, 2407 .request_port = sci_request_port, 2408 .config_port = sci_config_port, 2409 .verify_port = sci_verify_port, 2410 #ifdef CONFIG_CONSOLE_POLL 2411 .poll_get_char = sci_poll_get_char, 2412 .poll_put_char = sci_poll_put_char, 2413 #endif 2414 }; 2415 2416 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2417 { 2418 const char *clk_names[] = { 2419 [SCI_FCK] = "fck", 2420 [SCI_SCK] = "sck", 2421 [SCI_BRG_INT] = "brg_int", 2422 [SCI_SCIF_CLK] = "scif_clk", 2423 }; 2424 struct clk *clk; 2425 unsigned int i; 2426 2427 if (sci_port->cfg->type == PORT_HSCIF) 2428 clk_names[SCI_SCK] = "hsck"; 2429 2430 for (i = 0; i < SCI_NUM_CLKS; i++) { 2431 clk = devm_clk_get(dev, clk_names[i]); 2432 if (PTR_ERR(clk) == -EPROBE_DEFER) 2433 return -EPROBE_DEFER; 2434 2435 if (IS_ERR(clk) && i == SCI_FCK) { 2436 /* 2437 * "fck" used to be called "sci_ick", and we need to 2438 * maintain DT backward compatibility. 2439 */ 2440 clk = devm_clk_get(dev, "sci_ick"); 2441 if (PTR_ERR(clk) == -EPROBE_DEFER) 2442 return -EPROBE_DEFER; 2443 2444 if (!IS_ERR(clk)) 2445 goto found; 2446 2447 /* 2448 * Not all SH platforms declare a clock lookup entry 2449 * for SCI devices, in which case we need to get the 2450 * global "peripheral_clk" clock. 2451 */ 2452 clk = devm_clk_get(dev, "peripheral_clk"); 2453 if (!IS_ERR(clk)) 2454 goto found; 2455 2456 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2457 PTR_ERR(clk)); 2458 return PTR_ERR(clk); 2459 } 2460 2461 found: 2462 if (IS_ERR(clk)) 2463 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2464 PTR_ERR(clk)); 2465 else 2466 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i], 2467 clk, clk); 2468 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2469 } 2470 return 0; 2471 } 2472 2473 static const struct sci_port_params * 2474 sci_probe_regmap(const struct plat_sci_port *cfg) 2475 { 2476 unsigned int regtype; 2477 2478 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2479 return &sci_port_params[cfg->regtype]; 2480 2481 switch (cfg->type) { 2482 case PORT_SCI: 2483 regtype = SCIx_SCI_REGTYPE; 2484 break; 2485 case PORT_IRDA: 2486 regtype = SCIx_IRDA_REGTYPE; 2487 break; 2488 case PORT_SCIFA: 2489 regtype = SCIx_SCIFA_REGTYPE; 2490 break; 2491 case PORT_SCIFB: 2492 regtype = SCIx_SCIFB_REGTYPE; 2493 break; 2494 case PORT_SCIF: 2495 /* 2496 * The SH-4 is a bit of a misnomer here, although that's 2497 * where this particular port layout originated. This 2498 * configuration (or some slight variation thereof) 2499 * remains the dominant model for all SCIFs. 2500 */ 2501 regtype = SCIx_SH4_SCIF_REGTYPE; 2502 break; 2503 case PORT_HSCIF: 2504 regtype = SCIx_HSCIF_REGTYPE; 2505 break; 2506 default: 2507 pr_err("Can't probe register map for given port\n"); 2508 return NULL; 2509 } 2510 2511 return &sci_port_params[regtype]; 2512 } 2513 2514 static int sci_init_single(struct platform_device *dev, 2515 struct sci_port *sci_port, unsigned int index, 2516 const struct plat_sci_port *p, bool early) 2517 { 2518 struct uart_port *port = &sci_port->port; 2519 const struct resource *res; 2520 unsigned int i; 2521 int ret; 2522 2523 sci_port->cfg = p; 2524 2525 port->ops = &sci_uart_ops; 2526 port->iotype = UPIO_MEM; 2527 port->line = index; 2528 2529 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2530 if (res == NULL) 2531 return -ENOMEM; 2532 2533 port->mapbase = res->start; 2534 sci_port->reg_size = resource_size(res); 2535 2536 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2537 sci_port->irqs[i] = platform_get_irq(dev, i); 2538 2539 /* The SCI generates several interrupts. They can be muxed together or 2540 * connected to different interrupt lines. In the muxed case only one 2541 * interrupt resource is specified. In the non-muxed case three or four 2542 * interrupt resources are specified, as the BRI interrupt is optional. 2543 */ 2544 if (sci_port->irqs[0] < 0) 2545 return -ENXIO; 2546 2547 if (sci_port->irqs[1] < 0) { 2548 sci_port->irqs[1] = sci_port->irqs[0]; 2549 sci_port->irqs[2] = sci_port->irqs[0]; 2550 sci_port->irqs[3] = sci_port->irqs[0]; 2551 } 2552 2553 sci_port->params = sci_probe_regmap(p); 2554 if (unlikely(sci_port->params == NULL)) 2555 return -EINVAL; 2556 2557 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2558 * match the SoC datasheet, this should be investigated. Let platform 2559 * data override the sampling rate for now. 2560 */ 2561 sci_port->sampling_rate_mask = p->sampling_rate 2562 ? SCI_SR(p->sampling_rate) 2563 : sci_port->params->sampling_rate_mask; 2564 2565 if (!early) { 2566 ret = sci_init_clocks(sci_port, &dev->dev); 2567 if (ret < 0) 2568 return ret; 2569 2570 port->dev = &dev->dev; 2571 2572 pm_runtime_enable(&dev->dev); 2573 } 2574 2575 port->type = p->type; 2576 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2577 port->fifosize = sci_port->params->fifosize; 2578 2579 if (port->type == PORT_SCI) { 2580 if (sci_port->reg_size >= 0x20) 2581 port->regshift = 2; 2582 else 2583 port->regshift = 1; 2584 } 2585 2586 /* 2587 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2588 * for the multi-IRQ ports, which is where we are primarily 2589 * concerned with the shutdown path synchronization. 2590 * 2591 * For the muxed case there's nothing more to do. 2592 */ 2593 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2594 port->irqflags = 0; 2595 2596 port->serial_in = sci_serial_in; 2597 port->serial_out = sci_serial_out; 2598 2599 return 0; 2600 } 2601 2602 static void sci_cleanup_single(struct sci_port *port) 2603 { 2604 pm_runtime_disable(port->port.dev); 2605 } 2606 2607 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2608 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2609 static void serial_console_putchar(struct uart_port *port, int ch) 2610 { 2611 sci_poll_put_char(port, ch); 2612 } 2613 2614 /* 2615 * Print a string to the serial port trying not to disturb 2616 * any possible real use of the port... 2617 */ 2618 static void serial_console_write(struct console *co, const char *s, 2619 unsigned count) 2620 { 2621 struct sci_port *sci_port = &sci_ports[co->index]; 2622 struct uart_port *port = &sci_port->port; 2623 unsigned short bits, ctrl, ctrl_temp; 2624 unsigned long flags; 2625 int locked = 1; 2626 2627 local_irq_save(flags); 2628 #if defined(SUPPORT_SYSRQ) 2629 if (port->sysrq) 2630 locked = 0; 2631 else 2632 #endif 2633 if (oops_in_progress) 2634 locked = spin_trylock(&port->lock); 2635 else 2636 spin_lock(&port->lock); 2637 2638 /* first save SCSCR then disable interrupts, keep clock source */ 2639 ctrl = serial_port_in(port, SCSCR); 2640 ctrl_temp = SCSCR_RE | SCSCR_TE | 2641 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 2642 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 2643 serial_port_out(port, SCSCR, ctrl_temp); 2644 2645 uart_console_write(port, s, count, serial_console_putchar); 2646 2647 /* wait until fifo is empty and last bit has been transmitted */ 2648 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2649 while ((serial_port_in(port, SCxSR) & bits) != bits) 2650 cpu_relax(); 2651 2652 /* restore the SCSCR */ 2653 serial_port_out(port, SCSCR, ctrl); 2654 2655 if (locked) 2656 spin_unlock(&port->lock); 2657 local_irq_restore(flags); 2658 } 2659 2660 static int serial_console_setup(struct console *co, char *options) 2661 { 2662 struct sci_port *sci_port; 2663 struct uart_port *port; 2664 int baud = 115200; 2665 int bits = 8; 2666 int parity = 'n'; 2667 int flow = 'n'; 2668 int ret; 2669 2670 /* 2671 * Refuse to handle any bogus ports. 2672 */ 2673 if (co->index < 0 || co->index >= SCI_NPORTS) 2674 return -ENODEV; 2675 2676 sci_port = &sci_ports[co->index]; 2677 port = &sci_port->port; 2678 2679 /* 2680 * Refuse to handle uninitialized ports. 2681 */ 2682 if (!port->ops) 2683 return -ENODEV; 2684 2685 ret = sci_remap_port(port); 2686 if (unlikely(ret != 0)) 2687 return ret; 2688 2689 if (options) 2690 uart_parse_options(options, &baud, &parity, &bits, &flow); 2691 2692 return uart_set_options(port, co, baud, parity, bits, flow); 2693 } 2694 2695 static struct console serial_console = { 2696 .name = "ttySC", 2697 .device = uart_console_device, 2698 .write = serial_console_write, 2699 .setup = serial_console_setup, 2700 .flags = CON_PRINTBUFFER, 2701 .index = -1, 2702 .data = &sci_uart_driver, 2703 }; 2704 2705 static struct console early_serial_console = { 2706 .name = "early_ttySC", 2707 .write = serial_console_write, 2708 .flags = CON_PRINTBUFFER, 2709 .index = -1, 2710 }; 2711 2712 static char early_serial_buf[32]; 2713 2714 static int sci_probe_earlyprintk(struct platform_device *pdev) 2715 { 2716 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 2717 2718 if (early_serial_console.data) 2719 return -EEXIST; 2720 2721 early_serial_console.index = pdev->id; 2722 2723 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 2724 2725 serial_console_setup(&early_serial_console, early_serial_buf); 2726 2727 if (!strstr(early_serial_buf, "keep")) 2728 early_serial_console.flags |= CON_BOOT; 2729 2730 register_console(&early_serial_console); 2731 return 0; 2732 } 2733 2734 #define SCI_CONSOLE (&serial_console) 2735 2736 #else 2737 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 2738 { 2739 return -EINVAL; 2740 } 2741 2742 #define SCI_CONSOLE NULL 2743 2744 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 2745 2746 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 2747 2748 static struct uart_driver sci_uart_driver = { 2749 .owner = THIS_MODULE, 2750 .driver_name = "sci", 2751 .dev_name = "ttySC", 2752 .major = SCI_MAJOR, 2753 .minor = SCI_MINOR_START, 2754 .nr = SCI_NPORTS, 2755 .cons = SCI_CONSOLE, 2756 }; 2757 2758 static int sci_remove(struct platform_device *dev) 2759 { 2760 struct sci_port *port = platform_get_drvdata(dev); 2761 2762 uart_remove_one_port(&sci_uart_driver, &port->port); 2763 2764 sci_cleanup_single(port); 2765 2766 return 0; 2767 } 2768 2769 2770 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 2771 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 2772 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 2773 2774 static const struct of_device_id of_sci_match[] = { 2775 /* SoC-specific types */ 2776 { 2777 .compatible = "renesas,scif-r7s72100", 2778 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 2779 }, 2780 /* Family-specific types */ 2781 { 2782 .compatible = "renesas,rcar-gen1-scif", 2783 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 2784 }, { 2785 .compatible = "renesas,rcar-gen2-scif", 2786 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 2787 }, { 2788 .compatible = "renesas,rcar-gen3-scif", 2789 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 2790 }, 2791 /* Generic types */ 2792 { 2793 .compatible = "renesas,scif", 2794 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 2795 }, { 2796 .compatible = "renesas,scifa", 2797 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 2798 }, { 2799 .compatible = "renesas,scifb", 2800 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 2801 }, { 2802 .compatible = "renesas,hscif", 2803 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 2804 }, { 2805 .compatible = "renesas,sci", 2806 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 2807 }, { 2808 /* Terminator */ 2809 }, 2810 }; 2811 MODULE_DEVICE_TABLE(of, of_sci_match); 2812 2813 static struct plat_sci_port * 2814 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id) 2815 { 2816 struct device_node *np = pdev->dev.of_node; 2817 const struct of_device_id *match; 2818 struct plat_sci_port *p; 2819 struct sci_port *sp; 2820 int id; 2821 2822 if (!IS_ENABLED(CONFIG_OF) || !np) 2823 return NULL; 2824 2825 match = of_match_node(of_sci_match, np); 2826 if (!match) 2827 return NULL; 2828 2829 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 2830 if (!p) 2831 return NULL; 2832 2833 /* Get the line number from the aliases node. */ 2834 id = of_alias_get_id(np, "serial"); 2835 if (id < 0) { 2836 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 2837 return NULL; 2838 } 2839 2840 sp = &sci_ports[id]; 2841 *dev_id = id; 2842 2843 p->type = SCI_OF_TYPE(match->data); 2844 p->regtype = SCI_OF_REGTYPE(match->data); 2845 2846 if (of_find_property(np, "uart-has-rtscts", NULL)) 2847 sp->has_rtscts = true; 2848 2849 return p; 2850 } 2851 2852 static int sci_probe_single(struct platform_device *dev, 2853 unsigned int index, 2854 struct plat_sci_port *p, 2855 struct sci_port *sciport) 2856 { 2857 int ret; 2858 2859 /* Sanity check */ 2860 if (unlikely(index >= SCI_NPORTS)) { 2861 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 2862 index+1, SCI_NPORTS); 2863 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 2864 return -EINVAL; 2865 } 2866 2867 ret = sci_init_single(dev, sciport, index, p, false); 2868 if (ret) 2869 return ret; 2870 2871 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 2872 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS) 2873 return PTR_ERR(sciport->gpios); 2874 2875 if (sciport->has_rtscts) { 2876 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 2877 UART_GPIO_CTS)) || 2878 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 2879 UART_GPIO_RTS))) { 2880 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 2881 return -EINVAL; 2882 } 2883 sciport->port.flags |= UPF_HARD_FLOW; 2884 } 2885 2886 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 2887 if (ret) { 2888 sci_cleanup_single(sciport); 2889 return ret; 2890 } 2891 2892 return 0; 2893 } 2894 2895 static int sci_probe(struct platform_device *dev) 2896 { 2897 struct plat_sci_port *p; 2898 struct sci_port *sp; 2899 unsigned int dev_id; 2900 int ret; 2901 2902 /* 2903 * If we've come here via earlyprintk initialization, head off to 2904 * the special early probe. We don't have sufficient device state 2905 * to make it beyond this yet. 2906 */ 2907 if (is_early_platform_device(dev)) 2908 return sci_probe_earlyprintk(dev); 2909 2910 if (dev->dev.of_node) { 2911 p = sci_parse_dt(dev, &dev_id); 2912 if (p == NULL) 2913 return -EINVAL; 2914 } else { 2915 p = dev->dev.platform_data; 2916 if (p == NULL) { 2917 dev_err(&dev->dev, "no platform data supplied\n"); 2918 return -EINVAL; 2919 } 2920 2921 dev_id = dev->id; 2922 } 2923 2924 sp = &sci_ports[dev_id]; 2925 platform_set_drvdata(dev, sp); 2926 2927 ret = sci_probe_single(dev, dev_id, p, sp); 2928 if (ret) 2929 return ret; 2930 2931 #ifdef CONFIG_SH_STANDARD_BIOS 2932 sh_bios_gdb_detach(); 2933 #endif 2934 2935 return 0; 2936 } 2937 2938 static __maybe_unused int sci_suspend(struct device *dev) 2939 { 2940 struct sci_port *sport = dev_get_drvdata(dev); 2941 2942 if (sport) 2943 uart_suspend_port(&sci_uart_driver, &sport->port); 2944 2945 return 0; 2946 } 2947 2948 static __maybe_unused int sci_resume(struct device *dev) 2949 { 2950 struct sci_port *sport = dev_get_drvdata(dev); 2951 2952 if (sport) 2953 uart_resume_port(&sci_uart_driver, &sport->port); 2954 2955 return 0; 2956 } 2957 2958 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 2959 2960 static struct platform_driver sci_driver = { 2961 .probe = sci_probe, 2962 .remove = sci_remove, 2963 .driver = { 2964 .name = "sh-sci", 2965 .pm = &sci_dev_pm_ops, 2966 .of_match_table = of_match_ptr(of_sci_match), 2967 }, 2968 }; 2969 2970 static int __init sci_init(void) 2971 { 2972 int ret; 2973 2974 pr_info("%s\n", banner); 2975 2976 ret = uart_register_driver(&sci_uart_driver); 2977 if (likely(ret == 0)) { 2978 ret = platform_driver_register(&sci_driver); 2979 if (unlikely(ret)) 2980 uart_unregister_driver(&sci_uart_driver); 2981 } 2982 2983 return ret; 2984 } 2985 2986 static void __exit sci_exit(void) 2987 { 2988 platform_driver_unregister(&sci_driver); 2989 uart_unregister_driver(&sci_uart_driver); 2990 } 2991 2992 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 2993 early_platform_init_buffer("earlyprintk", &sci_driver, 2994 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 2995 #endif 2996 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 2997 static struct __init plat_sci_port port_cfg; 2998 2999 static int __init early_console_setup(struct earlycon_device *device, 3000 int type) 3001 { 3002 if (!device->port.membase) 3003 return -ENODEV; 3004 3005 device->port.serial_in = sci_serial_in; 3006 device->port.serial_out = sci_serial_out; 3007 device->port.type = type; 3008 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3009 port_cfg.type = type; 3010 sci_ports[0].cfg = &port_cfg; 3011 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3012 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3013 sci_serial_out(&sci_ports[0].port, SCSCR, 3014 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3015 3016 device->con->write = serial_console_write; 3017 return 0; 3018 } 3019 static int __init sci_early_console_setup(struct earlycon_device *device, 3020 const char *opt) 3021 { 3022 return early_console_setup(device, PORT_SCI); 3023 } 3024 static int __init scif_early_console_setup(struct earlycon_device *device, 3025 const char *opt) 3026 { 3027 return early_console_setup(device, PORT_SCIF); 3028 } 3029 static int __init scifa_early_console_setup(struct earlycon_device *device, 3030 const char *opt) 3031 { 3032 return early_console_setup(device, PORT_SCIFA); 3033 } 3034 static int __init scifb_early_console_setup(struct earlycon_device *device, 3035 const char *opt) 3036 { 3037 return early_console_setup(device, PORT_SCIFB); 3038 } 3039 static int __init hscif_early_console_setup(struct earlycon_device *device, 3040 const char *opt) 3041 { 3042 return early_console_setup(device, PORT_HSCIF); 3043 } 3044 3045 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3046 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3047 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3048 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3049 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3050 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3051 3052 module_init(sci_init); 3053 module_exit(sci_exit); 3054 3055 MODULE_LICENSE("GPL"); 3056 MODULE_ALIAS("platform:sh-sci"); 3057 MODULE_AUTHOR("Paul Mundt"); 3058 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3059