1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 #define SUPPORT_SYSRQ 20 #endif 21 22 #undef DEBUG 23 24 #include <linux/clk.h> 25 #include <linux/console.h> 26 #include <linux/ctype.h> 27 #include <linux/cpufreq.h> 28 #include <linux/delay.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/init.h> 34 #include <linux/interrupt.h> 35 #include <linux/ioport.h> 36 #include <linux/ktime.h> 37 #include <linux/major.h> 38 #include <linux/module.h> 39 #include <linux/mm.h> 40 #include <linux/of.h> 41 #include <linux/of_device.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/scatterlist.h> 45 #include <linux/serial.h> 46 #include <linux/serial_sci.h> 47 #include <linux/sh_dma.h> 48 #include <linux/slab.h> 49 #include <linux/string.h> 50 #include <linux/sysrq.h> 51 #include <linux/timer.h> 52 #include <linux/tty.h> 53 #include <linux/tty_flip.h> 54 55 #ifdef CONFIG_SUPERH 56 #include <asm/sh_bios.h> 57 #endif 58 59 #include "serial_mctrl_gpio.h" 60 #include "sh-sci.h" 61 62 /* Offsets into the sci_port->irqs array */ 63 enum { 64 SCIx_ERI_IRQ, 65 SCIx_RXI_IRQ, 66 SCIx_TXI_IRQ, 67 SCIx_BRI_IRQ, 68 SCIx_DRI_IRQ, 69 SCIx_TEI_IRQ, 70 SCIx_NR_IRQS, 71 72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 73 }; 74 75 #define SCIx_IRQ_IS_MUXED(port) \ 76 ((port)->irqs[SCIx_ERI_IRQ] == \ 77 (port)->irqs[SCIx_RXI_IRQ]) || \ 78 ((port)->irqs[SCIx_ERI_IRQ] && \ 79 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 80 81 enum SCI_CLKS { 82 SCI_FCK, /* Functional Clock */ 83 SCI_SCK, /* Optional External Clock */ 84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 86 SCI_NUM_CLKS 87 }; 88 89 /* Bit x set means sampling rate x + 1 is supported */ 90 #define SCI_SR(x) BIT((x) - 1) 91 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 92 93 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 95 SCI_SR(19) | SCI_SR(27) 96 97 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 98 #define max_sr(_port) fls((_port)->sampling_rate_mask) 99 100 /* Iterate over all supported sampling rates, from high to low */ 101 #define for_each_sr(_sr, _port) \ 102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 103 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 104 105 struct plat_sci_reg { 106 u8 offset, size; 107 }; 108 109 struct sci_port_params { 110 const struct plat_sci_reg regs[SCIx_NR_REGS]; 111 unsigned int fifosize; 112 unsigned int overrun_reg; 113 unsigned int overrun_mask; 114 unsigned int sampling_rate_mask; 115 unsigned int error_mask; 116 unsigned int error_clear; 117 }; 118 119 struct sci_port { 120 struct uart_port port; 121 122 /* Platform configuration */ 123 const struct sci_port_params *params; 124 const struct plat_sci_port *cfg; 125 unsigned int sampling_rate_mask; 126 resource_size_t reg_size; 127 struct mctrl_gpios *gpios; 128 129 /* Clocks */ 130 struct clk *clks[SCI_NUM_CLKS]; 131 unsigned long clk_rates[SCI_NUM_CLKS]; 132 133 int irqs[SCIx_NR_IRQS]; 134 char *irqstr[SCIx_NR_IRQS]; 135 136 struct dma_chan *chan_tx; 137 struct dma_chan *chan_rx; 138 139 #ifdef CONFIG_SERIAL_SH_SCI_DMA 140 struct dma_chan *chan_tx_saved; 141 struct dma_chan *chan_rx_saved; 142 dma_cookie_t cookie_tx; 143 dma_cookie_t cookie_rx[2]; 144 dma_cookie_t active_rx; 145 dma_addr_t tx_dma_addr; 146 unsigned int tx_dma_len; 147 struct scatterlist sg_rx[2]; 148 void *rx_buf[2]; 149 size_t buf_len_rx; 150 struct work_struct work_tx; 151 struct hrtimer rx_timer; 152 unsigned int rx_timeout; /* microseconds */ 153 #endif 154 unsigned int rx_frame; 155 int rx_trigger; 156 struct timer_list rx_fifo_timer; 157 int rx_fifo_timeout; 158 u16 hscif_tot; 159 160 bool has_rtscts; 161 bool autorts; 162 }; 163 164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 165 166 static struct sci_port sci_ports[SCI_NPORTS]; 167 static unsigned long sci_ports_in_use; 168 static struct uart_driver sci_uart_driver; 169 170 static inline struct sci_port * 171 to_sci_port(struct uart_port *uart) 172 { 173 return container_of(uart, struct sci_port, port); 174 } 175 176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 177 /* 178 * Common SCI definitions, dependent on the port's regshift 179 * value. 180 */ 181 [SCIx_SCI_REGTYPE] = { 182 .regs = { 183 [SCSMR] = { 0x00, 8 }, 184 [SCBRR] = { 0x01, 8 }, 185 [SCSCR] = { 0x02, 8 }, 186 [SCxTDR] = { 0x03, 8 }, 187 [SCxSR] = { 0x04, 8 }, 188 [SCxRDR] = { 0x05, 8 }, 189 }, 190 .fifosize = 1, 191 .overrun_reg = SCxSR, 192 .overrun_mask = SCI_ORER, 193 .sampling_rate_mask = SCI_SR(32), 194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 196 }, 197 198 /* 199 * Common definitions for legacy IrDA ports. 200 */ 201 [SCIx_IRDA_REGTYPE] = { 202 .regs = { 203 [SCSMR] = { 0x00, 8 }, 204 [SCBRR] = { 0x02, 8 }, 205 [SCSCR] = { 0x04, 8 }, 206 [SCxTDR] = { 0x06, 8 }, 207 [SCxSR] = { 0x08, 16 }, 208 [SCxRDR] = { 0x0a, 8 }, 209 [SCFCR] = { 0x0c, 8 }, 210 [SCFDR] = { 0x0e, 16 }, 211 }, 212 .fifosize = 1, 213 .overrun_reg = SCxSR, 214 .overrun_mask = SCI_ORER, 215 .sampling_rate_mask = SCI_SR(32), 216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 218 }, 219 220 /* 221 * Common SCIFA definitions. 222 */ 223 [SCIx_SCIFA_REGTYPE] = { 224 .regs = { 225 [SCSMR] = { 0x00, 16 }, 226 [SCBRR] = { 0x04, 8 }, 227 [SCSCR] = { 0x08, 16 }, 228 [SCxTDR] = { 0x20, 8 }, 229 [SCxSR] = { 0x14, 16 }, 230 [SCxRDR] = { 0x24, 8 }, 231 [SCFCR] = { 0x18, 16 }, 232 [SCFDR] = { 0x1c, 16 }, 233 [SCPCR] = { 0x30, 16 }, 234 [SCPDR] = { 0x34, 16 }, 235 }, 236 .fifosize = 64, 237 .overrun_reg = SCxSR, 238 .overrun_mask = SCIFA_ORER, 239 .sampling_rate_mask = SCI_SR_SCIFAB, 240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 242 }, 243 244 /* 245 * Common SCIFB definitions. 246 */ 247 [SCIx_SCIFB_REGTYPE] = { 248 .regs = { 249 [SCSMR] = { 0x00, 16 }, 250 [SCBRR] = { 0x04, 8 }, 251 [SCSCR] = { 0x08, 16 }, 252 [SCxTDR] = { 0x40, 8 }, 253 [SCxSR] = { 0x14, 16 }, 254 [SCxRDR] = { 0x60, 8 }, 255 [SCFCR] = { 0x18, 16 }, 256 [SCTFDR] = { 0x38, 16 }, 257 [SCRFDR] = { 0x3c, 16 }, 258 [SCPCR] = { 0x30, 16 }, 259 [SCPDR] = { 0x34, 16 }, 260 }, 261 .fifosize = 256, 262 .overrun_reg = SCxSR, 263 .overrun_mask = SCIFA_ORER, 264 .sampling_rate_mask = SCI_SR_SCIFAB, 265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 267 }, 268 269 /* 270 * Common SH-2(A) SCIF definitions for ports with FIFO data 271 * count registers. 272 */ 273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 274 .regs = { 275 [SCSMR] = { 0x00, 16 }, 276 [SCBRR] = { 0x04, 8 }, 277 [SCSCR] = { 0x08, 16 }, 278 [SCxTDR] = { 0x0c, 8 }, 279 [SCxSR] = { 0x10, 16 }, 280 [SCxRDR] = { 0x14, 8 }, 281 [SCFCR] = { 0x18, 16 }, 282 [SCFDR] = { 0x1c, 16 }, 283 [SCSPTR] = { 0x20, 16 }, 284 [SCLSR] = { 0x24, 16 }, 285 }, 286 .fifosize = 16, 287 .overrun_reg = SCLSR, 288 .overrun_mask = SCLSR_ORER, 289 .sampling_rate_mask = SCI_SR(32), 290 .error_mask = SCIF_DEFAULT_ERROR_MASK, 291 .error_clear = SCIF_ERROR_CLEAR, 292 }, 293 294 /* 295 * The "SCIFA" that is in RZ/T and RZ/A2. 296 * It looks like a normal SCIF with FIFO data, but with a 297 * compressed address space. Also, the break out of interrupts 298 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 299 */ 300 [SCIx_RZ_SCIFA_REGTYPE] = { 301 .regs = { 302 [SCSMR] = { 0x00, 16 }, 303 [SCBRR] = { 0x02, 8 }, 304 [SCSCR] = { 0x04, 16 }, 305 [SCxTDR] = { 0x06, 8 }, 306 [SCxSR] = { 0x08, 16 }, 307 [SCxRDR] = { 0x0A, 8 }, 308 [SCFCR] = { 0x0C, 16 }, 309 [SCFDR] = { 0x0E, 16 }, 310 [SCSPTR] = { 0x10, 16 }, 311 [SCLSR] = { 0x12, 16 }, 312 }, 313 .fifosize = 16, 314 .overrun_reg = SCLSR, 315 .overrun_mask = SCLSR_ORER, 316 .sampling_rate_mask = SCI_SR(32), 317 .error_mask = SCIF_DEFAULT_ERROR_MASK, 318 .error_clear = SCIF_ERROR_CLEAR, 319 }, 320 321 /* 322 * Common SH-3 SCIF definitions. 323 */ 324 [SCIx_SH3_SCIF_REGTYPE] = { 325 .regs = { 326 [SCSMR] = { 0x00, 8 }, 327 [SCBRR] = { 0x02, 8 }, 328 [SCSCR] = { 0x04, 8 }, 329 [SCxTDR] = { 0x06, 8 }, 330 [SCxSR] = { 0x08, 16 }, 331 [SCxRDR] = { 0x0a, 8 }, 332 [SCFCR] = { 0x0c, 8 }, 333 [SCFDR] = { 0x0e, 16 }, 334 }, 335 .fifosize = 16, 336 .overrun_reg = SCLSR, 337 .overrun_mask = SCLSR_ORER, 338 .sampling_rate_mask = SCI_SR(32), 339 .error_mask = SCIF_DEFAULT_ERROR_MASK, 340 .error_clear = SCIF_ERROR_CLEAR, 341 }, 342 343 /* 344 * Common SH-4(A) SCIF(B) definitions. 345 */ 346 [SCIx_SH4_SCIF_REGTYPE] = { 347 .regs = { 348 [SCSMR] = { 0x00, 16 }, 349 [SCBRR] = { 0x04, 8 }, 350 [SCSCR] = { 0x08, 16 }, 351 [SCxTDR] = { 0x0c, 8 }, 352 [SCxSR] = { 0x10, 16 }, 353 [SCxRDR] = { 0x14, 8 }, 354 [SCFCR] = { 0x18, 16 }, 355 [SCFDR] = { 0x1c, 16 }, 356 [SCSPTR] = { 0x20, 16 }, 357 [SCLSR] = { 0x24, 16 }, 358 }, 359 .fifosize = 16, 360 .overrun_reg = SCLSR, 361 .overrun_mask = SCLSR_ORER, 362 .sampling_rate_mask = SCI_SR(32), 363 .error_mask = SCIF_DEFAULT_ERROR_MASK, 364 .error_clear = SCIF_ERROR_CLEAR, 365 }, 366 367 /* 368 * Common SCIF definitions for ports with a Baud Rate Generator for 369 * External Clock (BRG). 370 */ 371 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 372 .regs = { 373 [SCSMR] = { 0x00, 16 }, 374 [SCBRR] = { 0x04, 8 }, 375 [SCSCR] = { 0x08, 16 }, 376 [SCxTDR] = { 0x0c, 8 }, 377 [SCxSR] = { 0x10, 16 }, 378 [SCxRDR] = { 0x14, 8 }, 379 [SCFCR] = { 0x18, 16 }, 380 [SCFDR] = { 0x1c, 16 }, 381 [SCSPTR] = { 0x20, 16 }, 382 [SCLSR] = { 0x24, 16 }, 383 [SCDL] = { 0x30, 16 }, 384 [SCCKS] = { 0x34, 16 }, 385 }, 386 .fifosize = 16, 387 .overrun_reg = SCLSR, 388 .overrun_mask = SCLSR_ORER, 389 .sampling_rate_mask = SCI_SR(32), 390 .error_mask = SCIF_DEFAULT_ERROR_MASK, 391 .error_clear = SCIF_ERROR_CLEAR, 392 }, 393 394 /* 395 * Common HSCIF definitions. 396 */ 397 [SCIx_HSCIF_REGTYPE] = { 398 .regs = { 399 [SCSMR] = { 0x00, 16 }, 400 [SCBRR] = { 0x04, 8 }, 401 [SCSCR] = { 0x08, 16 }, 402 [SCxTDR] = { 0x0c, 8 }, 403 [SCxSR] = { 0x10, 16 }, 404 [SCxRDR] = { 0x14, 8 }, 405 [SCFCR] = { 0x18, 16 }, 406 [SCFDR] = { 0x1c, 16 }, 407 [SCSPTR] = { 0x20, 16 }, 408 [SCLSR] = { 0x24, 16 }, 409 [HSSRR] = { 0x40, 16 }, 410 [SCDL] = { 0x30, 16 }, 411 [SCCKS] = { 0x34, 16 }, 412 [HSRTRGR] = { 0x54, 16 }, 413 [HSTTRGR] = { 0x58, 16 }, 414 }, 415 .fifosize = 128, 416 .overrun_reg = SCLSR, 417 .overrun_mask = SCLSR_ORER, 418 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 419 .error_mask = SCIF_DEFAULT_ERROR_MASK, 420 .error_clear = SCIF_ERROR_CLEAR, 421 }, 422 423 /* 424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 425 * register. 426 */ 427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 428 .regs = { 429 [SCSMR] = { 0x00, 16 }, 430 [SCBRR] = { 0x04, 8 }, 431 [SCSCR] = { 0x08, 16 }, 432 [SCxTDR] = { 0x0c, 8 }, 433 [SCxSR] = { 0x10, 16 }, 434 [SCxRDR] = { 0x14, 8 }, 435 [SCFCR] = { 0x18, 16 }, 436 [SCFDR] = { 0x1c, 16 }, 437 [SCLSR] = { 0x24, 16 }, 438 }, 439 .fifosize = 16, 440 .overrun_reg = SCLSR, 441 .overrun_mask = SCLSR_ORER, 442 .sampling_rate_mask = SCI_SR(32), 443 .error_mask = SCIF_DEFAULT_ERROR_MASK, 444 .error_clear = SCIF_ERROR_CLEAR, 445 }, 446 447 /* 448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 449 * count registers. 450 */ 451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 452 .regs = { 453 [SCSMR] = { 0x00, 16 }, 454 [SCBRR] = { 0x04, 8 }, 455 [SCSCR] = { 0x08, 16 }, 456 [SCxTDR] = { 0x0c, 8 }, 457 [SCxSR] = { 0x10, 16 }, 458 [SCxRDR] = { 0x14, 8 }, 459 [SCFCR] = { 0x18, 16 }, 460 [SCFDR] = { 0x1c, 16 }, 461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 462 [SCRFDR] = { 0x20, 16 }, 463 [SCSPTR] = { 0x24, 16 }, 464 [SCLSR] = { 0x28, 16 }, 465 }, 466 .fifosize = 16, 467 .overrun_reg = SCLSR, 468 .overrun_mask = SCLSR_ORER, 469 .sampling_rate_mask = SCI_SR(32), 470 .error_mask = SCIF_DEFAULT_ERROR_MASK, 471 .error_clear = SCIF_ERROR_CLEAR, 472 }, 473 474 /* 475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 476 * registers. 477 */ 478 [SCIx_SH7705_SCIF_REGTYPE] = { 479 .regs = { 480 [SCSMR] = { 0x00, 16 }, 481 [SCBRR] = { 0x04, 8 }, 482 [SCSCR] = { 0x08, 16 }, 483 [SCxTDR] = { 0x20, 8 }, 484 [SCxSR] = { 0x14, 16 }, 485 [SCxRDR] = { 0x24, 8 }, 486 [SCFCR] = { 0x18, 16 }, 487 [SCFDR] = { 0x1c, 16 }, 488 }, 489 .fifosize = 64, 490 .overrun_reg = SCxSR, 491 .overrun_mask = SCIFA_ORER, 492 .sampling_rate_mask = SCI_SR(16), 493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 495 }, 496 }; 497 498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 499 500 /* 501 * The "offset" here is rather misleading, in that it refers to an enum 502 * value relative to the port mapping rather than the fixed offset 503 * itself, which needs to be manually retrieved from the platform's 504 * register map for the given port. 505 */ 506 static unsigned int sci_serial_in(struct uart_port *p, int offset) 507 { 508 const struct plat_sci_reg *reg = sci_getreg(p, offset); 509 510 if (reg->size == 8) 511 return ioread8(p->membase + (reg->offset << p->regshift)); 512 else if (reg->size == 16) 513 return ioread16(p->membase + (reg->offset << p->regshift)); 514 else 515 WARN(1, "Invalid register access\n"); 516 517 return 0; 518 } 519 520 static void sci_serial_out(struct uart_port *p, int offset, int value) 521 { 522 const struct plat_sci_reg *reg = sci_getreg(p, offset); 523 524 if (reg->size == 8) 525 iowrite8(value, p->membase + (reg->offset << p->regshift)); 526 else if (reg->size == 16) 527 iowrite16(value, p->membase + (reg->offset << p->regshift)); 528 else 529 WARN(1, "Invalid register access\n"); 530 } 531 532 static void sci_port_enable(struct sci_port *sci_port) 533 { 534 unsigned int i; 535 536 if (!sci_port->port.dev) 537 return; 538 539 pm_runtime_get_sync(sci_port->port.dev); 540 541 for (i = 0; i < SCI_NUM_CLKS; i++) { 542 clk_prepare_enable(sci_port->clks[i]); 543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 544 } 545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 546 } 547 548 static void sci_port_disable(struct sci_port *sci_port) 549 { 550 unsigned int i; 551 552 if (!sci_port->port.dev) 553 return; 554 555 for (i = SCI_NUM_CLKS; i-- > 0; ) 556 clk_disable_unprepare(sci_port->clks[i]); 557 558 pm_runtime_put_sync(sci_port->port.dev); 559 } 560 561 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 562 { 563 /* 564 * Not all ports (such as SCIFA) will support REIE. Rather than 565 * special-casing the port type, we check the port initialization 566 * IRQ enable mask to see whether the IRQ is desired at all. If 567 * it's unset, it's logically inferred that there's no point in 568 * testing for it. 569 */ 570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 571 } 572 573 static void sci_start_tx(struct uart_port *port) 574 { 575 struct sci_port *s = to_sci_port(port); 576 unsigned short ctrl; 577 578 #ifdef CONFIG_SERIAL_SH_SCI_DMA 579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 580 u16 new, scr = serial_port_in(port, SCSCR); 581 if (s->chan_tx) 582 new = scr | SCSCR_TDRQE; 583 else 584 new = scr & ~SCSCR_TDRQE; 585 if (new != scr) 586 serial_port_out(port, SCSCR, new); 587 } 588 589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 590 dma_submit_error(s->cookie_tx)) { 591 s->cookie_tx = 0; 592 schedule_work(&s->work_tx); 593 } 594 #endif 595 596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 598 ctrl = serial_port_in(port, SCSCR); 599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 600 } 601 } 602 603 static void sci_stop_tx(struct uart_port *port) 604 { 605 unsigned short ctrl; 606 607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 608 ctrl = serial_port_in(port, SCSCR); 609 610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 611 ctrl &= ~SCSCR_TDRQE; 612 613 ctrl &= ~SCSCR_TIE; 614 615 serial_port_out(port, SCSCR, ctrl); 616 } 617 618 static void sci_start_rx(struct uart_port *port) 619 { 620 unsigned short ctrl; 621 622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 623 624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 625 ctrl &= ~SCSCR_RDRQE; 626 627 serial_port_out(port, SCSCR, ctrl); 628 } 629 630 static void sci_stop_rx(struct uart_port *port) 631 { 632 unsigned short ctrl; 633 634 ctrl = serial_port_in(port, SCSCR); 635 636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 637 ctrl &= ~SCSCR_RDRQE; 638 639 ctrl &= ~port_rx_irq_mask(port); 640 641 serial_port_out(port, SCSCR, ctrl); 642 } 643 644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 645 { 646 if (port->type == PORT_SCI) { 647 /* Just store the mask */ 648 serial_port_out(port, SCxSR, mask); 649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 651 /* Only clear the status bits we want to clear */ 652 serial_port_out(port, SCxSR, 653 serial_port_in(port, SCxSR) & mask); 654 } else { 655 /* Store the mask, clear parity/framing errors */ 656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 657 } 658 } 659 660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 662 663 #ifdef CONFIG_CONSOLE_POLL 664 static int sci_poll_get_char(struct uart_port *port) 665 { 666 unsigned short status; 667 int c; 668 669 do { 670 status = serial_port_in(port, SCxSR); 671 if (status & SCxSR_ERRORS(port)) { 672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 673 continue; 674 } 675 break; 676 } while (1); 677 678 if (!(status & SCxSR_RDxF(port))) 679 return NO_POLL_CHAR; 680 681 c = serial_port_in(port, SCxRDR); 682 683 /* Dummy read */ 684 serial_port_in(port, SCxSR); 685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 686 687 return c; 688 } 689 #endif 690 691 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 692 { 693 unsigned short status; 694 695 do { 696 status = serial_port_in(port, SCxSR); 697 } while (!(status & SCxSR_TDxE(port))); 698 699 serial_port_out(port, SCxTDR, c); 700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 701 } 702 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 703 CONFIG_SERIAL_SH_SCI_EARLYCON */ 704 705 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 706 { 707 struct sci_port *s = to_sci_port(port); 708 709 /* 710 * Use port-specific handler if provided. 711 */ 712 if (s->cfg->ops && s->cfg->ops->init_pins) { 713 s->cfg->ops->init_pins(port, cflag); 714 return; 715 } 716 717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 718 u16 data = serial_port_in(port, SCPDR); 719 u16 ctrl = serial_port_in(port, SCPCR); 720 721 /* Enable RXD and TXD pin functions */ 722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 723 if (to_sci_port(port)->has_rtscts) { 724 /* RTS# is output, active low, unless autorts */ 725 if (!(port->mctrl & TIOCM_RTS)) { 726 ctrl |= SCPCR_RTSC; 727 data |= SCPDR_RTSD; 728 } else if (!s->autorts) { 729 ctrl |= SCPCR_RTSC; 730 data &= ~SCPDR_RTSD; 731 } else { 732 /* Enable RTS# pin function */ 733 ctrl &= ~SCPCR_RTSC; 734 } 735 /* Enable CTS# pin function */ 736 ctrl &= ~SCPCR_CTSC; 737 } 738 serial_port_out(port, SCPDR, data); 739 serial_port_out(port, SCPCR, ctrl); 740 } else if (sci_getreg(port, SCSPTR)->size) { 741 u16 status = serial_port_in(port, SCSPTR); 742 743 /* RTS# is always output; and active low, unless autorts */ 744 status |= SCSPTR_RTSIO; 745 if (!(port->mctrl & TIOCM_RTS)) 746 status |= SCSPTR_RTSDT; 747 else if (!s->autorts) 748 status &= ~SCSPTR_RTSDT; 749 /* CTS# and SCK are inputs */ 750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 751 serial_port_out(port, SCSPTR, status); 752 } 753 } 754 755 static int sci_txfill(struct uart_port *port) 756 { 757 struct sci_port *s = to_sci_port(port); 758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 759 const struct plat_sci_reg *reg; 760 761 reg = sci_getreg(port, SCTFDR); 762 if (reg->size) 763 return serial_port_in(port, SCTFDR) & fifo_mask; 764 765 reg = sci_getreg(port, SCFDR); 766 if (reg->size) 767 return serial_port_in(port, SCFDR) >> 8; 768 769 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 770 } 771 772 static int sci_txroom(struct uart_port *port) 773 { 774 return port->fifosize - sci_txfill(port); 775 } 776 777 static int sci_rxfill(struct uart_port *port) 778 { 779 struct sci_port *s = to_sci_port(port); 780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 781 const struct plat_sci_reg *reg; 782 783 reg = sci_getreg(port, SCRFDR); 784 if (reg->size) 785 return serial_port_in(port, SCRFDR) & fifo_mask; 786 787 reg = sci_getreg(port, SCFDR); 788 if (reg->size) 789 return serial_port_in(port, SCFDR) & fifo_mask; 790 791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 792 } 793 794 /* ********************************************************************** * 795 * the interrupt related routines * 796 * ********************************************************************** */ 797 798 static void sci_transmit_chars(struct uart_port *port) 799 { 800 struct circ_buf *xmit = &port->state->xmit; 801 unsigned int stopped = uart_tx_stopped(port); 802 unsigned short status; 803 unsigned short ctrl; 804 int count; 805 806 status = serial_port_in(port, SCxSR); 807 if (!(status & SCxSR_TDxE(port))) { 808 ctrl = serial_port_in(port, SCSCR); 809 if (uart_circ_empty(xmit)) 810 ctrl &= ~SCSCR_TIE; 811 else 812 ctrl |= SCSCR_TIE; 813 serial_port_out(port, SCSCR, ctrl); 814 return; 815 } 816 817 count = sci_txroom(port); 818 819 do { 820 unsigned char c; 821 822 if (port->x_char) { 823 c = port->x_char; 824 port->x_char = 0; 825 } else if (!uart_circ_empty(xmit) && !stopped) { 826 c = xmit->buf[xmit->tail]; 827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 828 } else { 829 break; 830 } 831 832 serial_port_out(port, SCxTDR, c); 833 834 port->icount.tx++; 835 } while (--count > 0); 836 837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 838 839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 840 uart_write_wakeup(port); 841 if (uart_circ_empty(xmit)) { 842 sci_stop_tx(port); 843 } else { 844 ctrl = serial_port_in(port, SCSCR); 845 846 if (port->type != PORT_SCI) { 847 serial_port_in(port, SCxSR); /* Dummy read */ 848 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 849 } 850 851 ctrl |= SCSCR_TIE; 852 serial_port_out(port, SCSCR, ctrl); 853 } 854 } 855 856 /* On SH3, SCIF may read end-of-break as a space->mark char */ 857 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 858 859 static void sci_receive_chars(struct uart_port *port) 860 { 861 struct tty_port *tport = &port->state->port; 862 int i, count, copied = 0; 863 unsigned short status; 864 unsigned char flag; 865 866 status = serial_port_in(port, SCxSR); 867 if (!(status & SCxSR_RDxF(port))) 868 return; 869 870 while (1) { 871 /* Don't copy more bytes than there is room for in the buffer */ 872 count = tty_buffer_request_room(tport, sci_rxfill(port)); 873 874 /* If for any reason we can't copy more data, we're done! */ 875 if (count == 0) 876 break; 877 878 if (port->type == PORT_SCI) { 879 char c = serial_port_in(port, SCxRDR); 880 if (uart_handle_sysrq_char(port, c)) 881 count = 0; 882 else 883 tty_insert_flip_char(tport, c, TTY_NORMAL); 884 } else { 885 for (i = 0; i < count; i++) { 886 char c = serial_port_in(port, SCxRDR); 887 888 status = serial_port_in(port, SCxSR); 889 if (uart_handle_sysrq_char(port, c)) { 890 count--; i--; 891 continue; 892 } 893 894 /* Store data and status */ 895 if (status & SCxSR_FER(port)) { 896 flag = TTY_FRAME; 897 port->icount.frame++; 898 dev_notice(port->dev, "frame error\n"); 899 } else if (status & SCxSR_PER(port)) { 900 flag = TTY_PARITY; 901 port->icount.parity++; 902 dev_notice(port->dev, "parity error\n"); 903 } else 904 flag = TTY_NORMAL; 905 906 tty_insert_flip_char(tport, c, flag); 907 } 908 } 909 910 serial_port_in(port, SCxSR); /* dummy read */ 911 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 912 913 copied += count; 914 port->icount.rx += count; 915 } 916 917 if (copied) { 918 /* Tell the rest of the system the news. New characters! */ 919 tty_flip_buffer_push(tport); 920 } else { 921 /* TTY buffers full; read from RX reg to prevent lockup */ 922 serial_port_in(port, SCxRDR); 923 serial_port_in(port, SCxSR); /* dummy read */ 924 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 925 } 926 } 927 928 static int sci_handle_errors(struct uart_port *port) 929 { 930 int copied = 0; 931 unsigned short status = serial_port_in(port, SCxSR); 932 struct tty_port *tport = &port->state->port; 933 struct sci_port *s = to_sci_port(port); 934 935 /* Handle overruns */ 936 if (status & s->params->overrun_mask) { 937 port->icount.overrun++; 938 939 /* overrun error */ 940 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 941 copied++; 942 943 dev_notice(port->dev, "overrun error\n"); 944 } 945 946 if (status & SCxSR_FER(port)) { 947 /* frame error */ 948 port->icount.frame++; 949 950 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 951 copied++; 952 953 dev_notice(port->dev, "frame error\n"); 954 } 955 956 if (status & SCxSR_PER(port)) { 957 /* parity error */ 958 port->icount.parity++; 959 960 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 961 copied++; 962 963 dev_notice(port->dev, "parity error\n"); 964 } 965 966 if (copied) 967 tty_flip_buffer_push(tport); 968 969 return copied; 970 } 971 972 static int sci_handle_fifo_overrun(struct uart_port *port) 973 { 974 struct tty_port *tport = &port->state->port; 975 struct sci_port *s = to_sci_port(port); 976 const struct plat_sci_reg *reg; 977 int copied = 0; 978 u16 status; 979 980 reg = sci_getreg(port, s->params->overrun_reg); 981 if (!reg->size) 982 return 0; 983 984 status = serial_port_in(port, s->params->overrun_reg); 985 if (status & s->params->overrun_mask) { 986 status &= ~s->params->overrun_mask; 987 serial_port_out(port, s->params->overrun_reg, status); 988 989 port->icount.overrun++; 990 991 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 992 tty_flip_buffer_push(tport); 993 994 dev_dbg(port->dev, "overrun error\n"); 995 copied++; 996 } 997 998 return copied; 999 } 1000 1001 static int sci_handle_breaks(struct uart_port *port) 1002 { 1003 int copied = 0; 1004 unsigned short status = serial_port_in(port, SCxSR); 1005 struct tty_port *tport = &port->state->port; 1006 1007 if (uart_handle_break(port)) 1008 return 0; 1009 1010 if (status & SCxSR_BRK(port)) { 1011 port->icount.brk++; 1012 1013 /* Notify of BREAK */ 1014 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1015 copied++; 1016 1017 dev_dbg(port->dev, "BREAK detected\n"); 1018 } 1019 1020 if (copied) 1021 tty_flip_buffer_push(tport); 1022 1023 copied += sci_handle_fifo_overrun(port); 1024 1025 return copied; 1026 } 1027 1028 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1029 { 1030 unsigned int bits; 1031 1032 if (rx_trig < 1) 1033 rx_trig = 1; 1034 if (rx_trig >= port->fifosize) 1035 rx_trig = port->fifosize; 1036 1037 /* HSCIF can be set to an arbitrary level. */ 1038 if (sci_getreg(port, HSRTRGR)->size) { 1039 serial_port_out(port, HSRTRGR, rx_trig); 1040 return rx_trig; 1041 } 1042 1043 switch (port->type) { 1044 case PORT_SCIF: 1045 if (rx_trig < 4) { 1046 bits = 0; 1047 rx_trig = 1; 1048 } else if (rx_trig < 8) { 1049 bits = SCFCR_RTRG0; 1050 rx_trig = 4; 1051 } else if (rx_trig < 14) { 1052 bits = SCFCR_RTRG1; 1053 rx_trig = 8; 1054 } else { 1055 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1056 rx_trig = 14; 1057 } 1058 break; 1059 case PORT_SCIFA: 1060 case PORT_SCIFB: 1061 if (rx_trig < 16) { 1062 bits = 0; 1063 rx_trig = 1; 1064 } else if (rx_trig < 32) { 1065 bits = SCFCR_RTRG0; 1066 rx_trig = 16; 1067 } else if (rx_trig < 48) { 1068 bits = SCFCR_RTRG1; 1069 rx_trig = 32; 1070 } else { 1071 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1072 rx_trig = 48; 1073 } 1074 break; 1075 default: 1076 WARN(1, "unknown FIFO configuration"); 1077 return 1; 1078 } 1079 1080 serial_port_out(port, SCFCR, 1081 (serial_port_in(port, SCFCR) & 1082 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1083 1084 return rx_trig; 1085 } 1086 1087 static int scif_rtrg_enabled(struct uart_port *port) 1088 { 1089 if (sci_getreg(port, HSRTRGR)->size) 1090 return serial_port_in(port, HSRTRGR) != 0; 1091 else 1092 return (serial_port_in(port, SCFCR) & 1093 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1094 } 1095 1096 static void rx_fifo_timer_fn(struct timer_list *t) 1097 { 1098 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1099 struct uart_port *port = &s->port; 1100 1101 dev_dbg(port->dev, "Rx timed out\n"); 1102 scif_set_rtrg(port, 1); 1103 } 1104 1105 static ssize_t rx_trigger_show(struct device *dev, 1106 struct device_attribute *attr, 1107 char *buf) 1108 { 1109 struct uart_port *port = dev_get_drvdata(dev); 1110 struct sci_port *sci = to_sci_port(port); 1111 1112 return sprintf(buf, "%d\n", sci->rx_trigger); 1113 } 1114 1115 static ssize_t rx_trigger_store(struct device *dev, 1116 struct device_attribute *attr, 1117 const char *buf, 1118 size_t count) 1119 { 1120 struct uart_port *port = dev_get_drvdata(dev); 1121 struct sci_port *sci = to_sci_port(port); 1122 int ret; 1123 long r; 1124 1125 ret = kstrtol(buf, 0, &r); 1126 if (ret) 1127 return ret; 1128 1129 sci->rx_trigger = scif_set_rtrg(port, r); 1130 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1131 scif_set_rtrg(port, 1); 1132 1133 return count; 1134 } 1135 1136 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store); 1137 1138 static ssize_t rx_fifo_timeout_show(struct device *dev, 1139 struct device_attribute *attr, 1140 char *buf) 1141 { 1142 struct uart_port *port = dev_get_drvdata(dev); 1143 struct sci_port *sci = to_sci_port(port); 1144 int v; 1145 1146 if (port->type == PORT_HSCIF) 1147 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1148 else 1149 v = sci->rx_fifo_timeout; 1150 1151 return sprintf(buf, "%d\n", v); 1152 } 1153 1154 static ssize_t rx_fifo_timeout_store(struct device *dev, 1155 struct device_attribute *attr, 1156 const char *buf, 1157 size_t count) 1158 { 1159 struct uart_port *port = dev_get_drvdata(dev); 1160 struct sci_port *sci = to_sci_port(port); 1161 int ret; 1162 long r; 1163 1164 ret = kstrtol(buf, 0, &r); 1165 if (ret) 1166 return ret; 1167 1168 if (port->type == PORT_HSCIF) { 1169 if (r < 0 || r > 3) 1170 return -EINVAL; 1171 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1172 } else { 1173 sci->rx_fifo_timeout = r; 1174 scif_set_rtrg(port, 1); 1175 if (r > 0) 1176 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1177 } 1178 1179 return count; 1180 } 1181 1182 static DEVICE_ATTR_RW(rx_fifo_timeout); 1183 1184 1185 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1186 static void sci_dma_tx_complete(void *arg) 1187 { 1188 struct sci_port *s = arg; 1189 struct uart_port *port = &s->port; 1190 struct circ_buf *xmit = &port->state->xmit; 1191 unsigned long flags; 1192 1193 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1194 1195 spin_lock_irqsave(&port->lock, flags); 1196 1197 xmit->tail += s->tx_dma_len; 1198 xmit->tail &= UART_XMIT_SIZE - 1; 1199 1200 port->icount.tx += s->tx_dma_len; 1201 1202 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1203 uart_write_wakeup(port); 1204 1205 if (!uart_circ_empty(xmit)) { 1206 s->cookie_tx = 0; 1207 schedule_work(&s->work_tx); 1208 } else { 1209 s->cookie_tx = -EINVAL; 1210 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1211 u16 ctrl = serial_port_in(port, SCSCR); 1212 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1213 } 1214 } 1215 1216 spin_unlock_irqrestore(&port->lock, flags); 1217 } 1218 1219 /* Locking: called with port lock held */ 1220 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1221 { 1222 struct uart_port *port = &s->port; 1223 struct tty_port *tport = &port->state->port; 1224 int copied; 1225 1226 copied = tty_insert_flip_string(tport, buf, count); 1227 if (copied < count) 1228 port->icount.buf_overrun++; 1229 1230 port->icount.rx += copied; 1231 1232 return copied; 1233 } 1234 1235 static int sci_dma_rx_find_active(struct sci_port *s) 1236 { 1237 unsigned int i; 1238 1239 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1240 if (s->active_rx == s->cookie_rx[i]) 1241 return i; 1242 1243 return -1; 1244 } 1245 1246 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1247 { 1248 unsigned int i; 1249 1250 s->chan_rx = NULL; 1251 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1252 s->cookie_rx[i] = -EINVAL; 1253 s->active_rx = 0; 1254 } 1255 1256 static void sci_dma_rx_release(struct sci_port *s) 1257 { 1258 struct dma_chan *chan = s->chan_rx_saved; 1259 1260 s->chan_rx_saved = NULL; 1261 sci_dma_rx_chan_invalidate(s); 1262 dmaengine_terminate_sync(chan); 1263 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1264 sg_dma_address(&s->sg_rx[0])); 1265 dma_release_channel(chan); 1266 } 1267 1268 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1269 { 1270 long sec = usec / 1000000; 1271 long nsec = (usec % 1000000) * 1000; 1272 ktime_t t = ktime_set(sec, nsec); 1273 1274 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1275 } 1276 1277 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1278 { 1279 struct uart_port *port = &s->port; 1280 u16 scr; 1281 1282 /* Direct new serial port interrupts back to CPU */ 1283 scr = serial_port_in(port, SCSCR); 1284 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1285 scr &= ~SCSCR_RDRQE; 1286 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1287 } 1288 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1289 } 1290 1291 static void sci_dma_rx_complete(void *arg) 1292 { 1293 struct sci_port *s = arg; 1294 struct dma_chan *chan = s->chan_rx; 1295 struct uart_port *port = &s->port; 1296 struct dma_async_tx_descriptor *desc; 1297 unsigned long flags; 1298 int active, count = 0; 1299 1300 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1301 s->active_rx); 1302 1303 spin_lock_irqsave(&port->lock, flags); 1304 1305 active = sci_dma_rx_find_active(s); 1306 if (active >= 0) 1307 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1308 1309 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1310 1311 if (count) 1312 tty_flip_buffer_push(&port->state->port); 1313 1314 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1315 DMA_DEV_TO_MEM, 1316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1317 if (!desc) 1318 goto fail; 1319 1320 desc->callback = sci_dma_rx_complete; 1321 desc->callback_param = s; 1322 s->cookie_rx[active] = dmaengine_submit(desc); 1323 if (dma_submit_error(s->cookie_rx[active])) 1324 goto fail; 1325 1326 s->active_rx = s->cookie_rx[!active]; 1327 1328 dma_async_issue_pending(chan); 1329 1330 spin_unlock_irqrestore(&port->lock, flags); 1331 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1332 __func__, s->cookie_rx[active], active, s->active_rx); 1333 return; 1334 1335 fail: 1336 spin_unlock_irqrestore(&port->lock, flags); 1337 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1338 /* Switch to PIO */ 1339 spin_lock_irqsave(&port->lock, flags); 1340 dmaengine_terminate_async(chan); 1341 sci_dma_rx_chan_invalidate(s); 1342 sci_dma_rx_reenable_irq(s); 1343 spin_unlock_irqrestore(&port->lock, flags); 1344 } 1345 1346 static void sci_dma_tx_release(struct sci_port *s) 1347 { 1348 struct dma_chan *chan = s->chan_tx_saved; 1349 1350 cancel_work_sync(&s->work_tx); 1351 s->chan_tx_saved = s->chan_tx = NULL; 1352 s->cookie_tx = -EINVAL; 1353 dmaengine_terminate_sync(chan); 1354 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1355 DMA_TO_DEVICE); 1356 dma_release_channel(chan); 1357 } 1358 1359 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1360 { 1361 struct dma_chan *chan = s->chan_rx; 1362 struct uart_port *port = &s->port; 1363 unsigned long flags; 1364 int i; 1365 1366 for (i = 0; i < 2; i++) { 1367 struct scatterlist *sg = &s->sg_rx[i]; 1368 struct dma_async_tx_descriptor *desc; 1369 1370 desc = dmaengine_prep_slave_sg(chan, 1371 sg, 1, DMA_DEV_TO_MEM, 1372 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1373 if (!desc) 1374 goto fail; 1375 1376 desc->callback = sci_dma_rx_complete; 1377 desc->callback_param = s; 1378 s->cookie_rx[i] = dmaengine_submit(desc); 1379 if (dma_submit_error(s->cookie_rx[i])) 1380 goto fail; 1381 1382 } 1383 1384 s->active_rx = s->cookie_rx[0]; 1385 1386 dma_async_issue_pending(chan); 1387 return 0; 1388 1389 fail: 1390 /* Switch to PIO */ 1391 if (!port_lock_held) 1392 spin_lock_irqsave(&port->lock, flags); 1393 if (i) 1394 dmaengine_terminate_async(chan); 1395 sci_dma_rx_chan_invalidate(s); 1396 sci_start_rx(port); 1397 if (!port_lock_held) 1398 spin_unlock_irqrestore(&port->lock, flags); 1399 return -EAGAIN; 1400 } 1401 1402 static void sci_dma_tx_work_fn(struct work_struct *work) 1403 { 1404 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1405 struct dma_async_tx_descriptor *desc; 1406 struct dma_chan *chan = s->chan_tx; 1407 struct uart_port *port = &s->port; 1408 struct circ_buf *xmit = &port->state->xmit; 1409 unsigned long flags; 1410 dma_addr_t buf; 1411 1412 /* 1413 * DMA is idle now. 1414 * Port xmit buffer is already mapped, and it is one page... Just adjust 1415 * offsets and lengths. Since it is a circular buffer, we have to 1416 * transmit till the end, and then the rest. Take the port lock to get a 1417 * consistent xmit buffer state. 1418 */ 1419 spin_lock_irq(&port->lock); 1420 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1)); 1421 s->tx_dma_len = min_t(unsigned int, 1422 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), 1423 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); 1424 spin_unlock_irq(&port->lock); 1425 1426 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1427 DMA_MEM_TO_DEV, 1428 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1429 if (!desc) { 1430 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1431 goto switch_to_pio; 1432 } 1433 1434 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1435 DMA_TO_DEVICE); 1436 1437 spin_lock_irq(&port->lock); 1438 desc->callback = sci_dma_tx_complete; 1439 desc->callback_param = s; 1440 spin_unlock_irq(&port->lock); 1441 s->cookie_tx = dmaengine_submit(desc); 1442 if (dma_submit_error(s->cookie_tx)) { 1443 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1444 goto switch_to_pio; 1445 } 1446 1447 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1448 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx); 1449 1450 dma_async_issue_pending(chan); 1451 return; 1452 1453 switch_to_pio: 1454 spin_lock_irqsave(&port->lock, flags); 1455 s->chan_tx = NULL; 1456 sci_start_tx(port); 1457 spin_unlock_irqrestore(&port->lock, flags); 1458 return; 1459 } 1460 1461 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1462 { 1463 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1464 struct dma_chan *chan = s->chan_rx; 1465 struct uart_port *port = &s->port; 1466 struct dma_tx_state state; 1467 enum dma_status status; 1468 unsigned long flags; 1469 unsigned int read; 1470 int active, count; 1471 1472 dev_dbg(port->dev, "DMA Rx timed out\n"); 1473 1474 spin_lock_irqsave(&port->lock, flags); 1475 1476 active = sci_dma_rx_find_active(s); 1477 if (active < 0) { 1478 spin_unlock_irqrestore(&port->lock, flags); 1479 return HRTIMER_NORESTART; 1480 } 1481 1482 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1483 if (status == DMA_COMPLETE) { 1484 spin_unlock_irqrestore(&port->lock, flags); 1485 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1486 s->active_rx, active); 1487 1488 /* Let packet complete handler take care of the packet */ 1489 return HRTIMER_NORESTART; 1490 } 1491 1492 dmaengine_pause(chan); 1493 1494 /* 1495 * sometimes DMA transfer doesn't stop even if it is stopped and 1496 * data keeps on coming until transaction is complete so check 1497 * for DMA_COMPLETE again 1498 * Let packet complete handler take care of the packet 1499 */ 1500 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1501 if (status == DMA_COMPLETE) { 1502 spin_unlock_irqrestore(&port->lock, flags); 1503 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1504 return HRTIMER_NORESTART; 1505 } 1506 1507 /* Handle incomplete DMA receive */ 1508 dmaengine_terminate_async(s->chan_rx); 1509 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1510 1511 if (read) { 1512 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1513 if (count) 1514 tty_flip_buffer_push(&port->state->port); 1515 } 1516 1517 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1518 sci_dma_rx_submit(s, true); 1519 1520 sci_dma_rx_reenable_irq(s); 1521 1522 spin_unlock_irqrestore(&port->lock, flags); 1523 1524 return HRTIMER_NORESTART; 1525 } 1526 1527 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1528 enum dma_transfer_direction dir) 1529 { 1530 struct dma_chan *chan; 1531 struct dma_slave_config cfg; 1532 int ret; 1533 1534 chan = dma_request_slave_channel(port->dev, 1535 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1536 if (!chan) { 1537 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1538 return NULL; 1539 } 1540 1541 memset(&cfg, 0, sizeof(cfg)); 1542 cfg.direction = dir; 1543 if (dir == DMA_MEM_TO_DEV) { 1544 cfg.dst_addr = port->mapbase + 1545 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1546 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1547 } else { 1548 cfg.src_addr = port->mapbase + 1549 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1550 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1551 } 1552 1553 ret = dmaengine_slave_config(chan, &cfg); 1554 if (ret) { 1555 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1556 dma_release_channel(chan); 1557 return NULL; 1558 } 1559 1560 return chan; 1561 } 1562 1563 static void sci_request_dma(struct uart_port *port) 1564 { 1565 struct sci_port *s = to_sci_port(port); 1566 struct dma_chan *chan; 1567 1568 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1569 1570 if (!port->dev->of_node) 1571 return; 1572 1573 s->cookie_tx = -EINVAL; 1574 1575 /* 1576 * Don't request a dma channel if no channel was specified 1577 * in the device tree. 1578 */ 1579 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1580 return; 1581 1582 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1583 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1584 if (chan) { 1585 /* UART circular tx buffer is an aligned page. */ 1586 s->tx_dma_addr = dma_map_single(chan->device->dev, 1587 port->state->xmit.buf, 1588 UART_XMIT_SIZE, 1589 DMA_TO_DEVICE); 1590 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1591 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1592 dma_release_channel(chan); 1593 } else { 1594 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1595 __func__, UART_XMIT_SIZE, 1596 port->state->xmit.buf, &s->tx_dma_addr); 1597 1598 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1599 s->chan_tx_saved = s->chan_tx = chan; 1600 } 1601 } 1602 1603 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1604 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1605 if (chan) { 1606 unsigned int i; 1607 dma_addr_t dma; 1608 void *buf; 1609 1610 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1611 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1612 &dma, GFP_KERNEL); 1613 if (!buf) { 1614 dev_warn(port->dev, 1615 "Failed to allocate Rx dma buffer, using PIO\n"); 1616 dma_release_channel(chan); 1617 return; 1618 } 1619 1620 for (i = 0; i < 2; i++) { 1621 struct scatterlist *sg = &s->sg_rx[i]; 1622 1623 sg_init_table(sg, 1); 1624 s->rx_buf[i] = buf; 1625 sg_dma_address(sg) = dma; 1626 sg_dma_len(sg) = s->buf_len_rx; 1627 1628 buf += s->buf_len_rx; 1629 dma += s->buf_len_rx; 1630 } 1631 1632 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1633 s->rx_timer.function = sci_dma_rx_timer_fn; 1634 1635 s->chan_rx_saved = s->chan_rx = chan; 1636 1637 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1638 sci_dma_rx_submit(s, false); 1639 } 1640 } 1641 1642 static void sci_free_dma(struct uart_port *port) 1643 { 1644 struct sci_port *s = to_sci_port(port); 1645 1646 if (s->chan_tx_saved) 1647 sci_dma_tx_release(s); 1648 if (s->chan_rx_saved) 1649 sci_dma_rx_release(s); 1650 } 1651 1652 static void sci_flush_buffer(struct uart_port *port) 1653 { 1654 /* 1655 * In uart_flush_buffer(), the xmit circular buffer has just been 1656 * cleared, so we have to reset tx_dma_len accordingly. 1657 */ 1658 to_sci_port(port)->tx_dma_len = 0; 1659 } 1660 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1661 static inline void sci_request_dma(struct uart_port *port) 1662 { 1663 } 1664 1665 static inline void sci_free_dma(struct uart_port *port) 1666 { 1667 } 1668 1669 #define sci_flush_buffer NULL 1670 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1671 1672 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1673 { 1674 struct uart_port *port = ptr; 1675 struct sci_port *s = to_sci_port(port); 1676 1677 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1678 if (s->chan_rx) { 1679 u16 scr = serial_port_in(port, SCSCR); 1680 u16 ssr = serial_port_in(port, SCxSR); 1681 1682 /* Disable future Rx interrupts */ 1683 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1684 disable_irq_nosync(irq); 1685 scr |= SCSCR_RDRQE; 1686 } else { 1687 if (sci_dma_rx_submit(s, false) < 0) 1688 goto handle_pio; 1689 1690 scr &= ~SCSCR_RIE; 1691 } 1692 serial_port_out(port, SCSCR, scr); 1693 /* Clear current interrupt */ 1694 serial_port_out(port, SCxSR, 1695 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1696 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1697 jiffies, s->rx_timeout); 1698 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1699 1700 return IRQ_HANDLED; 1701 } 1702 1703 handle_pio: 1704 #endif 1705 1706 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1707 if (!scif_rtrg_enabled(port)) 1708 scif_set_rtrg(port, s->rx_trigger); 1709 1710 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1711 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1712 } 1713 1714 /* I think sci_receive_chars has to be called irrespective 1715 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1716 * to be disabled? 1717 */ 1718 sci_receive_chars(port); 1719 1720 return IRQ_HANDLED; 1721 } 1722 1723 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1724 { 1725 struct uart_port *port = ptr; 1726 unsigned long flags; 1727 1728 spin_lock_irqsave(&port->lock, flags); 1729 sci_transmit_chars(port); 1730 spin_unlock_irqrestore(&port->lock, flags); 1731 1732 return IRQ_HANDLED; 1733 } 1734 1735 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1736 { 1737 struct uart_port *port = ptr; 1738 1739 /* Handle BREAKs */ 1740 sci_handle_breaks(port); 1741 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1742 1743 return IRQ_HANDLED; 1744 } 1745 1746 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1747 { 1748 struct uart_port *port = ptr; 1749 struct sci_port *s = to_sci_port(port); 1750 1751 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1752 /* Break and Error interrupts are muxed */ 1753 unsigned short ssr_status = serial_port_in(port, SCxSR); 1754 1755 /* Break Interrupt */ 1756 if (ssr_status & SCxSR_BRK(port)) 1757 sci_br_interrupt(irq, ptr); 1758 1759 /* Break only? */ 1760 if (!(ssr_status & SCxSR_ERRORS(port))) 1761 return IRQ_HANDLED; 1762 } 1763 1764 /* Handle errors */ 1765 if (port->type == PORT_SCI) { 1766 if (sci_handle_errors(port)) { 1767 /* discard character in rx buffer */ 1768 serial_port_in(port, SCxSR); 1769 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1770 } 1771 } else { 1772 sci_handle_fifo_overrun(port); 1773 if (!s->chan_rx) 1774 sci_receive_chars(port); 1775 } 1776 1777 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1778 1779 /* Kick the transmission */ 1780 if (!s->chan_tx) 1781 sci_tx_interrupt(irq, ptr); 1782 1783 return IRQ_HANDLED; 1784 } 1785 1786 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1787 { 1788 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1789 struct uart_port *port = ptr; 1790 struct sci_port *s = to_sci_port(port); 1791 irqreturn_t ret = IRQ_NONE; 1792 1793 ssr_status = serial_port_in(port, SCxSR); 1794 scr_status = serial_port_in(port, SCSCR); 1795 if (s->params->overrun_reg == SCxSR) 1796 orer_status = ssr_status; 1797 else if (sci_getreg(port, s->params->overrun_reg)->size) 1798 orer_status = serial_port_in(port, s->params->overrun_reg); 1799 1800 err_enabled = scr_status & port_rx_irq_mask(port); 1801 1802 /* Tx Interrupt */ 1803 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1804 !s->chan_tx) 1805 ret = sci_tx_interrupt(irq, ptr); 1806 1807 /* 1808 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1809 * DR flags 1810 */ 1811 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1812 (scr_status & SCSCR_RIE)) 1813 ret = sci_rx_interrupt(irq, ptr); 1814 1815 /* Error Interrupt */ 1816 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1817 ret = sci_er_interrupt(irq, ptr); 1818 1819 /* Break Interrupt */ 1820 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1821 ret = sci_br_interrupt(irq, ptr); 1822 1823 /* Overrun Interrupt */ 1824 if (orer_status & s->params->overrun_mask) { 1825 sci_handle_fifo_overrun(port); 1826 ret = IRQ_HANDLED; 1827 } 1828 1829 return ret; 1830 } 1831 1832 static const struct sci_irq_desc { 1833 const char *desc; 1834 irq_handler_t handler; 1835 } sci_irq_desc[] = { 1836 /* 1837 * Split out handlers, the default case. 1838 */ 1839 [SCIx_ERI_IRQ] = { 1840 .desc = "rx err", 1841 .handler = sci_er_interrupt, 1842 }, 1843 1844 [SCIx_RXI_IRQ] = { 1845 .desc = "rx full", 1846 .handler = sci_rx_interrupt, 1847 }, 1848 1849 [SCIx_TXI_IRQ] = { 1850 .desc = "tx empty", 1851 .handler = sci_tx_interrupt, 1852 }, 1853 1854 [SCIx_BRI_IRQ] = { 1855 .desc = "break", 1856 .handler = sci_br_interrupt, 1857 }, 1858 1859 [SCIx_DRI_IRQ] = { 1860 .desc = "rx ready", 1861 .handler = sci_rx_interrupt, 1862 }, 1863 1864 [SCIx_TEI_IRQ] = { 1865 .desc = "tx end", 1866 .handler = sci_tx_interrupt, 1867 }, 1868 1869 /* 1870 * Special muxed handler. 1871 */ 1872 [SCIx_MUX_IRQ] = { 1873 .desc = "mux", 1874 .handler = sci_mpxed_interrupt, 1875 }, 1876 }; 1877 1878 static int sci_request_irq(struct sci_port *port) 1879 { 1880 struct uart_port *up = &port->port; 1881 int i, j, w, ret = 0; 1882 1883 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1884 const struct sci_irq_desc *desc; 1885 int irq; 1886 1887 /* Check if already registered (muxed) */ 1888 for (w = 0; w < i; w++) 1889 if (port->irqs[w] == port->irqs[i]) 1890 w = i + 1; 1891 if (w > i) 1892 continue; 1893 1894 if (SCIx_IRQ_IS_MUXED(port)) { 1895 i = SCIx_MUX_IRQ; 1896 irq = up->irq; 1897 } else { 1898 irq = port->irqs[i]; 1899 1900 /* 1901 * Certain port types won't support all of the 1902 * available interrupt sources. 1903 */ 1904 if (unlikely(irq < 0)) 1905 continue; 1906 } 1907 1908 desc = sci_irq_desc + i; 1909 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1910 dev_name(up->dev), desc->desc); 1911 if (!port->irqstr[j]) { 1912 ret = -ENOMEM; 1913 goto out_nomem; 1914 } 1915 1916 ret = request_irq(irq, desc->handler, up->irqflags, 1917 port->irqstr[j], port); 1918 if (unlikely(ret)) { 1919 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1920 goto out_noirq; 1921 } 1922 } 1923 1924 return 0; 1925 1926 out_noirq: 1927 while (--i >= 0) 1928 free_irq(port->irqs[i], port); 1929 1930 out_nomem: 1931 while (--j >= 0) 1932 kfree(port->irqstr[j]); 1933 1934 return ret; 1935 } 1936 1937 static void sci_free_irq(struct sci_port *port) 1938 { 1939 int i, j; 1940 1941 /* 1942 * Intentionally in reverse order so we iterate over the muxed 1943 * IRQ first. 1944 */ 1945 for (i = 0; i < SCIx_NR_IRQS; i++) { 1946 int irq = port->irqs[i]; 1947 1948 /* 1949 * Certain port types won't support all of the available 1950 * interrupt sources. 1951 */ 1952 if (unlikely(irq < 0)) 1953 continue; 1954 1955 /* Check if already freed (irq was muxed) */ 1956 for (j = 0; j < i; j++) 1957 if (port->irqs[j] == irq) 1958 j = i + 1; 1959 if (j > i) 1960 continue; 1961 1962 free_irq(port->irqs[i], port); 1963 kfree(port->irqstr[i]); 1964 1965 if (SCIx_IRQ_IS_MUXED(port)) { 1966 /* If there's only one IRQ, we're done. */ 1967 return; 1968 } 1969 } 1970 } 1971 1972 static unsigned int sci_tx_empty(struct uart_port *port) 1973 { 1974 unsigned short status = serial_port_in(port, SCxSR); 1975 unsigned short in_tx_fifo = sci_txfill(port); 1976 1977 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1978 } 1979 1980 static void sci_set_rts(struct uart_port *port, bool state) 1981 { 1982 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1983 u16 data = serial_port_in(port, SCPDR); 1984 1985 /* Active low */ 1986 if (state) 1987 data &= ~SCPDR_RTSD; 1988 else 1989 data |= SCPDR_RTSD; 1990 serial_port_out(port, SCPDR, data); 1991 1992 /* RTS# is output */ 1993 serial_port_out(port, SCPCR, 1994 serial_port_in(port, SCPCR) | SCPCR_RTSC); 1995 } else if (sci_getreg(port, SCSPTR)->size) { 1996 u16 ctrl = serial_port_in(port, SCSPTR); 1997 1998 /* Active low */ 1999 if (state) 2000 ctrl &= ~SCSPTR_RTSDT; 2001 else 2002 ctrl |= SCSPTR_RTSDT; 2003 serial_port_out(port, SCSPTR, ctrl); 2004 } 2005 } 2006 2007 static bool sci_get_cts(struct uart_port *port) 2008 { 2009 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2010 /* Active low */ 2011 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2012 } else if (sci_getreg(port, SCSPTR)->size) { 2013 /* Active low */ 2014 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2015 } 2016 2017 return true; 2018 } 2019 2020 /* 2021 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2022 * CTS/RTS is supported in hardware by at least one port and controlled 2023 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2024 * handled via the ->init_pins() op, which is a bit of a one-way street, 2025 * lacking any ability to defer pin control -- this will later be 2026 * converted over to the GPIO framework). 2027 * 2028 * Other modes (such as loopback) are supported generically on certain 2029 * port types, but not others. For these it's sufficient to test for the 2030 * existence of the support register and simply ignore the port type. 2031 */ 2032 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2033 { 2034 struct sci_port *s = to_sci_port(port); 2035 2036 if (mctrl & TIOCM_LOOP) { 2037 const struct plat_sci_reg *reg; 2038 2039 /* 2040 * Standard loopback mode for SCFCR ports. 2041 */ 2042 reg = sci_getreg(port, SCFCR); 2043 if (reg->size) 2044 serial_port_out(port, SCFCR, 2045 serial_port_in(port, SCFCR) | 2046 SCFCR_LOOP); 2047 } 2048 2049 mctrl_gpio_set(s->gpios, mctrl); 2050 2051 if (!s->has_rtscts) 2052 return; 2053 2054 if (!(mctrl & TIOCM_RTS)) { 2055 /* Disable Auto RTS */ 2056 serial_port_out(port, SCFCR, 2057 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2058 2059 /* Clear RTS */ 2060 sci_set_rts(port, 0); 2061 } else if (s->autorts) { 2062 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2063 /* Enable RTS# pin function */ 2064 serial_port_out(port, SCPCR, 2065 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2066 } 2067 2068 /* Enable Auto RTS */ 2069 serial_port_out(port, SCFCR, 2070 serial_port_in(port, SCFCR) | SCFCR_MCE); 2071 } else { 2072 /* Set RTS */ 2073 sci_set_rts(port, 1); 2074 } 2075 } 2076 2077 static unsigned int sci_get_mctrl(struct uart_port *port) 2078 { 2079 struct sci_port *s = to_sci_port(port); 2080 struct mctrl_gpios *gpios = s->gpios; 2081 unsigned int mctrl = 0; 2082 2083 mctrl_gpio_get(gpios, &mctrl); 2084 2085 /* 2086 * CTS/RTS is handled in hardware when supported, while nothing 2087 * else is wired up. 2088 */ 2089 if (s->autorts) { 2090 if (sci_get_cts(port)) 2091 mctrl |= TIOCM_CTS; 2092 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) { 2093 mctrl |= TIOCM_CTS; 2094 } 2095 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))) 2096 mctrl |= TIOCM_DSR; 2097 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))) 2098 mctrl |= TIOCM_CAR; 2099 2100 return mctrl; 2101 } 2102 2103 static void sci_enable_ms(struct uart_port *port) 2104 { 2105 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2106 } 2107 2108 static void sci_break_ctl(struct uart_port *port, int break_state) 2109 { 2110 unsigned short scscr, scsptr; 2111 unsigned long flags; 2112 2113 /* check wheter the port has SCSPTR */ 2114 if (!sci_getreg(port, SCSPTR)->size) { 2115 /* 2116 * Not supported by hardware. Most parts couple break and rx 2117 * interrupts together, with break detection always enabled. 2118 */ 2119 return; 2120 } 2121 2122 spin_lock_irqsave(&port->lock, flags); 2123 scsptr = serial_port_in(port, SCSPTR); 2124 scscr = serial_port_in(port, SCSCR); 2125 2126 if (break_state == -1) { 2127 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2128 scscr &= ~SCSCR_TE; 2129 } else { 2130 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2131 scscr |= SCSCR_TE; 2132 } 2133 2134 serial_port_out(port, SCSPTR, scsptr); 2135 serial_port_out(port, SCSCR, scscr); 2136 spin_unlock_irqrestore(&port->lock, flags); 2137 } 2138 2139 static int sci_startup(struct uart_port *port) 2140 { 2141 struct sci_port *s = to_sci_port(port); 2142 int ret; 2143 2144 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2145 2146 sci_request_dma(port); 2147 2148 ret = sci_request_irq(s); 2149 if (unlikely(ret < 0)) { 2150 sci_free_dma(port); 2151 return ret; 2152 } 2153 2154 return 0; 2155 } 2156 2157 static void sci_shutdown(struct uart_port *port) 2158 { 2159 struct sci_port *s = to_sci_port(port); 2160 unsigned long flags; 2161 u16 scr; 2162 2163 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2164 2165 s->autorts = false; 2166 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2167 2168 spin_lock_irqsave(&port->lock, flags); 2169 sci_stop_rx(port); 2170 sci_stop_tx(port); 2171 /* 2172 * Stop RX and TX, disable related interrupts, keep clock source 2173 * and HSCIF TOT bits 2174 */ 2175 scr = serial_port_in(port, SCSCR); 2176 serial_port_out(port, SCSCR, scr & 2177 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2178 spin_unlock_irqrestore(&port->lock, flags); 2179 2180 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2181 if (s->chan_rx_saved) { 2182 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2183 port->line); 2184 hrtimer_cancel(&s->rx_timer); 2185 } 2186 #endif 2187 2188 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2189 del_timer_sync(&s->rx_fifo_timer); 2190 sci_free_irq(s); 2191 sci_free_dma(port); 2192 } 2193 2194 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2195 unsigned int *srr) 2196 { 2197 unsigned long freq = s->clk_rates[SCI_SCK]; 2198 int err, min_err = INT_MAX; 2199 unsigned int sr; 2200 2201 if (s->port.type != PORT_HSCIF) 2202 freq *= 2; 2203 2204 for_each_sr(sr, s) { 2205 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2206 if (abs(err) >= abs(min_err)) 2207 continue; 2208 2209 min_err = err; 2210 *srr = sr - 1; 2211 2212 if (!err) 2213 break; 2214 } 2215 2216 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2217 *srr + 1); 2218 return min_err; 2219 } 2220 2221 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2222 unsigned long freq, unsigned int *dlr, 2223 unsigned int *srr) 2224 { 2225 int err, min_err = INT_MAX; 2226 unsigned int sr, dl; 2227 2228 if (s->port.type != PORT_HSCIF) 2229 freq *= 2; 2230 2231 for_each_sr(sr, s) { 2232 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2233 dl = clamp(dl, 1U, 65535U); 2234 2235 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2236 if (abs(err) >= abs(min_err)) 2237 continue; 2238 2239 min_err = err; 2240 *dlr = dl; 2241 *srr = sr - 1; 2242 2243 if (!err) 2244 break; 2245 } 2246 2247 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2248 min_err, *dlr, *srr + 1); 2249 return min_err; 2250 } 2251 2252 /* calculate sample rate, BRR, and clock select */ 2253 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2254 unsigned int *brr, unsigned int *srr, 2255 unsigned int *cks) 2256 { 2257 unsigned long freq = s->clk_rates[SCI_FCK]; 2258 unsigned int sr, br, prediv, scrate, c; 2259 int err, min_err = INT_MAX; 2260 2261 if (s->port.type != PORT_HSCIF) 2262 freq *= 2; 2263 2264 /* 2265 * Find the combination of sample rate and clock select with the 2266 * smallest deviation from the desired baud rate. 2267 * Prefer high sample rates to maximise the receive margin. 2268 * 2269 * M: Receive margin (%) 2270 * N: Ratio of bit rate to clock (N = sampling rate) 2271 * D: Clock duty (D = 0 to 1.0) 2272 * L: Frame length (L = 9 to 12) 2273 * F: Absolute value of clock frequency deviation 2274 * 2275 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2276 * (|D - 0.5| / N * (1 + F))| 2277 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2278 */ 2279 for_each_sr(sr, s) { 2280 for (c = 0; c <= 3; c++) { 2281 /* integerized formulas from HSCIF documentation */ 2282 prediv = sr * (1 << (2 * c + 1)); 2283 2284 /* 2285 * We need to calculate: 2286 * 2287 * br = freq / (prediv * bps) clamped to [1..256] 2288 * err = freq / (br * prediv) - bps 2289 * 2290 * Watch out for overflow when calculating the desired 2291 * sampling clock rate! 2292 */ 2293 if (bps > UINT_MAX / prediv) 2294 break; 2295 2296 scrate = prediv * bps; 2297 br = DIV_ROUND_CLOSEST(freq, scrate); 2298 br = clamp(br, 1U, 256U); 2299 2300 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2301 if (abs(err) >= abs(min_err)) 2302 continue; 2303 2304 min_err = err; 2305 *brr = br - 1; 2306 *srr = sr - 1; 2307 *cks = c; 2308 2309 if (!err) 2310 goto found; 2311 } 2312 } 2313 2314 found: 2315 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2316 min_err, *brr, *srr + 1, *cks); 2317 return min_err; 2318 } 2319 2320 static void sci_reset(struct uart_port *port) 2321 { 2322 const struct plat_sci_reg *reg; 2323 unsigned int status; 2324 struct sci_port *s = to_sci_port(port); 2325 2326 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2327 2328 reg = sci_getreg(port, SCFCR); 2329 if (reg->size) 2330 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2331 2332 sci_clear_SCxSR(port, 2333 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2334 SCxSR_BREAK_CLEAR(port)); 2335 if (sci_getreg(port, SCLSR)->size) { 2336 status = serial_port_in(port, SCLSR); 2337 status &= ~(SCLSR_TO | SCLSR_ORER); 2338 serial_port_out(port, SCLSR, status); 2339 } 2340 2341 if (s->rx_trigger > 1) { 2342 if (s->rx_fifo_timeout) { 2343 scif_set_rtrg(port, 1); 2344 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2345 } else { 2346 if (port->type == PORT_SCIFA || 2347 port->type == PORT_SCIFB) 2348 scif_set_rtrg(port, 1); 2349 else 2350 scif_set_rtrg(port, s->rx_trigger); 2351 } 2352 } 2353 } 2354 2355 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2356 struct ktermios *old) 2357 { 2358 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2359 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2360 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2361 struct sci_port *s = to_sci_port(port); 2362 const struct plat_sci_reg *reg; 2363 int min_err = INT_MAX, err; 2364 unsigned long max_freq = 0; 2365 int best_clk = -1; 2366 unsigned long flags; 2367 2368 if ((termios->c_cflag & CSIZE) == CS7) 2369 smr_val |= SCSMR_CHR; 2370 if (termios->c_cflag & PARENB) 2371 smr_val |= SCSMR_PE; 2372 if (termios->c_cflag & PARODD) 2373 smr_val |= SCSMR_PE | SCSMR_ODD; 2374 if (termios->c_cflag & CSTOPB) 2375 smr_val |= SCSMR_STOP; 2376 2377 /* 2378 * earlyprintk comes here early on with port->uartclk set to zero. 2379 * the clock framework is not up and running at this point so here 2380 * we assume that 115200 is the maximum baud rate. please note that 2381 * the baud rate is not programmed during earlyprintk - it is assumed 2382 * that the previous boot loader has enabled required clocks and 2383 * setup the baud rate generator hardware for us already. 2384 */ 2385 if (!port->uartclk) { 2386 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2387 goto done; 2388 } 2389 2390 for (i = 0; i < SCI_NUM_CLKS; i++) 2391 max_freq = max(max_freq, s->clk_rates[i]); 2392 2393 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2394 if (!baud) 2395 goto done; 2396 2397 /* 2398 * There can be multiple sources for the sampling clock. Find the one 2399 * that gives us the smallest deviation from the desired baud rate. 2400 */ 2401 2402 /* Optional Undivided External Clock */ 2403 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2404 port->type != PORT_SCIFB) { 2405 err = sci_sck_calc(s, baud, &srr1); 2406 if (abs(err) < abs(min_err)) { 2407 best_clk = SCI_SCK; 2408 scr_val = SCSCR_CKE1; 2409 sccks = SCCKS_CKS; 2410 min_err = err; 2411 srr = srr1; 2412 if (!err) 2413 goto done; 2414 } 2415 } 2416 2417 /* Optional BRG Frequency Divided External Clock */ 2418 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2419 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2420 &srr1); 2421 if (abs(err) < abs(min_err)) { 2422 best_clk = SCI_SCIF_CLK; 2423 scr_val = SCSCR_CKE1; 2424 sccks = 0; 2425 min_err = err; 2426 dl = dl1; 2427 srr = srr1; 2428 if (!err) 2429 goto done; 2430 } 2431 } 2432 2433 /* Optional BRG Frequency Divided Internal Clock */ 2434 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2435 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2436 &srr1); 2437 if (abs(err) < abs(min_err)) { 2438 best_clk = SCI_BRG_INT; 2439 scr_val = SCSCR_CKE1; 2440 sccks = SCCKS_XIN; 2441 min_err = err; 2442 dl = dl1; 2443 srr = srr1; 2444 if (!min_err) 2445 goto done; 2446 } 2447 } 2448 2449 /* Divided Functional Clock using standard Bit Rate Register */ 2450 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2451 if (abs(err) < abs(min_err)) { 2452 best_clk = SCI_FCK; 2453 scr_val = 0; 2454 min_err = err; 2455 brr = brr1; 2456 srr = srr1; 2457 cks = cks1; 2458 } 2459 2460 done: 2461 if (best_clk >= 0) 2462 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2463 s->clks[best_clk], baud, min_err); 2464 2465 sci_port_enable(s); 2466 2467 /* 2468 * Program the optional External Baud Rate Generator (BRG) first. 2469 * It controls the mux to select (H)SCK or frequency divided clock. 2470 */ 2471 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2472 serial_port_out(port, SCDL, dl); 2473 serial_port_out(port, SCCKS, sccks); 2474 } 2475 2476 spin_lock_irqsave(&port->lock, flags); 2477 2478 sci_reset(port); 2479 2480 uart_update_timeout(port, termios->c_cflag, baud); 2481 2482 /* byte size and parity */ 2483 switch (termios->c_cflag & CSIZE) { 2484 case CS5: 2485 bits = 7; 2486 break; 2487 case CS6: 2488 bits = 8; 2489 break; 2490 case CS7: 2491 bits = 9; 2492 break; 2493 default: 2494 bits = 10; 2495 break; 2496 } 2497 2498 if (termios->c_cflag & CSTOPB) 2499 bits++; 2500 if (termios->c_cflag & PARENB) 2501 bits++; 2502 2503 if (best_clk >= 0) { 2504 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2505 switch (srr + 1) { 2506 case 5: smr_val |= SCSMR_SRC_5; break; 2507 case 7: smr_val |= SCSMR_SRC_7; break; 2508 case 11: smr_val |= SCSMR_SRC_11; break; 2509 case 13: smr_val |= SCSMR_SRC_13; break; 2510 case 16: smr_val |= SCSMR_SRC_16; break; 2511 case 17: smr_val |= SCSMR_SRC_17; break; 2512 case 19: smr_val |= SCSMR_SRC_19; break; 2513 case 27: smr_val |= SCSMR_SRC_27; break; 2514 } 2515 smr_val |= cks; 2516 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2517 serial_port_out(port, SCSMR, smr_val); 2518 serial_port_out(port, SCBRR, brr); 2519 if (sci_getreg(port, HSSRR)->size) { 2520 unsigned int hssrr = srr | HSCIF_SRE; 2521 /* Calculate deviation from intended rate at the 2522 * center of the last stop bit in sampling clocks. 2523 */ 2524 int last_stop = bits * 2 - 1; 2525 int deviation = min_err * srr * last_stop / 2 / baud; 2526 2527 if (abs(deviation) >= 2) { 2528 /* At least two sampling clocks off at the 2529 * last stop bit; we can increase the error 2530 * margin by shifting the sampling point. 2531 */ 2532 int shift = min(-8, max(7, deviation / 2)); 2533 2534 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2535 HSCIF_SRHP_MASK; 2536 hssrr |= HSCIF_SRDE; 2537 } 2538 serial_port_out(port, HSSRR, hssrr); 2539 } 2540 2541 /* Wait one bit interval */ 2542 udelay((1000000 + (baud - 1)) / baud); 2543 } else { 2544 /* Don't touch the bit rate configuration */ 2545 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2546 smr_val |= serial_port_in(port, SCSMR) & 2547 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2548 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2549 serial_port_out(port, SCSMR, smr_val); 2550 } 2551 2552 sci_init_pins(port, termios->c_cflag); 2553 2554 port->status &= ~UPSTAT_AUTOCTS; 2555 s->autorts = false; 2556 reg = sci_getreg(port, SCFCR); 2557 if (reg->size) { 2558 unsigned short ctrl = serial_port_in(port, SCFCR); 2559 2560 if ((port->flags & UPF_HARD_FLOW) && 2561 (termios->c_cflag & CRTSCTS)) { 2562 /* There is no CTS interrupt to restart the hardware */ 2563 port->status |= UPSTAT_AUTOCTS; 2564 /* MCE is enabled when RTS is raised */ 2565 s->autorts = true; 2566 } 2567 2568 /* 2569 * As we've done a sci_reset() above, ensure we don't 2570 * interfere with the FIFOs while toggling MCE. As the 2571 * reset values could still be set, simply mask them out. 2572 */ 2573 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2574 2575 serial_port_out(port, SCFCR, ctrl); 2576 } 2577 if (port->flags & UPF_HARD_FLOW) { 2578 /* Refresh (Auto) RTS */ 2579 sci_set_mctrl(port, port->mctrl); 2580 } 2581 2582 scr_val |= SCSCR_RE | SCSCR_TE | 2583 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2584 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2585 if ((srr + 1 == 5) && 2586 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2587 /* 2588 * In asynchronous mode, when the sampling rate is 1/5, first 2589 * received data may become invalid on some SCIFA and SCIFB. 2590 * To avoid this problem wait more than 1 serial data time (1 2591 * bit time x serial data number) after setting SCSCR.RE = 1. 2592 */ 2593 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2594 } 2595 2596 /* 2597 * Calculate delay for 2 DMA buffers (4 FIFO). 2598 * See serial_core.c::uart_update_timeout(). 2599 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2600 * function calculates 1 jiffie for the data plus 5 jiffies for the 2601 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2602 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2603 * value obtained by this formula is too small. Therefore, if the value 2604 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2605 */ 2606 s->rx_frame = (10000 * bits) / (baud / 100); 2607 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2608 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2609 if (s->rx_timeout < 20) 2610 s->rx_timeout = 20; 2611 #endif 2612 2613 if ((termios->c_cflag & CREAD) != 0) 2614 sci_start_rx(port); 2615 2616 spin_unlock_irqrestore(&port->lock, flags); 2617 2618 sci_port_disable(s); 2619 2620 if (UART_ENABLE_MS(port, termios->c_cflag)) 2621 sci_enable_ms(port); 2622 } 2623 2624 static void sci_pm(struct uart_port *port, unsigned int state, 2625 unsigned int oldstate) 2626 { 2627 struct sci_port *sci_port = to_sci_port(port); 2628 2629 switch (state) { 2630 case UART_PM_STATE_OFF: 2631 sci_port_disable(sci_port); 2632 break; 2633 default: 2634 sci_port_enable(sci_port); 2635 break; 2636 } 2637 } 2638 2639 static const char *sci_type(struct uart_port *port) 2640 { 2641 switch (port->type) { 2642 case PORT_IRDA: 2643 return "irda"; 2644 case PORT_SCI: 2645 return "sci"; 2646 case PORT_SCIF: 2647 return "scif"; 2648 case PORT_SCIFA: 2649 return "scifa"; 2650 case PORT_SCIFB: 2651 return "scifb"; 2652 case PORT_HSCIF: 2653 return "hscif"; 2654 } 2655 2656 return NULL; 2657 } 2658 2659 static int sci_remap_port(struct uart_port *port) 2660 { 2661 struct sci_port *sport = to_sci_port(port); 2662 2663 /* 2664 * Nothing to do if there's already an established membase. 2665 */ 2666 if (port->membase) 2667 return 0; 2668 2669 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2670 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); 2671 if (unlikely(!port->membase)) { 2672 dev_err(port->dev, "can't remap port#%d\n", port->line); 2673 return -ENXIO; 2674 } 2675 } else { 2676 /* 2677 * For the simple (and majority of) cases where we don't 2678 * need to do any remapping, just cast the cookie 2679 * directly. 2680 */ 2681 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2682 } 2683 2684 return 0; 2685 } 2686 2687 static void sci_release_port(struct uart_port *port) 2688 { 2689 struct sci_port *sport = to_sci_port(port); 2690 2691 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2692 iounmap(port->membase); 2693 port->membase = NULL; 2694 } 2695 2696 release_mem_region(port->mapbase, sport->reg_size); 2697 } 2698 2699 static int sci_request_port(struct uart_port *port) 2700 { 2701 struct resource *res; 2702 struct sci_port *sport = to_sci_port(port); 2703 int ret; 2704 2705 res = request_mem_region(port->mapbase, sport->reg_size, 2706 dev_name(port->dev)); 2707 if (unlikely(res == NULL)) { 2708 dev_err(port->dev, "request_mem_region failed."); 2709 return -EBUSY; 2710 } 2711 2712 ret = sci_remap_port(port); 2713 if (unlikely(ret != 0)) { 2714 release_resource(res); 2715 return ret; 2716 } 2717 2718 return 0; 2719 } 2720 2721 static void sci_config_port(struct uart_port *port, int flags) 2722 { 2723 if (flags & UART_CONFIG_TYPE) { 2724 struct sci_port *sport = to_sci_port(port); 2725 2726 port->type = sport->cfg->type; 2727 sci_request_port(port); 2728 } 2729 } 2730 2731 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2732 { 2733 if (ser->baud_base < 2400) 2734 /* No paper tape reader for Mitch.. */ 2735 return -EINVAL; 2736 2737 return 0; 2738 } 2739 2740 static const struct uart_ops sci_uart_ops = { 2741 .tx_empty = sci_tx_empty, 2742 .set_mctrl = sci_set_mctrl, 2743 .get_mctrl = sci_get_mctrl, 2744 .start_tx = sci_start_tx, 2745 .stop_tx = sci_stop_tx, 2746 .stop_rx = sci_stop_rx, 2747 .enable_ms = sci_enable_ms, 2748 .break_ctl = sci_break_ctl, 2749 .startup = sci_startup, 2750 .shutdown = sci_shutdown, 2751 .flush_buffer = sci_flush_buffer, 2752 .set_termios = sci_set_termios, 2753 .pm = sci_pm, 2754 .type = sci_type, 2755 .release_port = sci_release_port, 2756 .request_port = sci_request_port, 2757 .config_port = sci_config_port, 2758 .verify_port = sci_verify_port, 2759 #ifdef CONFIG_CONSOLE_POLL 2760 .poll_get_char = sci_poll_get_char, 2761 .poll_put_char = sci_poll_put_char, 2762 #endif 2763 }; 2764 2765 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2766 { 2767 const char *clk_names[] = { 2768 [SCI_FCK] = "fck", 2769 [SCI_SCK] = "sck", 2770 [SCI_BRG_INT] = "brg_int", 2771 [SCI_SCIF_CLK] = "scif_clk", 2772 }; 2773 struct clk *clk; 2774 unsigned int i; 2775 2776 if (sci_port->cfg->type == PORT_HSCIF) 2777 clk_names[SCI_SCK] = "hsck"; 2778 2779 for (i = 0; i < SCI_NUM_CLKS; i++) { 2780 clk = devm_clk_get(dev, clk_names[i]); 2781 if (PTR_ERR(clk) == -EPROBE_DEFER) 2782 return -EPROBE_DEFER; 2783 2784 if (IS_ERR(clk) && i == SCI_FCK) { 2785 /* 2786 * "fck" used to be called "sci_ick", and we need to 2787 * maintain DT backward compatibility. 2788 */ 2789 clk = devm_clk_get(dev, "sci_ick"); 2790 if (PTR_ERR(clk) == -EPROBE_DEFER) 2791 return -EPROBE_DEFER; 2792 2793 if (!IS_ERR(clk)) 2794 goto found; 2795 2796 /* 2797 * Not all SH platforms declare a clock lookup entry 2798 * for SCI devices, in which case we need to get the 2799 * global "peripheral_clk" clock. 2800 */ 2801 clk = devm_clk_get(dev, "peripheral_clk"); 2802 if (!IS_ERR(clk)) 2803 goto found; 2804 2805 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2806 PTR_ERR(clk)); 2807 return PTR_ERR(clk); 2808 } 2809 2810 found: 2811 if (IS_ERR(clk)) 2812 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2813 PTR_ERR(clk)); 2814 else 2815 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2816 clk, clk_get_rate(clk)); 2817 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2818 } 2819 return 0; 2820 } 2821 2822 static const struct sci_port_params * 2823 sci_probe_regmap(const struct plat_sci_port *cfg) 2824 { 2825 unsigned int regtype; 2826 2827 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2828 return &sci_port_params[cfg->regtype]; 2829 2830 switch (cfg->type) { 2831 case PORT_SCI: 2832 regtype = SCIx_SCI_REGTYPE; 2833 break; 2834 case PORT_IRDA: 2835 regtype = SCIx_IRDA_REGTYPE; 2836 break; 2837 case PORT_SCIFA: 2838 regtype = SCIx_SCIFA_REGTYPE; 2839 break; 2840 case PORT_SCIFB: 2841 regtype = SCIx_SCIFB_REGTYPE; 2842 break; 2843 case PORT_SCIF: 2844 /* 2845 * The SH-4 is a bit of a misnomer here, although that's 2846 * where this particular port layout originated. This 2847 * configuration (or some slight variation thereof) 2848 * remains the dominant model for all SCIFs. 2849 */ 2850 regtype = SCIx_SH4_SCIF_REGTYPE; 2851 break; 2852 case PORT_HSCIF: 2853 regtype = SCIx_HSCIF_REGTYPE; 2854 break; 2855 default: 2856 pr_err("Can't probe register map for given port\n"); 2857 return NULL; 2858 } 2859 2860 return &sci_port_params[regtype]; 2861 } 2862 2863 static int sci_init_single(struct platform_device *dev, 2864 struct sci_port *sci_port, unsigned int index, 2865 const struct plat_sci_port *p, bool early) 2866 { 2867 struct uart_port *port = &sci_port->port; 2868 const struct resource *res; 2869 unsigned int i; 2870 int ret; 2871 2872 sci_port->cfg = p; 2873 2874 port->ops = &sci_uart_ops; 2875 port->iotype = UPIO_MEM; 2876 port->line = index; 2877 2878 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2879 if (res == NULL) 2880 return -ENOMEM; 2881 2882 port->mapbase = res->start; 2883 sci_port->reg_size = resource_size(res); 2884 2885 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2886 sci_port->irqs[i] = platform_get_irq(dev, i); 2887 2888 /* The SCI generates several interrupts. They can be muxed together or 2889 * connected to different interrupt lines. In the muxed case only one 2890 * interrupt resource is specified as there is only one interrupt ID. 2891 * In the non-muxed case, up to 6 interrupt signals might be generated 2892 * from the SCI, however those signals might have their own individual 2893 * interrupt ID numbers, or muxed together with another interrupt. 2894 */ 2895 if (sci_port->irqs[0] < 0) 2896 return -ENXIO; 2897 2898 if (sci_port->irqs[1] < 0) 2899 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2900 sci_port->irqs[i] = sci_port->irqs[0]; 2901 2902 sci_port->params = sci_probe_regmap(p); 2903 if (unlikely(sci_port->params == NULL)) 2904 return -EINVAL; 2905 2906 switch (p->type) { 2907 case PORT_SCIFB: 2908 sci_port->rx_trigger = 48; 2909 break; 2910 case PORT_HSCIF: 2911 sci_port->rx_trigger = 64; 2912 break; 2913 case PORT_SCIFA: 2914 sci_port->rx_trigger = 32; 2915 break; 2916 case PORT_SCIF: 2917 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2918 /* RX triggering not implemented for this IP */ 2919 sci_port->rx_trigger = 1; 2920 else 2921 sci_port->rx_trigger = 8; 2922 break; 2923 default: 2924 sci_port->rx_trigger = 1; 2925 break; 2926 } 2927 2928 sci_port->rx_fifo_timeout = 0; 2929 sci_port->hscif_tot = 0; 2930 2931 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2932 * match the SoC datasheet, this should be investigated. Let platform 2933 * data override the sampling rate for now. 2934 */ 2935 sci_port->sampling_rate_mask = p->sampling_rate 2936 ? SCI_SR(p->sampling_rate) 2937 : sci_port->params->sampling_rate_mask; 2938 2939 if (!early) { 2940 ret = sci_init_clocks(sci_port, &dev->dev); 2941 if (ret < 0) 2942 return ret; 2943 2944 port->dev = &dev->dev; 2945 2946 pm_runtime_enable(&dev->dev); 2947 } 2948 2949 port->type = p->type; 2950 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2951 port->fifosize = sci_port->params->fifosize; 2952 2953 if (port->type == PORT_SCI) { 2954 if (sci_port->reg_size >= 0x20) 2955 port->regshift = 2; 2956 else 2957 port->regshift = 1; 2958 } 2959 2960 /* 2961 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2962 * for the multi-IRQ ports, which is where we are primarily 2963 * concerned with the shutdown path synchronization. 2964 * 2965 * For the muxed case there's nothing more to do. 2966 */ 2967 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2968 port->irqflags = 0; 2969 2970 port->serial_in = sci_serial_in; 2971 port->serial_out = sci_serial_out; 2972 2973 return 0; 2974 } 2975 2976 static void sci_cleanup_single(struct sci_port *port) 2977 { 2978 pm_runtime_disable(port->port.dev); 2979 } 2980 2981 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2982 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2983 static void serial_console_putchar(struct uart_port *port, int ch) 2984 { 2985 sci_poll_put_char(port, ch); 2986 } 2987 2988 /* 2989 * Print a string to the serial port trying not to disturb 2990 * any possible real use of the port... 2991 */ 2992 static void serial_console_write(struct console *co, const char *s, 2993 unsigned count) 2994 { 2995 struct sci_port *sci_port = &sci_ports[co->index]; 2996 struct uart_port *port = &sci_port->port; 2997 unsigned short bits, ctrl, ctrl_temp; 2998 unsigned long flags; 2999 int locked = 1; 3000 3001 #if defined(SUPPORT_SYSRQ) 3002 if (port->sysrq) 3003 locked = 0; 3004 else 3005 #endif 3006 if (oops_in_progress) 3007 locked = spin_trylock_irqsave(&port->lock, flags); 3008 else 3009 spin_lock_irqsave(&port->lock, flags); 3010 3011 /* first save SCSCR then disable interrupts, keep clock source */ 3012 ctrl = serial_port_in(port, SCSCR); 3013 ctrl_temp = SCSCR_RE | SCSCR_TE | 3014 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3015 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3016 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3017 3018 uart_console_write(port, s, count, serial_console_putchar); 3019 3020 /* wait until fifo is empty and last bit has been transmitted */ 3021 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3022 while ((serial_port_in(port, SCxSR) & bits) != bits) 3023 cpu_relax(); 3024 3025 /* restore the SCSCR */ 3026 serial_port_out(port, SCSCR, ctrl); 3027 3028 if (locked) 3029 spin_unlock_irqrestore(&port->lock, flags); 3030 } 3031 3032 static int serial_console_setup(struct console *co, char *options) 3033 { 3034 struct sci_port *sci_port; 3035 struct uart_port *port; 3036 int baud = 115200; 3037 int bits = 8; 3038 int parity = 'n'; 3039 int flow = 'n'; 3040 int ret; 3041 3042 /* 3043 * Refuse to handle any bogus ports. 3044 */ 3045 if (co->index < 0 || co->index >= SCI_NPORTS) 3046 return -ENODEV; 3047 3048 sci_port = &sci_ports[co->index]; 3049 port = &sci_port->port; 3050 3051 /* 3052 * Refuse to handle uninitialized ports. 3053 */ 3054 if (!port->ops) 3055 return -ENODEV; 3056 3057 ret = sci_remap_port(port); 3058 if (unlikely(ret != 0)) 3059 return ret; 3060 3061 if (options) 3062 uart_parse_options(options, &baud, &parity, &bits, &flow); 3063 3064 return uart_set_options(port, co, baud, parity, bits, flow); 3065 } 3066 3067 static struct console serial_console = { 3068 .name = "ttySC", 3069 .device = uart_console_device, 3070 .write = serial_console_write, 3071 .setup = serial_console_setup, 3072 .flags = CON_PRINTBUFFER, 3073 .index = -1, 3074 .data = &sci_uart_driver, 3075 }; 3076 3077 static struct console early_serial_console = { 3078 .name = "early_ttySC", 3079 .write = serial_console_write, 3080 .flags = CON_PRINTBUFFER, 3081 .index = -1, 3082 }; 3083 3084 static char early_serial_buf[32]; 3085 3086 static int sci_probe_earlyprintk(struct platform_device *pdev) 3087 { 3088 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3089 3090 if (early_serial_console.data) 3091 return -EEXIST; 3092 3093 early_serial_console.index = pdev->id; 3094 3095 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3096 3097 serial_console_setup(&early_serial_console, early_serial_buf); 3098 3099 if (!strstr(early_serial_buf, "keep")) 3100 early_serial_console.flags |= CON_BOOT; 3101 3102 register_console(&early_serial_console); 3103 return 0; 3104 } 3105 3106 #define SCI_CONSOLE (&serial_console) 3107 3108 #else 3109 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3110 { 3111 return -EINVAL; 3112 } 3113 3114 #define SCI_CONSOLE NULL 3115 3116 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3117 3118 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3119 3120 static DEFINE_MUTEX(sci_uart_registration_lock); 3121 static struct uart_driver sci_uart_driver = { 3122 .owner = THIS_MODULE, 3123 .driver_name = "sci", 3124 .dev_name = "ttySC", 3125 .major = SCI_MAJOR, 3126 .minor = SCI_MINOR_START, 3127 .nr = SCI_NPORTS, 3128 .cons = SCI_CONSOLE, 3129 }; 3130 3131 static int sci_remove(struct platform_device *dev) 3132 { 3133 struct sci_port *port = platform_get_drvdata(dev); 3134 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3135 3136 sci_ports_in_use &= ~BIT(port->port.line); 3137 uart_remove_one_port(&sci_uart_driver, &port->port); 3138 3139 sci_cleanup_single(port); 3140 3141 if (port->port.fifosize > 1) { 3142 sysfs_remove_file(&dev->dev.kobj, 3143 &dev_attr_rx_fifo_trigger.attr); 3144 } 3145 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) { 3146 sysfs_remove_file(&dev->dev.kobj, 3147 &dev_attr_rx_fifo_timeout.attr); 3148 } 3149 3150 return 0; 3151 } 3152 3153 3154 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3155 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3156 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3157 3158 static const struct of_device_id of_sci_match[] = { 3159 /* SoC-specific types */ 3160 { 3161 .compatible = "renesas,scif-r7s72100", 3162 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3163 }, 3164 { 3165 .compatible = "renesas,scif-r7s9210", 3166 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3167 }, 3168 /* Family-specific types */ 3169 { 3170 .compatible = "renesas,rcar-gen1-scif", 3171 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3172 }, { 3173 .compatible = "renesas,rcar-gen2-scif", 3174 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3175 }, { 3176 .compatible = "renesas,rcar-gen3-scif", 3177 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3178 }, 3179 /* Generic types */ 3180 { 3181 .compatible = "renesas,scif", 3182 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3183 }, { 3184 .compatible = "renesas,scifa", 3185 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3186 }, { 3187 .compatible = "renesas,scifb", 3188 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3189 }, { 3190 .compatible = "renesas,hscif", 3191 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3192 }, { 3193 .compatible = "renesas,sci", 3194 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3195 }, { 3196 /* Terminator */ 3197 }, 3198 }; 3199 MODULE_DEVICE_TABLE(of, of_sci_match); 3200 3201 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3202 unsigned int *dev_id) 3203 { 3204 struct device_node *np = pdev->dev.of_node; 3205 struct plat_sci_port *p; 3206 struct sci_port *sp; 3207 const void *data; 3208 int id; 3209 3210 if (!IS_ENABLED(CONFIG_OF) || !np) 3211 return NULL; 3212 3213 data = of_device_get_match_data(&pdev->dev); 3214 3215 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3216 if (!p) 3217 return NULL; 3218 3219 /* Get the line number from the aliases node. */ 3220 id = of_alias_get_id(np, "serial"); 3221 if (id < 0 && ~sci_ports_in_use) 3222 id = ffz(sci_ports_in_use); 3223 if (id < 0) { 3224 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3225 return NULL; 3226 } 3227 if (id >= ARRAY_SIZE(sci_ports)) { 3228 dev_err(&pdev->dev, "serial%d out of range\n", id); 3229 return NULL; 3230 } 3231 3232 sp = &sci_ports[id]; 3233 *dev_id = id; 3234 3235 p->type = SCI_OF_TYPE(data); 3236 p->regtype = SCI_OF_REGTYPE(data); 3237 3238 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3239 3240 return p; 3241 } 3242 3243 static int sci_probe_single(struct platform_device *dev, 3244 unsigned int index, 3245 struct plat_sci_port *p, 3246 struct sci_port *sciport) 3247 { 3248 int ret; 3249 3250 /* Sanity check */ 3251 if (unlikely(index >= SCI_NPORTS)) { 3252 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3253 index+1, SCI_NPORTS); 3254 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3255 return -EINVAL; 3256 } 3257 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3258 if (sci_ports_in_use & BIT(index)) 3259 return -EBUSY; 3260 3261 mutex_lock(&sci_uart_registration_lock); 3262 if (!sci_uart_driver.state) { 3263 ret = uart_register_driver(&sci_uart_driver); 3264 if (ret) { 3265 mutex_unlock(&sci_uart_registration_lock); 3266 return ret; 3267 } 3268 } 3269 mutex_unlock(&sci_uart_registration_lock); 3270 3271 ret = sci_init_single(dev, sciport, index, p, false); 3272 if (ret) 3273 return ret; 3274 3275 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3276 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS) 3277 return PTR_ERR(sciport->gpios); 3278 3279 if (sciport->has_rtscts) { 3280 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3281 UART_GPIO_CTS)) || 3282 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios, 3283 UART_GPIO_RTS))) { 3284 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3285 return -EINVAL; 3286 } 3287 sciport->port.flags |= UPF_HARD_FLOW; 3288 } 3289 3290 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3291 if (ret) { 3292 sci_cleanup_single(sciport); 3293 return ret; 3294 } 3295 3296 return 0; 3297 } 3298 3299 static int sci_probe(struct platform_device *dev) 3300 { 3301 struct plat_sci_port *p; 3302 struct sci_port *sp; 3303 unsigned int dev_id; 3304 int ret; 3305 3306 /* 3307 * If we've come here via earlyprintk initialization, head off to 3308 * the special early probe. We don't have sufficient device state 3309 * to make it beyond this yet. 3310 */ 3311 if (is_early_platform_device(dev)) 3312 return sci_probe_earlyprintk(dev); 3313 3314 if (dev->dev.of_node) { 3315 p = sci_parse_dt(dev, &dev_id); 3316 if (p == NULL) 3317 return -EINVAL; 3318 } else { 3319 p = dev->dev.platform_data; 3320 if (p == NULL) { 3321 dev_err(&dev->dev, "no platform data supplied\n"); 3322 return -EINVAL; 3323 } 3324 3325 dev_id = dev->id; 3326 } 3327 3328 sp = &sci_ports[dev_id]; 3329 platform_set_drvdata(dev, sp); 3330 3331 ret = sci_probe_single(dev, dev_id, p, sp); 3332 if (ret) 3333 return ret; 3334 3335 if (sp->port.fifosize > 1) { 3336 ret = sysfs_create_file(&dev->dev.kobj, 3337 &dev_attr_rx_fifo_trigger.attr); 3338 if (ret) 3339 return ret; 3340 } 3341 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3342 sp->port.type == PORT_HSCIF) { 3343 ret = sysfs_create_file(&dev->dev.kobj, 3344 &dev_attr_rx_fifo_timeout.attr); 3345 if (ret) { 3346 if (sp->port.fifosize > 1) { 3347 sysfs_remove_file(&dev->dev.kobj, 3348 &dev_attr_rx_fifo_trigger.attr); 3349 } 3350 return ret; 3351 } 3352 } 3353 3354 #ifdef CONFIG_SH_STANDARD_BIOS 3355 sh_bios_gdb_detach(); 3356 #endif 3357 3358 sci_ports_in_use |= BIT(dev_id); 3359 return 0; 3360 } 3361 3362 static __maybe_unused int sci_suspend(struct device *dev) 3363 { 3364 struct sci_port *sport = dev_get_drvdata(dev); 3365 3366 if (sport) 3367 uart_suspend_port(&sci_uart_driver, &sport->port); 3368 3369 return 0; 3370 } 3371 3372 static __maybe_unused int sci_resume(struct device *dev) 3373 { 3374 struct sci_port *sport = dev_get_drvdata(dev); 3375 3376 if (sport) 3377 uart_resume_port(&sci_uart_driver, &sport->port); 3378 3379 return 0; 3380 } 3381 3382 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3383 3384 static struct platform_driver sci_driver = { 3385 .probe = sci_probe, 3386 .remove = sci_remove, 3387 .driver = { 3388 .name = "sh-sci", 3389 .pm = &sci_dev_pm_ops, 3390 .of_match_table = of_match_ptr(of_sci_match), 3391 }, 3392 }; 3393 3394 static int __init sci_init(void) 3395 { 3396 pr_info("%s\n", banner); 3397 3398 return platform_driver_register(&sci_driver); 3399 } 3400 3401 static void __exit sci_exit(void) 3402 { 3403 platform_driver_unregister(&sci_driver); 3404 3405 if (sci_uart_driver.state) 3406 uart_unregister_driver(&sci_uart_driver); 3407 } 3408 3409 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 3410 early_platform_init_buffer("earlyprintk", &sci_driver, 3411 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3412 #endif 3413 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3414 static struct plat_sci_port port_cfg __initdata; 3415 3416 static int __init early_console_setup(struct earlycon_device *device, 3417 int type) 3418 { 3419 if (!device->port.membase) 3420 return -ENODEV; 3421 3422 device->port.serial_in = sci_serial_in; 3423 device->port.serial_out = sci_serial_out; 3424 device->port.type = type; 3425 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3426 port_cfg.type = type; 3427 sci_ports[0].cfg = &port_cfg; 3428 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3429 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3430 sci_serial_out(&sci_ports[0].port, SCSCR, 3431 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3432 3433 device->con->write = serial_console_write; 3434 return 0; 3435 } 3436 static int __init sci_early_console_setup(struct earlycon_device *device, 3437 const char *opt) 3438 { 3439 return early_console_setup(device, PORT_SCI); 3440 } 3441 static int __init scif_early_console_setup(struct earlycon_device *device, 3442 const char *opt) 3443 { 3444 return early_console_setup(device, PORT_SCIF); 3445 } 3446 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3447 const char *opt) 3448 { 3449 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3450 return early_console_setup(device, PORT_SCIF); 3451 } 3452 static int __init scifa_early_console_setup(struct earlycon_device *device, 3453 const char *opt) 3454 { 3455 return early_console_setup(device, PORT_SCIFA); 3456 } 3457 static int __init scifb_early_console_setup(struct earlycon_device *device, 3458 const char *opt) 3459 { 3460 return early_console_setup(device, PORT_SCIFB); 3461 } 3462 static int __init hscif_early_console_setup(struct earlycon_device *device, 3463 const char *opt) 3464 { 3465 return early_console_setup(device, PORT_HSCIF); 3466 } 3467 3468 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3469 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3470 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3471 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3472 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3473 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3474 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3475 3476 module_init(sci_init); 3477 module_exit(sci_exit); 3478 3479 MODULE_LICENSE("GPL"); 3480 MODULE_ALIAS("platform:sh-sci"); 3481 MODULE_AUTHOR("Paul Mundt"); 3482 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3483