1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/bitops.h> 21 #include <linux/clk.h> 22 #include <linux/console.h> 23 #include <linux/cpufreq.h> 24 #include <linux/ctype.h> 25 #include <linux/delay.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/dmaengine.h> 28 #include <linux/err.h> 29 #include <linux/errno.h> 30 #include <linux/init.h> 31 #include <linux/interrupt.h> 32 #include <linux/io.h> 33 #include <linux/ioport.h> 34 #include <linux/ktime.h> 35 #include <linux/major.h> 36 #include <linux/minmax.h> 37 #include <linux/mm.h> 38 #include <linux/module.h> 39 #include <linux/of.h> 40 #include <linux/platform_device.h> 41 #include <linux/pm_runtime.h> 42 #include <linux/reset.h> 43 #include <linux/scatterlist.h> 44 #include <linux/serial.h> 45 #include <linux/serial_core.h> 46 #include <linux/serial_sci.h> 47 #include <linux/sh_dma.h> 48 #include <linux/slab.h> 49 #include <linux/string.h> 50 #include <linux/sysrq.h> 51 #include <linux/timer.h> 52 #include <linux/tty.h> 53 #include <linux/tty_flip.h> 54 55 #ifdef CONFIG_SUPERH 56 #include <asm/platform_early.h> 57 #include <asm/sh_bios.h> 58 #endif 59 60 #include "rsci.h" 61 #include "serial_mctrl_gpio.h" 62 #include "sh-sci-common.h" 63 64 #define SCI_MAJOR 204 65 #define SCI_MINOR_START 8 66 67 /* 68 * SCI register subset common for all port types. 69 * Not all registers will exist on all parts. 70 */ 71 enum { 72 SCSMR, /* Serial Mode Register */ 73 SCBRR, /* Bit Rate Register */ 74 SCSCR, /* Serial Control Register */ 75 SCxSR, /* Serial Status Register */ 76 SCFCR, /* FIFO Control Register */ 77 SCFDR, /* FIFO Data Count Register */ 78 SCxTDR, /* Transmit (FIFO) Data Register */ 79 SCxRDR, /* Receive (FIFO) Data Register */ 80 SCLSR, /* Line Status Register */ 81 SCTFDR, /* Transmit FIFO Data Count Register */ 82 SCRFDR, /* Receive FIFO Data Count Register */ 83 SCSPTR, /* Serial Port Register */ 84 HSSRR, /* Sampling Rate Register */ 85 SCPCR, /* Serial Port Control Register */ 86 SCPDR, /* Serial Port Data Register */ 87 SCDL, /* BRG Frequency Division Register */ 88 SCCKS, /* BRG Clock Select Register */ 89 HSRTRGR, /* Rx FIFO Data Count Trigger Register */ 90 HSTTRGR, /* Tx FIFO Data Count Trigger Register */ 91 SEMR, /* Serial extended mode register */ 92 }; 93 94 /* SCSMR (Serial Mode Register) */ 95 #define SCSMR_C_A BIT(7) /* Communication Mode */ 96 #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */ 97 #define SCSMR_ASYNC 0 /* - Asynchronous mode */ 98 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */ 99 #define SCSMR_PE BIT(5) /* Parity Enable */ 100 #define SCSMR_ODD BIT(4) /* Odd Parity */ 101 #define SCSMR_STOP BIT(3) /* Stop Bit Length */ 102 #define SCSMR_CKS 0x0003 /* Clock Select */ 103 104 /* Serial Mode Register, SCIFA/SCIFB only bits */ 105 #define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */ 106 #define SCSMR_SRC_MASK 0x0700 /* Sampling Control */ 107 #define SCSMR_SRC_16 0x0000 /* Sampling rate 1/16 */ 108 #define SCSMR_SRC_5 0x0100 /* Sampling rate 1/5 */ 109 #define SCSMR_SRC_7 0x0200 /* Sampling rate 1/7 */ 110 #define SCSMR_SRC_11 0x0300 /* Sampling rate 1/11 */ 111 #define SCSMR_SRC_13 0x0400 /* Sampling rate 1/13 */ 112 #define SCSMR_SRC_17 0x0500 /* Sampling rate 1/17 */ 113 #define SCSMR_SRC_19 0x0600 /* Sampling rate 1/19 */ 114 #define SCSMR_SRC_27 0x0700 /* Sampling rate 1/27 */ 115 116 /* Serial Control Register, SCI only bits */ 117 #define SCSCR_TEIE BIT(2) /* Transmit End Interrupt Enable */ 118 119 /* Serial Control Register, SCIFA/SCIFB only bits */ 120 #define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */ 121 #define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */ 122 123 /* Serial Control Register, HSCIF-only bits */ 124 #define HSSCR_TOT_SHIFT 14 125 126 /* SCxSR (Serial Status Register) on SCI */ 127 #define SCI_TDRE BIT(7) /* Transmit Data Register Empty */ 128 #define SCI_RDRF BIT(6) /* Receive Data Register Full */ 129 #define SCI_ORER BIT(5) /* Overrun Error */ 130 #define SCI_FER BIT(4) /* Framing Error */ 131 #define SCI_PER BIT(3) /* Parity Error */ 132 #define SCI_TEND BIT(2) /* Transmit End */ 133 #define SCI_RESERVED 0x03 /* All reserved bits */ 134 135 #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER) 136 137 #define SCI_RDxF_CLEAR (u32)(~(SCI_RESERVED | SCI_RDRF)) 138 #define SCI_ERROR_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)) 139 #define SCI_TDxE_CLEAR (u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE)) 140 #define SCI_BREAK_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)) 141 142 /* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */ 143 #define SCIF_ER BIT(7) /* Receive Error */ 144 #define SCIF_TEND BIT(6) /* Transmission End */ 145 #define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */ 146 #define SCIF_BRK BIT(4) /* Break Detect */ 147 #define SCIF_FER BIT(3) /* Framing Error */ 148 #define SCIF_PER BIT(2) /* Parity Error */ 149 #define SCIF_RDF BIT(1) /* Receive FIFO Data Full */ 150 #define SCIF_DR BIT(0) /* Receive Data Ready */ 151 /* SCIF only (optional) */ 152 #define SCIF_PERC 0xf000 /* Number of Parity Errors */ 153 #define SCIF_FERC 0x0f00 /* Number of Framing Errors */ 154 /*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */ 155 #define SCIFA_ORER BIT(9) /* Overrun Error */ 156 157 #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER) 158 159 #define SCIF_RDxF_CLEAR (u32)(~(SCIF_DR | SCIF_RDF)) 160 #define SCIF_ERROR_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_ER)) 161 #define SCIF_TDxE_CLEAR (u32)(~(SCIF_TDFE)) 162 #define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK)) 163 164 /* SCFCR (FIFO Control Register) */ 165 #define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */ 166 #define SCFCR_RTRG0 BIT(6) 167 #define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */ 168 #define SCFCR_TTRG0 BIT(4) 169 #define SCFCR_MCE BIT(3) /* Modem Control Enable */ 170 #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */ 171 #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */ 172 #define SCFCR_LOOP BIT(0) /* Loopback Test */ 173 174 /* SCLSR (Line Status Register) on (H)SCIF */ 175 #define SCLSR_TO BIT(2) /* Timeout */ 176 #define SCLSR_ORER BIT(0) /* Overrun Error */ 177 178 /* SCSPTR (Serial Port Register), optional */ 179 #define SCSPTR_RTSIO BIT(7) /* Serial Port RTS# Pin Input/Output */ 180 #define SCSPTR_RTSDT BIT(6) /* Serial Port RTS# Pin Data */ 181 #define SCSPTR_CTSIO BIT(5) /* Serial Port CTS# Pin Input/Output */ 182 #define SCSPTR_CTSDT BIT(4) /* Serial Port CTS# Pin Data */ 183 #define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */ 184 #define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */ 185 #define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */ 186 #define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */ 187 188 /* HSSRR HSCIF */ 189 #define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */ 190 #define HSCIF_SRDE BIT(14) /* Sampling Point Register Enable */ 191 192 #define HSCIF_SRHP_SHIFT 8 193 #define HSCIF_SRHP_MASK 0x0f00 194 195 /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */ 196 #define SCPCR_RTSC BIT(4) /* Serial Port RTS# Pin / Output Pin */ 197 #define SCPCR_CTSC BIT(3) /* Serial Port CTS# Pin / Input Pin */ 198 #define SCPCR_SCKC BIT(2) /* Serial Port SCK Pin / Output Pin */ 199 #define SCPCR_RXDC BIT(1) /* Serial Port RXD Pin / Input Pin */ 200 #define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */ 201 202 /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */ 203 #define SCPDR_RTSD BIT(4) /* Serial Port RTS# Output Pin Data */ 204 #define SCPDR_CTSD BIT(3) /* Serial Port CTS# Input Pin Data */ 205 #define SCPDR_SCKD BIT(2) /* Serial Port SCK Output Pin Data */ 206 #define SCPDR_RXDD BIT(1) /* Serial Port RXD Input Pin Data */ 207 #define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */ 208 209 /* 210 * BRG Clock Select Register (Some SCIF and HSCIF) 211 * The Baud Rate Generator for external clock can provide a clock source for 212 * the sampling clock. It outputs either its frequency divided clock, or the 213 * (undivided) (H)SCK external clock. 214 */ 215 #define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */ 216 #define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */ 217 218 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 219 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF) 220 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 221 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 222 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 223 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 224 225 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask) 226 227 #define SCxSR_RDxF_CLEAR(port) \ 228 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR) 229 #define SCxSR_ERROR_CLEAR(port) \ 230 (to_sci_port(port)->params->error_clear) 231 #define SCxSR_TDxE_CLEAR(port) \ 232 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR) 233 #define SCxSR_BREAK_CLEAR(port) \ 234 (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR) 235 236 #define SCIx_IRQ_IS_MUXED(port) \ 237 ((port)->irqs[SCIx_ERI_IRQ] == \ 238 (port)->irqs[SCIx_RXI_IRQ]) || \ 239 ((port)->irqs[SCIx_ERI_IRQ] && \ 240 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 241 242 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 243 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 244 SCI_SR(19) | SCI_SR(27) 245 246 /* Iterate over all supported sampling rates, from high to low */ 247 #define for_each_sr(_sr, _port) \ 248 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 249 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 250 251 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 252 253 #define SCI_PUBLIC_PORT_ID(port) (((port) & BIT(7)) ? PORT_GENERIC : (port)) 254 255 static struct sci_port sci_ports[SCI_NPORTS]; 256 static unsigned long sci_ports_in_use; 257 static struct uart_driver sci_uart_driver; 258 static bool sci_uart_earlycon; 259 static bool sci_uart_earlycon_dev_probing; 260 261 static const struct sci_port_params_bits sci_sci_port_params_bits = { 262 .rxtx_enable = SCSCR_RE | SCSCR_TE, 263 .te_clear = SCSCR_TE | SCSCR_TEIE, 264 .poll_sent_bits = SCI_TDRE | SCI_TEND 265 }; 266 267 static const struct sci_port_params_bits sci_scif_port_params_bits = { 268 .rxtx_enable = SCSCR_RE | SCSCR_TE, 269 .te_clear = SCSCR_TE | SCSCR_TEIE, 270 .poll_sent_bits = SCIF_TDFE | SCIF_TEND 271 }; 272 273 static const struct sci_common_regs sci_common_regs = { 274 .status = SCxSR, 275 .control = SCSCR, 276 }; 277 278 struct sci_suspend_regs { 279 u16 scdl; 280 u16 sccks; 281 u16 scsmr; 282 u16 scscr; 283 u16 scfcr; 284 u16 scsptr; 285 u16 hssrr; 286 u16 scpcr; 287 u16 scpdr; 288 u8 scbrr; 289 u8 semr; 290 }; 291 292 static size_t sci_suspend_regs_size(void) 293 { 294 return sizeof(struct sci_suspend_regs); 295 } 296 297 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 298 /* 299 * Common SCI definitions, dependent on the port's regshift 300 * value. 301 */ 302 [SCIx_SCI_REGTYPE] = { 303 .regs = { 304 [SCSMR] = { 0x00, 8 }, 305 [SCBRR] = { 0x01, 8 }, 306 [SCSCR] = { 0x02, 8 }, 307 [SCxTDR] = { 0x03, 8 }, 308 [SCxSR] = { 0x04, 8 }, 309 [SCxRDR] = { 0x05, 8 }, 310 }, 311 .fifosize = 1, 312 .overrun_reg = SCxSR, 313 .overrun_mask = SCI_ORER, 314 .sampling_rate_mask = SCI_SR(32), 315 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 316 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 317 .param_bits = &sci_sci_port_params_bits, 318 .common_regs = &sci_common_regs, 319 }, 320 321 /* 322 * Common definitions for legacy IrDA ports. 323 */ 324 [SCIx_IRDA_REGTYPE] = { 325 .regs = { 326 [SCSMR] = { 0x00, 8 }, 327 [SCBRR] = { 0x02, 8 }, 328 [SCSCR] = { 0x04, 8 }, 329 [SCxTDR] = { 0x06, 8 }, 330 [SCxSR] = { 0x08, 16 }, 331 [SCxRDR] = { 0x0a, 8 }, 332 [SCFCR] = { 0x0c, 8 }, 333 [SCFDR] = { 0x0e, 16 }, 334 }, 335 .fifosize = 1, 336 .overrun_reg = SCxSR, 337 .overrun_mask = SCI_ORER, 338 .sampling_rate_mask = SCI_SR(32), 339 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 340 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 341 .param_bits = &sci_scif_port_params_bits, 342 .common_regs = &sci_common_regs, 343 }, 344 345 /* 346 * Common SCIFA definitions. 347 */ 348 [SCIx_SCIFA_REGTYPE] = { 349 .regs = { 350 [SCSMR] = { 0x00, 16 }, 351 [SCBRR] = { 0x04, 8 }, 352 [SCSCR] = { 0x08, 16 }, 353 [SCxTDR] = { 0x20, 8 }, 354 [SCxSR] = { 0x14, 16 }, 355 [SCxRDR] = { 0x24, 8 }, 356 [SCFCR] = { 0x18, 16 }, 357 [SCFDR] = { 0x1c, 16 }, 358 [SCPCR] = { 0x30, 16 }, 359 [SCPDR] = { 0x34, 16 }, 360 }, 361 .fifosize = 64, 362 .overrun_reg = SCxSR, 363 .overrun_mask = SCIFA_ORER, 364 .sampling_rate_mask = SCI_SR_SCIFAB, 365 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 366 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 367 .param_bits = &sci_scif_port_params_bits, 368 .common_regs = &sci_common_regs, 369 }, 370 371 /* 372 * Common SCIFB definitions. 373 */ 374 [SCIx_SCIFB_REGTYPE] = { 375 .regs = { 376 [SCSMR] = { 0x00, 16 }, 377 [SCBRR] = { 0x04, 8 }, 378 [SCSCR] = { 0x08, 16 }, 379 [SCxTDR] = { 0x40, 8 }, 380 [SCxSR] = { 0x14, 16 }, 381 [SCxRDR] = { 0x60, 8 }, 382 [SCFCR] = { 0x18, 16 }, 383 [SCTFDR] = { 0x38, 16 }, 384 [SCRFDR] = { 0x3c, 16 }, 385 [SCPCR] = { 0x30, 16 }, 386 [SCPDR] = { 0x34, 16 }, 387 }, 388 .fifosize = 256, 389 .overrun_reg = SCxSR, 390 .overrun_mask = SCIFA_ORER, 391 .sampling_rate_mask = SCI_SR_SCIFAB, 392 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 393 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 394 .param_bits = &sci_scif_port_params_bits, 395 .common_regs = &sci_common_regs, 396 }, 397 398 /* 399 * Common SH-2(A) SCIF definitions for ports with FIFO data 400 * count registers. 401 */ 402 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 403 .regs = { 404 [SCSMR] = { 0x00, 16 }, 405 [SCBRR] = { 0x04, 8 }, 406 [SCSCR] = { 0x08, 16 }, 407 [SCxTDR] = { 0x0c, 8 }, 408 [SCxSR] = { 0x10, 16 }, 409 [SCxRDR] = { 0x14, 8 }, 410 [SCFCR] = { 0x18, 16 }, 411 [SCFDR] = { 0x1c, 16 }, 412 [SCSPTR] = { 0x20, 16 }, 413 [SCLSR] = { 0x24, 16 }, 414 }, 415 .fifosize = 16, 416 .overrun_reg = SCLSR, 417 .overrun_mask = SCLSR_ORER, 418 .sampling_rate_mask = SCI_SR(32), 419 .error_mask = SCIF_DEFAULT_ERROR_MASK, 420 .error_clear = SCIF_ERROR_CLEAR, 421 .param_bits = &sci_scif_port_params_bits, 422 .common_regs = &sci_common_regs, 423 }, 424 425 /* 426 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1. 427 * It looks like a normal SCIF with FIFO data, but with a 428 * compressed address space. Also, the break out of interrupts 429 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 430 */ 431 [SCIx_RZ_SCIFA_REGTYPE] = { 432 .regs = { 433 [SCSMR] = { 0x00, 16 }, 434 [SCBRR] = { 0x02, 8 }, 435 [SCSCR] = { 0x04, 16 }, 436 [SCxTDR] = { 0x06, 8 }, 437 [SCxSR] = { 0x08, 16 }, 438 [SCxRDR] = { 0x0A, 8 }, 439 [SCFCR] = { 0x0C, 16 }, 440 [SCFDR] = { 0x0E, 16 }, 441 [SCSPTR] = { 0x10, 16 }, 442 [SCLSR] = { 0x12, 16 }, 443 [SEMR] = { 0x14, 8 }, 444 }, 445 .fifosize = 16, 446 .overrun_reg = SCLSR, 447 .overrun_mask = SCLSR_ORER, 448 .sampling_rate_mask = SCI_SR(32), 449 .error_mask = SCIF_DEFAULT_ERROR_MASK, 450 .error_clear = SCIF_ERROR_CLEAR, 451 .param_bits = &sci_scif_port_params_bits, 452 .common_regs = &sci_common_regs, 453 }, 454 455 /* 456 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC 457 * with below differences, 458 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI, 459 * TEI-DRI, RXI-EDGE and TXI-EDGE. 460 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode. 461 * - SCFCR register does not have SCFCR_MCE bit. 462 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO. 463 */ 464 [SCIx_RZV2H_SCIF_REGTYPE] = { 465 .regs = { 466 [SCSMR] = { 0x00, 16 }, 467 [SCBRR] = { 0x02, 8 }, 468 [SCSCR] = { 0x04, 16 }, 469 [SCxTDR] = { 0x06, 8 }, 470 [SCxSR] = { 0x08, 16 }, 471 [SCxRDR] = { 0x0a, 8 }, 472 [SCFCR] = { 0x0c, 16 }, 473 [SCFDR] = { 0x0e, 16 }, 474 [SCSPTR] = { 0x10, 16 }, 475 [SCLSR] = { 0x12, 16 }, 476 [SEMR] = { 0x14, 8 }, 477 }, 478 .fifosize = 16, 479 .overrun_reg = SCLSR, 480 .overrun_mask = SCLSR_ORER, 481 .sampling_rate_mask = SCI_SR(32), 482 .error_mask = SCIF_DEFAULT_ERROR_MASK, 483 .error_clear = SCIF_ERROR_CLEAR, 484 .param_bits = &sci_scif_port_params_bits, 485 .common_regs = &sci_common_regs, 486 }, 487 488 /* 489 * Common SH-3 SCIF definitions. 490 */ 491 [SCIx_SH3_SCIF_REGTYPE] = { 492 .regs = { 493 [SCSMR] = { 0x00, 8 }, 494 [SCBRR] = { 0x02, 8 }, 495 [SCSCR] = { 0x04, 8 }, 496 [SCxTDR] = { 0x06, 8 }, 497 [SCxSR] = { 0x08, 16 }, 498 [SCxRDR] = { 0x0a, 8 }, 499 [SCFCR] = { 0x0c, 8 }, 500 [SCFDR] = { 0x0e, 16 }, 501 }, 502 .fifosize = 16, 503 .overrun_reg = SCLSR, 504 .overrun_mask = SCLSR_ORER, 505 .sampling_rate_mask = SCI_SR(32), 506 .error_mask = SCIF_DEFAULT_ERROR_MASK, 507 .error_clear = SCIF_ERROR_CLEAR, 508 .param_bits = &sci_scif_port_params_bits, 509 .common_regs = &sci_common_regs, 510 }, 511 512 /* 513 * Common SH-4(A) SCIF(B) definitions. 514 */ 515 [SCIx_SH4_SCIF_REGTYPE] = { 516 .regs = { 517 [SCSMR] = { 0x00, 16 }, 518 [SCBRR] = { 0x04, 8 }, 519 [SCSCR] = { 0x08, 16 }, 520 [SCxTDR] = { 0x0c, 8 }, 521 [SCxSR] = { 0x10, 16 }, 522 [SCxRDR] = { 0x14, 8 }, 523 [SCFCR] = { 0x18, 16 }, 524 [SCFDR] = { 0x1c, 16 }, 525 [SCSPTR] = { 0x20, 16 }, 526 [SCLSR] = { 0x24, 16 }, 527 }, 528 .fifosize = 16, 529 .overrun_reg = SCLSR, 530 .overrun_mask = SCLSR_ORER, 531 .sampling_rate_mask = SCI_SR(32), 532 .error_mask = SCIF_DEFAULT_ERROR_MASK, 533 .error_clear = SCIF_ERROR_CLEAR, 534 .param_bits = &sci_scif_port_params_bits, 535 .common_regs = &sci_common_regs, 536 }, 537 538 /* 539 * Common SCIF definitions for ports with a Baud Rate Generator for 540 * External Clock (BRG). 541 */ 542 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 543 .regs = { 544 [SCSMR] = { 0x00, 16 }, 545 [SCBRR] = { 0x04, 8 }, 546 [SCSCR] = { 0x08, 16 }, 547 [SCxTDR] = { 0x0c, 8 }, 548 [SCxSR] = { 0x10, 16 }, 549 [SCxRDR] = { 0x14, 8 }, 550 [SCFCR] = { 0x18, 16 }, 551 [SCFDR] = { 0x1c, 16 }, 552 [SCSPTR] = { 0x20, 16 }, 553 [SCLSR] = { 0x24, 16 }, 554 [SCDL] = { 0x30, 16 }, 555 [SCCKS] = { 0x34, 16 }, 556 }, 557 .fifosize = 16, 558 .overrun_reg = SCLSR, 559 .overrun_mask = SCLSR_ORER, 560 .sampling_rate_mask = SCI_SR(32), 561 .error_mask = SCIF_DEFAULT_ERROR_MASK, 562 .error_clear = SCIF_ERROR_CLEAR, 563 .param_bits = &sci_scif_port_params_bits, 564 .common_regs = &sci_common_regs, 565 }, 566 567 /* 568 * Common HSCIF definitions. 569 */ 570 [SCIx_HSCIF_REGTYPE] = { 571 .regs = { 572 [SCSMR] = { 0x00, 16 }, 573 [SCBRR] = { 0x04, 8 }, 574 [SCSCR] = { 0x08, 16 }, 575 [SCxTDR] = { 0x0c, 8 }, 576 [SCxSR] = { 0x10, 16 }, 577 [SCxRDR] = { 0x14, 8 }, 578 [SCFCR] = { 0x18, 16 }, 579 [SCFDR] = { 0x1c, 16 }, 580 [SCSPTR] = { 0x20, 16 }, 581 [SCLSR] = { 0x24, 16 }, 582 [HSSRR] = { 0x40, 16 }, 583 [SCDL] = { 0x30, 16 }, 584 [SCCKS] = { 0x34, 16 }, 585 [HSRTRGR] = { 0x54, 16 }, 586 [HSTTRGR] = { 0x58, 16 }, 587 }, 588 .fifosize = 128, 589 .overrun_reg = SCLSR, 590 .overrun_mask = SCLSR_ORER, 591 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 592 .error_mask = SCIF_DEFAULT_ERROR_MASK, 593 .error_clear = SCIF_ERROR_CLEAR, 594 .param_bits = &sci_scif_port_params_bits, 595 .common_regs = &sci_common_regs, 596 }, 597 598 /* 599 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 600 * register. 601 */ 602 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 603 .regs = { 604 [SCSMR] = { 0x00, 16 }, 605 [SCBRR] = { 0x04, 8 }, 606 [SCSCR] = { 0x08, 16 }, 607 [SCxTDR] = { 0x0c, 8 }, 608 [SCxSR] = { 0x10, 16 }, 609 [SCxRDR] = { 0x14, 8 }, 610 [SCFCR] = { 0x18, 16 }, 611 [SCFDR] = { 0x1c, 16 }, 612 [SCLSR] = { 0x24, 16 }, 613 }, 614 .fifosize = 16, 615 .overrun_reg = SCLSR, 616 .overrun_mask = SCLSR_ORER, 617 .sampling_rate_mask = SCI_SR(32), 618 .error_mask = SCIF_DEFAULT_ERROR_MASK, 619 .error_clear = SCIF_ERROR_CLEAR, 620 .param_bits = &sci_scif_port_params_bits, 621 .common_regs = &sci_common_regs, 622 }, 623 624 /* 625 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 626 * count registers. 627 */ 628 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 629 .regs = { 630 [SCSMR] = { 0x00, 16 }, 631 [SCBRR] = { 0x04, 8 }, 632 [SCSCR] = { 0x08, 16 }, 633 [SCxTDR] = { 0x0c, 8 }, 634 [SCxSR] = { 0x10, 16 }, 635 [SCxRDR] = { 0x14, 8 }, 636 [SCFCR] = { 0x18, 16 }, 637 [SCFDR] = { 0x1c, 16 }, 638 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 639 [SCRFDR] = { 0x20, 16 }, 640 [SCSPTR] = { 0x24, 16 }, 641 [SCLSR] = { 0x28, 16 }, 642 }, 643 .fifosize = 16, 644 .overrun_reg = SCLSR, 645 .overrun_mask = SCLSR_ORER, 646 .sampling_rate_mask = SCI_SR(32), 647 .error_mask = SCIF_DEFAULT_ERROR_MASK, 648 .error_clear = SCIF_ERROR_CLEAR, 649 .param_bits = &sci_scif_port_params_bits, 650 .common_regs = &sci_common_regs, 651 }, 652 653 /* 654 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 655 * registers. 656 */ 657 [SCIx_SH7705_SCIF_REGTYPE] = { 658 .regs = { 659 [SCSMR] = { 0x00, 16 }, 660 [SCBRR] = { 0x04, 8 }, 661 [SCSCR] = { 0x08, 16 }, 662 [SCxTDR] = { 0x20, 8 }, 663 [SCxSR] = { 0x14, 16 }, 664 [SCxRDR] = { 0x24, 8 }, 665 [SCFCR] = { 0x18, 16 }, 666 [SCFDR] = { 0x1c, 16 }, 667 }, 668 .fifosize = 64, 669 .overrun_reg = SCxSR, 670 .overrun_mask = SCIFA_ORER, 671 .sampling_rate_mask = SCI_SR(16), 672 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 673 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 674 .param_bits = &sci_scif_port_params_bits, 675 .common_regs = &sci_common_regs, 676 }, 677 }; 678 679 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 680 681 /* 682 * The "offset" here is rather misleading, in that it refers to an enum 683 * value relative to the port mapping rather than the fixed offset 684 * itself, which needs to be manually retrieved from the platform's 685 * register map for the given port. 686 */ 687 static unsigned int sci_serial_in(struct uart_port *p, int offset) 688 { 689 const struct plat_sci_reg *reg = sci_getreg(p, offset); 690 691 if (reg->size == 8) 692 return ioread8(p->membase + (reg->offset << p->regshift)); 693 else if (reg->size == 16) 694 return ioread16(p->membase + (reg->offset << p->regshift)); 695 else 696 WARN(1, "Invalid register access\n"); 697 698 return 0; 699 } 700 701 static void sci_serial_out(struct uart_port *p, int offset, int value) 702 { 703 const struct plat_sci_reg *reg = sci_getreg(p, offset); 704 705 if (reg->size == 8) 706 iowrite8(value, p->membase + (reg->offset << p->regshift)); 707 else if (reg->size == 16) 708 iowrite16(value, p->membase + (reg->offset << p->regshift)); 709 else 710 WARN(1, "Invalid register access\n"); 711 } 712 713 void sci_port_enable(struct sci_port *sci_port) 714 { 715 unsigned int i; 716 717 if (!sci_port->port.dev) 718 return; 719 720 pm_runtime_get_sync(sci_port->port.dev); 721 722 for (i = 0; i < SCI_NUM_CLKS; i++) { 723 clk_prepare_enable(sci_port->clks[i]); 724 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 725 } 726 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 727 } 728 EXPORT_SYMBOL_NS_GPL(sci_port_enable, "SH_SCI"); 729 730 void sci_port_disable(struct sci_port *sci_port) 731 { 732 unsigned int i; 733 734 if (!sci_port->port.dev) 735 return; 736 737 for (i = SCI_NUM_CLKS; i-- > 0; ) 738 clk_disable_unprepare(sci_port->clks[i]); 739 740 pm_runtime_put_sync(sci_port->port.dev); 741 } 742 EXPORT_SYMBOL_NS_GPL(sci_port_disable, "SH_SCI"); 743 744 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 745 { 746 /* 747 * Not all ports (such as SCIFA) will support REIE. Rather than 748 * special-casing the port type, we check the port initialization 749 * IRQ enable mask to see whether the IRQ is desired at all. If 750 * it's unset, it's logically inferred that there's no point in 751 * testing for it. 752 */ 753 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 754 } 755 756 static void sci_start_tx(struct uart_port *port) 757 { 758 struct sci_port *s = to_sci_port(port); 759 unsigned short ctrl; 760 761 #ifdef CONFIG_SERIAL_SH_SCI_DMA 762 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 763 u16 new, scr = sci_serial_in(port, SCSCR); 764 if (s->chan_tx) 765 new = scr | SCSCR_TDRQE; 766 else 767 new = scr & ~SCSCR_TDRQE; 768 if (new != scr) 769 sci_serial_out(port, SCSCR, new); 770 } 771 772 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) && 773 dma_submit_error(s->cookie_tx)) { 774 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) 775 /* Switch irq from SCIF to DMA */ 776 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); 777 778 s->cookie_tx = 0; 779 schedule_work(&s->work_tx); 780 } 781 #endif 782 783 if (!s->chan_tx || s->regtype == SCIx_RZ_SCIFA_REGTYPE || 784 s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 785 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 786 ctrl = sci_serial_in(port, SCSCR); 787 788 /* 789 * For SCI, TE (transmit enable) must be set after setting TIE 790 * (transmit interrupt enable) or in the same instruction to start 791 * the transmit process. 792 */ 793 if (s->type == PORT_SCI) 794 ctrl |= SCSCR_TE; 795 796 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE); 797 } 798 } 799 800 static void sci_stop_tx(struct uart_port *port) 801 { 802 struct sci_port *s = to_sci_port(port); 803 unsigned short ctrl; 804 805 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 806 ctrl = sci_serial_in(port, SCSCR); 807 808 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) 809 ctrl &= ~SCSCR_TDRQE; 810 811 ctrl &= ~SCSCR_TIE; 812 813 sci_serial_out(port, SCSCR, ctrl); 814 815 #ifdef CONFIG_SERIAL_SH_SCI_DMA 816 if (s->chan_tx && 817 !dma_submit_error(s->cookie_tx)) { 818 dmaengine_terminate_async(s->chan_tx); 819 s->cookie_tx = -EINVAL; 820 } 821 #endif 822 } 823 824 static void sci_start_rx(struct uart_port *port) 825 { 826 struct sci_port *s = to_sci_port(port); 827 unsigned short ctrl; 828 829 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port); 830 831 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) 832 ctrl &= ~SCSCR_RDRQE; 833 834 sci_serial_out(port, SCSCR, ctrl); 835 } 836 837 static void sci_stop_rx(struct uart_port *port) 838 { 839 struct sci_port *s = to_sci_port(port); 840 unsigned short ctrl; 841 842 ctrl = sci_serial_in(port, SCSCR); 843 844 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) 845 ctrl &= ~SCSCR_RDRQE; 846 847 ctrl &= ~port_rx_irq_mask(port); 848 849 sci_serial_out(port, SCSCR, ctrl); 850 } 851 852 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 853 { 854 struct sci_port *s = to_sci_port(port); 855 856 if (s->type == PORT_SCI) { 857 /* Just store the mask */ 858 sci_serial_out(port, SCxSR, mask); 859 } else if (s->params->overrun_mask == SCIFA_ORER) { 860 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 861 /* Only clear the status bits we want to clear */ 862 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask); 863 } else { 864 /* Store the mask, clear parity/framing errors */ 865 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 866 } 867 } 868 869 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 870 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 871 872 #ifdef CONFIG_CONSOLE_POLL 873 static int sci_poll_get_char(struct uart_port *port) 874 { 875 unsigned short status; 876 struct sci_port *s = to_sci_port(port); 877 int c; 878 879 do { 880 status = sci_serial_in(port, SCxSR); 881 if (status & SCxSR_ERRORS(port)) { 882 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 883 continue; 884 } 885 break; 886 } while (1); 887 888 if (!(status & SCxSR_RDxF(port))) 889 return NO_POLL_CHAR; 890 891 c = sci_serial_in(port, SCxRDR); 892 893 /* Dummy read */ 894 sci_serial_in(port, SCxSR); 895 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 896 897 return c; 898 } 899 #endif 900 901 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 902 { 903 struct sci_port *s = to_sci_port(port); 904 const struct sci_common_regs *regs = s->params->common_regs; 905 unsigned int status; 906 907 do { 908 status = s->ops->read_reg(port, regs->status); 909 } while (!(status & SCxSR_TDxE(port))); 910 911 sci_serial_out(port, SCxTDR, c); 912 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 913 } 914 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 915 CONFIG_SERIAL_SH_SCI_EARLYCON */ 916 917 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 918 { 919 struct sci_port *s = to_sci_port(port); 920 921 /* 922 * Use port-specific handler if provided. 923 */ 924 if (s->cfg->ops && s->cfg->ops->init_pins) { 925 s->cfg->ops->init_pins(port, cflag); 926 return; 927 } 928 929 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 930 u16 data = sci_serial_in(port, SCPDR); 931 u16 ctrl = sci_serial_in(port, SCPCR); 932 933 /* Enable RXD and TXD pin functions */ 934 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 935 if (s->has_rtscts) { 936 /* RTS# is output, active low, unless autorts */ 937 if (!(port->mctrl & TIOCM_RTS)) { 938 ctrl |= SCPCR_RTSC; 939 data |= SCPDR_RTSD; 940 } else if (!s->autorts) { 941 ctrl |= SCPCR_RTSC; 942 data &= ~SCPDR_RTSD; 943 } else { 944 /* Enable RTS# pin function */ 945 ctrl &= ~SCPCR_RTSC; 946 } 947 /* Enable CTS# pin function */ 948 ctrl &= ~SCPCR_CTSC; 949 } 950 sci_serial_out(port, SCPDR, data); 951 sci_serial_out(port, SCPCR, ctrl); 952 } else if (sci_getreg(port, SCSPTR)->size && s->regtype != SCIx_RZV2H_SCIF_REGTYPE) { 953 u16 status = sci_serial_in(port, SCSPTR); 954 955 /* RTS# is always output; and active low, unless autorts */ 956 status |= SCSPTR_RTSIO; 957 if (!(port->mctrl & TIOCM_RTS)) 958 status |= SCSPTR_RTSDT; 959 else if (!s->autorts) 960 status &= ~SCSPTR_RTSDT; 961 /* CTS# and SCK are inputs */ 962 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 963 sci_serial_out(port, SCSPTR, status); 964 } 965 } 966 967 static int sci_txfill(struct uart_port *port) 968 { 969 struct sci_port *s = to_sci_port(port); 970 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 971 const struct plat_sci_reg *reg; 972 973 reg = sci_getreg(port, SCTFDR); 974 if (reg->size) 975 return sci_serial_in(port, SCTFDR) & fifo_mask; 976 977 reg = sci_getreg(port, SCFDR); 978 if (reg->size) 979 return sci_serial_in(port, SCFDR) >> 8; 980 981 return !(sci_serial_in(port, SCxSR) & SCI_TDRE); 982 } 983 984 static int sci_txroom(struct uart_port *port) 985 { 986 return port->fifosize - sci_txfill(port); 987 } 988 989 static int sci_rxfill(struct uart_port *port) 990 { 991 struct sci_port *s = to_sci_port(port); 992 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 993 const struct plat_sci_reg *reg; 994 995 reg = sci_getreg(port, SCRFDR); 996 if (reg->size) 997 return sci_serial_in(port, SCRFDR) & fifo_mask; 998 999 reg = sci_getreg(port, SCFDR); 1000 if (reg->size) 1001 return sci_serial_in(port, SCFDR) & fifo_mask; 1002 1003 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 1004 } 1005 1006 /* ********************************************************************** * 1007 * the interrupt related routines * 1008 * ********************************************************************** */ 1009 1010 static void sci_transmit_chars(struct uart_port *port) 1011 { 1012 struct tty_port *tport = &port->state->port; 1013 unsigned int stopped = uart_tx_stopped(port); 1014 struct sci_port *s = to_sci_port(port); 1015 unsigned short status; 1016 unsigned short ctrl; 1017 int count; 1018 1019 status = sci_serial_in(port, SCxSR); 1020 if (!(status & SCxSR_TDxE(port))) { 1021 ctrl = sci_serial_in(port, SCSCR); 1022 if (kfifo_is_empty(&tport->xmit_fifo)) 1023 ctrl &= ~SCSCR_TIE; 1024 else 1025 ctrl |= SCSCR_TIE; 1026 sci_serial_out(port, SCSCR, ctrl); 1027 return; 1028 } 1029 1030 count = sci_txroom(port); 1031 1032 do { 1033 unsigned char c; 1034 1035 if (port->x_char) { 1036 c = port->x_char; 1037 port->x_char = 0; 1038 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { 1039 if (s->type == PORT_SCI && 1040 kfifo_is_empty(&tport->xmit_fifo)) { 1041 ctrl = sci_serial_in(port, SCSCR); 1042 ctrl &= ~SCSCR_TE; 1043 sci_serial_out(port, SCSCR, ctrl); 1044 return; 1045 } 1046 break; 1047 } 1048 1049 sci_serial_out(port, SCxTDR, c); 1050 s->tx_occurred = true; 1051 1052 port->icount.tx++; 1053 } while (--count > 0); 1054 1055 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 1056 1057 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1058 uart_write_wakeup(port); 1059 if (kfifo_is_empty(&tport->xmit_fifo)) { 1060 if (s->type == PORT_SCI) { 1061 ctrl = sci_serial_in(port, SCSCR); 1062 ctrl &= ~SCSCR_TIE; 1063 ctrl |= SCSCR_TEIE; 1064 sci_serial_out(port, SCSCR, ctrl); 1065 } 1066 1067 sci_stop_tx(port); 1068 } 1069 } 1070 1071 static void sci_receive_chars(struct uart_port *port) 1072 { 1073 struct tty_port *tport = &port->state->port; 1074 struct sci_port *s = to_sci_port(port); 1075 int i, count, copied = 0; 1076 unsigned short status; 1077 unsigned char flag; 1078 1079 status = sci_serial_in(port, SCxSR); 1080 if (!(status & SCxSR_RDxF(port))) 1081 return; 1082 1083 while (1) { 1084 /* Don't copy more bytes than there is room for in the buffer */ 1085 count = tty_buffer_request_room(tport, sci_rxfill(port)); 1086 1087 /* If for any reason we can't copy more data, we're done! */ 1088 if (count == 0) 1089 break; 1090 1091 if (s->type == PORT_SCI) { 1092 char c = sci_serial_in(port, SCxRDR); 1093 if (uart_handle_sysrq_char(port, c)) 1094 count = 0; 1095 else 1096 tty_insert_flip_char(tport, c, TTY_NORMAL); 1097 } else { 1098 for (i = 0; i < count; i++) { 1099 char c; 1100 1101 if (s->type == PORT_SCIF || 1102 s->type == PORT_HSCIF) { 1103 status = sci_serial_in(port, SCxSR); 1104 c = sci_serial_in(port, SCxRDR); 1105 } else { 1106 c = sci_serial_in(port, SCxRDR); 1107 status = sci_serial_in(port, SCxSR); 1108 } 1109 if (uart_handle_sysrq_char(port, c)) { 1110 count--; i--; 1111 continue; 1112 } 1113 1114 /* Store data and status */ 1115 if (status & SCxSR_FER(port)) { 1116 flag = TTY_FRAME; 1117 port->icount.frame++; 1118 } else if (status & SCxSR_PER(port)) { 1119 flag = TTY_PARITY; 1120 port->icount.parity++; 1121 } else 1122 flag = TTY_NORMAL; 1123 1124 tty_insert_flip_char(tport, c, flag); 1125 } 1126 } 1127 1128 sci_serial_in(port, SCxSR); /* dummy read */ 1129 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1130 1131 copied += count; 1132 port->icount.rx += count; 1133 } 1134 1135 if (copied) { 1136 /* Tell the rest of the system the news. New characters! */ 1137 tty_flip_buffer_push(tport); 1138 } else { 1139 /* TTY buffers full; read from RX reg to prevent lockup */ 1140 sci_serial_in(port, SCxRDR); 1141 sci_serial_in(port, SCxSR); /* dummy read */ 1142 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1143 } 1144 } 1145 1146 static int sci_handle_errors(struct uart_port *port) 1147 { 1148 int copied = 0; 1149 struct sci_port *s = to_sci_port(port); 1150 const struct sci_common_regs *regs = s->params->common_regs; 1151 unsigned int status = s->ops->read_reg(port, regs->status); 1152 struct tty_port *tport = &port->state->port; 1153 1154 /* Handle overruns */ 1155 if (status & s->params->overrun_mask) { 1156 port->icount.overrun++; 1157 1158 /* overrun error */ 1159 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 1160 copied++; 1161 } 1162 1163 if (status & SCxSR_FER(port)) { 1164 /* frame error */ 1165 port->icount.frame++; 1166 1167 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 1168 copied++; 1169 } 1170 1171 if (status & SCxSR_PER(port)) { 1172 /* parity error */ 1173 port->icount.parity++; 1174 1175 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 1176 copied++; 1177 } 1178 1179 if (copied) 1180 tty_flip_buffer_push(tport); 1181 1182 return copied; 1183 } 1184 1185 static int sci_handle_fifo_overrun(struct uart_port *port) 1186 { 1187 struct tty_port *tport = &port->state->port; 1188 struct sci_port *s = to_sci_port(port); 1189 const struct plat_sci_reg *reg; 1190 int copied = 0; 1191 u32 status; 1192 1193 if (s->type != SCI_PORT_RSCI) { 1194 reg = sci_getreg(port, s->params->overrun_reg); 1195 if (!reg->size) 1196 return 0; 1197 } 1198 1199 status = s->ops->read_reg(port, s->params->overrun_reg); 1200 if (status & s->params->overrun_mask) { 1201 status &= ~s->params->overrun_mask; 1202 s->ops->write_reg(port, s->params->overrun_reg, status); 1203 1204 port->icount.overrun++; 1205 1206 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1207 tty_flip_buffer_push(tport); 1208 copied++; 1209 } 1210 1211 return copied; 1212 } 1213 1214 static int sci_handle_breaks(struct uart_port *port) 1215 { 1216 int copied = 0; 1217 unsigned short status = sci_serial_in(port, SCxSR); 1218 struct tty_port *tport = &port->state->port; 1219 1220 if (uart_handle_break(port)) 1221 return 0; 1222 1223 if (status & SCxSR_BRK(port)) { 1224 port->icount.brk++; 1225 1226 /* Notify of BREAK */ 1227 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1228 copied++; 1229 } 1230 1231 if (copied) 1232 tty_flip_buffer_push(tport); 1233 1234 copied += sci_handle_fifo_overrun(port); 1235 1236 return copied; 1237 } 1238 1239 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1240 { 1241 struct sci_port *s = to_sci_port(port); 1242 unsigned int bits; 1243 1244 if (rx_trig >= port->fifosize) 1245 rx_trig = port->fifosize - 1; 1246 if (rx_trig < 1) 1247 rx_trig = 1; 1248 1249 /* HSCIF can be set to an arbitrary level. */ 1250 if (sci_getreg(port, HSRTRGR)->size) { 1251 sci_serial_out(port, HSRTRGR, rx_trig); 1252 return rx_trig; 1253 } 1254 1255 switch (s->type) { 1256 case PORT_SCIF: 1257 if (rx_trig < 4) { 1258 bits = 0; 1259 rx_trig = 1; 1260 } else if (rx_trig < 8) { 1261 bits = SCFCR_RTRG0; 1262 rx_trig = 4; 1263 } else if (rx_trig < 14) { 1264 bits = SCFCR_RTRG1; 1265 rx_trig = 8; 1266 } else { 1267 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1268 rx_trig = 14; 1269 } 1270 break; 1271 case PORT_SCIFA: 1272 case PORT_SCIFB: 1273 if (rx_trig < 16) { 1274 bits = 0; 1275 rx_trig = 1; 1276 } else if (rx_trig < 32) { 1277 bits = SCFCR_RTRG0; 1278 rx_trig = 16; 1279 } else if (rx_trig < 48) { 1280 bits = SCFCR_RTRG1; 1281 rx_trig = 32; 1282 } else { 1283 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1284 rx_trig = 48; 1285 } 1286 break; 1287 default: 1288 WARN(1, "unknown FIFO configuration"); 1289 return 1; 1290 } 1291 1292 sci_serial_out(port, SCFCR, 1293 (sci_serial_in(port, SCFCR) & 1294 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1295 1296 return rx_trig; 1297 } 1298 1299 static int scif_rtrg_enabled(struct uart_port *port) 1300 { 1301 if (sci_getreg(port, HSRTRGR)->size) 1302 return sci_serial_in(port, HSRTRGR) != 0; 1303 else 1304 return (sci_serial_in(port, SCFCR) & 1305 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1306 } 1307 1308 static void rx_fifo_timer_fn(struct timer_list *t) 1309 { 1310 struct sci_port *s = timer_container_of(s, t, rx_fifo_timer); 1311 struct uart_port *port = &s->port; 1312 1313 dev_dbg(port->dev, "Rx timed out\n"); 1314 s->ops->set_rtrg(port, 1); 1315 } 1316 1317 static ssize_t rx_fifo_trigger_show(struct device *dev, 1318 struct device_attribute *attr, char *buf) 1319 { 1320 struct uart_port *port = dev_get_drvdata(dev); 1321 struct sci_port *sci = to_sci_port(port); 1322 1323 return sprintf(buf, "%d\n", sci->rx_trigger); 1324 } 1325 1326 static ssize_t rx_fifo_trigger_store(struct device *dev, 1327 struct device_attribute *attr, 1328 const char *buf, size_t count) 1329 { 1330 struct uart_port *port = dev_get_drvdata(dev); 1331 struct sci_port *sci = to_sci_port(port); 1332 int ret; 1333 long r; 1334 1335 ret = kstrtol(buf, 0, &r); 1336 if (ret) 1337 return ret; 1338 1339 sci->rx_trigger = sci->ops->set_rtrg(port, r); 1340 if (sci->type == PORT_SCIFA || sci->type == PORT_SCIFB) 1341 sci->ops->set_rtrg(port, 1); 1342 1343 return count; 1344 } 1345 1346 static DEVICE_ATTR_RW(rx_fifo_trigger); 1347 1348 static ssize_t rx_fifo_timeout_show(struct device *dev, 1349 struct device_attribute *attr, 1350 char *buf) 1351 { 1352 struct uart_port *port = dev_get_drvdata(dev); 1353 struct sci_port *sci = to_sci_port(port); 1354 int v; 1355 1356 if (sci->type == PORT_HSCIF) 1357 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1358 else 1359 v = sci->rx_fifo_timeout; 1360 1361 return sprintf(buf, "%d\n", v); 1362 } 1363 1364 static ssize_t rx_fifo_timeout_store(struct device *dev, 1365 struct device_attribute *attr, 1366 const char *buf, 1367 size_t count) 1368 { 1369 struct uart_port *port = dev_get_drvdata(dev); 1370 struct sci_port *sci = to_sci_port(port); 1371 int ret; 1372 long r; 1373 1374 ret = kstrtol(buf, 0, &r); 1375 if (ret) 1376 return ret; 1377 1378 if (sci->type == PORT_HSCIF) { 1379 if (r < 0 || r > 3) 1380 return -EINVAL; 1381 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1382 } else { 1383 sci->rx_fifo_timeout = r; 1384 sci->ops->set_rtrg(port, 1); 1385 if (r > 0) 1386 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1387 } 1388 1389 return count; 1390 } 1391 1392 static DEVICE_ATTR_RW(rx_fifo_timeout); 1393 1394 1395 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1396 static void sci_dma_tx_complete(void *arg) 1397 { 1398 struct sci_port *s = arg; 1399 struct uart_port *port = &s->port; 1400 struct tty_port *tport = &port->state->port; 1401 unsigned long flags; 1402 1403 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1404 1405 uart_port_lock_irqsave(port, &flags); 1406 1407 uart_xmit_advance(port, s->tx_dma_len); 1408 1409 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1410 uart_write_wakeup(port); 1411 1412 s->tx_occurred = true; 1413 1414 if (!kfifo_is_empty(&tport->xmit_fifo)) { 1415 s->cookie_tx = 0; 1416 schedule_work(&s->work_tx); 1417 } else { 1418 s->cookie_tx = -EINVAL; 1419 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || 1420 s->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1421 u16 ctrl = sci_serial_in(port, SCSCR); 1422 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1423 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1424 /* Switch irq from DMA to SCIF */ 1425 dmaengine_pause(s->chan_tx_saved); 1426 enable_irq(s->irqs[SCIx_TXI_IRQ]); 1427 } 1428 } 1429 } 1430 1431 uart_port_unlock_irqrestore(port, flags); 1432 } 1433 1434 /* Locking: called with port lock held */ 1435 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1436 { 1437 struct uart_port *port = &s->port; 1438 struct tty_port *tport = &port->state->port; 1439 int copied; 1440 1441 copied = tty_insert_flip_string(tport, buf, count); 1442 if (copied < count) 1443 port->icount.buf_overrun++; 1444 1445 port->icount.rx += copied; 1446 1447 return copied; 1448 } 1449 1450 static int sci_dma_rx_find_active(struct sci_port *s) 1451 { 1452 unsigned int i; 1453 1454 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1455 if (s->active_rx == s->cookie_rx[i]) 1456 return i; 1457 1458 return -1; 1459 } 1460 1461 /* Must only be called with uart_port_lock taken */ 1462 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1463 { 1464 unsigned int i; 1465 1466 s->chan_rx = NULL; 1467 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1468 s->cookie_rx[i] = -EINVAL; 1469 s->active_rx = 0; 1470 } 1471 1472 static void sci_dma_rx_release(struct sci_port *s) 1473 { 1474 struct dma_chan *chan = s->chan_rx_saved; 1475 struct uart_port *port = &s->port; 1476 unsigned long flags; 1477 1478 uart_port_lock_irqsave(port, &flags); 1479 s->chan_rx_saved = NULL; 1480 sci_dma_rx_chan_invalidate(s); 1481 uart_port_unlock_irqrestore(port, flags); 1482 1483 dmaengine_terminate_sync(chan); 1484 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1485 sg_dma_address(&s->sg_rx[0])); 1486 dma_release_channel(chan); 1487 } 1488 1489 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1490 { 1491 long sec = usec / 1000000; 1492 long nsec = (usec % 1000000) * 1000; 1493 ktime_t t = ktime_set(sec, nsec); 1494 1495 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1496 } 1497 1498 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1499 { 1500 struct uart_port *port = &s->port; 1501 u16 scr; 1502 1503 /* Direct new serial port interrupts back to CPU */ 1504 scr = sci_serial_in(port, SCSCR); 1505 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || 1506 s->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1507 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1508 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) 1509 s->ops->set_rtrg(port, s->rx_trigger); 1510 else 1511 scr &= ~SCSCR_RDRQE; 1512 } 1513 sci_serial_out(port, SCSCR, scr | SCSCR_RIE); 1514 } 1515 1516 static void sci_dma_rx_complete(void *arg) 1517 { 1518 struct sci_port *s = arg; 1519 struct dma_chan *chan = s->chan_rx; 1520 struct uart_port *port = &s->port; 1521 struct dma_async_tx_descriptor *desc; 1522 unsigned long flags; 1523 int active, count = 0; 1524 1525 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1526 s->active_rx); 1527 1528 hrtimer_cancel(&s->rx_timer); 1529 1530 uart_port_lock_irqsave(port, &flags); 1531 1532 active = sci_dma_rx_find_active(s); 1533 if (active >= 0) 1534 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1535 1536 if (count) 1537 tty_flip_buffer_push(&port->state->port); 1538 1539 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1540 DMA_DEV_TO_MEM, 1541 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1542 if (!desc) 1543 goto fail; 1544 1545 desc->callback = sci_dma_rx_complete; 1546 desc->callback_param = s; 1547 s->cookie_rx[active] = dmaengine_submit(desc); 1548 if (dma_submit_error(s->cookie_rx[active])) 1549 goto fail; 1550 1551 s->active_rx = s->cookie_rx[!active]; 1552 1553 dma_async_issue_pending(chan); 1554 1555 uart_port_unlock_irqrestore(port, flags); 1556 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1557 __func__, s->cookie_rx[active], active, s->active_rx); 1558 1559 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1560 1561 return; 1562 1563 fail: 1564 /* Switch to PIO */ 1565 dmaengine_terminate_async(chan); 1566 sci_dma_rx_chan_invalidate(s); 1567 sci_dma_rx_reenable_irq(s); 1568 uart_port_unlock_irqrestore(port, flags); 1569 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1570 } 1571 1572 static void sci_dma_tx_release(struct sci_port *s) 1573 { 1574 struct dma_chan *chan = s->chan_tx_saved; 1575 1576 cancel_work_sync(&s->work_tx); 1577 s->chan_tx_saved = s->chan_tx = NULL; 1578 s->cookie_tx = -EINVAL; 1579 dmaengine_terminate_sync(chan); 1580 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1581 DMA_TO_DEVICE); 1582 dma_release_channel(chan); 1583 } 1584 1585 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1586 { 1587 struct dma_chan *chan = s->chan_rx; 1588 struct uart_port *port = &s->port; 1589 unsigned long flags; 1590 int i; 1591 1592 for (i = 0; i < 2; i++) { 1593 struct scatterlist *sg = &s->sg_rx[i]; 1594 struct dma_async_tx_descriptor *desc; 1595 1596 desc = dmaengine_prep_slave_sg(chan, 1597 sg, 1, DMA_DEV_TO_MEM, 1598 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1599 if (!desc) 1600 goto fail; 1601 1602 desc->callback = sci_dma_rx_complete; 1603 desc->callback_param = s; 1604 s->cookie_rx[i] = dmaengine_submit(desc); 1605 if (dma_submit_error(s->cookie_rx[i])) 1606 goto fail; 1607 1608 } 1609 1610 s->active_rx = s->cookie_rx[0]; 1611 1612 dma_async_issue_pending(chan); 1613 return 0; 1614 1615 fail: 1616 /* Switch to PIO */ 1617 if (!port_lock_held) 1618 uart_port_lock_irqsave(port, &flags); 1619 if (i) 1620 dmaengine_terminate_async(chan); 1621 sci_dma_rx_chan_invalidate(s); 1622 sci_start_rx(port); 1623 if (!port_lock_held) 1624 uart_port_unlock_irqrestore(port, flags); 1625 return -EAGAIN; 1626 } 1627 1628 static void sci_dma_tx_work_fn(struct work_struct *work) 1629 { 1630 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1631 struct dma_async_tx_descriptor *desc; 1632 struct dma_chan *chan = s->chan_tx; 1633 struct uart_port *port = &s->port; 1634 struct tty_port *tport = &port->state->port; 1635 unsigned long flags; 1636 unsigned int tail; 1637 dma_addr_t buf; 1638 1639 /* 1640 * DMA is idle now. 1641 * Port xmit buffer is already mapped, and it is one page... Just adjust 1642 * offsets and lengths. Since it is a circular buffer, we have to 1643 * transmit till the end, and then the rest. Take the port lock to get a 1644 * consistent xmit buffer state. 1645 */ 1646 uart_port_lock_irq(port); 1647 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail, 1648 UART_XMIT_SIZE); 1649 buf = s->tx_dma_addr + tail; 1650 if (!s->tx_dma_len) { 1651 /* Transmit buffer has been flushed */ 1652 uart_port_unlock_irq(port); 1653 return; 1654 } 1655 1656 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1657 DMA_MEM_TO_DEV, 1658 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1659 if (!desc) { 1660 uart_port_unlock_irq(port); 1661 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1662 goto switch_to_pio; 1663 } 1664 1665 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1666 DMA_TO_DEVICE); 1667 1668 desc->callback = sci_dma_tx_complete; 1669 desc->callback_param = s; 1670 s->cookie_tx = dmaengine_submit(desc); 1671 if (dma_submit_error(s->cookie_tx)) { 1672 uart_port_unlock_irq(port); 1673 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1674 goto switch_to_pio; 1675 } 1676 1677 uart_port_unlock_irq(port); 1678 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n", 1679 __func__, tport->xmit_buf, tail, s->cookie_tx); 1680 1681 dma_async_issue_pending(chan); 1682 return; 1683 1684 switch_to_pio: 1685 uart_port_lock_irqsave(port, &flags); 1686 s->chan_tx = NULL; 1687 sci_start_tx(port); 1688 uart_port_unlock_irqrestore(port, flags); 1689 return; 1690 } 1691 1692 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1693 { 1694 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1695 struct dma_chan *chan = s->chan_rx; 1696 struct uart_port *port = &s->port; 1697 struct dma_tx_state state; 1698 enum dma_status status; 1699 unsigned long flags; 1700 unsigned int read; 1701 int active, count; 1702 1703 dev_dbg(port->dev, "DMA Rx timed out\n"); 1704 1705 uart_port_lock_irqsave(port, &flags); 1706 1707 active = sci_dma_rx_find_active(s); 1708 if (active < 0) { 1709 uart_port_unlock_irqrestore(port, flags); 1710 return HRTIMER_NORESTART; 1711 } 1712 1713 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1714 if (status == DMA_COMPLETE) { 1715 uart_port_unlock_irqrestore(port, flags); 1716 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1717 s->active_rx, active); 1718 1719 /* Let packet complete handler take care of the packet */ 1720 return HRTIMER_NORESTART; 1721 } 1722 1723 dmaengine_pause(chan); 1724 1725 /* 1726 * sometimes DMA transfer doesn't stop even if it is stopped and 1727 * data keeps on coming until transaction is complete so check 1728 * for DMA_COMPLETE again 1729 * Let packet complete handler take care of the packet 1730 */ 1731 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1732 if (status == DMA_COMPLETE) { 1733 uart_port_unlock_irqrestore(port, flags); 1734 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1735 return HRTIMER_NORESTART; 1736 } 1737 1738 /* Handle incomplete DMA receive */ 1739 dmaengine_terminate_async(s->chan_rx); 1740 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1741 1742 if (read) { 1743 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1744 if (count) 1745 tty_flip_buffer_push(&port->state->port); 1746 } 1747 1748 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || 1749 s->regtype == SCIx_RZ_SCIFA_REGTYPE) 1750 sci_dma_rx_submit(s, true); 1751 1752 sci_dma_rx_reenable_irq(s); 1753 1754 uart_port_unlock_irqrestore(port, flags); 1755 1756 return HRTIMER_NORESTART; 1757 } 1758 1759 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1760 enum dma_transfer_direction dir) 1761 { 1762 struct dma_chan *chan; 1763 struct dma_slave_config cfg; 1764 int ret; 1765 1766 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1767 if (IS_ERR(chan)) { 1768 dev_dbg(port->dev, "dma_request_chan failed\n"); 1769 return NULL; 1770 } 1771 1772 memset(&cfg, 0, sizeof(cfg)); 1773 cfg.direction = dir; 1774 cfg.dst_addr = port->mapbase + 1775 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1776 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1777 cfg.src_addr = port->mapbase + 1778 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1779 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1780 1781 ret = dmaengine_slave_config(chan, &cfg); 1782 if (ret) { 1783 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1784 dma_release_channel(chan); 1785 return NULL; 1786 } 1787 1788 return chan; 1789 } 1790 1791 static void sci_request_dma(struct uart_port *port) 1792 { 1793 struct sci_port *s = to_sci_port(port); 1794 struct tty_port *tport = &port->state->port; 1795 struct dma_chan *chan; 1796 1797 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1798 1799 /* 1800 * DMA on console may interfere with Kernel log messages which use 1801 * plain putchar(). So, simply don't use it with a console. 1802 */ 1803 if (uart_console(port)) 1804 return; 1805 1806 if (!port->dev->of_node) 1807 return; 1808 1809 s->cookie_tx = -EINVAL; 1810 1811 /* 1812 * Don't request a dma channel if no channel was specified 1813 * in the device tree. 1814 */ 1815 if (!of_property_present(port->dev->of_node, "dmas")) 1816 return; 1817 1818 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1819 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1820 if (chan) { 1821 /* UART circular tx buffer is an aligned page. */ 1822 s->tx_dma_addr = dma_map_single(chan->device->dev, 1823 tport->xmit_buf, 1824 UART_XMIT_SIZE, 1825 DMA_TO_DEVICE); 1826 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1827 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1828 dma_release_channel(chan); 1829 } else { 1830 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1831 __func__, UART_XMIT_SIZE, 1832 tport->xmit_buf, &s->tx_dma_addr); 1833 1834 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1835 s->chan_tx_saved = s->chan_tx = chan; 1836 } 1837 } 1838 1839 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1840 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1841 if (chan) { 1842 unsigned int i; 1843 dma_addr_t dma; 1844 void *buf; 1845 1846 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1847 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1848 &dma, GFP_KERNEL); 1849 if (!buf) { 1850 dev_warn(port->dev, 1851 "Failed to allocate Rx dma buffer, using PIO\n"); 1852 dma_release_channel(chan); 1853 return; 1854 } 1855 1856 for (i = 0; i < 2; i++) { 1857 struct scatterlist *sg = &s->sg_rx[i]; 1858 1859 sg_init_table(sg, 1); 1860 s->rx_buf[i] = buf; 1861 sg_dma_address(sg) = dma; 1862 sg_dma_len(sg) = s->buf_len_rx; 1863 1864 buf += s->buf_len_rx; 1865 dma += s->buf_len_rx; 1866 } 1867 1868 hrtimer_setup(&s->rx_timer, sci_dma_rx_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1869 1870 s->chan_rx_saved = s->chan_rx = chan; 1871 1872 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || 1873 s->regtype == SCIx_RZ_SCIFA_REGTYPE) 1874 sci_dma_rx_submit(s, false); 1875 } 1876 } 1877 1878 static void sci_free_dma(struct uart_port *port) 1879 { 1880 struct sci_port *s = to_sci_port(port); 1881 1882 if (s->chan_tx_saved) 1883 sci_dma_tx_release(s); 1884 if (s->chan_rx_saved) 1885 sci_dma_rx_release(s); 1886 } 1887 1888 static void sci_flush_buffer(struct uart_port *port) 1889 { 1890 struct sci_port *s = to_sci_port(port); 1891 1892 /* 1893 * In uart_flush_buffer(), the xmit circular buffer has just been 1894 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1895 * pending transfers 1896 */ 1897 s->tx_dma_len = 0; 1898 if (s->chan_tx) { 1899 dmaengine_terminate_async(s->chan_tx); 1900 s->cookie_tx = -EINVAL; 1901 } 1902 } 1903 1904 static void sci_dma_check_tx_occurred(struct sci_port *s) 1905 { 1906 struct dma_tx_state state; 1907 enum dma_status status; 1908 1909 if (!s->chan_tx) 1910 return; 1911 1912 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state); 1913 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS) 1914 s->tx_occurred = true; 1915 } 1916 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1917 static inline void sci_request_dma(struct uart_port *port) 1918 { 1919 } 1920 1921 static inline void sci_free_dma(struct uart_port *port) 1922 { 1923 } 1924 1925 static void sci_dma_check_tx_occurred(struct sci_port *s) 1926 { 1927 } 1928 1929 #define sci_flush_buffer NULL 1930 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1931 1932 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1933 { 1934 struct uart_port *port = ptr; 1935 struct sci_port *s = to_sci_port(port); 1936 1937 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1938 if (s->chan_rx) { 1939 u16 scr = sci_serial_in(port, SCSCR); 1940 u16 ssr = sci_serial_in(port, SCxSR); 1941 1942 /* Disable future Rx interrupts */ 1943 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || 1944 s->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1945 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); 1946 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1947 s->ops->set_rtrg(port, 1); 1948 scr |= SCSCR_RIE; 1949 } else { 1950 scr |= SCSCR_RDRQE; 1951 } 1952 } else { 1953 if (sci_dma_rx_submit(s, false) < 0) 1954 goto handle_pio; 1955 1956 scr &= ~SCSCR_RIE; 1957 } 1958 sci_serial_out(port, SCSCR, scr); 1959 /* Clear current interrupt */ 1960 sci_serial_out(port, SCxSR, 1961 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1962 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1963 jiffies, s->rx_timeout); 1964 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1965 1966 return IRQ_HANDLED; 1967 } 1968 1969 handle_pio: 1970 #endif 1971 1972 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1973 if (!s->ops->rtrg_enabled(port)) 1974 s->ops->set_rtrg(port, s->rx_trigger); 1975 1976 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1977 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1978 } 1979 1980 /* I think sci_receive_chars has to be called irrespective 1981 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1982 * to be disabled? 1983 */ 1984 s->ops->receive_chars(port); 1985 1986 return IRQ_HANDLED; 1987 } 1988 1989 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1990 { 1991 struct uart_port *port = ptr; 1992 unsigned long flags; 1993 struct sci_port *s = to_sci_port(port); 1994 1995 uart_port_lock_irqsave(port, &flags); 1996 s->ops->transmit_chars(port); 1997 uart_port_unlock_irqrestore(port, flags); 1998 1999 return IRQ_HANDLED; 2000 } 2001 2002 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) 2003 { 2004 struct uart_port *port = ptr; 2005 struct sci_port *s = to_sci_port(port); 2006 const struct sci_common_regs *regs = s->params->common_regs; 2007 unsigned long flags; 2008 u32 ctrl; 2009 2010 if (s->type != PORT_SCI && s->type != SCI_PORT_RSCI) 2011 return sci_tx_interrupt(irq, ptr); 2012 2013 uart_port_lock_irqsave(port, &flags); 2014 ctrl = s->ops->read_reg(port, regs->control) & 2015 ~(s->params->param_bits->te_clear); 2016 s->ops->write_reg(port, regs->control, ctrl); 2017 uart_port_unlock_irqrestore(port, flags); 2018 2019 return IRQ_HANDLED; 2020 } 2021 2022 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 2023 { 2024 struct uart_port *port = ptr; 2025 struct sci_port *s = to_sci_port(port); 2026 2027 /* Handle BREAKs */ 2028 sci_handle_breaks(port); 2029 2030 /* drop invalid character received before break was detected */ 2031 sci_serial_in(port, SCxRDR); 2032 2033 s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 2034 2035 return IRQ_HANDLED; 2036 } 2037 2038 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 2039 { 2040 struct uart_port *port = ptr; 2041 struct sci_port *s = to_sci_port(port); 2042 2043 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 2044 /* Break and Error interrupts are muxed */ 2045 unsigned short ssr_status = sci_serial_in(port, SCxSR); 2046 2047 /* Break Interrupt */ 2048 if (ssr_status & SCxSR_BRK(port)) 2049 sci_br_interrupt(irq, ptr); 2050 2051 /* Break only? */ 2052 if (!(ssr_status & SCxSR_ERRORS(port))) 2053 return IRQ_HANDLED; 2054 } 2055 2056 /* Handle errors */ 2057 if (s->type == PORT_SCI) { 2058 if (sci_handle_errors(port)) { 2059 /* discard character in rx buffer */ 2060 sci_serial_in(port, SCxSR); 2061 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 2062 } 2063 } else { 2064 sci_handle_fifo_overrun(port); 2065 if (!s->chan_rx) 2066 s->ops->receive_chars(port); 2067 } 2068 2069 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 2070 2071 /* Kick the transmission */ 2072 if (!s->chan_tx) 2073 sci_tx_interrupt(irq, ptr); 2074 2075 return IRQ_HANDLED; 2076 } 2077 2078 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 2079 { 2080 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 2081 struct uart_port *port = ptr; 2082 struct sci_port *s = to_sci_port(port); 2083 irqreturn_t ret = IRQ_NONE; 2084 2085 ssr_status = sci_serial_in(port, SCxSR); 2086 scr_status = sci_serial_in(port, SCSCR); 2087 if (s->params->overrun_reg == SCxSR) 2088 orer_status = ssr_status; 2089 else if (sci_getreg(port, s->params->overrun_reg)->size) 2090 orer_status = sci_serial_in(port, s->params->overrun_reg); 2091 2092 err_enabled = scr_status & port_rx_irq_mask(port); 2093 2094 /* Tx Interrupt */ 2095 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 2096 !s->chan_tx) 2097 ret = sci_tx_interrupt(irq, ptr); 2098 2099 /* 2100 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 2101 * DR flags 2102 */ 2103 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 2104 (scr_status & SCSCR_RIE)) 2105 ret = sci_rx_interrupt(irq, ptr); 2106 2107 /* Error Interrupt */ 2108 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 2109 ret = sci_er_interrupt(irq, ptr); 2110 2111 /* Break Interrupt */ 2112 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 2113 (ssr_status & SCxSR_BRK(port)) && err_enabled) 2114 ret = sci_br_interrupt(irq, ptr); 2115 2116 /* Overrun Interrupt */ 2117 if (orer_status & s->params->overrun_mask) { 2118 sci_handle_fifo_overrun(port); 2119 ret = IRQ_HANDLED; 2120 } 2121 2122 return ret; 2123 } 2124 2125 static const struct sci_irq_desc { 2126 const char *desc; 2127 irq_handler_t handler; 2128 } sci_irq_desc[] = { 2129 /* 2130 * Split out handlers, the default case. 2131 */ 2132 [SCIx_ERI_IRQ] = { 2133 .desc = "rx err", 2134 .handler = sci_er_interrupt, 2135 }, 2136 2137 [SCIx_RXI_IRQ] = { 2138 .desc = "rx full", 2139 .handler = sci_rx_interrupt, 2140 }, 2141 2142 [SCIx_TXI_IRQ] = { 2143 .desc = "tx empty", 2144 .handler = sci_tx_interrupt, 2145 }, 2146 2147 [SCIx_BRI_IRQ] = { 2148 .desc = "break", 2149 .handler = sci_br_interrupt, 2150 }, 2151 2152 [SCIx_DRI_IRQ] = { 2153 .desc = "rx ready", 2154 .handler = sci_rx_interrupt, 2155 }, 2156 2157 [SCIx_TEI_IRQ] = { 2158 .desc = "tx end", 2159 .handler = sci_tx_end_interrupt, 2160 }, 2161 2162 /* 2163 * Special muxed handler. 2164 */ 2165 [SCIx_MUX_IRQ] = { 2166 .desc = "mux", 2167 .handler = sci_mpxed_interrupt, 2168 }, 2169 }; 2170 2171 static int sci_request_irq(struct sci_port *port) 2172 { 2173 struct uart_port *up = &port->port; 2174 int i, j, w, ret = 0; 2175 2176 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 2177 const struct sci_irq_desc *desc; 2178 int irq; 2179 2180 /* Check if already registered (muxed) */ 2181 for (w = 0; w < i; w++) 2182 if (port->irqs[w] == port->irqs[i]) 2183 w = i + 1; 2184 if (w > i) 2185 continue; 2186 2187 if (SCIx_IRQ_IS_MUXED(port)) { 2188 i = SCIx_MUX_IRQ; 2189 irq = up->irq; 2190 } else { 2191 irq = port->irqs[i]; 2192 2193 /* 2194 * Certain port types won't support all of the 2195 * available interrupt sources. 2196 */ 2197 if (unlikely(irq < 0)) 2198 continue; 2199 } 2200 2201 desc = sci_irq_desc + i; 2202 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 2203 dev_name(up->dev), desc->desc); 2204 if (!port->irqstr[j]) { 2205 ret = -ENOMEM; 2206 goto out_nomem; 2207 } 2208 2209 ret = request_irq(irq, desc->handler, up->irqflags, 2210 port->irqstr[j], port); 2211 if (unlikely(ret)) { 2212 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 2213 goto out_noirq; 2214 } 2215 } 2216 2217 return 0; 2218 2219 out_noirq: 2220 while (--i >= 0) 2221 free_irq(port->irqs[i], port); 2222 2223 out_nomem: 2224 while (--j >= 0) 2225 kfree(port->irqstr[j]); 2226 2227 return ret; 2228 } 2229 2230 static void sci_free_irq(struct sci_port *port) 2231 { 2232 int i, j; 2233 2234 /* 2235 * Intentionally in reverse order so we iterate over the muxed 2236 * IRQ first. 2237 */ 2238 for (i = 0; i < SCIx_NR_IRQS; i++) { 2239 int irq = port->irqs[i]; 2240 2241 /* 2242 * Certain port types won't support all of the available 2243 * interrupt sources. 2244 */ 2245 if (unlikely(irq < 0)) 2246 continue; 2247 2248 /* Check if already freed (irq was muxed) */ 2249 for (j = 0; j < i; j++) 2250 if (port->irqs[j] == irq) 2251 j = i + 1; 2252 if (j > i) 2253 continue; 2254 2255 free_irq(port->irqs[i], port); 2256 kfree(port->irqstr[i]); 2257 2258 if (SCIx_IRQ_IS_MUXED(port)) { 2259 /* If there's only one IRQ, we're done. */ 2260 return; 2261 } 2262 } 2263 } 2264 2265 static unsigned int sci_tx_empty(struct uart_port *port) 2266 { 2267 unsigned short status = sci_serial_in(port, SCxSR); 2268 unsigned short in_tx_fifo = sci_txfill(port); 2269 struct sci_port *s = to_sci_port(port); 2270 2271 sci_dma_check_tx_occurred(s); 2272 2273 if (!s->tx_occurred) 2274 return TIOCSER_TEMT; 2275 2276 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 2277 } 2278 2279 static void sci_set_rts(struct uart_port *port, bool state) 2280 { 2281 struct sci_port *s = to_sci_port(port); 2282 2283 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 2284 u16 data = sci_serial_in(port, SCPDR); 2285 2286 /* Active low */ 2287 if (state) 2288 data &= ~SCPDR_RTSD; 2289 else 2290 data |= SCPDR_RTSD; 2291 sci_serial_out(port, SCPDR, data); 2292 2293 /* RTS# is output */ 2294 sci_serial_out(port, SCPCR, 2295 sci_serial_in(port, SCPCR) | SCPCR_RTSC); 2296 } else if (sci_getreg(port, SCSPTR)->size) { 2297 u16 ctrl = sci_serial_in(port, SCSPTR); 2298 2299 /* Active low */ 2300 if (state) 2301 ctrl &= ~SCSPTR_RTSDT; 2302 else 2303 ctrl |= SCSPTR_RTSDT; 2304 sci_serial_out(port, SCSPTR, ctrl); 2305 } 2306 } 2307 2308 static bool sci_get_cts(struct uart_port *port) 2309 { 2310 struct sci_port *s = to_sci_port(port); 2311 2312 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 2313 /* Active low */ 2314 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD); 2315 } else if (sci_getreg(port, SCSPTR)->size) { 2316 /* Active low */ 2317 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT); 2318 } 2319 2320 return true; 2321 } 2322 2323 /* 2324 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2325 * CTS/RTS is supported in hardware by at least one port and controlled 2326 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2327 * handled via the ->init_pins() op, which is a bit of a one-way street, 2328 * lacking any ability to defer pin control -- this will later be 2329 * converted over to the GPIO framework). 2330 * 2331 * Other modes (such as loopback) are supported generically on certain 2332 * port types, but not others. For these it's sufficient to test for the 2333 * existence of the support register and simply ignore the port type. 2334 */ 2335 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2336 { 2337 struct sci_port *s = to_sci_port(port); 2338 2339 if (mctrl & TIOCM_LOOP) { 2340 const struct plat_sci_reg *reg; 2341 2342 /* 2343 * Standard loopback mode for SCFCR ports. 2344 */ 2345 reg = sci_getreg(port, SCFCR); 2346 if (reg->size) 2347 sci_serial_out(port, SCFCR, 2348 sci_serial_in(port, SCFCR) | SCFCR_LOOP); 2349 } 2350 2351 mctrl_gpio_set(s->gpios, mctrl); 2352 2353 if (!s->has_rtscts) 2354 return; 2355 2356 if (!(mctrl & TIOCM_RTS)) { 2357 /* Disable Auto RTS */ 2358 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2359 sci_serial_out(port, SCFCR, 2360 sci_serial_in(port, SCFCR) & ~SCFCR_MCE); 2361 2362 /* Clear RTS */ 2363 sci_set_rts(port, 0); 2364 } else if (s->autorts) { 2365 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { 2366 /* Enable RTS# pin function */ 2367 sci_serial_out(port, SCPCR, 2368 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC); 2369 } 2370 2371 /* Enable Auto RTS */ 2372 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE) 2373 sci_serial_out(port, SCFCR, 2374 sci_serial_in(port, SCFCR) | SCFCR_MCE); 2375 } else { 2376 /* Set RTS */ 2377 sci_set_rts(port, 1); 2378 } 2379 } 2380 2381 static unsigned int sci_get_mctrl(struct uart_port *port) 2382 { 2383 struct sci_port *s = to_sci_port(port); 2384 struct mctrl_gpios *gpios = s->gpios; 2385 unsigned int mctrl = 0; 2386 2387 mctrl_gpio_get(gpios, &mctrl); 2388 2389 /* 2390 * CTS/RTS is handled in hardware when supported, while nothing 2391 * else is wired up. 2392 */ 2393 if (s->autorts) { 2394 if (sci_get_cts(port)) 2395 mctrl |= TIOCM_CTS; 2396 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2397 mctrl |= TIOCM_CTS; 2398 } 2399 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2400 mctrl |= TIOCM_DSR; 2401 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2402 mctrl |= TIOCM_CAR; 2403 2404 return mctrl; 2405 } 2406 2407 static void sci_enable_ms(struct uart_port *port) 2408 { 2409 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2410 } 2411 2412 static void sci_break_ctl(struct uart_port *port, int break_state) 2413 { 2414 unsigned short scscr, scsptr; 2415 unsigned long flags; 2416 2417 /* check whether the port has SCSPTR */ 2418 if (!sci_getreg(port, SCSPTR)->size) { 2419 /* 2420 * Not supported by hardware. Most parts couple break and rx 2421 * interrupts together, with break detection always enabled. 2422 */ 2423 return; 2424 } 2425 2426 uart_port_lock_irqsave(port, &flags); 2427 scsptr = sci_serial_in(port, SCSPTR); 2428 scscr = sci_serial_in(port, SCSCR); 2429 2430 if (break_state == -1) { 2431 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2432 scscr &= ~SCSCR_TE; 2433 } else { 2434 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2435 scscr |= SCSCR_TE; 2436 } 2437 2438 sci_serial_out(port, SCSPTR, scsptr); 2439 sci_serial_out(port, SCSCR, scscr); 2440 uart_port_unlock_irqrestore(port, flags); 2441 } 2442 2443 static void sci_shutdown_complete(struct uart_port *port) 2444 { 2445 struct sci_port *s = to_sci_port(port); 2446 u16 scr; 2447 2448 scr = sci_serial_in(port, SCSCR); 2449 sci_serial_out(port, SCSCR, 2450 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2451 } 2452 2453 int sci_startup(struct uart_port *port) 2454 { 2455 struct sci_port *s = to_sci_port(port); 2456 int ret; 2457 2458 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2459 2460 s->tx_occurred = false; 2461 sci_request_dma(port); 2462 2463 ret = sci_request_irq(s); 2464 if (unlikely(ret < 0)) { 2465 sci_free_dma(port); 2466 return ret; 2467 } 2468 2469 return 0; 2470 } 2471 EXPORT_SYMBOL_NS_GPL(sci_startup, "SH_SCI"); 2472 2473 void sci_shutdown(struct uart_port *port) 2474 { 2475 struct sci_port *s = to_sci_port(port); 2476 unsigned long flags; 2477 2478 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2479 2480 s->autorts = false; 2481 mctrl_gpio_disable_ms_sync(to_sci_port(port)->gpios); 2482 2483 uart_port_lock_irqsave(port, &flags); 2484 s->port.ops->stop_rx(port); 2485 s->port.ops->stop_tx(port); 2486 s->ops->shutdown_complete(port); 2487 uart_port_unlock_irqrestore(port, flags); 2488 2489 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2490 if (s->chan_rx_saved) { 2491 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2492 port->line); 2493 hrtimer_cancel(&s->rx_timer); 2494 } 2495 #endif 2496 2497 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2498 timer_delete_sync(&s->rx_fifo_timer); 2499 sci_free_irq(s); 2500 sci_free_dma(port); 2501 } 2502 EXPORT_SYMBOL_NS_GPL(sci_shutdown, "SH_SCI"); 2503 2504 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2505 unsigned int *srr) 2506 { 2507 unsigned long freq = s->clk_rates[SCI_SCK]; 2508 int err, min_err = INT_MAX; 2509 unsigned int sr; 2510 2511 if (s->type != PORT_HSCIF) 2512 freq *= 2; 2513 2514 for_each_sr(sr, s) { 2515 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2516 if (abs(err) >= abs(min_err)) 2517 continue; 2518 2519 min_err = err; 2520 *srr = sr - 1; 2521 2522 if (!err) 2523 break; 2524 } 2525 2526 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2527 *srr + 1); 2528 return min_err; 2529 } 2530 2531 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2532 unsigned long freq, unsigned int *dlr, 2533 unsigned int *srr) 2534 { 2535 int err, min_err = INT_MAX; 2536 unsigned int sr, dl; 2537 2538 if (s->type != PORT_HSCIF) 2539 freq *= 2; 2540 2541 for_each_sr(sr, s) { 2542 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2543 dl = clamp(dl, 1U, 65535U); 2544 2545 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2546 if (abs(err) >= abs(min_err)) 2547 continue; 2548 2549 min_err = err; 2550 *dlr = dl; 2551 *srr = sr - 1; 2552 2553 if (!err) 2554 break; 2555 } 2556 2557 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2558 min_err, *dlr, *srr + 1); 2559 return min_err; 2560 } 2561 2562 /* calculate sample rate, BRR, and clock select */ 2563 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2564 unsigned int *brr, unsigned int *srr, 2565 unsigned int *cks) 2566 { 2567 unsigned long freq = s->clk_rates[SCI_FCK]; 2568 unsigned int sr, br, prediv, scrate, c; 2569 int err, min_err = INT_MAX; 2570 2571 if (s->type != PORT_HSCIF) 2572 freq *= 2; 2573 2574 /* 2575 * Find the combination of sample rate and clock select with the 2576 * smallest deviation from the desired baud rate. 2577 * Prefer high sample rates to maximise the receive margin. 2578 * 2579 * M: Receive margin (%) 2580 * N: Ratio of bit rate to clock (N = sampling rate) 2581 * D: Clock duty (D = 0 to 1.0) 2582 * L: Frame length (L = 9 to 12) 2583 * F: Absolute value of clock frequency deviation 2584 * 2585 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2586 * (|D - 0.5| / N * (1 + F))| 2587 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2588 */ 2589 for_each_sr(sr, s) { 2590 for (c = 0; c <= 3; c++) { 2591 /* integerized formulas from HSCIF documentation */ 2592 prediv = sr << (2 * c + 1); 2593 2594 /* 2595 * We need to calculate: 2596 * 2597 * br = freq / (prediv * bps) clamped to [1..256] 2598 * err = freq / (br * prediv) - bps 2599 * 2600 * Watch out for overflow when calculating the desired 2601 * sampling clock rate! 2602 */ 2603 if (bps > UINT_MAX / prediv) 2604 break; 2605 2606 scrate = prediv * bps; 2607 br = DIV_ROUND_CLOSEST(freq, scrate); 2608 br = clamp(br, 1U, 256U); 2609 2610 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2611 if (abs(err) >= abs(min_err)) 2612 continue; 2613 2614 min_err = err; 2615 *brr = br - 1; 2616 *srr = sr - 1; 2617 *cks = c; 2618 2619 if (!err) 2620 goto found; 2621 } 2622 } 2623 2624 found: 2625 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2626 min_err, *brr, *srr + 1, *cks); 2627 return min_err; 2628 } 2629 2630 static void sci_reset(struct uart_port *port) 2631 { 2632 const struct plat_sci_reg *reg; 2633 unsigned int status; 2634 struct sci_port *s = to_sci_port(port); 2635 2636 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2637 2638 reg = sci_getreg(port, SCFCR); 2639 if (reg->size) 2640 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2641 2642 s->ops->clear_SCxSR(port, 2643 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2644 SCxSR_BREAK_CLEAR(port)); 2645 if (sci_getreg(port, SCLSR)->size) { 2646 status = sci_serial_in(port, SCLSR); 2647 status &= ~(SCLSR_TO | SCLSR_ORER); 2648 sci_serial_out(port, SCLSR, status); 2649 } 2650 2651 if (s->rx_trigger > 1) { 2652 if (s->rx_fifo_timeout) { 2653 s->ops->set_rtrg(port, 1); 2654 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2655 } else { 2656 if (s->type == PORT_SCIFA || 2657 s->type == PORT_SCIFB) 2658 s->ops->set_rtrg(port, 1); 2659 else 2660 s->ops->set_rtrg(port, s->rx_trigger); 2661 } 2662 } 2663 } 2664 2665 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2666 const struct ktermios *old) 2667 { 2668 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2669 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2670 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2671 struct sci_port *s = to_sci_port(port); 2672 const struct plat_sci_reg *reg; 2673 int min_err = INT_MAX, err; 2674 unsigned long max_freq = 0; 2675 int best_clk = -1; 2676 unsigned long flags; 2677 2678 if ((termios->c_cflag & CSIZE) == CS7) { 2679 smr_val |= SCSMR_CHR; 2680 } else { 2681 termios->c_cflag &= ~CSIZE; 2682 termios->c_cflag |= CS8; 2683 } 2684 if (termios->c_cflag & PARENB) 2685 smr_val |= SCSMR_PE; 2686 if (termios->c_cflag & PARODD) 2687 smr_val |= SCSMR_PE | SCSMR_ODD; 2688 if (termios->c_cflag & CSTOPB) 2689 smr_val |= SCSMR_STOP; 2690 2691 /* 2692 * earlyprintk comes here early on with port->uartclk set to zero. 2693 * the clock framework is not up and running at this point so here 2694 * we assume that 115200 is the maximum baud rate. please note that 2695 * the baud rate is not programmed during earlyprintk - it is assumed 2696 * that the previous boot loader has enabled required clocks and 2697 * setup the baud rate generator hardware for us already. 2698 */ 2699 if (!port->uartclk) { 2700 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2701 goto done; 2702 } 2703 2704 for (i = 0; i < SCI_NUM_CLKS; i++) 2705 max_freq = max(max_freq, s->clk_rates[i]); 2706 2707 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2708 if (!baud) 2709 goto done; 2710 2711 /* 2712 * There can be multiple sources for the sampling clock. Find the one 2713 * that gives us the smallest deviation from the desired baud rate. 2714 */ 2715 2716 /* Optional Undivided External Clock */ 2717 if (s->clk_rates[SCI_SCK] && s->type != PORT_SCIFA && 2718 s->type != PORT_SCIFB) { 2719 err = sci_sck_calc(s, baud, &srr1); 2720 if (abs(err) < abs(min_err)) { 2721 best_clk = SCI_SCK; 2722 scr_val = SCSCR_CKE1; 2723 sccks = SCCKS_CKS; 2724 min_err = err; 2725 srr = srr1; 2726 if (!err) 2727 goto done; 2728 } 2729 } 2730 2731 /* Optional BRG Frequency Divided External Clock */ 2732 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2733 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2734 &srr1); 2735 if (abs(err) < abs(min_err)) { 2736 best_clk = SCI_SCIF_CLK; 2737 scr_val = SCSCR_CKE1; 2738 sccks = 0; 2739 min_err = err; 2740 dl = dl1; 2741 srr = srr1; 2742 if (!err) 2743 goto done; 2744 } 2745 } 2746 2747 /* Optional BRG Frequency Divided Internal Clock */ 2748 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2749 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2750 &srr1); 2751 if (abs(err) < abs(min_err)) { 2752 best_clk = SCI_BRG_INT; 2753 scr_val = SCSCR_CKE1; 2754 sccks = SCCKS_XIN; 2755 min_err = err; 2756 dl = dl1; 2757 srr = srr1; 2758 if (!min_err) 2759 goto done; 2760 } 2761 } 2762 2763 /* Divided Functional Clock using standard Bit Rate Register */ 2764 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2765 if (abs(err) < abs(min_err)) { 2766 best_clk = SCI_FCK; 2767 scr_val = 0; 2768 min_err = err; 2769 brr = brr1; 2770 srr = srr1; 2771 cks = cks1; 2772 } 2773 2774 done: 2775 if (best_clk >= 0) 2776 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2777 s->clks[best_clk], baud, min_err); 2778 2779 sci_port_enable(s); 2780 2781 /* 2782 * Program the optional External Baud Rate Generator (BRG) first. 2783 * It controls the mux to select (H)SCK or frequency divided clock. 2784 */ 2785 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2786 sci_serial_out(port, SCDL, dl); 2787 sci_serial_out(port, SCCKS, sccks); 2788 } 2789 2790 uart_port_lock_irqsave(port, &flags); 2791 2792 sci_reset(port); 2793 2794 uart_update_timeout(port, termios->c_cflag, baud); 2795 2796 /* byte size and parity */ 2797 bits = tty_get_frame_size(termios->c_cflag); 2798 2799 if (sci_getreg(port, SEMR)->size) 2800 sci_serial_out(port, SEMR, 0); 2801 2802 if (best_clk >= 0) { 2803 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) 2804 switch (srr + 1) { 2805 case 5: smr_val |= SCSMR_SRC_5; break; 2806 case 7: smr_val |= SCSMR_SRC_7; break; 2807 case 11: smr_val |= SCSMR_SRC_11; break; 2808 case 13: smr_val |= SCSMR_SRC_13; break; 2809 case 16: smr_val |= SCSMR_SRC_16; break; 2810 case 17: smr_val |= SCSMR_SRC_17; break; 2811 case 19: smr_val |= SCSMR_SRC_19; break; 2812 case 27: smr_val |= SCSMR_SRC_27; break; 2813 } 2814 smr_val |= cks; 2815 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2816 sci_serial_out(port, SCSMR, smr_val); 2817 sci_serial_out(port, SCBRR, brr); 2818 if (sci_getreg(port, HSSRR)->size) { 2819 unsigned int hssrr = srr | HSCIF_SRE; 2820 /* Calculate deviation from intended rate at the 2821 * center of the last stop bit in sampling clocks. 2822 */ 2823 int last_stop = bits * 2 - 1; 2824 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2825 (int)(srr + 1), 2826 2 * (int)baud); 2827 2828 if (abs(deviation) >= 2) { 2829 /* At least two sampling clocks off at the 2830 * last stop bit; we can increase the error 2831 * margin by shifting the sampling point. 2832 */ 2833 int shift = clamp(deviation / 2, -8, 7); 2834 2835 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2836 HSCIF_SRHP_MASK; 2837 hssrr |= HSCIF_SRDE; 2838 } 2839 sci_serial_out(port, HSSRR, hssrr); 2840 } 2841 2842 /* Wait one bit interval */ 2843 udelay((1000000 + (baud - 1)) / baud); 2844 } else { 2845 /* Don't touch the bit rate configuration */ 2846 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2847 smr_val |= sci_serial_in(port, SCSMR) & 2848 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2849 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2850 sci_serial_out(port, SCSMR, smr_val); 2851 } 2852 2853 sci_init_pins(port, termios->c_cflag); 2854 2855 port->status &= ~UPSTAT_AUTOCTS; 2856 s->autorts = false; 2857 reg = sci_getreg(port, SCFCR); 2858 if (reg->size) { 2859 unsigned short ctrl = sci_serial_in(port, SCFCR); 2860 2861 if ((port->flags & UPF_HARD_FLOW) && 2862 (termios->c_cflag & CRTSCTS)) { 2863 /* There is no CTS interrupt to restart the hardware */ 2864 port->status |= UPSTAT_AUTOCTS; 2865 /* MCE is enabled when RTS is raised */ 2866 s->autorts = true; 2867 } 2868 2869 /* 2870 * As we've done a sci_reset() above, ensure we don't 2871 * interfere with the FIFOs while toggling MCE. As the 2872 * reset values could still be set, simply mask them out. 2873 */ 2874 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2875 2876 sci_serial_out(port, SCFCR, ctrl); 2877 } 2878 if (port->flags & UPF_HARD_FLOW) { 2879 /* Refresh (Auto) RTS */ 2880 sci_set_mctrl(port, port->mctrl); 2881 } 2882 2883 /* 2884 * For SCI, TE (transmit enable) must be set after setting TIE 2885 * (transmit interrupt enable) or in the same instruction to 2886 * start the transmitting process. So skip setting TE here for SCI. 2887 */ 2888 if (s->type != PORT_SCI) 2889 scr_val |= SCSCR_TE; 2890 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2891 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2892 if ((srr + 1 == 5) && 2893 (s->type == PORT_SCIFA || s->type == PORT_SCIFB)) { 2894 /* 2895 * In asynchronous mode, when the sampling rate is 1/5, first 2896 * received data may become invalid on some SCIFA and SCIFB. 2897 * To avoid this problem wait more than 1 serial data time (1 2898 * bit time x serial data number) after setting SCSCR.RE = 1. 2899 */ 2900 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2901 } 2902 2903 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2904 s->rx_frame = (10000 * bits) / (baud / 100); 2905 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2906 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2907 #endif 2908 2909 if ((termios->c_cflag & CREAD) != 0) 2910 sci_start_rx(port); 2911 2912 uart_port_unlock_irqrestore(port, flags); 2913 2914 sci_port_disable(s); 2915 2916 if (UART_ENABLE_MS(port, termios->c_cflag)) 2917 sci_enable_ms(port); 2918 } 2919 2920 void sci_pm(struct uart_port *port, unsigned int state, 2921 unsigned int oldstate) 2922 { 2923 struct sci_port *sci_port = to_sci_port(port); 2924 2925 switch (state) { 2926 case UART_PM_STATE_OFF: 2927 sci_port_disable(sci_port); 2928 break; 2929 default: 2930 sci_port_enable(sci_port); 2931 break; 2932 } 2933 } 2934 EXPORT_SYMBOL_NS_GPL(sci_pm, "SH_SCI"); 2935 2936 static const char *sci_type(struct uart_port *port) 2937 { 2938 struct sci_port *s = to_sci_port(port); 2939 2940 switch (s->type) { 2941 case PORT_IRDA: 2942 return "irda"; 2943 case PORT_SCI: 2944 return "sci"; 2945 case PORT_SCIF: 2946 return "scif"; 2947 case PORT_SCIFA: 2948 return "scifa"; 2949 case PORT_SCIFB: 2950 return "scifb"; 2951 case PORT_HSCIF: 2952 return "hscif"; 2953 } 2954 2955 return NULL; 2956 } 2957 2958 static int sci_remap_port(struct uart_port *port) 2959 { 2960 struct sci_port *sport = to_sci_port(port); 2961 2962 /* 2963 * Nothing to do if there's already an established membase. 2964 */ 2965 if (port->membase) 2966 return 0; 2967 2968 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2969 port->membase = ioremap(port->mapbase, sport->reg_size); 2970 if (unlikely(!port->membase)) { 2971 dev_err(port->dev, "can't remap port#%d\n", port->line); 2972 return -ENXIO; 2973 } 2974 } else { 2975 /* 2976 * For the simple (and majority of) cases where we don't 2977 * need to do any remapping, just cast the cookie 2978 * directly. 2979 */ 2980 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2981 } 2982 2983 return 0; 2984 } 2985 2986 void sci_release_port(struct uart_port *port) 2987 { 2988 struct sci_port *sport = to_sci_port(port); 2989 2990 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2991 iounmap(port->membase); 2992 port->membase = NULL; 2993 } 2994 2995 release_mem_region(port->mapbase, sport->reg_size); 2996 } 2997 EXPORT_SYMBOL_NS_GPL(sci_release_port, "SH_SCI"); 2998 2999 int sci_request_port(struct uart_port *port) 3000 { 3001 struct resource *res; 3002 struct sci_port *sport = to_sci_port(port); 3003 int ret; 3004 3005 res = request_mem_region(port->mapbase, sport->reg_size, 3006 dev_name(port->dev)); 3007 if (unlikely(res == NULL)) { 3008 dev_err(port->dev, "request_mem_region failed."); 3009 return -EBUSY; 3010 } 3011 3012 ret = sci_remap_port(port); 3013 if (unlikely(ret != 0)) { 3014 release_resource(res); 3015 return ret; 3016 } 3017 3018 return 0; 3019 } 3020 EXPORT_SYMBOL_NS_GPL(sci_request_port, "SH_SCI"); 3021 3022 void sci_config_port(struct uart_port *port, int flags) 3023 { 3024 if (flags & UART_CONFIG_TYPE) { 3025 struct sci_port *sport = to_sci_port(port); 3026 port->type = SCI_PUBLIC_PORT_ID(sport->type); 3027 sci_request_port(port); 3028 } 3029 } 3030 EXPORT_SYMBOL_NS_GPL(sci_config_port, "SH_SCI"); 3031 3032 int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 3033 { 3034 if (ser->baud_base < 2400) 3035 /* No paper tape reader for Mitch.. */ 3036 return -EINVAL; 3037 3038 return 0; 3039 } 3040 EXPORT_SYMBOL_NS_GPL(sci_verify_port, "SH_SCI"); 3041 3042 static void sci_prepare_console_write(struct uart_port *port, u32 ctrl) 3043 { 3044 struct sci_port *s = to_sci_port(port); 3045 u32 ctrl_temp = 3046 s->params->param_bits->rxtx_enable | 3047 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3048 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)) | 3049 s->hscif_tot; 3050 sci_serial_out(port, SCSCR, ctrl_temp); 3051 } 3052 3053 static void sci_console_save(struct uart_port *port) 3054 { 3055 struct sci_port *s = to_sci_port(port); 3056 struct sci_suspend_regs *regs = s->suspend_regs; 3057 3058 if (sci_getreg(port, SCDL)->size) 3059 regs->scdl = sci_serial_in(port, SCDL); 3060 if (sci_getreg(port, SCCKS)->size) 3061 regs->sccks = sci_serial_in(port, SCCKS); 3062 if (sci_getreg(port, SCSMR)->size) 3063 regs->scsmr = sci_serial_in(port, SCSMR); 3064 if (sci_getreg(port, SCSCR)->size) 3065 regs->scscr = sci_serial_in(port, SCSCR); 3066 if (sci_getreg(port, SCFCR)->size) 3067 regs->scfcr = sci_serial_in(port, SCFCR); 3068 if (sci_getreg(port, SCSPTR)->size) 3069 regs->scsptr = sci_serial_in(port, SCSPTR); 3070 if (sci_getreg(port, SCBRR)->size) 3071 regs->scbrr = sci_serial_in(port, SCBRR); 3072 if (sci_getreg(port, HSSRR)->size) 3073 regs->hssrr = sci_serial_in(port, HSSRR); 3074 if (sci_getreg(port, SCPCR)->size) 3075 regs->scpcr = sci_serial_in(port, SCPCR); 3076 if (sci_getreg(port, SCPDR)->size) 3077 regs->scpdr = sci_serial_in(port, SCPDR); 3078 if (sci_getreg(port, SEMR)->size) 3079 regs->semr = sci_serial_in(port, SEMR); 3080 } 3081 3082 static void sci_console_restore(struct uart_port *port) 3083 { 3084 struct sci_port *s = to_sci_port(port); 3085 struct sci_suspend_regs *regs = s->suspend_regs; 3086 3087 if (sci_getreg(port, SCDL)->size) 3088 sci_serial_out(port, SCDL, regs->scdl); 3089 if (sci_getreg(port, SCCKS)->size) 3090 sci_serial_out(port, SCCKS, regs->sccks); 3091 if (sci_getreg(port, SCSMR)->size) 3092 sci_serial_out(port, SCSMR, regs->scsmr); 3093 if (sci_getreg(port, SCSCR)->size) 3094 sci_serial_out(port, SCSCR, regs->scscr); 3095 if (sci_getreg(port, SCFCR)->size) 3096 sci_serial_out(port, SCFCR, regs->scfcr); 3097 if (sci_getreg(port, SCSPTR)->size) 3098 sci_serial_out(port, SCSPTR, regs->scsptr); 3099 if (sci_getreg(port, SCBRR)->size) 3100 sci_serial_out(port, SCBRR, regs->scbrr); 3101 if (sci_getreg(port, HSSRR)->size) 3102 sci_serial_out(port, HSSRR, regs->hssrr); 3103 if (sci_getreg(port, SCPCR)->size) 3104 sci_serial_out(port, SCPCR, regs->scpcr); 3105 if (sci_getreg(port, SCPDR)->size) 3106 sci_serial_out(port, SCPDR, regs->scpdr); 3107 if (sci_getreg(port, SEMR)->size) 3108 sci_serial_out(port, SEMR, regs->semr); 3109 } 3110 3111 static const struct uart_ops sci_uart_ops = { 3112 .tx_empty = sci_tx_empty, 3113 .set_mctrl = sci_set_mctrl, 3114 .get_mctrl = sci_get_mctrl, 3115 .start_tx = sci_start_tx, 3116 .stop_tx = sci_stop_tx, 3117 .stop_rx = sci_stop_rx, 3118 .enable_ms = sci_enable_ms, 3119 .break_ctl = sci_break_ctl, 3120 .startup = sci_startup, 3121 .shutdown = sci_shutdown, 3122 .flush_buffer = sci_flush_buffer, 3123 .set_termios = sci_set_termios, 3124 .pm = sci_pm, 3125 .type = sci_type, 3126 .release_port = sci_release_port, 3127 .request_port = sci_request_port, 3128 .config_port = sci_config_port, 3129 .verify_port = sci_verify_port, 3130 #ifdef CONFIG_CONSOLE_POLL 3131 .poll_get_char = sci_poll_get_char, 3132 .poll_put_char = sci_poll_put_char, 3133 #endif 3134 }; 3135 3136 static const struct sci_port_ops sci_port_ops = { 3137 .read_reg = sci_serial_in, 3138 .write_reg = sci_serial_out, 3139 .clear_SCxSR = sci_clear_SCxSR, 3140 .transmit_chars = sci_transmit_chars, 3141 .receive_chars = sci_receive_chars, 3142 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3143 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3144 .poll_put_char = sci_poll_put_char, 3145 #endif 3146 .set_rtrg = scif_set_rtrg, 3147 .rtrg_enabled = scif_rtrg_enabled, 3148 .shutdown_complete = sci_shutdown_complete, 3149 .prepare_console_write = sci_prepare_console_write, 3150 .console_save = sci_console_save, 3151 .console_restore = sci_console_restore, 3152 .suspend_regs_size = sci_suspend_regs_size, 3153 }; 3154 3155 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 3156 { 3157 const char *clk_names[] = { 3158 [SCI_FCK] = "fck", 3159 [SCI_SCK] = "sck", 3160 [SCI_BRG_INT] = "brg_int", 3161 [SCI_SCIF_CLK] = "scif_clk", 3162 }; 3163 struct clk *clk; 3164 unsigned int i; 3165 3166 if (sci_port->type == PORT_HSCIF) { 3167 clk_names[SCI_SCK] = "hsck"; 3168 } else if (sci_port->type == SCI_PORT_RSCI) { 3169 clk_names[SCI_FCK] = "operation"; 3170 clk_names[SCI_BRG_INT] = "bus"; 3171 } 3172 3173 for (i = 0; i < SCI_NUM_CLKS; i++) { 3174 const char *name = clk_names[i]; 3175 3176 clk = devm_clk_get_optional(dev, name); 3177 if (IS_ERR(clk)) 3178 return PTR_ERR(clk); 3179 3180 if (!clk && sci_port->type == SCI_PORT_RSCI && 3181 (i == SCI_FCK || i == SCI_BRG_INT)) { 3182 return dev_err_probe(dev, -ENODEV, 3183 "failed to get %s\n", 3184 name); 3185 } 3186 3187 if (!clk && i == SCI_FCK) { 3188 /* 3189 * Not all SH platforms declare a clock lookup entry 3190 * for SCI devices, in which case we need to get the 3191 * global "peripheral_clk" clock. 3192 */ 3193 clk = devm_clk_get(dev, "peripheral_clk"); 3194 if (IS_ERR(clk)) 3195 return dev_err_probe(dev, PTR_ERR(clk), 3196 "failed to get %s\n", 3197 name); 3198 } 3199 3200 if (!clk) 3201 dev_dbg(dev, "failed to get %s\n", name); 3202 else 3203 dev_dbg(dev, "clk %s is %pC rate %lu\n", name, 3204 clk, clk_get_rate(clk)); 3205 sci_port->clks[i] = clk; 3206 } 3207 return 0; 3208 } 3209 3210 static const struct sci_port_params * 3211 sci_probe_regmap(const struct plat_sci_port *cfg, struct sci_port *sci_port) 3212 { 3213 unsigned int regtype; 3214 3215 sci_port->ops = &sci_port_ops; 3216 sci_port->port.ops = &sci_uart_ops; 3217 3218 if (cfg->regtype != SCIx_PROBE_REGTYPE) 3219 return &sci_port_params[cfg->regtype]; 3220 3221 switch (cfg->type) { 3222 case PORT_SCI: 3223 regtype = SCIx_SCI_REGTYPE; 3224 break; 3225 case PORT_IRDA: 3226 regtype = SCIx_IRDA_REGTYPE; 3227 break; 3228 case PORT_SCIFA: 3229 regtype = SCIx_SCIFA_REGTYPE; 3230 break; 3231 case PORT_SCIFB: 3232 regtype = SCIx_SCIFB_REGTYPE; 3233 break; 3234 case PORT_SCIF: 3235 /* 3236 * The SH-4 is a bit of a misnomer here, although that's 3237 * where this particular port layout originated. This 3238 * configuration (or some slight variation thereof) 3239 * remains the dominant model for all SCIFs. 3240 */ 3241 regtype = SCIx_SH4_SCIF_REGTYPE; 3242 break; 3243 case PORT_HSCIF: 3244 regtype = SCIx_HSCIF_REGTYPE; 3245 break; 3246 default: 3247 pr_err("Can't probe register map for given port\n"); 3248 return NULL; 3249 } 3250 3251 return &sci_port_params[regtype]; 3252 } 3253 3254 static int sci_init_single(struct platform_device *dev, 3255 struct sci_port *sci_port, unsigned int index, 3256 const struct plat_sci_port *p, bool early) 3257 { 3258 struct uart_port *port = &sci_port->port; 3259 const struct resource *res; 3260 unsigned int i; 3261 int ret; 3262 3263 sci_port->cfg = p; 3264 3265 sci_port->type = p->type; 3266 sci_port->regtype = p->regtype; 3267 3268 port->iotype = UPIO_MEM; 3269 port->line = index; 3270 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 3271 3272 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 3273 if (res == NULL) 3274 return -ENOMEM; 3275 3276 port->mapbase = res->start; 3277 sci_port->reg_size = resource_size(res); 3278 3279 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 3280 if (i) 3281 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 3282 else 3283 sci_port->irqs[i] = platform_get_irq(dev, i); 3284 } 3285 3286 /* 3287 * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so 3288 * shuffle the interrupts. 3289 */ 3290 if (p->type == PORT_SCI || p->type == SCI_PORT_RSCI) 3291 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); 3292 3293 /* The SCI generates several interrupts. They can be muxed together or 3294 * connected to different interrupt lines. In the muxed case only one 3295 * interrupt resource is specified as there is only one interrupt ID. 3296 * In the non-muxed case, up to 6 interrupt signals might be generated 3297 * from the SCI, however those signals might have their own individual 3298 * interrupt ID numbers, or muxed together with another interrupt. 3299 */ 3300 if (sci_port->irqs[0] < 0) 3301 return -ENXIO; 3302 3303 if (sci_port->irqs[1] < 0) 3304 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 3305 sci_port->irqs[i] = sci_port->irqs[0]; 3306 3307 switch (p->type) { 3308 case PORT_SCIFB: 3309 sci_port->rx_trigger = 48; 3310 break; 3311 case PORT_HSCIF: 3312 sci_port->rx_trigger = 64; 3313 break; 3314 case PORT_SCIFA: 3315 sci_port->rx_trigger = 32; 3316 break; 3317 case PORT_SCIF: 3318 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 3319 /* RX triggering not implemented for this IP */ 3320 sci_port->rx_trigger = 1; 3321 else 3322 sci_port->rx_trigger = 8; 3323 break; 3324 case SCI_PORT_RSCI: 3325 sci_port->rx_trigger = 15; 3326 break; 3327 default: 3328 sci_port->rx_trigger = 1; 3329 break; 3330 } 3331 3332 sci_port->rx_fifo_timeout = 0; 3333 sci_port->hscif_tot = 0; 3334 3335 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 3336 * match the SoC datasheet, this should be investigated. Let platform 3337 * data override the sampling rate for now. 3338 */ 3339 sci_port->sampling_rate_mask = p->sampling_rate 3340 ? SCI_SR(p->sampling_rate) 3341 : sci_port->params->sampling_rate_mask; 3342 3343 if (!early) { 3344 ret = sci_init_clocks(sci_port, &dev->dev); 3345 if (ret < 0) 3346 return ret; 3347 } 3348 3349 port->type = SCI_PUBLIC_PORT_ID(p->type); 3350 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 3351 port->fifosize = sci_port->params->fifosize; 3352 3353 if (p->type == PORT_SCI && !dev->dev.of_node) { 3354 if (sci_port->reg_size >= 0x20) 3355 port->regshift = 2; 3356 else 3357 port->regshift = 1; 3358 } 3359 3360 /* 3361 * The UART port needs an IRQ value, so we peg this to the RX IRQ 3362 * for the multi-IRQ ports, which is where we are primarily 3363 * concerned with the shutdown path synchronization. 3364 * 3365 * For the muxed case there's nothing more to do. 3366 */ 3367 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 3368 port->irqflags = 0; 3369 3370 return 0; 3371 } 3372 3373 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3374 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3375 static void serial_console_putchar(struct uart_port *port, unsigned char ch) 3376 { 3377 to_sci_port(port)->ops->poll_put_char(port, ch); 3378 } 3379 3380 /* 3381 * Print a string to the serial port trying not to disturb 3382 * any possible real use of the port... 3383 */ 3384 static void serial_console_write(struct console *co, const char *s, 3385 unsigned count) 3386 { 3387 struct sci_port *sci_port = &sci_ports[co->index]; 3388 struct uart_port *port = &sci_port->port; 3389 const struct sci_common_regs *regs = sci_port->params->common_regs; 3390 unsigned int bits; 3391 u32 ctrl; 3392 unsigned long flags; 3393 int locked = 1; 3394 3395 if (port->sysrq) 3396 locked = 0; 3397 else if (oops_in_progress) 3398 locked = uart_port_trylock_irqsave(port, &flags); 3399 else 3400 uart_port_lock_irqsave(port, &flags); 3401 3402 /* first save SCSCR then disable interrupts, keep clock source */ 3403 3404 ctrl = sci_port->ops->read_reg(port, regs->control); 3405 sci_port->ops->prepare_console_write(port, ctrl); 3406 3407 uart_console_write(port, s, count, serial_console_putchar); 3408 3409 /* wait until fifo is empty and last bit has been transmitted */ 3410 3411 bits = sci_port->params->param_bits->poll_sent_bits; 3412 3413 while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits) 3414 cpu_relax(); 3415 3416 /* restore the SCSCR */ 3417 sci_port->ops->write_reg(port, regs->control, ctrl); 3418 3419 if (locked) 3420 uart_port_unlock_irqrestore(port, flags); 3421 } 3422 3423 static int serial_console_setup(struct console *co, char *options) 3424 { 3425 struct sci_port *sci_port; 3426 struct uart_port *port; 3427 int baud = 115200; 3428 int bits = 8; 3429 int parity = 'n'; 3430 int flow = 'n'; 3431 int ret; 3432 3433 /* 3434 * Refuse to handle any bogus ports. 3435 */ 3436 if (co->index < 0 || co->index >= SCI_NPORTS) 3437 return -ENODEV; 3438 3439 sci_port = &sci_ports[co->index]; 3440 port = &sci_port->port; 3441 3442 /* 3443 * Refuse to handle uninitialized ports. 3444 */ 3445 if (!port->ops) 3446 return -ENODEV; 3447 3448 ret = sci_remap_port(port); 3449 if (unlikely(ret != 0)) 3450 return ret; 3451 3452 if (options) 3453 uart_parse_options(options, &baud, &parity, &bits, &flow); 3454 3455 return uart_set_options(port, co, baud, parity, bits, flow); 3456 } 3457 3458 static struct console serial_console = { 3459 .name = "ttySC", 3460 .device = uart_console_device, 3461 .write = serial_console_write, 3462 .setup = serial_console_setup, 3463 .flags = CON_PRINTBUFFER, 3464 .index = -1, 3465 .data = &sci_uart_driver, 3466 }; 3467 3468 #ifdef CONFIG_SUPERH 3469 static char early_serial_buf[32]; 3470 3471 static int early_serial_console_setup(struct console *co, char *options) 3472 { 3473 /* 3474 * This early console is always registered using the earlyprintk= 3475 * parameter, which does not call add_preferred_console(). Thus 3476 * @options is always NULL and the options for this early console 3477 * are passed using a custom buffer. 3478 */ 3479 WARN_ON(options); 3480 3481 return serial_console_setup(co, early_serial_buf); 3482 } 3483 3484 static struct console early_serial_console = { 3485 .name = "early_ttySC", 3486 .write = serial_console_write, 3487 .setup = early_serial_console_setup, 3488 .flags = CON_PRINTBUFFER, 3489 .index = -1, 3490 }; 3491 3492 static int sci_probe_earlyprintk(struct platform_device *pdev) 3493 { 3494 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3495 struct sci_port *sp = &sci_ports[pdev->id]; 3496 3497 if (early_serial_console.data) 3498 return -EEXIST; 3499 3500 early_serial_console.index = pdev->id; 3501 3502 sp->params = sci_probe_regmap(cfg, sp); 3503 if (!sp->params) 3504 return -ENODEV; 3505 3506 sci_init_single(pdev, sp, pdev->id, cfg, true); 3507 3508 if (!strstr(early_serial_buf, "keep")) 3509 early_serial_console.flags |= CON_BOOT; 3510 3511 register_console(&early_serial_console); 3512 return 0; 3513 } 3514 #endif 3515 3516 #define SCI_CONSOLE (&serial_console) 3517 3518 #else 3519 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3520 { 3521 return -EINVAL; 3522 } 3523 3524 #define SCI_CONSOLE NULL 3525 3526 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3527 3528 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3529 3530 static DEFINE_MUTEX(sci_uart_registration_lock); 3531 static struct uart_driver sci_uart_driver = { 3532 .owner = THIS_MODULE, 3533 .driver_name = "sci", 3534 .dev_name = "ttySC", 3535 .major = SCI_MAJOR, 3536 .minor = SCI_MINOR_START, 3537 .nr = SCI_NPORTS, 3538 .cons = SCI_CONSOLE, 3539 }; 3540 3541 static void sci_remove(struct platform_device *dev) 3542 { 3543 struct sci_port *s = platform_get_drvdata(dev); 3544 unsigned int type = s->type; /* uart_remove_... clears it */ 3545 3546 sci_ports_in_use &= ~BIT(s->port.line); 3547 uart_remove_one_port(&sci_uart_driver, &s->port); 3548 3549 if (s->port.fifosize > 1) 3550 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3551 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF || 3552 type == SCI_PORT_RSCI) 3553 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3554 } 3555 3556 static const struct sci_of_data of_sci_scif_sh2 = { 3557 .type = PORT_SCIF, 3558 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 3559 .ops = &sci_port_ops, 3560 .uart_ops = &sci_uart_ops, 3561 .params = &sci_port_params[SCIx_SH2_SCIF_FIFODATA_REGTYPE], 3562 }; 3563 3564 static const struct sci_of_data of_sci_scif_rz_scifa = { 3565 .type = PORT_SCIF, 3566 .regtype = SCIx_RZ_SCIFA_REGTYPE, 3567 .ops = &sci_port_ops, 3568 .uart_ops = &sci_uart_ops, 3569 .params = &sci_port_params[SCIx_RZ_SCIFA_REGTYPE], 3570 }; 3571 3572 static const struct sci_of_data of_sci_scif_rzv2h = { 3573 .type = PORT_SCIF, 3574 .regtype = SCIx_RZV2H_SCIF_REGTYPE, 3575 .ops = &sci_port_ops, 3576 .uart_ops = &sci_uart_ops, 3577 .params = &sci_port_params[SCIx_RZV2H_SCIF_REGTYPE], 3578 }; 3579 3580 static const struct sci_of_data of_sci_rcar_scif = { 3581 .type = PORT_SCIF, 3582 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE, 3583 .ops = &sci_port_ops, 3584 .uart_ops = &sci_uart_ops, 3585 .params = &sci_port_params[SCIx_SH4_SCIF_BRG_REGTYPE], 3586 }; 3587 3588 static const struct sci_of_data of_sci_scif_sh4 = { 3589 .type = PORT_SCIF, 3590 .regtype = SCIx_SH4_SCIF_REGTYPE, 3591 .ops = &sci_port_ops, 3592 .uart_ops = &sci_uart_ops, 3593 .params = &sci_port_params[SCIx_SH4_SCIF_REGTYPE], 3594 }; 3595 3596 static const struct sci_of_data of_sci_scifa = { 3597 .type = PORT_SCIFA, 3598 .regtype = SCIx_SCIFA_REGTYPE, 3599 .ops = &sci_port_ops, 3600 .uart_ops = &sci_uart_ops, 3601 .params = &sci_port_params[SCIx_SCIFA_REGTYPE], 3602 }; 3603 3604 static const struct sci_of_data of_sci_scifb = { 3605 .type = PORT_SCIFB, 3606 .regtype = SCIx_SCIFB_REGTYPE, 3607 .ops = &sci_port_ops, 3608 .uart_ops = &sci_uart_ops, 3609 .params = &sci_port_params[SCIx_SCIFB_REGTYPE], 3610 }; 3611 3612 static const struct sci_of_data of_sci_hscif = { 3613 .type = PORT_HSCIF, 3614 .regtype = SCIx_HSCIF_REGTYPE, 3615 .ops = &sci_port_ops, 3616 .uart_ops = &sci_uart_ops, 3617 .params = &sci_port_params[SCIx_HSCIF_REGTYPE], 3618 }; 3619 3620 static const struct sci_of_data of_sci_sci = { 3621 .type = PORT_SCI, 3622 .regtype = SCIx_SCI_REGTYPE, 3623 .ops = &sci_port_ops, 3624 .uart_ops = &sci_uart_ops, 3625 .params = &sci_port_params[SCIx_SCI_REGTYPE], 3626 }; 3627 3628 static const struct of_device_id of_sci_match[] __maybe_unused = { 3629 /* SoC-specific types */ 3630 { 3631 .compatible = "renesas,scif-r7s72100", 3632 .data = &of_sci_scif_sh2, 3633 }, 3634 { 3635 .compatible = "renesas,scif-r7s9210", 3636 .data = &of_sci_scif_rz_scifa, 3637 }, 3638 { 3639 .compatible = "renesas,scif-r9a07g044", 3640 .data = &of_sci_scif_rz_scifa, 3641 }, 3642 { 3643 .compatible = "renesas,scif-r9a09g057", 3644 .data = &of_sci_scif_rzv2h, 3645 }, 3646 #ifdef CONFIG_SERIAL_RSCI 3647 { 3648 .compatible = "renesas,r9a09g077-rsci", 3649 .data = &of_sci_rsci_data, 3650 }, 3651 #endif /* CONFIG_SERIAL_RSCI */ 3652 /* Family-specific types */ 3653 { 3654 .compatible = "renesas,rcar-gen1-scif", 3655 .data = &of_sci_rcar_scif, 3656 }, { 3657 .compatible = "renesas,rcar-gen2-scif", 3658 .data = &of_sci_rcar_scif, 3659 }, { 3660 .compatible = "renesas,rcar-gen3-scif", 3661 .data = &of_sci_rcar_scif 3662 }, { 3663 .compatible = "renesas,rcar-gen4-scif", 3664 .data = &of_sci_rcar_scif 3665 }, { 3666 .compatible = "renesas,rcar-gen5-scif", 3667 .data = &of_sci_rcar_scif 3668 }, 3669 /* Generic types */ 3670 { 3671 .compatible = "renesas,scif", 3672 .data = &of_sci_scif_sh4, 3673 }, { 3674 .compatible = "renesas,scifa", 3675 .data = &of_sci_scifa, 3676 }, { 3677 .compatible = "renesas,scifb", 3678 .data = &of_sci_scifb, 3679 }, { 3680 .compatible = "renesas,hscif", 3681 .data = &of_sci_hscif, 3682 }, { 3683 .compatible = "renesas,sci", 3684 .data = &of_sci_sci, 3685 }, { 3686 /* Terminator */ 3687 }, 3688 }; 3689 MODULE_DEVICE_TABLE(of, of_sci_match); 3690 3691 static void sci_reset_control_assert(void *data) 3692 { 3693 reset_control_assert(data); 3694 } 3695 3696 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3697 unsigned int *dev_id) 3698 { 3699 struct device_node *np = pdev->dev.of_node; 3700 struct reset_control *rstc; 3701 struct plat_sci_port *p; 3702 struct sci_port *sp; 3703 const struct sci_of_data *data; 3704 int id, ret; 3705 3706 if (!IS_ENABLED(CONFIG_OF) || !np) 3707 return ERR_PTR(-EINVAL); 3708 3709 data = of_device_get_match_data(&pdev->dev); 3710 3711 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3712 if (IS_ERR(rstc)) 3713 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3714 "failed to get reset ctrl\n")); 3715 3716 ret = reset_control_deassert(rstc); 3717 if (ret) { 3718 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3719 return ERR_PTR(ret); 3720 } 3721 3722 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3723 if (ret) { 3724 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3725 ret); 3726 return ERR_PTR(ret); 3727 } 3728 3729 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3730 if (!p) 3731 return ERR_PTR(-ENOMEM); 3732 3733 /* Get the line number from the aliases node. */ 3734 id = of_alias_get_id(np, "serial"); 3735 if (id < 0 && ~sci_ports_in_use) 3736 id = ffz(sci_ports_in_use); 3737 if (id < 0) { 3738 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3739 return ERR_PTR(-EINVAL); 3740 } 3741 if (id >= ARRAY_SIZE(sci_ports)) { 3742 dev_err(&pdev->dev, "serial%d out of range\n", id); 3743 return ERR_PTR(-EINVAL); 3744 } 3745 3746 sp = &sci_ports[id]; 3747 sp->rstc = rstc; 3748 *dev_id = id; 3749 3750 p->type = data->type; 3751 p->regtype = data->regtype; 3752 3753 sp->ops = data->ops; 3754 sp->port.ops = data->uart_ops; 3755 sp->params = data->params; 3756 3757 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3758 3759 return p; 3760 } 3761 3762 static int sci_probe_single(struct platform_device *dev, 3763 unsigned int index, 3764 struct plat_sci_port *p, 3765 struct sci_port *sciport, 3766 struct resource *sci_res) 3767 { 3768 int ret; 3769 3770 /* Sanity check */ 3771 if (unlikely(index >= SCI_NPORTS)) { 3772 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3773 index+1, SCI_NPORTS); 3774 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3775 return -EINVAL; 3776 } 3777 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3778 if (sci_ports_in_use & BIT(index)) 3779 return -EBUSY; 3780 3781 mutex_lock(&sci_uart_registration_lock); 3782 if (!sci_uart_driver.state) { 3783 ret = uart_register_driver(&sci_uart_driver); 3784 if (ret) { 3785 mutex_unlock(&sci_uart_registration_lock); 3786 return ret; 3787 } 3788 } 3789 mutex_unlock(&sci_uart_registration_lock); 3790 3791 ret = sci_init_single(dev, sciport, index, p, false); 3792 if (ret) 3793 return ret; 3794 3795 sciport->port.dev = &dev->dev; 3796 ret = devm_pm_runtime_enable(&dev->dev); 3797 if (ret) 3798 return ret; 3799 3800 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3801 if (IS_ERR(sciport->gpios)) 3802 return PTR_ERR(sciport->gpios); 3803 3804 if (sciport->has_rtscts) { 3805 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3806 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3807 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3808 return -EINVAL; 3809 } 3810 sciport->port.flags |= UPF_HARD_FLOW; 3811 } 3812 3813 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) { 3814 /* 3815 * In case: 3816 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and 3817 * - it now maps to an alias other than zero and 3818 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is 3819 * available in bootargs) 3820 * 3821 * we need to avoid disabling clocks and PM domains through the runtime 3822 * PM APIs called in __device_attach(). For this, increment the runtime 3823 * PM reference counter (the clocks and PM domains were already enabled 3824 * by the bootloader). Otherwise the earlycon may access the HW when it 3825 * has no clocks enabled leading to failures (infinite loop in 3826 * sci_poll_put_char()). 3827 */ 3828 pm_runtime_get_noresume(&dev->dev); 3829 3830 /* 3831 * Skip cleanup the sci_port[0] in early_console_exit(), this 3832 * port is the same as the earlycon one. 3833 */ 3834 sci_uart_earlycon_dev_probing = true; 3835 } 3836 3837 return uart_add_one_port(&sci_uart_driver, &sciport->port); 3838 } 3839 3840 static int sci_probe(struct platform_device *dev) 3841 { 3842 struct plat_sci_port *p; 3843 struct resource *res; 3844 struct sci_port *sp; 3845 unsigned int dev_id; 3846 int ret; 3847 3848 /* 3849 * If we've come here via earlyprintk initialization, head off to 3850 * the special early probe. We don't have sufficient device state 3851 * to make it beyond this yet. 3852 */ 3853 #ifdef CONFIG_SUPERH 3854 if (is_sh_early_platform_device(dev)) 3855 return sci_probe_earlyprintk(dev); 3856 #endif 3857 3858 if (dev->dev.of_node) { 3859 p = sci_parse_dt(dev, &dev_id); 3860 if (IS_ERR(p)) 3861 return PTR_ERR(p); 3862 sp = &sci_ports[dev_id]; 3863 } else { 3864 p = dev->dev.platform_data; 3865 if (p == NULL) { 3866 dev_err(&dev->dev, "no platform data supplied\n"); 3867 return -EINVAL; 3868 } 3869 3870 dev_id = dev->id; 3871 sp = &sci_ports[dev_id]; 3872 sp->params = sci_probe_regmap(p, sp); 3873 if (!sp->params) 3874 return -ENODEV; 3875 } 3876 3877 sp->suspend_regs = devm_kzalloc(&dev->dev, 3878 sp->ops->suspend_regs_size(), 3879 GFP_KERNEL); 3880 if (!sp->suspend_regs) 3881 return -ENOMEM; 3882 3883 /* 3884 * In case: 3885 * - the probed port alias is zero (as the one used by earlycon), and 3886 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in 3887 * bootargs) 3888 * 3889 * defer the probe of this serial. This is a debug scenario and the user 3890 * must be aware of it. 3891 * 3892 * Except when the probed port is the same as the earlycon port. 3893 */ 3894 3895 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 3896 if (!res) 3897 return -ENODEV; 3898 3899 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start) 3900 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n"); 3901 3902 platform_set_drvdata(dev, sp); 3903 3904 ret = sci_probe_single(dev, dev_id, p, sp, res); 3905 if (ret) 3906 return ret; 3907 3908 if (sp->port.fifosize > 1) { 3909 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3910 if (ret) 3911 return ret; 3912 } 3913 if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB || 3914 sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) { 3915 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3916 if (ret) { 3917 if (sp->port.fifosize > 1) { 3918 device_remove_file(&dev->dev, 3919 &dev_attr_rx_fifo_trigger); 3920 } 3921 return ret; 3922 } 3923 } 3924 3925 #ifdef CONFIG_SH_STANDARD_BIOS 3926 sh_bios_gdb_detach(); 3927 #endif 3928 3929 sci_ports_in_use |= BIT(dev_id); 3930 return 0; 3931 } 3932 3933 static int sci_suspend(struct device *dev) 3934 { 3935 struct sci_port *sport = dev_get_drvdata(dev); 3936 3937 if (sport) { 3938 uart_suspend_port(&sci_uart_driver, &sport->port); 3939 3940 if (!console_suspend_enabled && uart_console(&sport->port)) { 3941 if (sport->ops->console_save) 3942 sport->ops->console_save(&sport->port); 3943 } 3944 else 3945 return reset_control_assert(sport->rstc); 3946 } 3947 3948 return 0; 3949 } 3950 3951 static int sci_resume(struct device *dev) 3952 { 3953 struct sci_port *sport = dev_get_drvdata(dev); 3954 3955 if (sport) { 3956 if (!console_suspend_enabled && uart_console(&sport->port)) { 3957 if (sport->ops->console_restore) 3958 sport->ops->console_restore(&sport->port); 3959 } else { 3960 int ret = reset_control_deassert(sport->rstc); 3961 3962 if (ret) 3963 return ret; 3964 } 3965 3966 uart_resume_port(&sci_uart_driver, &sport->port); 3967 } 3968 3969 return 0; 3970 } 3971 3972 static DEFINE_SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3973 3974 static struct platform_driver sci_driver = { 3975 .probe = sci_probe, 3976 .remove = sci_remove, 3977 .driver = { 3978 .name = "sh-sci", 3979 .pm = pm_sleep_ptr(&sci_dev_pm_ops), 3980 .of_match_table = of_match_ptr(of_sci_match), 3981 }, 3982 }; 3983 3984 static int __init sci_init(void) 3985 { 3986 pr_info("%s\n", banner); 3987 3988 return platform_driver_register(&sci_driver); 3989 } 3990 3991 static void __exit sci_exit(void) 3992 { 3993 platform_driver_unregister(&sci_driver); 3994 3995 if (sci_uart_driver.state) 3996 uart_unregister_driver(&sci_uart_driver); 3997 } 3998 3999 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 4000 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 4001 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 4002 #endif 4003 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 4004 static struct plat_sci_port port_cfg; 4005 4006 static int early_console_exit(struct console *co) 4007 { 4008 struct sci_port *sci_port = &sci_ports[0]; 4009 4010 /* 4011 * Clean the slot used by earlycon. A new SCI device might 4012 * map to this slot. 4013 */ 4014 if (!sci_uart_earlycon_dev_probing) { 4015 memset(sci_port, 0, sizeof(*sci_port)); 4016 sci_uart_earlycon = false; 4017 } 4018 4019 return 0; 4020 } 4021 4022 int __init scix_early_console_setup(struct earlycon_device *device, 4023 const struct sci_of_data *data) 4024 { 4025 const struct sci_common_regs *regs; 4026 4027 if (!device->port.membase) 4028 return -ENODEV; 4029 4030 device->port.type = SCI_PUBLIC_PORT_ID(data->type); 4031 4032 sci_ports[0].port = device->port; 4033 sci_ports[0].type = data->type; 4034 sci_ports[0].regtype = data->regtype; 4035 4036 port_cfg.type = data->type; 4037 port_cfg.regtype = data->regtype; 4038 4039 sci_ports[0].cfg = &port_cfg; 4040 sci_ports[0].params = data->params; 4041 sci_ports[0].ops = data->ops; 4042 sci_ports[0].port.ops = data->uart_ops; 4043 sci_uart_earlycon = true; 4044 regs = sci_ports[0].params->common_regs; 4045 4046 port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control); 4047 sci_ports[0].ops->write_reg(&sci_ports[0].port, 4048 regs->control, 4049 sci_ports[0].params->param_bits->rxtx_enable | port_cfg.scscr); 4050 4051 device->con->write = serial_console_write; 4052 device->con->exit = early_console_exit; 4053 4054 return 0; 4055 } 4056 static int __init sci_early_console_setup(struct earlycon_device *device, 4057 const char *opt) 4058 { 4059 return scix_early_console_setup(device, &of_sci_sci); 4060 } 4061 static int __init scif_early_console_setup(struct earlycon_device *device, 4062 const char *opt) 4063 { 4064 return scix_early_console_setup(device, &of_sci_scif_sh4); 4065 } 4066 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 4067 const char *opt) 4068 { 4069 return scix_early_console_setup(device, &of_sci_scif_rz_scifa); 4070 } 4071 4072 static int __init rzv2hscif_early_console_setup(struct earlycon_device *device, 4073 const char *opt) 4074 { 4075 return scix_early_console_setup(device, &of_sci_scif_rzv2h); 4076 } 4077 4078 static int __init scifa_early_console_setup(struct earlycon_device *device, 4079 const char *opt) 4080 { 4081 return scix_early_console_setup(device, &of_sci_scifa); 4082 } 4083 static int __init scifb_early_console_setup(struct earlycon_device *device, 4084 const char *opt) 4085 { 4086 return scix_early_console_setup(device, &of_sci_scifb); 4087 } 4088 static int __init hscif_early_console_setup(struct earlycon_device *device, 4089 const char *opt) 4090 { 4091 return scix_early_console_setup(device, &of_sci_hscif); 4092 } 4093 4094 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 4095 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 4096 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 4097 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 4098 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup); 4099 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 4100 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 4101 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 4102 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 4103 4104 module_init(sci_init); 4105 module_exit(sci_exit); 4106 4107 MODULE_LICENSE("GPL"); 4108 MODULE_ALIAS("platform:sh-sci"); 4109 MODULE_AUTHOR("Paul Mundt"); 4110 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 4111