1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/module.h> 35 #include <linux/mm.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/platform_device.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/reset.h> 41 #include <linux/scatterlist.h> 42 #include <linux/serial.h> 43 #include <linux/serial_sci.h> 44 #include <linux/sh_dma.h> 45 #include <linux/slab.h> 46 #include <linux/string.h> 47 #include <linux/sysrq.h> 48 #include <linux/timer.h> 49 #include <linux/tty.h> 50 #include <linux/tty_flip.h> 51 52 #ifdef CONFIG_SUPERH 53 #include <asm/sh_bios.h> 54 #include <asm/platform_early.h> 55 #endif 56 57 #include "serial_mctrl_gpio.h" 58 #include "sh-sci.h" 59 60 /* Offsets into the sci_port->irqs array */ 61 enum { 62 SCIx_ERI_IRQ, 63 SCIx_RXI_IRQ, 64 SCIx_TXI_IRQ, 65 SCIx_BRI_IRQ, 66 SCIx_DRI_IRQ, 67 SCIx_TEI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71 }; 72 73 #define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79 enum SCI_CLKS { 80 SCI_FCK, /* Functional Clock */ 81 SCI_SCK, /* Optional External Clock */ 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 84 SCI_NUM_CLKS 85 }; 86 87 /* Bit x set means sampling rate x + 1 is supported */ 88 #define SCI_SR(x) BIT((x) - 1) 89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 90 91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 93 SCI_SR(19) | SCI_SR(27) 94 95 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 96 #define max_sr(_port) fls((_port)->sampling_rate_mask) 97 98 /* Iterate over all supported sampling rates, from high to low */ 99 #define for_each_sr(_sr, _port) \ 100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 101 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 102 103 struct plat_sci_reg { 104 u8 offset, size; 105 }; 106 107 struct sci_port_params { 108 const struct plat_sci_reg regs[SCIx_NR_REGS]; 109 unsigned int fifosize; 110 unsigned int overrun_reg; 111 unsigned int overrun_mask; 112 unsigned int sampling_rate_mask; 113 unsigned int error_mask; 114 unsigned int error_clear; 115 }; 116 117 struct sci_port { 118 struct uart_port port; 119 120 /* Platform configuration */ 121 const struct sci_port_params *params; 122 const struct plat_sci_port *cfg; 123 unsigned int sampling_rate_mask; 124 resource_size_t reg_size; 125 struct mctrl_gpios *gpios; 126 127 /* Clocks */ 128 struct clk *clks[SCI_NUM_CLKS]; 129 unsigned long clk_rates[SCI_NUM_CLKS]; 130 131 int irqs[SCIx_NR_IRQS]; 132 char *irqstr[SCIx_NR_IRQS]; 133 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 137 #ifdef CONFIG_SERIAL_SH_SCI_DMA 138 struct dma_chan *chan_tx_saved; 139 struct dma_chan *chan_rx_saved; 140 dma_cookie_t cookie_tx; 141 dma_cookie_t cookie_rx[2]; 142 dma_cookie_t active_rx; 143 dma_addr_t tx_dma_addr; 144 unsigned int tx_dma_len; 145 struct scatterlist sg_rx[2]; 146 void *rx_buf[2]; 147 size_t buf_len_rx; 148 struct work_struct work_tx; 149 struct hrtimer rx_timer; 150 unsigned int rx_timeout; /* microseconds */ 151 #endif 152 unsigned int rx_frame; 153 int rx_trigger; 154 struct timer_list rx_fifo_timer; 155 int rx_fifo_timeout; 156 u16 hscif_tot; 157 158 bool has_rtscts; 159 bool autorts; 160 }; 161 162 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 163 164 static struct sci_port sci_ports[SCI_NPORTS]; 165 static unsigned long sci_ports_in_use; 166 static struct uart_driver sci_uart_driver; 167 168 static inline struct sci_port * 169 to_sci_port(struct uart_port *uart) 170 { 171 return container_of(uart, struct sci_port, port); 172 } 173 174 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 175 /* 176 * Common SCI definitions, dependent on the port's regshift 177 * value. 178 */ 179 [SCIx_SCI_REGTYPE] = { 180 .regs = { 181 [SCSMR] = { 0x00, 8 }, 182 [SCBRR] = { 0x01, 8 }, 183 [SCSCR] = { 0x02, 8 }, 184 [SCxTDR] = { 0x03, 8 }, 185 [SCxSR] = { 0x04, 8 }, 186 [SCxRDR] = { 0x05, 8 }, 187 }, 188 .fifosize = 1, 189 .overrun_reg = SCxSR, 190 .overrun_mask = SCI_ORER, 191 .sampling_rate_mask = SCI_SR(32), 192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 194 }, 195 196 /* 197 * Common definitions for legacy IrDA ports. 198 */ 199 [SCIx_IRDA_REGTYPE] = { 200 .regs = { 201 [SCSMR] = { 0x00, 8 }, 202 [SCBRR] = { 0x02, 8 }, 203 [SCSCR] = { 0x04, 8 }, 204 [SCxTDR] = { 0x06, 8 }, 205 [SCxSR] = { 0x08, 16 }, 206 [SCxRDR] = { 0x0a, 8 }, 207 [SCFCR] = { 0x0c, 8 }, 208 [SCFDR] = { 0x0e, 16 }, 209 }, 210 .fifosize = 1, 211 .overrun_reg = SCxSR, 212 .overrun_mask = SCI_ORER, 213 .sampling_rate_mask = SCI_SR(32), 214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 216 }, 217 218 /* 219 * Common SCIFA definitions. 220 */ 221 [SCIx_SCIFA_REGTYPE] = { 222 .regs = { 223 [SCSMR] = { 0x00, 16 }, 224 [SCBRR] = { 0x04, 8 }, 225 [SCSCR] = { 0x08, 16 }, 226 [SCxTDR] = { 0x20, 8 }, 227 [SCxSR] = { 0x14, 16 }, 228 [SCxRDR] = { 0x24, 8 }, 229 [SCFCR] = { 0x18, 16 }, 230 [SCFDR] = { 0x1c, 16 }, 231 [SCPCR] = { 0x30, 16 }, 232 [SCPDR] = { 0x34, 16 }, 233 }, 234 .fifosize = 64, 235 .overrun_reg = SCxSR, 236 .overrun_mask = SCIFA_ORER, 237 .sampling_rate_mask = SCI_SR_SCIFAB, 238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 240 }, 241 242 /* 243 * Common SCIFB definitions. 244 */ 245 [SCIx_SCIFB_REGTYPE] = { 246 .regs = { 247 [SCSMR] = { 0x00, 16 }, 248 [SCBRR] = { 0x04, 8 }, 249 [SCSCR] = { 0x08, 16 }, 250 [SCxTDR] = { 0x40, 8 }, 251 [SCxSR] = { 0x14, 16 }, 252 [SCxRDR] = { 0x60, 8 }, 253 [SCFCR] = { 0x18, 16 }, 254 [SCTFDR] = { 0x38, 16 }, 255 [SCRFDR] = { 0x3c, 16 }, 256 [SCPCR] = { 0x30, 16 }, 257 [SCPDR] = { 0x34, 16 }, 258 }, 259 .fifosize = 256, 260 .overrun_reg = SCxSR, 261 .overrun_mask = SCIFA_ORER, 262 .sampling_rate_mask = SCI_SR_SCIFAB, 263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 265 }, 266 267 /* 268 * Common SH-2(A) SCIF definitions for ports with FIFO data 269 * count registers. 270 */ 271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 272 .regs = { 273 [SCSMR] = { 0x00, 16 }, 274 [SCBRR] = { 0x04, 8 }, 275 [SCSCR] = { 0x08, 16 }, 276 [SCxTDR] = { 0x0c, 8 }, 277 [SCxSR] = { 0x10, 16 }, 278 [SCxRDR] = { 0x14, 8 }, 279 [SCFCR] = { 0x18, 16 }, 280 [SCFDR] = { 0x1c, 16 }, 281 [SCSPTR] = { 0x20, 16 }, 282 [SCLSR] = { 0x24, 16 }, 283 }, 284 .fifosize = 16, 285 .overrun_reg = SCLSR, 286 .overrun_mask = SCLSR_ORER, 287 .sampling_rate_mask = SCI_SR(32), 288 .error_mask = SCIF_DEFAULT_ERROR_MASK, 289 .error_clear = SCIF_ERROR_CLEAR, 290 }, 291 292 /* 293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 294 * It looks like a normal SCIF with FIFO data, but with a 295 * compressed address space. Also, the break out of interrupts 296 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 297 */ 298 [SCIx_RZ_SCIFA_REGTYPE] = { 299 .regs = { 300 [SCSMR] = { 0x00, 16 }, 301 [SCBRR] = { 0x02, 8 }, 302 [SCSCR] = { 0x04, 16 }, 303 [SCxTDR] = { 0x06, 8 }, 304 [SCxSR] = { 0x08, 16 }, 305 [SCxRDR] = { 0x0A, 8 }, 306 [SCFCR] = { 0x0C, 16 }, 307 [SCFDR] = { 0x0E, 16 }, 308 [SCSPTR] = { 0x10, 16 }, 309 [SCLSR] = { 0x12, 16 }, 310 [SEMR] = { 0x14, 8 }, 311 }, 312 .fifosize = 16, 313 .overrun_reg = SCLSR, 314 .overrun_mask = SCLSR_ORER, 315 .sampling_rate_mask = SCI_SR(32), 316 .error_mask = SCIF_DEFAULT_ERROR_MASK, 317 .error_clear = SCIF_ERROR_CLEAR, 318 }, 319 320 /* 321 * Common SH-3 SCIF definitions. 322 */ 323 [SCIx_SH3_SCIF_REGTYPE] = { 324 .regs = { 325 [SCSMR] = { 0x00, 8 }, 326 [SCBRR] = { 0x02, 8 }, 327 [SCSCR] = { 0x04, 8 }, 328 [SCxTDR] = { 0x06, 8 }, 329 [SCxSR] = { 0x08, 16 }, 330 [SCxRDR] = { 0x0a, 8 }, 331 [SCFCR] = { 0x0c, 8 }, 332 [SCFDR] = { 0x0e, 16 }, 333 }, 334 .fifosize = 16, 335 .overrun_reg = SCLSR, 336 .overrun_mask = SCLSR_ORER, 337 .sampling_rate_mask = SCI_SR(32), 338 .error_mask = SCIF_DEFAULT_ERROR_MASK, 339 .error_clear = SCIF_ERROR_CLEAR, 340 }, 341 342 /* 343 * Common SH-4(A) SCIF(B) definitions. 344 */ 345 [SCIx_SH4_SCIF_REGTYPE] = { 346 .regs = { 347 [SCSMR] = { 0x00, 16 }, 348 [SCBRR] = { 0x04, 8 }, 349 [SCSCR] = { 0x08, 16 }, 350 [SCxTDR] = { 0x0c, 8 }, 351 [SCxSR] = { 0x10, 16 }, 352 [SCxRDR] = { 0x14, 8 }, 353 [SCFCR] = { 0x18, 16 }, 354 [SCFDR] = { 0x1c, 16 }, 355 [SCSPTR] = { 0x20, 16 }, 356 [SCLSR] = { 0x24, 16 }, 357 }, 358 .fifosize = 16, 359 .overrun_reg = SCLSR, 360 .overrun_mask = SCLSR_ORER, 361 .sampling_rate_mask = SCI_SR(32), 362 .error_mask = SCIF_DEFAULT_ERROR_MASK, 363 .error_clear = SCIF_ERROR_CLEAR, 364 }, 365 366 /* 367 * Common SCIF definitions for ports with a Baud Rate Generator for 368 * External Clock (BRG). 369 */ 370 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 371 .regs = { 372 [SCSMR] = { 0x00, 16 }, 373 [SCBRR] = { 0x04, 8 }, 374 [SCSCR] = { 0x08, 16 }, 375 [SCxTDR] = { 0x0c, 8 }, 376 [SCxSR] = { 0x10, 16 }, 377 [SCxRDR] = { 0x14, 8 }, 378 [SCFCR] = { 0x18, 16 }, 379 [SCFDR] = { 0x1c, 16 }, 380 [SCSPTR] = { 0x20, 16 }, 381 [SCLSR] = { 0x24, 16 }, 382 [SCDL] = { 0x30, 16 }, 383 [SCCKS] = { 0x34, 16 }, 384 }, 385 .fifosize = 16, 386 .overrun_reg = SCLSR, 387 .overrun_mask = SCLSR_ORER, 388 .sampling_rate_mask = SCI_SR(32), 389 .error_mask = SCIF_DEFAULT_ERROR_MASK, 390 .error_clear = SCIF_ERROR_CLEAR, 391 }, 392 393 /* 394 * Common HSCIF definitions. 395 */ 396 [SCIx_HSCIF_REGTYPE] = { 397 .regs = { 398 [SCSMR] = { 0x00, 16 }, 399 [SCBRR] = { 0x04, 8 }, 400 [SCSCR] = { 0x08, 16 }, 401 [SCxTDR] = { 0x0c, 8 }, 402 [SCxSR] = { 0x10, 16 }, 403 [SCxRDR] = { 0x14, 8 }, 404 [SCFCR] = { 0x18, 16 }, 405 [SCFDR] = { 0x1c, 16 }, 406 [SCSPTR] = { 0x20, 16 }, 407 [SCLSR] = { 0x24, 16 }, 408 [HSSRR] = { 0x40, 16 }, 409 [SCDL] = { 0x30, 16 }, 410 [SCCKS] = { 0x34, 16 }, 411 [HSRTRGR] = { 0x54, 16 }, 412 [HSTTRGR] = { 0x58, 16 }, 413 }, 414 .fifosize = 128, 415 .overrun_reg = SCLSR, 416 .overrun_mask = SCLSR_ORER, 417 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 418 .error_mask = SCIF_DEFAULT_ERROR_MASK, 419 .error_clear = SCIF_ERROR_CLEAR, 420 }, 421 422 /* 423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 424 * register. 425 */ 426 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 427 .regs = { 428 [SCSMR] = { 0x00, 16 }, 429 [SCBRR] = { 0x04, 8 }, 430 [SCSCR] = { 0x08, 16 }, 431 [SCxTDR] = { 0x0c, 8 }, 432 [SCxSR] = { 0x10, 16 }, 433 [SCxRDR] = { 0x14, 8 }, 434 [SCFCR] = { 0x18, 16 }, 435 [SCFDR] = { 0x1c, 16 }, 436 [SCLSR] = { 0x24, 16 }, 437 }, 438 .fifosize = 16, 439 .overrun_reg = SCLSR, 440 .overrun_mask = SCLSR_ORER, 441 .sampling_rate_mask = SCI_SR(32), 442 .error_mask = SCIF_DEFAULT_ERROR_MASK, 443 .error_clear = SCIF_ERROR_CLEAR, 444 }, 445 446 /* 447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 448 * count registers. 449 */ 450 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 451 .regs = { 452 [SCSMR] = { 0x00, 16 }, 453 [SCBRR] = { 0x04, 8 }, 454 [SCSCR] = { 0x08, 16 }, 455 [SCxTDR] = { 0x0c, 8 }, 456 [SCxSR] = { 0x10, 16 }, 457 [SCxRDR] = { 0x14, 8 }, 458 [SCFCR] = { 0x18, 16 }, 459 [SCFDR] = { 0x1c, 16 }, 460 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 461 [SCRFDR] = { 0x20, 16 }, 462 [SCSPTR] = { 0x24, 16 }, 463 [SCLSR] = { 0x28, 16 }, 464 }, 465 .fifosize = 16, 466 .overrun_reg = SCLSR, 467 .overrun_mask = SCLSR_ORER, 468 .sampling_rate_mask = SCI_SR(32), 469 .error_mask = SCIF_DEFAULT_ERROR_MASK, 470 .error_clear = SCIF_ERROR_CLEAR, 471 }, 472 473 /* 474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 475 * registers. 476 */ 477 [SCIx_SH7705_SCIF_REGTYPE] = { 478 .regs = { 479 [SCSMR] = { 0x00, 16 }, 480 [SCBRR] = { 0x04, 8 }, 481 [SCSCR] = { 0x08, 16 }, 482 [SCxTDR] = { 0x20, 8 }, 483 [SCxSR] = { 0x14, 16 }, 484 [SCxRDR] = { 0x24, 8 }, 485 [SCFCR] = { 0x18, 16 }, 486 [SCFDR] = { 0x1c, 16 }, 487 }, 488 .fifosize = 64, 489 .overrun_reg = SCxSR, 490 .overrun_mask = SCIFA_ORER, 491 .sampling_rate_mask = SCI_SR(16), 492 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 493 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 494 }, 495 }; 496 497 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 498 499 /* 500 * The "offset" here is rather misleading, in that it refers to an enum 501 * value relative to the port mapping rather than the fixed offset 502 * itself, which needs to be manually retrieved from the platform's 503 * register map for the given port. 504 */ 505 static unsigned int sci_serial_in(struct uart_port *p, int offset) 506 { 507 const struct plat_sci_reg *reg = sci_getreg(p, offset); 508 509 if (reg->size == 8) 510 return ioread8(p->membase + (reg->offset << p->regshift)); 511 else if (reg->size == 16) 512 return ioread16(p->membase + (reg->offset << p->regshift)); 513 else 514 WARN(1, "Invalid register access\n"); 515 516 return 0; 517 } 518 519 static void sci_serial_out(struct uart_port *p, int offset, int value) 520 { 521 const struct plat_sci_reg *reg = sci_getreg(p, offset); 522 523 if (reg->size == 8) 524 iowrite8(value, p->membase + (reg->offset << p->regshift)); 525 else if (reg->size == 16) 526 iowrite16(value, p->membase + (reg->offset << p->regshift)); 527 else 528 WARN(1, "Invalid register access\n"); 529 } 530 531 static void sci_port_enable(struct sci_port *sci_port) 532 { 533 unsigned int i; 534 535 if (!sci_port->port.dev) 536 return; 537 538 pm_runtime_get_sync(sci_port->port.dev); 539 540 for (i = 0; i < SCI_NUM_CLKS; i++) { 541 clk_prepare_enable(sci_port->clks[i]); 542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 543 } 544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 545 } 546 547 static void sci_port_disable(struct sci_port *sci_port) 548 { 549 unsigned int i; 550 551 if (!sci_port->port.dev) 552 return; 553 554 for (i = SCI_NUM_CLKS; i-- > 0; ) 555 clk_disable_unprepare(sci_port->clks[i]); 556 557 pm_runtime_put_sync(sci_port->port.dev); 558 } 559 560 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 561 { 562 /* 563 * Not all ports (such as SCIFA) will support REIE. Rather than 564 * special-casing the port type, we check the port initialization 565 * IRQ enable mask to see whether the IRQ is desired at all. If 566 * it's unset, it's logically inferred that there's no point in 567 * testing for it. 568 */ 569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 570 } 571 572 static void sci_start_tx(struct uart_port *port) 573 { 574 struct sci_port *s = to_sci_port(port); 575 unsigned short ctrl; 576 577 #ifdef CONFIG_SERIAL_SH_SCI_DMA 578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 579 u16 new, scr = serial_port_in(port, SCSCR); 580 if (s->chan_tx) 581 new = scr | SCSCR_TDRQE; 582 else 583 new = scr & ~SCSCR_TDRQE; 584 if (new != scr) 585 serial_port_out(port, SCSCR, new); 586 } 587 588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 589 dma_submit_error(s->cookie_tx)) { 590 s->cookie_tx = 0; 591 schedule_work(&s->work_tx); 592 } 593 #endif 594 595 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 596 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 597 ctrl = serial_port_in(port, SCSCR); 598 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 599 } 600 } 601 602 static void sci_stop_tx(struct uart_port *port) 603 { 604 unsigned short ctrl; 605 606 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 607 ctrl = serial_port_in(port, SCSCR); 608 609 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 610 ctrl &= ~SCSCR_TDRQE; 611 612 ctrl &= ~SCSCR_TIE; 613 614 serial_port_out(port, SCSCR, ctrl); 615 616 #ifdef CONFIG_SERIAL_SH_SCI_DMA 617 if (to_sci_port(port)->chan_tx && 618 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 619 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 620 to_sci_port(port)->cookie_tx = -EINVAL; 621 } 622 #endif 623 } 624 625 static void sci_start_rx(struct uart_port *port) 626 { 627 unsigned short ctrl; 628 629 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 630 631 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 632 ctrl &= ~SCSCR_RDRQE; 633 634 serial_port_out(port, SCSCR, ctrl); 635 } 636 637 static void sci_stop_rx(struct uart_port *port) 638 { 639 unsigned short ctrl; 640 641 ctrl = serial_port_in(port, SCSCR); 642 643 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 644 ctrl &= ~SCSCR_RDRQE; 645 646 ctrl &= ~port_rx_irq_mask(port); 647 648 serial_port_out(port, SCSCR, ctrl); 649 } 650 651 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 652 { 653 if (port->type == PORT_SCI) { 654 /* Just store the mask */ 655 serial_port_out(port, SCxSR, mask); 656 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 657 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 658 /* Only clear the status bits we want to clear */ 659 serial_port_out(port, SCxSR, 660 serial_port_in(port, SCxSR) & mask); 661 } else { 662 /* Store the mask, clear parity/framing errors */ 663 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 664 } 665 } 666 667 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 668 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 669 670 #ifdef CONFIG_CONSOLE_POLL 671 static int sci_poll_get_char(struct uart_port *port) 672 { 673 unsigned short status; 674 int c; 675 676 do { 677 status = serial_port_in(port, SCxSR); 678 if (status & SCxSR_ERRORS(port)) { 679 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 680 continue; 681 } 682 break; 683 } while (1); 684 685 if (!(status & SCxSR_RDxF(port))) 686 return NO_POLL_CHAR; 687 688 c = serial_port_in(port, SCxRDR); 689 690 /* Dummy read */ 691 serial_port_in(port, SCxSR); 692 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 693 694 return c; 695 } 696 #endif 697 698 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 699 { 700 unsigned short status; 701 702 do { 703 status = serial_port_in(port, SCxSR); 704 } while (!(status & SCxSR_TDxE(port))); 705 706 serial_port_out(port, SCxTDR, c); 707 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 708 } 709 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 710 CONFIG_SERIAL_SH_SCI_EARLYCON */ 711 712 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 713 { 714 struct sci_port *s = to_sci_port(port); 715 716 /* 717 * Use port-specific handler if provided. 718 */ 719 if (s->cfg->ops && s->cfg->ops->init_pins) { 720 s->cfg->ops->init_pins(port, cflag); 721 return; 722 } 723 724 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 725 u16 data = serial_port_in(port, SCPDR); 726 u16 ctrl = serial_port_in(port, SCPCR); 727 728 /* Enable RXD and TXD pin functions */ 729 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 730 if (to_sci_port(port)->has_rtscts) { 731 /* RTS# is output, active low, unless autorts */ 732 if (!(port->mctrl & TIOCM_RTS)) { 733 ctrl |= SCPCR_RTSC; 734 data |= SCPDR_RTSD; 735 } else if (!s->autorts) { 736 ctrl |= SCPCR_RTSC; 737 data &= ~SCPDR_RTSD; 738 } else { 739 /* Enable RTS# pin function */ 740 ctrl &= ~SCPCR_RTSC; 741 } 742 /* Enable CTS# pin function */ 743 ctrl &= ~SCPCR_CTSC; 744 } 745 serial_port_out(port, SCPDR, data); 746 serial_port_out(port, SCPCR, ctrl); 747 } else if (sci_getreg(port, SCSPTR)->size) { 748 u16 status = serial_port_in(port, SCSPTR); 749 750 /* RTS# is always output; and active low, unless autorts */ 751 status |= SCSPTR_RTSIO; 752 if (!(port->mctrl & TIOCM_RTS)) 753 status |= SCSPTR_RTSDT; 754 else if (!s->autorts) 755 status &= ~SCSPTR_RTSDT; 756 /* CTS# and SCK are inputs */ 757 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 758 serial_port_out(port, SCSPTR, status); 759 } 760 } 761 762 static int sci_txfill(struct uart_port *port) 763 { 764 struct sci_port *s = to_sci_port(port); 765 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 766 const struct plat_sci_reg *reg; 767 768 reg = sci_getreg(port, SCTFDR); 769 if (reg->size) 770 return serial_port_in(port, SCTFDR) & fifo_mask; 771 772 reg = sci_getreg(port, SCFDR); 773 if (reg->size) 774 return serial_port_in(port, SCFDR) >> 8; 775 776 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 777 } 778 779 static int sci_txroom(struct uart_port *port) 780 { 781 return port->fifosize - sci_txfill(port); 782 } 783 784 static int sci_rxfill(struct uart_port *port) 785 { 786 struct sci_port *s = to_sci_port(port); 787 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 788 const struct plat_sci_reg *reg; 789 790 reg = sci_getreg(port, SCRFDR); 791 if (reg->size) 792 return serial_port_in(port, SCRFDR) & fifo_mask; 793 794 reg = sci_getreg(port, SCFDR); 795 if (reg->size) 796 return serial_port_in(port, SCFDR) & fifo_mask; 797 798 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 799 } 800 801 /* ********************************************************************** * 802 * the interrupt related routines * 803 * ********************************************************************** */ 804 805 static void sci_transmit_chars(struct uart_port *port) 806 { 807 struct circ_buf *xmit = &port->state->xmit; 808 unsigned int stopped = uart_tx_stopped(port); 809 unsigned short status; 810 unsigned short ctrl; 811 int count; 812 813 status = serial_port_in(port, SCxSR); 814 if (!(status & SCxSR_TDxE(port))) { 815 ctrl = serial_port_in(port, SCSCR); 816 if (uart_circ_empty(xmit)) 817 ctrl &= ~SCSCR_TIE; 818 else 819 ctrl |= SCSCR_TIE; 820 serial_port_out(port, SCSCR, ctrl); 821 return; 822 } 823 824 count = sci_txroom(port); 825 826 do { 827 unsigned char c; 828 829 if (port->x_char) { 830 c = port->x_char; 831 port->x_char = 0; 832 } else if (!uart_circ_empty(xmit) && !stopped) { 833 c = xmit->buf[xmit->tail]; 834 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 835 } else { 836 break; 837 } 838 839 serial_port_out(port, SCxTDR, c); 840 841 port->icount.tx++; 842 } while (--count > 0); 843 844 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 845 846 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 847 uart_write_wakeup(port); 848 if (uart_circ_empty(xmit)) 849 sci_stop_tx(port); 850 851 } 852 853 static void sci_receive_chars(struct uart_port *port) 854 { 855 struct tty_port *tport = &port->state->port; 856 int i, count, copied = 0; 857 unsigned short status; 858 unsigned char flag; 859 860 status = serial_port_in(port, SCxSR); 861 if (!(status & SCxSR_RDxF(port))) 862 return; 863 864 while (1) { 865 /* Don't copy more bytes than there is room for in the buffer */ 866 count = tty_buffer_request_room(tport, sci_rxfill(port)); 867 868 /* If for any reason we can't copy more data, we're done! */ 869 if (count == 0) 870 break; 871 872 if (port->type == PORT_SCI) { 873 char c = serial_port_in(port, SCxRDR); 874 if (uart_handle_sysrq_char(port, c)) 875 count = 0; 876 else 877 tty_insert_flip_char(tport, c, TTY_NORMAL); 878 } else { 879 for (i = 0; i < count; i++) { 880 char c; 881 882 if (port->type == PORT_SCIF || 883 port->type == PORT_HSCIF) { 884 status = serial_port_in(port, SCxSR); 885 c = serial_port_in(port, SCxRDR); 886 } else { 887 c = serial_port_in(port, SCxRDR); 888 status = serial_port_in(port, SCxSR); 889 } 890 if (uart_handle_sysrq_char(port, c)) { 891 count--; i--; 892 continue; 893 } 894 895 /* Store data and status */ 896 if (status & SCxSR_FER(port)) { 897 flag = TTY_FRAME; 898 port->icount.frame++; 899 } else if (status & SCxSR_PER(port)) { 900 flag = TTY_PARITY; 901 port->icount.parity++; 902 } else 903 flag = TTY_NORMAL; 904 905 tty_insert_flip_char(tport, c, flag); 906 } 907 } 908 909 serial_port_in(port, SCxSR); /* dummy read */ 910 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 911 912 copied += count; 913 port->icount.rx += count; 914 } 915 916 if (copied) { 917 /* Tell the rest of the system the news. New characters! */ 918 tty_flip_buffer_push(tport); 919 } else { 920 /* TTY buffers full; read from RX reg to prevent lockup */ 921 serial_port_in(port, SCxRDR); 922 serial_port_in(port, SCxSR); /* dummy read */ 923 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 924 } 925 } 926 927 static int sci_handle_errors(struct uart_port *port) 928 { 929 int copied = 0; 930 unsigned short status = serial_port_in(port, SCxSR); 931 struct tty_port *tport = &port->state->port; 932 struct sci_port *s = to_sci_port(port); 933 934 /* Handle overruns */ 935 if (status & s->params->overrun_mask) { 936 port->icount.overrun++; 937 938 /* overrun error */ 939 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 940 copied++; 941 } 942 943 if (status & SCxSR_FER(port)) { 944 /* frame error */ 945 port->icount.frame++; 946 947 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 948 copied++; 949 } 950 951 if (status & SCxSR_PER(port)) { 952 /* parity error */ 953 port->icount.parity++; 954 955 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 956 copied++; 957 } 958 959 if (copied) 960 tty_flip_buffer_push(tport); 961 962 return copied; 963 } 964 965 static int sci_handle_fifo_overrun(struct uart_port *port) 966 { 967 struct tty_port *tport = &port->state->port; 968 struct sci_port *s = to_sci_port(port); 969 const struct plat_sci_reg *reg; 970 int copied = 0; 971 u16 status; 972 973 reg = sci_getreg(port, s->params->overrun_reg); 974 if (!reg->size) 975 return 0; 976 977 status = serial_port_in(port, s->params->overrun_reg); 978 if (status & s->params->overrun_mask) { 979 status &= ~s->params->overrun_mask; 980 serial_port_out(port, s->params->overrun_reg, status); 981 982 port->icount.overrun++; 983 984 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 985 tty_flip_buffer_push(tport); 986 copied++; 987 } 988 989 return copied; 990 } 991 992 static int sci_handle_breaks(struct uart_port *port) 993 { 994 int copied = 0; 995 unsigned short status = serial_port_in(port, SCxSR); 996 struct tty_port *tport = &port->state->port; 997 998 if (uart_handle_break(port)) 999 return 0; 1000 1001 if (status & SCxSR_BRK(port)) { 1002 port->icount.brk++; 1003 1004 /* Notify of BREAK */ 1005 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1006 copied++; 1007 } 1008 1009 if (copied) 1010 tty_flip_buffer_push(tport); 1011 1012 copied += sci_handle_fifo_overrun(port); 1013 1014 return copied; 1015 } 1016 1017 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1018 { 1019 unsigned int bits; 1020 1021 if (rx_trig >= port->fifosize) 1022 rx_trig = port->fifosize - 1; 1023 if (rx_trig < 1) 1024 rx_trig = 1; 1025 1026 /* HSCIF can be set to an arbitrary level. */ 1027 if (sci_getreg(port, HSRTRGR)->size) { 1028 serial_port_out(port, HSRTRGR, rx_trig); 1029 return rx_trig; 1030 } 1031 1032 switch (port->type) { 1033 case PORT_SCIF: 1034 if (rx_trig < 4) { 1035 bits = 0; 1036 rx_trig = 1; 1037 } else if (rx_trig < 8) { 1038 bits = SCFCR_RTRG0; 1039 rx_trig = 4; 1040 } else if (rx_trig < 14) { 1041 bits = SCFCR_RTRG1; 1042 rx_trig = 8; 1043 } else { 1044 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1045 rx_trig = 14; 1046 } 1047 break; 1048 case PORT_SCIFA: 1049 case PORT_SCIFB: 1050 if (rx_trig < 16) { 1051 bits = 0; 1052 rx_trig = 1; 1053 } else if (rx_trig < 32) { 1054 bits = SCFCR_RTRG0; 1055 rx_trig = 16; 1056 } else if (rx_trig < 48) { 1057 bits = SCFCR_RTRG1; 1058 rx_trig = 32; 1059 } else { 1060 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1061 rx_trig = 48; 1062 } 1063 break; 1064 default: 1065 WARN(1, "unknown FIFO configuration"); 1066 return 1; 1067 } 1068 1069 serial_port_out(port, SCFCR, 1070 (serial_port_in(port, SCFCR) & 1071 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1072 1073 return rx_trig; 1074 } 1075 1076 static int scif_rtrg_enabled(struct uart_port *port) 1077 { 1078 if (sci_getreg(port, HSRTRGR)->size) 1079 return serial_port_in(port, HSRTRGR) != 0; 1080 else 1081 return (serial_port_in(port, SCFCR) & 1082 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1083 } 1084 1085 static void rx_fifo_timer_fn(struct timer_list *t) 1086 { 1087 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1088 struct uart_port *port = &s->port; 1089 1090 dev_dbg(port->dev, "Rx timed out\n"); 1091 scif_set_rtrg(port, 1); 1092 } 1093 1094 static ssize_t rx_fifo_trigger_show(struct device *dev, 1095 struct device_attribute *attr, char *buf) 1096 { 1097 struct uart_port *port = dev_get_drvdata(dev); 1098 struct sci_port *sci = to_sci_port(port); 1099 1100 return sprintf(buf, "%d\n", sci->rx_trigger); 1101 } 1102 1103 static ssize_t rx_fifo_trigger_store(struct device *dev, 1104 struct device_attribute *attr, 1105 const char *buf, size_t count) 1106 { 1107 struct uart_port *port = dev_get_drvdata(dev); 1108 struct sci_port *sci = to_sci_port(port); 1109 int ret; 1110 long r; 1111 1112 ret = kstrtol(buf, 0, &r); 1113 if (ret) 1114 return ret; 1115 1116 sci->rx_trigger = scif_set_rtrg(port, r); 1117 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1118 scif_set_rtrg(port, 1); 1119 1120 return count; 1121 } 1122 1123 static DEVICE_ATTR_RW(rx_fifo_trigger); 1124 1125 static ssize_t rx_fifo_timeout_show(struct device *dev, 1126 struct device_attribute *attr, 1127 char *buf) 1128 { 1129 struct uart_port *port = dev_get_drvdata(dev); 1130 struct sci_port *sci = to_sci_port(port); 1131 int v; 1132 1133 if (port->type == PORT_HSCIF) 1134 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1135 else 1136 v = sci->rx_fifo_timeout; 1137 1138 return sprintf(buf, "%d\n", v); 1139 } 1140 1141 static ssize_t rx_fifo_timeout_store(struct device *dev, 1142 struct device_attribute *attr, 1143 const char *buf, 1144 size_t count) 1145 { 1146 struct uart_port *port = dev_get_drvdata(dev); 1147 struct sci_port *sci = to_sci_port(port); 1148 int ret; 1149 long r; 1150 1151 ret = kstrtol(buf, 0, &r); 1152 if (ret) 1153 return ret; 1154 1155 if (port->type == PORT_HSCIF) { 1156 if (r < 0 || r > 3) 1157 return -EINVAL; 1158 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1159 } else { 1160 sci->rx_fifo_timeout = r; 1161 scif_set_rtrg(port, 1); 1162 if (r > 0) 1163 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1164 } 1165 1166 return count; 1167 } 1168 1169 static DEVICE_ATTR_RW(rx_fifo_timeout); 1170 1171 1172 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1173 static void sci_dma_tx_complete(void *arg) 1174 { 1175 struct sci_port *s = arg; 1176 struct uart_port *port = &s->port; 1177 struct circ_buf *xmit = &port->state->xmit; 1178 unsigned long flags; 1179 1180 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1181 1182 spin_lock_irqsave(&port->lock, flags); 1183 1184 xmit->tail += s->tx_dma_len; 1185 xmit->tail &= UART_XMIT_SIZE - 1; 1186 1187 port->icount.tx += s->tx_dma_len; 1188 1189 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1190 uart_write_wakeup(port); 1191 1192 if (!uart_circ_empty(xmit)) { 1193 s->cookie_tx = 0; 1194 schedule_work(&s->work_tx); 1195 } else { 1196 s->cookie_tx = -EINVAL; 1197 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1198 u16 ctrl = serial_port_in(port, SCSCR); 1199 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1200 } 1201 } 1202 1203 spin_unlock_irqrestore(&port->lock, flags); 1204 } 1205 1206 /* Locking: called with port lock held */ 1207 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1208 { 1209 struct uart_port *port = &s->port; 1210 struct tty_port *tport = &port->state->port; 1211 int copied; 1212 1213 copied = tty_insert_flip_string(tport, buf, count); 1214 if (copied < count) 1215 port->icount.buf_overrun++; 1216 1217 port->icount.rx += copied; 1218 1219 return copied; 1220 } 1221 1222 static int sci_dma_rx_find_active(struct sci_port *s) 1223 { 1224 unsigned int i; 1225 1226 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1227 if (s->active_rx == s->cookie_rx[i]) 1228 return i; 1229 1230 return -1; 1231 } 1232 1233 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1234 { 1235 unsigned int i; 1236 1237 s->chan_rx = NULL; 1238 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1239 s->cookie_rx[i] = -EINVAL; 1240 s->active_rx = 0; 1241 } 1242 1243 static void sci_dma_rx_release(struct sci_port *s) 1244 { 1245 struct dma_chan *chan = s->chan_rx_saved; 1246 1247 s->chan_rx_saved = NULL; 1248 sci_dma_rx_chan_invalidate(s); 1249 dmaengine_terminate_sync(chan); 1250 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1251 sg_dma_address(&s->sg_rx[0])); 1252 dma_release_channel(chan); 1253 } 1254 1255 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1256 { 1257 long sec = usec / 1000000; 1258 long nsec = (usec % 1000000) * 1000; 1259 ktime_t t = ktime_set(sec, nsec); 1260 1261 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1262 } 1263 1264 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1265 { 1266 struct uart_port *port = &s->port; 1267 u16 scr; 1268 1269 /* Direct new serial port interrupts back to CPU */ 1270 scr = serial_port_in(port, SCSCR); 1271 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1272 scr &= ~SCSCR_RDRQE; 1273 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1274 } 1275 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1276 } 1277 1278 static void sci_dma_rx_complete(void *arg) 1279 { 1280 struct sci_port *s = arg; 1281 struct dma_chan *chan = s->chan_rx; 1282 struct uart_port *port = &s->port; 1283 struct dma_async_tx_descriptor *desc; 1284 unsigned long flags; 1285 int active, count = 0; 1286 1287 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1288 s->active_rx); 1289 1290 spin_lock_irqsave(&port->lock, flags); 1291 1292 active = sci_dma_rx_find_active(s); 1293 if (active >= 0) 1294 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1295 1296 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1297 1298 if (count) 1299 tty_flip_buffer_push(&port->state->port); 1300 1301 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1302 DMA_DEV_TO_MEM, 1303 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1304 if (!desc) 1305 goto fail; 1306 1307 desc->callback = sci_dma_rx_complete; 1308 desc->callback_param = s; 1309 s->cookie_rx[active] = dmaengine_submit(desc); 1310 if (dma_submit_error(s->cookie_rx[active])) 1311 goto fail; 1312 1313 s->active_rx = s->cookie_rx[!active]; 1314 1315 dma_async_issue_pending(chan); 1316 1317 spin_unlock_irqrestore(&port->lock, flags); 1318 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1319 __func__, s->cookie_rx[active], active, s->active_rx); 1320 return; 1321 1322 fail: 1323 spin_unlock_irqrestore(&port->lock, flags); 1324 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1325 /* Switch to PIO */ 1326 spin_lock_irqsave(&port->lock, flags); 1327 dmaengine_terminate_async(chan); 1328 sci_dma_rx_chan_invalidate(s); 1329 sci_dma_rx_reenable_irq(s); 1330 spin_unlock_irqrestore(&port->lock, flags); 1331 } 1332 1333 static void sci_dma_tx_release(struct sci_port *s) 1334 { 1335 struct dma_chan *chan = s->chan_tx_saved; 1336 1337 cancel_work_sync(&s->work_tx); 1338 s->chan_tx_saved = s->chan_tx = NULL; 1339 s->cookie_tx = -EINVAL; 1340 dmaengine_terminate_sync(chan); 1341 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1342 DMA_TO_DEVICE); 1343 dma_release_channel(chan); 1344 } 1345 1346 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1347 { 1348 struct dma_chan *chan = s->chan_rx; 1349 struct uart_port *port = &s->port; 1350 unsigned long flags; 1351 int i; 1352 1353 for (i = 0; i < 2; i++) { 1354 struct scatterlist *sg = &s->sg_rx[i]; 1355 struct dma_async_tx_descriptor *desc; 1356 1357 desc = dmaengine_prep_slave_sg(chan, 1358 sg, 1, DMA_DEV_TO_MEM, 1359 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1360 if (!desc) 1361 goto fail; 1362 1363 desc->callback = sci_dma_rx_complete; 1364 desc->callback_param = s; 1365 s->cookie_rx[i] = dmaengine_submit(desc); 1366 if (dma_submit_error(s->cookie_rx[i])) 1367 goto fail; 1368 1369 } 1370 1371 s->active_rx = s->cookie_rx[0]; 1372 1373 dma_async_issue_pending(chan); 1374 return 0; 1375 1376 fail: 1377 /* Switch to PIO */ 1378 if (!port_lock_held) 1379 spin_lock_irqsave(&port->lock, flags); 1380 if (i) 1381 dmaengine_terminate_async(chan); 1382 sci_dma_rx_chan_invalidate(s); 1383 sci_start_rx(port); 1384 if (!port_lock_held) 1385 spin_unlock_irqrestore(&port->lock, flags); 1386 return -EAGAIN; 1387 } 1388 1389 static void sci_dma_tx_work_fn(struct work_struct *work) 1390 { 1391 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1392 struct dma_async_tx_descriptor *desc; 1393 struct dma_chan *chan = s->chan_tx; 1394 struct uart_port *port = &s->port; 1395 struct circ_buf *xmit = &port->state->xmit; 1396 unsigned long flags; 1397 dma_addr_t buf; 1398 int head, tail; 1399 1400 /* 1401 * DMA is idle now. 1402 * Port xmit buffer is already mapped, and it is one page... Just adjust 1403 * offsets and lengths. Since it is a circular buffer, we have to 1404 * transmit till the end, and then the rest. Take the port lock to get a 1405 * consistent xmit buffer state. 1406 */ 1407 spin_lock_irq(&port->lock); 1408 head = xmit->head; 1409 tail = xmit->tail; 1410 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1)); 1411 s->tx_dma_len = min_t(unsigned int, 1412 CIRC_CNT(head, tail, UART_XMIT_SIZE), 1413 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE)); 1414 if (!s->tx_dma_len) { 1415 /* Transmit buffer has been flushed */ 1416 spin_unlock_irq(&port->lock); 1417 return; 1418 } 1419 1420 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1421 DMA_MEM_TO_DEV, 1422 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1423 if (!desc) { 1424 spin_unlock_irq(&port->lock); 1425 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1426 goto switch_to_pio; 1427 } 1428 1429 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1430 DMA_TO_DEVICE); 1431 1432 desc->callback = sci_dma_tx_complete; 1433 desc->callback_param = s; 1434 s->cookie_tx = dmaengine_submit(desc); 1435 if (dma_submit_error(s->cookie_tx)) { 1436 spin_unlock_irq(&port->lock); 1437 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1438 goto switch_to_pio; 1439 } 1440 1441 spin_unlock_irq(&port->lock); 1442 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1443 __func__, xmit->buf, tail, head, s->cookie_tx); 1444 1445 dma_async_issue_pending(chan); 1446 return; 1447 1448 switch_to_pio: 1449 spin_lock_irqsave(&port->lock, flags); 1450 s->chan_tx = NULL; 1451 sci_start_tx(port); 1452 spin_unlock_irqrestore(&port->lock, flags); 1453 return; 1454 } 1455 1456 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1457 { 1458 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1459 struct dma_chan *chan = s->chan_rx; 1460 struct uart_port *port = &s->port; 1461 struct dma_tx_state state; 1462 enum dma_status status; 1463 unsigned long flags; 1464 unsigned int read; 1465 int active, count; 1466 1467 dev_dbg(port->dev, "DMA Rx timed out\n"); 1468 1469 spin_lock_irqsave(&port->lock, flags); 1470 1471 active = sci_dma_rx_find_active(s); 1472 if (active < 0) { 1473 spin_unlock_irqrestore(&port->lock, flags); 1474 return HRTIMER_NORESTART; 1475 } 1476 1477 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1478 if (status == DMA_COMPLETE) { 1479 spin_unlock_irqrestore(&port->lock, flags); 1480 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1481 s->active_rx, active); 1482 1483 /* Let packet complete handler take care of the packet */ 1484 return HRTIMER_NORESTART; 1485 } 1486 1487 dmaengine_pause(chan); 1488 1489 /* 1490 * sometimes DMA transfer doesn't stop even if it is stopped and 1491 * data keeps on coming until transaction is complete so check 1492 * for DMA_COMPLETE again 1493 * Let packet complete handler take care of the packet 1494 */ 1495 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1496 if (status == DMA_COMPLETE) { 1497 spin_unlock_irqrestore(&port->lock, flags); 1498 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1499 return HRTIMER_NORESTART; 1500 } 1501 1502 /* Handle incomplete DMA receive */ 1503 dmaengine_terminate_async(s->chan_rx); 1504 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1505 1506 if (read) { 1507 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1508 if (count) 1509 tty_flip_buffer_push(&port->state->port); 1510 } 1511 1512 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1513 sci_dma_rx_submit(s, true); 1514 1515 sci_dma_rx_reenable_irq(s); 1516 1517 spin_unlock_irqrestore(&port->lock, flags); 1518 1519 return HRTIMER_NORESTART; 1520 } 1521 1522 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1523 enum dma_transfer_direction dir) 1524 { 1525 struct dma_chan *chan; 1526 struct dma_slave_config cfg; 1527 int ret; 1528 1529 chan = dma_request_slave_channel(port->dev, 1530 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1531 if (!chan) { 1532 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1533 return NULL; 1534 } 1535 1536 memset(&cfg, 0, sizeof(cfg)); 1537 cfg.direction = dir; 1538 if (dir == DMA_MEM_TO_DEV) { 1539 cfg.dst_addr = port->mapbase + 1540 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1541 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1542 } else { 1543 cfg.src_addr = port->mapbase + 1544 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1545 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1546 } 1547 1548 ret = dmaengine_slave_config(chan, &cfg); 1549 if (ret) { 1550 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1551 dma_release_channel(chan); 1552 return NULL; 1553 } 1554 1555 return chan; 1556 } 1557 1558 static void sci_request_dma(struct uart_port *port) 1559 { 1560 struct sci_port *s = to_sci_port(port); 1561 struct dma_chan *chan; 1562 1563 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1564 1565 /* 1566 * DMA on console may interfere with Kernel log messages which use 1567 * plain putchar(). So, simply don't use it with a console. 1568 */ 1569 if (uart_console(port)) 1570 return; 1571 1572 if (!port->dev->of_node) 1573 return; 1574 1575 s->cookie_tx = -EINVAL; 1576 1577 /* 1578 * Don't request a dma channel if no channel was specified 1579 * in the device tree. 1580 */ 1581 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1582 return; 1583 1584 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1585 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1586 if (chan) { 1587 /* UART circular tx buffer is an aligned page. */ 1588 s->tx_dma_addr = dma_map_single(chan->device->dev, 1589 port->state->xmit.buf, 1590 UART_XMIT_SIZE, 1591 DMA_TO_DEVICE); 1592 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1593 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1594 dma_release_channel(chan); 1595 } else { 1596 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1597 __func__, UART_XMIT_SIZE, 1598 port->state->xmit.buf, &s->tx_dma_addr); 1599 1600 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1601 s->chan_tx_saved = s->chan_tx = chan; 1602 } 1603 } 1604 1605 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1606 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1607 if (chan) { 1608 unsigned int i; 1609 dma_addr_t dma; 1610 void *buf; 1611 1612 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1613 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1614 &dma, GFP_KERNEL); 1615 if (!buf) { 1616 dev_warn(port->dev, 1617 "Failed to allocate Rx dma buffer, using PIO\n"); 1618 dma_release_channel(chan); 1619 return; 1620 } 1621 1622 for (i = 0; i < 2; i++) { 1623 struct scatterlist *sg = &s->sg_rx[i]; 1624 1625 sg_init_table(sg, 1); 1626 s->rx_buf[i] = buf; 1627 sg_dma_address(sg) = dma; 1628 sg_dma_len(sg) = s->buf_len_rx; 1629 1630 buf += s->buf_len_rx; 1631 dma += s->buf_len_rx; 1632 } 1633 1634 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1635 s->rx_timer.function = sci_dma_rx_timer_fn; 1636 1637 s->chan_rx_saved = s->chan_rx = chan; 1638 1639 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1640 sci_dma_rx_submit(s, false); 1641 } 1642 } 1643 1644 static void sci_free_dma(struct uart_port *port) 1645 { 1646 struct sci_port *s = to_sci_port(port); 1647 1648 if (s->chan_tx_saved) 1649 sci_dma_tx_release(s); 1650 if (s->chan_rx_saved) 1651 sci_dma_rx_release(s); 1652 } 1653 1654 static void sci_flush_buffer(struct uart_port *port) 1655 { 1656 struct sci_port *s = to_sci_port(port); 1657 1658 /* 1659 * In uart_flush_buffer(), the xmit circular buffer has just been 1660 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1661 * pending transfers 1662 */ 1663 s->tx_dma_len = 0; 1664 if (s->chan_tx) { 1665 dmaengine_terminate_async(s->chan_tx); 1666 s->cookie_tx = -EINVAL; 1667 } 1668 } 1669 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1670 static inline void sci_request_dma(struct uart_port *port) 1671 { 1672 } 1673 1674 static inline void sci_free_dma(struct uart_port *port) 1675 { 1676 } 1677 1678 #define sci_flush_buffer NULL 1679 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1680 1681 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1682 { 1683 struct uart_port *port = ptr; 1684 struct sci_port *s = to_sci_port(port); 1685 1686 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1687 if (s->chan_rx) { 1688 u16 scr = serial_port_in(port, SCSCR); 1689 u16 ssr = serial_port_in(port, SCxSR); 1690 1691 /* Disable future Rx interrupts */ 1692 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1693 disable_irq_nosync(irq); 1694 scr |= SCSCR_RDRQE; 1695 } else { 1696 if (sci_dma_rx_submit(s, false) < 0) 1697 goto handle_pio; 1698 1699 scr &= ~SCSCR_RIE; 1700 } 1701 serial_port_out(port, SCSCR, scr); 1702 /* Clear current interrupt */ 1703 serial_port_out(port, SCxSR, 1704 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1705 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1706 jiffies, s->rx_timeout); 1707 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1708 1709 return IRQ_HANDLED; 1710 } 1711 1712 handle_pio: 1713 #endif 1714 1715 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1716 if (!scif_rtrg_enabled(port)) 1717 scif_set_rtrg(port, s->rx_trigger); 1718 1719 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1720 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1721 } 1722 1723 /* I think sci_receive_chars has to be called irrespective 1724 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1725 * to be disabled? 1726 */ 1727 sci_receive_chars(port); 1728 1729 return IRQ_HANDLED; 1730 } 1731 1732 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1733 { 1734 struct uart_port *port = ptr; 1735 unsigned long flags; 1736 1737 spin_lock_irqsave(&port->lock, flags); 1738 sci_transmit_chars(port); 1739 spin_unlock_irqrestore(&port->lock, flags); 1740 1741 return IRQ_HANDLED; 1742 } 1743 1744 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1745 { 1746 struct uart_port *port = ptr; 1747 1748 /* Handle BREAKs */ 1749 sci_handle_breaks(port); 1750 1751 /* drop invalid character received before break was detected */ 1752 serial_port_in(port, SCxRDR); 1753 1754 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1755 1756 return IRQ_HANDLED; 1757 } 1758 1759 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1760 { 1761 struct uart_port *port = ptr; 1762 struct sci_port *s = to_sci_port(port); 1763 1764 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1765 /* Break and Error interrupts are muxed */ 1766 unsigned short ssr_status = serial_port_in(port, SCxSR); 1767 1768 /* Break Interrupt */ 1769 if (ssr_status & SCxSR_BRK(port)) 1770 sci_br_interrupt(irq, ptr); 1771 1772 /* Break only? */ 1773 if (!(ssr_status & SCxSR_ERRORS(port))) 1774 return IRQ_HANDLED; 1775 } 1776 1777 /* Handle errors */ 1778 if (port->type == PORT_SCI) { 1779 if (sci_handle_errors(port)) { 1780 /* discard character in rx buffer */ 1781 serial_port_in(port, SCxSR); 1782 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1783 } 1784 } else { 1785 sci_handle_fifo_overrun(port); 1786 if (!s->chan_rx) 1787 sci_receive_chars(port); 1788 } 1789 1790 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1791 1792 /* Kick the transmission */ 1793 if (!s->chan_tx) 1794 sci_tx_interrupt(irq, ptr); 1795 1796 return IRQ_HANDLED; 1797 } 1798 1799 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1800 { 1801 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1802 struct uart_port *port = ptr; 1803 struct sci_port *s = to_sci_port(port); 1804 irqreturn_t ret = IRQ_NONE; 1805 1806 ssr_status = serial_port_in(port, SCxSR); 1807 scr_status = serial_port_in(port, SCSCR); 1808 if (s->params->overrun_reg == SCxSR) 1809 orer_status = ssr_status; 1810 else if (sci_getreg(port, s->params->overrun_reg)->size) 1811 orer_status = serial_port_in(port, s->params->overrun_reg); 1812 1813 err_enabled = scr_status & port_rx_irq_mask(port); 1814 1815 /* Tx Interrupt */ 1816 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1817 !s->chan_tx) 1818 ret = sci_tx_interrupt(irq, ptr); 1819 1820 /* 1821 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1822 * DR flags 1823 */ 1824 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1825 (scr_status & SCSCR_RIE)) 1826 ret = sci_rx_interrupt(irq, ptr); 1827 1828 /* Error Interrupt */ 1829 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1830 ret = sci_er_interrupt(irq, ptr); 1831 1832 /* Break Interrupt */ 1833 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 1834 (ssr_status & SCxSR_BRK(port)) && err_enabled) 1835 ret = sci_br_interrupt(irq, ptr); 1836 1837 /* Overrun Interrupt */ 1838 if (orer_status & s->params->overrun_mask) { 1839 sci_handle_fifo_overrun(port); 1840 ret = IRQ_HANDLED; 1841 } 1842 1843 return ret; 1844 } 1845 1846 static const struct sci_irq_desc { 1847 const char *desc; 1848 irq_handler_t handler; 1849 } sci_irq_desc[] = { 1850 /* 1851 * Split out handlers, the default case. 1852 */ 1853 [SCIx_ERI_IRQ] = { 1854 .desc = "rx err", 1855 .handler = sci_er_interrupt, 1856 }, 1857 1858 [SCIx_RXI_IRQ] = { 1859 .desc = "rx full", 1860 .handler = sci_rx_interrupt, 1861 }, 1862 1863 [SCIx_TXI_IRQ] = { 1864 .desc = "tx empty", 1865 .handler = sci_tx_interrupt, 1866 }, 1867 1868 [SCIx_BRI_IRQ] = { 1869 .desc = "break", 1870 .handler = sci_br_interrupt, 1871 }, 1872 1873 [SCIx_DRI_IRQ] = { 1874 .desc = "rx ready", 1875 .handler = sci_rx_interrupt, 1876 }, 1877 1878 [SCIx_TEI_IRQ] = { 1879 .desc = "tx end", 1880 .handler = sci_tx_interrupt, 1881 }, 1882 1883 /* 1884 * Special muxed handler. 1885 */ 1886 [SCIx_MUX_IRQ] = { 1887 .desc = "mux", 1888 .handler = sci_mpxed_interrupt, 1889 }, 1890 }; 1891 1892 static int sci_request_irq(struct sci_port *port) 1893 { 1894 struct uart_port *up = &port->port; 1895 int i, j, w, ret = 0; 1896 1897 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1898 const struct sci_irq_desc *desc; 1899 int irq; 1900 1901 /* Check if already registered (muxed) */ 1902 for (w = 0; w < i; w++) 1903 if (port->irqs[w] == port->irqs[i]) 1904 w = i + 1; 1905 if (w > i) 1906 continue; 1907 1908 if (SCIx_IRQ_IS_MUXED(port)) { 1909 i = SCIx_MUX_IRQ; 1910 irq = up->irq; 1911 } else { 1912 irq = port->irqs[i]; 1913 1914 /* 1915 * Certain port types won't support all of the 1916 * available interrupt sources. 1917 */ 1918 if (unlikely(irq < 0)) 1919 continue; 1920 } 1921 1922 desc = sci_irq_desc + i; 1923 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1924 dev_name(up->dev), desc->desc); 1925 if (!port->irqstr[j]) { 1926 ret = -ENOMEM; 1927 goto out_nomem; 1928 } 1929 1930 ret = request_irq(irq, desc->handler, up->irqflags, 1931 port->irqstr[j], port); 1932 if (unlikely(ret)) { 1933 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1934 goto out_noirq; 1935 } 1936 } 1937 1938 return 0; 1939 1940 out_noirq: 1941 while (--i >= 0) 1942 free_irq(port->irqs[i], port); 1943 1944 out_nomem: 1945 while (--j >= 0) 1946 kfree(port->irqstr[j]); 1947 1948 return ret; 1949 } 1950 1951 static void sci_free_irq(struct sci_port *port) 1952 { 1953 int i, j; 1954 1955 /* 1956 * Intentionally in reverse order so we iterate over the muxed 1957 * IRQ first. 1958 */ 1959 for (i = 0; i < SCIx_NR_IRQS; i++) { 1960 int irq = port->irqs[i]; 1961 1962 /* 1963 * Certain port types won't support all of the available 1964 * interrupt sources. 1965 */ 1966 if (unlikely(irq < 0)) 1967 continue; 1968 1969 /* Check if already freed (irq was muxed) */ 1970 for (j = 0; j < i; j++) 1971 if (port->irqs[j] == irq) 1972 j = i + 1; 1973 if (j > i) 1974 continue; 1975 1976 free_irq(port->irqs[i], port); 1977 kfree(port->irqstr[i]); 1978 1979 if (SCIx_IRQ_IS_MUXED(port)) { 1980 /* If there's only one IRQ, we're done. */ 1981 return; 1982 } 1983 } 1984 } 1985 1986 static unsigned int sci_tx_empty(struct uart_port *port) 1987 { 1988 unsigned short status = serial_port_in(port, SCxSR); 1989 unsigned short in_tx_fifo = sci_txfill(port); 1990 1991 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1992 } 1993 1994 static void sci_set_rts(struct uart_port *port, bool state) 1995 { 1996 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1997 u16 data = serial_port_in(port, SCPDR); 1998 1999 /* Active low */ 2000 if (state) 2001 data &= ~SCPDR_RTSD; 2002 else 2003 data |= SCPDR_RTSD; 2004 serial_port_out(port, SCPDR, data); 2005 2006 /* RTS# is output */ 2007 serial_port_out(port, SCPCR, 2008 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2009 } else if (sci_getreg(port, SCSPTR)->size) { 2010 u16 ctrl = serial_port_in(port, SCSPTR); 2011 2012 /* Active low */ 2013 if (state) 2014 ctrl &= ~SCSPTR_RTSDT; 2015 else 2016 ctrl |= SCSPTR_RTSDT; 2017 serial_port_out(port, SCSPTR, ctrl); 2018 } 2019 } 2020 2021 static bool sci_get_cts(struct uart_port *port) 2022 { 2023 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2024 /* Active low */ 2025 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2026 } else if (sci_getreg(port, SCSPTR)->size) { 2027 /* Active low */ 2028 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2029 } 2030 2031 return true; 2032 } 2033 2034 /* 2035 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2036 * CTS/RTS is supported in hardware by at least one port and controlled 2037 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2038 * handled via the ->init_pins() op, which is a bit of a one-way street, 2039 * lacking any ability to defer pin control -- this will later be 2040 * converted over to the GPIO framework). 2041 * 2042 * Other modes (such as loopback) are supported generically on certain 2043 * port types, but not others. For these it's sufficient to test for the 2044 * existence of the support register and simply ignore the port type. 2045 */ 2046 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2047 { 2048 struct sci_port *s = to_sci_port(port); 2049 2050 if (mctrl & TIOCM_LOOP) { 2051 const struct plat_sci_reg *reg; 2052 2053 /* 2054 * Standard loopback mode for SCFCR ports. 2055 */ 2056 reg = sci_getreg(port, SCFCR); 2057 if (reg->size) 2058 serial_port_out(port, SCFCR, 2059 serial_port_in(port, SCFCR) | 2060 SCFCR_LOOP); 2061 } 2062 2063 mctrl_gpio_set(s->gpios, mctrl); 2064 2065 if (!s->has_rtscts) 2066 return; 2067 2068 if (!(mctrl & TIOCM_RTS)) { 2069 /* Disable Auto RTS */ 2070 serial_port_out(port, SCFCR, 2071 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2072 2073 /* Clear RTS */ 2074 sci_set_rts(port, 0); 2075 } else if (s->autorts) { 2076 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2077 /* Enable RTS# pin function */ 2078 serial_port_out(port, SCPCR, 2079 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2080 } 2081 2082 /* Enable Auto RTS */ 2083 serial_port_out(port, SCFCR, 2084 serial_port_in(port, SCFCR) | SCFCR_MCE); 2085 } else { 2086 /* Set RTS */ 2087 sci_set_rts(port, 1); 2088 } 2089 } 2090 2091 static unsigned int sci_get_mctrl(struct uart_port *port) 2092 { 2093 struct sci_port *s = to_sci_port(port); 2094 struct mctrl_gpios *gpios = s->gpios; 2095 unsigned int mctrl = 0; 2096 2097 mctrl_gpio_get(gpios, &mctrl); 2098 2099 /* 2100 * CTS/RTS is handled in hardware when supported, while nothing 2101 * else is wired up. 2102 */ 2103 if (s->autorts) { 2104 if (sci_get_cts(port)) 2105 mctrl |= TIOCM_CTS; 2106 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2107 mctrl |= TIOCM_CTS; 2108 } 2109 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2110 mctrl |= TIOCM_DSR; 2111 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2112 mctrl |= TIOCM_CAR; 2113 2114 return mctrl; 2115 } 2116 2117 static void sci_enable_ms(struct uart_port *port) 2118 { 2119 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2120 } 2121 2122 static void sci_break_ctl(struct uart_port *port, int break_state) 2123 { 2124 unsigned short scscr, scsptr; 2125 unsigned long flags; 2126 2127 /* check whether the port has SCSPTR */ 2128 if (!sci_getreg(port, SCSPTR)->size) { 2129 /* 2130 * Not supported by hardware. Most parts couple break and rx 2131 * interrupts together, with break detection always enabled. 2132 */ 2133 return; 2134 } 2135 2136 spin_lock_irqsave(&port->lock, flags); 2137 scsptr = serial_port_in(port, SCSPTR); 2138 scscr = serial_port_in(port, SCSCR); 2139 2140 if (break_state == -1) { 2141 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2142 scscr &= ~SCSCR_TE; 2143 } else { 2144 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2145 scscr |= SCSCR_TE; 2146 } 2147 2148 serial_port_out(port, SCSPTR, scsptr); 2149 serial_port_out(port, SCSCR, scscr); 2150 spin_unlock_irqrestore(&port->lock, flags); 2151 } 2152 2153 static int sci_startup(struct uart_port *port) 2154 { 2155 struct sci_port *s = to_sci_port(port); 2156 int ret; 2157 2158 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2159 2160 sci_request_dma(port); 2161 2162 ret = sci_request_irq(s); 2163 if (unlikely(ret < 0)) { 2164 sci_free_dma(port); 2165 return ret; 2166 } 2167 2168 return 0; 2169 } 2170 2171 static void sci_shutdown(struct uart_port *port) 2172 { 2173 struct sci_port *s = to_sci_port(port); 2174 unsigned long flags; 2175 u16 scr; 2176 2177 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2178 2179 s->autorts = false; 2180 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2181 2182 spin_lock_irqsave(&port->lock, flags); 2183 sci_stop_rx(port); 2184 sci_stop_tx(port); 2185 /* 2186 * Stop RX and TX, disable related interrupts, keep clock source 2187 * and HSCIF TOT bits 2188 */ 2189 scr = serial_port_in(port, SCSCR); 2190 serial_port_out(port, SCSCR, scr & 2191 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2192 spin_unlock_irqrestore(&port->lock, flags); 2193 2194 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2195 if (s->chan_rx_saved) { 2196 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2197 port->line); 2198 hrtimer_cancel(&s->rx_timer); 2199 } 2200 #endif 2201 2202 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2203 del_timer_sync(&s->rx_fifo_timer); 2204 sci_free_irq(s); 2205 sci_free_dma(port); 2206 } 2207 2208 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2209 unsigned int *srr) 2210 { 2211 unsigned long freq = s->clk_rates[SCI_SCK]; 2212 int err, min_err = INT_MAX; 2213 unsigned int sr; 2214 2215 if (s->port.type != PORT_HSCIF) 2216 freq *= 2; 2217 2218 for_each_sr(sr, s) { 2219 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2220 if (abs(err) >= abs(min_err)) 2221 continue; 2222 2223 min_err = err; 2224 *srr = sr - 1; 2225 2226 if (!err) 2227 break; 2228 } 2229 2230 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2231 *srr + 1); 2232 return min_err; 2233 } 2234 2235 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2236 unsigned long freq, unsigned int *dlr, 2237 unsigned int *srr) 2238 { 2239 int err, min_err = INT_MAX; 2240 unsigned int sr, dl; 2241 2242 if (s->port.type != PORT_HSCIF) 2243 freq *= 2; 2244 2245 for_each_sr(sr, s) { 2246 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2247 dl = clamp(dl, 1U, 65535U); 2248 2249 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2250 if (abs(err) >= abs(min_err)) 2251 continue; 2252 2253 min_err = err; 2254 *dlr = dl; 2255 *srr = sr - 1; 2256 2257 if (!err) 2258 break; 2259 } 2260 2261 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2262 min_err, *dlr, *srr + 1); 2263 return min_err; 2264 } 2265 2266 /* calculate sample rate, BRR, and clock select */ 2267 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2268 unsigned int *brr, unsigned int *srr, 2269 unsigned int *cks) 2270 { 2271 unsigned long freq = s->clk_rates[SCI_FCK]; 2272 unsigned int sr, br, prediv, scrate, c; 2273 int err, min_err = INT_MAX; 2274 2275 if (s->port.type != PORT_HSCIF) 2276 freq *= 2; 2277 2278 /* 2279 * Find the combination of sample rate and clock select with the 2280 * smallest deviation from the desired baud rate. 2281 * Prefer high sample rates to maximise the receive margin. 2282 * 2283 * M: Receive margin (%) 2284 * N: Ratio of bit rate to clock (N = sampling rate) 2285 * D: Clock duty (D = 0 to 1.0) 2286 * L: Frame length (L = 9 to 12) 2287 * F: Absolute value of clock frequency deviation 2288 * 2289 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2290 * (|D - 0.5| / N * (1 + F))| 2291 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2292 */ 2293 for_each_sr(sr, s) { 2294 for (c = 0; c <= 3; c++) { 2295 /* integerized formulas from HSCIF documentation */ 2296 prediv = sr << (2 * c + 1); 2297 2298 /* 2299 * We need to calculate: 2300 * 2301 * br = freq / (prediv * bps) clamped to [1..256] 2302 * err = freq / (br * prediv) - bps 2303 * 2304 * Watch out for overflow when calculating the desired 2305 * sampling clock rate! 2306 */ 2307 if (bps > UINT_MAX / prediv) 2308 break; 2309 2310 scrate = prediv * bps; 2311 br = DIV_ROUND_CLOSEST(freq, scrate); 2312 br = clamp(br, 1U, 256U); 2313 2314 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2315 if (abs(err) >= abs(min_err)) 2316 continue; 2317 2318 min_err = err; 2319 *brr = br - 1; 2320 *srr = sr - 1; 2321 *cks = c; 2322 2323 if (!err) 2324 goto found; 2325 } 2326 } 2327 2328 found: 2329 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2330 min_err, *brr, *srr + 1, *cks); 2331 return min_err; 2332 } 2333 2334 static void sci_reset(struct uart_port *port) 2335 { 2336 const struct plat_sci_reg *reg; 2337 unsigned int status; 2338 struct sci_port *s = to_sci_port(port); 2339 2340 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2341 2342 reg = sci_getreg(port, SCFCR); 2343 if (reg->size) 2344 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2345 2346 sci_clear_SCxSR(port, 2347 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2348 SCxSR_BREAK_CLEAR(port)); 2349 if (sci_getreg(port, SCLSR)->size) { 2350 status = serial_port_in(port, SCLSR); 2351 status &= ~(SCLSR_TO | SCLSR_ORER); 2352 serial_port_out(port, SCLSR, status); 2353 } 2354 2355 if (s->rx_trigger > 1) { 2356 if (s->rx_fifo_timeout) { 2357 scif_set_rtrg(port, 1); 2358 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2359 } else { 2360 if (port->type == PORT_SCIFA || 2361 port->type == PORT_SCIFB) 2362 scif_set_rtrg(port, 1); 2363 else 2364 scif_set_rtrg(port, s->rx_trigger); 2365 } 2366 } 2367 } 2368 2369 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2370 struct ktermios *old) 2371 { 2372 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2373 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2374 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2375 struct sci_port *s = to_sci_port(port); 2376 const struct plat_sci_reg *reg; 2377 int min_err = INT_MAX, err; 2378 unsigned long max_freq = 0; 2379 int best_clk = -1; 2380 unsigned long flags; 2381 2382 if ((termios->c_cflag & CSIZE) == CS7) 2383 smr_val |= SCSMR_CHR; 2384 if (termios->c_cflag & PARENB) 2385 smr_val |= SCSMR_PE; 2386 if (termios->c_cflag & PARODD) 2387 smr_val |= SCSMR_PE | SCSMR_ODD; 2388 if (termios->c_cflag & CSTOPB) 2389 smr_val |= SCSMR_STOP; 2390 2391 /* 2392 * earlyprintk comes here early on with port->uartclk set to zero. 2393 * the clock framework is not up and running at this point so here 2394 * we assume that 115200 is the maximum baud rate. please note that 2395 * the baud rate is not programmed during earlyprintk - it is assumed 2396 * that the previous boot loader has enabled required clocks and 2397 * setup the baud rate generator hardware for us already. 2398 */ 2399 if (!port->uartclk) { 2400 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2401 goto done; 2402 } 2403 2404 for (i = 0; i < SCI_NUM_CLKS; i++) 2405 max_freq = max(max_freq, s->clk_rates[i]); 2406 2407 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2408 if (!baud) 2409 goto done; 2410 2411 /* 2412 * There can be multiple sources for the sampling clock. Find the one 2413 * that gives us the smallest deviation from the desired baud rate. 2414 */ 2415 2416 /* Optional Undivided External Clock */ 2417 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2418 port->type != PORT_SCIFB) { 2419 err = sci_sck_calc(s, baud, &srr1); 2420 if (abs(err) < abs(min_err)) { 2421 best_clk = SCI_SCK; 2422 scr_val = SCSCR_CKE1; 2423 sccks = SCCKS_CKS; 2424 min_err = err; 2425 srr = srr1; 2426 if (!err) 2427 goto done; 2428 } 2429 } 2430 2431 /* Optional BRG Frequency Divided External Clock */ 2432 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2433 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2434 &srr1); 2435 if (abs(err) < abs(min_err)) { 2436 best_clk = SCI_SCIF_CLK; 2437 scr_val = SCSCR_CKE1; 2438 sccks = 0; 2439 min_err = err; 2440 dl = dl1; 2441 srr = srr1; 2442 if (!err) 2443 goto done; 2444 } 2445 } 2446 2447 /* Optional BRG Frequency Divided Internal Clock */ 2448 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2449 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2450 &srr1); 2451 if (abs(err) < abs(min_err)) { 2452 best_clk = SCI_BRG_INT; 2453 scr_val = SCSCR_CKE1; 2454 sccks = SCCKS_XIN; 2455 min_err = err; 2456 dl = dl1; 2457 srr = srr1; 2458 if (!min_err) 2459 goto done; 2460 } 2461 } 2462 2463 /* Divided Functional Clock using standard Bit Rate Register */ 2464 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2465 if (abs(err) < abs(min_err)) { 2466 best_clk = SCI_FCK; 2467 scr_val = 0; 2468 min_err = err; 2469 brr = brr1; 2470 srr = srr1; 2471 cks = cks1; 2472 } 2473 2474 done: 2475 if (best_clk >= 0) 2476 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2477 s->clks[best_clk], baud, min_err); 2478 2479 sci_port_enable(s); 2480 2481 /* 2482 * Program the optional External Baud Rate Generator (BRG) first. 2483 * It controls the mux to select (H)SCK or frequency divided clock. 2484 */ 2485 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2486 serial_port_out(port, SCDL, dl); 2487 serial_port_out(port, SCCKS, sccks); 2488 } 2489 2490 spin_lock_irqsave(&port->lock, flags); 2491 2492 sci_reset(port); 2493 2494 uart_update_timeout(port, termios->c_cflag, baud); 2495 2496 /* byte size and parity */ 2497 bits = tty_get_frame_size(termios->c_cflag); 2498 2499 if (sci_getreg(port, SEMR)->size) 2500 serial_port_out(port, SEMR, 0); 2501 2502 if (best_clk >= 0) { 2503 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2504 switch (srr + 1) { 2505 case 5: smr_val |= SCSMR_SRC_5; break; 2506 case 7: smr_val |= SCSMR_SRC_7; break; 2507 case 11: smr_val |= SCSMR_SRC_11; break; 2508 case 13: smr_val |= SCSMR_SRC_13; break; 2509 case 16: smr_val |= SCSMR_SRC_16; break; 2510 case 17: smr_val |= SCSMR_SRC_17; break; 2511 case 19: smr_val |= SCSMR_SRC_19; break; 2512 case 27: smr_val |= SCSMR_SRC_27; break; 2513 } 2514 smr_val |= cks; 2515 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2516 serial_port_out(port, SCSMR, smr_val); 2517 serial_port_out(port, SCBRR, brr); 2518 if (sci_getreg(port, HSSRR)->size) { 2519 unsigned int hssrr = srr | HSCIF_SRE; 2520 /* Calculate deviation from intended rate at the 2521 * center of the last stop bit in sampling clocks. 2522 */ 2523 int last_stop = bits * 2 - 1; 2524 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2525 (int)(srr + 1), 2526 2 * (int)baud); 2527 2528 if (abs(deviation) >= 2) { 2529 /* At least two sampling clocks off at the 2530 * last stop bit; we can increase the error 2531 * margin by shifting the sampling point. 2532 */ 2533 int shift = clamp(deviation / 2, -8, 7); 2534 2535 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2536 HSCIF_SRHP_MASK; 2537 hssrr |= HSCIF_SRDE; 2538 } 2539 serial_port_out(port, HSSRR, hssrr); 2540 } 2541 2542 /* Wait one bit interval */ 2543 udelay((1000000 + (baud - 1)) / baud); 2544 } else { 2545 /* Don't touch the bit rate configuration */ 2546 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2547 smr_val |= serial_port_in(port, SCSMR) & 2548 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2549 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2550 serial_port_out(port, SCSMR, smr_val); 2551 } 2552 2553 sci_init_pins(port, termios->c_cflag); 2554 2555 port->status &= ~UPSTAT_AUTOCTS; 2556 s->autorts = false; 2557 reg = sci_getreg(port, SCFCR); 2558 if (reg->size) { 2559 unsigned short ctrl = serial_port_in(port, SCFCR); 2560 2561 if ((port->flags & UPF_HARD_FLOW) && 2562 (termios->c_cflag & CRTSCTS)) { 2563 /* There is no CTS interrupt to restart the hardware */ 2564 port->status |= UPSTAT_AUTOCTS; 2565 /* MCE is enabled when RTS is raised */ 2566 s->autorts = true; 2567 } 2568 2569 /* 2570 * As we've done a sci_reset() above, ensure we don't 2571 * interfere with the FIFOs while toggling MCE. As the 2572 * reset values could still be set, simply mask them out. 2573 */ 2574 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2575 2576 serial_port_out(port, SCFCR, ctrl); 2577 } 2578 if (port->flags & UPF_HARD_FLOW) { 2579 /* Refresh (Auto) RTS */ 2580 sci_set_mctrl(port, port->mctrl); 2581 } 2582 2583 scr_val |= SCSCR_RE | SCSCR_TE | 2584 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2585 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2586 if ((srr + 1 == 5) && 2587 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2588 /* 2589 * In asynchronous mode, when the sampling rate is 1/5, first 2590 * received data may become invalid on some SCIFA and SCIFB. 2591 * To avoid this problem wait more than 1 serial data time (1 2592 * bit time x serial data number) after setting SCSCR.RE = 1. 2593 */ 2594 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2595 } 2596 2597 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2598 s->rx_frame = (10000 * bits) / (baud / 100); 2599 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2600 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2601 #endif 2602 2603 if ((termios->c_cflag & CREAD) != 0) 2604 sci_start_rx(port); 2605 2606 spin_unlock_irqrestore(&port->lock, flags); 2607 2608 sci_port_disable(s); 2609 2610 if (UART_ENABLE_MS(port, termios->c_cflag)) 2611 sci_enable_ms(port); 2612 } 2613 2614 static void sci_pm(struct uart_port *port, unsigned int state, 2615 unsigned int oldstate) 2616 { 2617 struct sci_port *sci_port = to_sci_port(port); 2618 2619 switch (state) { 2620 case UART_PM_STATE_OFF: 2621 sci_port_disable(sci_port); 2622 break; 2623 default: 2624 sci_port_enable(sci_port); 2625 break; 2626 } 2627 } 2628 2629 static const char *sci_type(struct uart_port *port) 2630 { 2631 switch (port->type) { 2632 case PORT_IRDA: 2633 return "irda"; 2634 case PORT_SCI: 2635 return "sci"; 2636 case PORT_SCIF: 2637 return "scif"; 2638 case PORT_SCIFA: 2639 return "scifa"; 2640 case PORT_SCIFB: 2641 return "scifb"; 2642 case PORT_HSCIF: 2643 return "hscif"; 2644 } 2645 2646 return NULL; 2647 } 2648 2649 static int sci_remap_port(struct uart_port *port) 2650 { 2651 struct sci_port *sport = to_sci_port(port); 2652 2653 /* 2654 * Nothing to do if there's already an established membase. 2655 */ 2656 if (port->membase) 2657 return 0; 2658 2659 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2660 port->membase = ioremap(port->mapbase, sport->reg_size); 2661 if (unlikely(!port->membase)) { 2662 dev_err(port->dev, "can't remap port#%d\n", port->line); 2663 return -ENXIO; 2664 } 2665 } else { 2666 /* 2667 * For the simple (and majority of) cases where we don't 2668 * need to do any remapping, just cast the cookie 2669 * directly. 2670 */ 2671 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2672 } 2673 2674 return 0; 2675 } 2676 2677 static void sci_release_port(struct uart_port *port) 2678 { 2679 struct sci_port *sport = to_sci_port(port); 2680 2681 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2682 iounmap(port->membase); 2683 port->membase = NULL; 2684 } 2685 2686 release_mem_region(port->mapbase, sport->reg_size); 2687 } 2688 2689 static int sci_request_port(struct uart_port *port) 2690 { 2691 struct resource *res; 2692 struct sci_port *sport = to_sci_port(port); 2693 int ret; 2694 2695 res = request_mem_region(port->mapbase, sport->reg_size, 2696 dev_name(port->dev)); 2697 if (unlikely(res == NULL)) { 2698 dev_err(port->dev, "request_mem_region failed."); 2699 return -EBUSY; 2700 } 2701 2702 ret = sci_remap_port(port); 2703 if (unlikely(ret != 0)) { 2704 release_resource(res); 2705 return ret; 2706 } 2707 2708 return 0; 2709 } 2710 2711 static void sci_config_port(struct uart_port *port, int flags) 2712 { 2713 if (flags & UART_CONFIG_TYPE) { 2714 struct sci_port *sport = to_sci_port(port); 2715 2716 port->type = sport->cfg->type; 2717 sci_request_port(port); 2718 } 2719 } 2720 2721 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2722 { 2723 if (ser->baud_base < 2400) 2724 /* No paper tape reader for Mitch.. */ 2725 return -EINVAL; 2726 2727 return 0; 2728 } 2729 2730 static const struct uart_ops sci_uart_ops = { 2731 .tx_empty = sci_tx_empty, 2732 .set_mctrl = sci_set_mctrl, 2733 .get_mctrl = sci_get_mctrl, 2734 .start_tx = sci_start_tx, 2735 .stop_tx = sci_stop_tx, 2736 .stop_rx = sci_stop_rx, 2737 .enable_ms = sci_enable_ms, 2738 .break_ctl = sci_break_ctl, 2739 .startup = sci_startup, 2740 .shutdown = sci_shutdown, 2741 .flush_buffer = sci_flush_buffer, 2742 .set_termios = sci_set_termios, 2743 .pm = sci_pm, 2744 .type = sci_type, 2745 .release_port = sci_release_port, 2746 .request_port = sci_request_port, 2747 .config_port = sci_config_port, 2748 .verify_port = sci_verify_port, 2749 #ifdef CONFIG_CONSOLE_POLL 2750 .poll_get_char = sci_poll_get_char, 2751 .poll_put_char = sci_poll_put_char, 2752 #endif 2753 }; 2754 2755 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2756 { 2757 const char *clk_names[] = { 2758 [SCI_FCK] = "fck", 2759 [SCI_SCK] = "sck", 2760 [SCI_BRG_INT] = "brg_int", 2761 [SCI_SCIF_CLK] = "scif_clk", 2762 }; 2763 struct clk *clk; 2764 unsigned int i; 2765 2766 if (sci_port->cfg->type == PORT_HSCIF) 2767 clk_names[SCI_SCK] = "hsck"; 2768 2769 for (i = 0; i < SCI_NUM_CLKS; i++) { 2770 clk = devm_clk_get_optional(dev, clk_names[i]); 2771 if (IS_ERR(clk)) 2772 return PTR_ERR(clk); 2773 2774 if (!clk && i == SCI_FCK) { 2775 /* 2776 * Not all SH platforms declare a clock lookup entry 2777 * for SCI devices, in which case we need to get the 2778 * global "peripheral_clk" clock. 2779 */ 2780 clk = devm_clk_get(dev, "peripheral_clk"); 2781 if (IS_ERR(clk)) 2782 return dev_err_probe(dev, PTR_ERR(clk), 2783 "failed to get %s\n", 2784 clk_names[i]); 2785 } 2786 2787 if (!clk) 2788 dev_dbg(dev, "failed to get %s\n", clk_names[i]); 2789 else 2790 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2791 clk, clk_get_rate(clk)); 2792 sci_port->clks[i] = clk; 2793 } 2794 return 0; 2795 } 2796 2797 static const struct sci_port_params * 2798 sci_probe_regmap(const struct plat_sci_port *cfg) 2799 { 2800 unsigned int regtype; 2801 2802 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2803 return &sci_port_params[cfg->regtype]; 2804 2805 switch (cfg->type) { 2806 case PORT_SCI: 2807 regtype = SCIx_SCI_REGTYPE; 2808 break; 2809 case PORT_IRDA: 2810 regtype = SCIx_IRDA_REGTYPE; 2811 break; 2812 case PORT_SCIFA: 2813 regtype = SCIx_SCIFA_REGTYPE; 2814 break; 2815 case PORT_SCIFB: 2816 regtype = SCIx_SCIFB_REGTYPE; 2817 break; 2818 case PORT_SCIF: 2819 /* 2820 * The SH-4 is a bit of a misnomer here, although that's 2821 * where this particular port layout originated. This 2822 * configuration (or some slight variation thereof) 2823 * remains the dominant model for all SCIFs. 2824 */ 2825 regtype = SCIx_SH4_SCIF_REGTYPE; 2826 break; 2827 case PORT_HSCIF: 2828 regtype = SCIx_HSCIF_REGTYPE; 2829 break; 2830 default: 2831 pr_err("Can't probe register map for given port\n"); 2832 return NULL; 2833 } 2834 2835 return &sci_port_params[regtype]; 2836 } 2837 2838 static int sci_init_single(struct platform_device *dev, 2839 struct sci_port *sci_port, unsigned int index, 2840 const struct plat_sci_port *p, bool early) 2841 { 2842 struct uart_port *port = &sci_port->port; 2843 const struct resource *res; 2844 unsigned int i; 2845 int ret; 2846 2847 sci_port->cfg = p; 2848 2849 port->ops = &sci_uart_ops; 2850 port->iotype = UPIO_MEM; 2851 port->line = index; 2852 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2853 2854 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2855 if (res == NULL) 2856 return -ENOMEM; 2857 2858 port->mapbase = res->start; 2859 sci_port->reg_size = resource_size(res); 2860 2861 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2862 if (i) 2863 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2864 else 2865 sci_port->irqs[i] = platform_get_irq(dev, i); 2866 } 2867 2868 /* The SCI generates several interrupts. They can be muxed together or 2869 * connected to different interrupt lines. In the muxed case only one 2870 * interrupt resource is specified as there is only one interrupt ID. 2871 * In the non-muxed case, up to 6 interrupt signals might be generated 2872 * from the SCI, however those signals might have their own individual 2873 * interrupt ID numbers, or muxed together with another interrupt. 2874 */ 2875 if (sci_port->irqs[0] < 0) 2876 return -ENXIO; 2877 2878 if (sci_port->irqs[1] < 0) 2879 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2880 sci_port->irqs[i] = sci_port->irqs[0]; 2881 2882 sci_port->params = sci_probe_regmap(p); 2883 if (unlikely(sci_port->params == NULL)) 2884 return -EINVAL; 2885 2886 switch (p->type) { 2887 case PORT_SCIFB: 2888 sci_port->rx_trigger = 48; 2889 break; 2890 case PORT_HSCIF: 2891 sci_port->rx_trigger = 64; 2892 break; 2893 case PORT_SCIFA: 2894 sci_port->rx_trigger = 32; 2895 break; 2896 case PORT_SCIF: 2897 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2898 /* RX triggering not implemented for this IP */ 2899 sci_port->rx_trigger = 1; 2900 else 2901 sci_port->rx_trigger = 8; 2902 break; 2903 default: 2904 sci_port->rx_trigger = 1; 2905 break; 2906 } 2907 2908 sci_port->rx_fifo_timeout = 0; 2909 sci_port->hscif_tot = 0; 2910 2911 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2912 * match the SoC datasheet, this should be investigated. Let platform 2913 * data override the sampling rate for now. 2914 */ 2915 sci_port->sampling_rate_mask = p->sampling_rate 2916 ? SCI_SR(p->sampling_rate) 2917 : sci_port->params->sampling_rate_mask; 2918 2919 if (!early) { 2920 ret = sci_init_clocks(sci_port, &dev->dev); 2921 if (ret < 0) 2922 return ret; 2923 2924 port->dev = &dev->dev; 2925 2926 pm_runtime_enable(&dev->dev); 2927 } 2928 2929 port->type = p->type; 2930 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2931 port->fifosize = sci_port->params->fifosize; 2932 2933 if (port->type == PORT_SCI) { 2934 if (sci_port->reg_size >= 0x20) 2935 port->regshift = 2; 2936 else 2937 port->regshift = 1; 2938 } 2939 2940 /* 2941 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2942 * for the multi-IRQ ports, which is where we are primarily 2943 * concerned with the shutdown path synchronization. 2944 * 2945 * For the muxed case there's nothing more to do. 2946 */ 2947 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2948 port->irqflags = 0; 2949 2950 port->serial_in = sci_serial_in; 2951 port->serial_out = sci_serial_out; 2952 2953 return 0; 2954 } 2955 2956 static void sci_cleanup_single(struct sci_port *port) 2957 { 2958 pm_runtime_disable(port->port.dev); 2959 } 2960 2961 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 2962 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 2963 static void serial_console_putchar(struct uart_port *port, unsigned char ch) 2964 { 2965 sci_poll_put_char(port, ch); 2966 } 2967 2968 /* 2969 * Print a string to the serial port trying not to disturb 2970 * any possible real use of the port... 2971 */ 2972 static void serial_console_write(struct console *co, const char *s, 2973 unsigned count) 2974 { 2975 struct sci_port *sci_port = &sci_ports[co->index]; 2976 struct uart_port *port = &sci_port->port; 2977 unsigned short bits, ctrl, ctrl_temp; 2978 unsigned long flags; 2979 int locked = 1; 2980 2981 if (port->sysrq) 2982 locked = 0; 2983 else if (oops_in_progress) 2984 locked = spin_trylock_irqsave(&port->lock, flags); 2985 else 2986 spin_lock_irqsave(&port->lock, flags); 2987 2988 /* first save SCSCR then disable interrupts, keep clock source */ 2989 ctrl = serial_port_in(port, SCSCR); 2990 ctrl_temp = SCSCR_RE | SCSCR_TE | 2991 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 2992 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 2993 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 2994 2995 uart_console_write(port, s, count, serial_console_putchar); 2996 2997 /* wait until fifo is empty and last bit has been transmitted */ 2998 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 2999 while ((serial_port_in(port, SCxSR) & bits) != bits) 3000 cpu_relax(); 3001 3002 /* restore the SCSCR */ 3003 serial_port_out(port, SCSCR, ctrl); 3004 3005 if (locked) 3006 spin_unlock_irqrestore(&port->lock, flags); 3007 } 3008 3009 static int serial_console_setup(struct console *co, char *options) 3010 { 3011 struct sci_port *sci_port; 3012 struct uart_port *port; 3013 int baud = 115200; 3014 int bits = 8; 3015 int parity = 'n'; 3016 int flow = 'n'; 3017 int ret; 3018 3019 /* 3020 * Refuse to handle any bogus ports. 3021 */ 3022 if (co->index < 0 || co->index >= SCI_NPORTS) 3023 return -ENODEV; 3024 3025 sci_port = &sci_ports[co->index]; 3026 port = &sci_port->port; 3027 3028 /* 3029 * Refuse to handle uninitialized ports. 3030 */ 3031 if (!port->ops) 3032 return -ENODEV; 3033 3034 ret = sci_remap_port(port); 3035 if (unlikely(ret != 0)) 3036 return ret; 3037 3038 if (options) 3039 uart_parse_options(options, &baud, &parity, &bits, &flow); 3040 3041 return uart_set_options(port, co, baud, parity, bits, flow); 3042 } 3043 3044 static struct console serial_console = { 3045 .name = "ttySC", 3046 .device = uart_console_device, 3047 .write = serial_console_write, 3048 .setup = serial_console_setup, 3049 .flags = CON_PRINTBUFFER, 3050 .index = -1, 3051 .data = &sci_uart_driver, 3052 }; 3053 3054 #ifdef CONFIG_SUPERH 3055 static struct console early_serial_console = { 3056 .name = "early_ttySC", 3057 .write = serial_console_write, 3058 .flags = CON_PRINTBUFFER, 3059 .index = -1, 3060 }; 3061 3062 static char early_serial_buf[32]; 3063 3064 static int sci_probe_earlyprintk(struct platform_device *pdev) 3065 { 3066 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3067 3068 if (early_serial_console.data) 3069 return -EEXIST; 3070 3071 early_serial_console.index = pdev->id; 3072 3073 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3074 3075 serial_console_setup(&early_serial_console, early_serial_buf); 3076 3077 if (!strstr(early_serial_buf, "keep")) 3078 early_serial_console.flags |= CON_BOOT; 3079 3080 register_console(&early_serial_console); 3081 return 0; 3082 } 3083 #endif 3084 3085 #define SCI_CONSOLE (&serial_console) 3086 3087 #else 3088 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3089 { 3090 return -EINVAL; 3091 } 3092 3093 #define SCI_CONSOLE NULL 3094 3095 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3096 3097 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3098 3099 static DEFINE_MUTEX(sci_uart_registration_lock); 3100 static struct uart_driver sci_uart_driver = { 3101 .owner = THIS_MODULE, 3102 .driver_name = "sci", 3103 .dev_name = "ttySC", 3104 .major = SCI_MAJOR, 3105 .minor = SCI_MINOR_START, 3106 .nr = SCI_NPORTS, 3107 .cons = SCI_CONSOLE, 3108 }; 3109 3110 static int sci_remove(struct platform_device *dev) 3111 { 3112 struct sci_port *port = platform_get_drvdata(dev); 3113 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3114 3115 sci_ports_in_use &= ~BIT(port->port.line); 3116 uart_remove_one_port(&sci_uart_driver, &port->port); 3117 3118 sci_cleanup_single(port); 3119 3120 if (port->port.fifosize > 1) 3121 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3122 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3123 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3124 3125 return 0; 3126 } 3127 3128 3129 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3130 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3131 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3132 3133 static const struct of_device_id of_sci_match[] = { 3134 /* SoC-specific types */ 3135 { 3136 .compatible = "renesas,scif-r7s72100", 3137 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3138 }, 3139 { 3140 .compatible = "renesas,scif-r7s9210", 3141 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3142 }, 3143 { 3144 .compatible = "renesas,scif-r9a07g044", 3145 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3146 }, 3147 /* Family-specific types */ 3148 { 3149 .compatible = "renesas,rcar-gen1-scif", 3150 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3151 }, { 3152 .compatible = "renesas,rcar-gen2-scif", 3153 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3154 }, { 3155 .compatible = "renesas,rcar-gen3-scif", 3156 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3157 }, { 3158 .compatible = "renesas,rcar-gen4-scif", 3159 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3160 }, 3161 /* Generic types */ 3162 { 3163 .compatible = "renesas,scif", 3164 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3165 }, { 3166 .compatible = "renesas,scifa", 3167 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3168 }, { 3169 .compatible = "renesas,scifb", 3170 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3171 }, { 3172 .compatible = "renesas,hscif", 3173 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3174 }, { 3175 .compatible = "renesas,sci", 3176 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3177 }, { 3178 /* Terminator */ 3179 }, 3180 }; 3181 MODULE_DEVICE_TABLE(of, of_sci_match); 3182 3183 static void sci_reset_control_assert(void *data) 3184 { 3185 reset_control_assert(data); 3186 } 3187 3188 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3189 unsigned int *dev_id) 3190 { 3191 struct device_node *np = pdev->dev.of_node; 3192 struct reset_control *rstc; 3193 struct plat_sci_port *p; 3194 struct sci_port *sp; 3195 const void *data; 3196 int id, ret; 3197 3198 if (!IS_ENABLED(CONFIG_OF) || !np) 3199 return ERR_PTR(-EINVAL); 3200 3201 data = of_device_get_match_data(&pdev->dev); 3202 3203 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3204 if (IS_ERR(rstc)) 3205 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3206 "failed to get reset ctrl\n")); 3207 3208 ret = reset_control_deassert(rstc); 3209 if (ret) { 3210 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3211 return ERR_PTR(ret); 3212 } 3213 3214 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3215 if (ret) { 3216 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3217 ret); 3218 return ERR_PTR(ret); 3219 } 3220 3221 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3222 if (!p) 3223 return ERR_PTR(-ENOMEM); 3224 3225 /* Get the line number from the aliases node. */ 3226 id = of_alias_get_id(np, "serial"); 3227 if (id < 0 && ~sci_ports_in_use) 3228 id = ffz(sci_ports_in_use); 3229 if (id < 0) { 3230 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3231 return ERR_PTR(-EINVAL); 3232 } 3233 if (id >= ARRAY_SIZE(sci_ports)) { 3234 dev_err(&pdev->dev, "serial%d out of range\n", id); 3235 return ERR_PTR(-EINVAL); 3236 } 3237 3238 sp = &sci_ports[id]; 3239 *dev_id = id; 3240 3241 p->type = SCI_OF_TYPE(data); 3242 p->regtype = SCI_OF_REGTYPE(data); 3243 3244 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3245 3246 return p; 3247 } 3248 3249 static int sci_probe_single(struct platform_device *dev, 3250 unsigned int index, 3251 struct plat_sci_port *p, 3252 struct sci_port *sciport) 3253 { 3254 int ret; 3255 3256 /* Sanity check */ 3257 if (unlikely(index >= SCI_NPORTS)) { 3258 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3259 index+1, SCI_NPORTS); 3260 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3261 return -EINVAL; 3262 } 3263 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3264 if (sci_ports_in_use & BIT(index)) 3265 return -EBUSY; 3266 3267 mutex_lock(&sci_uart_registration_lock); 3268 if (!sci_uart_driver.state) { 3269 ret = uart_register_driver(&sci_uart_driver); 3270 if (ret) { 3271 mutex_unlock(&sci_uart_registration_lock); 3272 return ret; 3273 } 3274 } 3275 mutex_unlock(&sci_uart_registration_lock); 3276 3277 ret = sci_init_single(dev, sciport, index, p, false); 3278 if (ret) 3279 return ret; 3280 3281 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3282 if (IS_ERR(sciport->gpios)) 3283 return PTR_ERR(sciport->gpios); 3284 3285 if (sciport->has_rtscts) { 3286 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3287 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3288 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3289 return -EINVAL; 3290 } 3291 sciport->port.flags |= UPF_HARD_FLOW; 3292 } 3293 3294 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3295 if (ret) { 3296 sci_cleanup_single(sciport); 3297 return ret; 3298 } 3299 3300 return 0; 3301 } 3302 3303 static int sci_probe(struct platform_device *dev) 3304 { 3305 struct plat_sci_port *p; 3306 struct sci_port *sp; 3307 unsigned int dev_id; 3308 int ret; 3309 3310 /* 3311 * If we've come here via earlyprintk initialization, head off to 3312 * the special early probe. We don't have sufficient device state 3313 * to make it beyond this yet. 3314 */ 3315 #ifdef CONFIG_SUPERH 3316 if (is_sh_early_platform_device(dev)) 3317 return sci_probe_earlyprintk(dev); 3318 #endif 3319 3320 if (dev->dev.of_node) { 3321 p = sci_parse_dt(dev, &dev_id); 3322 if (IS_ERR(p)) 3323 return PTR_ERR(p); 3324 } else { 3325 p = dev->dev.platform_data; 3326 if (p == NULL) { 3327 dev_err(&dev->dev, "no platform data supplied\n"); 3328 return -EINVAL; 3329 } 3330 3331 dev_id = dev->id; 3332 } 3333 3334 sp = &sci_ports[dev_id]; 3335 platform_set_drvdata(dev, sp); 3336 3337 ret = sci_probe_single(dev, dev_id, p, sp); 3338 if (ret) 3339 return ret; 3340 3341 if (sp->port.fifosize > 1) { 3342 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3343 if (ret) 3344 return ret; 3345 } 3346 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3347 sp->port.type == PORT_HSCIF) { 3348 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3349 if (ret) { 3350 if (sp->port.fifosize > 1) { 3351 device_remove_file(&dev->dev, 3352 &dev_attr_rx_fifo_trigger); 3353 } 3354 return ret; 3355 } 3356 } 3357 3358 #ifdef CONFIG_SH_STANDARD_BIOS 3359 sh_bios_gdb_detach(); 3360 #endif 3361 3362 sci_ports_in_use |= BIT(dev_id); 3363 return 0; 3364 } 3365 3366 static __maybe_unused int sci_suspend(struct device *dev) 3367 { 3368 struct sci_port *sport = dev_get_drvdata(dev); 3369 3370 if (sport) 3371 uart_suspend_port(&sci_uart_driver, &sport->port); 3372 3373 return 0; 3374 } 3375 3376 static __maybe_unused int sci_resume(struct device *dev) 3377 { 3378 struct sci_port *sport = dev_get_drvdata(dev); 3379 3380 if (sport) 3381 uart_resume_port(&sci_uart_driver, &sport->port); 3382 3383 return 0; 3384 } 3385 3386 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3387 3388 static struct platform_driver sci_driver = { 3389 .probe = sci_probe, 3390 .remove = sci_remove, 3391 .driver = { 3392 .name = "sh-sci", 3393 .pm = &sci_dev_pm_ops, 3394 .of_match_table = of_match_ptr(of_sci_match), 3395 }, 3396 }; 3397 3398 static int __init sci_init(void) 3399 { 3400 pr_info("%s\n", banner); 3401 3402 return platform_driver_register(&sci_driver); 3403 } 3404 3405 static void __exit sci_exit(void) 3406 { 3407 platform_driver_unregister(&sci_driver); 3408 3409 if (sci_uart_driver.state) 3410 uart_unregister_driver(&sci_uart_driver); 3411 } 3412 3413 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3414 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3415 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3416 #endif 3417 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3418 static struct plat_sci_port port_cfg __initdata; 3419 3420 static int __init early_console_setup(struct earlycon_device *device, 3421 int type) 3422 { 3423 if (!device->port.membase) 3424 return -ENODEV; 3425 3426 device->port.serial_in = sci_serial_in; 3427 device->port.serial_out = sci_serial_out; 3428 device->port.type = type; 3429 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3430 port_cfg.type = type; 3431 sci_ports[0].cfg = &port_cfg; 3432 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3433 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3434 sci_serial_out(&sci_ports[0].port, SCSCR, 3435 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3436 3437 device->con->write = serial_console_write; 3438 return 0; 3439 } 3440 static int __init sci_early_console_setup(struct earlycon_device *device, 3441 const char *opt) 3442 { 3443 return early_console_setup(device, PORT_SCI); 3444 } 3445 static int __init scif_early_console_setup(struct earlycon_device *device, 3446 const char *opt) 3447 { 3448 return early_console_setup(device, PORT_SCIF); 3449 } 3450 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3451 const char *opt) 3452 { 3453 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3454 return early_console_setup(device, PORT_SCIF); 3455 } 3456 3457 static int __init scifa_early_console_setup(struct earlycon_device *device, 3458 const char *opt) 3459 { 3460 return early_console_setup(device, PORT_SCIFA); 3461 } 3462 static int __init scifb_early_console_setup(struct earlycon_device *device, 3463 const char *opt) 3464 { 3465 return early_console_setup(device, PORT_SCIFB); 3466 } 3467 static int __init hscif_early_console_setup(struct earlycon_device *device, 3468 const char *opt) 3469 { 3470 return early_console_setup(device, PORT_HSCIF); 3471 } 3472 3473 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3474 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3475 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3476 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3477 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3478 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3479 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3480 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3481 3482 module_init(sci_init); 3483 module_exit(sci_exit); 3484 3485 MODULE_LICENSE("GPL"); 3486 MODULE_ALIAS("platform:sh-sci"); 3487 MODULE_AUTHOR("Paul Mundt"); 3488 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3489